# IPC Functions
[IPC]

## Functions

CSL_IDEF_INLINE void | CSL_IPC_genNMIEvent (Uint32 index)
CSL_IDEF_INLINE void | CSL_IPC_genGEMInterrupt (Uint32 index, Uint32 srcId)
CSL_IDEF_INLINE Uint32 | CSL_IPC_isGEMInterruptSourceSet (Uint32 index, Uint32 srcId)
CSL_IDEF_INLINE Uint32 | CSL_IPC_isGEMInterruptAckSet (Uint32 index, Uint32 srcId)
CSL_IDEF_INLINE void | CSL_IPC_clearGEMInterruptSource (Uint32 index, Uint32 srcId)
CSL_IDEF_INLINE void | CSL_IPC_genHostInterrupt (Uint32 srcId)
CSL_IDEF_INLINE Uint32 | CSL_IPC_isHostInterruptSourceSet (Uint32 srcId)
CSL_IDEF_INLINE Uint32 | CSL_IPC_isHostInterruptAckSet (Uint32 srcId)
CSL_IDEF_INLINE void | CSL_IPC_clearHostInterruptSource (Uint32 srcId)

## Function Documentation

CSL_IDEF_INLINE void CSL_IPC_clearGEMInterruptSource | ( | Uint32 | index,
|  | Uint32 | srcId |
| ) |  |  |

============================================================================
CSL_IPC_clearGEMInterruptSource

Description
This function clears the interrupt source IDs by setting the SRCCx bit of the IPC Acknowledgment Register (IPCARx) and SRCSx bit of IPC Generation Register (IPCGRx) corresponding to the GEM index and Source ID specified.

Arguments

            index       GEM number for which the interrupt surce is to be cleared.
            srcId       Indicates which of the 0-27 SRCSx/SRCCx bits needs to be cleared
                        in the IPCGRx/IPCARx registers corresponding to the index specified.

Return Value
None

Pre Condition
None

Post Condition
SRCSx/SRCCx bits in the corresponding IPCGRx/IPCARx register are cleared.

Writes
IPC_IPCAR_SRCC0=0; IPC_IPCAR_SRCC1=0; IPC_IPCAR_SRCC2=0; IPC_IPCAR_SRCC3=0; IPC_IPCAR_SRCC4=0; IPC_IPCAR_SRCC5=0; IPC_IPCAR_SRCC6=0; IPC_IPCAR_SRCC7=0; IPC_IPCAR_SRCC8=0; IPC_IPCAR_SRCC9=0; IPC_IPCAR_SRCC10=0; IPC_IPCAR_SRCC11=0; IPC_IPCAR_SRCC12=0; IPC_IPCAR_SRCC13=0; IPC_IPCAR_SRCC14=0; IPC_IPCAR_SRCC15=0; IPC_IPCAR_SRCC16=0; IPC_IPCAR_SRCC17=0; IPC_IPCAR_SRCC18=0; IPC_IPCAR_SRCC19=0; IPC_IPCAR_SRCC20=0; IPC_IPCAR_SRCC21=0; IPC_IPCAR_SRCC22=0; IPC_IPCAR_SRCC23=0; IPC_IPCAR_SRCC24=0; IPC_IPCAR_SRCC25=0; IPC_IPCAR_SRCC26=0; IPC_IPCAR_SRCC27=0

Affects
IPC_IPCGR_SRCS0=0, IPC_IPCGR_SRCS1=0; IPC_IPCGR_SRCS2=0; IPC_IPCGR_SRCS3=0; IPC_IPCGR_SRCS4=0; IPC_IPCGR_SRCS5=0; IPC_IPCGR_SRCS6=0; IPC_IPCGR_SRCS7=0; IPC_IPCGR_SRCS8=0; IPC_IPCGR_SRCS9=0; IPC_IPCGR_SRCS10=0; IPC_IPCGR_SRCS11=0; IPC_IPCGR_SRCS12=0; IPC_IPCGR_SRCS13=0; IPC_IPCGR_SRCS14=0; IPC_IPCGR_SRCS15=0; IPC_IPCGR_SRCS16=0; IPC_IPCGR_SRCS17=0; IPC_IPCGR_SRCS18=0; IPC_IPCGR_SRCS19=0; IPC_IPCGR_SRCS20=0; IPC_IPCGR_SRCS21=0; IPC_IPCGR_SRCS22=0; IPC_IPCGR_SRCS23=0; IPC_IPCGR_SRCS24=0; IPC_IPCGR_SRCS25=0; IPC_IPCGR_SRCS26=0; IPC_IPCGR_SRCS27=0

Example

            Example 1: Clear the interrupt for Gem 1 raised by Gem 2.
            Uint32 	index = 1;
            Uint32	srcId = 2;

            CSL_IPC_clearGEMInterruptSource (index, srcId);

=============================================================================

CSL_IDEF_INLINE void CSL_IPC_clearHostInterruptSource | ( | Uint32 | srcId | ) |

============================================================================
CSL_IPC_clearHostInterruptSource

Description
This function clears the interrupt source IDs by setting the SRCCx bit of the Host IPC Acknowledgment Register (IPCARH) and SRCSx bit of Host IPC Generation Register (IPCGRH) corresponding to the Source ID specified.

Arguments

            srcId       Indicates which of the 0-27 SRCSx/SRCCx bits needs to be cleared
                        in the IPCGRH/IPCARH registers.

Return Value
None

Pre Condition
None

Post Condition
SRCSx/SRCCx bits in the corresponding IPCGRH/IPCARH register are cleared.

Writes
IPC_IPCARH_SRCC0=0; IPC_IPCARH_SRCC1=0; IPC_IPCARH_SRCC2=0; IPC_IPCARH_SRCC3=0; IPC_IPCARH_SRCC4=0; IPC_IPCARH_SRCC5=0; IPC_IPCARH_SRCC6=0; IPC_IPCARH_SRCC7=0; IPC_IPCARH_SRCC8=0; IPC_IPCARH_SRCC9=0; IPC_IPCARH_SRCC10=0; IPC_IPCARH_SRCC11=0; IPC_IPCARH_SRCC12=0; IPC_IPCARH_SRCC13=0; IPC_IPCARH_SRCC14=0; IPC_IPCARH_SRCC15=0; IPC_IPCARH_SRCC16=0; IPC_IPCARH_SRCC17=0; IPC_IPCARH_SRCC18=0; IPC_IPCARH_SRCC19=0; IPC_IPCARH_SRCC20=0; IPC_IPCARH_SRCC21=0; IPC_IPCARH_SRCC22=0; IPC_IPCARH_SRCC23=0; IPC_IPCARH_SRCC24=0; IPC_IPCARH_SRCC25=0; IPC_IPCARH_SRCC26=0; IPC_IPCARH_SRCC27=0

Affects
IPC_IPCGRH_SRCS0=0; IPC_IPCGRH_SRCS1=0; IPC_IPCGRH_SRCS2=0; IPC_IPCGRH_SRCS3=0; IPC_IPCGRH_SRCS4=0; IPC_IPCGRH_SRCS5=0; IPC_IPCGRH_SRCS6=0; IPC_IPCGRH_SRCS7=0; IPC_IPCGRH_SRCS8=0; IPC_IPCGRH_SRCS9=0; IPC_IPCGRH_SRCS10=0; IPC_IPCGRH_SRCS11=0; IPC_IPCGRH_SRCS12=0; IPC_IPCGRH_SRCS13=0; IPC_IPCGRH_SRCS14=0; IPC_IPCGRH_SRCS15=0; IPC_IPCGRH_SRCS16=0; IPC_IPCGRH_SRCS17=0; IPC_IPCGRH_SRCS18=0; IPC_IPCGRH_SRCS19=0; IPC_IPCGRH_SRCS20=0; IPC_IPCGRH_SRCS21=0; IPC_IPCGRH_SRCS22=0; IPC_IPCGRH_SRCS23=0; IPC_IPCGRH_SRCS24=0; IPC_IPCGRH_SRCS25=0; IPC_IPCGRH_SRCS26=0; IPC_IPCGRH_SRCS27=0;

Example

            Example 1: Clear the host interrupt raised by Gem 2.
            Uint32	srcId = 2;

            CSL_IPC_clearHostInterruptSource (srcId);

=============================================================================

CSL_IDEF_INLINE void CSL_IPC_genGEMInterrupt | ( | Uint32 | index,
|  | Uint32 | srcId |
| ) |  |  |

============================================================================
CSL_IPC_genGEMInterrupt

Description
This function sets the IPCG bit of the IPC Generation Register (IPCGRx) to create an inter-DSP pulse to the GEM corresponding to the index specified here. This API also configures the source ID for this interrupt by setting the SRCSx bit of the IPCGRx register based on the source ID specified.

Arguments

            index       GEM number for which the interrupt is to be raised.
            srcId       Indicates which of the 0-27 SRCSx bits needs to be set
                        in the IPCGRx registers corresponding to the index specified.

Return Value
None

Pre Condition
None

Post Condition
IPCG and SRCSx/SRCCx bits in the corresponding IPCGRx/IPCARx register configured.

Writes
IPC_IPCGR_IPCG=1, IPC_IPCGR_SRCS0=1; IPC_IPCGR_SRCS1=1; IPC_IPCGR_SRCS2=1; IPC_IPCGR_SRCS3=1; IPC_IPCGR_SRCS4=1; IPC_IPCGR_SRCS5=1; IPC_IPCGR_SRCS6=1; IPC_IPCGR_SRCS7=1; IPC_IPCGR_SRCS8=1; IPC_IPCGR_SRCS9=1; IPC_IPCGR_SRCS10=1; IPC_IPCGR_SRCS11=1; IPC_IPCGR_SRCS12=1; IPC_IPCGR_SRCS13=1; IPC_IPCGR_SRCS14=1; IPC_IPCGR_SRCS15=1; IPC_IPCGR_SRCS16=1; IPC_IPCGR_SRCS17=1; IPC_IPCGR_SRCS18=1; IPC_IPCGR_SRCS19=1; IPC_IPCGR_SRCS20=1; IPC_IPCGR_SRCS21=1; IPC_IPCGR_SRCS22=1; IPC_IPCGR_SRCS23=1; IPC_IPCGR_SRCS24=1; IPC_IPCGR_SRCS25=1; IPC_IPCGR_SRCS26=1; IPC_IPCGR_SRCS27=1;

Affects
IPC_IPCAR_SRCC0=1; IPC_IPCAR_SRCC1=1; IPC_IPCAR_SRCC2=1; IPC_IPCAR_SRCC3=1; IPC_IPCAR_SRCC4=1; IPC_IPCAR_SRCC5=1; IPC_IPCAR_SRCC6=1; IPC_IPCAR_SRCC7=1; IPC_IPCAR_SRCC8=1; IPC_IPCAR_SRCC9=1; IPC_IPCAR_SRCC10=1; IPC_IPCAR_SRCC11=1; IPC_IPCAR_SRCC12=1; IPC_IPCAR_SRCC13=1; IPC_IPCAR_SRCC14=1; IPC_IPCAR_SRCC15=1; IPC_IPCAR_SRCC16=1; IPC_IPCAR_SRCC17=1; IPC_IPCAR_SRCC18=1; IPC_IPCAR_SRCC19=1; IPC_IPCAR_SRCC20=1; IPC_IPCAR_SRCC21=1; IPC_IPCAR_SRCC22=1; IPC_IPCAR_SRCC23=1; IPC_IPCAR_SRCC24=1; IPC_IPCAR_SRCC25=1; IPC_IPCAR_SRCC26=1; IPC_IPCAR_SRCC27=1

Example

            Example 1: An application running on GEM 2 is trying to raise
            an interrupt to Gem 1. The source Id for Gem 2 say is 2.
            Uint32 	index = 1;
            Uint32	srcId = 2;

            CSL_IPC_genGEMInterrupt (index, srcId);

=============================================================================

CSL_IDEF_INLINE void CSL_IPC_genHostInterrupt | ( | Uint32 | srcId | ) |

============================================================================
CSL_IPC_genHostInterrupt

Description
This function sets the IPCG bit of the Host IPC Generation Register (IPCGRH) to create an interrupt pulse on the device pin. This API also configures the source ID for this interrupt by setting the SRCSx bit of the IPCGRHx register based on the source ID specified.

Arguments

            srcId       Indicates which of the 0-27 SRCSx bits needs to be set
                        in the IPCGRH register.

Return Value
None

Pre Condition
None

Post Condition
IPCG and SRCSx/SRCCx bits in the IPCGRH/IPCARH register configured.

Writes
IPC_IPCGRH_IPCG=1, IPC_IPCGRH_SRCS0=1; IPC_IPCGRH_SRCS1=1; IPC_IPCGRH_SRCS2=1; IPC_IPCGRH_SRCS3=1; IPC_IPCGRH_SRCS4=1; IPC_IPCGRH_SRCS5=1; IPC_IPCGRH_SRCS6=1; IPC_IPCGRH_SRCS7=1; IPC_IPCGRH_SRCS8=1; IPC_IPCGRH_SRCS9=1; IPC_IPCGRH_SRCS10=1; IPC_IPCGRH_SRCS11=1; IPC_IPCGRH_SRCS12=1; IPC_IPCGRH_SRCS13=1; IPC_IPCGRH_SRCS14=1; IPC_IPCGRH_SRCS15=1; IPC_IPCGRH_SRCS16=1; IPC_IPCGRH_SRCS17=1; IPC_IPCGRH_SRCS18=1; IPC_IPCGRH_SRCS19=1; IPC_IPCGRH_SRCS20=1; IPC_IPCGRH_SRCS21=1; IPC_IPCGRH_SRCS22=1; IPC_IPCGRH_SRCS23=1; IPC_IPCGRH_SRCS24=1; IPC_IPCGRH_SRCS25=1; IPC_IPCGRH_SRCS26=1; IPC_IPCGRH_SRCS27=1

Affects IPC_IPCARH_SRCC0=1; IPC_IPCARH_SRCC1=1; IPC_IPCARH_SRCC2=1; IPC_IPCARH_SRCC3=1; IPC_IPCARH_SRCC4=1; IPC_IPCARH_SRCC5=1; IPC_IPCARH_SRCC6=1; IPC_IPCARH_SRCC7=1; IPC_IPCARH_SRCC8=1; IPC_IPCARH_SRCC9=1; IPC_IPCARH_SRCC10=1; IPC_IPCARH_SRCC11=1; IPC_IPCARH_SRCC12=1; IPC_IPCARH_SRCC13=1; IPC_IPCARH_SRCC14=1; IPC_IPCARH_SRCC15=1; IPC_IPCARH_SRCC16=1; IPC_IPCARH_SRCC17=1; IPC_IPCARH_SRCC18=1; IPC_IPCARH_SRCC19=1; IPC_IPCARH_SRCC20=1; IPC_IPCARH_SRCC21=1; IPC_IPCARH_SRCC22=1; IPC_IPCARH_SRCC23=1; IPC_IPCARH_SRCC24=1; IPC_IPCARH_SRCC25=1; IPC_IPCARH_SRCC26=1; IPC_IPCARH_SRCC27=1

Example

            Example 1: An application running on GEM 2 is trying to raise
            a host interrupt.
            Uint32	srcId = 2;

            CSL_IPC_genHostInterrupt (srcId);

=============================================================================

CSL_IDEF_INLINE void CSL_IPC_genNMIEvent | ( | Uint32 | index | ) |

============================================================================
CSL_IPC_genNMIEvent

Description
This function sets the NMIG bit of the NMI Generation Register (NMIGRx) to create an NMI pulse to the GEM corresponding to the index specified here.

Arguments

            index       GEM number for which the NMI event is to be raised.

Return Value
None

Pre Condition
None.

Post Condition
NMIG bit in the corresponding NMIGRx register configured.

Writes
IPC_NMIGR_NMIG=1

Example

            Example 1: Raise an NMI interrupt to Gem 2
            Uint32 index = 2;

            CSL_IPC_genNMIEvent (index);

=============================================================================

CSL_IDEF_INLINE Uint32 CSL_IPC_isGEMInterruptAckSet | ( | Uint32 | index,
|  | Uint32 | srcId |
| ) |  |  |

============================================================================
CSL_IPC_isGEMInterruptAckSet

Description
This function checks if the SRCCx bit of the IPCARx register is set. It returns 1 if the SRCCx bit corresponding to the srcId is set in the IPCARx register corresponding to the index specified. Otherwise it returns 0.

Arguments

            index       GEM number for which the IPCARx register needs to be checked.
            srcId       Indicates which of the 0-27 SRCCx bits needs to be read
                        in the IPCARx registers corresponding to the index specified.

Return Value
1 - Indicates that the corresponding SRCCx bit is set and the srcId specified is in fact the source for the IPC Gem interrupt.
0 - Indicates that corresponding SRCCx bit not set and the srcId specified is not the IPC source.

Pre Condition
None

Post Condition
None

Reads
IPC_IPCAR_SRCC0; IPC_IPCAR_SRCC1; IPC_IPCAR_SRCC2; IPC_IPCAR_SRCC3; IPC_IPCAR_SRCC4; IPC_IPCAR_SRCC5; IPC_IPCAR_SRCC6; IPC_IPCAR_SRCC7; IPC_IPCAR_SRCC8; IPC_IPCAR_SRCC9; IPC_IPCAR_SRCC10; IPC_IPCAR_SRCC11; IPC_IPCAR_SRCC12; IPC_IPCAR_SRCC13; IPC_IPCAR_SRCC14; IPC_IPCAR_SRCC15; IPC_IPCAR_SRCC16; IPC_IPCAR_SRCC17; IPC_IPCAR_SRCC18; IPC_IPCAR_SRCC19; IPC_IPCAR_SRCC20; IPC_IPCAR_SRCC21; IPC_IPCAR_SRCC22; IPC_IPCAR_SRCC23; IPC_IPCAR_SRCC24; IPC_IPCAR_SRCC25; IPC_IPCAR_SRCC26; IPC_IPCAR_SRCC27

Example

            Uint32  index = 1;
            Uint32  srcId = 2;
            Uint32  retVal;

            retVal = CSL_IPC_isGEMInterruptAckSet (index, srcId);

=============================================================================

CSL_IDEF_INLINE Uint32 CSL_IPC_isGEMInterruptSourceSet | ( | Uint32 | index,
|  | Uint32 | srcId |
| ) |  |  |

============================================================================
CSL_IPC_isGEMInterruptSourceSet

Description
This function checks if the SRCSx bit of the IPCGRx register is set. It returns 1 if the SRCSx bit corresponding to the srcId is set in the IPCGRx register corresponding to the index specified. Otherwise it returns 0.

Arguments

            index       GEM number for which the IPCGRx register needs to be checked.
            srcId       Indicates which of the 0-27 SRCSx bits needs to be read
                        in the IPCGRx registers corresponding to the index specified.

Return Value
1 - Indicates that the corresponding SRCSx bit is set and the srcId specified is in fact the source for the IPC Gem interrupt.
0 - Indicates that corresponding SRCSx bit not set and the srcId specified is not the IPC source.

Pre Condition
None

Post Condition
None

Reads
IPC_IPCGR_SRCS0; IPC_IPCGR_SRCS1; IPC_IPCGR_SRCS2; IPC_IPCGR_SRCS3; IPC_IPCGR_SRCS4; IPC_IPCGR_SRCS5; IPC_IPCGR_SRCS6; IPC_IPCGR_SRCS7; IPC_IPCGR_SRCS8; IPC_IPCGR_SRCS9; IPC_IPCGR_SRCS10; IPC_IPCGR_SRCS11; IPC_IPCGR_SRCS12; IPC_IPCGR_SRCS13; IPC_IPCGR_SRCS14; IPC_IPCGR_SRCS15; IPC_IPCGR_SRCS16; IPC_IPCGR_SRCS17; IPC_IPCGR_SRCS18; IPC_IPCGR_SRCS19; IPC_IPCGR_SRCS20; IPC_IPCGR_SRCS21; IPC_IPCGR_SRCS22; IPC_IPCGR_SRCS23; IPC_IPCGR_SRCS24; IPC_IPCGR_SRCS25; IPC_IPCGR_SRCS26; IPC_IPCGR_SRCS27

Example

            Example 1: An application running on Gem 1 received an interrupt and
            wants to check if the interrupt was from the core it was waiting on,
            i.e., the Gem 2.

            Uint32 	index = 1;
            Uint32	srcId = 2;
            Uint32	retVal;

            retVal = CSL_IPC_isGEMInterruptSourceSet (index, srcId);

            if (retVal == 0)
            {
            	...		// Maybe cotinue waiting for the IPC/message
           	}
           	else
           	{
           		...		// Do the needful processing.
           	}

=============================================================================

CSL_IDEF_INLINE Uint32 CSL_IPC_isHostInterruptAckSet | ( | Uint32 | srcId | ) |

============================================================================
CSL_IPC_isHostInterruptAckSet

Description
This function checks if the SRCCx bit of the IPCARH register is set. It returns 1 if the SRCCx bit corresponding to the srcId is set in the IPCARH register. Otherwise it returns 0.

Arguments

            srcId       Indicates which of the 0-27 SRCCx bits needs to be read
                        in the IPCARH register.

Return Value
1 - Indicates that the corresponding SRCCx bit is set and the srcId specified is in fact the source for the IPC Host interrupt.
0 - Indicates that corresponding SRCCx bit not set and the srcId specified is not the IPC source.

Pre Condition
None

Post Condition
None

Reads
IPC_IPCARH_SRCC0; IPC_IPCARH_SRCC1; IPC_IPCARH_SRCC2; IPC_IPCARH_SRCC3; IPC_IPCARH_SRCC4; IPC_IPCARH_SRCC5; IPC_IPCARH_SRCC6; IPC_IPCARH_SRCC7; IPC_IPCARH_SRCC8; IPC_IPCARH_SRCC9; IPC_IPCARH_SRCC10; IPC_IPCARH_SRCC11; IPC_IPCARH_SRCC12; IPC_IPCARH_SRCC13; IPC_IPCARH_SRCC14; IPC_IPCARH_SRCC15; IPC_IPCARH_SRCC16; IPC_IPCARH_SRCC17; IPC_IPCARH_SRCC18; IPC_IPCARH_SRCC19; IPC_IPCARH_SRCC20; IPC_IPCARH_SRCC21; IPC_IPCARH_SRCC22; IPC_IPCARH_SRCC23; IPC_IPCARH_SRCC24; IPC_IPCARH_SRCC25; IPC_IPCARH_SRCC26; IPC_IPCARH_SRCC27

Example

            Uint32  srcId = 2;
            Uint32  retVal;

            retVal = CSL_IPC_isHostInterruptAckSet (srcId);

=============================================================================

CSL_IDEF_INLINE Uint32 CSL_IPC_isHostInterruptSourceSet | ( | Uint32 | srcId | ) |

============================================================================
CSL_IPC_isHostInterruptSourceSet

Description
This function checks if the SRCSx bit of the IPCGRH register is set. It returns 1 if the SRCSx bit corresponding to the srcId is set in the IPCGRH register. Otherwise it returns 0.

Arguments

            srcId       Indicates which of the 0-27 SRCSx bits needs to be read
                        in the IPCGRH register.

Return Value
1 - Indicates that the corresponding SRCSx bit is set and the srcId specified is in fact the source for the IPC Host interrupt.
0 - Indicates that corresponding SRCSx bit not set and the srcId specified is not the IPC source.

Pre Condition
None

Post Condition
None

Reads
IPC_IPCGRH_SRCS0; IPC_IPCGRH_SRCS1; IPC_IPCGRH_SRCS2; IPC_IPCGRH_SRCS3; IPC_IPCGRH_SRCS4; IPC_IPCGRH_SRCS5; IPC_IPCGRH_SRCS6; IPC_IPCGRH_SRCS7; IPC_IPCGRH_SRCS8; IPC_IPCGRH_SRCS9; IPC_IPCGRH_SRCS10; IPC_IPCGRH_SRCS11; IPC_IPCGRH_SRCS12; IPC_IPCGRH_SRCS13; IPC_IPCGRH_SRCS14; IPC_IPCGRH_SRCS15; IPC_IPCGRH_SRCS16; IPC_IPCGRH_SRCS17; IPC_IPCGRH_SRCS18; IPC_IPCGRH_SRCS19; IPC_IPCGRH_SRCS20; IPC_IPCGRH_SRCS21; IPC_IPCGRH_SRCS22; IPC_IPCGRH_SRCS23; IPC_IPCGRH_SRCS24; IPC_IPCGRH_SRCS25; IPC_IPCGRH_SRCS26; IPC_IPCGRH_SRCS27

Example

            Example 1: Check if the host interrupt's source was set correctly
            to 2, i.e., the Gem 2 the source of the host interrupt.

            Uint32	srcId = 2;
            Uint32	retVal;

            retVal = CSL_IPC_isHostInterruptSourceSet (srcId);

            if (retVal == 0)
            {
                ...		// Do something.
            }
            else
            {
                ...		// Do the needful processing.
            }

=============================================================================

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