# QMSS Low Level Driver Symbols Defined
[QMSS]

## Data Structures

struct | Qmss_QosSchedStats
| QoS scheduler statistics. More...

## Modules

| QMSS Low Level Driver Enums
| QMSS Low Level Driver Data Structures

## Defines

#define | QMSS_ACC_IDLE 0
#define | QMSS_ACC_SOK 1
#define | QMSS_ACC_INVALID_COMMAND 2
#define | QMSS_ACC_INVALID_CHANNEL 3
#define | QMSS_ACC_CHANNEL_NOT_ACTIVE 4
#define | QMSS_ACC_CHANNEL_ALREADY_ACTIVE 5
#define | QMSS_ACC_INVALID_QUEUE_NUMBER 6
#define | QMSS_LINKING_RAM_OFFSET 0x80000
#define | QMSS_LINKING_RAM_REGION_0_DEFAULT_SIZE 0x3FFF
#define | QMSS_PARAM_NOT_SPECIFIED -1
#define | QMSS_HW_INIT_COMPLETE 0xABCD
#define | QMSS_SOK 0
#define | QMSS_LLD_EBASE (-128)
#define | QMSS_INVALID_PARAM QMSS_LLD_EBASE-1
#define | QMSS_NOT_INITIALIZED QMSS_LLD_EBASE-2
#define | QMSS_QUEUE_OPEN_ERROR QMSS_LLD_EBASE-3
#define | QMSS_MEMREGION_NOT_INITIALIZED QMSS_LLD_EBASE-4
#define | QMSS_MEMREGION_ALREADY_INITIALIZED QMSS_LLD_EBASE-5
#define | QMSS_MEMREGION_INVALID_PARAM QMSS_LLD_EBASE-6
#define | QMSS_MAX_DESCRIPTORS_CONFIGURED QMSS_LLD_EBASE-7
#define | QMSS_MEMREGION_INVALID_INDEX QMSS_LLD_EBASE-8
#define | QMSS_MEMREGION_OVERLAP QMSS_LLD_EBASE-9
#define | QMSS_MEMREGION_ORDERING QMSS_LLD_EBASE-10
#define | QMSS_FIRMWARE_DOWNLOAD_FAILED QMSS_LLD_EBASE-11
#define | QMSS_RESOURCE_INIT_DENIED QMSS_LLD_EBASE-12
#define | QMSS_RESOURCE_USE_DENIED QMSS_LLD_EBASE-13
#define | QMSS_RESOURCE_MEM_REGION_INIT_DENIED QMSS_LLD_EBASE-14
#define | QMSS_RESOURCE_MEM_REGION_USE_DENIED QMSS_LLD_EBASE-15
#define | QMSS_RESOURCE_LINKING_RAM_INIT_DENIED QMSS_LLD_EBASE-16
#define | QMSS_FIRMWARE_REVISION_DIFFERENCE QMSS_LLD_EBASE-17
#define | QMSS_MAX_MEM_REGIONS 20
#define | QMSS_DESC_PTR(desc) ((uint32_t)desc & 0xFFFFFFF0)
#define | QMSS_DESC_SIZE(desc) ((((uint32_t)desc & 0x0000000F) + 1) << 4)
#define | QMSS_QOS_PDSP_NUM 1
#define | QMSS_QOS_MAX_QUE_RR_HIGH_PRI 4
#define | QMSS_QOS_SRIO_MIN_TX_Q 2
#define | QMSS_QOS_SRIO_SHADOW_GARBAGE_Q_OFFSET 0
#define | QMSS_QOS_SRIO_SHADOW_TX_Q_OFFSET 6
#define | QMSS_QOS_SRIO_SHADOW_TX_COMPLETION_Q_OFFSET 11
#define | QMSS_QOS_SRIO_GARBAGE_Q_OFFSET 16
#define | QMSS_QOS_SRIO_TX_COMPLETION_Q_OFFSET 21
#define | QMSS_QCMD_GET_QUEUE_BASE 0x80
#define | QCMD_RETCODE_SUCCESS 1
#define | QMSS_QCMD_INVALID_COMMAND 2
#define | QMSS_QCMD_INVALID_INDEX 3
#define | QMSS_QCMD_INVALID_OPTION 4
#define | QMSS_QCMD_INVALID_MODE 100
#define | QMSS_QCMD_INVALID_RR_HIGH_Q 101
#define | QMSS_QCMD_INVALID_RR_LOW_Q 102
#define | QMSS_QCMD_INVALID_RR_EGRESS_Q 103
#define | QMSS_QCMD_INVALID_SRIO_NUM_Q 104
#define | QMSS_QOS_SCHED_PDSP_NUM 1
#define | QMSS_QOS_SCHED_FULL_MAX_PHYS_PORTS 2
#define | QMSS_QOS_SCHED_LITE_MAX_PHYS_PORTS 10
#define | QMSS_QOS_SCHED_MAX_PHYS_PORTS
#define | QMSS_QOS_SCHED_FULL_MAX_LOG_GROUPS 5
#define | QMSS_QOS_SCHED_LITE_MAX_LOG_GROUPS 1
#define | QMSS_QOS_SCHED_FULL_MAX_QUEUES_PER_GROUP 8
#define | QMSS_QOS_SCHED_LITE_MAX_QUEUES_PER_GROUP 4
#define | QMSS_QOS_SCHED_STATS_FORWARDED_BYTES 1
#define | QMSS_QOS_SCHED_RETCODE_SUCCESS 1
#define | QMSS_QOS_SCHED_INVALID_COMMAND 2
#define | QMSS_QOS_SCHED_INVALID_INDEX 3
#define | QMSS_QOS_SCHED_INVALID_OPTION 4
#define | QMSS_QOS_SCHED_INVALID_PORT 100
#define | QMSS_QOS_SCHED_INVALID_GROUP 101
#define | QMSS_QOS_SCHED_INVALID_QUEUE 102
#define | QMSS_QOS_SCHED_INVALID_WRRTYPE 103
#define | QMSS_QOS_SCHED_INVALID_CIRTYPE 104
#define | QMSS_QOS_SCHED_INVALID_CONGTYPE 105
#define | QMSS_QOS_SCHED_INVALID_PORT_STATE 106
#define | QMSS_QOS_SCHED_INVALID_GROUP_STATE 107
#define | QMSS_QOS_SCHED_INVALID_CIR_MAX 108
#define | QMSS_QOS_SCHED_INVALID_PIR_MAX 109
#define | QMSS_QOS_SCHED_PACKETS_SCALE_SHIFT 20
#define | QMSS_QOS_SCHED_BYTES_SCALE_SHIFT 11

## Define Documentation

#define QCMD_RETCODE_SUCCESS 1

QMSS QoS return and Error Codes QMSS QoS successful return code

#define QMSS_ACC_CHANNEL_ALREADY_ACTIVE 5

QMSS accumulator channel already active

#define QMSS_ACC_CHANNEL_NOT_ACTIVE 4

QMSS accumulator channel not active return code

#define QMSS_ACC_IDLE 0

QMSS accumulator return and Error Codes QMSS accumulator idle return code

#define QMSS_ACC_INVALID_CHANNEL 3

QMSS accumulator invalid channel return code

#define QMSS_ACC_INVALID_COMMAND 2

QMSS accumulator invalid command return code

#define QMSS_ACC_INVALID_QUEUE_NUMBER 6

QMSS accumulator invalid queue number

#define QMSS_ACC_SOK 1

QMSS accumulator successful return code

#define QMSS_DESC_PTR | ( | desc |  | ) | ((uint32_t)desc & 0xFFFFFFF0)

Macro to get the descriptor pointer if the popped descriptor contains the descriptor size. If Qmss_queuePushDescSize() API is used to push a descriptor onto a queue, the descriptor when popped will have the descriptor size information in the lower 4 bits. This macro is provided to clear out the size information

#define QMSS_DESC_SIZE | ( | desc |  | ) | ((((uint32_t)desc & 0x0000000F) + 1) << 4)

Macro to get the descriptor size if the popped descriptor contains the descriptor size. If Qmss_queuePushDescSize() API is used to push a descriptor onto a queue, the descriptor when popped will have the descriptor size information in the lower 4 bits. This macro is provided to obtain the size information. Minimum size is 16 bytes. Maximum size is 256 bytes

#define QMSS_FIRMWARE_DOWNLOAD_FAILED QMSS_LLD_EBASE-11

QMSS PDSP firmware download failure

#define QMSS_FIRMWARE_REVISION_DIFFERENCE QMSS_LLD_EBASE-17

QMSS firmware revision difference

#define QMSS_HW_INIT_COMPLETE 0xABCD

Used to indicate that QMSS HW Initialization is complete

#define QMSS_INVALID_PARAM QMSS_LLD_EBASE-1

QMSS LLD invalid parameter

#define QMSS_LINKING_RAM_OFFSET 0x80000

Internal Linking RAM offset

#define QMSS_LINKING_RAM_REGION_0_DEFAULT_SIZE 0x3FFF

Internal Linking RAM default size

#define QMSS_LLD_EBASE (-128)

QMSS Error Base

#define QMSS_MAX_DESCRIPTORS_CONFIGURED QMSS_LLD_EBASE-7

QMSS maximum number of allowed descriptor are already configured

#define QMSS_MAX_MEM_REGIONS 20

QMSS maximum number of memory regions

#define QMSS_MEMREGION_ALREADY_INITIALIZED QMSS_LLD_EBASE-5

QMSS memory region already initialized

#define QMSS_MEMREGION_INVALID_INDEX QMSS_LLD_EBASE-8

QMSS Specified memory region index is invalid or no memory regions are available

#define QMSS_MEMREGION_INVALID_PARAM QMSS_LLD_EBASE-6

QMSS memory region invalid parameter

#define QMSS_MEMREGION_NOT_INITIALIZED QMSS_LLD_EBASE-4

QMSS memory region not initialized

#define QMSS_MEMREGION_ORDERING QMSS_LLD_EBASE-10

QMSS memory region not in acscending order

#define QMSS_MEMREGION_OVERLAP QMSS_LLD_EBASE-9

QMSS memory region overlap

#define QMSS_NOT_INITIALIZED QMSS_LLD_EBASE-2

QMSS LLD not initialized

#define QMSS_PARAM_NOT_SPECIFIED -1

Used as input parameter when queue number is not known and not specified

#define QMSS_QCMD_GET_QUEUE_BASE 0x80

QMSS QoS commands

#define QMSS_QCMD_INVALID_COMMAND 2

QMSS QoS invalid command return code

#define QMSS_QCMD_INVALID_INDEX 3

QMSS QoS invalid index return code

#define QMSS_QCMD_INVALID_MODE 100

QMSS QoS invalid cluster mode

#define QMSS_QCMD_INVALID_OPTION 4

QMSS QoS invalid option return code

#define QMSS_QCMD_INVALID_RR_EGRESS_Q 103

QMSS QoS invalid round robin low priority q num

#define QMSS_QCMD_INVALID_RR_HIGH_Q 101

QMSS QoS invalid round robin high priority q num

#define QMSS_QCMD_INVALID_RR_LOW_Q 102

QMSS QoS invalid round robin low priority q num

#define QMSS_QCMD_INVALID_SRIO_NUM_Q 104

QMSS QoS SRIO invalid number of queues

#define QMSS_QOS_MAX_QUE_RR_HIGH_PRI 4

Specifications for Round Robin cluster

#define QMSS_QOS_PDSP_NUM 1

QMSS QoS PDSP number. QoS PDSP is downloaded to PDSP 1

#define QMSS_QOS_SCHED_BYTES_SCALE_SHIFT 11

Shift to convert from bytes to the format used for credits. This is used when the type is Qmss_QosSchedAcctType_BYTES 8 means that each unit represents 1/2048 of a byte

#define QMSS_QOS_SCHED_FULL_MAX_LOG_GROUPS 5

Number of logical groups in full featured port

#define QMSS_QOS_SCHED_FULL_MAX_PHYS_PORTS 2

Number of full featured physical ports

#define QMSS_QOS_SCHED_FULL_MAX_QUEUES_PER_GROUP 8

Number of queues per group in full featured port

#define QMSS_QOS_SCHED_INVALID_CIR_MAX 108

QMSS QoS scheduler cirMax too big (adding credit would overflow)

#define QMSS_QOS_SCHED_INVALID_CIRTYPE 104

QMSS QoS scheduler invalid port config cirType

#define QMSS_QOS_SCHED_INVALID_COMMAND 2

QMSS QoS scheduler invalid command return code

#define QMSS_QOS_SCHED_INVALID_CONGTYPE 105

QMSS QoS scheduler invalid port config congestionType

#define QMSS_QOS_SCHED_INVALID_GROUP 101

QMSS QoS scheduler invalid group in port

#define QMSS_QOS_SCHED_INVALID_GROUP_STATE 107

QMSS QoS scheduler attempted to configure a running group

#define QMSS_QOS_SCHED_INVALID_INDEX 3

QMSS QoS scheduler invalid index return code

#define QMSS_QOS_SCHED_INVALID_OPTION 4

QMSS QoS scheduler invalid option return code

#define QMSS_QOS_SCHED_INVALID_PIR_MAX 109

QMSS QoS scheduler pirMax too big (adding credit would overflow)

#define QMSS_QOS_SCHED_INVALID_PORT 100

QMSS QoS scheduler invalid physical port

#define QMSS_QOS_SCHED_INVALID_PORT_STATE 106

QMSS QoS scheduler attempted to configure a running port

#define QMSS_QOS_SCHED_INVALID_QUEUE 102

QMSS QoS scheduler invalid queue in group

#define QMSS_QOS_SCHED_INVALID_WRRTYPE 103

QMSS QoS scheduler invalid port config wrrType

#define QMSS_QOS_SCHED_LITE_MAX_LOG_GROUPS 1

Number of logical groups in reduced feature port

#define QMSS_QOS_SCHED_LITE_MAX_PHYS_PORTS 10

Number of reduced feature physical ports

#define QMSS_QOS_SCHED_LITE_MAX_QUEUES_PER_GROUP 4

Number of queues per group in reduced feature port

#define QMSS_QOS_SCHED_MAX_PHYS_PORTS

Value:

    (QMSS_QOS_SCHED_FULL_MAX_PHYS_PORTS +\
                                           QMSS_QOS_SCHED_LITE_MAX_PHYS_PORTS)

Total number of physical ports

#define QMSS_QOS_SCHED_PACKETS_SCALE_SHIFT 20

Shift to convert from packets to the format used for credits. This is used when the type is Qmss_QosSchedAcctType_PACKETS. 20 means that each unit represents 1/1048576 of a packet

#define QMSS_QOS_SCHED_PDSP_NUM 1

QMSS QoS PDSP number. QoS PDSP is downloaded to PDSP 1

#define QMSS_QOS_SCHED_RETCODE_SUCCESS 1

QMSS QoS scheduler return and Error Codes QMSS QoS scheduler successful return code

#define QMSS_QOS_SCHED_STATS_FORWARDED_BYTES 1

Bits representing statistics types

#define QMSS_QOS_SRIO_GARBAGE_Q_OFFSET 16

Offset relative to Qmss_QosSrioCfg::queBase for first Garbage Collection Completion Queue.

The firmware will move descriptors from the Shadow Garbage Collection Queues to the Garbage Collection Completion Queues

#define QMSS_QOS_SRIO_MIN_TX_Q 2

Specifications for the SRIO monitor cluster

#define QMSS_QOS_SRIO_SHADOW_GARBAGE_Q_OFFSET 0

Offset relative to Qmss_QosSrioCfg::queBase for first Shadow Garbage Collection Queue.

#define QMSS_QOS_SRIO_SHADOW_TX_COMPLETION_Q_OFFSET 11

Offset relative to Qmss_QosSrioCfg::queBase for first Shadow Transmit Completion Queue.

SRIO's return queues should be pointed here.

#define QMSS_QOS_SRIO_SHADOW_TX_Q_OFFSET 6

Offset relative to Qmss_QosSrioCfg::queBase for first Shadow Transmit Queue.

SW places descriptors for SRIO transactions here

#define QMSS_QOS_SRIO_TX_COMPLETION_Q_OFFSET 21

Offset relative to Qmss_QosSrioCfg::queBase for first Transmit Completion Queue.

The firmware will move descriptors from the Shadow Transmit Completion Queue to the Transmit Completion queue after subtracting the pending descriptor the number of pending descriptors on the hardware tx queue.

#define QMSS_QUEUE_OPEN_ERROR QMSS_LLD_EBASE-3

QMSS LLD queue open error

#define QMSS_RESOURCE_INIT_DENIED QMSS_LLD_EBASE-12

QMSS resource initialization permission denied

#define QMSS_RESOURCE_LINKING_RAM_INIT_DENIED QMSS_LLD_EBASE-16

QMSS general linking RAM initialization permission denied

#define QMSS_RESOURCE_MEM_REGION_INIT_DENIED QMSS_LLD_EBASE-14

QMSS memory region initialization permission denied

#define QMSS_RESOURCE_MEM_REGION_USE_DENIED QMSS_LLD_EBASE-15

QMSS memory region usage permission denied

#define QMSS_RESOURCE_USE_DENIED QMSS_LLD_EBASE-13

QMSS resource usage permission denied

#define QMSS_SOK 0

QMSS Low level Driver return and Error Codes QMSS successful return code

Copyright 2012, Texas Instruments Incorporated