# pcieAckFreqReg_s Struct Reference
[PCIE LLD Port Logic Register Definitions]

Specification of the Ack Frequency register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
uint8_t | aspmL1
| [rw] Allow ASPM L1 without partner going to L0s.
uint8_t | l1EntryLatency
| [rw] L1 entrance latency.
uint8_t | l0sEntryLatency
| [rw] L0s entrance latency.
uint8_t | commNFts
| [rw] Number of fast training sequences for common clock
uint8_t | nFts
| [rw] Number of fast training sequences to be transmitted
uint8_t | ackFreq
| [rw] Ack Frequency.

## Detailed Description

Specification of the Ack Frequency register.

This register may be used for both endpoint and root complex modes.

## Field Documentation

uint8_t pcieAckFreqReg_s::ackFreq

[rw] Ack Frequency.

Default is to wait until 255 Ack DLLPs are pending before it is sent.

Field size: 8 bits

uint8_t pcieAckFreqReg_s::aspmL1

[rw] Allow ASPM L1 without partner going to L0s.

Set to allow entering ASPM L1 even when link partner did not go to L0s. When cleared, the ASPM L1 state is entered only after idle period during which both RX and TX are in L0s.

Field size: 1 bit

uint8_t pcieAckFreqReg_s::commNFts

[rw] Number of fast training sequences for common clock

Number of fast training sequences when common clock is used and when transitioning from L0s to L0.

Field size: 8 bits

uint8_t pcieAckFreqReg_s::l0sEntryLatency

[rw] L0s entrance latency.

The latency is set to l0sEntryLatency + 1 microseconds. Maximum is 7 microseconds.

l0sEntryLatency | latency in µs
--- | ---
0 | 1µs
1 | 2µs
2 | 3µs
3 | 4µs
4 | 5µs
5 | 6µs
6 | 7µs
7 | 7µs

Field size: 3 bits

uint8_t pcieAckFreqReg_s::l1EntryLatency

[rw] L1 entrance latency.

The latency is set to 2^l1EntryLatency microseconds with the max being 64 microseconds.

l1EntryLatency | latency in µs
--- | ---
0 | 1µs
1 | 2µs
2 | 4µs
3 | 8µs
4 | 16µs
5 | 32µs
6 | 64µs
7 | 64µs

Field size: 3 bits

uint8_t pcieAckFreqReg_s::nFts

[rw] Number of fast training sequences to be transmitted

Number of fast training sequences to be transmitted when transitioning from L0s to L0. Value of 0 is not supported.

Field size: 8 bits

uint32_t pcieAckFreqReg_s::raw

[ro] Raw image of register on read; actual value on write

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated