# pcieBarReg_s Struct Reference
[PCIE LLD Type0 (endpoint) Register Definitions]

Specification of the Base Address Register (BAR). More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint32_t | base
| [rw] Base Address
uint8_t | prefetch
| [rw] Prefetchable region?
uint8_t | type
| [rw] Bar Type
uint8_t | memSpace
| [rw] Memory or IO BAR

## Detailed Description

Specification of the Base Address Register (BAR).

This should be used to access a BAR register.

There are two situations when this structure should be used:
1. When setting up a 32 bit BAR
2. When setting up the lower 32bits of a 64bits BAR

Refer to pcieBar32bitReg_t for the other possible BAR configurations

## Field Documentation

uint32_t pcieBarReg_s::base

[rw] Base Address

Field size: 28 bits

uint8_t pcieBarReg_s::memSpace

[rw] Memory or IO BAR

0 = Memory BAR.
1 = I/O BAR.

Field size: 1 bit

uint8_t pcieBarReg_s::prefetch

[rw] Prefetchable region?

For memory BARs, it indicates whether the region is prefetchable.
0 = Non-prefetchable.
1 = Prefetchable.

For I/O Bars, it is used as second least significant bit (LSB) of the base address.

Field size: 1 bit

uint8_t pcieBarReg_s::type

[rw] Bar Type

For memory BARs, they determine the BAR type.
0h = 32-bit BAR.
2h = 64-bit BAR.
Others = Reserved.

For I/O BARs, bit 2 is the least significant bit (LSB) of the base address and bit 1 is 0.

Field size: 2 bits

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated