# pcieType1SecStatReg_s Struct Reference
[PCIE LLD Type1 (root) Register Definitions]

Specification of the Secondary Status and IO Base/Limit Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint8_t | dtctPError
| [rw] Detected Parity Error.
uint8_t | rxSysError
| [rw] Received System Error.
uint8_t | rxMstAbort
| [rw] Received Master Abort.
uint8_t | rxTgtAbort
| [rw] Received Target Abort.
uint8_t | txTgtAbort
| [rw] Signaled Target Abort.
uint8_t | mstDPErr
| [rw] Master Data Parity Error.
uint8_t | IOLimit
| [rw] Upper 4 bits of 16bit IO Space Limit Address.
uint8_t | IOLimitAddr
| [rw] Indicates addressing for IO Limit Address.
uint8_t | IOBase
| [rw] Upper 4 bits of 16bit IO Space Base Address.
uint8_t | IOBaseAddr
| [rw] Indicates addressing for the IO Base Address.

## Detailed Description

Specification of the Secondary Status and IO Base/Limit Register.

## Field Documentation

uint8_t pcieType1SecStatReg_s::dtctPError

[rw] Detected Parity Error.

Read 1 if received a poisoned TLP. Write 1 to clear; write 0 has no effect.

Field size: 1 bits

uint8_t pcieType1SecStatReg_s::IOBase

[rw] Upper 4 bits of 16bit IO Space Base Address.

Field size: 4 bits

uint8_t pcieType1SecStatReg_s::IOBaseAddr

[rw] Indicates addressing for the IO Base Address.

Writable from internal bus interface. 0 = 16-bit IO addressing. 1 = 32-bit IO addressing.

Field size: 1 bits

uint8_t pcieType1SecStatReg_s::IOLimit

[rw] Upper 4 bits of 16bit IO Space Limit Address.

Field size: 4 bits

uint8_t pcieType1SecStatReg_s::IOLimitAddr

[rw] Indicates addressing for IO Limit Address.

Writable from internal bus interface. 0 = 16-bit IO addressing. 1 = 32-bit IO addressing.

Field size: 1 bits

uint8_t pcieType1SecStatReg_s::mstDPErr

[rw] Master Data Parity Error.

Read 1 if the parity error enable bit pcieType1BridgeIntReg_s::pErrRespEn is set and either the condition that the requester receives a poisoned completion or the condition that the requester poisons a write request is true. Write 1 to clear; write 0 has no effect.

Field size: 1 bits

uint8_t pcieType1SecStatReg_s::rxMstAbort

[rw] Received Master Abort.

Read 1 if received a completion with unsupported request completion status. Write 1 to clear; write 0 has no effect.

Field size: 1 bits

uint8_t pcieType1SecStatReg_s::rxSysError

[rw] Received System Error.

Read 1 if received an ERR_FATAL or ERR_NONFATAL message. Write 1 to clear; write 0 has no effect.

Field size: 1 bits

uint8_t pcieType1SecStatReg_s::rxTgtAbort

[rw] Received Target Abort.

Read 1 if received a completion with completer abort completion status. Write 1 to clear; write 0 has no effect.

Field size: 1 bits

uint8_t pcieType1SecStatReg_s::txTgtAbort

[rw] Signaled Target Abort.

Read 1 if sent a posted or non-posted request as a completer abort error. Write 1 to clear; write 0 has no effect.

Field size: 1 bits

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated