/*                                                                          */
/* Function    : define exceptions codes useful by few applications         */
/*                                                                          */
/*                                                                          */
/*                                                                          */

#include  "mbdr_dsp_common_type_def.h"
#include  "windef.h"

#ifndef _MBDR_DSP_COMMON_DESCRIPTORS_H
#define _MBDR_DSP_COMMON_DESCRIPTORS_H


typedef struct _mbdr_dsp_common_sw_module_code_t
{
  UCHAR main;          /* main   module code that DSP is occupied with*/
  UCHAR middle;        /* middle   "     "    "    "  "     "      "  */
  UCHAR sub_module;    /* sub      "     "    "    "  "     "      "  */
  UCHAR state_machine; /* state machine code of current SW module     */
}mbdr_dsp_common_sw_module_code_t;

/**********************************************/
/* exception descriptor                       */
/**********************************************/
enum MBDR_DSP_EXCEPTION_SEVERITY_T{

   /* system accessed closed to limit, but no further treatment is needed    */
   MBDR_DSP_EXCEPTION_SEVERITY_T_WARNING,

   /* error that does not demand restart happened, but these error may cause */
   /* to signals loss                                                        */
   MBDR_DSP_EXCEPTION_SEVERITY_T_SIGNAL_LOSS,

   /* error that demands system restart happened */
   MBDR_DSP_EXCEPTION_SEVERITY_T_FATAL,

   /* error that does not demand restart happened, but these error may cause */
   /* to signals loss                                                        */
   MBDR_DSP_EXCEPTION_SEVERITY_T_MISSION_LOSS};

typedef struct _mbdr_dsp_exception_descriptor_header_t
{                                   /* DW  bits  */
 ULONG_BIT_FIELD header_cyclic_index:8;          /*  0   7..0 */
 ULONG_BIT_FIELD spare_0          :24;        /*  0  31.24 */
 ULONG_BIT_FIELD sequential_number:8;        /*  1   7..0 */
 ULONG_BIT_FIELD exception_code:8;           /*  1  15..8 */
 ULONG_BIT_FIELD mission_number:10;        /*  1  25.16 */
 ULONG_BIT_FIELD severity : 2;             /*  1  27.26 */
 ULONG_BIT_FIELD spare_1_0:4;               /* 1  31.28 */
}mbdr_dsp_exception_descriptor_header_t;

/* up to exception_code size */
#define MBDR_DSP_EXCEPTION_CODES_NUMBER 256;

typedef struct _mbdr_dsp_exception_descriptor_data_t
{                 /* DW  bits   */
 ULONG data_0;    /*  0  31..0  */
 ULONG data_1;    /*  1  30..0  */
}mbdr_dsp_exception_descriptor_data_t;

typedef struct _mbdr_dsp_exception_descriptor_t
{                                              /*  DW   */
 mbdr_dsp_exception_descriptor_header_t header;/* 1-0   */
 mbdr_dsp_exception_descriptor_data_t   data;  /* 3-2   */
}mbdr_dsp_exception_descriptor_t;


typedef struct _mbdr_dsp_exception_descriptor_data_memory_smash_t
{                 /* DW  bits   */
 mbdr_dsp_common_sw_module_code_t sw_module_code;
 ULONG_BIT_FIELD                  address:20;
 ULONG_BIT_FIELD                  application_extra_info  : 4;
 UCHAR                            memory_dw_size;
}mbdr_dsp_exception_descriptor_data_memory_smash_t;

typedef union _mbdr_dsp_exception_descriptor_memory_smash_union_t
{                                              /*  DW   */
 mbdr_dsp_exception_descriptor_data_memory_smash_t field;/* 1-0   */
 mbdr_dsp_exception_descriptor_data_t              overlay;  /* 3-2   */
}mbdr_dsp_exception_descriptor_memory_smash_union_t;
typedef struct _mbdr_dsp_exception_lost_fir_instruction_t
{                                                    /* DW  bits   */
 ULONG_BIT_FIELD   fir_instruction_dw_0_26_lsb   :26;
 ULONG_BIT_FIELD   cyclic_read_index             : 6;
 ULONG             fir_header;
}mbdr_dsp_exception_lost_fir_instruction_t;


typedef struct _mbdr_dsp_exception_descriptor_extra_if_process_input_queue_full_t
{
 UCHAR fifo_size;
 UCHAR fine_fandler_to_if_extra_write_a_occupied_entries;
 UCHAR fine_fandler_to_if_extra_scope_output_b_occupied_entries;
 UCHAR if_extra_write_to_if_extra_scope_outpt_c_occupied_entries;

 ULONG spare;
}mbdr_dsp_exception_descriptor_extra_if_process_input_queue_full_t;


typedef struct _mbdr_dsp_exception_descriptor_data_fir_header_command_mismatch_t
{                                                /* DW  bits   */
 ULONG              instruction_first_dw;        /*  0  31..0  */
 ULONG_BIT_FIELD    reply_header_bits_30_0: 31;  /*  1  30..0  */
 ULONG_BIT_FIELD    dual_antenna_mission_f:  1;  /*  1     31  */
}mbdr_dsp_exception_descriptor_data_fir_header_instruction_mismatch_t;

typedef union _mbdr_dsp_exception_descriptor_data_fir_header_instruction_union_t
{                                              /*  DW   */
 mbdr_dsp_exception_descriptor_data_fir_header_instruction_mismatch_t field;/* 1-0   */
 mbdr_dsp_exception_descriptor_data_t   data;  /* 3-2   */
}mbdr_dsp_exception_descriptor_data_fir_header_instruction_union_t;

typedef struct _mbdr_dsp_exception_descriptor_if_offset_from_start_address_mismatch_field_t
{                                    /* DW  bits   */
  ULONG_BIT_FIELD  former_rcg_IFOffsetFromStartAdr  :20;      /*  0  19..0  */
  ULONG_BIT_FIELD  former_rcg_frame_count_bits_11_0 :12;      /*  0  31.20  */

  ULONG_BIT_FIELD  current_rcg_IFOffsetFromStartAdr :20;      /*  0  19..0  */
  ULONG_BIT_FIELD  former_rcg_frame_count_bits_19_12: 8;      /*  0  27.20  */
  ULONG_BIT_FIELD  spare                            : 4;      /*  1  31.28  */
}mbdr_dsp_exception_descriptor_if_offset_from_start_address_mismatch_field_t;

typedef union _mbdr_dsp_exception_descriptor_former_frame_cnt_and_new_if_offset_mismatch_union_t
{                                                                                  /*  DW   */
 mbdr_dsp_exception_descriptor_if_offset_from_start_address_mismatch_field_t field;/* 1-0   */
 mbdr_dsp_exception_descriptor_data_t   overlay;                                   /* 1-0   */
}mbdr_dsp_exception_descriptor_if_offset_from_start_address_mismatch_union_t;


typedef struct _mbdr_dsp_exception_real_time_clock_synchronization_field_t
{                                                    /* DW  bits   */
 ULONG_BIT_FIELD last_send_echo       : 4;
 ULONG_BIT_FIELD last_received_echo   : 4;
 ULONG_BIT_FIELD spare_0              :16;
 ULONG           spare_1;
}mbdr_dsp_exception_real_time_clock_synchronization_field_t;

typedef union  _mbdr_dsp_exception_real_time_clock_synchronization_union_t
{                                                                   /*  DW   */
 mbdr_dsp_exception_real_time_clock_synchronization_field_t field;  /* 1-0   */
 mbdr_dsp_exception_descriptor_data_t                       overlay;/* 1-0   */
}mbdr_dsp_exception_real_time_clock_synchronization_union_t;


typedef struct _mbdr_dsp_exception_send_get_instruction_overload_field_t
{                                                    /* DW  bits   */
 ULONG_BIT_FIELD last_send_echo       : 4;
 ULONG_BIT_FIELD last_received_echo   : 4;
 ULONG_BIT_FIELD get_index            : 4;
 ULONG_BIT_FIELD spare_0              :20;
 ULONG           spare_1;
}mbdr_dsp_exception_send_get_instruction_overload_field_t;
typedef union  _mbdr_dsp_exception_send_get_instruction_overload_union_t
{                                                                   /*  DW   */
 mbdr_dsp_exception_send_get_instruction_overload_field_t   field;  /* 1-0   */
 mbdr_dsp_exception_descriptor_data_t                       overlay;/* 1-0   */
}mbdr_dsp_exception_send_get_instruction_overload_union_t;



typedef struct
{
 ULONG           hwimage_set_segment_header;		 	/* 0 31..0 */
 ULONG_BIT_FIELD queue_dw_index       :12;       /* 1 11..0 */
 ULONG_BIT_FIELD cyclic_buffer_base_p :20;       /* 1 31.12 base_data_address */
}mbdr_dsp_exception_code_hw_set_segment_illegal_header_field_t;

typedef union
{
  mbdr_dsp_exception_code_hw_set_segment_illegal_header_field_t    field;
  mbdr_dsp_exception_descriptor_data_t          			       overlay;
}mbdr_dsp_exception_code_hw_set_segment_illegal_header_union_t;

/**********************************************/
/* exception descriptor                       */
/**********************************************/
enum MBDR_DSP_EXCEPTION_COMMON_CODE_T{

   /* MBDR FPGA internal buffer overflow, in some projects it excludes  */
   /* monitor case                                                      */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_MBDR_FPGA_INTERNAL_FIFO_FULL_FATAL=1,

   /* MEMORY SMASH, result of application specific location check */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_MEMORY_SMASH,

   /* MBDR FPGA internal monitor messages buffer overflow              */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_MBDR_FPGA_INTERNAL_FIFO_FULL_MONITOR,

   /* local SW version application depend exception, that suits spicific  */
   /* scenarion and SW version                                            */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_TEMPORARY,

   /* FIR&DEC header consists unexpected echo */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_LOST_FIR_INSTRUCTION,

   /* waiting time for get request from HW expired and application unable */
   /* to continue without these information                               */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_GET_TIME_OUT_FATAL,

   /* extra IF process input queue full */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_EXTRA_IF_PROCESS_INPUT_QUEUE_FULL,

   /* FIR header does not fit command parameters */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_FIR_HEADER_INSTRUCTION_MISMATCH,

   /* mismatch between previous RCG frame count and following RCG  */
   /* IFOffsetFromStartAdr difference                              */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_IF_OFFSET_FROM_START_ADDRESS_MISMATCH,

   /* waiting time for get request from HW expired, but application    */
   /* has overcome ability, it does not send fatal exception           */
   /* These message is helpfuk for statistics of lost get instructions */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_GET_TIME_OUT_WARNING,

   /* real time clock synchonization fault  */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_REAL_TIME_CLOCK_SYNCHRONIZATION,

   /* DSP SW requested repeated time to send the same get instruction         */
   /* although overload in echo index, DSP should declare some function fault */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_SEND_GET_INSTRUCTION_OVERLOAD,

   /* CW by HW header consists unexpected echo */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_LOST_CW_INSTRUCTION,

   MBDR_DSP_EXCEPTION_COMMON_CODE_T_MESSAGE_CHECKSUM,

   /* waiting for header middle synchronization time out */
   MBDR_DSP_EXCEPTION_COMMON_CODE_T_WAIT_FOR_HEADER_MIDDLE_SYNCHRONIZATION_TIME_OUT=28,

   /* illegal write to HW set segment module FIFO */
   MBDR_DSP_EXCEPTION_CODE_T_HWIMAGE_SET_SEGMENT_ILLEGAL_HEADER

 };




#endif
