# pciePcsCfg1Reg_s Struct Reference
[PCIE LLD Application Register Definitions]

Specification of the PCS Configuration 1 Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint16_t | pcsErrBit
| [rw] Error bit enable.
uint8_t | pcsErrLn
| [rw] Error lane enable
uint8_t | pcsErrMode
| [rw] Error injection mode

## Detailed Description

Specification of the PCS Configuration 1 Register.

## Field Documentation

uint16_t pciePcsCfg1Reg_s::pcsErrBit

[rw] Error bit enable.

Field size: 10 bits

uint8_t pciePcsCfg1Reg_s::pcsErrLn

[rw] Error lane enable

Field size: 2 bits

uint8_t pciePcsCfg1Reg_s::pcsErrMode

[rw] Error injection mode

Field size: 2 bits

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated