/*                                                                          */
/* Functions   : Initialization utilities                                   */
/*     1) mbdr_dsp_sdc_sync_with_cpu_do_init_0_2 initializes                */
/*          internal memory                                                 */
/*          FPGA->DSP buffers                                               */
/*          CPU<->DSP buffers                                               */
/*          real time clock                                                 */
/* Output:                                                                  */
/*     handshake structures in HW memory or CPU memory                      */
/*     global control variables: cyclic buffers, real time clock etc.       */
/*                                                                          */
/* Content     : 1) mbdr_dsp_sdc_sync_with_cpu - synchronization manage     */
/*                                                                          */
/*                                                                          */
/*                                                                          */
#include  "windef.h"
#include  "mbdr_dsp_common_ti_peripheral_utils.h"
#include  "mbdr_dsp_common_status.h"
#include  "mbdr_dsp_common_boot_loader_app.h"
#include  "mbdr_dsp_utils.h"
#include  "mbdr_dsp_system_utils.h"
#include  "mbdr_dsp_pci_utils_base_tbl.h"
#include  "mbdr_dsp_cyclic_buffer_double_header.h"
#include  "mbdr_dsp_xpci_manage_utils.h"
#include  "mbdr_dsp_sw_version.h"
#include  "mbdr_dsp_platform_proc_ptrs.h"

#include  "mbdr_dsp_sdc_hwimage_int.h"
#include  "mbdr_dsp_sdc_sync_with_cpu.h"
#include  "mbdr_dsp_sdc_pci_utils_base_tbl.h"
#include  "mbdr_dsp_sdc_main_flow_data.h"



void mbdr_dsp_sdc_sync_with_cpu_do_init_0_2(
              mbdr_dsp_common_config_multi_core_t pi_dummy_config_multi_core)
{/* mbdr_dsp_sdc_sync_with_cpu_do_init_0_2 */


  /* avoid warning */
  mbdr_dsp_utils_dummy = pi_dummy_config_multi_core.spare_0;

  /* Initialize internal peripherals */
  //mbdr_dsp_sdc_internal_peripherals_init();


  /* initialize PCI access table */
  mbdr_dsp_sdc_sync_with_cpu_update_fpga_ptrs();

  /* update helpful pointer */
  mbdr_dsp_cpu_common_interface_cpu_image_p
   = mbdr_dsp_boot_loader_config[0].common.mbdr_dsp_cpu_main_interface_p;

  /* table of PCI base address */
  mbdr_dsp_pci_utils_base_tbl
     [MBDR_DSP_SDC_PCI_UTILS_BASE_TBL_T_CPU_DSP_MAIN_INTERFACE] =
                   (LONG)mbdr_dsp_cpu_common_interface_cpu_image_p;


  /* clear internal interface structures */
  memset(&mbdr_dsp_cpu_common_interface_dsp[0],
         0,
         sizeof(mbdr_dsp_cpu_common_interface_t));


  /* update main_interface in relevant data */
  MBDR_DSP_SDC_SET_DW_IN_MAIN_INTERFACE_IN_TWO_IMAGES_M(
             (LONG)&mbdr_dsp_cpu_common_interface_dsp[0],
             main_interface_dsp_bofs);
}/* mbdr_dsp_sdc_sync_with_cpu_do_init_0_2 */

void  mbdr_dsp_sdc_sync_with_cpu_do_init_2_0(
              mbdr_dsp_common_config_multi_core_t pi_dummy_config_multi_core)
{/* mbdr_dsp_sdc_sync_with_cpu_do_init_2_0 */

  mbdr_dsp_utils_dummy = pi_dummy_config_multi_core.spare_0;


}/* mbdr_dsp_sdc_sync_with_cpu_do_init_2_0 */

/* reads and update fpga pointers */
void mbdr_dsp_sdc_sync_with_cpu_update_fpga_ptrs(void)
{/* mbdr_dsp_sdc_sync_with_cpu_update_fpga_ptrs */


}/* mbdr_dsp_sdc_sync_with_cpu_update_fpga_ptrs */

void mbdr_dsp_sdc_internal_peripherals_init(void)
{/* mbdr_dsp_sdc_internal_peripherals_init */

    /* initialize chip support libraryemif A */
	//CSL_init();

    /* initialize emif A */
    mbdr_dsp_application_emif_init();

}/* mbdr_dsp_sdc_internal_peripherals_init */




