# Mcbsp_srgConfig_t Struct Reference

McBSP sample rate generator configuration structure. More...

`#include <mcbsp_drv.h>`

## Data Fields

Bool | gSync
Mcbsp_ClkSPol | clksPolarity
Mcbsp_SrgClk | srgInputClkMode
uint32_t | srgrInputFreq
uint32_t | srgFrmPulseWidth

## Detailed Description

McBSP sample rate generator configuration structure.

Configurations for the Sample rate generator to generate the BCLK and Frame Sync signals are specified using this structure.

## Field Documentation

Mcbsp_ClkSPol Mcbsp_srgConfig_t::clksPolarity

CLKS polarity used to drive the CLKG and FSG clocks

Bool Mcbsp_srgConfig_t::gSync

sample rate generator clock syncronization bit (only if CLKS is used)

uint32_t Mcbsp_srgConfig_t::srgFrmPulseWidth

Set the Frame Sync Pulse width in terms of FSG clock

Mcbsp_SrgClk Mcbsp_srgConfig_t::srgInputClkMode

Source for the Sample rate generator (CLKS,CPU,CLKX,CLKR)

uint32_t Mcbsp_srgConfig_t::srgrInputFreq

input clock frequency for the SRGR (freq of CLKS or CLKX etc..)

The documentation for this struct was generated from the following file:

- mcbsp_drv.h

Copyright 2012, Texas Instruments Incorporated