# pcieType1BistHeaderReg_s Struct Reference
[PCIE LLD Type1 (root) Register Definitions]

Specification of the BIST, Header Type, Latency Time and Cache Line Size Regiser. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint8_t | bistCap
| [ro] Returns a 1 for BIST capability and 0 otherwise.
uint8_t | startBist
| [ro] Write a one to start BIST.
uint8_t | compCode
| [rw] Completion Code.
uint8_t | mulFunDev
| [rw] Returns 1 if it is a multi-function device.
uint8_t | hdrType
| [rw] Configuration Header Format.
uint8_t | latTmr
| [ro] Not applicable in PCIe
uint8_t | cacheLnSize
| [ro] Not applicable in PCIe

## Detailed Description

Specification of the BIST, Header Type, Latency Time and Cache Line Size Regiser.

## Field Documentation

uint8_t pcieType1BistHeaderReg_s::bistCap

[ro] Returns a 1 for BIST capability and 0 otherwise.

Not supported by PCIESS.

Field size: 1 bit

uint8_t pcieType1BistHeaderReg_s::cacheLnSize

[ro] Not applicable in PCIe

Field size: 8 bits

uint8_t pcieType1BistHeaderReg_s::compCode

[rw] Completion Code.

Not supported by PCIESS.

Field size: 4 bits

uint8_t pcieType1BistHeaderReg_s::hdrType

[rw] Configuration Header Format.

0 = EP mode
1 = RC mode

Field size: 7 bits

uint8_t pcieType1BistHeaderReg_s::latTmr

[ro] Not applicable in PCIe

Field size: 8 bits

uint8_t pcieType1BistHeaderReg_s::mulFunDev

[rw] Returns 1 if it is a multi-function device.

Field size: 1 bit

uint8_t pcieType1BistHeaderReg_s::startBist

[ro] Write a one to start BIST.

Not supported by PCIESS.

Field size: 1 bit

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated