# PCIe Low Level Driver

### 1.0.0.3

## Introduction

This document describes the Low Level Driver (LLD) for the Peripheral Component Interconnect Express (PCIe).

The PCI Express module supports dual operation mode: End Point (EP or Type0) or Root Complex (RC or Type1). This driver focuses on EP mode but it also provides access to some basic RC configuration/functionalities.

The PCIe userguide can be found at <http://www.ti.com/lit/sprugs6a>.

The PCIe subsystem has two address spaces. The first (Address Space 0) is dedicated for local application registers, local configuration accesses and remote configuration accesses. The second (Address Space 1) is dedicated for data transfer.

The PCIe driver focuses on the registers for Address Space 0.

Throughout the LLD, the registers/APIs are grouped into the following:

1. PCIe Application Registers/APIs
2. PCIe Configuration Registers/APIs (Local and Remote)
   2.1 Type0 and Type1 Common Registers/APIs
   2.2 Type0 Registers/APIs
   2.3 Type1 Registers/APIs
   2.4 MSI Registers/APIs
   2.5 Capabylity Registers/APIs
   2.6 Extended Capability Registers/APIs
   2.7 Port Logic Registers/APIs

The normal sequence of events to enable the peripheral is listed below.
There is a C code example in ti/drv/pcie/example/sample.

1. Set up the SERDES PLL, reference clock
2. Set up the peripheral mode (EP/RC)
3. Power up the peripheral
4. Disable link training
5. Configure the peripheral, including BAR masks
6. Configure Inbound Address Translation
7. Configure Outbound Address Translation
8. Enable Link Training
9. Insure Link Training completion
   PCIe link is up and ready to be used.

In order to check that all values are within bounds, the LLD can be recompiled with the -Dpcie_DEBUG compiler flag. This will ensure that all values passed to writes fit within their assigned bitfields.

Copyright 2012, Texas Instruments Incorporated