# pcieDebug1Reg_s Struct Reference
[PCIE LLD Port Logic Register Definitions]

Specification of the Debug 1 Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
uint8_t | scramblerDisable
| [rw] Scrambling disabled for the link.
uint8_t | linkDisable
| [rw] LTSSM in DISABLE state. Link inoperable.
uint8_t | linkInTraining
| [rw] LTSSM performing link training.
uint8_t | rcvrRevrsPolEn
| [rw] LTSSM testing for polarity reversal.
uint8_t | trainingRstN
| [rw] LTSSM-negotiated link reset.
uint8_t | pipeTxdetectrxLb
| [rw] PIPE receiver detect/loopback request.
uint8_t | pipeTxelecidle
| [rw] PIPE transmit electrical idle request.
uint8_t | pipeTxcompliance
| [rw] PIPE transmit compliance request.
uint8_t | appInitRst
| [rw] Application request to initiate training reset.
uint8_t | rmlhTsLinkNum
| [rw] Link number advertised/confirmed by link partner.
uint8_t | xmlhLinkUp
| [rw] LTSSM reports PHY link up.
uint8_t | rmlhInskipRcv
| [rw] Receiver reports skip reception.
uint8_t | rmlhTs1Rcvd
| [rw] TS1 training sequence received (pulse).
uint8_t | rmlhTs2Rcvd
| [rw] TS2 training sequence received (pulse).
uint8_t | rmlhRcvdLaneRev
| [rw] Receiver detected lane reversal.

## Detailed Description

Specification of the Debug 1 Register.

This register may be used for both endpoint and root complex modes.

## Field Documentation

uint8_t pcieDebug1Reg_s::appInitRst

[rw] Application request to initiate training reset.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::linkDisable

[rw] LTSSM in DISABLE state. Link inoperable.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::linkInTraining

[rw] LTSSM performing link training.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::pipeTxcompliance

[rw] PIPE transmit compliance request.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::pipeTxdetectrxLb

[rw] PIPE receiver detect/loopback request.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::pipeTxelecidle

[rw] PIPE transmit electrical idle request.

Field size: 1 bit

uint32_t pcieDebug1Reg_s::raw

[ro] Raw image of register on read; actual value on write

uint8_t pcieDebug1Reg_s::rcvrRevrsPolEn

[rw] LTSSM testing for polarity reversal.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::rmlhInskipRcv

[rw] Receiver reports skip reception.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::rmlhRcvdLaneRev

[rw] Receiver detected lane reversal.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::rmlhTs1Rcvd

[rw] TS1 training sequence received (pulse).

Field size: 1 bit

uint8_t pcieDebug1Reg_s::rmlhTs2Rcvd

[rw] TS2 training sequence received (pulse).

Field size: 1 bit

uint8_t pcieDebug1Reg_s::rmlhTsLinkNum

[rw] Link number advertised/confirmed by link partner.

Field size: 8 bits

uint8_t pcieDebug1Reg_s::scramblerDisable

[rw] Scrambling disabled for the link.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::trainingRstN

[rw] LTSSM-negotiated link reset.

Field size: 1 bit

uint8_t pcieDebug1Reg_s::xmlhLinkUp

[rw] LTSSM reports PHY link up.

Field size: 1 bit

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated