Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

### - l -

- l0Latency : pcieDeviceCapReg_s
- l0sEntryLatency : pcieAckFreqReg_s
- l1EntryLatency : pcieAckFreqReg_s
- l1ExitLat : pcieLinkCapReg_s
- l1Latency : pcieDeviceCapReg_s
- l2Deskew : pcieLaneSkewReg_s
- laneSkew : pcieRegisters_s , pcieLaneSkewReg_s
- latTmr : pcieBistReg_s , pcieType1BistHeaderReg_s
- legacyIrqEnableClr : pcieRegisters_s
- legacyIrqEnableSet : pcieRegisters_s
- legacyIrqEnClr : pcieLegacyIrqEnableClrReg_s
- legacyIrqEnSet : pcieLegacyIrqEnableSetReg_s
- legacyIrqStatus : pcieRegisters_s , pcieLegacyIrqStatusReg_s
- legacyIrqStatusRaw : pcieRegisters_s
- legacyRawStatus : pcieLegacyIrqStatusRawReg_s
- limit : pcieType1MemspaceReg_s , pciePrefMemReg_s , pciePrefLimitUpperReg_s
- limitAddr : pciePrefMemReg_s
- linkBwIntEn : pcieLinkStatCtrlReg_s
- linkBwMgmtIntEn : pcieLinkStatCtrlReg_s
- linkBwMgmtStatus : pcieLinkStatCtrlReg_s
- linkBwStatus : pcieLinkStatCtrlReg_s
- linkCap : pcieRegisters_s
- linkCtrl2 : pcieRegisters_s
- linkDisable : pcieLinkStatCtrlReg_s , pcieDebug1Reg_s
- linkInTraining : pcieDebug1Reg_s
- linkNum : pciePlForceLinkReg_s
- linkRstReq : pciePmRstIrqStatusRawReg_s , pciePmRstIrqStatusReg_s , pciePmRstIrqEnableSetReg_s , pciePmRstIrqEnableClrReg_s
- linkSpeed : pcieLinkStatCtrlReg_s
- linkStatCtrl : pcieRegisters_s
- linkTraining : pcieLinkStatCtrlReg_s
- lnEn : pcieGen2Reg_s
- lnkCtrl : pcieRegisters_s
- lnkMode : pcieLnkCtrlReg_s
- lnkRate : pcieLnkCtrlReg_s
- lnkState : pciePlForceLinkReg_s
- location : pcieBarCfg_s
- losExitLat : pcieLinkCapReg_s
- lpbkEn : pcieLnkCtrlReg_s
- lpeCnt : pciePlForceLinkReg_s
- ltssmEn : pcieCmdStatusReg_s
- ltssmState : pcieDebug0Reg_s

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