Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

### - p -

- parError : pcieStatusCmdReg_s
- parity : pcieStatusCmdReg_s
- pcieCap : pciePciesCapReg_s
- pciesCap : pcieRegisters_s
- pcsCfg0 : pcieRegisters_s
- pcsCfg1 : pcieRegisters_s
- pcsDetDelay : pciePcsCfg0Reg_s
- pcsErrBit : pciePcsCfg1Reg_s
- pcsErrLn : pciePcsCfg1Reg_s
- pcsErrMode : pciePcsCfg1Reg_s
- pcsFixStd : pciePcsCfg0Reg_s
- pcsFixTerm : pciePcsCfg0Reg_s
- pcsHoldOff : pciePcsCfg0Reg_s
- pcsL2EnidlOff : pciePcsCfg0Reg_s
- pcsL2L0SRxOff : pciePcsCfg0Reg_s
- pcsLnEn : pciePcsStatusReg_s
- pcsRCDelay : pciePcsCfg0Reg_s
- pcsRev : pciePcsStatusReg_s
- pcsRxEn : pciePcsStatusReg_s
- pcsRxTxOn : pciePcsCfg0Reg_s
- pcsRxTxRst : pciePcsCfg0Reg_s
- pcsShrtTM : pciePcsCfg0Reg_s
- pcsStat186 : pciePcsCfg0Reg_s
- pcsStatus : pcieRegisters_s
- pcsSync : pciePcsCfg0Reg_s
- pcsTxEn : pciePcsStatusReg_s
- pErrRespEn : pcieType1BridgeIntReg_s
- phantomEn : pcieDevStatCtrlReg_s
- phantomFld : pcieDeviceCapReg_s
- pid : pcieRegisters_s
- pipeTxcompliance : pcieDebug1Reg_s
- pipeTxData : pcieDebug0Reg_s
- pipeTxDataK : pcieDebug0Reg_s
- pipeTxdetectrxLb : pcieDebug1Reg_s
- pipeTxelecidle : pcieDebug1Reg_s
- plAckTimer : pcieRegisters_s
- plForceLink : pcieRegisters_s
- plOMsg : pcieRegisters_s
- pmCap : pcieRegisters_s
- pmCapCtlStat : pcieRegisters_s
- pmCapID : pciePMCapReg_s
- pmCfg : pcieRegisters_s
- pmCmd : pcieRegisters_s
- pmCtl : pcieSlotStatCtrlReg_s
- pme : pciePmCmdReg_s
- pmeClk : pciePMCapReg_s
- pmeEn : pciePMCapCtlStatReg_s
- pmeIntEn : pcieRootCtrlCapReg_s
- pmePend : pcieRootStatusReg_s
- pmeReqID : pcieRootStatusReg_s
- pmeSpecVer : pciePMCapReg_s
- pmeStatus : pciePMCapCtlStatReg_s , pcieRootStatusReg_s
- pmeSuppN : pciePMCapReg_s
- pmIndCtl : pcieSlotStatCtrlReg_s
- pmNextPtr : pciePMCapReg_s
- pmPme : pciePmRstIrqEnableSetReg_s , pciePmRstIrqStatusRawReg_s , pciePmRstIrqStatusReg_s , pciePmRstIrqEnableClrReg_s
- pmRstIrqEnableClr : pcieRegisters_s
- pmRstIrqEnableSet : pcieRegisters_s
- pmRstIrqStatus : pcieRegisters_s
- pmRstIrqStatusRaw : pcieRegisters_s
- pmToAck : pciePmRstIrqStatusRawReg_s , pciePmRstIrqStatusReg_s , pciePmRstIrqEnableClrReg_s , pciePmRstIrqEnableSetReg_s
- pmTurnoff : pciePmRstIrqStatusRawReg_s , pciePmRstIrqStatusReg_s , pciePmRstIrqEnableClrReg_s , pciePmRstIrqEnableSetReg_s
- pollDeemph : pcieLinkCtrl2Reg_s
- portNum : pcieLinkCapReg_s
- postedWrEn : pcieCmdStatusReg_s
- prefBaseUpper : pcieRegisters_s
- prefetch : pcieBarReg_s , pcieBarCfg_s
- prefLimitUpper : pcieRegisters_s
- prefMem : pcieRegisters_s
- presenceChg : pcieSlotStatCtrlReg_s
- presenceDet : pcieSlotStatCtrlReg_s
- priBusNum : pcieType1BusNumReg_s
- priority : pcieRegisters_s
- priTimer : pcieType1BridgeIntReg_s
- prsDetChgEn : pcieSlotStatCtrlReg_s
- psndTlpMsk : pcieUncErrMaskReg_s
- psndTlpSt : pcieUncErrReg_s
- psndTlpSvrty : pcieUncErrSvrtyReg_s
- ptr : pcieCapPtrReg_s
- pwrCtl : pcieSlotCapReg_s
- pwrFault : pcieSlotStatCtrlReg_s
- pwrFltDetEn : pcieSlotStatCtrlReg_s
- pwrInd : pcieSlotCapReg_s
- pwrLimitScale : pcieDeviceCapReg_s
- pwrLimitValue : pcieDeviceCapReg_s
- pwrLmtScale : pcieSlotCapReg_s
- pwrLmtValue : pcieSlotCapReg_s
- pwrState : pciePMCapCtlStatReg_s

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