# MDIO Symbols Defined
[MDIO]

## Defines

#define | PHYREG0_read(regadr, phyadr)
#define | PHYREG0_write(regadr, phyadr, data)
#define | PHYREG0_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) )
#define | PHYREG0_waitResults(results)
#define | PHYREG0_waitResultsAck(results, ack)
#define | PHYREG1_read(regadr, phyadr)
#define | PHYREG1_write(regadr, phyadr, data)
#define | PHYREG1_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS1,MDIO_USERACCESS1_GO) )
#define | PHYREG1_waitResults(results)
#define | PHYREG1_waitResultsAck(results, ack)
#define | MDIO_MODEFLG_AUTONEG 0x0001
#define | MDIO_MODEFLG_HD10 0x0002
#define | MDIO_MODEFLG_FD10 0x0004
#define | MDIO_MODEFLG_HD100 0x0008
#define | MDIO_MODEFLG_FD100 0x0010
#define | MDIO_MODEFLG_FD1000 0x0020
#define | MDIO_MODEFLG_LOOPBACK 0x0040
#define | MDIO_MODEFLG_NWAYACTIVE 0x0080
#define | MDIO_MODEFLG_EXTLOOPBACK 0x0100
#define | MDIO_MODEFLG_SPECPHYADDR 0x0200
#define | MDIO_LINKSTATUS_NOLINK 0
#define | MDIO_LINKSTATUS_HD10 1
#define | MDIO_LINKSTATUS_FD10 2
#define | MDIO_LINKSTATUS_HD100 3
#define | MDIO_LINKSTATUS_FD100 4
#define | MDIO_LINKSTATUS_FD1000 5
#define | MDIO_EVENT_NOCHANGE 0
#define | MDIO_EVENT_LINKDOWN 1
#define | MDIO_EVENT_LINKUP 2
#define | MDIO_EVENT_PHYERROR 3
#define | MDIO_ERROR_INVALID 1
| Standard Error Codes.
#define | VBUSCLK 165
#define | PHYREG_CONTROL 0
#define | PHYREG_CONTROL_RESET (1<<15)
#define | PHYREG_CONTROL_LOOPBACK (1<<14)
#define | PHYREG_CONTROL_SPEEDLSB (1<<13)
#define | PHYREG_CONTROL_AUTONEGEN (1<<12)
#define | PHYREG_CONTROL_POWERDOWN (1<<11)
#define | PHYREG_CONTROL_ISOLATE (1<<10)
#define | PHYREG_CONTROL_AUTORESTART (1<<9)
#define | PHYREG_CONTROL_DUPLEXFULL (1<<8)
#define | PHYREG_CONTROL_SPEEDMSB (1<<6)
#define | PHYREG_STATUS 1
#define | PHYREG_STATUS_FD100 (1<<14)
#define | PHYREG_STATUS_HD100 (1<<13)
#define | PHYREG_STATUS_FD10 (1<<12)
#define | PHYREG_STATUS_HD10 (1<<11)
#define | PHYREG_STATUS_EXTSTATUS (1<<8)
#define | PHYREG_STATUS_NOPREAMBLE (1<<6)
#define | PHYREG_STATUS_AUTOCOMPLETE (1<<5)
#define | PHYREG_STATUS_REMOTEFAULT (1<<4)
#define | PHYREG_STATUS_AUTOCAPABLE (1<<3)
#define | PHYREG_STATUS_LINKSTATUS (1<<2)
#define | PHYREG_STATUS_JABBER (1<<1)
#define | PHYREG_STATUS_EXTENDED (1<<0)
#define | PHYREG_ID1 2
#define | PHYREG_ID2 3
#define | PHYREG_ADVERTISE 4
#define | PHYREG_ADVERTISE_NEXTPAGE (1<<15)
#define | PHYREG_ADVERTISE_FAULT (1<<13)
#define | PHYREG_ADVERTISE_PAUSE (1<<10)
#define | PHYREG_ADVERTISE_FD100 (1<<8)
#define | PHYREG_ADVERTISE_HD100 (1<<7)
#define | PHYREG_ADVERTISE_FD10 (1<<6)
#define | PHYREG_ADVERTISE_HD10 (1<<5)
#define | PHYREG_ADVERTISE_MSGMASK (0x1F)
#define | PHYREG_ADVERTISE_MSG (1)
#define | PHYREG_PARTNER 5
#define | PHYREG_PARTNER_NEXTPAGE (1<<15)
#define | PHYREG_PARTNER_ACK (1<<14)
#define | PHYREG_PARTNER_FAULT (1<<13)
#define | PHYREG_PARTNER_PAUSE (1<<10)
#define | PHYREG_PARTNER_FD100 (1<<8)
#define | PHYREG_PARTNER_HD100 (1<<7)
#define | PHYREG_PARTNER_FD10 (1<<6)
#define | PHYREG_PARTNER_HD10 (1<<5)
#define | PHYREG_PARTNER_MSGMASK (0x1F)
#define | PHYREG_1000CONTROL 9
#define | PHYREG_ADVERTISE_FD1000 (1<<9)
#define | PHYREG_1000STATUS 0xA
#define | PHYREG_PARTNER_FD1000 (1<<11)
#define | PHYREG_EXTSTATUS 0x0F
#define | PHYREG_EXTSTATUS_FD1000 (1<<13)
#define | PHYREG_SHADOW 0x18
#define | PHYREG_SHADOW_EXTLOOPBACK 0x8400
#define | PHYREG_SHADOW_RGMIIMODE 0xF080
#define | PHYREG_SHADOW_INBAND 0xF1C7
#define | PHYREG_ACCESS 0x1C
#define | PHYREG_ACCESS_COPPER 0xFC00
#define | PHYSTATE_MDIOINIT 0
#define | PHYSTATE_RESET 1
#define | PHYSTATE_NWAYSTART 2
#define | PHYSTATE_NWAYWAIT 3
#define | PHYSTATE_LINKWAIT 4
#define | PHYSTATE_LINKED 5

## Define Documentation

#define MDIO_ERROR_INVALID 1

Standard Error Codes.

Function or calling parameter is invalid

#define MDIO_EVENT_LINKDOWN 1

Link down event

#define MDIO_EVENT_LINKUP 2

Link (or re-link) event

#define MDIO_EVENT_NOCHANGE 0

These events are returned by MDIO_timerTick() to allow the application (or EMAC) to track MDIO status. No change from previous status

#define MDIO_EVENT_PHYERROR 3

No PHY connected

#define MDIO_LINKSTATUS_FD10 2

Link Status: FD10

#define MDIO_LINKSTATUS_FD100 4

Link Status: FD100

#define MDIO_LINKSTATUS_FD1000 5

Link Status: FD1000

#define MDIO_LINKSTATUS_HD10 1

Link Status: HD10

#define MDIO_LINKSTATUS_HD100 3

Link Status: HD100

#define MDIO_LINKSTATUS_NOLINK 0

These values indicate current PHY link status Link Status: No Link

#define MDIO_MODEFLG_AUTONEG 0x0001

These flags determine how the MDIO module behaves Use Autonegotiate

#define MDIO_MODEFLG_EXTLOOPBACK 0x0100

Use external PHY Loopback, with plug

#define MDIO_MODEFLG_FD10 0x0004

Use 10Mb/s Full Duplex

#define MDIO_MODEFLG_FD100 0x0010

Use 100Mb/s Full Duplex

#define MDIO_MODEFLG_FD1000 0x0020

Use 1000Mb/s Full Duplex

#define MDIO_MODEFLG_HD10 0x0002

Use 10Mb/s Half Duplex

#define MDIO_MODEFLG_HD100 0x0008

Use 100Mb/s Half Duplex

#define MDIO_MODEFLG_LOOPBACK 0x0040

Use PHY Loopback

#define MDIO_MODEFLG_NWAYACTIVE 0x0080

NWAY currently active

#define MDIO_MODEFLG_SPECPHYADDR 0x0200

Monitor PHY address which is specified by user

#define PHYREG0_read | ( | regadr,
|  | phyadr |  | ) |

Value:

    MDIO_REGS->USERACCESS0 =                            \
                        CSL_FMK(MDIO_USERACCESS0_GO,1u)         |   \
                        CSL_FMK(MDIO_USERACCESS0_REGADR,regadr) |   \
                        CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)

This macro reads from the PHY register through the USERACESS0 register provided in MDIO module

#define PHYREG0_wait | ( |  | ) | while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) )

Waits for GO bit to set

#define PHYREG0_waitResults | ( | results |  | ) |

Value:

    {                                                \
                while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) );             \
                results = CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_DATA); }

Waits for GO bit to set and reads data from the PHY register

#define PHYREG0_waitResultsAck | ( | results,
|  | ack |  | ) |

Value:

    {                                        \
                while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) );             \
                results = CSL_FEXT( MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_DATA );            \
                ack = CSL_FEXT( MDIO_REGS->USERACCESS0, MDIO_USERACCESS0_ACK); }

Waits for GO bit to set, reads data from the PHY register and checks for ACK

#define PHYREG0_write | ( | regadr,
|  | phyadr,
|  | data |  | ) |

Value:

    MDIO_REGS->USERACCESS0 =                            \
                        CSL_FMK(MDIO_USERACCESS0_GO,1u)         |   \
                        CSL_FMK(MDIO_USERACCESS0_WRITE,1)       |   \
                        CSL_FMK(MDIO_USERACCESS0_REGADR,regadr) |   \
                        CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr) |   \
                        CSL_FMK(MDIO_USERACCESS0_DATA, data)

This macro writes to the PHY register through the USERACESS0 register provided in MDIO module

#define PHYREG1_read | ( | regadr,
|  | phyadr |  | ) |

Value:

    MDIO_REGS->USERACCESS1 =                            \
                        CSL_FMK(MDIO_USERACCESS1_GO,1u)         |   \
                        CSL_FMK(MDIO_USERACCESS1_REGADR,regadr) |   \
                        CSL_FMK(MDIO_USERACCESS1_PHYADR,phyadr)

This macro reads from the PHY register through the USERACESS1 register provided in MDIO module

#define PHYREG1_wait | ( |  | ) | while( CSL_FEXT(MDIO_REGS->USERACCESS1,MDIO_USERACCESS1_GO) )

Waits for GO bit to set

#define PHYREG1_waitResults | ( | results |  | ) |

Value:

    {                                                \
                while( CSL_FEXT(MDIO_REGS->USERACCESS1,MDIO_USERACCESS1_GO) );             \
                results = CSL_FEXT(MDIO_REGS->USERACCESS1,MDIO_USERACCESS1_DATA); }

Waits for GO bit to set and reads data from the PHY register

#define PHYREG1_waitResultsAck | ( | results,
|  | ack |  | ) |

Value:

    {                                        \
                while( CSL_FEXT(MDIO_REGS->USERACCESS1,MDIO_USERACCESS1_GO) );             \
                results = CSL_FEXT( MDIO_REGS->USERACCESS1,MDIO_USERACCESS1_DATA );            \
                ack = CSL_FEXT( MDIO_REGS->USERACCESS1, MDIO_USERACCESS1_ACK); }

Waits for GO bit to set, reads data from the PHY register and checks for ACK

#define PHYREG1_write | ( | regadr,
|  | phyadr,
|  | data |  | ) |

Value:

    MDIO_REGS->USERACCESS1 =                            \
                        CSL_FMK(MDIO_USERACCESS1_GO,1u)         |   \
                        CSL_FMK(MDIO_USERACCESS1_WRITE,1)       |   \
                        CSL_FMK(MDIO_USERACCESS1_REGADR,regadr) |   \
                        CSL_FMK(MDIO_USERACCESS1_PHYADR,phyadr) |   \
                        CSL_FMK(MDIO_USERACCESS1_DATA, data)

This macro writes to the PHY register through the USERACESS1 register provided in MDIO module

#define PHYREG_1000CONTROL 9

Physical 1000 Ctrl reg

#define PHYREG_1000STATUS 0xA

Phy 1000 Status reg

#define PHYREG_ACCESS 0x1C

Physical Access

#define PHYREG_ACCESS_COPPER 0xFC00

Access Copper

#define PHYREG_ADVERTISE 4

Used by MDIO to configure a MII compliant PHY Physical Advertise reg

#define PHYREG_ADVERTISE_FAULT (1<<13)

Set Fault bit

#define PHYREG_ADVERTISE_FD10 (1<<6)

Set FD10 bit

#define PHYREG_ADVERTISE_FD100 (1<<8)

Set FD100 bit

#define PHYREG_ADVERTISE_FD1000 (1<<9)

Advertise FD1000 bit

#define PHYREG_ADVERTISE_HD10 (1<<5)

Set HD10 bit

#define PHYREG_ADVERTISE_HD100 (1<<7)

Set HD100 bit

#define PHYREG_ADVERTISE_MSG (1)

Set Message bit

#define PHYREG_ADVERTISE_MSGMASK (0x1F)

Set Message mask bit

#define PHYREG_ADVERTISE_NEXTPAGE (1<<15)

Set next page bit

#define PHYREG_ADVERTISE_PAUSE (1<<10)

Set Pause bit

#define PHYREG_CONTROL 0

Used by MDIO to configure a MII compliant PHY

Used by MDIO to configure a MII compliant PHY Control register

#define PHYREG_CONTROL_AUTONEGEN (1<<12)

Auto Negate Enable bit

#define PHYREG_CONTROL_AUTORESTART (1<<9)

Set Auto restart bit

#define PHYREG_CONTROL_DUPLEXFULL (1<<8)

Set Full Duplex bit

#define PHYREG_CONTROL_ISOLATE (1<<10)

Set Isolate bit

#define PHYREG_CONTROL_LOOPBACK (1<<14)

Set Loop back bit

#define PHYREG_CONTROL_POWERDOWN (1<<11)

Set Power Down bit

#define PHYREG_CONTROL_RESET (1<<15)

Set Reset bit

#define PHYREG_CONTROL_SPEEDLSB (1<<13)

Set Speed LSB bit

#define PHYREG_CONTROL_SPEEDMSB (1<<6)

Set Speed MSB bit

#define PHYREG_EXTSTATUS 0x0F

Physical Ext status reg

#define PHYREG_EXTSTATUS_FD1000 (1<<13)

Ext Status FD1000 bit

#define PHYREG_ID1 2

Used by MDIO to configure a MII compliant PHY Physical ID 1 register

#define PHYREG_ID2 3

Physical ID 1 register

#define PHYREG_PARTNER 5

Used by MDIO to configure a MII compliant PHY Physical Partner reg

#define PHYREG_PARTNER_ACK (1<<14)

Set Acknowledge bit

#define PHYREG_PARTNER_FAULT (1<<13)

Set Fault bit

#define PHYREG_PARTNER_FD10 (1<<6)

Set FD10 bit

#define PHYREG_PARTNER_FD100 (1<<8)

Set FD100 bit

#define PHYREG_PARTNER_FD1000 (1<<11)

Partner FD1000 bit

#define PHYREG_PARTNER_HD10 (1<<5)

Set HD10 bit

#define PHYREG_PARTNER_HD100 (1<<7)

Set HD100 bit

#define PHYREG_PARTNER_MSGMASK (0x1F)

Set Message mask bit

#define PHYREG_PARTNER_NEXTPAGE (1<<15)

Set next page bit

#define PHYREG_PARTNER_PAUSE (1<<10)

Set Pause bit

#define PHYREG_SHADOW 0x18

Used by MDIO to configure a MII compliant PHY Physical shadow reg

#define PHYREG_SHADOW_EXTLOOPBACK 0x8400

Shadow Ext Loopback bit

#define PHYREG_SHADOW_INBAND 0xF1C7

Shadow In band bit

#define PHYREG_SHADOW_RGMIIMODE 0xF080

Shadow RGMII mode bit

#define PHYREG_STATUS 1

Used by MDIO to configure a MII compliant PHY Status register

#define PHYREG_STATUS_AUTOCAPABLE (1<<3)

Set Auto Capable bit

#define PHYREG_STATUS_AUTOCOMPLETE (1<<5)

Set Auto complete bit

#define PHYREG_STATUS_EXTENDED (1<<0)

Set Extended bit

#define PHYREG_STATUS_EXTSTATUS (1<<8)

Set External Status bit

#define PHYREG_STATUS_FD10 (1<<12)

Set FD10 bit

#define PHYREG_STATUS_FD100 (1<<14)

Set FD100 bit

#define PHYREG_STATUS_HD10 (1<<11)

Set HD10bit

#define PHYREG_STATUS_HD100 (1<<13)

Set HD100 bit

#define PHYREG_STATUS_JABBER (1<<1)

Set Jabber bit

#define PHYREG_STATUS_LINKSTATUS (1<<2)

Set Link status bit

#define PHYREG_STATUS_NOPREAMBLE (1<<6)

Set No preamble bit

#define PHYREG_STATUS_REMOTEFAULT (1<<4)

Set Reomte default bit

#define PHYSTATE_LINKED 5

MDIO Linked

#define PHYSTATE_LINKWAIT 4

MDIO Wait for link

#define PHYSTATE_MDIOINIT 0

When using auto-negotiation, the software must keep the MAC in sync with the PHY (for duplex). This module will also attempt to "auto-select" the PHY from a potential list of 32 based on which is first to get a link.

On detection of a good link, the link speed and duplex settings will be used to update the EMAC configuration (done external to this module).

States in the PHY State Machine: MDIO Initialization state

#define PHYSTATE_NWAYSTART 2

MDIO N Way start

#define PHYSTATE_NWAYWAIT 3

MDIO N Way wait

#define PHYSTATE_RESET 1

MDIO Reset State

#define VBUSCLK 165

Standard defines/assumptions for MDIO interface

Copyright 2012, Texas Instruments Incorporated