# pciePMCapReg_s Struct Reference
[PCIE LLD Power Management Register Definitions]

Specification of the Power Management Capability Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint8_t | pmeSuppN
| [rw] PME Support.
uint8_t | d2SuppN
| [rw] D2 Support.
uint8_t | d1SuppN
| [rw] D1 Support.
uint8_t | auxCurrN
| [rw] Auxiliary Current
uint8_t | dsiN
| [rw] Device Specific Initialization
uint8_t | pmeClk
| [ro] PME clock. Hardwired to zero.
uint8_t | pmeSpecVer
| [rw] Power Management Specification Version
uint8_t | pmNextPtr
| [rw] Next capability pointer.
uint8_t | pmCapID
| [rw] Power Management Capability ID.

## Detailed Description

Specification of the Power Management Capability Register.

This register may be used for both endpoint and root complex modes.

## Field Documentation

uint8_t pciePMCapReg_s::auxCurrN

[rw] Auxiliary Current

Field size: 3 bits

uint8_t pciePMCapReg_s::d1SuppN

[rw] D1 Support.

Field size: 1 bit

uint8_t pciePMCapReg_s::d2SuppN

[rw] D2 Support.

Field size: 1 bit

uint8_t pciePMCapReg_s::dsiN

[rw] Device Specific Initialization

Field size: 1 bit

uint8_t pciePMCapReg_s::pmCapID

[rw] Power Management Capability ID.

Field size: 8 bits

uint8_t pciePMCapReg_s::pmeClk

[ro] PME clock. Hardwired to zero.

Field size: 1 bit

uint8_t pciePMCapReg_s::pmeSpecVer

[rw] Power Management Specification Version

Field size: 3 bits

uint8_t pciePMCapReg_s::pmeSuppN

[rw] PME Support.

Identifies the power states from which generates PME Messages. A value of 0 for any bit indicates that the device (or function) is not capable of generating PME Messages while in that power state.

bit 0x10: If set, PME Messages can be generated from D3cold.
bit 0x08: If set, PME Messages can be generated from D3hot.
bit 0x04: If set, PME Messages can be generated from D2.
bit 0x02: If set, PME Messages can be generated from D1.
bit 0x01: If set, PME Messages can be generated from D0.

Field size: 5 bits

uint8_t pciePMCapReg_s::pmNextPtr

[rw] Next capability pointer.

By default, it points to Message Signaled Interrupt structure.

Field size: 8 bits

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated