/*                                                                          */
/* Function    : allocate platform depend routines pointers                 */
/*                                                                          */
/* Background:   In some application FPGA is real and in other it is        */
/*               simulated, the same for CPU therefore each application     */
/*               supplies its own CPU/FPGA access routine pointers          */
/*                                                                          */
/*               Check in                                                   */



//INCLUDE FILES
//=============
#include  "windef.h"

#include  "mbdr_dsp_utils.h"
#include  "mbdr_dsp_cyclic_buffer.h"

//#include  "mbdr_dsp_debug_hw.h"
#include  "mbdr_dsp_debug_prob.h"


#include  "mbdr_dsp_dbg_print_stream_puts.h"
#include  "mbdr_dsp_pci_hw_utils.h"
#include  "mbdr_dsp_pci_manage_utils.h"
#include  "mbdr_dsp_platform_proc_ptrs.h"
#include  "mbdr_dsp_common_config_multi_core.h"
#include  "mbdr_dsp_sdc_sync_msg_operation_mode.h"
#include  "mbdr_dsp_debug_pci_simulation.h"


#include  "mbdr_dsp_sdc_sync_with_cpu.h"
#include  "mbdr_dsp_sdc_main_flow_code.h"
#include  "mbdr_dsp_sdc_system_simulation_app.h"

#include  "mbdr_dsp_sdc_sync_msg_operation_mode.h"

/* code is the same like MBDR_DSP_SYNC_MSG_WORD_T */
/* see mbdr_dsp_common_sync_msg.h                 */

mbdr_dsp_platform_external_io_access_proc_ptrs_t
                  mbdr_dsp_platform_external_io_access_proc_ptrs_tbl
 [MBDR_DSP_SDC_SYNC_MSG_OPERATION_MODE_T_SIZE] =
 {
   /* 0 - MBDR_DSP_SDC_SYNC_MSG_OPERATION_MODE_T_UNUSED */
   {0
   },

   /* 1- MBDR_DSP_SDC_SYNC_MSG_OPERATION_MODE_T_OPERATIONAL  */
   {
    &mbdr_dsp_pci_manage_utils_memcpy_write_no_base, /* cpu_write_memcpy */
    &mbdr_dsp_pci_manage_utils_write_dw_no_base     /* cpu_write_dw     */
   },

   /* 2- MBDR_DS_GRP_SYNC_MSG_OPERATION_MODE_T_SIMULATOR  */
   {
    &mbdr_dsp_cyclic_buf_standat_c_memcpy,        /* cpu_write_memcpy  */
    &mbdr_dsp_debug_pci_simulation_dw_write      /* cpu_write_dw      */
   }

 };





mbdr_dsp_platform_core_debug_proc_ptrs_t
     mbdr_dsp_platform_core_debug_proc_tbl[
                MBDR_DSP_SDC_SYNC_MSG_OPERATION_MODE_T_SIZE] =
{
    /* 0 - MBDR_DSP_SYNC_MSG_WORD_T_FPGA_DEFAULT */
   {0
   },

   {/* 1- MBDR_DSP_SYNC_MSG_WORD_T_OPERATIONAL  */
     &mbdr_dsp_utils_nop,    /* *host_wake_up                    */
     &mbdr_dsp_utils_nop,    /* *host_sync_with_dsp_work_1_0     */
     &mbdr_dsp_utils_nop,    /* *host_write_mission_to_dsp       */
     &mbdr_dsp_utils_nop_single_param,/* *host_write_cpu_state_number */
     &mbdr_dsp_utils_nop_single_param,/* *host_poll_dsp_state_number  */
     &mbdr_dsp_utils_nop, /* *dsp_initialize_print_stream             */
     &mbdr_dsp_utils_nop, /* *dsp_main_loop_kernel_debug_hook         */
     &mbdr_dsp_dbg_print_prob_dw_buf_nop /* print_prob_dw_buf */
   },


   /* 2- MBDR_DSP_SYNC_MSG_WORD_T_SIMULATOR */
   {
     /* *host_wake_up  */
     &mbdr_dsp_sdc_system_simulation_host_wake_up,

	 /* *host_sync_with_dsp_work_1_0     */
     &mbdr_dsp_sdc_system_simulation_host_sync_with_dsp_work_1_0,

	 /* *host_write_mission_to_dsp       */
     &mbdr_dsp_sdc_system_simulation_host_write_mission_to_dsp,

	 /* *host_write_cpu_state_number */
     &mbdr_dsp_sdc_system_simulation_host_write_cpu_state_number,

	 /* *host_poll_dsp_state_number  */
     &mbdr_dsp_sdc_system_simulation_host_poll_dsp_state_number,

	 /* *dsp_initialize_print_stream             */
     &mbdr_dsp_debug_initialize_print_stream,

	 /* *dsp_main_loop_kernel_debug_hook         */
     &mbdr_dsp_sdc_main_loop_user_hook_simulator,

     /* print_prob_dw_buf */
     &mbdr_dsp_dbg_print_prob_dw_buf}
};
