# pcieDevStatCtrlReg_s Struct Reference
[PCIE LLD Capabilities Register Definitions]

Specification of the Device Status and Control Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint8_t | tpend
| [ro] Transaction Pending
uint8_t | auxPwr
| [ro] Auxiliary Power Detected
uint8_t | rqDet
| [rw] Unsupported Request Detected
uint8_t | fatalEr
| [rw] Fatal Error Detected
uint8_t | nFatalEr
| [rw] Non-fatal Error Detected
uint8_t | corrEr
| [rw] Correctable Error Detected
uint8_t | maxSz
| [rw] Maximum Read Request Size
uint8_t | noSnoop
| [rw] Enable no snoop
uint8_t | auxPwrEn
| [rw] AUX Power PM Enable
uint8_t | phantomEn
| [rw] Phantom Function Enable
uint8_t | xtagEn
| [rw] Extended Tag Field Enable
uint8_t | maxPayld
| [rw] Maximum Payload Size
uint8_t | relaxed
| [rw] Enable Relaxed Ordering
uint8_t | reqRp
| [rw] Enable Unsupported Request Reporting
uint8_t | fatalErRp
| [rw] Fatal Error Reporting Enable
uint8_t | nFatalErRp
| [rw] Non-fatal Error Reporting Enable
uint8_t | corErRp
| [rw] Correctable Error Reporting Enable

## Detailed Description

Specification of the Device Status and Control Register.

This register may be used for both endpoint and root complex modes.

## Field Documentation

uint8_t pcieDevStatCtrlReg_s::auxPwr

[ro] Auxiliary Power Detected

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::auxPwrEn

[rw] AUX Power PM Enable

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::corErRp

[rw] Correctable Error Reporting Enable

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::corrEr

[rw] Correctable Error Detected

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::fatalEr

[rw] Fatal Error Detected

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::fatalErRp

[rw] Fatal Error Reporting Enable

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::maxPayld

[rw] Maximum Payload Size

Field size: 3 bits

uint8_t pcieDevStatCtrlReg_s::maxSz

[rw] Maximum Read Request Size

Field size: 3 bits

uint8_t pcieDevStatCtrlReg_s::nFatalEr

[rw] Non-fatal Error Detected

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::nFatalErRp

[rw] Non-fatal Error Reporting Enable

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::noSnoop

[rw] Enable no snoop

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::phantomEn

[rw] Phantom Function Enable

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::relaxed

[rw] Enable Relaxed Ordering

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::reqRp

[rw] Enable Unsupported Request Reporting

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::rqDet

[rw] Unsupported Request Detected

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::tpend

[ro] Transaction Pending

Field size: 1 bit

uint8_t pcieDevStatCtrlReg_s::xtagEn

[rw] Extended Tag Field Enable

Field size: 1 bit

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated