# Cppi_RxFlowCfg Struct Reference
[CPPI Low Level Driver Data Structures]

CPPI receive flow configuration structure. More...

`#include <cppi_drv.h>`

## Data Fields

int16_t | flowIdNum
uint16_t | rx_dest_qnum
uint16_t | rx_dest_qmgr
uint16_t | rx_sop_offset
uint16_t | rx_ps_location
uint8_t | rx_desc_type
uint16_t | rx_error_handling
uint16_t | rx_psinfo_present
uint16_t | rx_einfo_present
uint8_t | rx_dest_tag_lo
uint8_t | rx_dest_tag_hi
uint8_t | rx_src_tag_lo
uint8_t | rx_src_tag_hi
uint8_t | rx_size_thresh0_en
uint8_t | rx_size_thresh1_en
uint8_t | rx_size_thresh2_en
uint8_t | rx_dest_tag_lo_sel
uint8_t | rx_dest_tag_hi_sel
uint8_t | rx_src_tag_lo_sel
uint8_t | rx_src_tag_hi_sel
uint16_t | rx_fdq1_qnum
uint16_t | rx_fdq1_qmgr
uint16_t | rx_fdq0_sz0_qnum
uint16_t | rx_fdq0_sz0_qmgr
uint16_t | rx_fdq3_qnum
uint16_t | rx_fdq3_qmgr
uint16_t | rx_fdq2_qnum
uint16_t | rx_fdq2_qmgr
uint16_t | rx_size_thresh1
uint16_t | rx_size_thresh0
uint16_t | rx_fdq0_sz1_qnum
uint16_t | rx_fdq0_sz1_qmgr
uint16_t | rx_size_thresh2
uint16_t | rx_fdq0_sz3_qnum
uint16_t | rx_fdq0_sz3_qmgr
uint16_t | rx_fdq0_sz2_qnum
uint16_t | rx_fdq0_sz2_qmgr

## Detailed Description

CPPI receive flow configuration structure.

## Field Documentation

int16_t Cppi_RxFlowCfg::flowIdNum

Rx flow configuration register A flow ID number If flowIdNum is set to CPPI_PARAM_NOT_SPECIFIED then the next available flow ID will be allocated

uint8_t Cppi_RxFlowCfg::rx_desc_type

This field indicates the descriptor type to use 1 = Host, 2 = Monolithic

uint16_t Cppi_RxFlowCfg::rx_dest_qmgr

This field indicates the default receive queue manager that this channel should use

uint16_t Cppi_RxFlowCfg::rx_dest_qnum

This field indicates the default receive queue that this channel should use

uint8_t Cppi_RxFlowCfg::rx_dest_tag_hi

This is the value to insert into bits 15:8 of the destination tag if the rx_dest_tag_hi_sel is set to 1

uint8_t Cppi_RxFlowCfg::rx_dest_tag_hi_sel

This field specifies the source for bits 15:8 of the source tag field in the word 1 of the output PD. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_dest_tag_hi 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with dest_tag[7:0] from back end application 5 = overwrite with dest_tag[15:8] from back end application 6-7 = RESERVED

uint8_t Cppi_RxFlowCfg::rx_dest_tag_lo

Rx flow configuration register B This is the value to insert into bits 7:0 of the destination tag if the rx_dest_tag_lo_sel is set to 1

uint8_t Cppi_RxFlowCfg::rx_dest_tag_lo_sel

This field specifies the source for bits 7:0 of the source tag field in word 1 of the output PD. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_dest_tag_lo 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with dest_tag[7:0] from back end application 5 = overwrite with dest_tag[15:8] from back end application 6-7 = RESERVED

uint16_t Cppi_RxFlowCfg::rx_einfo_present

This field controls whether or not the Extended Packet Info Block will be present in the Rx Packet Descriptor. 0 - The port DMA will clear the Extended Packet Info Block Present bit in the PD and will drop any extended packet info words that are presented from the back end application. 1 - The port DMA will set the Extended Packet Info Block Present bit in the PD and will copy any extended packet info words that are presented across the Rx streaming interface into the extended packet info words in the descriptor. If no extended packet info words are presented from the back end application, the port DMA will overwrite the fields with zeroes.

uint16_t Cppi_RxFlowCfg::rx_error_handling

This field controls the error handling mode for the flow and is only used when channel errors occurs 0 = Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues/pools they were allocated to 1 = Starvation errors result in subsequent re-try of the descriptor allocation operation.

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz0_qmgr

This field specifies which Queue Manager should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz0_qnum

This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz1_qmgr

This field specifies which Queue Manager should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz1_qnum

Rx flow configuration register G This field specifies which Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size0 value

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz2_qmgr

This field specifies which Free Descriptor Queue Manager should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz2_qnum

This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size2 value

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz3_qmgr

This field specifies which Free Descriptor Queue Manager should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size3 value

uint16_t Cppi_RxFlowCfg::rx_fdq0_sz3_qnum

Rx flow configuration register H This field specifies which Free Descriptor Queue should be used for the 1st Rx buffer in a packet whose size is less than or equal to the rx_size3 value

uint16_t Cppi_RxFlowCfg::rx_fdq1_qmgr

This field specifies which Queue Manager should be used for the 2nd Rx buffer in a host type packet

uint16_t Cppi_RxFlowCfg::rx_fdq1_qnum

Rx flow configuration register D This field specifies which Free Descriptor Queue should be used for the 2nd Rx buffer in a host type packet

uint16_t Cppi_RxFlowCfg::rx_fdq2_qmgr

This field specifies which Queue Manager should be used for the 3rd Rx buffer in a host type packet

uint16_t Cppi_RxFlowCfg::rx_fdq2_qnum

This field specifies which Free Descriptor Queue should be used for the 3rd Rx buffer in a host type packet

uint16_t Cppi_RxFlowCfg::rx_fdq3_qmgr

This field specifies which Queue Manager should be used for the 4th or later Rx buffers in a host type packet

uint16_t Cppi_RxFlowCfg::rx_fdq3_qnum

Rx flow configuration register E This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet

uint16_t Cppi_RxFlowCfg::rx_ps_location

This field controls where the Protocol Specific words will be placed in the Host Mode CPPI data structure 0 - protocol specific information is located in descriptor 1 - protocol specific information is located in SOP buffer

uint16_t Cppi_RxFlowCfg::rx_psinfo_present

This field controls whether or not the Protocol Specific words will be present in the Rx Packet Descriptor 0 - The port DMA will set the PS word count to 0 in the PD and will drop any PS words that are presented from the back end application. 1 - The port DMA will set the PS word count to the value given by the back end application and will copy the PS words from the back end application to the location

uint16_t Cppi_RxFlowCfg::rx_size_thresh0

This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the rx_fdq0_sz0_qmgr and rx_fdq0_sz0_qnum fields. This field is optional.

uint8_t Cppi_RxFlowCfg::rx_size_thresh0_en

Rx flow configuration register C This bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_thresh0 fields to determine which FDQ to allocate the SOP buffer from. The bits in this field is encoded as follows: 0 = Do not use the threshold. 1 = Use the thresholds to select SOP FDQ rx_fdq0_sz0_qnum/rx_fdq0_sz0_qmgr.

uint16_t Cppi_RxFlowCfg::rx_size_thresh1

Rx flow configuration register F This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is greater than the rx_size_thresh0 but is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the rx_fdq0_sz1_qmgr and rx_fdq0_sz1_qnum fields. If enabled, this value must be greater than the value given in the rx_size_thresh0 field. This field is optional.

uint8_t Cppi_RxFlowCfg::rx_size_thresh1_en

This bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_thresh1 fields to determine which FDQ to allocate the SOP buffer from. The bits in this field is encoded as follows: 0 = Do not use the threshold. 1 = Use the thresholds to select SOP FDQ rx_fdq0_sz1_qnum/rx_fdq0_sz1_qmgr.

uint16_t Cppi_RxFlowCfg::rx_size_thresh2

This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet. If the packet size is less than or equal to the value given in this threshold, the DMA controller in the port will allocate the SOP buffer from the queue given by the rx_fdq0_sz2_qmgr and rx_fdq0_sz2_qnum fields. If enabled, this value must be greater than the value given in the rx_size_thresh1 field. This field is optional.

uint8_t Cppi_RxFlowCfg::rx_size_thresh2_en

This bits control whether or not the flow will compare the packet size received from the back end application against the rx_size_thresh2 fields to determine which FDQ to allocate the SOP buffer from. The bits in this field is encoded as follows: 0 = Do not use the threshold. 1 = Use the thresholds to select SOP FDQ rx_fdq0_sz2_qnum/rx_fdq0_sz2_qmgr.

uint16_t Cppi_RxFlowCfg::rx_sop_offset

This field specifies the number of bytes that are to be skipped in the SOP buffer before beginning to write the payload or protocol specific bytes(if they are in the sop buffer). This value must be less than the minimum size of a buffer in the system

uint8_t Cppi_RxFlowCfg::rx_src_tag_hi

This is the value to insert into bits 15:8 of the source tag if the rx_src_tag_hi_sel is set to 1

uint8_t Cppi_RxFlowCfg::rx_src_tag_hi_sel

This field specifies the source for bits 15:8 of the source tag field in the output packet descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_src_tag_hi 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with src_tag[7:0] from back end application 5 = RESERVED 6-7 = RESERVED

uint8_t Cppi_RxFlowCfg::rx_src_tag_lo

This is the value to insert into bits 7:0 of the source tag if the rx_src_tag_lo_sel is set to 1

uint8_t Cppi_RxFlowCfg::rx_src_tag_lo_sel

This field specifies the source for bits 7:0 of the source tag field in the output packet descriptor. This field is encoded as follows: 0 = do not overwrite 1 = overwrite with value given in rx_src_tag_lo 2 = overwrite with flow_id[7:0] from back end application 3 = RESERVED 4 = overwrite with src_tag[7:0] from back end application 5 = RESERVED 6-7 = RESERVED

The documentation for this struct was generated from the following file:

- cppi_drv.h

Copyright 2012, Texas Instruments Incorporated