# RM LLD Resource Table Definition Symbols and Structures
[RM LLD Module API]

## Data Structures

struct | Rm_Resource
| Resource Table resource definition structure. More...

## Defines

#define | QMSS_PDSP_DEFAULT_START_RANGE (0u)
| QMSS DPSP default start and end ranges.
#define | QMSS_QUEUE_DEFAULT_START_RANGE (0u)
| QMSS queue default start and end ranges.
#define | QMSS_MEM_REGION_DEFAULT_START_RANGE (0u)
| QMSS memory region default start and end ranges.
#define | QMSS_LINK_RAM_DEFAULT_START_RANGE (0x00000000)
| QMSS Linking RAM default start and end ranges.
#define | QMSS_ACCUM_CH_DEFAULT_START_RANGE (0u)
| QMSS Accumulator channels default start and end ranges.
#define | QMSS_QOS_CLUSTER_DEFAULT_START_RANGE (0u)
| QMSS QOS clusters default start and end ranges.
#define | QMSS_QOS_QUEUE_DEFAULT_START_RANGE (0u)
| QMSS QOS queue default start and end ranges.
#define | CPPI_SRIO_TX_CH_DEFAULT_START_RANGE (0u)
| CPPI SRIO tx channels default start and end ranges.
#define | CPPI_SRIO_RX_CH_DEFAULT_START_RANGE (0u)
| CPPI SRIO rx channels default start and end ranges.
#define | CPPI_SRIO_FLOW_DEFAULT_START_RANGE (0u)
| CPPI SRIO rx flows default start and end ranges.
#define | CPPI_QMSS_TX_CH_DEFAULT_START_RANGE (0u)
| CPPI QMSS tx channels default start and end ranges.
#define | CPPI_QMSS_RX_CH_DEFAULT_START_RANGE (0u)
| CPPI QMSS rx channels default start and end ranges.
#define | CPPI_QMSS_FLOW_DEFAULT_START_RANGE (0u)
| CPPI QMSS rx flows default start and end ranges.
#define | PA_LUT_ENTRY_DEFAULT_START_RANGE (0u)
| PA LUT entry default start and end ranges.
#define | RM_RESOURCE_MAGIC_NUMBER (0x76543210)
#define | RM_RESOURCE_FINAL_ENTRY (0xFFFFFFFF)
#define | RM_RESOURCE_QMSS_BASE 0
#define | RM_RESOURCE_QMSS_FIRMWARE_PDSP (RM_RESOURCE_QMSS_BASE+1)
#define | RM_RESOURCE_QMSS_QUEUE (RM_RESOURCE_QMSS_BASE+2)
#define | RM_RESOURCE_QMSS_MEMORY_REGION (RM_RESOURCE_QMSS_BASE+3)
#define | RM_RESOURCE_QMSS_LINKING_RAM_CONTROL (RM_RESOURCE_QMSS_BASE+4)
#define | RM_RESOURCE_QMSS_LINKING_RAM (RM_RESOURCE_QMSS_BASE+5)
#define | RM_RESOURCE_QMSS_ACCUMULATOR_CH (RM_RESOURCE_QMSS_BASE+6)
#define | RM_RESOURCE_QMSS_QOS_PDSP_TIMER (RM_RESOURCE_QMSS_BASE+7)
#define | RM_RESOURCE_QMSS_QOS_CLUSTER (RM_RESOURCE_QMSS_BASE+8)
#define | RM_RESOURCE_QMSS_QOS_QUEUE (RM_RESOURCE_QMSS_BASE+9)
#define | RM_RESOURCE_CPPI_BASE 64
#define | RM_RESOURCE_CPPI_SRIO_TX_CH (RM_RESOURCE_CPPI_BASE+1)
#define | RM_RESOURCE_CPPI_SRIO_RX_CH (RM_RESOURCE_CPPI_BASE+2)
#define | RM_RESOURCE_CPPI_SRIO_FLOW (RM_RESOURCE_CPPI_BASE+3)
#define | RM_RESOURCE_CPPI_AIF_TX_CH (RM_RESOURCE_CPPI_BASE+4)
#define | RM_RESOURCE_CPPI_AIF_RX_CH (RM_RESOURCE_CPPI_BASE+5)
#define | RM_RESOURCE_CPPI_AIF_FLOW (RM_RESOURCE_CPPI_BASE+6)
#define | RM_RESOURCE_CPPI_FFTC_A_TX_CH (RM_RESOURCE_CPPI_BASE+7)
#define | RM_RESOURCE_CPPI_FFTC_A_RX_CH (RM_RESOURCE_CPPI_BASE+8)
#define | RM_RESOURCE_CPPI_FFTC_A_FLOW (RM_RESOURCE_CPPI_BASE+9)
#define | RM_RESOURCE_CPPI_FFTC_B_TX_CH (RM_RESOURCE_CPPI_BASE+10)
#define | RM_RESOURCE_CPPI_FFTC_B_RX_CH (RM_RESOURCE_CPPI_BASE+11)
#define | RM_RESOURCE_CPPI_FFTC_B_FLOW (RM_RESOURCE_CPPI_BASE+12)
#define | RM_RESOURCE_CPPI_PASS_TX_CH (RM_RESOURCE_CPPI_BASE+13)
#define | RM_RESOURCE_CPPI_PASS_RX_CH (RM_RESOURCE_CPPI_BASE+14)
#define | RM_RESOURCE_CPPI_PASS_FLOW (RM_RESOURCE_CPPI_BASE+15)
#define | RM_RESOURCE_CPPI_QMSS_TX_CH (RM_RESOURCE_CPPI_BASE+16)
#define | RM_RESOURCE_CPPI_QMSS_RX_CH (RM_RESOURCE_CPPI_BASE+17)
#define | RM_RESOURCE_CPPI_QMSS_FLOW (RM_RESOURCE_CPPI_BASE+18)
#define | RM_RESOURCE_CPPI_FFTC_C_TX_CH (RM_RESOURCE_CPPI_BASE+19)
#define | RM_RESOURCE_CPPI_FFTC_C_RX_CH (RM_RESOURCE_CPPI_BASE+20)
#define | RM_RESOURCE_CPPI_FFTC_C_FLOW (RM_RESOURCE_CPPI_BASE+21)
#define | RM_RESOURCE_CPPI_BCP_TX_CH (RM_RESOURCE_CPPI_BASE+22)
#define | RM_RESOURCE_CPPI_BCP_RX_CH (RM_RESOURCE_CPPI_BASE+23)
#define | RM_RESOURCE_CPPI_BCP_FLOW (RM_RESOURCE_CPPI_BASE+24)
#define | RM_RESOURCE_PA_BASE 128
#define | RM_RESOURCE_PA_FIRMWARE (RM_RESOURCE_PA_BASE+1)
#define | RM_RESOURCE_PA_LUT_ENTRY (RM_RESOURCE_PA_BASE+2)
#define | RM_RESOURCE_PERM_DENIED 0x0
#define | RM_RESOURCE_PERM_ALLOWED 0x1
#define | RM_RESOURCE_FLAG_DSP_SHIFT(dspNum, perms) (((uint32_t) perms) << dspNum)
#define | RM_RESOURCE_ALL_DSPS_FULL_PERMS

## Variables

const Rm_Resource | rmResourceTable []
| RM LLD resource table permissions Must be cache line aligned.

## Define Documentation

#define RM_RESOURCE_ALL_DSPS_FULL_PERMS

Value:

    ((RM_RESOURCE_FLAG_DSP_SHIFT(0, RM_RESOURCE_PERM_ALLOWED)) | \
                            (RM_RESOURCE_FLAG_DSP_SHIFT(1, RM_RESOURCE_PERM_ALLOWED)) | \
                            (RM_RESOURCE_FLAG_DSP_SHIFT(2, RM_RESOURCE_PERM_ALLOWED)) | \
                            (RM_RESOURCE_FLAG_DSP_SHIFT(3, RM_RESOURCE_PERM_ALLOWED)))

Full Permissions - All DSPs can use and initialize resource

#define RM_RESOURCE_CPPI_AIF_FLOW (RM_RESOURCE_CPPI_BASE+6)

CPPI AIF flow

#define RM_RESOURCE_CPPI_AIF_RX_CH (RM_RESOURCE_CPPI_BASE+5)

CPPI AIF receive channel

#define RM_RESOURCE_CPPI_AIF_TX_CH (RM_RESOURCE_CPPI_BASE+4)

CPPI AIF transmit channel

#define RM_RESOURCE_CPPI_BASE 64

Start of CPPI resource identifiers

#define RM_RESOURCE_CPPI_BCP_FLOW (RM_RESOURCE_CPPI_BASE+24)

CPPI BCP flow

#define RM_RESOURCE_CPPI_BCP_RX_CH (RM_RESOURCE_CPPI_BASE+23)

CPPI BCP receive channel

#define RM_RESOURCE_CPPI_BCP_TX_CH (RM_RESOURCE_CPPI_BASE+22)

CPPI BCP transmit channel

#define RM_RESOURCE_CPPI_FFTC_A_FLOW (RM_RESOURCE_CPPI_BASE+9)

CPPI FFTC_A flow

#define RM_RESOURCE_CPPI_FFTC_A_RX_CH (RM_RESOURCE_CPPI_BASE+8)

CPPI FFTC_A receive channel

#define RM_RESOURCE_CPPI_FFTC_A_TX_CH (RM_RESOURCE_CPPI_BASE+7)

CPPI FFTC_A transmit channel

#define RM_RESOURCE_CPPI_FFTC_B_FLOW (RM_RESOURCE_CPPI_BASE+12)

CPPI FFTC_B flow

#define RM_RESOURCE_CPPI_FFTC_B_RX_CH (RM_RESOURCE_CPPI_BASE+11)

CPPI FFTC_B receive channel

#define RM_RESOURCE_CPPI_FFTC_B_TX_CH (RM_RESOURCE_CPPI_BASE+10)

CPPI FFTC_B transmit channel

#define RM_RESOURCE_CPPI_FFTC_C_FLOW (RM_RESOURCE_CPPI_BASE+21)

CPPI FFTC_C flow

#define RM_RESOURCE_CPPI_FFTC_C_RX_CH (RM_RESOURCE_CPPI_BASE+20)

CPPI FFTC_C receive channel

#define RM_RESOURCE_CPPI_FFTC_C_TX_CH (RM_RESOURCE_CPPI_BASE+19)

CPPI FFTC_C transmit channel

#define RM_RESOURCE_CPPI_PASS_FLOW (RM_RESOURCE_CPPI_BASE+15)

CPPI PASS flow

#define RM_RESOURCE_CPPI_PASS_RX_CH (RM_RESOURCE_CPPI_BASE+14)

CPPI PASS receive channel

#define RM_RESOURCE_CPPI_PASS_TX_CH (RM_RESOURCE_CPPI_BASE+13)

CPPI PASS transmit channel

#define RM_RESOURCE_CPPI_QMSS_FLOW (RM_RESOURCE_CPPI_BASE+18)

CPPI QMSS flow

#define RM_RESOURCE_CPPI_QMSS_RX_CH (RM_RESOURCE_CPPI_BASE+17)

CPPI QMSS receive channel

#define RM_RESOURCE_CPPI_QMSS_TX_CH (RM_RESOURCE_CPPI_BASE+16)

CPPI QMSS transmit channel

#define RM_RESOURCE_CPPI_SRIO_FLOW (RM_RESOURCE_CPPI_BASE+3)

CPPI SRIO flow

#define RM_RESOURCE_CPPI_SRIO_RX_CH (RM_RESOURCE_CPPI_BASE+2)

CPPI SRIO receive channel

#define RM_RESOURCE_CPPI_SRIO_TX_CH (RM_RESOURCE_CPPI_BASE+1)

CPPI SRIO transmit channel

#define RM_RESOURCE_FINAL_ENTRY (0xFFFFFFFF)

This value should be last entry in the resource table. Used by RM to find last entry in resource table.

#define RM_RESOURCE_FLAG_DSP_SHIFT | ( | dspNum,
|  | perms |  | ) | (((uint32_t) perms) << dspNum)

Resource entry flags bitfield DSP shift macro

#define RM_RESOURCE_MAGIC_NUMBER (0x76543210)

RM LLD Resource Table Resource Identifiers This value should be first entry in the resource table. Used to verify RM can read the resource table.

#define RM_RESOURCE_PA_BASE 128

Start of CPPI resource identifiers

#define RM_RESOURCE_PA_FIRMWARE (RM_RESOURCE_PA_BASE+1)

PA Firmware write permissions

#define RM_RESOURCE_PA_LUT_ENTRY (RM_RESOURCE_PA_BASE+2)

PA look-up table entry

#define RM_RESOURCE_PERM_ALLOWED 0x1

Init or use permission denied

#define RM_RESOURCE_PERM_DENIED 0x0

RM LLD Resource Table Permission Codes Init or use permission allowed

#define RM_RESOURCE_QMSS_ACCUMULATOR_CH (RM_RESOURCE_QMSS_BASE+6)

QMSS accumulator channels

#define RM_RESOURCE_QMSS_BASE 0

Start of QMSS resource identifiers

#define RM_RESOURCE_QMSS_FIRMWARE_PDSP (RM_RESOURCE_QMSS_BASE+1)

QMSS Firmware PDSP write permissions

#define RM_RESOURCE_QMSS_LINKING_RAM (RM_RESOURCE_QMSS_BASE+5)

QMSS Linking RAM indices

#define RM_RESOURCE_QMSS_LINKING_RAM_CONTROL (RM_RESOURCE_QMSS_BASE+4)

QMSS Linking RAM Control

#define RM_RESOURCE_QMSS_MEMORY_REGION (RM_RESOURCE_QMSS_BASE+3)

QMSS Memory regions

#define RM_RESOURCE_QMSS_QOS_CLUSTER (RM_RESOURCE_QMSS_BASE+8)

QMSS QOS clusters

#define RM_RESOURCE_QMSS_QOS_PDSP_TIMER (RM_RESOURCE_QMSS_BASE+7)

QMSS QOS PDSP timer

#define RM_RESOURCE_QMSS_QOS_QUEUE (RM_RESOURCE_QMSS_BASE+9)

QMSS QOS queues

#define RM_RESOURCE_QMSS_QUEUE (RM_RESOURCE_QMSS_BASE+2)

QMSS queues. This identifier will be expanded to identify all queue types in the near future

Copyright 2012, Texas Instruments Incorporated