# Cppi_CpDmaInitCfg Struct Reference
[CPPI Low Level Driver Data Structures]

CPPI CPDMA configuration structure. More...

`#include <cppi_drv.h>`

## Data Fields

Cppi_CpDma | dmaNum
uint8_t | writeFifoDepth
uint16_t | timeoutCount
volatile uint32_t | qm0BaseAddress
volatile uint32_t | qm1BaseAddress
volatile uint32_t | qm2BaseAddress
volatile uint32_t | qm3BaseAddress

## Detailed Description

CPPI CPDMA configuration structure.

## Field Documentation

Cppi_CpDma Cppi_CpDmaInitCfg::dmaNum

CPDMA configuring control registers

volatile uint32_t Cppi_CpDmaInitCfg::qm0BaseAddress

The QM N Queues Region Base Address Register is used to provide a programmable pointer to the base address of the queues region in Queue Manager N in the system Queue Manager 0 base address register

volatile uint32_t Cppi_CpDmaInitCfg::qm1BaseAddress

Queue Manager 1 base address register

volatile uint32_t Cppi_CpDmaInitCfg::qm2BaseAddress

Queue Manager 2 base address register

volatile uint32_t Cppi_CpDmaInitCfg::qm3BaseAddress

Queue Manager 3 base address register

uint16_t Cppi_CpDmaInitCfg::timeoutCount

This field sets the timeout duration in clock cycles. This field controls the minimum amount of time that an Rx channel will be required to wait when it encounters a buffer starvation condition and the Rx error handling bit is set to 1 (packet is to be preserved - no discard). If the Rx error handling bit in the flow table is cleared, this field will have no effect on the Rx operation. When this field is set to 0, the Rx engine will not force an Rx channel to wait after encountering a starvation event (the feature is disabled). When this field is set to a value other than 0, the Rx engine will force any channel whose associated flow had the Rx error handling bit asserted and which encounters starvation to wait for at least the specified # of clock cycles before coming into context again to retry the access to the QM

uint8_t Cppi_CpDmaInitCfg::writeFifoDepth

This field sets the depth of the write arbitration FIFO which stores write transaction information between the command arbiter and write data arbiters in the Bus Interface Unit. Setting this field to smaller values will cause prevent the CDMAHP from having an excess of write transactions outstanding whose data is still waiting to be transferred. System performance can suffer if write commands are allowed to be issued long before the corresponding write data will be transferred. This field allows the command count to be optimized based on system dynamics

Valid range is 1 to 32. If writeFifoDepth field is set to 0, this field will not be configured. The reset/default value is 20.

The documentation for this struct was generated from the following file:

- cppi_drv.h

Copyright 2012, Texas Instruments Incorporated