# hyperlink Low Level Driver

### 1.0.1.5

## Introduction

The Hyperlink peripheral has also been known as vUSR and MCM. Some chip-specific definitions in CSL and documentation may have references to the old names.

The Hyperlink peripheral provides a high-speed, low-latency, and low-power point-to-point link between two KeyStone devices.

There is a userguide <http://www.ti.com/lit/sprugw8>.

The HyperLink provides three basic functionalities between two devices:

1. There is a memory mapped window on the local device which can be mapped by the remote device. This is the top part of the diagram below.
2. There is a mapping functionality in the receive direction which allows the incoming addresses to be mapped across the device's memory space. This is the bottom part of the diagram below
3. There is the ability to send events (which can trigger hardware such as the EDMA or produce interrupts).
4. Finally there is an ability to bootload the secondary device. See <http://www.ti.com/lit/sprugy5>.

The primary APIs are:
-- Hyplnk_open : Opens the driver (by pointing to the peripheral's base address)
-- Hyplnk_readRegs : Reads one or more registers or tables
-- Hyplnk_writeRegs : Writes one or more registers or tables
-- Hyplnk_close : Close the driver instance (NOP since no memory is used by the driver)
-- Hyplnk_getWindow : Get the base address of the memory window used to access remote device

The normal sequence of events to enable peripheral are below. There is a C code example in ti/drv/hyplnk/example/memoryMappedExample.

1. Set up the system PLL (in the example, this is done via ti/drv/hyplnk/example/board_setup.gel)
2. Enable the power domain for the peripheral via the CSL_PSC_enablePowerDomain() CSL_PSC_setModuleNextState() and CSL_PSC_startStateTransition. This sequence is in the example in function hyplnkExampleSysSetup().
3. Set up the SERDES configuration in CSL_BootCfgSetVUSRConfigPLL, CSL_BootCfgSetVUSRRxConfig, and CSL_BootCfgSetVUSRTxConfig.
4. Confirm that the power is enabled by reading the revision register hyplnkRevReg_s.
5. Enable the peripherial via the control register hyplnkControlReg_s
6. The peripheral is ready when hyplnkStatusReg_s::pllUnlock becomes 0, the hyplnkStatusReg_s::link becomes 1. Since both endpoints of the HyperLink must perform the synchronization, busywaiting as in the example may not be applicable. Once the peripheral is up, one of the two endpoints can program the communication for both since both the local and remote registers are available to both sides.
7. The errors in hyplnkStatusReg_s::lError, hyplnkStatusReg_s::rError, and in hyplnkECCErrorsReg_s should not occur. These indicate problems with the link. Troubleshooting can involve reducing the link speed via the SERDES registers in the boot config peripheral.

Once the link is up, both devices can see each other's peripheral registers. Thus, each device can program its own parameters, or one can act as a master and control both device's parameters.

The following actions are generally taken to set up the logical connection once the link is established

1. Use hyplnkRegisters_s::TXAddrOvly and hyplnkRegisters_s::RXAddrSel to specify the agreed address encoding between the two devices.
2. Use hyplnkRegisters_s::RXPrivIDTbl and hyplnkRegisters_s::RXSegTbl to specify the address decoding.
3. Use hyplnkRegisters_s::intCtrlTbl and hyplnkRegisters_s::intPtrTbl to specify event/interrupt configuration (consider hyplnkControlReg_s::int2cfg).

Once the local memory window is identified by Hyplnk_getWindow, the remote device can be read/written via this memory window using any master (direct CPU access (memcpy), peripherals, or DMA (EDMA).

Copyright 2012, Texas Instruments Incorporated