# pcieBistReg_s Struct Reference
[PCIE LLD Type0 (endpoint) Register Definitions]

Specification of the BIST Header Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint8_t | bistCap
| [ro] Bist capability
uint8_t | startBist
| [ro] Start Bist
uint8_t | compCode
| [ro] Completion code
uint8_t | mulfunDev
| [ro] Multifunction device
uint8_t | hdrType
| [ro] Header type
uint8_t | latTmr
| [ro] Not applicable in PCIe
uint8_t | cacheLnSize
| [ro] Not applicable in PCIe

## Detailed Description

Specification of the BIST Header Register.

## Field Documentation

uint8_t pcieBistReg_s::bistCap

[ro] Bist capability

Returns a one for BIST capability and zero otherwise. Not supported by PCIESS.

Field size: 1 bit

uint8_t pcieBistReg_s::cacheLnSize

[ro] Not applicable in PCIe

Field size: 8 bits

uint8_t pcieBistReg_s::compCode

[ro] Completion code

Not supported by PCIESS.

Field size: 4 bits

uint8_t pcieBistReg_s::hdrType

[ro] Header type

Configuration header format.

0 = EP mode
1 = RC mode

Field size: 7 bits

uint8_t pcieBistReg_s::latTmr

[ro] Not applicable in PCIe

Field size: 8 bits

uint8_t pcieBistReg_s::mulfunDev

[ro] Multifunction device

Field size: 1 bit

uint8_t pcieBistReg_s::startBist

[ro] Start Bist

Write a one to start BIST. Not supported by PCIESS.

Field size: 1 bit

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated