# pciePmCfgReg_s Struct Reference
[PCIE LLD Application Register Definitions]

Specification of the Power Management Configuration Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
| [ro] Raw image of register on read; actual value on write
uint8_t | entrL23
| [rw] PM Turn off

## Detailed Description

Specification of the Power Management Configuration Register.

## Field Documentation

uint8_t pciePmCfgReg_s::entrL23

[rw] PM Turn off

Write 1 to enable entry to L2/L3 ready state. Read to check L2/L3 entry readiness. Applicable to RC and EP.

0 = Disable entry to L2/L3 ready state.
1 = Enable entry to L2/L3 ready state.

Field size: 1 bit

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated