# pcieSlotCapReg_s Struct Reference
[PCIE LLD Capabilities Register Definitions]

Specification of the Slot Capabilities register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
uint16_t | slotNum
| [rw] Physical Slot Number.
uint8_t | cmdCompSupp
| [rw] No Command Complete Support
uint8_t | emlPresent
| [rw] Electromechanical Interlock Present.
uint8_t | pwrLmtScale
| [rw] Slot Power Limit Scale.
uint8_t | pwrLmtValue
| [rw] Slot Power Limit Value.
uint8_t | hpCap
| [rw] Hot Plug Capable.
uint8_t | hpSurprise
| [rw] Hot Plug Surprise.
uint8_t | pwrInd
| [rw] Power Indicator Present.
uint8_t | attnInd
| [rw] Attention Indicator Present.
uint8_t | mrlSensor
| [rw] MRL Sensor Present.
uint8_t | pwrCtl
| [rw] Power Controller Present.
uint8_t | attnButton
| [rw] Attention Indicator Present.

## Detailed Description

Specification of the Slot Capabilities register.

This register may only be used for root complex mode.

## Field Documentation

uint8_t pcieSlotCapReg_s::attnButton

[rw] Attention Indicator Present.

Field size: 1 bit

uint8_t pcieSlotCapReg_s::attnInd

[rw] Attention Indicator Present.

Field size: 1 bit

uint8_t pcieSlotCapReg_s::cmdCompSupp

[rw] No Command Complete Support

When Set, this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller

Field size: 1 bit

uint8_t pcieSlotCapReg_s::emlPresent

[rw] Electromechanical Interlock Present.

When Set, this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot.

Field size: 1 bit

uint8_t pcieSlotCapReg_s::hpCap

[rw] Hot Plug Capable.

Field size: 1 bit

uint8_t pcieSlotCapReg_s::hpSurprise

[rw] Hot Plug Surprise.

Field size: 1 bit

uint8_t pcieSlotCapReg_s::mrlSensor

[rw] MRL Sensor Present.

Field size: 1 bit

uint8_t pcieSlotCapReg_s::pwrCtl

[rw] Power Controller Present.

If there is no power controller, software must ensure that system power is up before reading Presence Detect state

Field size: 1 bit

uint8_t pcieSlotCapReg_s::pwrInd

[rw] Power Indicator Present.

Field size: 1 bit

uint8_t pcieSlotCapReg_s::pwrLmtScale

[rw] Slot Power Limit Scale.

Field size: 2 bits

uint8_t pcieSlotCapReg_s::pwrLmtValue

[rw] Slot Power Limit Value.

Field size: 8 bits

uint32_t pcieSlotCapReg_s::raw

[ro] Raw image of register on read; actual value on write

uint16_t pcieSlotCapReg_s::slotNum

[rw] Physical Slot Number.

Field size: 13 bits [0-0x1FFF]

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated