# pcieMsiIrqEnableClrReg_s Struct Reference
[PCIE LLD Application Register Definitions]

Specification of the MSI Interrupt Enable Clear Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
uint8_t | msiIrqEnClr
| [rw] Each bit, when written to, disables the MSI interrupt (24, 16, 8, 0) associated with the bit

## Detailed Description

Specification of the MSI Interrupt Enable Clear Register.

There are multiple instances (0-7) of this register.

## Field Documentation

uint8_t pcieMsiIrqEnableClrReg_s::msiIrqEnClr

[rw] Each bit, when written to, disables the MSI interrupt (24, 16, 8, 0) associated with the bit

Field size: 4 bits

uint32_t pcieMsiIrqEnableClrReg_s::raw

[ro] Raw image of register on read; actual value on write

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated