/*                      L                                                    */
/* Function    : dsp status report to its internal memory                   */

#include  "windef.h"
#include  "mbdr_dsp_common_descriptors.h"
#include  "mbdr_dsp_sw_version.h"
#include  "mbdr_dsp_exceptions_number.h"
#include  "mbdr_dsp_numbers.h"

#ifndef  _MBDR_DSP_COMMON_STATUS_H
#define  _MBDR_DSP_COMMON_STATUS_H



typedef struct _mbdr_dsp_common_status_t
{
                                   /* information                           */
 ULONG exception_history_sticky_flags[MBDR_DSP_EXCEPTIONS_NUMBER/MBDR_DSP_32]; /*0..7*/
 mbdr_dsp_exception_descriptor_t last_exception;                     /*11.8*/
 volatile mbdr_dsp_common_sw_module_code_t sw_module_code;
 UCHAR poll_pci_transmit_f;  /* waits for pci transmitter free              */
 UCHAR poll_get_reply_f;     /* waits for get reply                         */
 USHORT spare_0          ;   /* sub      "     "    "    "  "     "      "  */
 ULONG dsp_clock_mhz_q16 ;   /* 14 */
 ULONG last_exception_toa_for_monitor ;    /* 15 */
 ULONG exception_record_cyclic_write_index;/* 16 */
 ULONG application_general_debug;          /* 17 */
 ULONG spare[8];                           /* 18..25 */
 ULONG boot_loader_version_from_application; /* 26     */
 ULONG boot_loader_version_from_boot;        /* 27     */
 mbdr_dsp_sw_version_t dsp_sw_version;       /* 28, 29 */
 ULONG expected_add_checksum;/*30  ADD checksum as computed by external tool */
 ULONG boot_loader_add_checksum;/*31   "      "    "      "    "  boot loader   */
                             /*    up to read data from flash                */
}mbdr_dsp_common_status_t;

/* mbdr dsp common status */
extern mbdr_dsp_common_status_t mbdr_dsp_common_status[1];


enum MBDR_DSP_MAIN_MODULE_CODE_T{
                  MBDR_DSP_MAIN_MODULE_CODE_T_BOOT_LOADER_START=1,
                  MBDR_DSP_MAIN_MODULE_CODE_T_BOOT_LOADER_AFTER_SYNC_WITH_CPU,
                  MBDR_DSP_MAIN_MODULE_CODE_T_BOOT_LOADER_AFTER_COPY_FROM_FLASH,
                  MBDR_DSP_MAIN_MODULE_CODE_T_BOOT_LOADER_FINISH,
                  MBDR_DSP_MAIN_MODULE_CODE_T_MAIN_START,
                  MBDR_DSP_MAIN_MODULE_CODE_T_MAIN_GOT_MAGIC_WORD,
                  MBDR_DSP_MAIN_MODULE_CODE_T_MAIN_AFTER_SYNC_WITH_CPU,
                  MBDR_DSP_MAIN_MODULE_CODE_T_FATAL_EXCEPTION_WAIT_FOREVER,
                  MBDR_DSP_MAIN_MODULE_CODE_T_MAIN_LOOP,
                  MBDR_DSP_MAIN_MODULE_CODE_T_MAIN_LOOP_HOOK,
                  MBDR_DSP_MAIN_MODULE_CODE_T_SPOT_HANDLER,
                  MBDR_DSP_MAIN_MODULE_CODE_T_FIR_HANDLER,
                  MBDR_DSP_MAIN_MODULE_CODE_T_FINE_HANDLER,
                  MBDR_DSP_MAIN_MODULE_CODE_T_BOOT_LOADER_CHECKSUM_FAULT,
                  MBDR_DSP_MAIN_MODULE_CODE_T_EXTRA_IF_PROCESS_HANDLER,
                  MBDR_DSP_MAIN_MODULE_CODE_T_MAIN_BOOT_LOADER_VERSION_MISMATCH};

#define MBDR_DSP_SET_SW_MAIN_MODULE_CODE_M(pi_sw_main_module_code)\
   mbdr_dsp_common_status[0].sw_module_code.sub_module = 0;\
   mbdr_dsp_common_status[0].sw_module_code.middle = 0;\
   mbdr_dsp_common_status[0].sw_module_code.main   = pi_sw_main_module_code

#define MBDR_DSP_SET_SW_ALL_MODULE_CODE_M(PI_SW_MODULE_CODE)\
		 mbdr_dsp_common_status[0].sw_module_code = PI_SW_MODULE_CODE

/*the macro set sub module to be zero				*/
/*and update middle field to be current code section*/
#define MBDR_DSP_SET_MIDDLE_MODULE_CODE_STATUS_M(pi_sw_middle_module_code)\
   mbdr_dsp_common_status[0].sw_module_code.sub_module = 0;\
   mbdr_dsp_common_status[0].sw_module_code.middle = pi_sw_middle_module_code

#define MBDR_DSP_SET_SUB_MODULE_CODE_STATUS_M(pi_sw_sub_module_code)\
   mbdr_dsp_common_status[0].sw_module_code.sub_module = pi_sw_sub_module_code

#define MBDR_DSP_SET_SW_MODULE_STATE_CODE_M(pi_sw_module_code_state_machine)\
   mbdr_dsp_common_status[0].sw_module_code.state_machine   = pi_sw_module_code_state_machine

enum MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T{
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_START_WITHIN_ANT_STEP=1,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_EVENTS_HANDLE,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_CHECK_EXTENSION_INDICATION,
		MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_IF_BAND,
		MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_SPURIOUS_REJECT,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_MDFT,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_HISTOGRAM,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_DROP_REDUNDANT,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_PROCESS_END,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_MANAGER_START,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_MANAGER_WHILE,
        MBDR_DSP_SPOT_HANDLER_MIDDLE_MODULE_CODE_T_BITCAL};

enum MBDR_DSP_FIR_HANDLER_MIDDLE_MODULE_CODE_T{
        MBDR_DSP_FIR_HANDLER_MIDDLE_MODULE_CODE_T_FIR_WRITE=1,
        MBDR_DSP_FIR_HANDLER_MIDDLE_MODULE_CODE_T_FIR_SCOPE_OUTPUT};



enum MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T{
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_MAIN_START=1,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC1_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC1_SEARCH_OVER_TRESHOLD,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC1_SEARCH_FALL,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC1_SEARCH_PEAK_POWER,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC1_SEARCH_RISING_EDGE,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC1_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC2_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC2_SEARCH_TOE,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC2_COMPUTE_FREQUENCY,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_CALC2_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PLS_MAIN_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_MAIN_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_MAIN_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_FIR_OPERATE_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_FIR_OPERATE_SEND,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_FIR_OPERATE_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_FIR_SEND_SPOT_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_FIR_SEND_SPOT_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PCI_SEND,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_MANAGER_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_MANAGER_WHILE,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_BEFORE_FIR,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_AFTER_FIR,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_CALC1_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_CALC1_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_CALC2_START,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_CALC2_END,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_CALC2_COMPUTE_FREQUENCY,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_MOP_PLS_MAIN,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_MOP_PLS_KERNEL,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_CW_S_MDFT,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_BITCAL};


enum MBDR_DSP_CW_SEPARATION_SUB_MODULE_CODE_T{
  MBDR_DSP_CW_SEPARATION_SUB_MODULE_CODE_T_=1,
   MBDR_DSP_FINE_HANDLER_MIDDLE_MODULE_CODE_T_PHASE_CORRECTION};

enum MBDR_DSP_EXTRA_IF_PROCESS_HANDLER_MIDDLE_MODULE_CODE_T{
        MBDR_DSP_EXTRA_IF_PROCESS_HANDLER_MIDDLE_MODULE_CODE_T_WRITE=1,
        MBDR_DSP_EXTRA_IF_PROCESS_HANDLER_MIDDLE_MODULE_CODE_T_SCOPE_OUTPUT};



#define MBDR_DSP_SW_MODULE_STATE_CODE_NOT_SET 0x33

#endif
