/*                                                                          */

#define DSP_6657_BOOT_SEQUENCE_START_ADDRESS_BYTE_OFFSET 0x0072DC0
#define DSP_6657_BOOT_SEQUENCE_END_ADDRESS_BYTE_OFFSET   0x007ffff
#define DSP_6657_BOOT_SEQUENCE_DWORD_SIZE\
	              (( DSP_6657_BOOT_SEQUENCE_END_ADDRESS_BYTE_OFFSET\
	                -DSP_6657_BOOT_SEQUENCE_START_ADDRESS_BYTE_OFFSET\
	                +1)/sizeof(LONG))

/* Threshold per BIN table   */
//#pragma DATA_MEM_BANK   (dsp_6657_boot_sequence_memory, 0);
//#pragma DATA_SECTION    (dsp_6657_boot_sequence_memory, ".dsp_6657_boot_sequence_memory_sect");
//LONG     dsp_6657_boot_sequence_memory[DSP_6657_BOOT_SEQUENCE_DWORD_SIZE];




MEMORY 
{
 BOOT_LOADER_LOCATE_STACK  :origin= 0x00800000, len = 0x0020 /* .002K byte       */
 BOOT_LOADER_START_CODE    :origin= 0x00800020, len = 0x0160 /*.375K byte       */
 BOOT_LOADER_ROUTINES:origin= 0x00800180, len = 0x00280  /* .625K byte       */
 BOOT_LOADER_STACK   :origin= 0x00800800, len = 0x000100 /* .25K  byte       */
 SPARE               :origin= 0x00800900, len = 0x0F700 /* 92K byte      */
 BOOT_LOADER_HEADER  :origin= 0x00820000, len = 0x000080 /* .125K byte      */
 IPRAM               :origin= 0x00820080, len = 0x03FF80 /*.5   Mega byte   */

 BOOT_QEQUENCE       :origin= 0x00872DC0, len = 0x0D240 /*.5   Mega byte   */



 IDRAM_LOW           :origin= 0x00880000, len = 0x040000 /* 256   Kbyte */
 HOST_SIMULATION_RAM :origin= 0x008C0000, len = 0x010000 /* 128   Kbyte */
 IDRAM_CPU_INTERFACE_0 :origin= 0x008D0000, len = 0x009800 /*  38   Kbyte */
 IDRAM_CPU_INTERFACE_1 :origin= 0x008D9800, len = 0x000800 /*   2   Kbyte */

 IDRAM_CPU_INTERFACE_APP :origin= 0x008DA000, len = 0x004800 /* 128   Kbyte */
 IDRAM_MONITOR_REPORT:origin= 0x008Dff80, len = 0x000080 /* .125K byte      */
 IDRAM_BUF           :origin= 0x008E0000, len = 0x01FB80 /* 128   Kbyte */

 REPORT_USEFUL_ADDRESS :origin= 0x008FFB80, len = 0x000080 /*0.125K          */
 EXCEPTION_RECORD      :origin= 0x008FFC00, len = 0x000280 /*0.375K          */
 COMMON_STATUS         :origin= 0x008FFE80, len = 0x000080 /*0.125K          */
 CONFIG                :origin= 0x008FFF00, len = 0x000100 /* .125K byte      */
 FLASH                 :origin= 0x64000000, len = 0x400000 /*  8  Mega byte */
 EXTERNAL_RAM_LOW      :origin= 0x80000000, len = 0x100000 /*  1  Mega byte */
 EXTERNAL_RAM_HIGH     :origin= 0x80100000, len = 0x100000 /*  1  Mega byte */
}

SECTIONS
{
  .vectors > IPRAM 
  .text    > IPRAM
  .switch  > IPRAM
  .bss     > IDRAM_LOW
  .cinit   > IDRAM_LOW
  .const   > IDRAM_LOW
  .far     > IDRAM_LOW
  .stack   > IDRAM_LOW
  .cio     > IDRAM_LOW
  .sysmem  > IDRAM_LOW
  .data    > IDRAM_LOW
  .neardata > IDRAM_LOW
  .fardata > IDRAM_LOW
  .rodata > IDRAM_LOW


  .dsp_6657_boot_sequence_memory_sect > BOOT_QEQUENCE
  .dummy_array_sect > IDRAM_LOW

  /* BOOT LOADER code sections with     important order */
  .mbdr_dsp_boot_loader_set_stack_sect      > BOOT_LOADER_LOCATE_STACK

/* temporary override  */
 .mbdr_dsp_boot_loader_sect                   align 0x10   > BOOT_LOADER_START_CODE


  /* -"-   -"-    -"-   -"-    -"- non     -"-     -"-  */
  .mbdr_dsp_boot_loader_routines_sect            align  0x10  > BOOT_LOADER_ROUTINES


  /* BOOT LOADER STACK */
  .mbdr_dsp_boot_loader_stack_sect        align 32 > BOOT_LOADER_STACK

  /* BOOT LOADER HEADER reports int0 address */
  /* .mbdr_dsp_boot_loader_header_sect       align 32 > BOOT_LOADER_HEADER , type = COPY*/
  .mbdr_dsp_boot_loader_header_sect       align 32 > BOOT_LOADER_HEADER

  /* CPU <--> DSP interface */

  .mbdr_dsp_cpu_common_interface_dsp_sect  align 32 > IDRAM_LOW

  /* dsp STATUS  */
  .mbdr_dsp_common_status_sect  > COMMON_STATUS, type = NOINIT

  /* config area */
  .mbdr_dsp_boot_loader_config_sect  > CONFIG

  /* host/tracker/FPGA memory*/ 
  .mbdr_dsp_cpu_common_interface_cpu_sect                   align 0x0100 > EXTERNAL_RAM_LOW



  /* probs memory */
  .mbdr_dsp_read_probs_sect      align 32 > EXTERNAL_RAM_HIGH
  .mbdr_dsp_write_probs_sect     align 32 > EXTERNAL_RAM_HIGH
}
