# CHIP

## Modules

| CHIP Enumerated Data Types
| CHIP Functions

## Detailed Description

## Introduction

### Overview

This module deals with all System On Chip (SOC) configurations. It consists of Configuration Registers specific for the chip. Following are the Registers associated with the CHIP module:

(1) Addressing Mode Register - This register specifies the addressing mode for the registers which can perform linear or circular addressing, also contain sizes for circular addressing

(2) Control Status Register - This register contains the control and status bits. This register is used to control the mode of cache. This is also used to enable or disable all the interrupts except reset and non maskable interrupt.

(3) Interrupt Flag Register - This register contains the status of INT4-INT15 and NMI interrupt. Each corresponding bit in the IFR is set to 1 when that interrupt occurs; otherwise, the bits are cleared to 0.

(4) Interrupt Set Register - This register allows user to manually set the maskable interrupts (INT4-INT15) in the interrupt flag register (IFR). Writing a 1 to any of the bits in ISR causes the corresponding interrupt flag to be set in IFR.

(5) Interrupt Clear Register - This register allows user to manually clear the maskable interrupts (INT15-INT4) in the interrupt flag register (IFR). Writing a 1 to any of the bits in ICR causes the corresponding interrupt flag to be cleared in IFR.

(6) Interrupt Enable Register - This register enables and disables individual interrupts and this not accessible in User mode.

(7) Interrupt Service Table Pointer Register - This register is used to locate the interrupt service routine (ISR).

(8) Interrupt Return Pointer Register - This register contains the return pointer that directs the CPU to the proper location to continue program execution after processing a maskable interrupt.

(9) Nonmaskable Interrupt (NMI) Return Pointer Register - This register contains the return pointer that directs the CPU to the proper location to continue program execution after processing of a non-maskable interrupt (NMI).

(10)Exception Return Pointer Register - This register contains the return pointer that directs the CPU to the proper location to continue program execution after processing of a exception.

(11)Time Stamp Counter Registers - The CPU contains a free running 64-bit counter that advances each CPU clock after counting is enabled. The counter is accessed using two 32-bit read-only control registers, Time Stamp Counter Registers - Low (TSCL) and Time Stamp Counter Registers - High (TSCH). The counter is enabled by writing to TSCL. The value written is ignored. Once enabled, counting cannot be disabled under program control. Counting is disabled in the following cases: a. After exiting the reset state. b. When the CPU is fully powered down.

(12)Analysis Return Pointer

(13)SPLOOP Inner Loop Count Register - The SPLOOP or SPLOOPD instructions use the SPLOOP inner loop count register (ILC), as the count of the number of iterations left to perform. The ILC content is decremented at each stage boundary until the ILC content reaches 0.

(14)SPLOOP Reload Inner Loop Count Register - Predicated SPLOOP or SPLOOPD instructions used in conjunction with a SPMASKR or SPKERNELR instruction use the SPLOOP reload inner loop count register (RILC), as the iteration count value to be written to the SPLOOP inner loop count register (ILC) in the cycle before the reload operation begins.

(15)Restricted Entry Point Address Register - This register is used by the SWENR instruction as the target of the change of control when an SWENR instruction is issued. The contents of REP should be preinitialized by the processor in Supervisor mode before any SWENR instruction is issued.

(16)E1 Phase Program Counter - This register contains the 32-bit address of the fetch packet in the E1 pipeline phase.

(17)DSP Core Number Register - This register provides an identifier to shared resources in the system which identifies which CPU is accessing those resources. The contents of this register are set to a specific value at reset.

(18)Saturation Status Register - This register provides saturation flags for each functional unit, making it possible for the program to distinguish between saturations caused by different instructions in the same execute packet.

(19)GMPY Polynomial.A Side Register - The GMPY instruction uses the 32-bit polynomial in the GMPY polynomial-A side register (GPLYA), when the instruction is executed on the M1 unit.

(20)GMPY Polynomial.B Side Register - The GMPY instruction uses the 32-bit polynomial in the GMPY polynomial-B side register (GPLYB), when the instruction is executed on the M2 unit.

(21)Galois Field Polynomial Generator Function Register - This register controls the field size and the Galois field polynomial generator of the Galois field multiply hardware.

(22)Debug Interrupt Enable Register - This register is used to designate which interrupts and exceptions are treated as high priority interrupts when operating in real-time emulation mode.

(23)Task State Register - This register contains all of the status bits that determine or indicate the current execution environment. TSR is saved in the event of an interrupt or exception to the ITSR or NTSR, respectively.

(24)Interrupt Task State Register - This register is used to store the contents of the task state register (TSR) in the event of an interrupt.

(25)NMI/Exception Task State Register - This register is used to store the contents of the task state register (TSR) and the conditions under which an exception occurred in the event of a nonmaskable interrupt (NMI) or an exception.

(26)Exception Flag Register - This register contains bits that indicate which exceptions have been detected. Clearing the EFR bits is done by writing a 1 to the corresponding bit position in the exception clear register (ECR).

(27)Exception Clear Register - This register is used to clear individual bits in the exception flag register (EFR). Writing a 1 to any bit in ECR clears the corresponding bit in EFR.

(28)Internal Exception Report Register - This register contains flags that indicate the cause of the internal exception.

Copyright 2012, Texas Instruments Incorporated