# pcieLaneSkewReg_s Struct Reference
[PCIE LLD Port Logic Register Definitions]

Specification of the Lane Skew register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
uint8_t | l2Deskew
| [rw] Set to Disable Lane to Lane Deskew.
uint8_t | ackDisable
| [rw] Set to disable Ack and Nak DLLP transmission.
uint8_t | fcDisable
| [rw] Set to disable transmission of Flow Control DLLPs.
uint32_t | laneSkew
| [rw] Insert Lane Skew for Transmit.

## Detailed Description

Specification of the Lane Skew register.

This register may be used for both endpoint and root complex modes.

## Field Documentation

uint8_t pcieLaneSkewReg_s::ackDisable

[rw] Set to disable Ack and Nak DLLP transmission.

Field size: 1 bit

uint8_t pcieLaneSkewReg_s::fcDisable

[rw] Set to disable transmission of Flow Control DLLPs.

Field size: 1 bit

uint8_t pcieLaneSkewReg_s::l2Deskew

[rw] Set to Disable Lane to Lane Deskew.

Field size: 1 bit

uint32_t pcieLaneSkewReg_s::laneSkew

[rw] Insert Lane Skew for Transmit.

The value is in units of one symbol time. Thus a value 0x02 will force a skew of two symbol times for that lane. Max allowed is 5 symbol times. This 24 bit field is used for programming skew for eight lanes with three bits per lane.

Field size: 24 bits

uint32_t pcieLaneSkewReg_s::raw

[ro] Raw image of register on read; actual value on write

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated