# pcieRootCtrlCapReg_s Struct Reference
[PCIE LLD Capabilities Register Definitions]

Specification of the Root Control and Capabilities Register. More...

`#include <pcie.h>`

## Data Fields

uint32_t | raw
uint8_t | crsSw
| [ro] CRS Software Visibility. Not supported and set to 0.
uint8_t | crsSwEn
| [ro] CRS Software Visibility Enable. Not supported and set to 0x0.
uint8_t | pmeIntEn
| [rw] PME Interrupt Enable
uint8_t | serrFatalErr
| [rw] System Error on Fatal Error Enable
uint8_t | serrNFatalErr
| [rw] System Error on Non-fatal Error Enable
uint8_t | serrEn
| [rw] System Error on Correctable Error Enable

## Detailed Description

Specification of the Root Control and Capabilities Register.

This register may only be used for root complex mode.

## Field Documentation

uint8_t pcieRootCtrlCapReg_s::crsSw

[ro] CRS Software Visibility. Not supported and set to 0.

Field size: 1 bit

uint8_t pcieRootCtrlCapReg_s::crsSwEn

[ro] CRS Software Visibility Enable. Not supported and set to 0x0.

Field size: 1 bit

uint8_t pcieRootCtrlCapReg_s::pmeIntEn

[rw] PME Interrupt Enable

Field size: 1 bit

uint32_t pcieRootCtrlCapReg_s::raw

[ro] Raw image of register on read; actual value on write

uint8_t pcieRootCtrlCapReg_s::serrEn

[rw] System Error on Correctable Error Enable

Field size: 1 bit

uint8_t pcieRootCtrlCapReg_s::serrFatalErr

[rw] System Error on Fatal Error Enable

Field size: 1 bit

uint8_t pcieRootCtrlCapReg_s::serrNFatalErr

[rw] System Error on Non-fatal Error Enable

Field size: 1 bit

The documentation for this struct was generated from the following file:

- pcie.h

Copyright 2012, Texas Instruments Incorporated