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MDIO CSL Implementation on DSP side. More...
#include <ti/csl/cslr.h>#include <ti/csl/soc.h>#include <ti/csl/csl_error.h>#include <ti/csl/csl_types.h>#include <ti/csl/cslr_mdio.h>Data Structures | |
| struct | _MDIO_Device |
| MDIO_Device This is the MDIO object that contains the MDIO device object characteristics. More... | |
Defines | |
| #define | DEV_REGS ((CSL_DevRegs *) CSL_DEV_REGS) |
| #define | MDIO_REGS ((CSL_MdioRegs *) CSL_MDIO_0_REGS) |
| #define | PHYREG0_read(regadr, phyadr) |
| #define | PHYREG0_write(regadr, phyadr, data) |
| #define | PHYREG0_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ) |
| #define | PHYREG0_waitResults(results) |
| #define | PHYREG0_waitResultsAck(results, ack) |
| #define | PHYREG1_read(regadr, phyadr) |
| #define | PHYREG1_write(regadr, phyadr, data) |
| #define | PHYREG1_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS1,MDIO_USERACCESS1_GO) ) |
| #define | PHYREG1_waitResults(results) |
| #define | PHYREG1_waitResultsAck(results, ack) |
| #define | MDIO_MODEFLG_AUTONEG 0x0001 |
| #define | MDIO_MODEFLG_HD10 0x0002 |
| #define | MDIO_MODEFLG_FD10 0x0004 |
| #define | MDIO_MODEFLG_HD100 0x0008 |
| #define | MDIO_MODEFLG_FD100 0x0010 |
| #define | MDIO_MODEFLG_FD1000 0x0020 |
| #define | MDIO_MODEFLG_LOOPBACK 0x0040 |
| #define | MDIO_MODEFLG_NWAYACTIVE 0x0080 |
| #define | MDIO_MODEFLG_EXTLOOPBACK 0x0100 |
| #define | MDIO_MODEFLG_SPECPHYADDR 0x0200 |
| #define | MDIO_LINKSTATUS_NOLINK 0 |
| #define | MDIO_LINKSTATUS_HD10 1 |
| #define | MDIO_LINKSTATUS_FD10 2 |
| #define | MDIO_LINKSTATUS_HD100 3 |
| #define | MDIO_LINKSTATUS_FD100 4 |
| #define | MDIO_LINKSTATUS_FD1000 5 |
| #define | MDIO_EVENT_NOCHANGE 0 |
| #define | MDIO_EVENT_LINKDOWN 1 |
| #define | MDIO_EVENT_LINKUP 2 |
| #define | MDIO_EVENT_PHYERROR 3 |
| #define | MDIO_ERROR_INVALID 1 |
| Standard Error Codes. | |
| #define | VBUSCLK 165 |
| #define | PHYREG_CONTROL 0 |
| #define | PHYREG_CONTROL_RESET (1<<15) |
| #define | PHYREG_CONTROL_LOOPBACK (1<<14) |
| #define | PHYREG_CONTROL_SPEEDLSB (1<<13) |
| #define | PHYREG_CONTROL_AUTONEGEN (1<<12) |
| #define | PHYREG_CONTROL_POWERDOWN (1<<11) |
| #define | PHYREG_CONTROL_ISOLATE (1<<10) |
| #define | PHYREG_CONTROL_AUTORESTART (1<<9) |
| #define | PHYREG_CONTROL_DUPLEXFULL (1<<8) |
| #define | PHYREG_CONTROL_SPEEDMSB (1<<6) |
| #define | PHYREG_STATUS 1 |
| #define | PHYREG_STATUS_FD100 (1<<14) |
| #define | PHYREG_STATUS_HD100 (1<<13) |
| #define | PHYREG_STATUS_FD10 (1<<12) |
| #define | PHYREG_STATUS_HD10 (1<<11) |
| #define | PHYREG_STATUS_EXTSTATUS (1<<8) |
| #define | PHYREG_STATUS_NOPREAMBLE (1<<6) |
| #define | PHYREG_STATUS_AUTOCOMPLETE (1<<5) |
| #define | PHYREG_STATUS_REMOTEFAULT (1<<4) |
| #define | PHYREG_STATUS_AUTOCAPABLE (1<<3) |
| #define | PHYREG_STATUS_LINKSTATUS (1<<2) |
| #define | PHYREG_STATUS_JABBER (1<<1) |
| #define | PHYREG_STATUS_EXTENDED (1<<0) |
| #define | PHYREG_ID1 2 |
| #define | PHYREG_ID2 3 |
| #define | PHYREG_ADVERTISE 4 |
| #define | PHYREG_ADVERTISE_NEXTPAGE (1<<15) |
| #define | PHYREG_ADVERTISE_FAULT (1<<13) |
| #define | PHYREG_ADVERTISE_PAUSE (1<<10) |
| #define | PHYREG_ADVERTISE_FD100 (1<<8) |
| #define | PHYREG_ADVERTISE_HD100 (1<<7) |
| #define | PHYREG_ADVERTISE_FD10 (1<<6) |
| #define | PHYREG_ADVERTISE_HD10 (1<<5) |
| #define | PHYREG_ADVERTISE_MSGMASK (0x1F) |
| #define | PHYREG_ADVERTISE_MSG (1) |
| #define | PHYREG_PARTNER 5 |
| #define | PHYREG_PARTNER_NEXTPAGE (1<<15) |
| #define | PHYREG_PARTNER_ACK (1<<14) |
| #define | PHYREG_PARTNER_FAULT (1<<13) |
| #define | PHYREG_PARTNER_PAUSE (1<<10) |
| #define | PHYREG_PARTNER_FD100 (1<<8) |
| #define | PHYREG_PARTNER_HD100 (1<<7) |
| #define | PHYREG_PARTNER_FD10 (1<<6) |
| #define | PHYREG_PARTNER_HD10 (1<<5) |
| #define | PHYREG_PARTNER_MSGMASK (0x1F) |
| #define | PHYREG_1000CONTROL 9 |
| #define | PHYREG_ADVERTISE_FD1000 (1<<9) |
| #define | PHYREG_1000STATUS 0xA |
| #define | PHYREG_PARTNER_FD1000 (1<<11) |
| #define | PHYREG_EXTSTATUS 0x0F |
| #define | PHYREG_EXTSTATUS_FD1000 (1<<13) |
| #define | PHYREG_SHADOW 0x18 |
| #define | PHYREG_SHADOW_EXTLOOPBACK 0x8400 |
| #define | PHYREG_SHADOW_RGMIIMODE 0xF080 |
| #define | PHYREG_SHADOW_INBAND 0xF1C7 |
| #define | PHYREG_ACCESS 0x1C |
| #define | PHYREG_ACCESS_COPPER 0xFC00 |
| #define | PHYSTATE_MDIOINIT 0 |
| #define | PHYSTATE_RESET 1 |
| #define | PHYSTATE_NWAYSTART 2 |
| #define | PHYSTATE_NWAYWAIT 3 |
| #define | PHYSTATE_LINKWAIT 4 |
| #define | PHYSTATE_LINKED 5 |
Typedefs | |
| typedef void * | Handle |
| typedef struct _MDIO_Device | MDIO_Device |
| MDIO_Device This is the MDIO object that contains the MDIO device object characteristics. | |
Enumerations | |
| enum | Interface { MII = 0, RMII, GMII, RGMII } |
Interface. More... | |
Functions | |
| Uint32 | MDIO_open (int instNum, Uint32 mdioModeFlags, Uint32 phyAddr, Handle hMDIO) |
| void | MDIO_close (Handle hMDIO) |
| void | MDIO_getStatus (Handle hMDIO, Uint32 *pPhy, Uint32 *pLinkStatus) |
| Uint32 | MDIO_timerTick (Handle hMDIO) |
| Uint32 | MDIO_initPHY (Handle hMDIO, Uint32 phyAddr) |
| Uint32 | MDIO_phyRegRead (Uint32 phyIdx, Uint32 phyReg, Uint16 *pData) |
| Uint32 | MDIO_phyRegWrite (Uint32 phyIdx, Uint32 phyReg, Uint16 data) |
MDIO CSL Implementation on DSP side.
============================================================================
PATH: $(CSLPATH)\inc
| #define DEV_REGS ((CSL_DevRegs *) CSL_DEV_REGS) |
Base address of device registers
| #define MDIO_REGS ((CSL_MdioRegs *) CSL_MDIO_0_REGS) |
Base address of MDIO registers
| typedef void* Handle |
Constants, Objects and interfaces for MDIO Void pointer type defined for MDIO