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| #define CSL_EMAC_NUMCHANNELS 8 |
Number of Tx/Rx channels
| #define CSL_EMAC_NUMCORES 1 |
Number of cores
| #define CSL_EMAC_NUMMACADDRS 32 |
Number of MAC addresses supported
| #define EMAC_CONFIG_MODEFLAG_GIGFORCE 0x100000 |
Set gigabit force mode
| #define EMAC_CONFIG_MODEFLG_CHPRIORITY 0x00001 |
CfgModeFlags Configuration Mode Flags.
Use Tx channel priority
| #define EMAC_CONFIG_MODEFLG_CMDIDLE 0x01000 |
Enable IDLE command
| #define EMAC_CONFIG_MODEFLG_EXTEN 0x80000 |
Set external enable bit
| #define EMAC_CONFIG_MODEFLG_FULLDUPLEX 0x20000 |
Set full duplex mode
| #define EMAC_CONFIG_MODEFLG_GIGABIT 0x40000 |
Set gigabit
| #define EMAC_CONFIG_MODEFLG_GMIIEN 0x800000 |
Set GMII mode
| #define EMAC_CONFIG_MODEFLG_MACLOOPBACK 0x00002 |
MAC internal loopback
| #define EMAC_CONFIG_MODEFLG_PASSALL 0x00040 |
pass all frames
| #define EMAC_CONFIG_MODEFLG_PASSCONTROL 0x00020 |
Pass control frames
| #define EMAC_CONFIG_MODEFLG_PASSERROR 0x00010 |
Pass error frames
| #define EMAC_CONFIG_MODEFLG_RXBUFFERFLOWCNTL 0x10000 |
Enable rx buffer flow control
| #define EMAC_CONFIG_MODEFLG_RXCRC 0x00004 |
Include CRC in RX frames
| #define EMAC_CONFIG_MODEFLG_RXFIFOFLOWCNTL 0x00800 |
Enable rx fifo flow control
| #define EMAC_CONFIG_MODEFLG_RXNOCHAIN 0x00100 |
Select no buffer chaining
| #define EMAC_CONFIG_MODEFLG_RXOFFLENBLOCK 0x00200 |
Enable offset/length blocking
| #define EMAC_CONFIG_MODEFLG_RXOWNERSHIP 0x00400 |
Use ownership bit as 1
| #define EMAC_CONFIG_MODEFLG_RXQOS 0x00080 |
Enable QOS at receive side
| #define EMAC_CONFIG_MODEFLG_TXCRC 0x00008 |
Tx frames include CRC
| #define EMAC_CONFIG_MODEFLG_TXFLOWCNTL 0x08000 |
Enable tx flow control
| #define EMAC_CONFIG_MODEFLG_TXPACE 0x04000 |
Enable tx pacing
| #define EMAC_CONFIG_MODEFLG_TXSHORTGAPEN 0x02000 |
Enable tx short gap
| #define EMAC_DESC_BASE_CPPI 0x00002 |
Use CPPI RAM as desriptor memory
| #define EMAC_DESC_BASE_DDR 0x00004 |
Use DDR as descriptor memory
| #define EMAC_DESC_BASE_L2 0x00001 |
Descriptor memory selection Flags.
Use L2 as Descriptor memory
| #define EMAC_DEVMAGIC 0x0aceface |
Device Magic number
| #define EMAC_ERROR_ALREADY 1 |
ErrCodes STANDARD ERROR CODES.
Operation has already been started
| #define EMAC_ERROR_BADPACKET 5 |
Supplied packet was invalid
| #define EMAC_ERROR_DEVICE 3 |
Device hardware error
| #define EMAC_ERROR_INVALID 4 |
Function or calling parameter is invalid
| #define EMAC_ERROR_MACFATAL 6 |
Fatal Error - EMAC_close() required
| #define EMAC_ERROR_NOTREADY 2 |
Device is not open or not ready
| #define EMAC_NUMSTATS 36 |
Number of statistics regs
| #define EMAC_PKT_FLAGS_ALIGNERROR 0x00040000u |
RxErr: Alignment Error
| #define EMAC_PKT_FLAGS_CODEERROR 0x00080000u |
RxErr: Code Error
| #define EMAC_PKT_FLAGS_CONTROL 0x00200000u |
RxCtl: Control Frame
| #define EMAC_PKT_FLAGS_CRCERROR 0x00020000u |
RxErr: Bad CRC
| #define EMAC_PKT_FLAGS_EOP 0x40000000u |
End of packet
| #define EMAC_PKT_FLAGS_FRAGMENT 0x00800000u |
RxErr: Fragment
| #define EMAC_PKT_FLAGS_HASCRC 0x04000000u |
RecvPktFlags Receive Packet flags.
The Following Packet flags are set in Flags on RX packets only RxCrc: PKT has 4byte CRC
| #define EMAC_PKT_FLAGS_JABBER 0x02000000u |
RxErr: Jabber
| #define EMAC_PKT_FLAGS_NOMATCH 0x00010000u |
RxPrm: No Match
| #define EMAC_PKT_FLAGS_OVERRUN 0x00100000u |
RxErr: Overrun
| #define EMAC_PKT_FLAGS_OVERSIZE 0x01000000u |
RxErr: Oversize
| #define EMAC_PKT_FLAGS_SOP 0x80000000u |
EMACPktFlags Packet Buffer Flags set in Flags.
Start of packet
| #define EMAC_PKT_FLAGS_UNDERSIZED 0x00400000u |
RxErr: Undersized
| #define EMAC_RXFILTER_ALL 5 |
Receive filter set to All
| #define EMAC_RXFILTER_ALLMULTICAST 4 |
Receive filter set to All Mcast
| #define EMAC_RXFILTER_BROADCAST 2 |
Receive filter set to Broadcast
| #define EMAC_RXFILTER_DIRECT 1 |
Receive filter set to Direct
| #define EMAC_RXFILTER_MULTICAST 3 |
Receive filter set to Multicast
| #define EMAC_RXFILTER_NOTHING 0 |
PktFiltering Packet Filtering.
Packet Filtering Settings (cumulative) Receive filter set to Nothing
| #define EMAC_TEARDOWN_CHANNEL | ( | x | ) | (1 << x) |
Macro to tear down selective Rx/Tx channels