System Setup:
 Supply: VDD = LVDT_PWR = 12V
 GATE Pin: Connected to 0V (Gate control disabled in software via ALPWR).
 Configuration:
     LVDT_OP_CTRL = 0xCA (Single-ended, Internal Filter enabled, Gain 1 V/V, VCM 1.25V).
     WAVEFORM_DAC_OFFSET = 0x2C00 (Aligned to ~0.86V).
     AMUX_CTRL = 0xF0 (Connecting Waveform DAC to Amp).
     WAVEFORM_GEN_CTRL = 0x01 (Enabled).
 Load: Currently testing with no load (open circuit), but I have also tested with a 10kΩ resistor from P1 to GND to prevent floating.

The Issue:
Despite configuring the registers for operation, the voltage at pins P1 and P2 remains at 0V.

Observations & Measurements:
1.  Waveform Generator is working: I probed the PI and PE pins and observed a correct 2.5 kHz sine wave centered at approx 0.88V with a clean amplitude. This confirms the digital generation path is functional.
2.  Power Supply: LVDT_PWR (Pin 43) is confirmed at 24V (also tested at lower voltages like 12V with same result).
3.  Fault Register (AFEDIAG): When I read the diagnostics, I consistently see the P1_OV (Overvoltage on P1) bit set.
4.  Gain Setting: The gain is set to 1 V/V. Since the input at PE is correct (~0.88V DC + Signal), the output should theoretically be within the valid range (centered at 1.25V), yet the output stays latched at 0V.

Troubleshooting Attempted:
 I have ensured ALPWR is set to 0x14 to disable the external Gate Control logic (since GATE is tied to GND).
 I have attempted to clear the AFEDIAG register (writing 1s) after enabling the waveform generator to handle startup transients.
 I verified continuity between LVDT_PWR and the supply.
 I verified the connection between PI and PE (internal SKIP_FILTER bit is set, and I have also verified with an external connection).

Questions:
1.  If the input signal at PE is valid and within range, why would the amplifier immediately trip a P1_OV fault and latch the output to 0V?
2.  Could an issue with the Gate Control configuration (even if disabled in ALPWR) cause the high-voltage amplifier to remain in a shutdown state or trigger a false OV flag?
3.  Is it possible the output stage is physically damaged (shorted), and if so, is there a specific resistance check between P1/P2 and GND to confirm silicon failure?

Any guidance on debugging this P1_OV latch would be appreciated.



### Before you post:
 Double-check your supply voltage text: In the draft, I wrote "LVDT_PWR is confirmed at 24V" because you mentioned 24V in our chat, but the text you pasted says "Supply is VDD = LVDT_PWR = 12V". Please edit the voltage in the "System Setup" section to match exactly what you are currently using.
 Safety: If you are currently using 24V, I highly recommend lowering it to 12V or 5V before taking further measurements to prevent damaging a new chip if you replace it.