# 1 "arch/arm/dts/.vau-p3.dtb.pre.tmp"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "./../include/linux/kconfig.h" 1



# 1 "include/generated/autoconf.h" 1
# 5 "./../include/linux/kconfig.h" 2
# 1 "<command-line>" 2
# 1 "arch/arm/dts/.vau-p3.dtb.pre.tmp"
# 9 "arch/arm/dts/.vau-p3.dtb.pre.tmp"
# 1 "../arch/arm/dts/vau-p3-common.dtsi" 1







/dts-v1/;

# 1 "../arch/arm/dts/dra74x.dtsi" 1
# 10 "../arch/arm/dts/dra74x.dtsi"
# 1 "../arch/arm/dts/dra7.dtsi" 1
# 10 "../arch/arm/dts/dra7.dtsi"
# 1 "../arch/arm/dts/include/dt-bindings/interrupt-controller/arm-gic.h" 1







# 1 "../arch/arm/dts/include/dt-bindings/interrupt-controller/irq.h" 1
# 9 "../arch/arm/dts/include/dt-bindings/interrupt-controller/arm-gic.h" 2
# 11 "../arch/arm/dts/dra7.dtsi" 2
# 1 "../arch/arm/dts/include/dt-bindings/pinctrl/dra.h" 1
# 12 "../arch/arm/dts/dra7.dtsi" 2



/ {
 #address-cells = <2>;
 #size-cells = <2>;

 compatible = "ti,dra7xx";
 interrupt-parent = <&crossbar_mpu>;
 chosen { };

 aliases {
  i2c0 = &i2c1;
  i2c1 = &i2c2;
  i2c2 = &i2c3;
  i2c3 = &i2c4;
  i2c4 = &i2c5;
  serial0 = &uart1;
  serial1 = &uart2;
  serial2 = &uart3;
  serial3 = &uart4;
  serial4 = &uart5;
  serial5 = &uart6;
  serial6 = &uart7;
  serial7 = &uart8;
  serial8 = &uart9;
  serial9 = &uart10;
  ethernet0 = &cpsw_emac0;
  ethernet1 = &cpsw_emac1;
  d_can0 = &dcan1;
  d_can1 = &dcan2;
  spi0 = &qspi;
 };

 timer {
  compatible = "arm,armv7-timer";
  interrupts = <1 13 ((((1 << (2)) - 1) << 8) | 8)>,
        <1 14 ((((1 << (2)) - 1) << 8) | 8)>,
        <1 11 ((((1 << (2)) - 1) << 8) | 8)>,
        <1 10 ((((1 << (2)) - 1) << 8) | 8)>;
  interrupt-parent = <&gic>;
 };

 gic: interrupt-controller@48211000 {
  compatible = "arm,cortex-a15-gic";
  interrupt-controller;
  #interrupt-cells = <3>;
  reg = <0x0 0x48211000 0x0 0x1000>,
        <0x0 0x48212000 0x0 0x2000>,
        <0x0 0x48214000 0x0 0x2000>,
        <0x0 0x48216000 0x0 0x2000>;
  interrupts = <1 9 ((((1 << (2)) - 1) << 8) | 4)>;
  interrupt-parent = <&gic>;
 };

 wakeupgen: interrupt-controller@48281000 {
  compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  interrupt-controller;
  #interrupt-cells = <3>;
  reg = <0x0 0x48281000 0x0 0x1000>;
  interrupt-parent = <&gic>;
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a15";
   reg = <0>;

   operating-points-v2 = <&cpu0_opp_table>;

   clocks = <&dpll_mpu_ck>;
   clock-names = "cpu";

   clock-latency = <300000>;


   cooling-min-level = <0>;
   cooling-max-level = <2>;
   #cooling-cells = <2>;
  };
 };

 cpu0_opp_table: opp-table {
  compatible = "operating-points-v2-ti-cpu";
  syscon = <&scm_wkup>;

  opp_nom-1000000000 {
   opp-hz = /bits/ 64 <1000000000>;
   opp-microvolt = <1060000 850000 1150000>;
   opp-supported-hw = <0xFF 0x01>;
   opp-suspend;
  };

  opp_od-1176000000 {
   opp-hz = /bits/ 64 <1176000000>;
   opp-microvolt = <1160000 885000 1160000>;
   opp-supported-hw = <0xFF 0x02>;
  };
 };





 soc {
  compatible = "ti,omap-infra";
  mpu {
   compatible = "ti,omap5-mpu";
   ti,hwmods = "mpu";
  };
 };
# 135 "../arch/arm/dts/dra7.dtsi"
 ocp {
  compatible = "ti,dra7-l3-noc", "simple-bus";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x0 0x0 0xc0000000>;
  ti,hwmods = "l3_main_1", "l3_main_2";
  reg = <0x0 0x44000000 0x0 0x1000000>,
        <0x0 0x45000000 0x0 0x1000>;
  interrupts-extended = <&crossbar_mpu 0 4 4>,
          <&wakeupgen 0 10 4>;

  l4_cfg: l4@4a000000 {
   compatible = "ti,dra7-l4-cfg", "simple-bus";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x4a000000 0x22c000>;

   scm: scm@2000 {
    compatible = "ti,dra7-scm-core", "simple-bus";
    reg = <0x2000 0x2000>;
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0 0x2000 0x2000>;

    scm_conf: scm_conf@0 {
     compatible = "syscon", "simple-bus";
     reg = <0x0 0x1400>;
     #address-cells = <1>;
     #size-cells = <1>;
     ranges = <0 0x0 0x1400>;

     pbias_regulator: pbias_regulator@e00 {
      compatible = "ti,pbias-dra7", "ti,pbias-omap";
      reg = <0xe00 0x4>;
      syscon = <&scm_conf>;
      pbias_mmc_reg: pbias_mmc_omap5 {
       regulator-name = "pbias_mmc_omap5";
       regulator-min-microvolt = <1800000>;
       regulator-max-microvolt = <3000000>;
      };
     };

     scm_conf_clocks: clocks {
      #address-cells = <1>;
      #size-cells = <0>;
     };
    };

    dra7_pmx_core: pinmux@1400 {
     compatible = "ti,dra7-padconf",
           "pinctrl-single";
     reg = <0x1400 0x0468>;
     #address-cells = <1>;
     #size-cells = <0>;
     #pinctrl-cells = <1>;
     #interrupt-cells = <1>;
     interrupt-controller;
     pinctrl-single,register-width = <32>;
     pinctrl-single,function-mask = <0x3fffffff>;
    };

    scm_conf1: scm_conf@1c04 {
     compatible = "syscon";
     reg = <0x1c04 0x0020>;
     #syscon-cells = <2>;
    };

    scm_conf_pcie: scm_conf@1c24 {
     compatible = "syscon";
     reg = <0x1c24 0x0024>;
    };

    sdma_xbar: dma-router@b78 {
     compatible = "ti,dra7-dma-crossbar";
     reg = <0xb78 0xfc>;
     #dma-cells = <1>;
     dma-requests = <205>;
     ti,dma-safe-map = <0>;
     dma-masters = <&sdma>;
    };

    edma_xbar: dma-router@c78 {
     compatible = "ti,dra7-dma-crossbar";
     reg = <0xc78 0x7c>;
     #dma-cells = <2>;
     dma-requests = <204>;
     ti,dma-safe-map = <0>;
     dma-masters = <&edma>;
    };
   };

   cm_core_aon: cm_core_aon@5000 {
    compatible = "ti,dra7-cm-core-aon";
    reg = <0x5000 0x2000>;

    cm_core_aon_clocks: clocks {
     #address-cells = <1>;
     #size-cells = <0>;
    };

    cm_core_aon_clockdomains: clockdomains {
    };
   };

   cm_core: cm_core@8000 {
    compatible = "ti,dra7-cm-core";
    reg = <0x8000 0x3000>;

    cm_core_clocks: clocks {
     #address-cells = <1>;
     #size-cells = <0>;
    };

    cm_core_clockdomains: clockdomains {
    };
   };
  };

  l4_wkup: l4@4ae00000 {
   compatible = "ti,dra7-l4-wkup", "simple-bus";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x4ae00000 0x3f000>;

   counter32k: counter@4000 {
    compatible = "ti,omap-counter32k";
    reg = <0x4000 0x40>;
    ti,hwmods = "counter_32k";
   };

   prm: prm@6000 {
    compatible = "ti,dra7-prm";
    reg = <0x6000 0x3000>;
    interrupts = <0 6 4>;

    prm_clocks: clocks {
     #address-cells = <1>;
     #size-cells = <0>;
    };

    prm_clockdomains: clockdomains {
    };
   };

   scm_wkup: scm_conf@c000 {
    compatible = "syscon";
    reg = <0xc000 0x1000>;
   };
  };

  axi@0 {
   compatible = "simple-bus";
   #size-cells = <1>;
   #address-cells = <1>;
   ranges = <0x51000000 0x51000000 0x3000
      0x0 0x20000000 0x10000000>;




   pcie1_rc: pcie@51000000 {
    compatible = "ti,dra7-pcie";
    reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
    reg-names = "rc_dbics", "ti_conf", "config";
    interrupts = <0 232 0x4>, <0 233 0x4>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    ranges = <0x81000000 0 0 0x03000 0 0x00010000
       0x82000000 0 0x20013000 0x13000 0 0xffed000>;
    bus-range = <0x00 0xff>;
    #interrupt-cells = <1>;
    num-lanes = <1>;
    linux,pci-domain = <0>;
    ti,hwmods = "pcie1";
    phys = <&pcie1_phy>;
    phy-names = "pcie-phy0";
    interrupt-map-mask = <0 0 0 7>;
    interrupt-map = <0 0 0 1 &pcie1_intc 1>,
      <0 0 0 2 &pcie1_intc 2>,
      <0 0 0 3 &pcie1_intc 3>,
      <0 0 0 4 &pcie1_intc 4>;
    status = "disabled";
    pcie1_intc: interrupt-controller {
     interrupt-controller;
     #address-cells = <0>;
     #interrupt-cells = <1>;
    };
   };

   pcie1_ep: pcie_ep@51000000 {
    compatible = "ti,dra7-pcie-ep";
    reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
    reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
    interrupts = <0 232 0x4>;
    num-lanes = <1>;
    num-ib-windows = <4>;
    num-ob-windows = <16>;
    ti,hwmods = "pcie1";
    phys = <&pcie1_phy>;
    phy-names = "pcie-phy0";
    ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
    status = "disabled";
   };
  };

  axi@1 {
   compatible = "simple-bus";
   #size-cells = <1>;
   #address-cells = <1>;
   ranges = <0x51800000 0x51800000 0x3000
      0x0 0x30000000 0x10000000>;
   status = "disabled";
   pcie@51800000 {
    compatible = "ti,dra7-pcie";
    reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
    reg-names = "rc_dbics", "ti_conf", "config";
    interrupts = <0 355 0x4>, <0 356 0x4>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    ranges = <0x81000000 0 0 0x03000 0 0x00010000
       0x82000000 0 0x30013000 0x13000 0 0xffed000>;
    bus-range = <0x00 0xff>;
    #interrupt-cells = <1>;
    num-lanes = <1>;
    linux,pci-domain = <1>;
    ti,hwmods = "pcie2";
    phys = <&pcie2_phy>;
    phy-names = "pcie-phy0";
    interrupt-map-mask = <0 0 0 7>;
    interrupt-map = <0 0 0 1 &pcie2_intc 1>,
      <0 0 0 2 &pcie2_intc 2>,
      <0 0 0 3 &pcie2_intc 3>,
      <0 0 0 4 &pcie2_intc 4>;
    pcie2_intc: interrupt-controller {
     interrupt-controller;
     #address-cells = <0>;
     #interrupt-cells = <1>;
    };
   };
  };

  ocmcram1: ocmcram@40300000 {
   compatible = "mmio-sram";
   reg = <0x40300000 0x80000>;
   ranges = <0x0 0x40300000 0x80000>;
   #address-cells = <1>;
   #size-cells = <1>;
# 395 "../arch/arm/dts/dra7.dtsi"
   sram-hs@0 {
    compatible = "ti,secure-ram";
    reg = <0x0 0x0>;
   };
  };







  ocmcram2: ocmcram@40400000 {
   status = "disabled";
   compatible = "mmio-sram";
   reg = <0x40400000 0x100000>;
   ranges = <0x0 0x40400000 0x100000>;
   #address-cells = <1>;
   #size-cells = <1>;
  };

  ocmcram3: ocmcram@40500000 {
   status = "disabled";
   compatible = "mmio-sram";
   reg = <0x40500000 0x100000>;
   ranges = <0x0 0x40500000 0x100000>;
   #address-cells = <1>;
   #size-cells = <1>;
  };

  bandgap: bandgap@4a0021e0 {
   reg = <0x4a0021e0 0xc
    0x4a00232c 0xc
    0x4a002380 0x2c
    0x4a0023C0 0x3c
    0x4a002564 0x8
    0x4a002574 0x50>;
    compatible = "ti,dra752-bandgap";
    interrupts = <0 121 4>;
    #thermal-sensor-cells = <1>;
  };

  dsp1_system: dsp_system@40d00000 {
   compatible = "syscon";
   reg = <0x40d00000 0x100>;
  };

  dra7_iodelay_core: padconf@4844a000 {
   compatible = "ti,dra7-iodelay";
   reg = <0x4844a000 0x0d1c>;
   #address-cells = <1>;
   #size-cells = <0>;
   #pinctrl-cells = <2>;
  };

  sdma: dma-controller@4a056000 {
   compatible = "ti,omap4430-sdma";
   reg = <0x4a056000 0x1000>;
   interrupts = <0 7 4>,
         <0 8 4>,
         <0 9 4>,
         <0 10 4>;
   #dma-cells = <1>;
   dma-channels = <32>;
   dma-requests = <127>;
  };

  edma: edma@43300000 {
   compatible = "ti,edma3-tpcc";
   ti,hwmods = "tpcc";
   reg = <0x43300000 0x100000>;
   reg-names = "edma3_cc";
   interrupts = <0 361 4>,
         <0 360 4>,
         <0 359 4>;
   interrupt-names = "edma3_ccint", "edma3_mperr",
       "edma3_ccerrint";
   dma-requests = <64>;
   #dma-cells = <2>;

   ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;







  };

  edma_tptc0: tptc@43400000 {
   compatible = "ti,edma3-tptc";
   ti,hwmods = "tptc0";
   reg = <0x43400000 0x100000>;
   interrupts = <0 370 4>;
   interrupt-names = "edma3_tcerrint";
  };

  edma_tptc1: tptc@43500000 {
   compatible = "ti,edma3-tptc";
   ti,hwmods = "tptc1";
   reg = <0x43500000 0x100000>;
   interrupts = <0 371 4>;
   interrupt-names = "edma3_tcerrint";
  };

  gpio1: gpio@4ae10000 {
   compatible = "ti,omap4-gpio";
   reg = <0x4ae10000 0x200>;
   interrupts = <0 24 4>;
   ti,hwmods = "gpio1";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio2: gpio@48055000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48055000 0x200>;
   interrupts = <0 25 4>;
   ti,hwmods = "gpio2";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio3: gpio@48057000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48057000 0x200>;
   interrupts = <0 26 4>;
   ti,hwmods = "gpio3";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio4: gpio@48059000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48059000 0x200>;
   interrupts = <0 27 4>;
   ti,hwmods = "gpio4";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio5: gpio@4805b000 {
   compatible = "ti,omap4-gpio";
   reg = <0x4805b000 0x200>;
   interrupts = <0 28 4>;
   ti,hwmods = "gpio5";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio6: gpio@4805d000 {
   compatible = "ti,omap4-gpio";
   reg = <0x4805d000 0x200>;
   interrupts = <0 29 4>;
   ti,hwmods = "gpio6";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio7: gpio@48051000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48051000 0x200>;
   interrupts = <0 30 4>;
   ti,hwmods = "gpio7";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio8: gpio@48053000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48053000 0x200>;
   interrupts = <0 116 4>;
   ti,hwmods = "gpio8";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  uart1: serial@4806a000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806a000 0x100>;
   interrupts-extended = <&crossbar_mpu 0 67 4>;
   ti,hwmods = "uart1";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
   dma-names = "tx", "rx";
  };

  uart2: serial@4806c000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806c000 0x100>;
   interrupts = <0 68 4>;
   ti,hwmods = "uart2";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
   dma-names = "tx", "rx";
  };

  uart3: serial@48020000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48020000 0x100>;
   interrupts = <0 69 4>;
   ti,hwmods = "uart3";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
   dma-names = "tx", "rx";
  };

  uart4: serial@4806e000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806e000 0x100>;
   interrupts = <0 65 4>;
   ti,hwmods = "uart4";
   clock-frequency = <48000000>;
                        status = "disabled";
   dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
   dma-names = "tx", "rx";
  };

  uart5: serial@48066000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48066000 0x100>;
   interrupts = <0 100 4>;
   ti,hwmods = "uart5";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
   dma-names = "tx", "rx";
  };

  uart6: serial@48068000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48068000 0x100>;
   interrupts = <0 101 4>;
   ti,hwmods = "uart6";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
   dma-names = "tx", "rx";
  };

  uart7: serial@48420000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48420000 0x100>;
   interrupts = <0 218 4>;
   ti,hwmods = "uart7";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  uart8: serial@48422000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48422000 0x100>;
   interrupts = <0 219 4>;
   ti,hwmods = "uart8";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  uart9: serial@48424000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48424000 0x100>;
   interrupts = <0 220 4>;
   ti,hwmods = "uart9";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  uart10: serial@4ae2b000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4ae2b000 0x100>;
   interrupts = <0 221 4>;
   ti,hwmods = "uart10";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  mailbox1: mailbox@4a0f4000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4a0f4000 0x200>;
   interrupts = <0 21 4>,
         <0 135 4>,
         <0 134 4>;
   ti,hwmods = "mailbox1";
   #mbox-cells = <1>;
   ti,mbox-num-users = <3>;
   ti,mbox-num-fifos = <8>;
   status = "disabled";
  };

  mailbox2: mailbox@4883a000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4883a000 0x200>;
   interrupts = <0 237 4>,
         <0 238 4>,
         <0 239 4>,
         <0 240 4>;
   ti,hwmods = "mailbox2";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox3: mailbox@4883c000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4883c000 0x200>;
   interrupts = <0 241 4>,
         <0 242 4>,
         <0 243 4>,
         <0 244 4>;
   ti,hwmods = "mailbox3";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox4: mailbox@4883e000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4883e000 0x200>;
   interrupts = <0 245 4>,
         <0 246 4>,
         <0 247 4>,
         <0 248 4>;
   ti,hwmods = "mailbox4";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox5: mailbox@48840000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48840000 0x200>;
   interrupts = <0 249 4>,
         <0 250 4>,
         <0 251 4>,
         <0 252 4>;
   ti,hwmods = "mailbox5";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox6: mailbox@48842000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48842000 0x200>;
   interrupts = <0 253 4>,
         <0 254 4>,
         <0 255 4>,
         <0 256 4>;
   ti,hwmods = "mailbox6";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox7: mailbox@48844000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48844000 0x200>;
   interrupts = <0 257 4>,
         <0 258 4>,
         <0 259 4>,
         <0 260 4>;
   ti,hwmods = "mailbox7";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox8: mailbox@48846000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48846000 0x200>;
   interrupts = <0 261 4>,
         <0 262 4>,
         <0 263 4>,
         <0 264 4>;
   ti,hwmods = "mailbox8";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox9: mailbox@4885e000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4885e000 0x200>;
   interrupts = <0 265 4>,
         <0 266 4>,
         <0 267 4>,
         <0 268 4>;
   ti,hwmods = "mailbox9";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox10: mailbox@48860000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48860000 0x200>;
   interrupts = <0 269 4>,
         <0 270 4>,
         <0 271 4>,
         <0 272 4>;
   ti,hwmods = "mailbox10";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox11: mailbox@48862000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48862000 0x200>;
   interrupts = <0 273 4>,
         <0 274 4>,
         <0 275 4>,
         <0 276 4>;
   ti,hwmods = "mailbox11";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox12: mailbox@48864000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48864000 0x200>;
   interrupts = <0 277 4>,
         <0 278 4>,
         <0 279 4>,
         <0 280 4>;
   ti,hwmods = "mailbox12";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox13: mailbox@48802000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48802000 0x200>;
   interrupts = <0 379 4>,
         <0 380 4>,
         <0 381 4>,
         <0 382 4>;
   ti,hwmods = "mailbox13";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  timer1: timer@4ae18000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4ae18000 0x80>;
   interrupts = <0 32 4>;
   ti,hwmods = "timer1";
   ti,timer-alwon;
  };

  timer2: timer@48032000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48032000 0x80>;
   interrupts = <0 33 4>;
   ti,hwmods = "timer2";
  };

  timer3: timer@48034000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48034000 0x80>;
   interrupts = <0 34 4>;
   ti,hwmods = "timer3";
  };

  timer4: timer@48036000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48036000 0x80>;
   interrupts = <0 35 4>;
   ti,hwmods = "timer4";
  };

  timer5: timer@48820000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48820000 0x80>;
   interrupts = <0 36 4>;
   ti,hwmods = "timer5";
  };

  timer6: timer@48822000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48822000 0x80>;
   interrupts = <0 37 4>;
   ti,hwmods = "timer6";
  };

  timer7: timer@48824000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48824000 0x80>;
   interrupts = <0 38 4>;
   ti,hwmods = "timer7";
  };

  timer8: timer@48826000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48826000 0x80>;
   interrupts = <0 39 4>;
   ti,hwmods = "timer8";
  };

  timer9: timer@4803e000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4803e000 0x80>;
   interrupts = <0 40 4>;
   ti,hwmods = "timer9";
  };

  timer10: timer@48086000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48086000 0x80>;
   interrupts = <0 41 4>;
   ti,hwmods = "timer10";
  };

  timer11: timer@48088000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48088000 0x80>;
   interrupts = <0 42 4>;
   ti,hwmods = "timer11";
  };

  timer12: timer@4ae20000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4ae20000 0x80>;
   interrupts = <0 90 4>;
   ti,hwmods = "timer12";
   ti,timer-alwon;
   ti,timer-secure;
  };

  timer13: timer@48828000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48828000 0x80>;
   interrupts = <0 339 4>;
   ti,hwmods = "timer13";
  };

  timer14: timer@4882a000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4882a000 0x80>;
   interrupts = <0 340 4>;
   ti,hwmods = "timer14";
  };

  timer15: timer@4882c000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4882c000 0x80>;
   interrupts = <0 341 4>;
   ti,hwmods = "timer15";
  };

  timer16: timer@4882e000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4882e000 0x80>;
   interrupts = <0 342 4>;
   ti,hwmods = "timer16";
  };

  wdt2: wdt@4ae14000 {
   compatible = "ti,omap3-wdt";
   reg = <0x4ae14000 0x80>;
   interrupts = <0 75 4>;
   ti,hwmods = "wd_timer2";
  };

  hwspinlock: spinlock@4a0f6000 {
   compatible = "ti,omap4-hwspinlock";
   reg = <0x4a0f6000 0x1000>;
   ti,hwmods = "spinlock";
   #hwlock-cells = <1>;
  };

  dmm@4e000000 {
   compatible = "ti,omap5-dmm";
   reg = <0x4e000000 0x800>;
   interrupts = <0 108 4>;
   ti,hwmods = "dmm";
  };

  i2c1: i2c@48070000 {
   compatible = "ti,omap4-i2c";
   reg = <0x48070000 0x100>;
   interrupts = <0 51 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c1";
   status = "disabled";
  };

  i2c2: i2c@48072000 {
   compatible = "ti,omap4-i2c";
   reg = <0x48072000 0x100>;
   interrupts = <0 52 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c2";
   status = "disabled";
  };

  i2c3: i2c@48060000 {
   compatible = "ti,omap4-i2c";
   reg = <0x48060000 0x100>;
   interrupts = <0 56 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c3";
   status = "disabled";
  };

  i2c4: i2c@4807a000 {
   compatible = "ti,omap4-i2c";
   reg = <0x4807a000 0x100>;
   interrupts = <0 57 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c4";
   status = "disabled";
  };

  i2c5: i2c@4807c000 {
   compatible = "ti,omap4-i2c";
   reg = <0x4807c000 0x100>;
   interrupts = <0 55 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c5";
   status = "disabled";
  };

  mmc1: mmc@4809c000 {
   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
   reg = <0x4809c000 0x400>;
   interrupts = <0 78 4>;
   ti,hwmods = "mmc1";
   ti,dual-volt;
   ti,needs-special-reset;
   dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
   dma-names = "tx", "rx";
   status = "disabled";
   pbias-supply = <&pbias_mmc_reg>;
   max-frequency = <192000000>;
   sd-uhs-sdr104;
   sd-uhs-sdr50;
   sd-uhs-ddr50;
   sd-uhs-sdr25;
   sd-uhs-sdr12;
  };

  mmc2: mmc@480b4000 {
   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
   reg = <0x480b4000 0x400>;
   interrupts = <0 81 4>;
   ti,hwmods = "mmc2";
   ti,needs-special-reset;
   dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
   dma-names = "tx", "rx";
   status = "disabled";
   max-frequency = <192000000>;
   sd-uhs-sdr25;
   sd-uhs-sdr12;
   mmc-hs200-1_8v;
   mmc-ddr-1_8v;
  };

  mmc3: mmc@480ad000 {
   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
   reg = <0x480ad000 0x400>;
   interrupts = <0 89 4>;
   ti,hwmods = "mmc3";
   ti,needs-special-reset;
   dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
   dma-names = "tx", "rx";
   status = "disabled";

   max-frequency = <64000000>;
   sd-uhs-sdr12;
   sd-uhs-sdr25;
   sd-uhs-sdr50;
  };

  mmc4: mmc@480d1000 {
   compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc";
   reg = <0x480d1000 0x400>;
   interrupts = <0 91 4>;
   ti,hwmods = "mmc4";
   ti,needs-special-reset;
   dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
   dma-names = "tx", "rx";
   status = "disabled";
   max-frequency = <192000000>;
   sd-uhs-sdr12;
   sd-uhs-sdr25;
  };

  mmu0_dsp1: mmu@40d01000 {
   compatible = "ti,dra7-dsp-iommu";
   reg = <0x40d01000 0x100>;
   interrupts = <0 23 4>;
   ti,hwmods = "mmu0_dsp1";
   #iommu-cells = <0>;
   ti,syscon-mmuconfig = <&dsp1_system 0x0>;
   status = "disabled";
  };

  mmu1_dsp1: mmu@40d02000 {
   compatible = "ti,dra7-dsp-iommu";
   reg = <0x40d02000 0x100>;
   interrupts = <0 145 4>;
   ti,hwmods = "mmu1_dsp1";
   #iommu-cells = <0>;
   ti,syscon-mmuconfig = <&dsp1_system 0x1>;
   status = "disabled";
  };

  mmu_ipu1: mmu@58882000 {
   compatible = "ti,dra7-iommu";
   reg = <0x58882000 0x100>;
   interrupts = <0 395 4>;
   ti,hwmods = "mmu_ipu1";
   #iommu-cells = <0>;
   ti,iommu-bus-err-back;
   status = "disabled";
  };

  mmu_ipu2: mmu@55082000 {
   compatible = "ti,dra7-iommu";
   reg = <0x55082000 0x100>;
   interrupts = <0 396 4>;
   ti,hwmods = "mmu_ipu2";
   #iommu-cells = <0>;
   ti,iommu-bus-err-back;
   status = "disabled";
  };

  abb_mpu: regulator-abb-mpu {
   compatible = "ti,abb-v3";
   regulator-name = "abb_mpu";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
         <0x4ae06014 0x4>, <0x4a003b20 0xc>,
         <0x4ae0c158 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x80>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1060000 0 0x0 0 0x02000000 0x01F00000
   1160000 0 0x4 0 0x02000000 0x01F00000
   1210000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  abb_ivahd: regulator-abb-ivahd {
   compatible = "ti,abb-v3";
   regulator-name = "abb_ivahd";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
         <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
         <0x4a002470 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x40000000>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1055000 0 0x0 0 0x02000000 0x01F00000
   1150000 0 0x4 0 0x02000000 0x01F00000
   1250000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  abb_dspeve: regulator-abb-dspeve {
   compatible = "ti,abb-v3";
   regulator-name = "abb_dspeve";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
         <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
         <0x4a00246c 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x20000000>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1055000 0 0x0 0 0x02000000 0x01F00000
   1150000 0 0x4 0 0x02000000 0x01F00000
   1250000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  abb_gpu: regulator-abb-gpu {
   compatible = "ti,abb-v3";
   regulator-name = "abb_gpu";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
         <0x4ae06010 0x4>, <0x4a003b08 0xc>,
         <0x4ae0c154 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x10000000>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1090000 0 0x0 0 0x02000000 0x01F00000
   1210000 0 0x4 0 0x02000000 0x01F00000
   1280000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  mcspi1: spi@48098000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x48098000 0x200>;
   interrupts = <0 60 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi1";
   ti,spi-num-cs = <4>;
   dmas = <&sdma_xbar 35>,
          <&sdma_xbar 36>,
          <&sdma_xbar 37>,
          <&sdma_xbar 38>,
          <&sdma_xbar 39>,
          <&sdma_xbar 40>,
          <&sdma_xbar 41>,
          <&sdma_xbar 42>;
   dma-names = "tx0", "rx0", "tx1", "rx1",
        "tx2", "rx2", "tx3", "rx3";
   status = "disabled";
  };

  mcspi2: spi@4809a000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x4809a000 0x200>;
   interrupts = <0 61 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi2";
   ti,spi-num-cs = <2>;
   dmas = <&sdma_xbar 43>,
          <&sdma_xbar 44>,
          <&sdma_xbar 45>,
          <&sdma_xbar 46>;
   dma-names = "tx0", "rx0", "tx1", "rx1";
   status = "disabled";
  };

  mcspi3: spi@480b8000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x480b8000 0x200>;
   interrupts = <0 86 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi3";
   ti,spi-num-cs = <2>;
   dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
   dma-names = "tx0", "rx0";
   status = "disabled";
  };

  mcspi4: spi@480ba000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x480ba000 0x200>;
   interrupts = <0 43 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi4";
   ti,spi-num-cs = <1>;
   dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
   dma-names = "tx0", "rx0";
   status = "disabled";
  };

  qspi: qspi@4b300000 {
   compatible = "ti,dra7xxx-qspi";
   reg = <0x4b300000 0x100>,
         <0x5c000000 0x4000000>;
   reg-names = "qspi_base", "qspi_mmap";
   syscon-chipselects = <&scm_conf 0x558>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "qspi";
   clocks = <&qspi_gfclk_div>;
   clock-names = "fck";
   num-cs = <4>;
   interrupts = <0 343 4>;
   status = "disabled";
  };


  ocp2scp@4a090000 {
   compatible = "ti,omap-ocp2scp";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;
   reg = <0x4a090000 0x20>;
   ti,hwmods = "ocp2scp3";
   sata_phy: phy@4A096000 {
    compatible = "ti,phy-pipe3-sata";
    reg = <0x4A096000 0x80>,
          <0x4A096400 0x64>,
          <0x4A096800 0x40>;
    reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    syscon-phy-power = <&scm_conf 0x374>;
    clocks = <&sys_clkin1>, <&sata_ref_clk>;
    clock-names = "sysclk", "refclk";
    syscon-pllreset = <&scm_conf 0x3fc>;
    #phy-cells = <0>;
   };

   pcie1_phy: pciephy@4a094000 {
    compatible = "ti,phy-pipe3-pcie";
    reg = <0x4a094000 0x80>,
          <0x4a094400 0x64>;
    reg-names = "phy_rx", "phy_tx";
    syscon-phy-power = <&scm_conf_pcie 0x1c>;
    syscon-pcs = <&scm_conf_pcie 0x10>;
    clocks = <&dpll_pcie_ref_ck>,
      <&dpll_pcie_ref_m2ldo_ck>,
      <&optfclk_pciephy1_32khz>,
      <&optfclk_pciephy1_clk>,
      <&optfclk_pciephy1_div_clk>,
      <&optfclk_pciephy_div>,
      <&sys_clkin1>;
    clock-names = "dpll_ref", "dpll_ref_m2",
           "wkupclk", "refclk",
           "div-clk", "phy-div", "sysclk";
    #phy-cells = <0>;
   };

   pcie2_phy: pciephy@4a095000 {
    compatible = "ti,phy-pipe3-pcie";
    reg = <0x4a095000 0x80>,
          <0x4a095400 0x64>;
    reg-names = "phy_rx", "phy_tx";
    syscon-phy-power = <&scm_conf_pcie 0x20>;
    syscon-pcs = <&scm_conf_pcie 0x10>;
    clocks = <&dpll_pcie_ref_ck>,
      <&dpll_pcie_ref_m2ldo_ck>,
      <&optfclk_pciephy2_32khz>,
      <&optfclk_pciephy2_clk>,
      <&optfclk_pciephy2_div_clk>,
      <&optfclk_pciephy_div>,
      <&sys_clkin1>;
    clock-names = "dpll_ref", "dpll_ref_m2",
           "wkupclk", "refclk",
           "div-clk", "phy-div", "sysclk";
    #phy-cells = <0>;
    status = "disabled";
   };
  };

  sata: sata@4a141100 {
   compatible = "snps,dwc-ahci";
   reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
   interrupts = <0 49 4>;
   phys = <&sata_phy>;
   phy-names = "sata-phy";
   clocks = <&sata_ref_clk>;
   ti,hwmods = "sata";
   ports-implemented = <0x1>;
  };

  rtc: rtc@48838000 {
   compatible = "ti,am3352-rtc";
   reg = <0x48838000 0x100>;
   interrupts = <0 217 4>,
         <0 217 4>;
   ti,hwmods = "rtcss";
   clocks = <&sys_32k_ck>;
  };


  ocp2scp@4a080000 {
   compatible = "ti,omap-ocp2scp";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;
   reg = <0x4a080000 0x20>;
   ti,hwmods = "ocp2scp1";

   usb2_phy1: phy@4a084000 {
    compatible = "ti,dra7x-usb2", "ti,omap-usb2";
    reg = <0x4a084000 0x400>;
    syscon-phy-power = <&scm_conf 0x300>;
    clocks = <&usb_phy1_always_on_clk32k>,
      <&usb_otg_ss1_refclk960m>;
    clock-names = "wkupclk",
      "refclk";
    #phy-cells = <0>;
   };

   usb2_phy2: phy@4a085000 {
    compatible = "ti,dra7x-usb2-phy2",
          "ti,omap-usb2";
    reg = <0x4a085000 0x400>;
    syscon-phy-power = <&scm_conf 0xe74>;
    clocks = <&usb_phy2_always_on_clk32k>,
      <&usb_otg_ss2_refclk960m>;
    clock-names = "wkupclk",
      "refclk";
    #phy-cells = <0>;
   };

   usb3_phy1: phy@4a084400 {
    compatible = "ti,omap-usb3";
    reg = <0x4a084400 0x80>,
          <0x4a084800 0x64>,
          <0x4a084c00 0x40>;
    reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    syscon-phy-power = <&scm_conf 0x370>;
    clocks = <&usb_phy3_always_on_clk32k>,
      <&sys_clkin1>,
      <&usb_otg_ss1_refclk960m>;
    clock-names = "wkupclk",
      "sysclk",
      "refclk";
    #phy-cells = <0>;
   };
  };

  omap_dwc3_1: omap_dwc3_1@48880000 {
   compatible = "ti,dwc3";
   ti,hwmods = "usb_otg_ss1";
   reg = <0x48880000 0x10000>;
   interrupts = <0 72 4>;
   #address-cells = <1>;
   #size-cells = <1>;
   utmi-mode = <2>;
   ranges;
   usb1: usb@48890000 {
    compatible = "snps,dwc3";
    reg = <0x48890000 0x17000>;
    interrupts = <0 71 4>,
          <0 71 4>,
          <0 72 4>;
    interrupt-names = "peripheral",
        "host",
        "otg";
    phys = <&usb2_phy1>, <&usb3_phy1>;
    phy-names = "usb2-phy", "usb3-phy";
    maximum-speed = "super-speed";
    dr_mode = "otg";
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
   };
  };

  omap_dwc3_2: omap_dwc3_2@488c0000 {
   compatible = "ti,dwc3";
   ti,hwmods = "usb_otg_ss2";
   reg = <0x488c0000 0x10000>;
   interrupts = <0 87 4>;
   #address-cells = <1>;
   #size-cells = <1>;
   utmi-mode = <2>;
   ranges;
   usb2: usb@488d0000 {
    compatible = "snps,dwc3";
    reg = <0x488d0000 0x17000>;
    interrupts = <0 73 4>,
          <0 73 4>,
          <0 87 4>;
    interrupt-names = "peripheral",
        "host",
        "otg";
    phys = <&usb2_phy2>;
    phy-names = "usb2-phy";
    maximum-speed = "high-speed";
    dr_mode = "otg";
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
   };
  };


  omap_dwc3_3: omap_dwc3_3@48900000 {
   compatible = "ti,dwc3";
   ti,hwmods = "usb_otg_ss3";
   reg = <0x48900000 0x10000>;
   interrupts = <0 344 4>;
   #address-cells = <1>;
   #size-cells = <1>;
   utmi-mode = <2>;
   ranges;
   status = "disabled";
   usb3: usb@48910000 {
    compatible = "snps,dwc3";
    reg = <0x48910000 0x17000>;
    interrupts = <0 88 4>,
          <0 88 4>,
          <0 344 4>;
    interrupt-names = "peripheral",
        "host",
        "otg";
    maximum-speed = "high-speed";
    dr_mode = "otg";
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
   };
  };

  elm: elm@48078000 {
   compatible = "ti,am3352-elm";
   reg = <0x48078000 0xfc0>;
   interrupts = <0 1 4>;
   ti,hwmods = "elm";
   status = "disabled";
  };

  gpmc: gpmc@50000000 {
   compatible = "ti,am3352-gpmc";
   ti,hwmods = "gpmc";
   reg = <0x50000000 0x37c>;
   interrupts = <0 15 4>;
   dmas = <&edma_xbar 4 0>;
   dma-names = "rxtx";
   gpmc,num-cs = <8>;
   gpmc,num-waitpins = <2>;
   #address-cells = <2>;
   #size-cells = <1>;
   interrupt-controller;
   #interrupt-cells = <2>;
   gpio-controller;
   #gpio-cells = <2>;
   status = "disabled";
  };

  atl: atl@4843c000 {
   compatible = "ti,dra7-atl";
   reg = <0x4843c000 0x3ff>;
   ti,hwmods = "atl";
   ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
          <&atl_clkin2_ck>, <&atl_clkin3_ck>;
   clocks = <&atl_gfclk_mux>;
   clock-names = "fck";
   status = "disabled";
  };

  mcasp1: mcasp@48460000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp1";
   reg = <0x48460000 0x2000>,
         <0x45800000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 104 4>,
         <0 103 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
     <&mcasp1_ahclkr_mux>;
   clock-names = "fck", "ahclkx", "ahclkr";
   status = "disabled";
  };

  mcasp2: mcasp@48464000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp2";
   reg = <0x48464000 0x2000>,
         <0x45c00000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 149 4>,
         <0 148 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
     <&mcasp2_ahclkr_mux>;
   clock-names = "fck", "ahclkx", "ahclkr";
   status = "disabled";
  };

  mcasp3: mcasp@48468000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp3";
   reg = <0x48468000 0x2000>,
         <0x46000000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 151 4>,
         <0 150 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp4: mcasp@4846c000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp4";
   reg = <0x4846c000 0x2000>,
         <0x48436000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 153 4>,
         <0 152 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp5: mcasp@48470000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp5";
   reg = <0x48470000 0x2000>,
         <0x4843a000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 155 4>,
         <0 154 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp6: mcasp@48474000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp6";
   reg = <0x48474000 0x2000>,
         <0x4844c000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 157 4>,
         <0 156 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp7: mcasp@48478000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp7";
   reg = <0x48478000 0x2000>,
         <0x48450000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 159 4>,
         <0 158 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp8: mcasp@4847c000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp8";
   reg = <0x4847c000 0x2000>,
         <0x48454000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 161 4>,
         <0 160 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
   dma-names = "tx", "rx";
   clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  crossbar_mpu: crossbar@4a002a48 {
   compatible = "ti,irq-crossbar";
   reg = <0x4a002a48 0x130>;
   interrupt-controller;
   interrupt-parent = <&wakeupgen>;
   #interrupt-cells = <3>;
   ti,max-irqs = <160>;
   ti,max-crossbar-sources = <400>;
   ti,reg-size = <2>;
   ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
   ti,irqs-skip = <10 133 139 140>;
   ti,irqs-safe-map = <0>;
  };

  mac: ethernet@48484000 {
   compatible = "ti,dra7-cpsw","ti,cpsw";
   ti,hwmods = "gmac";
   clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
   clock-names = "fck", "cpts";
   cpdma_channels = <8>;
   ale_entries = <1024>;
   bd_ram_size = <0x2000>;
   mac_control = <0x20>;
   slaves = <2>;
   active_slave = <0>;
   cpts_clock_mult = <0x784CFE14>;
   cpts_clock_shift = <29>;
   reg = <0x48484000 0x1000
          0x48485200 0x2E00>;
   #address-cells = <1>;
   #size-cells = <1>;
# 1793 "../arch/arm/dts/dra7.dtsi"
   ti,no-idle;







   interrupts = <0 334 4>,
         <0 335 4>,
         <0 336 4>,
         <0 337 4>;
   ranges;
   syscon = <&scm_conf>;
   status = "disabled";

   davinci_mdio: mdio@48485000 {
    compatible = "ti,cpsw-mdio","ti,davinci_mdio";
    #address-cells = <1>;
    #size-cells = <0>;
    ti,hwmods = "davinci_mdio";
    bus_freq = <1000000>;
    reg = <0x48485000 0x100>;
   };

   cpsw_emac0: slave@48480200 {

    mac-address = [ 00 00 00 00 00 00 ];
   };

   cpsw_emac1: slave@48480300 {

    mac-address = [ 00 00 00 00 00 00 ];
   };

   phy_sel: cpsw-phy-sel@4a002554 {
    compatible = "ti,dra7xx-cpsw-phy-sel";
    reg= <0x4a002554 0x4>;
    reg-names = "gmii-sel";
   };
  };

  dcan1: can@481cc000 {
   compatible = "ti,dra7-d_can";
   ti,hwmods = "dcan1";
   reg = <0x4ae3c000 0x2000>;
   syscon-raminit = <&scm_conf 0x558 0>;
   interrupts = <0 222 4>;
   clocks = <&dcan1_sys_clk_mux>;
   status = "disabled";
  };

  dcan2: can@481d0000 {
   compatible = "ti,dra7-d_can";
   ti,hwmods = "dcan2";
   reg = <0x48480000 0x2000>;
   syscon-raminit = <&scm_conf 0x558 1>;
   interrupts = <0 225 4>;
   clocks = <&sys_clkin1>;
   status = "disabled";
  };

  dss: dss@58000000 {
   compatible = "ti,dra7-dss";


   status = "disabled";
   ti,hwmods = "dss_core";

   syscon-pll-ctrl = <&scm_conf 0x538>;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;

   dispc@58001000 {
    compatible = "ti,dra7-dispc";
    reg = <0x58001000 0x1000>;
    interrupts = <0 20 4>;
    ti,hwmods = "dss_dispc";
    clocks = <&dss_dss_clk>;
    clock-names = "fck";

    syscon-pol = <&scm_conf 0x534>;
   };

   hdmi: encoder@58060000 {
    compatible = "ti,dra7-hdmi";
    reg = <0x58040000 0x200>,
          <0x58040200 0x80>,
          <0x58040300 0x80>,
          <0x58060000 0x19000>;
    reg-names = "wp", "pll", "phy", "core";
    interrupts = <0 96 4>;
    status = "disabled";
    ti,hwmods = "dss_hdmi";
    clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
    clock-names = "fck", "sys_clk";
   };
  };

  epwmss0: epwmss@4843e000 {
   compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
   reg = <0x4843e000 0x30>;
   ti,hwmods = "epwmss0";
   #address-cells = <1>;
   #size-cells = <1>;
   status = "disabled";
   ranges;

   ehrpwm0: pwm@4843e200 {
    compatible = "ti,dra746-ehrpwm",
          "ti,am3352-ehrpwm";
    #pwm-cells = <3>;
    reg = <0x4843e200 0x80>;
    clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
    clock-names = "tbclk", "fck";
    status = "disabled";
   };

   ecap0: ecap@4843e100 {
    compatible = "ti,dra746-ecap",
          "ti,am3352-ecap";
    #pwm-cells = <3>;
    reg = <0x4843e100 0x80>;
    clocks = <&l4_root_clk_div>;
    clock-names = "fck";
    status = "disabled";
   };
  };

  epwmss1: epwmss@48440000 {
   compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
   reg = <0x48440000 0x30>;
   ti,hwmods = "epwmss1";
   #address-cells = <1>;
   #size-cells = <1>;
   status = "disabled";
   ranges;

   ehrpwm1: pwm@48440200 {
    compatible = "ti,dra746-ehrpwm",
          "ti,am3352-ehrpwm";
    #pwm-cells = <3>;
    reg = <0x48440200 0x80>;
    clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
    clock-names = "tbclk", "fck";
    status = "disabled";
   };

   ecap1: ecap@48440100 {
    compatible = "ti,dra746-ecap",
          "ti,am3352-ecap";
    #pwm-cells = <3>;
    reg = <0x48440100 0x80>;
    clocks = <&l4_root_clk_div>;
    clock-names = "fck";
    status = "disabled";
   };
  };

  epwmss2: epwmss@48442000 {
   compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
   reg = <0x48442000 0x30>;
   ti,hwmods = "epwmss2";
   #address-cells = <1>;
   #size-cells = <1>;
   status = "disabled";
   ranges;

   ehrpwm2: pwm@48442200 {
    compatible = "ti,dra746-ehrpwm",
          "ti,am3352-ehrpwm";
    #pwm-cells = <3>;
    reg = <0x48442200 0x80>;
    clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
    clock-names = "tbclk", "fck";
    status = "disabled";
   };

   ecap2: ecap@48442100 {
    compatible = "ti,dra746-ecap",
          "ti,am3352-ecap";
    #pwm-cells = <3>;
    reg = <0x48442100 0x80>;
    clocks = <&l4_root_clk_div>;
    clock-names = "fck";
    status = "disabled";
   };
  };

  aes1: aes@4b500000 {
   compatible = "ti,omap4-aes";
   ti,hwmods = "aes1";
   reg = <0x4b500000 0xa0>;
   interrupts = <0 80 4>;
   dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
   dma-names = "tx", "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  aes2: aes@4b700000 {
   compatible = "ti,omap4-aes";
   ti,hwmods = "aes2";
   reg = <0x4b700000 0xa0>;
   interrupts = <0 59 4>;
   dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
   dma-names = "tx", "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  des: des@480a5000 {
   compatible = "ti,omap4-des";
   ti,hwmods = "des";
   reg = <0x480a5000 0xa0>;
   interrupts = <0 77 4>;
   dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
   dma-names = "tx", "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  sham: sham@53100000 {
   compatible = "ti,omap5-sham";
   ti,hwmods = "sham";
   reg = <0x4b101000 0x300>;
   interrupts = <0 46 4>;
   dmas = <&edma_xbar 119 0>;
   dma-names = "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  rng: rng@48090000 {
   compatible = "ti,omap4-rng";
   ti,hwmods = "rng";
   reg = <0x48090000 0x2000>;
   interrupts = <0 47 4>;
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };
 };

 thermal_zones: thermal-zones {
# 1 "../arch/arm/dts/omap4-cpu-thermal.dtsi" 1
# 12 "../arch/arm/dts/omap4-cpu-thermal.dtsi"
# 1 "../arch/arm/dts/include/dt-bindings/thermal/thermal.h" 1
# 13 "../arch/arm/dts/omap4-cpu-thermal.dtsi" 2

cpu_thermal: cpu_thermal {
 polling-delay-passive = <250>;
 polling-delay = <1000>;


        thermal-sensors = <&bandgap 0>;

 cpu_trips: trips {
                cpu_alert0: cpu_alert {
                        temperature = <100000>;
                        hysteresis = <2000>;
                        type = "passive";
                };
                cpu_crit: cpu_crit {
                        temperature = <125000>;
                        hysteresis = <2000>;
                        type = "critical";
                };
        };

 cpu_cooling_maps: cooling-maps {
  map0 {
   trip = <&cpu_alert0>;
   cooling-device =
    <&cpu0 (~0) (~0)>;
  };
 };
};
# 2039 "../arch/arm/dts/dra7.dtsi" 2
# 1 "../arch/arm/dts/omap5-gpu-thermal.dtsi" 1
# 14 "../arch/arm/dts/omap5-gpu-thermal.dtsi"
gpu_thermal: gpu_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 1>;

 trips {
  gpu_crit: gpu_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2040 "../arch/arm/dts/dra7.dtsi" 2
# 1 "../arch/arm/dts/omap5-core-thermal.dtsi" 1
# 14 "../arch/arm/dts/omap5-core-thermal.dtsi"
core_thermal: core_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 2>;

 trips {
  core_crit: core_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2041 "../arch/arm/dts/dra7.dtsi" 2
# 1 "../arch/arm/dts/dra7-dspeve-thermal.dtsi" 1
# 13 "../arch/arm/dts/dra7-dspeve-thermal.dtsi"
dspeve_thermal: dspeve_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 3>;

 trips {
  dspeve_crit: dspeve_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2042 "../arch/arm/dts/dra7.dtsi" 2
# 1 "../arch/arm/dts/dra7-iva-thermal.dtsi" 1
# 13 "../arch/arm/dts/dra7-iva-thermal.dtsi"
iva_thermal: iva_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 4>;

 trips {
  iva_crit: iva_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2043 "../arch/arm/dts/dra7.dtsi" 2
 };

};

&cpu_thermal {
 polling-delay = <500>;
 coefficients = <0 2000>;
};

&gpu_thermal {
 coefficients = <0 2000>;
};

&core_thermal {
 coefficients = <0 2000>;
};

&dspeve_thermal {
 coefficients = <0 2000>;
};

&iva_thermal {
 coefficients = <0 2000>;
};

&cpu_crit {
 temperature = <120000>;
};

/include/ "dra7xx-clocks.dtsi"
# 11 "../arch/arm/dts/dra74x.dtsi" 2

/ {
 compatible = "ti,dra742", "ti,dra74", "ti,dra7";

 cpus {
  cpu@1 {
   device_type = "cpu";
   compatible = "arm,cortex-a15";
   reg = <1>;
   operating-points-v2 = <&cpu0_opp_table>;
  };
 };

 pmu {
  compatible = "arm,cortex-a15-pmu";
  interrupt-parent = <&wakeupgen>;
  interrupts = <0 131 4>,
        <0 132 4>;
 };

 ocp {
  dsp2_system: dsp_system@41500000 {
   compatible = "syscon";
   reg = <0x41500000 0x100>;
  };

  omap_dwc3_4: omap_dwc3_4@48940000 {
   compatible = "ti,dwc3";
   ti,hwmods = "usb_otg_ss4";
   reg = <0x48940000 0x10000>;
   interrupts = <0 346 4>;
   #address-cells = <1>;
   #size-cells = <1>;
   utmi-mode = <2>;
   ranges;
   status = "disabled";
   usb4: usb@48950000 {
    compatible = "snps,dwc3";
    reg = <0x48950000 0x17000>;
    interrupts = <0 345 4>,
          <0 345 4>,
          <0 346 4>;
    interrupt-names = "peripheral",
        "host",
        "otg";
    maximum-speed = "high-speed";
    dr_mode = "otg";
   };
  };

  mmu0_dsp2: mmu@41501000 {
   compatible = "ti,dra7-dsp-iommu";
   reg = <0x41501000 0x100>;
   interrupts = <0 146 4>;
   ti,hwmods = "mmu0_dsp2";
   #iommu-cells = <0>;
   ti,syscon-mmuconfig = <&dsp2_system 0x0>;
   status = "disabled";
  };

  mmu1_dsp2: mmu@41502000 {
   compatible = "ti,dra7-dsp-iommu";
   reg = <0x41502000 0x100>;
   interrupts = <0 147 4>;
   ti,hwmods = "mmu1_dsp2";
   #iommu-cells = <0>;
   ti,syscon-mmuconfig = <&dsp2_system 0x1>;
   status = "disabled";
  };
 };
};

&cpu0_opp_table {
 opp-shared;
};

&dss {
 reg = <0x58000000 0x80>,
       <0x58004054 0x4>,
       <0x58004300 0x20>,
       <0x58009054 0x4>,
       <0x58009300 0x20>;
 reg-names = "dss", "pll1_clkctrl", "pll1",
      "pll2_clkctrl", "pll2";

 clocks = <&dss_dss_clk>,
   <&dss_video1_clk>,
   <&dss_video2_clk>;
 clock-names = "fck", "video1_clk", "video2_clk";
};

&mailbox5 {
 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
  ti,mbox-tx = <6 2 2>;
  ti,mbox-rx = <4 2 2>;
  status = "disabled";
 };
 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
  ti,mbox-tx = <5 2 2>;
  ti,mbox-rx = <1 2 2>;
  status = "disabled";
 };
};

&mailbox6 {
 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
  ti,mbox-tx = <6 2 2>;
  ti,mbox-rx = <4 2 2>;
  status = "disabled";
 };
 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
  ti,mbox-tx = <5 2 2>;
  ti,mbox-rx = <1 2 2>;
  status = "disabled";
 };
};
# 11 "../arch/arm/dts/vau-p3-common.dtsi" 2
# 1 "../arch/arm/dts/am57xx-commercial-grade.dtsi" 1

&cpu_alert0 {
 temperature = <80000>;
};

&cpu_crit {
 temperature = <90000>;
};

&gpu_crit {
 temperature = <90000>;
};

&core_crit {
 temperature = <90000>;
};

&dspeve_crit {
 temperature = <90000>;
};

&iva_crit {
 temperature = <90000>;
};
# 12 "../arch/arm/dts/vau-p3-common.dtsi" 2
# 1 "../arch/arm/dts/dra74x-mmc-iodelay.dtsi" 1
# 40 "../arch/arm/dts/dra74x-mmc-iodelay.dtsi"
&dra7_pmx_core {
 mmc1_pins_default: mmc1_pins_default {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
  >;
 };

 mmc1_pins_sdr12: mmc1_pins_sdr12 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
  >;
 };

 mmc1_pins_hs: mmc1_pins_hs {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
  >;
 };

 mmc1_pins_sdr25: mmc1_pins_sdr25 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xb << 4)) | 0x0)
  >;
 };

 mmc1_pins_sdr50: mmc1_pins_sdr50 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xa << 4)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xa << 4)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xa << 4)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xa << 4)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xa << 4)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xa << 4)) | 0x0)
  >;
 };

 mmc1_pins_ddr50: mmc1_pins_ddr50 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
  >;
 };

 mmc1_pins_sdr104: mmc1_pins_sdr104 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
  >;
 };

 mmc2_pins_default: mmc2_pins_default {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
  >;
 };

 mmc2_pins_hs: mmc2_pins_hs {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
  >;
 };

 mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
  >;
 };

 mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
  >;
 };

 mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
  >;
 };

 mmc2_pins_hs200: mmc2_pins_hs200 {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
  >;
 };

 mmc4_pins_default: mmc4_pins_default {
  pinctrl-single,pins = <
   (((0x37e8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37ec) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37fc) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
  >;
 };

 mmc4_pins_hs: mmc4_pins_hs {
  pinctrl-single,pins = <
   (((0x37e8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37ec) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37fc) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
  >;
 };

 mmc3_pins_default: mmc3_pins_default {
  pinctrl-single,pins = <
   (((0x377c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3780) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3784) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3788) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x378c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3790) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
  >;
 };

 mmc3_pins_hs: mmc3_pins_hs {
  pinctrl-single,pins = <
   (((0x377c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3780) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3784) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3788) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x378c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3790) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
  >;
 };

 mmc3_pins_sdr12: mmc3_pins_sdr12 {
  pinctrl-single,pins = <
   (((0x377c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3780) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3784) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3788) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x378c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3790) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
  >;
 };

 mmc3_pins_sdr25: mmc3_pins_sdr25 {
  pinctrl-single,pins = <
   (((0x377c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3780) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3784) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3788) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x378c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
   (((0x3790) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | 0x0))
  >;
 };

 mmc3_pins_sdr50: mmc3_pins_sdr50 {
  pinctrl-single,pins = <
   (((0x377c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0))
   (((0x3780) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0))
   (((0x3784) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0))
   (((0x3788) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0))
   (((0x378c) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0))
   (((0x3790) & 0xffff) - 0x3400) ((((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0))
  >;
 };

 mmc4_pins_sdr12: mmc4_pins_sdr12 {
  pinctrl-single,pins = <
   (((0x37e8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37ec) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37fc) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
  >;
 };

 mmc4_pins_sdr25: mmc4_pins_sdr25 {
  pinctrl-single,pins = <
   (((0x37e8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37ec) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37f8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
   (((0x37fc) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x3)
  >;
 };
};

&dra7_iodelay_core {


 mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf {
  pinctrl-pin-array = <
   0x618 ((572) & 0xffff) ((540) & 0xffff)
   0x620 ((1525) & 0xffff) ((0) & 0xffff)
   0x624 ((0) & 0xffff) ((600) & 0xffff)
   0x628 ((0) & 0xffff) ((0) & 0xffff)
   0x62c ((55) & 0xffff) ((0) & 0xffff)
   0x630 ((403) & 0xffff) ((120) & 0xffff)
   0x634 ((0) & 0xffff) ((0) & 0xffff)
   0x638 ((0) & 0xffff) ((0) & 0xffff)
   0x63c ((23) & 0xffff) ((60) & 0xffff)
   0x640 ((0) & 0xffff) ((0) & 0xffff)
   0x644 ((0) & 0xffff) ((0) & 0xffff)
   0x648 ((25) & 0xffff) ((60) & 0xffff)
   0x64c ((0) & 0xffff) ((0) & 0xffff)
   0x650 ((0) & 0xffff) ((0) & 0xffff)
   0x654 ((0) & 0xffff) ((0) & 0xffff)
   0x658 ((0) & 0xffff) ((0) & 0xffff)
   0x65c ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
  pinctrl-pin-array = <
   0x618 ((1076) & 0xffff) ((330) & 0xffff)
   0x620 ((1271) & 0xffff) ((0) & 0xffff)
   0x624 ((722) & 0xffff) ((0) & 0xffff)
   0x628 ((0) & 0xffff) ((0) & 0xffff)
   0x62C ((0) & 0xffff) ((0) & 0xffff)
   0x630 ((751) & 0xffff) ((0) & 0xffff)
   0x634 ((0) & 0xffff) ((0) & 0xffff)
   0x638 ((20) & 0xffff) ((0) & 0xffff)
   0x63C ((256) & 0xffff) ((0) & 0xffff)
   0x640 ((0) & 0xffff) ((0) & 0xffff)
   0x644 ((0) & 0xffff) ((0) & 0xffff)
   0x648 ((263) & 0xffff) ((0) & 0xffff)
   0x64C ((0) & 0xffff) ((0) & 0xffff)
   0x650 ((0) & 0xffff) ((0) & 0xffff)
   0x654 ((0) & 0xffff) ((0) & 0xffff)
   0x658 ((0) & 0xffff) ((0) & 0xffff)
   0x65C ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
  pinctrl-pin-array = <
   0x620 ((1063) & 0xffff) ((17) & 0xffff)
   0x628 ((0) & 0xffff) ((0) & 0xffff)
   0x62c ((23) & 0xffff) ((0) & 0xffff)
   0x634 ((0) & 0xffff) ((0) & 0xffff)
   0x638 ((0) & 0xffff) ((0) & 0xffff)
   0x640 ((0) & 0xffff) ((0) & 0xffff)
   0x644 ((2) & 0xffff) ((0) & 0xffff)
   0x64c ((0) & 0xffff) ((0) & 0xffff)
   0x650 ((0) & 0xffff) ((0) & 0xffff)
   0x658 ((0) & 0xffff) ((0) & 0xffff)
   0x65c ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
  pinctrl-pin-array = <
   0x620 ((600) & 0xffff) ((400) & 0xffff)
   0x628 ((0) & 0xffff) ((0) & 0xffff)
   0x62c ((0) & 0xffff) ((0) & 0xffff)
   0x634 ((0) & 0xffff) ((0) & 0xffff)
   0x638 ((30) & 0xffff) ((0) & 0xffff)
   0x640 ((0) & 0xffff) ((0) & 0xffff)
   0x644 ((0) & 0xffff) ((0) & 0xffff)
   0x64c ((0) & 0xffff) ((0) & 0xffff)
   0x650 ((0) & 0xffff) ((0) & 0xffff)
   0x658 ((0) & 0xffff) ((0) & 0xffff)
   0x65c ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf {
  pinctrl-pin-array = <
   0x190 ((621) & 0xffff) ((600) & 0xffff)
   0x194 ((300) & 0xffff) ((0) & 0xffff)
   0x1a8 ((739) & 0xffff) ((600) & 0xffff)
   0x1ac ((240) & 0xffff) ((0) & 0xffff)
   0x1b4 ((812) & 0xffff) ((600) & 0xffff)
   0x1b8 ((240) & 0xffff) ((0) & 0xffff)
   0x1c0 ((954) & 0xffff) ((600) & 0xffff)
   0x1c4 ((60) & 0xffff) ((0) & 0xffff)
   0x1d0 ((1340) & 0xffff) ((420) & 0xffff)
   0x1d8 ((935) & 0xffff) ((600) & 0xffff)
   0x1dc ((0) & 0xffff) ((0) & 0xffff)
   0x1e4 ((525) & 0xffff) ((600) & 0xffff)
   0x1e8 ((120) & 0xffff) ((0) & 0xffff)
   0x1f0 ((767) & 0xffff) ((600) & 0xffff)
   0x1f4 ((225) & 0xffff) ((0) & 0xffff)
   0x1fc ((565) & 0xffff) ((600) & 0xffff)
   0x200 ((60) & 0xffff) ((0) & 0xffff)
   0x364 ((969) & 0xffff) ((600) & 0xffff)
   0x368 ((180) & 0xffff) ((0) & 0xffff)
       >;
 };


 mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
  pinctrl-pin-array = <
   0x190 ((274) & 0xffff) ((0) & 0xffff)
   0x194 ((162) & 0xffff) ((0) & 0xffff)
   0x1a8 ((401) & 0xffff) ((0) & 0xffff)
   0x1ac ((73) & 0xffff) ((0) & 0xffff)
   0x1b4 ((465) & 0xffff) ((0) & 0xffff)
   0x1b8 ((115) & 0xffff) ((0) & 0xffff)
   0x1c0 ((633) & 0xffff) ((0) & 0xffff)
   0x1c4 ((47) & 0xffff) ((0) & 0xffff)
   0x1d0 ((935) & 0xffff) ((280) & 0xffff)
   0x1d8 ((621) & 0xffff) ((0) & 0xffff)
   0x1dc ((0) & 0xffff) ((0) & 0xffff)
   0x1e4 ((183) & 0xffff) ((0) & 0xffff)
   0x1e8 ((0) & 0xffff) ((0) & 0xffff)
   0x1f0 ((467) & 0xffff) ((0) & 0xffff)
   0x1f4 ((0) & 0xffff) ((0) & 0xffff)
   0x1fc ((262) & 0xffff) ((0) & 0xffff)
   0x200 ((46) & 0xffff) ((0) & 0xffff)
   0x364 ((684) & 0xffff) ((0) & 0xffff)
   0x368 ((76) & 0xffff) ((0) & 0xffff)
       >;
 };


 mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf {
  pinctrl-pin-array = <
   0x18c ((0) & 0xffff) ((120) & 0xffff)
   0x190 ((0) & 0xffff) ((0) & 0xffff)
   0x194 ((174) & 0xffff) ((0) & 0xffff)
   0x1a4 ((265) & 0xffff) ((360) & 0xffff)
   0x1a8 ((0) & 0xffff) ((0) & 0xffff)
   0x1ac ((168) & 0xffff) ((0) & 0xffff)
   0x1b0 ((0) & 0xffff) ((120) & 0xffff)
   0x1b4 ((0) & 0xffff) ((0) & 0xffff)
   0x1b8 ((136) & 0xffff) ((0) & 0xffff)
   0x1bc ((0) & 0xffff) ((120) & 0xffff)
   0x1c0 ((0) & 0xffff) ((0) & 0xffff)
   0x1c4 ((0) & 0xffff) ((0) & 0xffff)
   0x1c8 ((287) & 0xffff) ((420) & 0xffff)
   0x1d0 ((879) & 0xffff) ((0) & 0xffff)
   0x1d4 ((144) & 0xffff) ((240) & 0xffff)
   0x1d8 ((0) & 0xffff) ((0) & 0xffff)
   0x1dc ((0) & 0xffff) ((0) & 0xffff)
   0x1e0 ((0) & 0xffff) ((0) & 0xffff)
   0x1e4 ((0) & 0xffff) ((0) & 0xffff)
   0x1e8 ((34) & 0xffff) ((0) & 0xffff)
   0x1ec ((0) & 0xffff) ((120) & 0xffff)
   0x1f0 ((0) & 0xffff) ((0) & 0xffff)
   0x1f4 ((120) & 0xffff) ((0) & 0xffff)
   0x1f8 ((120) & 0xffff) ((180) & 0xffff)
   0x1fc ((0) & 0xffff) ((0) & 0xffff)
   0x200 ((0) & 0xffff) ((0) & 0xffff)
   0x360 ((0) & 0xffff) ((0) & 0xffff)
   0x364 ((0) & 0xffff) ((0) & 0xffff)
   0x368 ((11) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
  pinctrl-pin-array = <
   0x18c ((0) & 0xffff) ((0) & 0xffff)
   0x190 ((0) & 0xffff) ((0) & 0xffff)
   0x194 ((174) & 0xffff) ((0) & 0xffff)
   0x1a4 ((274) & 0xffff) ((240) & 0xffff)
   0x1a8 ((0) & 0xffff) ((0) & 0xffff)
   0x1ac ((168) & 0xffff) ((0) & 0xffff)
   0x1b0 ((0) & 0xffff) ((60) & 0xffff)
   0x1b4 ((0) & 0xffff) ((0) & 0xffff)
   0x1b8 ((136) & 0xffff) ((0) & 0xffff)
   0x1bc ((0) & 0xffff) ((60) & 0xffff)
   0x1c0 ((0) & 0xffff) ((0) & 0xffff)
   0x1c4 ((0) & 0xffff) ((0) & 0xffff)
   0x1c8 ((514) & 0xffff) ((360) & 0xffff)
   0x1d0 ((879) & 0xffff) ((0) & 0xffff)
   0x1d4 ((187) & 0xffff) ((120) & 0xffff)
   0x1d8 ((0) & 0xffff) ((0) & 0xffff)
   0x1dc ((0) & 0xffff) ((0) & 0xffff)
   0x1e0 ((0) & 0xffff) ((0) & 0xffff)
   0x1e4 ((0) & 0xffff) ((0) & 0xffff)
   0x1e8 ((34) & 0xffff) ((0) & 0xffff)
   0x1ec ((0) & 0xffff) ((60) & 0xffff)
   0x1f0 ((0) & 0xffff) ((0) & 0xffff)
   0x1f4 ((120) & 0xffff) ((0) & 0xffff)
   0x1f8 ((121) & 0xffff) ((60) & 0xffff)
   0x1fc ((0) & 0xffff) ((0) & 0xffff)
   0x200 ((0) & 0xffff) ((0) & 0xffff)
   0x360 ((0) & 0xffff) ((0) & 0xffff)
   0x364 ((0) & 0xffff) ((0) & 0xffff)
   0x368 ((11) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf {
  pinctrl-pin-array = <
   0x678 ((0) & 0xffff) ((386) & 0xffff)
   0x680 ((605) & 0xffff) ((0) & 0xffff)
   0x684 ((0) & 0xffff) ((0) & 0xffff)
   0x688 ((0) & 0xffff) ((0) & 0xffff)
   0x68c ((0) & 0xffff) ((0) & 0xffff)
   0x690 ((171) & 0xffff) ((0) & 0xffff)
   0x694 ((0) & 0xffff) ((0) & 0xffff)
   0x698 ((0) & 0xffff) ((0) & 0xffff)
   0x69c ((221) & 0xffff) ((0) & 0xffff)
   0x6a0 ((0) & 0xffff) ((0) & 0xffff)
   0x6a4 ((0) & 0xffff) ((0) & 0xffff)
   0x6a8 ((0) & 0xffff) ((0) & 0xffff)
   0x6ac ((0) & 0xffff) ((0) & 0xffff)
   0x6b0 ((0) & 0xffff) ((0) & 0xffff)
   0x6b4 ((474) & 0xffff) ((0) & 0xffff)
   0x6b8 ((0) & 0xffff) ((0) & 0xffff)
   0x6bc ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf {
  pinctrl-pin-array = <
   0x678 ((406) & 0xffff) ((0) & 0xffff)
   0x680 ((659) & 0xffff) ((0) & 0xffff)
   0x684 ((0) & 0xffff) ((0) & 0xffff)
   0x688 ((0) & 0xffff) ((0) & 0xffff)
   0x68c ((0) & 0xffff) ((0) & 0xffff)
   0x690 ((130) & 0xffff) ((0) & 0xffff)
   0x694 ((0) & 0xffff) ((0) & 0xffff)
   0x698 ((0) & 0xffff) ((0) & 0xffff)
   0x69c ((169) & 0xffff) ((0) & 0xffff)
   0x6a0 ((0) & 0xffff) ((0) & 0xffff)
   0x6a4 ((0) & 0xffff) ((0) & 0xffff)
   0x6a8 ((0) & 0xffff) ((0) & 0xffff)
   0x6ac ((0) & 0xffff) ((0) & 0xffff)
   0x6b0 ((0) & 0xffff) ((0) & 0xffff)
   0x6b4 ((457) & 0xffff) ((0) & 0xffff)
   0x6b8 ((0) & 0xffff) ((0) & 0xffff)
   0x6bc ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
  pinctrl-pin-array = <
   0x840 ((0) & 0xffff) ((0) & 0xffff)
   0x848 ((0) & 0xffff) ((0) & 0xffff)
   0x84c ((96) & 0xffff) ((0) & 0xffff)
   0x850 ((0) & 0xffff) ((0) & 0xffff)
   0x854 ((0) & 0xffff) ((0) & 0xffff)
   0x870 ((582) & 0xffff) ((0) & 0xffff)
   0x874 ((0) & 0xffff) ((0) & 0xffff)
   0x878 ((0) & 0xffff) ((0) & 0xffff)
   0x87c ((391) & 0xffff) ((0) & 0xffff)
   0x880 ((0) & 0xffff) ((0) & 0xffff)
   0x884 ((0) & 0xffff) ((0) & 0xffff)
   0x888 ((561) & 0xffff) ((0) & 0xffff)
   0x88c ((0) & 0xffff) ((0) & 0xffff)
   0x890 ((0) & 0xffff) ((0) & 0xffff)
   0x894 ((588) & 0xffff) ((0) & 0xffff)
   0x898 ((0) & 0xffff) ((0) & 0xffff)
   0x89c ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
  pinctrl-pin-array = <
   0x840 ((0) & 0xffff) ((0) & 0xffff)
   0x848 ((0) & 0xffff) ((0) & 0xffff)
   0x84c ((307) & 0xffff) ((0) & 0xffff)
   0x850 ((0) & 0xffff) ((0) & 0xffff)
   0x854 ((0) & 0xffff) ((0) & 0xffff)
   0x870 ((785) & 0xffff) ((0) & 0xffff)
   0x874 ((0) & 0xffff) ((0) & 0xffff)
   0x878 ((0) & 0xffff) ((0) & 0xffff)
   0x87c ((613) & 0xffff) ((0) & 0xffff)
   0x880 ((0) & 0xffff) ((0) & 0xffff)
   0x884 ((0) & 0xffff) ((0) & 0xffff)
   0x888 ((683) & 0xffff) ((0) & 0xffff)
   0x88c ((0) & 0xffff) ((0) & 0xffff)
   0x890 ((0) & 0xffff) ((0) & 0xffff)
   0x894 ((835) & 0xffff) ((0) & 0xffff)
   0x898 ((0) & 0xffff) ((0) & 0xffff)
   0x89c ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
  pinctrl-pin-array = <
   0x840 ((0) & 0xffff) ((0) & 0xffff)
   0x848 ((2651) & 0xffff) ((0) & 0xffff)
   0x84c ((1572) & 0xffff) ((0) & 0xffff)
   0x850 ((0) & 0xffff) ((0) & 0xffff)
   0x854 ((0) & 0xffff) ((0) & 0xffff)
   0x870 ((1913) & 0xffff) ((0) & 0xffff)
   0x874 ((0) & 0xffff) ((0) & 0xffff)
   0x878 ((0) & 0xffff) ((0) & 0xffff)
   0x87c ((1721) & 0xffff) ((0) & 0xffff)
   0x880 ((0) & 0xffff) ((0) & 0xffff)
   0x884 ((0) & 0xffff) ((0) & 0xffff)
   0x888 ((1891) & 0xffff) ((0) & 0xffff)
   0x88c ((0) & 0xffff) ((0) & 0xffff)
   0x890 ((0) & 0xffff) ((0) & 0xffff)
   0x894 ((1919) & 0xffff) ((0) & 0xffff)
   0x898 ((0) & 0xffff) ((0) & 0xffff)
   0x89c ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
  pinctrl-pin-array = <
   0x840 ((0) & 0xffff) ((0) & 0xffff)
   0x848 ((1147) & 0xffff) ((0) & 0xffff)
   0x84c ((1834) & 0xffff) ((0) & 0xffff)
   0x850 ((0) & 0xffff) ((0) & 0xffff)
   0x854 ((0) & 0xffff) ((0) & 0xffff)
   0x870 ((2165) & 0xffff) ((0) & 0xffff)
   0x874 ((0) & 0xffff) ((0) & 0xffff)
   0x878 ((0) & 0xffff) ((0) & 0xffff)
   0x87c ((1929) & 0xffff) ((64) & 0xffff)
   0x880 ((0) & 0xffff) ((0) & 0xffff)
   0x884 ((0) & 0xffff) ((0) & 0xffff)
   0x888 ((1935) & 0xffff) ((128) & 0xffff)
   0x88c ((0) & 0xffff) ((0) & 0xffff)
   0x890 ((0) & 0xffff) ((0) & 0xffff)
   0x894 ((2172) & 0xffff) ((44) & 0xffff)
   0x898 ((0) & 0xffff) ((0) & 0xffff)
   0x89c ((0) & 0xffff) ((0) & 0xffff)
  >;
 };
};
# 13 "../arch/arm/dts/vau-p3-common.dtsi" 2
# 1 "../arch/arm/dts/include/dt-bindings/gpio/gpio.h" 1
# 14 "../arch/arm/dts/vau-p3-common.dtsi" 2

# 1 "../arch/arm/dts/include/dt-bindings/net/ti-dp83867.h" 1
# 16 "../arch/arm/dts/vau-p3-common.dtsi" 2
# 65 "../arch/arm/dts/vau-p3-common.dtsi"
/ {
 compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7", "red-ant,vau-p3";

 aliases {
  rtc0 = &mcp_rtc;
  rtc1 = &tps659038_rtc;
  rtc2 = &rtc;
  display0 = &hdmi0;
 };

 chosen {
  stdout-path = &uart3;
 };

 memory@0 {
  device_type = "memory";
  reg = <0x0 0x80000000 0x0 0x80000000>;
 };

 vdd_3v3: fixedregulator-vdd_3v3 {
  compatible = "regulator-fixed";
  regulator-name = "vdd_3v3";
  vin-supply = <&regen1>;
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
 };

 aic_dvdd: fixedregulator-aic_dvdd {
  compatible = "regulator-fixed";
  regulator-name = "aic_dvdd_fixed";
  vin-supply = <&vdd_3v3>;
  regulator-min-microvolt = <1800000>;
  regulator-max-microvolt = <1800000>;
 };

 vtt_fixed: fixedregulator-vtt {

  compatible = "regulator-fixed";
  regulator-name = "vtt_fixed";
  vin-supply = <&smps3_reg>;
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
  regulator-always-on;
  regulator-boot-on;
  enable-active-high;
  gpio = <&gpio7 11 0>;
 };

 leds {
  compatible = "gpio-leds";

  led0 {
   label = "beagle-x15:usr0";
   gpios = <&gpio7 9 0>;
   linux,default-trigger = "heartbeat";
   default-state = "off";
  };

  led1 {
   label = "beagle-x15:usr1";
   gpios = <&gpio7 8 0>;
   linux,default-trigger = "cpu0";
   default-state = "off";
  };

  led2 {
   label = "beagle-x15:usr2";
   gpios = <&gpio7 14 0>;
   linux,default-trigger = "mmc0";
   default-state = "off";
  };

  led3 {
   label = "beagle-x15:usr3";
   gpios = <&gpio7 15 0>;
   linux,default-trigger = "disk-activity";
   default-state = "off";
  };
 };

 gpio_fan: gpio_fan {

  compatible = "gpio-fan";
  gpios = <&tps659038_gpio 2 0>;
  gpio-fan,speed-map = <0 0>,
         <13000 1>;
  #cooling-cells = <2>;
 };

 hdmi0: connector {
  compatible = "hdmi-connector";
  label = "hdmi";

  type = "a";

  port {
   hdmi_connector_in: endpoint {
    remote-endpoint = <&tpd12s015_out>;
   };
  };
 };

 tpd12s015: encoder {
  compatible = "ti,tpd12s015";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;

    tpd12s015_in: endpoint {
     remote-endpoint = <&hdmi_out>;
    };
   };

   port@1 {
    reg = <1>;

    tpd12s015_out: endpoint {
     remote-endpoint = <&hdmi_connector_in>;
    };
   };
  };
 };

 sound0: sound0 {
  compatible = "simple-audio-card";
  simple-audio-card,name = "BeagleBoard-X15";
  simple-audio-card,widgets =
   "Line", "Line Out",
   "Line", "Line In";
  simple-audio-card,routing =
   "Line Out", "LLOUT",
   "Line Out", "RLOUT",
   "MIC2L", "Line In",
   "MIC2R", "Line In";
  simple-audio-card,format = "dsp_b";
  simple-audio-card,bitclock-master = <&sound0_master>;
  simple-audio-card,frame-master = <&sound0_master>;
  simple-audio-card,bitclock-inversion;

  simple-audio-card,cpu {
   sound-dai = <&mcasp3>;
  };

  sound0_master: simple-audio-card,codec {
   sound-dai = <&tlv320aic3104>;
   clocks = <&clkout2_clk>;
  };
 };
};

&i2c1 {
 status = "okay";
 clock-frequency = <400000>;

 tps659038: tps659038@58 {
  compatible = "ti,tps659038";
  reg = <0x58>;
  interrupt-parent = <&gpio1>;
  interrupts = <0 8>;

  #interrupt-cells = <2>;
  interrupt-controller;

  ti,system-power-controller;
  ti,palmas-override-powerhold;

  tps659038_pmic {
   compatible = "ti,tps659038-pmic";

   regulators {
    smps12_reg: smps12 {

     regulator-name = "smps12";
     regulator-min-microvolt = < 850000>;
     regulator-max-microvolt = <1250000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps3_reg: smps3 {

     regulator-name = "smps3";
     regulator-min-microvolt = <1350000>;
     regulator-max-microvolt = <1350000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps45_reg: smps45 {

     regulator-name = "smps45";
     regulator-min-microvolt = < 850000>;
     regulator-max-microvolt = <1250000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps6_reg: smps6 {

     regulator-name = "smps6";
     regulator-min-microvolt = <850000>;
     regulator-max-microvolt = <1150000>;
     regulator-always-on;
     regulator-boot-on;
    };



    smps8_reg: smps8 {

     regulator-name = "smps8";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };



    ldo1_reg: ldo1 {

     regulator-name = "ldo1";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <3300000>;
     regulator-boot-on;
     regulator-always-on;
    };

    ldo2_reg: ldo2 {

     regulator-name = "ldo2";
     regulator-min-microvolt = <3300000>;
     regulator-max-microvolt = <3300000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldo3_reg: ldo3 {

     regulator-name = "ldo3";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldo4_reg: ldo4 {

     regulator-name = "ldo4";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldo9_reg: ldo9 {

     regulator-name = "ldo9";
     regulator-min-microvolt = <1050000>;
     regulator-max-microvolt = <1050000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldoln_reg: ldoln {

     regulator-name = "ldoln";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldousb_reg: ldousb {

     regulator-name = "ldousb";
     regulator-min-microvolt = <3300000>;
     regulator-max-microvolt = <3300000>;
     regulator-boot-on;
    };

    regen1: regen1 {

     regulator-name = "regen1";
     regulator-boot-on;
     regulator-always-on;
    };
   };
  };

  tps659038_rtc: tps659038_rtc {
   compatible = "ti,palmas-rtc";
   interrupt-parent = <&tps659038>;
   interrupts = <8 2>;
   wakeup-source;
  };

  tps659038_pwr_button: tps659038_pwr_button {
   compatible = "ti,palmas-pwrbutton";
   interrupt-parent = <&tps659038>;
   interrupts = <1 2>;
   wakeup-source;
   ti,palmas-long-press-seconds = <12>;
  };

  tps659038_gpio: tps659038_gpio {
   compatible = "ti,palmas-gpio";
   gpio-controller;
   #gpio-cells = <2>;
  };

  extcon_usb2: tps659038_usb {
   compatible = "ti,palmas-usb-vid";
   ti,enable-vbus-detection;
   vbus-gpio = <&gpio4 21 0>;
  };

 };

 tmp102: tmp102@48 {
  compatible = "ti,tmp102";
  reg = <0x48>;
  interrupt-parent = <&gpio7>;
  interrupts = <16 8>;
  #thermal-sensor-cells = <1>;
 };

 tlv320aic3104: tlv320aic3104@18 {
  #sound-dai-cells = <0>;
  compatible = "ti,tlv320aic3104";
  reg = <0x18>;
  assigned-clocks = <&clkoutmux2_clk_mux>;
  assigned-clock-parents = <&sys_clk2_dclk_div>;

  status = "okay";
  adc-settle-ms = <40>;

  AVDD-supply = <&vdd_3v3>;
  IOVDD-supply = <&vdd_3v3>;
  DRVDD-supply = <&vdd_3v3>;
  DVDD-supply = <&aic_dvdd>;
 };

 eeprom: eeprom@50 {
  compatible = "atmel,24c32";
  reg = <0x50>;
 };
};

&i2c3 {
 status = "okay";
 clock-frequency = <400000>;

 mcp_rtc: rtc@6f {
  compatible = "microchip,mcp7941x";
  reg = <0x6f>;
  interrupts-extended = <&crossbar_mpu 0 2 1>,
          <&dra7_pmx_core 0x424>;
  interrupt-names = "irq", "wakeup";

  vcc-supply = <&vdd_3v3>;
  wakeup-source;
 };
};

&gpio7 {
 ti,no-reset-on-init;
 ti,no-idle-on-init;
};

&cpu0 {
 cpu0-supply = <&smps12_reg>;
 voltage-tolerance = <1>;
};

&uart3 {
 status = "okay";
 interrupts-extended = <&crossbar_mpu 0 69 4>,
         <&dra7_pmx_core 0x3f8>;
};

&davinci_mdio {
 phy0: ethernet-phy@0 {
  reg = <0>;
  ti,rx-internal-delay = <0x8>;
  ti,tx-internal-delay = <0x0>;
  ti,fifo-depth = <0x03>;
  ti,min-output-impedance;
  ti,dp83867-rxctrl-strap-quirk;
 };

 phy1: ethernet-phy@1 {
  reg = <1>;
  ti,rx-internal-delay = <0x8>;
  ti,tx-internal-delay = <0x0>;
  ti,fifo-depth = <0x03>;
  ti,min-output-impedance;
  ti,dp83867-rxctrl-strap-quirk;
 };
};

&mac {
 status = "okay";
 dual_emac;
};

&cpsw_emac0 {

 phy_id = <&davinci_mdio>, <0>;
 phy-mode = "rgmii-id";
 dual_emac_res_vlan = <0>;
 mac-address = [ 65 00 6A 87 8D 15 ];
 status = "okay";
};

&cpsw_emac1 {

 phy_id = <&davinci_mdio>, <1>;
 phy-mode = "rgmii-id";
 dual_emac_res_vlan = <1>;
 mac-address = [ 65 00 6A 87 8D 17 ];
 status = "okay";
};

&mmc1 {
 status = "okay";

 pinctrl-names = "default";
 pinctrl-0 = <&mmc1_pins_default>;

 bus-width = <4>;
 cd-gpios = <&gpio6 27 1>;
};

&mmc2 {
 status = "okay";

 pinctrl-names = "default";
 pinctrl-0 = <&mmc2_pins_default>;

 vmmc-supply = <&vdd_3v3>;
 bus-width = <8>;
 ti,non-removable;
 cap-mmc-dual-data-rate;
};

&mmc3 {
 status = "okay";

 pinctrl-names = "default";
 pinctrl-0 = <&mmc3_pins_default>;

 vmmc-supply = <&vdd_3v3>;
 bus-width = <8>;
 ti,non-removable;
 cap-mmc-dual-data-rate;
};

&sata {
 status = "okay";
};

&usb2_phy1 {
 phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
 phy-supply = <&ldousb_reg>;
};

&usb1 {
 dr_mode = "host";
};

&omap_dwc3_2 {
 extcon = <&extcon_usb2>;
};

&usb2 {
# 556 "../arch/arm/dts/vau-p3-common.dtsi"
 dr_mode = "peripheral";
};

&cpu_trips {
 cpu_alert1: cpu_alert1 {
  temperature = <50000>;
  hysteresis = <2000>;
  type = "active";
 };
};

&cpu_cooling_maps {
 map1 {
  trip = <&cpu_alert1>;
  cooling-device = <&gpio_fan (~0) (~0)>;
 };
};

&thermal_zones {
 board_thermal: board_thermal {
  polling-delay-passive = <1250>;
  polling-delay = <1500>;


  thermal-sensors = <&tmp102 0>;

  board_trips: trips {
   board_alert0: board_alert {
    temperature = <40000>;
    hysteresis = <2000>;
    type = "active";
   };

   board_crit: board_crit {
    temperature = <105000>;
    hysteresis = <0>;
    type = "critical";
   };
  };

  board_cooling_maps: cooling-maps {
   map0 {
    trip = <&board_alert0>;
    cooling-device =
      <&gpio_fan (~0) (~0)>;
   };
  };
       };
};

&dss {
 status = "ok";

 vdda_video-supply = <&ldoln_reg>;
};

&hdmi {
 status = "ok";
 vdda-supply = <&ldo4_reg>;

 port {
  hdmi_out: endpoint {
   remote-endpoint = <&tpd12s015_in>;
  };
 };
};

&pcie1_rc {
 status = "ok";
 gpios = <&gpio2 8 1>;
};

&pcie1_ep {
 gpios = <&gpio2 8 1>;
};

&mcasp3 {
 #sound-dai-cells = <0>;
 assigned-clocks = <&mcasp3_ahclkx_mux>;
 assigned-clock-parents = <&sys_clkin2>;
 status = "okay";

 op-mode = <0>;
 tdm-slots = <2>;

 serial-dir = <
  1 2 0 0
 >;
 tx-num-evt = <32>;
 rx-num-evt = <32>;
};

&mailbox5 {
 status = "okay";
 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
  status = "okay";
 };
 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
  status = "okay";
 };
};

&mailbox6 {
 status = "okay";
 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
  status = "okay";
 };
 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
  status = "okay";
 };
};
# 10 "arch/arm/dts/.vau-p3.dtb.pre.tmp" 2

/ {
 model = "red-ant VAU P3";
};

&tpd12s015 {
 gpios = <&gpio7 10 0>,
  <&gpio2 30 0>,
  <&gpio7 12 0>;
};
# 53 "arch/arm/dts/.vau-p3.dtb.pre.tmp"
# 1 "../arch/arm/dts/omap5-u-boot.dtsi" 1
# 10 "../arch/arm/dts/omap5-u-boot.dtsi"
/{
 chosen {
  tick-timer = &timer2;
 };

 ocp {
  u-boot,dm-spl;

  ocp2scp@4a080000 {
   compatible = "ti,omap-ocp2scp", "simple-bus";
  };

  ocp2scp@4a090000 {
   compatible = "ti,omap-ocp2scp", "simple-bus";
  };

  bandgap@4a0021e0 {
   u-boot,dm-spl;
  };
 };
};

&uart1 {
 u-boot,dm-spl;
 reg-shift = <2>;
};

&uart3 {
 u-boot,dm-spl;
 reg-shift = <2>;
};

&mmc1 {
 u-boot,dm-spl;
};

&mmc2 {
 u-boot,dm-spl;
};

&l4_cfg {
 u-boot,dm-spl;
};

&scm {
 u-boot,dm-spl;
};

&scm_conf {
 u-boot,dm-spl;
};

&qspi {
 u-boot,dm-spl;

 m25p80@0 {
  compatible = "spi-flash";
  u-boot,dm-spl;
 };
};

&gpio1 {
 u-boot,dm-spl;
};

&gpio2 {
 u-boot,dm-spl;
};

&gpio3 {
 u-boot,dm-spl;
};

&gpio4 {
 u-boot,dm-spl;
};

&gpio5 {
 u-boot,dm-spl;
};

&gpio6 {
 u-boot,dm-spl;
};

&gpio7 {
 u-boot,dm-spl;
};
# 53 "arch/arm/dts/.vau-p3.dtb.pre.tmp" 2