//- 21.5 inch,  For 1920 x 1080
/*Dmesg from kernel*/
jht_8mq:/ # dmesg |grep DSI84-I2C
[    2.762404] DSI84-I2C: read 0x00  - 0x35
[    2.763336] DSI84-I2C: read 0x0d  - 0x00
[    2.764266] DSI84-I2C: read 0x0a  - 0x05
[    2.765203] DSI84-I2C: read 0x0b  - 0x10
[    2.766137] DSI84-I2C: read 0x10  - 0x26
[    2.767067] DSI84-I2C: read 0x18  - 0x6c
[    2.767998] DSI84-I2C: read 0x1a  - 0x03
[    2.768934] DSI84-I2C: read 0x20  - 0x80
[    2.769864] DSI84-I2C: read 0x21  - 0x07
[    2.770796] DSI84-I2C: read 0x22  - 0x00
[    2.771729] DSI84-I2C: read 0x23  - 0x00
[    2.772662] DSI84-I2C: read 0x24  - 0x00
[    2.773590] DSI84-I2C: read 0x25  - 0x00
[    2.774510] DSI84-I2C: read 0x26  - 0x00
[    2.775431] DSI84-I2C: read 0x27  - 0x00
[    2.776352] DSI84-I2C: read 0x28  - 0x1f
[    2.777039] DSI84-I2C: read 0x29  - 0x04
[    2.777961] DSI84-I2C: read 0x2a  - 0x00
[    2.778882] DSI84-I2C: read 0x2b  - 0x00
[    2.779805] DSI84-I2C: read 0x2c  - 0x0f
[    2.780728] DSI84-I2C: read 0x2d  - 0x00
[    2.781658] DSI84-I2C: read 0x2e  - 0x00
[    2.782588] DSI84-I2C: read 0x2f  - 0x00
[    2.783519] DSI84-I2C: read 0x30  - 0x06
[    2.784449] DSI84-I2C: read 0x31  - 0x00
[    2.785384] DSI84-I2C: read 0x32  - 0x00
[    2.786316] DSI84-I2C: read 0x33  - 0x00
[    2.787246] DSI84-I2C: read 0x34  - 0x2f
[    2.788179] DSI84-I2C: read 0x35  - 0x00
[    2.789105] DSI84-I2C: read 0x36  - 0x00
[    2.790025] DSI84-I2C: read 0x37  - 0x00
[    2.790947] DSI84-I2C: read 0x38  - 0x2f
[    2.791868] DSI84-I2C: read 0x39  - 0x00
[    2.792791] DSI84-I2C: read 0x3a  - 0x00
[    2.793655] DSI84-I2C: read 0x3b  - 0x00


//-21.5 inch, For 1920 x 1080
/*Set the registers on driver*/ 
/* Soft reset and disable PLL */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_SOFT_RESET, 0x01);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_PLL_EN, 0x00);

/* four DSI lanes with single channel*/
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_CFG, 0x26);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_EQ, 0x00);

/* set DSI clock range */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_DSI_CLK_RNG, 0x2D);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_DSI_CLK_RNG, 0x00);

/* set LVDS for single channel, 24 bit mode, HS/VS low, DE high */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_LVDS_MODE, 0x6C);

/* x resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_LO, 0x80);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_HI, 0x07);
		
/* x resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_HI, 0x00);

/* y resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_HI, 0x00);

/* y resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_HI, 0x00);

/* SYNC delay high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_LO, 0x1F);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_HI, 0x04);

/* SYNC delay high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_HI, 0x00);

/* HSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_LO, 0x0F);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_HI, 0x00);

/* HSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_LO, 0x06);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_HI, 0x00);

/* Horizontal BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_BACKPORCH, 0x2F);

/* Horizontal BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_BACKPORCH, 0x00);

/* Vertical BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_BACKPORCH, 0x00);

/* Vertical BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_BACKPORCH, 0x00);

/* Horizontal FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_FRONTPORCH, 0x00);

/* Horizontal FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_FRONTPORCH, 0x00);