File descriptions

./models:
nominal.lib            //device model 

./netlist:
DPHY440_HS_RX_EQ_enc.hsp   //HSPICE file for single lane HS Rx

     //Pin List:
     //  vcc_1p8    Supply. Nominal 1.8V
     //  gnd        Ground
     //  d          Digitalized EQ output 
     //  eqoutp     Positive EQ output
     //  da_p       Positive data input (DAxP pin of DPHY440)
     //  da_n       Negative data input (DAxN pin of DPHY440)
     //  eqoutn     Negative EQ output
     //  dz         Digitalized EQ output (reversed polarity)
     //  eq         Tri-level input for EQ level selection. 
     //             0:0dB; 0.5*vcc_1p8:2.5dB; vcc_1p8:4dB

DPHY440_HS_TX_enc.hsp  //HSPICE file for single lane HS TX

     //Pin List:
     //  erc_1      {erc_1,ecr_0} are 2-bits control for HS edge rate.
     //  erc_0      Logic High: 1.2V, Logic Low: 0V. 
     //  data_in    HS-TX data input (from digital core), input high is 1.2V, input low is 0V.
                    Max 1Gbps. 
     //  vsadj_1    {vsadj_1,vsadj_0} are 2-bits control for VOD.
     //  vsadj_0    Logic High: 1.2V, Logic Low: 0V.
                    00: 180mV  01:200mV (default)  1x: 220mV
     //  gnd        Ground
     //  vcc_1p8    Supply. Nominal 1.8v
     //  dout1p     Positive output. (DBxP pin of DPHY440)
     //  dout1n     Negative output. (DBxN pin of DPHY440)

./tb:
input_rx.hsp           //Reference simulation input file, trace/cable not included
input_tx.hsp           //Reference simulation input file, trace/cable not included

