Indirect Address Register	0xB1	Indirect Data Register	0xB2					
Page	Address	Register Name	Bit(s)	Field	Type	Default Value	Description	Public
	0x00	Reserved						yes
			7:0	RESERVED	R	0	Reserved	yes
	0x01	PGEN_CTL					Pattern Generator Control Register	yes
			7:1	RESERVED	RW	0	Reserved	yes
			0	PGEN_ENABLE	RW	0	Pattern Generator Enable 1: Enable Pattern Generator 0: Disable Pattern Generator	yes
	0x02	PGEN_CFG					Pattern Generator Configuration Register	yes
			7	PGEN_FIXED_EN	RW	0	Fixed Pattern Enable Setting this bit enables Fixed Color Patterns. 0 : Send Color Bar Pattern 1 : Send Fixed Color Pattern	yes
			6	RESERVED	RW	0	Reserved	yes
			5:4	NUM_CBARS	RW	0x3	Number of Color Bars 00 : 1 Color Bar 01 : 2 Color Bars 10 : 4 Color Bars 11 : 8 Color Bars	yes
			3:0	BLOCK_SIZE	RW	0x3	Block Size. For Fixed Color Patterns, this field controls the size of the fixed color field in bytes.  Allowed values are 1 to 12.	yes
	0x03	PGEN_CSI_DI					Pattern Generator CSI DI Register	yes
			7:6	PGEN_CSI_VC	RW	0	CSI Virtual Channel Identifier This field controls the value sent in the CSI packet for the Virtual Channel Identifier	yes
			5:0	PGEN_CSI_DT	RW	0x24	CSI Data Type This field controls the value sent in the CSI packet for the Data Type.  The default value (0x24) indicates RGB888.	yes
	0x04	PGEN_LINE_SIZE1					Pattern Generator Line Size Register 1	yes
			7:0	PGEN_LINE_SIZE[15:8]	RW	0x07	Most significant byte of the Pattern Generator line size.  This is the active line length in bytes.  Default setting is for 1920 bytes for a 640 pixel line width.	yes
	0x05	PGEN_LINE_SIZE0					Pattern Generator Line Size Register 0	yes
			7:0	PGEN_LINE_SIZE[7:0]	RW	0x80	Least significant byte of the Pattern Generator line size.  This is the active line length in bytes.  Default setting is for 1920 bytes for a 640 pixel line width.	yes
	0x06	PGEN_BAR_SIZE1					Pattern Generator Bar Size Register 1	yes
			7:0	PGEN_BAR_SIZE[15:8]	RW	0x00	Most significant byte of the Pattern Generator color bar size.  This is the active length in bytes for the color bars.  This value is used for all except the last color bar.  The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value.	yes
	0x07	PGEN_BAR_SIZE0					Pattern Generator Bar Size Register 0	yes
			7:0	PGEN_BAR_SIZE[7:0]	RW	0xF0	Least significant byte of the Pattern Generator color bar size.  This is the active length in bytes for the color bars.  This value is used for all except the last color bar.  The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value.	yes
	0x08	PGEN_ACT_LPF1					Pattern Generator Active LPF Register 1	yes
			7:0	PGEN_ACT_LPF[15:8]	RW	0x01	Active Lines Per Frame Most significant byte of the number of active lines per frame.  Default setting is for 480 active lines per frame.	yes
	0x09	PGEN_ACT_LPF0					Pattern Generator Active LPF Register 0	yes
			7:0	PGEN_ACT_LPF[7:0]	RW	0xE0	Active Lines Per Frame Least significant byte of the number of active lines per frame.  Default setting is for 480 active lines per frame.	yes
	0x0A	PGEN_TOT_LPF1					Pattern Generator Total LPF Register 1	yes
			7:0	PGEN_TOT_LPF[15:8]	RW	0x02	Total Lines Per Frame Most significant byte of the number of total lines per frame including vertical blanking	yes
	0x0B	PGEN_TOT_LPF0					Pattern Generator Total LPF Register 0	yes
			7:0	PGEN_TOT_LPF[7:0]	RW	0x0D	Total Lines Per Frame Least significant byte of the number of total lines per frame including vertical blanking	yes
	0x0C	PGEN_LINE_PD1					Pattern Generator Line Period Register 1	yes
			7:0	PGEN_LINE_PD[15:8]	RW	0x0C	Line Period Most significant byte of the line period in 10ns units.  The default setting for the line period registers sets a line period of 31.75 microseconds.	yes
	0x0D	PGEN_LINE_PD0					Pattern Generator Line Period Register 0	yes
			7:0	PGEN_LINE_PD[7:0]	RW	0x67	Line Period Least significant byte of the line period in 10ns units.  The default setting for the line period registers sets a line period of 31.75 microseconds.	yes
	0x0E	PGEN_VBP					Pattern Generator VBP Register	yes
			7:0	PGEN_VBP	RW	0x21	Vertical Back Porch This value provides the vertical back porch portion of the vertical blanking interval.  This value provides the number of blank lines between the FrameStart packet and the first video data packet.	yes
	0x0F	PGEN_VFP					Pattern Generator VFP Register	yes
			7:0	PGEN_VFP	RW	0x0A	Vertical Front Porch This value provides the vertical front porch portion of the vertical blanking interval.  This value provides the number of blank lines between the last video line and the FrameEnd packet.	yes
	0x10	PGEN_COLOR0					Pattern Generator Color 0 Register	yes
			7:0	PGEN_COLOR0	RW	0xAA	Pattern Generator Color 0 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 0. For Fixed Color Patterns, this register controls the first byte of the fixed color pattern.	yes
	0x11	PGEN_COLOR1					Pattern Generator Color 1 Register	yes
			7:0	PGEN_COLOR1	RW	0x33	Pattern Generator Color 1 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 1. For Fixed Color Patterns, this register controls the second byte of the fixed color pattern.	yes
	0x12	PGEN_COLOR2					Pattern Generator Color 2 Register	yes
			7:0	PGEN_COLOR2	RW	0xF0	Pattern Generator Color 2 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 2. For Fixed Color Patterns, this register controls the third byte of the fixed color pattern.	yes
	0x13	PGEN_COLOR3					Pattern Generator Color 3 Register	yes
			7:0	PGEN_COLOR3	RW	0x7F	Pattern Generator Color 3 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 3. For Fixed Color Patterns, this register controls the fourth byte of the fixed color pattern.	yes
	0x14	PGEN_COLOR4					Pattern Generator Color 4 Register	yes
			7:0	PGEN_COLOR4	RW	0x55	Pattern Generator Color 4 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 4. For Fixed Color Patterns, this register controls the fifth byte of the fixed color pattern.	yes
	0x15	PGEN_COLOR5					Pattern Generator Color 5 Register	yes
			7:0	PGEN_COLOR5	RW	0xCC	Pattern Generator Color 5 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 5. For Fixed Color Patterns, this register controls the sixth byte of the fixed color pattern.	yes
	0x16	PGEN_COLOR6					Pattern Generator Color 6 Register	yes
			7:0	PGEN_COLOR6	RW	0x0F	Pattern Generator Color 6 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 6. For Fixed Color Patterns, this register controls the seventh byte of the fixed color pattern.	yes
	0x17	PGEN_COLOR7					Pattern Generator Color 7 Register	yes
			7:0	PGEN_COLOR7	RW	0x80	Pattern Generator Color 7 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 7. For Fixed Color Patterns, this register controls the eighth byte of the fixed color pattern.	yes
	0x18	PGEN_COLOR8					Pattern Generator Color 8 Register	yes
			7:0	PGEN_COLOR8	RW	0x00	Pattern Generator Color 8 For Fixed Color Patterns, this register controls the ninth byte of the fixed color pattern.	yes
	0x19	PGEN_COLOR9					Pattern Generator Color 9 Register	yes
			7:0	PGEN_COLOR9	RW	0x00	Pattern Generator Color 9 For Fixed Color Patterns, this register controls the tenth byte of the fixed color pattern.	yes
	0x1A	PGEN_COLOR10					Pattern Generator Color 10 Register	yes
			7:0	PGEN_COLOR10	RW	0x00	Pattern Generator Color 10 For Fixed Color Patterns, this register controls the eleventh byte of the fixed color pattern.	yes
	0x1B	PGEN_COLOR11					Pattern Generator Color 11 Register	yes
			7:0	PGEN_COLOR11	RW	0x00	Pattern Generator Color 11 For Fixed Color Patterns, this register controls the twelfth byte of the fixed color pattern.	yes
	0x1C	PGEN_COLOR12					Pattern Generator Color 12 Register	yes
			7:0	PGEN_COLOR12	RW	0x00	Pattern Generator Color 12 For Fixed Color Patterns, this register controls the thirteenth byte of the fixed color pattern.	yes
	0x1D	PGEN_COLOR13					Pattern Generator Color 13 Register	yes
			7:0	PGEN_COLOR13	RW	0x00	Pattern Generator Color 13 For Fixed Color Patterns, this register controls the fourteenth byte of the fixed color pattern.	yes
	0x1E	PGEN_COLOR14					Pattern Generator Color 14 Register	yes
			7:0	PGEN_COLOR14	RW	0x00	Pattern Generator Color 14 For Fixed Color Patterns, this register controls the fifteenth byte of the fixed color pattern.	yes
	0x1F	PGEN_COLOR15					Pattern Generator Color 15 Register	yes
			7:0	PGEN_COLOR15	RW	0x00	Pattern Generator Color 15 For Fixed Color Patterns, this register controls the sixteenth byte of the fixed color pattern.	yes
	0x40	CSI0_TCK_PREP						
			7	MR_TCK_PREP_OV	RW	0	Override CSI Tck-prep parameter 0: Tck-prep is automatically determined 1: Override Tck-prep with value in bits 6:0 of this register	yes
			6:0	MR_TCK_PREP	RW	0x0	Tck-prep value	yes
	0x41	CSI0_TCK_ZERO						yes
			7	MR_TCK_ZERO_OV	RW	0	Override CSI Tck-zero parameter 0: Tck-zero is automatically determined 1: Override Tck-zero with value in bits 6:0 of this register	yes
			6:0	MR_TCK_ZERO	RW	0x0	Tck-zero value	yes
	0x42	CSI0_TCK_TRAIL						yes
			7	MR_TCK_TRAIL_OV	RW	0	Override CSI Tck-trail parameter 0: Tck-trail is automatically determined 1: Override Tck-trail with value in bits 6:0 of this register	yes
			6:0	MR_TCK_TRAIL	RW	0x0	Tck-trail value	yes
	0x43	CSI0_TCK_POST						yes
			7	MR_TCK_POST_OV	RW	0	Override CSI Tck-post parameter 0: Tck-post is automatically determined 1: Override Tck-post with value in bits 6:0 of this register	yes
			6:0	MR_TCK_POST	RW	0x0	Tck-post value	yes
	0x44	CSI0_THS_PREP						yes
			7	MR_THS_PREP_OV	RW	0	Override CSI Ths-prep parameter 0: Ths-prep is automatically determined 1: Override Ths-prep with value in bits 6:0 of this register	yes
			6:0	MR_THS_PREP	RW	0x0	Ths-prep value	yes
	0x45	CSI0_THS_ZERO						yes
			7	MR_THS_ZERO_OV	RW	0	Override CSI Ths-zero parameter 0: Ths-zero is automatically determined 1: Override Ths-zero with value in bits 6:0 of this register	yes
			6:0	MR_THS_ZERO	RW	0x0	Ths-zero value	yes
	0x46	CSI0_THS_TRAIL						yes
			7	MR_THS_TRAIL_OV	RW	0	Override CSI Ths-trail parameter 0: Ths-trail is automatically determined 1: Override Ths-trail with value in bits 6:0 of this register	yes
			6:0	MR_THS_TRAIL	RW	0x0	Ths-trail value	yes
	0x47	CSI0_THS_EXIT						yes
			7	MR_THS_EXIT_OV	RW	0	Override CSI Ths-exit parameter 0: Ths-exit is automatically determined 1: Override Ths-exit with value in bits 6:0 of this register	yes
			6:0	MR_THS_EXIT	RW	0x0	Ths-exit value	yes
	0x48	CSI0_TPLX						yes
			7	MR_TPLX_OV	RW	0	Override CSI Tplx parameter 0: Tplx is automatically determined 1: Override Tplx with value in bits 6:0 of this register	yes
			6:0	MR_TPLX	RW	0x0	Tplx value	yes
	0x49	CSI0_TRIM_TCK_PREP						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_PREP_50M	RW	0x0	Tck-prep timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_PREP_100M	RW	0x0	Tck-prep timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_PREP_200M	RW	0x0	Tck-prep timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x4A	CSI0_TRIM_TCK_ZERO						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_ZERO_50M	RW	0x0	Tck-zero timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_ZERO_100M	RW	0x0	Tck-zero timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_ZERO_200M	RW	0x0	Tck-zero timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x4B	CSI0_TRIM_TCK_TRAIL						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_TRAIL_50M	RW	0x0	Tck-trail timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_TRAIL_100M	RW	0x0	Tck-trail timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_TRAIL_200M	RW	0x0	Tck-trail timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x4C	CSI0_TRIM_TCK_POST						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_POST_50M	RW	0x0	Tck-post timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_POST_100M	RW	0x0	Tck-post timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_POST_200M	RW	0x0	Tck-post timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x4D	CSI0_TRIM_THS_PREP						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_PREP_50M	RW	0x0	ths-prep timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_PREP_100M	RW	0x0	ths-prep timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_PREP_200M	RW	0x0	ths-prep timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x4E	CSI0_TRIM_THS_ZERO						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_ZERO_50M	RW	0x0	ths-zero timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_ZERO_100M	RW	0x0	ths-zero timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_ZERO_200M	RW	0x0	ths-zero timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x4F	CSI0_TRIM_THS_TRAIL						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_TRAIL_50M	RW	0x0	ths-trail timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_TRAIL_100M	RW	0x0	ths-trail timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_TRAIL_200M	RW	0x0	ths-trail timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x50	CSI0_TRIM_THS_EXIT						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_EXIT_50M	RW	0x0	ths-exit timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_EXIT_100M	RW	0x0	ths-exit timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_EXIT_200M	RW	0x0	ths-exit timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x51	CSI0_TRIM_TPLX						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TPLX_50M	RW	0x0	tplx timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TPLX_100M	RW	0x0	tplx timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TPLX_200M	RW	0x0	tplx timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
								yes
	0x60	CSI1_TCK_PREP						
			7	MR_TCK_PREP_OV	RW	0	Override CSI Tck-prep parameter 0: Tck-prep is automatically determined 1: Override Tck-prep with value in bits 6:0 of this register	yes
			6:0	MR_TCK_PREP	RW	0x0	Tck-prep value	yes
	0x61	CSI1_TCK_ZERO						yes
			7	MR_TCK_ZERO_OV	RW	0	Override CSI Tck-zero parameter 0: Tck-zero is automatically determined 1: Override Tck-zero with value in bits 6:0 of this register	yes
			6:0	MR_TCK_ZERO	RW	0x0	Tck-zero value	yes
	0x62	CSI1_TCK_TRAIL						yes
			7	MR_TCK_TRAIL_OV	RW	0	Override CSI Tck-trail parameter 0: Tck-trail is automatically determined 1: Override Tck-trail with value in bits 6:0 of this register	yes
			6:0	MR_TCK_TRAIL	RW	0x0	Tck-trail value	yes
	0x63	CSI1_TCK_POST						yes
			7	MR_TCK_POST_OV	RW	0	Override CSI Tck-post parameter 0: Tck-post is automatically determined 1: Override Tck-post with value in bits 6:0 of this register	yes
			6:0	MR_TCK_POST	RW	0x0	Tck-post value	yes
	0x64	CSI1_THS_PREP						yes
			7	MR_THS_PREP_OV	RW	0	Override CSI Ths-prep parameter 0: Ths-prep is automatically determined 1: Override Ths-prep with value in bits 6:0 of this register	yes
			6:0	MR_THS_PREP	RW	0x0	Ths-prep value	yes
	0x65	CSI1_THS_ZERO						yes
			7	MR_THS_ZERO_OV	RW	0	Override CSI Ths-zero parameter 0: Ths-zero is automatically determined 1: Override Ths-zero with value in bits 6:0 of this register	yes
			6:0	MR_THS_ZERO	RW	0x0	Ths-zero value	yes
	0x66	CSI1_THS_TRAIL						yes
			7	MR_THS_TRAIL_OV	RW	0	Override CSI Ths-trail parameter 0: Ths-trail is automatically determined 1: Override Ths-trail with value in bits 6:0 of this register	yes
			6:0	MR_THS_TRAIL	RW	0x0	Ths-trail value	yes
	0x67	CSI1_THS_EXIT						yes
			7	MR_THS_EXIT_OV	RW	0	Override CSI Ths-exit parameter 0: Ths-exit is automatically determined 1: Override Ths-exit with value in bits 6:0 of this register	yes
			6:0	MR_THS_EXIT	RW	0x0	Ths-exit value	yes
	0x68	CSI1_TPLX						yes
			7	MR_TPLX_OV	RW	0	Override CSI Tplx parameter 0: Tplx is automatically determined 1: Override Tplx with value in bits 6:0 of this register	yes
			6:0	MR_TPLX	RW	0x0	Tplx value	yes
	0x69	CSI1_TRIM_TCK_PREP						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_PREP_50M	RW	0x0	Tck-prep timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_PREP_100M	RW	0x0	Tck-prep timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_PREP_200M	RW	0x0	Tck-prep timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x6A	CSI1_TRIM_TCK_ZERO						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_ZERO_50M	RW	0x0	Tck-zero timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_ZERO_100M	RW	0x0	Tck-zero timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_ZERO_200M	RW	0x0	Tck-zero timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x6B	CSI1_TRIM_TCK_TRAIL						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_TRAIL_50M	RW	0x0	Tck-trail timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_TRAIL_100M	RW	0x0	Tck-trail timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_TRAIL_200M	RW	0x0	Tck-trail timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x6C	CSI1_TRIM_TCK_POST						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TCK_POST_50M	RW	0x0	Tck-post timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TCK_POST_100M	RW	0x0	Tck-post timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TCK_POST_200M	RW	0x0	Tck-post timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x6D	CSI1_TRIM_THS_PREP						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_PREP_50M	RW	0x0	ths-prep timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_PREP_100M	RW	0x0	ths-prep timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_PREP_200M	RW	0x0	ths-prep timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x6E	CSI1_TRIM_THS_ZERO						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_ZERO_50M	RW	0x0	ths-zero timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_ZERO_100M	RW	0x0	ths-zero timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_ZERO_200M	RW	0x0	ths-zero timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x6F	CSI1_TRIM_THS_TRAIL						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_TRAIL_50M	RW	0x0	ths-trail timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_TRAIL_100M	RW	0x0	ths-trail timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_TRAIL_200M	RW	0x0	ths-trail timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x70	CSI1_TRIM_THS_EXIT						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_THS_EXIT_50M	RW	0x0	ths-exit timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_THS_EXIT_100M	RW	0x0	ths-exit timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_THS_EXIT_200M	RW	0x0	ths-exit timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
	0x71	CSI1_TRIM_TPLX						yes
			7:6	RESERVED	R	0x0	Reserved	yes
			5:4	TRIM_TPLX_50M	RW	0x0	tplx timing trim for 50 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			3:2	TRIM_TPLX_100M	RW	0x0	tplx timing trim for 100 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
			1:0	TRIM_TPLX_200M	RW	0x0	tplx timing trim for 200 MHz mode 00: +0 01: +1 10: +2 11: -1	yes
								
