Indirect Address Register	0xB1	Indirect Data Register	0xB2					
Page	Address	Register Name	Bit(s)	Field	Type	Default Value	Description	Public
	0x00	csi_reg_0						Yes
			7:6		RW	1	reserved	Yes
			5:3	atp enable csi port0 driver d0	RW	0	"000: ATP1: disable, ATP0: disable 001: vreg0p4, VDD 010: VDD, vreg1_0p3 011: VSS, vreg0p4 100: VSS, vreg1p2 101: VSS, ib_100u_dmos11 110: vreg1p2, vref2 111: VDD18, ib_100u_depmos18"	Yes
			2:0	atp enable csi port0 driver clock	RW	0	"000: ATP1: disable, ATP0: disable 001: vreg0p4, VDD 010: VDD, vreg1_0p3 011: VSS, vreg0p4 100: VSS, vreg1p2 101: VSS, ib_100u_dmos11 110: vreg1p2, vref2 111: VDD18, ib_100u_depmos18"	Yes
	0x01	csi_reg_1						Yes
			7:6	reserved	RW	0		Yes
			5:3	atp enable csi port0 driver d2	RW	0	"000: ATP1: disable, ATP0: disable 001: vreg0p4, VDD 010: VDD, vreg1_0p3 011: VSS, vreg0p4 100: VSS, vreg1p2 101: VSS, ib_100u_dmos11 110: vreg1p2, vref2 111: VDD18, ib_100u_depmos18"	Yes
			2:0	atp enable csi port0 driver d1	RW	0	"000: ATP1: disable, ATP0: disable 001: vreg0p4, VDD 010: VDD, vreg1_0p3 011: VSS, vreg0p4 100: VSS, vreg1p2 101: VSS, ib_100u_dmos11 110: vreg1p2, vref2 111: VDD18, ib_100u_depmos18"	Yes
	0x02	csi_reg_2						Yes
			7:3	reserved	RW	0		Yes
			2:0	atp enable csi port0 driver d3	RW	0	"000: ATP1: disable, ATP0: disable 001: vreg0p4, VDD 010: VDD, vreg1_0p3 011: VSS, vreg0p4 100: VSS, vreg1p2 101: VSS, ib_100u_dmos11 110: vreg1p2, vref2 111: VDD18, ib_100u_depmos18"	Yes
	0x03	csi_reg_3						Yes
			7:3		RW	0x08	reserved	Yes
			2:0	atp enable csi port1 driver clk	RW	0	"000: ATP1: disable, ATP0: disable 001: vreg0p4, VDD 010: VDD, vreg1_0p3 011: VSS, vreg0p4 100: VSS, vreg1p2 101: VSS, ib_100u_dmos11 110: vreg1p2, vref2 111: VDD18, ib_100u_depmos18"	Yes
	0x04	csi_reg_4						Yes
			7:0	Reserved	RW	0		Yes
	0x05	csi_reg_5						Yes
			7	dig_clk_sel_100M	R	0	1: analog output digital clock is 100MHz  0: analog output digital clock is 200MHz Read-only version of this register control.  Value is controlled in main digital registers via CSI_PLL_CTL:REF_CLK_MODE (register 0x1F[2])	Yes
			6	ATP_AC_EN_CSI_PLL	RW	0	1: enable PFD ATP output	Yes
			5	ATP_EN_CSI_PLL	RW	0	1: enable VSS	Yes
			4	ATP_EN_CSI_PLL	RW	0	1: enable op_out	Yes
			3	ATP_EN_CSI_PLL	RW	0	1: enable VCTRL	Yes
			2	ATP_EN_CSI_PLL	RW	0	1: enable VBP_atp	Yes
			1	ATP_EN_CSI_PLL	RW	0	1: enable NBIAS	Yes
			0	ATP_EN_CSI_PLL	RW	0	1: enable VBN_VCO	Yes
	0x06	csi_reg_6						Yes
			7:5	Reserved	RW	0		Yes
			4:2	Reserved	RW	0		Yes
			1:0	csi port0 hs driver bleeding resistor control	RW	0	00: 1000 ohm (default) 01: 500 ohm 10: 250 ohm 11: 200ohm	Yes
	0x07	csi_reg_7						Yes
			7:6	CSI PLL Vinit select	RW	2'b11	00: 0.64V 01: 0.78V 10: 0.86V 11: 1.38V (default)	Yes
			5	csi line rate select	R	1	"1: 800Mbps, csi_hsdrv tr/tf   @  nom 0: 1.6Gbps, csi_hsdrv Tr/Tf   @  fast  This is a read-only version of this register control.  The value for this bit is controlled in main digital registers via the CSI_PLL_CTL:CSI_TX_SPEED[1] (register 0x1F[1])."	Yes
			4:0	CSI2 PLL CP current select	RW	5'b00100	5'b01000: 1 5'b00100: 0.5 (default) 5'b00010: 0.25    5'b00001: 0.125  5'b10000: 0.0625	Yes
	0x08	csi_reg_8						Yes
			7:6	csi pll sel_div	RW	0	Divider setting for CSI PLL.  Used to scale CSI TX lane frequency from either 1.6 Gpbs or 800 Mbps depending on the csi line rate select in csi_reg_7[5] 00:  div64 - provides max CSI TX of 1.6 Gbps 01:  div60 - provides max CSI TX of 1.5 Gbps 10:  div56 - provides max CSI TX of 1.4 Gbps 11:  div52 - provides max CSI TX of 1.3 Gbps	Yes
			5	enable IO 3.3V register select	RW	0	"0: auto VDDIO detect 1: bypass auto VDDIO detect, register control VDDIO level select"	Yes
			4	IO 3.3V sel	RW	0	0: VDDIO 1.8V 1: VDDIO 3.3V	Yes
			3:0	CSI PLL Y select	RW	0	4'b0000:  4 (default) 4'b0001:  2 4'b0010: 1.33 4'b0100: 0.8	Yes
	0x09	csi_reg_9						Yes
			7:4	reserved	RW	0	reserved	Yes
			3:0	CSI BIAS ATP select	RW	0	4'b0001: atp_50u_1p8 4'b0010: atp_vref 4'b0100: atp_ibrx_50ua 4'b1000: atp_ibtx_50ua	Yes
	0x0A	csi_reg_a						Yes
			7	reserved	RW	0		Yes
			6	CSI_BIAS SEL_VRES	RW	0		Yes
			5	CSI_BIAS SEL_IREF	RW	0		Yes
			4:0	CSI_BIAS IBRX_TRIM	RW	0		Yes
	0x0B	csi_reg_b						Yes
			7:2	reserved	RW	0		Yes
			1:0	CSI_BIAS RTRIM	RW	1		Yes
	0x0C	csi_reg_c						Yes
			7:5	reserved	RW	0		Yes
			4	IDX block test enable	RW	0		Yes
			3	resetb IDX block	RW	1	0: reset cad block	Yes
			2:0	IDX address 	RW	0		Yes
	0x0D	csi_reg_d						Yes
			7:5	reserved	RW	0		Yes
			4	mode select block test enable	RW	0		Yes
			3	resetb mode select block	RW	1	0: reset mode select block	Yes
			2:0	mode select over write	RW	0		Yes
	0x0E	csi_reg_e						Yes
			7:1	RESERVED	RW	0	Reserved.	Yes
			0	enable CSI_PLL VCO clock div2	RW	0	"0 disable, 1 enable, select csi1_clk output to CSI_PLL VCO div2"	Yes
	0x0F	csi_reg_f						Yes
			7:0	RESERVED	RW	0	Reserved.	Yes
	0x10	csi_trim_0						Yes
			7:5	AON trim	RW	0		Yes
			4:0	CSI HS driver bottom R trim	RW	0x14		Yes
	0x11	csi_trim_1						Yes
			7:5	AON trim	RW	0		Yes
			4:0	CSI HS data driver Vreg trim	RW	0x0F		Yes
	0x12	csi_trim_2						Yes
			7:5	reserved	RW	0		Yes
			4:0	CSI HS driver top R trim	RW	0x14		Yes
	0x13	csi_trim_3						Yes
			7:5	reserved	RW	0		Yes
			4:0	CSI LP driver Vreg trim	RW	0x0F		Yes
	0x14	csi_trim_4						Yes
			7:5	reserved	RW	0		Yes
			4:0	CSI HS clock driver Vreg trim	RW	0x0F	Reserved.	Yes
	0x15	csi_pd_rst_ctl						Yes
			7	PD_CSI_PLL_OV	RW	0	1: override for Analog CSI PLL Powerdown.  Setting this bit will automatically select the Always-On clock for the digital reference clock rather than the CSi PLL output.	Yes
			6	PD_CSI_PLL	RW	0	Analog CSI PLL Powerdown override value	Yes
			5	PD_CSI_PLL_CHG_OV	RW	0	1: override for Analog CSI PLL Charge Powerdown	Yes
			4	PD_CSI_PLL_CHG	RW	0	Analog CSI PLL Charge Powerdown override value	Yes
			3	CSI0_REG_RSTB_OV	RW	0	1: override for CSI0 Register reset	Yes
			2	CSI0_REG_RSTB	RW	0	CSI0 Register reset override value	Yes
			1	CSI1_REG_RSTB_OV	RW	0	1: override for CSI1 Register reset	Yes
			0	CSI1_REG_RSTB	RW	0	CSI1 Register reset override value	Yes
	0x16	csi_trim_5						Yes
			7:4	CSI_PORT0_D1 delay selecct	RW	0	"bit3=1, min delay = 3 buffers bit3=0, delay time increased;         bit<2:0> : 000-minimum dly = 3 buffers                      001- 4 buffers                      010: 5 buffers delay                      011: 6 buffers delay                      100: 7 buffers delay                      101: 8 buffers delay (max delay)                      110: invalid                      111: invalid"	Yes
			3:0	CSI_PORT0_D0 delay selecct	RW	0	"bit3=1, min delay = 3 buffers bit3=0, delay time increased;         bit<2:0> : 000-minimum dly = 3 buffers                      001- 4 buffers                      010: 5 buffers delay                      011: 6 buffers delay                      100: 7 buffers delay                      101: 8 buffers delay (max delay)                      110: invalid                      111: invalid"	Yes
	0x17	csi_trim_6						Yes
			7:4	CSI_PORT0_D3 delay selecct	RW	0	"bit3=1, min delay = 3 buffers bit3=0, delay time increased;         bit<2:0> : 000-minimum dly = 3 buffers                      001- 4 buffers                      010: 5 buffers delay                      011: 6 buffers delay                      100: 7 buffers delay                      101: 8 buffers delay (max delay)                      110: invalid                      111: invalid"	Yes
			3:0	CSI_PORT0_D2 delay selecct	RW	0	"bit3=1, min delay = 3 buffers bit3=0, delay time increased;         bit<2:0> : 000-minimum dly = 3 buffers                      001- 4 buffers                      010: 5 buffers delay                      011: 6 buffers delay                      100: 7 buffers delay                      101: 8 buffers delay (max delay)                      110: invalid                      111: invalid"	Yes
	0x18	csi_trim_7						Yes
			7:6	reserved	RW	0		Yes
			5:0	AON trim	RW	0		Yes
	0x19	csi_trim_8						Yes
			7:5	csi LDO_ATP	RW	0		Yes
			4:0	csi LDO_V_Cntrl	RW	0		Yes
	0x1A	csi_trim_9						Yes
			7:4	CSI_PORT1_CLK delay selecct	RW	0	"bit3=1, min delay = 3 buffers bit3=0, delay time increased;         bit<2:0> : 000-minimum dly = 3 buffers                      001- 4 buffers                      010: 5 buffers delay                      011: 6 buffers delay                      100: 7 buffers delay                      101: 8 buffers delay (max delay)                      110: invalid                      111: invalid"	Yes
			3:0	CSI_PORT0_CLK delay selecct	RW	0	"bit3=1, min delay = 3 buffers bit3=0, delay time increased;         bit<2:0> : 000-minimum dly = 3 buffers                      001- 4 buffers                      010: 5 buffers delay                      011: 6 buffers delay                      100: 7 buffers delay                      101: 8 buffers delay (max delay)                      110: invalid                      111: invalid"	Yes
	0x1B	csi_trim_a						Yes
			7:4	reserved	RW	0		Yes
			3	register over write Tr/Tf 	RW	0	"0:  fix  Tr/Tf setting by csi_reg_3<5>, 1- register select Tr/Tf"	Yes
			2:0	CSI_PORT0 rise/fall contrl	RW	0	"xx0b- 1 mux, x11b- 1 buf+2 MUX, 001b-- 2 buf+ 3mux,  101b:3 buf+3 mux"	Yes
	0x1C	csi_trim_b						Yes
			7:0	Reserved.	RW	0	Reserved.	Yes
	0x1D	csi_trim_c						Yes
			7:0	Reserved.	RW	0	Reserved.	Yes
								
								
								
								
								
								
