======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== 0D 00 ======ADDR 0A======= 0A 02 ======ADDR 0B======= 0B 00 ======ADDR 10======= 10 20 ======ADDR 12======= 12 1E ======ADDR 18======= 18 72 ======ADDR 20======= ======CHA_LINE_LENGTH_LOW======== 20 00 ======ADDR 21======= ======CHA_LINE_LENGTH_HIGH======== 21 04 ======ADDR 22======= ======CHB_LINE_LENGTH_LOW======== 22 00 ======ADDR 23======= ======CHB_LINE_LENGTH_HIGH======== 23 00 ======ADDR 24======= ======CHA_VERTICAL_DISPLAY_SIZE_LOW======== 24 58 ======ADDR 25======= ======CHA_VERTICAL_DISPLAY_SIZE_HIGH======== 25 02 ======ADDR 26======= ======CHB_VERTICAL_DISPLAY_SIZE_LOW======== 26 00 ======ADDR 27======= ======CHB_VERTICAL_DISPLAY_SIZE_HIGH======== 27 00 ======ADDR 28======= ======CHA_SYNC_DELAY_LOW======== 28 00 ======ADDR 29======= ======CHA_SYNC_DELAY_HIGH======== 29 02 ======ADDR 2A======= ======CHB_SYNC_DELAY_LOW======== 2A 00 ======ADDR 2B======= ======CHB_SYNC_DELAY_HIGH======== 2B 00 ======ADDR 2C======= ======CHA_HSYNC_PULSE_WIDTH_LOW======== 2C 88 ======ADDR 2D======= ======CHA_HSYNC_PULSE_WIDTH_HIGH======== 2D 00 ======ADDR 2E======= ======CHB_HSYNC_PULSE_WIDTH_LOW======== 2E 00 ======ADDR 2F======= ======CHB_HSYNC_PULSE_WIDTH_HIGH======== 2F 00 ======ADDR 30======= ======CHA_VSYNC_PULSE_WIDTH_LOW======== 30 03 ======ADDR 31======= ======CHA_VSYNC_PULSE_WIDTH_HIGH======== 31 00 ======ADDR 32======= ======CHB_VSYNC_PULSE_WIDTH_LOW======== 32 00 ======ADDR 33======= ======CHB_VSYNC_PULSE_WIDTH_HIGH======== 33 00 ======ADDR 34======= ======CHA_HOR_BACK_PORCH======== 34 A0 ======ADDR 35======= ======CHB_HOR_BACK_PORCH======== 35 00 ======ADDR 36======= ======CHA_VER_BACK_PORCH======== 36 16 ======ADDR 37======= ======CHB_VER_BACK_PORCH======== 37 00 ======ADDR 38======= ======CHA_HOR_FRONT_PORCH======== 38 18 ======ADDR 39======= ======CHB_HOR_FRONT_PORCH======== 39 00 ======ADDR 3A======= ======CHA_VER_FRONT_PORCH======== 3A 00 ======ADDR 3B======= ======CHB_VER_FRONT_PORCH======== 3B 00 ======ADDR 3C======= ======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)======== 3C 10 ======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== 0D 01 =====SOFTRESET======= 09 01 ======Read====== 00 ======Read====== 00