// Copyright (c) 2004-2020 Microchip Technology Inc. and its subsidiaries. // SPDX-License-IdenTIfier: MIT #ifndef _MEPA_TI_REGISTERS_H #define _MEPA_TI_REGISTERS_H // Macros #define TI_DEF_MASK 0xffff #define TI_BIT(x) (1 << x) #define TI_BIT_T(x) ((x >> 5) & 0x03) #define TI_BIT_MASK(x) ((1U << (x)) - 1) #define TI_EXTRACT_BITFIELD(value, offset, width) (((value) >> (offset)) & TI_BIT_MASK(width)) #define TI_ENCODE_BITFIELD(value, offset, width) (((value) & TI_BIT_MASK(width)) << (offset)) #define TI_ENCODE_BITMASK(offset, width) (TI_BIT_MASK(width) << (offset)) /*#define TI_EXT_PAGE_0 0 #define TI_EXT_PAGE_1 1 #define TI_EXT_PAGE_2 2 #define TI_EXT_PAGE_3 3 #define TI_EXT_PAGE_4 4 #define TI_EXT_PAGE_5 5 #define TI_EXT_PAGE_28 28 #define TI_EXT_PAGE_29 29 #define TI_EXT_PAGE_31 31*/ #define TI_MMD_7 7 // Direct registers // Register - 0 BMCR #define TI_BMCR 0 #define TI_F_BMCR_SPEED_SEL_BIT_1 TI_BIT(6) #define TI_F_BMCR_DUP_MODE TI_BIT(8) #define TI_F_BMCR_RESTART_ANEG TI_BIT(9) #define TI_F_BMCR_ISO_MODE_EN TI_BIT(10) #define TI_F_BMCR_SOFT_POW_DOWN TI_BIT(11) #define TI_F_BMCR_ANEG_ENA TI_BIT(12) #define TI_F_BMCR_SPEED_SEL_BIT_0 TI_BIT(13) #define TI_F_BMCR_LOOPBACK TI_BIT(14) #define TI_F_BMCR_SOFT_RESET TI_BIT(15) #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define TI_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ BMCR_FULLDPLX | \ BMCR_SPEED1000) // Register - 1 BMSR #define TI_BMSR 1 #define TI_F_BMSR_LINK_STATUS TI_BIT(2) #define TI_F_BMSR_ANEG_COMPLETE TI_BIT(5) #define TI_F_BMSR_EXT_STATUS TI_BIT(8) #define TI_F_BMSR_100_T2_HALF_DUP TI_BIT(13) #define TI_F_BMSR_100_T2_FULL_DUP TI_BIT(14) #define TI_F_BMSR_10_T_HALF_DUP TI_BIT(11) #define TI_F_BMSR_10_T_FULL_DUP TI_BIT(12) // Register - 3 PHYIDR2 Register #define TI_DEVICE_ID_2 3 #define TI_X_DEV_ID_PHY_ID(x) TI_EXTRACT_BITFIELD(x, 10, 6) #define TI_X_DEV_ID_MODEL(x) TI_EXTRACT_BITFIELD(x, 4, 6) #define TI_X_DEV_ID_REV(x) TI_EXTRACT_BITFIELD(x, 0, 4) // Register - 4 ANAR Register #define TI_ANEG_ADVERTISEMENT 4 // Register - 5 ALNPAR Register #define TI_ALNPAR_LP_BASE 5 #define TI_F_ALNPAR_LP_BASE_10_T_HALF_DUP TI_BIT(5) #define TI_F_ALNPAR_LP_BASE_10_T_FULL_DUP TI_BIT(6) #define TI_F_ALNPAR_LP_BASE_100_X_HALF_DUP TI_BIT(7) #define TI_F_ALNPAR_LP_BASE_100_X_FULL_DUP TI_BIT(8) #define TI_F_ALNPAR_LP_BASE_SYM_PAUSE TI_BIT(10) #define TI_F_ALNPAR_LP_BASE_ASYM_PAUSE TI_BIT(11) // Register - 9 GEN_CFG1 Register #define TI_GEN_CFG1 9 #define TI_F_GEN_CFG1_G_1000BT_FD_ADV TI_BIT(9) #define TI_F_GEN_CFG1_G_1000BT_HD_ADV TI_BIT(8) #define TI_F_GEN_CFG1_G_PORT_TYPE TI_BIT(10) #define TI_F_GEN_CFG1_CFG_MAN_CFG_VAL TI_BIT(11) #define TI_F_GEN_CFG1_CFG_MAN_CFG_ENA TI_BIT(12) #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ #define CTL1000_AS_MASTER 0x0800 #define TI_CFG1_DEFAULT (ADVERTISE_1000HALF | \ ADVERTISE_1000FULL | \ CTL1000_AS_MASTER) // Register - 10 GEN_STATUS1 Register #define TI_GEN_STATUS1 10 #define TI_F_GEN_STATUS1_CFG_FAULT TI_BIT(15) #define TI_F_GEN_STATUS1_CFG_RES TI_BIT(14) #define TI_F_GEN_STATUS1_1000_T_FULL_DUP TI_BIT(11) #define TI_F_GEN_STATUS1_1000_T_HALF_DUP TI_BIT(10) // Register - 13 REGCR Register #define TI_MMD_ACCESS_CTRL 13 #define TI_F_MMD_ACCESS_CTRL_MMD_FUNC 0x4000 // Register - 14 ADDAR Register #define TI_MMD_ACCESS_ADDR_DATA 14 // Register - 15 1KSCR Register #define TI_EXTENDED_STATUS 15 #define TI_F_EXT_STATUS_1000_T_HALF_DUP TI_BIT(12) #define TI_F_EXT_STATUS_1000_T_FULL_DUP TI_BIT(13) #define TI_F_EXT_STATUS_1000_X_HALF_DUP TI_BIT(14) #define TI_F_EXT_STATUS_1000_X_FULL_DUP TI_BIT(15) // Register - 16 PHY_CONTROL #define TI_PHY_CONTROL 16 #define DP83869_PHY_CTRL_DEFAULT 0x0048 #define TI_F_RX_FIFO_DEPTH 0x1000 #define TI_F_TX_FIFO_DEPTH 0x4000 // Register - 17 /*#define TI_PCS_LOOP_POLARITY_CTRL 17 #define TI_F_PCS_LOOP_CTRL_PORT_LOOP TI_BIT(8)*/ // Register - 18 /*#define TI_CABLE_DIAG 18 #define TI_F_CABLE_DIAG_TEST_ENA TI_BIT(15) #define TI_F_CABLE_DIAG_DISABLE_TX TI_BIT(14) #define TI_F_CABLE_TEST_PAIR(x) TI_ENCODE_BITFIELD(x, 12, 2) #define TI_M_CABLE_TEST_PAIR TI_ENCODE_BITMASK(12, 2) #define TI_X_CABLE_DIAG_STATUS(x) TI_EXTRACT_BITFIELD(x, 8, 2) #define TI_X_CABLE_DIAG_DATA(x) TI_EXTRACT_BITFIELD(x, 0, 8)*/ // Register - 22 /*#define TI_EXT_PAGE_ACCESS_CTRL 22 #define TI_F_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000*/ //#define TI_EXT_PAGE_ACCESS_ADDR_DATA 23 // Register - 18 INTERRUPT_MASK Register #define TI_INTERRUPT_MASK 18 // Same bit fields of this register apply to interrupt status register also #define TI_F_INTERRUPT_MASK_LINK_STATUS TI_BIT(10) #define TI_F_INTERRUPT_MASK_SPEED_STATUS TI_BIT(14) /* MICR Interrupt bits */ #define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) #define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) #define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) #define MII_DP83869_MICR_WOL_INT_EN BIT(3) #define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) #define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) #define MII_DP83869_MICR_JABBER_INT_EN BIT(0) // Register - 26 /*#define TI_UNH_TEST 26 #define TI_F_TEST_RX_CLK TI_BIT(8)*/ // Register - 19 INTERRUPT STATUS #define TI_INTR_STATUS 19 // Register - 20 GEN_CFG2 Register #define TI_GEN_CFG2 20 #define TI_F_SGMII_AUTONEG_EN TI_BIT(7) #define TI_F_SPEED_OPT_EN (TI_BIT(8) | TI_BIT(9)) #define TI_F_DOWNSHIFT_ATTEMPT_MASK (TI_BIT(10) | TI_BIT(11)) #define TI_F_SGMII_SOFT_RESET TI_BIT(12) #define DP83869_DOWNSHIFT_1_COUNT_VAL 0 #define DP83869_DOWNSHIFT_2_COUNT_VAL 1 #define DP83869_DOWNSHIFT_4_COUNT_VAL 2 #define DP83869_DOWNSHIFT_8_COUNT_VAL 3 #define DP83869_DOWNSHIFT_1_COUNT 1 #define DP83869_DOWNSHIFT_2_COUNT 2 #define DP83869_DOWNSHIFT_4_COUNT 4 #define DP83869_DOWNSHIFT_8_COUNT 8 //Register - 30 TI_GEN_CFG4 #define TI_GEN_CFG4 30 #define TI_F_INT_OE TI_BIT(7) //Register - 31 GEN_CTRL Register #define TI_GEN_CTRL 31 #define TI_F_SW_RESET TI_BIT(15) #define TI_F_SW_RESTART TI_BIT(14) //Register - 49 GEN_CFG3 Register #define TI_GEN_CFG3 49 #define TI_SGMII_AUTONEG_TIME(x) (((x) >> 5) & 0x03) //#define TI_SGMII_AUTONEG_TIME TI_BIT_T(5) //Regisiter - 22 BIST_CONTROL Register LOOPBACK_MODE /*#define TI_BIST_CONTROL 22 #define TI_F_PCS_LOOP_CTRL(X) TI_EXTRACT_BITFIELD(X,0,1)*/ #define TI_STRAP_STATUS_1 110 #define TI_X_STRAP_STATUS_STRAP_PHYAD(x) TI_EXTRACT_BITFIELD(x, 9, 3) //Register - 170 IO_MUX_CFG #define TI_IO_MUX_CFG 368 //Register - 479 OP_MODE_DECODE #define TI_OP_MODE_DECODE 479 #define TI_RGMII_COPPER_ETHERNET 0x00 #define TI_RGMII_1000_BASE 0x01 #define TI_RGMII_100_BASE 0x02 #define TI_RGMII_SGMII_BRIDGE 0x03 #define TI_1000M_MEDIA_CONVERT 0x04 #define TI_100M_MEDIA_CONVERT 0x05 #define TI_SGMII_COPPER_ETHERNET 0x06 //Register - 3072 FX_CTRL #define TI_FX_CTRL 3072 #define TI_FX_CTRL_DEFAULT TI_DP83869_BMCR_DEFAULT #define TI_CTRL0_RESTART_AN TI_BIT(9) #define DP83869_STRAP_STS1 0x006e #define DP83869_SGMII_COPPER_ETHERNET 0x06 /* IO_MUX_CFG - Clock output selection */ #define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 #define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 #define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 #define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 #define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 #define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 #define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 #define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa #define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb #define DP83869_CLK_O_SEL_REF_CLK 0xc /* IO_MUX_CFG bits */ #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8) #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 #define DP83869_IO_MUX_CFG_CLK (DP83869_CLK_O_SEL_REF_CLK << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT) #endif