Altium

Design Rule Verification Report

Date: 1/21/2025
Time: 3:49:59 PM
Elapsed Time: 00:00:27
Filename: C:\Users\a0509466\AppData\Local\TempReleases\Snapshot\1\AMPS262A.PcbDoc
Warnings: 0
Rule Violations: 0
Waived Violations: 14

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=7.874mil) (All),(All) 0
Clearance Constraint (Gap=7mil) (HasFootprint('DSF*')),(All) 0
Clearance Constraint (Gap=0mil) (IsKeepOut and InComponentClass('FiducialMark')),(IsPad and InComponentClass('FiducialMark')) 0
Clearance Constraint (Gap=0mil) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Clearance Constraint (Gap=7.874mil) (InPolygon),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=10mil) (MinWidth=20mil) (MaxWidth=65mil) (PreferedWidth=20mil) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=100mil) (Prefered=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Prefered=15mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Minimum Annular Ring (Minimum=5.906mil) (IsVia and InAnyComponent) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Hole Size Constraint (Min=7.874mil) (Max=251mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Minimum Solder Mask Sliver (Gap=3.5mil) (HasFootprint('DSF*')),(All) 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 0
Silk To Solder Mask (Clearance=3.5mil) (HasFootprint('DSF0006A') or HasFootprint('LTST-C170TBKT_Blue')),((IsPad or IsFill or IsRegion)) 0
Silk To Solder Mask (Clearance=3.5mil) (HasFootprint('LTST*')),(All) 0
Silk To Solder Mask (Clearance=3.937mil) (All),(All) 0
Silk To Solder Mask (Clearance=2.2mil) (HasFootprint('1008')),((IsPad or IsFill or IsRegion)) 0
Silk To Solder Mask (Clearance=5mil) ((IsPad or IsFill or IsRegion) and InAnycomponent),(All) 0
Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Silk to Silk (Clearance=3.937mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (InNet('No Net')) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and InComponentClass('Mounting Holes')) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and IsPoly) 0
Board Clearance Constraint (Gap=0mil) ((OnCopper AND (HasFootprint('CONN_USB_DX4R205JJA') OR HasFootprint('SWITCHCRAFT_35RASM'))) and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (Disabled)(HasFootprint('APM_RM3X8MM 2701')),(HasFootprint('Keystone_24434')) 0
Component Clearance Constraint ( Horizontal Gap = 8.5mil, Vertical Gap = 10mil ) (Disabled)(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0603*') or HasFootprint('0805*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1008*') or HasFootprint('2512*') or HasFootprint('Abracon*') or HasFootprint('DBV*') or HasFootprint('DC*') or HasFootprint('DDA*') or HasFootprint('DEM*') or HasFootprint('DFE*') or HasFootprint('DQM*') or HasFootprint('DRL*') or HasFootprint('DRY*') or HasFootprint('DSF*') or HasFootprint('DSS*') or HasFootprint('FDSD*') or HasFootprint('HAR*') or HasFootprint('HXB*') or HasFootprint('IND*') or HasFootprint('LDC*') or HasFootprint('LTST*') or HasFootprint('MPZ*') or HasFootprint('MRA*') or HasFootprint('NFZ*') or HasFootprint('PG*') or HasFootprint('PW*') or HasFootprint('PT*') or HasFootprint('Relay*') or HasFootprint('RGT*') or HasFootprint('RHB*') or HasFootprint('RLT*') or HasFootprint('RSV*') or HasFootprint('SM*') or HasFootprint('SOT*') or HasFootprint('TP*') or HasFootprint('VLS*') or HasFootprint('XAL*') or HasFootprint('XTAL*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0603*') or HasFootprint('0805*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1008*') or HasFootprint('2512*') or HasFootprint('Abracon*') or HasFootprint('DBV*') or HasFootprint('DC*') or HasFootprint('DDA*') or HasFootprint('DEM*') or HasFootprint('DFE*') or HasFootprint('DQM*') or HasFootprint('DRL*') or HasFootprint('DRY*') or HasFootprint('DSF*') or HasFootprint('DSS*') or HasFootprint('FDSD*') or HasFootprint('HAR*') or HasFootprint('HXB*') or HasFootprint('IND*') or HasFootprint('LDC*') or HasFootprint('LTST*') or HasFootprint('MPZ*') or HasFootprint('MRA*') or HasFootprint('NFZ*') or HasFootprint('PG*') or HasFootprint('PW*') or HasFootprint('PT*') or HasFootprint('Relay*') or HasFootprint('RGT*') or HasFootprint('RHB*') or HasFootprint('RLT*') or HasFootprint('RSV*') or HasFootprint('SM*') or HasFootprint('SOT*') or HasFootprint('TP*') or HasFootprint('VLS*') or HasFootprint('XAL*') or HasFootprint('XTAL*')) 0
Component Clearance Constraint ( Horizontal Gap = 250mil, Vertical Gap = Infinite ) (Disabled)(InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 25mil, Vertical Gap = 30mil ) (Disabled)(IsThruComponent),(IsSMTComponent) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 10mil ) (Disabled)(All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 30mil ) (Disabled)(IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (Disabled)(InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (Disabled)(InComponent('H1')),(InComponent('U1')) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (Disabled)(InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) (Disabled)((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (Disabled)(InComponentClass('Logo')),(All) 0
Height Constraint (Min=0mil) (Max=1050mil) (Prefered=500mil) (Disabled)(All) 0
Total 0

Waived Violations Count
Clearance Constraint (Gap=7.874mil) (All),(All) 4
Short-Circuit Constraint (Allowed=No) (All),(All) 4
Minimum Annular Ring (Minimum=5mil) (All) 2
Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly) 4
Total 14

Rule Violations

Waived Violations

Clearance Constraint (Gap=7.874mil) (All),(All)
Clearance Constraint: (Collision < 7.874mil) Between Pad J25-10(67.087mil,1739.173mil) on Multi-Layer And Region (0 hole(s)) Top Layer
Waived by Ramsey Foote at 1/17/2025 3:13:37 PM
Clearance Constraint: (Collision < 7.874mil) Between Pad J25-7(67.087mil,1410.433mil) on Multi-Layer And Region (0 hole(s)) Top Layer
Waived by Ramsey Foote at 1/17/2025 5:01:58 PM
Clearance Constraint: (Collision < 7.874mil) Between Region (0 hole(s)) Top Layer And Track (67.087mil,1410.433mil)(67.087mil,1529.527mil) on Top Layer
Waived by Ramsey Foote at 1/17/2025 5:02:00 PM
Clearance Constraint: (Collision < 7.874mil) Between Region (0 hole(s)) Top Layer And Track (67.087mil,1620.079mil)(67.087mil,1739.173mil) on Top Layer
Waived by Ramsey Foote at 1/17/2025 5:02:32 PM
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Short-Circuit Constraint (Allowed=No) (All),(All)
Short-Circuit Constraint: Between Pad J25-10(67.087mil,1739.173mil) on Multi-Layer And Region (0 hole(s)) Top Layer Location : [X = 759.087mil][Y = 3265.261mil]
Waived by Ramsey Foote at 1/17/2025 3:13:26 PM
Short-Circuit Constraint: Between Pad J25-7(67.087mil,1410.433mil) on Multi-Layer And Region (0 hole(s)) Top Layer Location : [X = 759.087mil][Y = 2952.345mil]
Waived by Ramsey Foote at 1/17/2025 5:02:03 PM
Short-Circuit Constraint: Between Region (0 hole(s)) Top Layer And Track (67.087mil,1410.433mil)(67.087mil,1529.527mil) on Top Layer Location : [X = 759.087mil][Y = 2975.437mil]
Waived by Ramsey Foote at 1/17/2025 5:02:06 PM
Short-Circuit Constraint: Between Region (0 hole(s)) Top Layer And Track (67.087mil,1620.079mil)(67.087mil,1739.173mil) on Top Layer Location : [X = 759.087mil][Y = 3242.169mil]
Waived by Ramsey Foote at 1/17/2025 5:02:43 PM
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Minimum Annular Ring (Minimum=5mil) (All)
Minimum Annular Ring: (3.936mil < 5mil) Pad J25-10(67.087mil,1739.173mil) on Multi-Layer (Annular Ring=3.937mil) On (Top Layer)
Waived by Ramsey Foote at 1/17/2025 5:02:37 PM
Minimum Annular Ring: (3.936mil < 5mil) Pad J25-7(67.087mil,1410.433mil) on Multi-Layer (Annular Ring=3.937mil) On (Top Layer)
Waived by Ramsey Foote at 1/17/2025 5:05:34 PM
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Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly)
Board Outline Clearance(Outline Edge): (27.717mil < 39.37mil) Between Board Edge And Pad J25-10(67.087mil,1739.173mil) on Multi-Layer
Waived by Ramsey Foote at 1/17/2025 5:02:25 PM
Board Outline Clearance(Outline Edge): (27.717mil < 39.37mil) Between Board Edge And Pad J25-7(67.087mil,1410.433mil) on Multi-Layer
Waived by Ramsey Foote at 1/17/2025 5:05:40 PM
Board Outline Clearance(Outline Edge): (27.717mil < 35mil) Between Board Edge And Pad J25-8(67.087mil,1529.527mil) on Top Layer
Waived by Ramsey Foote at 1/17/2025 5:05:44 PM
Board Outline Clearance(Outline Edge): (27.717mil < 35mil) Between Board Edge And Pad J25-9(67.087mil,1620.079mil) on Top Layer
Waived by Ramsey Foote at 1/17/2025 5:05:48 PM
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