// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2023 NXP */ /dts-v1/; #include #include #include #include "imx95.dtsi" #define FALLING_EDGE BIT(0) #define RISING_EDGE BIT(1) / { model = "NXP i.MX95 19X19 board"; compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; aliases { /* ethernet0,1 swap */ ethernet0 = &enetc_port1; ethernet1 = &enetc_port0; ethernet2 = &enetc_port2; rtc0 = &rx8900; rtc1 = &scmi_bbm; mtd0 = &flash0; mtd1 = &flash4; /*mtd2 = &flash1; mtd3 = &flash2;*/ }; chosen { stdout-path = &lpuart6; #address-cells = <2>; #size-cells = <2>; /* will be updated by U-boot when booting Xen */ module@0 { bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; compatible = "xen,linux-zimage", "xen,multiboot-module"; reg = <0x00000000 0x9e000000 0x00000000 0x2000000>; }; }; fan0: pwm-fan { compatible = "pwm-fan"; cooling-min-state = <0>; cooling-max-state = <3>; #cooling-cells = <2>; pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; cooling-levels = <64 128 192 255>; }; memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; linux_cma: linux,cma { compatible = "shared-dma-pool"; reusable; size = <0 0x3c000000>; alloc-ranges = <0 0x80000000 0 0x7F000000>; linux,cma-default; }; vpu_boot: vpu_boot@a0000000 { reg = <0 0xa0000000 0 0x100000>; no-map; }; vdev0vring0: vdev0vring0@88000000 { reg = <0 0x88000000 0 0x8000>; no-map; }; vdev0vring1: vdev0vring1@88008000 { reg = <0 0x88008000 0 0x8000>; no-map; }; vdev1vring0: vdev1vring0@88010000 { reg = <0 0x88010000 0 0x8000>; no-map; }; vdev1vring1: vdev1vring1@88018000 { reg = <0 0x88018000 0 0x8000>; no-map; }; rsc_table: rsc-table@88220000 { reg = <0 0x88220000 0 0x1000>; no-map; }; vdevbuffer: vdevbuffer@88020000 { compatible = "shared-dma-pool"; reg = <0 0x88020000 0 0x100000>; no-map; }; }; reg_usb_otg_vbus: regulator-usb-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio_exp2 13 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; reg_audio_pwr: regulator-audio-pwr { compatible = "regulator-fixed"; regulator-name = "audio-pwr"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; }; reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; regulator-name = "+V1.8_SW"; }; reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "+V3.3_SW"; }; reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; regulator-name = "VDD_SD2_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; off-on-delay-us = <12000>; enable-active-high; }; reg_pcie0: regulator-pcie { compatible = "regulator-fixed"; regulator-name = "PCIE_WLAN_EN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; regulator-always-on; }; reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; reg_slot_pwr: regulator-slot-pwr { compatible = "regulator-fixed"; regulator-name = "PCIe slot-power"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; regulator-always-on; }; reg_aqr_stby: regulator-aqr-stby { compatible = "regulator-fixed"; regulator-name = "aqr-stby"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; regulator-always-on; }; reg_aqr_en: regulator-aqr-en { compatible = "regulator-fixed"; regulator-name = "aqr-en"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <®_aqr_stby>; enable-active-high; }; cm7: imx95-cm7 { compatible = "fsl,imx95-cm7"; mbox-names = "tx", "rx", "rxdb"; mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; fsl,startup-delay-ms = <50>; status = "disabled"; }; /*sound: sound { compatible = "fsl,imx-audio-sgtl5000"; model = "sgtl5000"; ssi-controller = <&sai3>; audio-codec = <&acodec>; no-audmux; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", "Headphone Jack", "HP_OUT"; };*/ /*sound_hdmi: sound-hdmi { compatible = "simple-audio-card"; simple-audio-card,name = "sound-hdmi"; simple-audio-card,format = "i2s"; simple-audio-card,cpu { sound-dai = <&sai5>; system-clock-direction-out; }; simple-audio-card,codec { sound-dai = <<9611uxc>; }; };*/ extcon_usb_otg: extcon_usb_otg@1 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; }; lvds_backlight0: lvds_backlight@0 { compatible = "pwm-backlight"; pwms = <&tpm3 3 5000000 0>; status = "disabled"; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; default-brightness-level = <80>; }; lvds_backlight1: lvds_backlight@1 { compatible = "pwm-backlight"; pwms = <&tpm4 3 5000000 0>; status = "disabled"; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; default-brightness-level = <80>; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; lid@1 { label = "LID KEY"; gpios = <&gpio_exp1 14 GPIO_ACTIVE_HIGH>; linux,input-type = ; //EV_KEY 1, EV_PWR 22 linux,code = ; //KEY_SUSPEND 205, KEY_SLEEP 142, KEY_POWER 116 wakeup-source; debounce-interval = <100>; }; sleep@2 { label = "SLEEP KEY"; gpios = <&gpio_exp1 15 GPIO_ACTIVE_HIGH>; linux,input-type = ; //EV_KEY 1, EV_PWR 22 linux,code = ; //KEY_SUSPEND 205, KEY_SLEEP 142, KEY_POWER 116 wakeup-source; debounce-interval = <100>; }; }; }; &adc1 { vref-supply = <®_vref_1v8>; status = "okay"; }; &displaymix_irqsteer { status = "okay"; }; &dpu { status = "okay"; }; &tpm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm3>; status = "okay"; }; &tpm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm4>; status = "okay"; }; &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; status = "okay"; }; &flexcan3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan3>; status = "okay"; }; &flexspi1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_flexspi1>; pinctrl-1 = <&pinctrl_flexspi1>; status = "okay"; flash0: w25q64jwssiq@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor", "winbond,w25q64"; spi-max-frequency = <29000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; }; flash4: w25q64jwssiq@1 { reg = <1>; #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor", "winbond,w25q64"; spi-max-frequency = <29000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; }; }; &lpi2c2 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c2>; pinctrl-1 = <&pinctrl_lpi2c2>; status = "okay"; gpio_exp1: pca6416@20 { compatible = "nxp,pca6416"; #gpio-cells = <2>; gpio-controller; reg = <0x20>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpio2>; interrupts = <13 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpioexp1>; vcc-supply = <®_1p8v>; }; gpio_exp2: pca6416@21 { compatible = "nxp,pca6416"; #gpio-cells = <2>; gpio-controller; reg = <0x21>; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpio2>; interrupts = <26 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpioexp2>; vcc-supply = <®_3p3v>; }; wdt: msp430g2202@29 { compatible = "fsl,adv-wdt-i2c"; reg = <0x29>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdt>; wdt-en-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; wdt-ping-gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; lt9611uxc: lt9611uxc@2b { compatible = "lontium,lt9611uxc"; status = "disabled"; reg = <0x2b>; #sound-dai-cells = <0>; reset-gpios = <&gpio_exp2 5 GPIO_ACTIVE_HIGH>; /* DSI_RST */ interrupts-extended = <&gpio_exp2 3 IRQ_TYPE_EDGE_FALLING>; /* DSI_HDMI_INT */ }; st33htpi: st33htpi@2e { compatible = "st,st33htpm-i2c"; reg = <0x2e>; pinctrl-names = "default"; }; rx8900: rx8900c@32 { compatible = "epson,rx8900"; reg = <0x32>; status = "okay"; }; adp5585: mfd@34 { compatible = "adi,adp5585"; reg = <0x34>; adp5585gpio: gpio-adp5585 { compatible = "adp5585-gpio"; gpio-controller; #gpio-cells = <2>; }; adp5585pwm: pwm-adp5585 { compatible = "adp5585-pwm"; #pwm-cells = <3>; }; }; eeprom1: 24c64@50 { compatible = "st,24c64"; reg = <0x50>; }; }; &lpi2c3 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c3>; pinctrl-1 = <&pinctrl_lpi2c3>; status = "okay"; ov5640_0: ov5640_adv@3c { compatible = "ovti,ov5640_adv"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_csi1_pwn>, <&pinctrl_csi1_rst>, <&pinctrl_csi_mclk>; clocks = <&scmi_clk IMX95_CLK_CCMCKO1>; clock-names = "xclk"; assigned-clocks = <&scmi_clk IMX95_CLK_CCMCKO1>; assigned-clock-parents = <&scmi_clk IMX95_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; powerdown-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; mclk = <24000000>; mclk_source = <0>; mipi_csi; pm-runtime; status = "okay"; port { ov5640_adv_0_ep: endpoint { remote-endpoint = <&mipi_csi0_ep>; data-lanes = <1 2>; clock-lanes = <0>; }; }; }; }; / { sound-tas2563 { compatible = "simple-audio-card"; simple-audio-card,name = "tas2563"; simple-audio-card,format = "i2s"; //simple-audio-card,bitclock-inversion; simple-audio-card,frame-master = <&cpu_dai>; simple-audio-card,bitclock-master = <&cpu_dai>; simple-audio-card,widgets = "Speaker", "Ext Spk"; simple-audio-card,routing = "Speaker", "SPK_OUT"; cpu_dai: simple-audio-card,cpu { sound-dai = <&sai3>; dai-tdm-slot-num = <1>; dai-tdm-slot-width = <16>; }; codec_dai: simple-audio-card,codec { sound-dai = <&audio_amp>; }; }; }; &lpi2c4 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c4>; pinctrl-1 = <&pinctrl_lpi2c4>; status = "okay"; gpio_expander: gpio@74 { compatible = "ti,tca9539"; reg = <0x74>; pinctrl-names = "default"; gpio-controller; #gpio-cells = <2>; interrupt-parent = <&gpio3>; interrupts = <03 IRQ_TYPE_LEVEL_LOW>; }; /*acodec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&scmi_clk IMX95_CLK_SAI3>; clock-names = "mclk"; pinctrl-names = "default"; VDDA-supply = <®_audio_pwr>; VDDIO-supply = <®_audio_pwr>; };*/ audio_amp: tas2563@4c { compatible = "ti,tas2563"; reg = <0x4c>; #sound-dai-cells = <0>; ti,reset-gpio = <&gpio_expander 0 GPIO_ACTIVE_HIGH>; //ti,irq-gpio = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; ti,irq-gpio = <&gpio3 22 IRQ_TYPE_LEVEL_LOW>; ti,asi-format = <0>; /* 0, i2S; 1, DSP; */ ti,left-slot = <0>; /* */ //ti,right-slot = <1>; /* */ ti,imon-slot-no = <0>; /* */ ti,vmon-slot-no = <2>; /* */ ti,i2s-bits = <16>; /* support 16, 24, 32 */ ti,bypass-tmax = <0>; /* 0, not bypass; 1, bypass */ clocks = <&scmi_clk IMX95_CLK_SAI3>; clock-names = "mclk"; vdd-supply = <®_3p3v>; iovdd-supply = <®_1p8v>; }; eeprom2: 24c64@50 { compatible = "st,24c64"; reg = <0x50>; }; gpio_exp3: tca9538@70 { compatible = "nxp,pca9538"; reg = <0x70>; gpio-controller; #gpio-cells = <2>; }; }; &lpi2c7 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c7>; pinctrl-1 = <&pinctrl_lpi2c7>; status = "okay"; hcd3020@44 { compatible = "hcd3020,sht3x"; reg = <0x44>; }; eeprom3: 24c64@57 { compatible = "st,24c64"; reg = <0x57>; }; }; &lpi2c8 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_lpi2c8>; pinctrl-1 = <&pinctrl_lpi2c8>; status = "okay"; }; &dphy_rx { status = "okay"; }; &mipi_csi0 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mipi_csi0_ep: endpoint { remote-endpoint = <&ov5640_adv_0_ep>; data-lanes = <1 2>; clock-lanes = <0>; }; }; port@1 { reg = <1>; mipi_csi0_out: endpoint { remote-endpoint = <&formatter_0_in>; }; }; }; }; &csi_pixel_formatter_0 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; formatter_0_in: endpoint { remote-endpoint = <&mipi_csi0_out>; }; }; port@1 { reg = <1>; formatter_0_out: endpoint { remote-endpoint = <&isi_in_2>; }; }; }; }; &isi { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@2 { reg = <2>; isi_in_2: endpoint { remote-endpoint = <&formatter_0_out>; }; }; }; }; &lpuart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "disabled"; }; &lpuart5 { /* BT */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; fsl,uart-has-rtscts; linux,rs485-enabled-at-boot-time; rs485-rx-during-tx; status = "okay"; }; &lpuart6 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart6>; fsl,uart-has-rtscts; linux,rs485-enabled-at-boot-time; rs485-rx-during-tx; status = "okay"; }; &lpspi4 { fsl,spi-num-chipselects = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi4>; cs-gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; status = "okay"; tpm: tpm_tis@0 { compatible = "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <10000000>; }; /*flash1: w25q64jwssiq@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor", "winbond,w25q64"; spi-max-frequency = <25000000>; }; flash2: w25q64jwssiq@1 { reg = <1>; #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor", "winbond,w25q64"; spi-max-frequency = <25000000>; };*/ }; &mu7 { status = "okay"; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; pinctrl-3 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; no-sdio; no-sd; status = "okay"; }; &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; fsl,cd-gpio-wakeup-disable; vmmc-supply = <®_usdhc2_vmmc>; bus-width = <4>; status = "okay"; }; &enetc_port0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enetc0>; phy-handle = <ðphy0>; phy-mode = "rgmii-id"; if-name = "eth1"; /* ethernet0,1 swap */ status = "okay"; }; &enetc_port1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enetc1>; phy-handle = <ðphy1>; phy-mode = "rgmii-id"; if-name = "eth0"; /* ethernet0,1 swap */ status = "okay"; }; &enetc_port2 { phy-handle = <ðphy2>; phy-mode = "10gbase-r"; managed = "in-band-status"; status = "okay"; }; &netc_timer { status = "okay"; }; &netc_prb_ierb { netc-interfaces = ; }; &netc_emdio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emdio>; phy-supply = <®_aqr_en>; status = "okay"; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; }; ethphy0: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; eee-broken-1000t; }; ethphy2: ethernet-phy@8 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <8>; }; }; &usb2 { dr_mode = "host"; status = "okay"; }; &thermal_zones { a55 { trips { atrip2: trip2 { temperature = <55000>; hysteresis = <2000>; type = "active"; }; atrip3: trip3 { temperature = <65000>; hysteresis = <2000>; type = "active"; }; atrip4: trip4 { temperature = <75000>; hysteresis = <2000>; type = "active"; }; }; cooling-maps { map1 { trip = <&atrip2>; cooling-device = <&fan0 0 1>; }; map2 { trip = <&atrip3>; cooling-device = <&fan0 1 2>; }; map3 { trip = <&atrip4>; cooling-device = <&fan0 2 3>; }; }; }; pf09 { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&scmi_sensor 2>; trips { pf09_alert: trip0 { temperature = <140000>; hysteresis = <2000>; type = "passive"; }; pf09_crit: trip1 { temperature = <155000>; hysteresis = <2000>; type = "critical"; }; }; }; pf53_arm { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&scmi_sensor 4>; trips { pf5301_alert: trip0 { temperature = <140000>; hysteresis = <2000>; type = "passive"; }; pf5301_crit: trip1 { temperature = <155000>; hysteresis = <2000>; type = "critical"; }; }; cooling-maps { map0 { trip = <&pf5301_alert>; cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; pf53_soc { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&scmi_sensor 3>; trips { pf5302_alert: trip0 { temperature = <140000>; hysteresis = <2000>; type = "passive"; }; pf5302_crit: trip1 { temperature = <155000>; hysteresis = <2000>; type = "critical"; }; }; }; }; &usb3 { status = "okay"; }; &usb3_phy { status = "okay"; }; &usb3_dwc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg>; dr_mode = "host"; extcon = <&extcon_usb_otg>; vbus-supply = <®_usb_otg_vbus>; status = "okay"; }; &scmi_misc { status = "disabled"; }; &scmi_iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; pinctrl_hog: hoggrp { fsl,pins = < IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x51e /* GPIO0 */ IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x51e /* GPIO2 */ IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x51e /* GPIO4 */ IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x51e /* GPIO5 */ IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x51e /* GPIO6 */ IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x51e /* GPIO7 */ >; }; pinctrl_tpm3: tpm3grp { fsl,pins = < IMX95_PAD_GPIO_IO24__TPM3_CH3 0x51e /* LCD0_BKLT_PWM */ >; }; pinctrl_tpm4: tpm4grp { fsl,pins = < IMX95_PAD_GPIO_IO25__TPM4_CH3 0x51e /* LCD1_BKLT_PWM */ >; }; pinctrl_flexcan1: flexcan1grp { fsl,pins = < IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e >; }; pinctrl_flexcan3: flexcan3grp { fsl,pins = < IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e >; }; pinctrl_lpi2c1: lpi2c1grp { fsl,pins = < IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e >; }; pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e >; }; pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e >; }; pinctrl_lpi2c4: lpi2c4grp { fsl,pins = < IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e >; }; pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e >; }; pinctrl_lpi2c8: lpi2c8grp { fsl,pins = < IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e >; }; pinctrl_uart1: uart1grp { fsl,pins = < IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e >; }; pinctrl_uart5: uart5grp { fsl,pins = < IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e IMX95_PAD_GPIO_IO01__LPUART5_RX 0x31e IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e >; }; pinctrl_uart6: uart6grp { fsl,pins = < IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e IMX95_PAD_GPIO_IO05__LPUART6_RX 0x31e IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e >; }; pinctrl_lpspi4: lpspi4grp { fsl,pins = < IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x3fe /* SPI4_CS0 */ IMX95_PAD_GPIO_IO35__LPSPI4_SIN 0x3fe IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x3fe IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x3fe >; }; pinctrl_emdio: emdiogrp{ fsl,pins = < IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e >; }; pinctrl_enetc1: enetc1grp { fsl,pins = < IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x5fe IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x5fe IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e >; }; pinctrl_enetc0: enetc0grp { fsl,pins = < IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e >; }; pinctrl_flexspi1: flexspi1grp { fsl,pins = < IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x3fe IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe >; }; pinctrl_gpioexp1: gpioexp1grp { fsl,pins = < IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x31e >; }; pinctrl_gpioexp2: gpioexp2grp { fsl,pins = < IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x31e >; }; pinctrl_wdt: wdt_grp { fsl,pins = < IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x31e /* WDT_EN */ IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x31e /* WDT_TRIG */ >; }; pinctrl_sai1: sai1grp { fsl,pins = < IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e >; }; pinctrl_sai3: sai3grp { fsl,pins = < IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x31e IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e >; }; pinctrl_sai5: sai5grp { fsl,pins = < IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x31e IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x31e IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x31e >; }; pinctrl_usb_otg: usb_otg_grp { fsl,pins = < IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x31e >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe >; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e >; }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; pinctrl_csi_mclk: csi_mclk_grp { fsl,pins = < IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x39e >; }; pinctrl_csi1_pwn: csi1_pwn_grp { fsl,pins = < IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 0x31e >; }; pinctrl_csi1_rst: csi1_rst_grp { fsl,pins = < IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x31e >; }; }; &vpuctrl { boot = <&vpu_boot>; sram = <&sram1>; }; &pcie0 { fsl,refclk-pad-mode = ; reset-gpio = <&gpio_exp2 12 GPIO_ACTIVE_LOW>; /* PCIE1_RST */ vpcie-supply = <®_pcie0>; status = "okay"; }; &pcie1 { fsl,refclk-pad-mode = ; reset-gpio = <&gpio_exp2 11 GPIO_ACTIVE_LOW>; /* PCIE2_RST */ vpcie-supply = <®_slot_pwr>; status = "okay"; }; &sai1 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, <&scmi_clk IMX95_CLK_AUDIOPLL2>, <&scmi_clk IMX95_CLK_SAI1>; assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; fsl,sai-mclk-direction-output; status = "okay"; }; &sai3 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, <&scmi_clk IMX95_CLK_AUDIOPLL2>, <&scmi_clk IMX95_CLK_SAI3>; assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; fsl,sai-mclk-direction-output; fsl,sai-synchronous-rx; status = "okay"; }; &sai5 { #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai5>; assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, <&scmi_clk IMX95_CLK_AUDIOPLL2>, <&scmi_clk IMX95_CLK_SAI5>; assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; fsl,sai-mclk-direction-output; status = "okay"; }; &display_pixel_link { status = "okay"; }; &dpu { assigned-clocks = <&scmi_clk IMX95_CLK_DISP1PIX>, <&scmi_clk IMX95_CLK_VIDEOPLL1_VCO>, <&scmi_clk IMX95_CLK_VIDEOPLL1>; assigned-clock-parents = <&scmi_clk IMX95_CLK_VIDEOPLL1>; #assigned-clock-rates = <0>, <2673000000>, <297000000>; assigned-clock-rates = <0>, <4008000000>, <445333334>; }; <9611uxc { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; lt9611uxc_from_dsim: endpoint { remote-endpoint = <&dsim_to_lt9611uxc>; }; }; }; }; &mipi_dsi { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; dsim_to_lt9611uxc: endpoint { remote-endpoint = <<9611uxc_from_dsim>; }; }; }; }; &pixel_interleaver { #address-cells = <1>; #size-cells = <0>; status = "okay"; channel@0 { reg = <0>; status = "okay"; }; };