******************************************************************************** * *[File name] SN74LV1T32.cir *[File Rev] 1.0 *[Date] 2018-08-21 00:00:00 *[Source] * Texas Instruments Incorporated. * Standard Logic, SLHR * 12500 TI Blvd * Dallas, TX -75243 * *[Notes] Revision History: * Rev 1.0: 2018-08-21 00:00:00 * - Initial version of the model * - Model generated from datasheet values * - Built using generic logic gate behavioral pspice model V2 * - Build using an automated model which generalizes parts under same family * - Performance is expected typical behavior at 25C * - Written for and tested with Tina-TI Version 9.3.100.244 SF-TI * ******************************************************************************** *[Disclaimer] * This model is designed as an aid for customers of Texas Instruments. * TI and its licensors and suppliers make no warranties, either expressed * or implied, with respect to this model, including the warranties of * merchantability or fitness for a particular purpose. The model is * provided solely on an "as is" basis. The entire risk as to its quality * and performance is with the customer. * *[Copyright] *(C) Copyright 2016 Texas Instruments Incorporated.All rights reserved. * * ******************************************************************************** * SN74LV1T32 ******************************************************************************** .SUBCKT GATE_2INPUT_LVC_2i_OR_PP_CMOS Y A B VCC AGND XU1 Y A B VCC AGND LOGIC_GATE_2PIN_OD_LVC_2i_OR_PP_CMOS .ENDS *$ .SUBCKT LOGIC_GATE_2PIN_OD_LVC_2i_OR_PP_CMOS OUT A B VCC GND .PARAM VCC_ABS_MAX = 7 .PARAM VCC_MAX = 5.5 .PARAM RA = 880000000 .PARAM RB = 880000000 .PARAM CA = 2e-12 .PARAM CB = 2e-12 .PARAM ROEZ = 36.36363636363637 .PARAM COEZ = 2.5e-12 RA A GND {RA} RB B GND {RB} CA A GND {CA} CB B GND {CB} XUA NA A VCC GND LOGIC_INPUT_LVC_2i_OR_PP_CMOS XUB NB B VCC GND LOGIC_INPUT_LVC_2i_OR_PP_CMOS XUG NA NB NOUTG VCC GND LOGIC_FUNCTION_2_LVC_2i_OR_PP_CMOS XOUTPD NOUTG NOUTTPD VCC GND TPD_LVC_2i_OR_PP_CMOS XUOUT NOUTTPD NOUT_INT VCC GND LOGIC_PP_OUTPUT_LVC_2i_OR_PP_CMOS XICC VCC GND NVIOUT LOGIC_ICC_LVC_2i_OR_PP_CMOS SICC VCC GND VCC GND SW1 * Monitor Output Current * H1 NVIOUT GND VIOUT 1 VIOUT NOUT_INT OUTsw 0 SIOFF OUTsw OUT VCC GND SW2 *DA1 NA1 VCC D1 DA2 GND A D1 *DB1 NB1 VCC D1 DB2 GND B D1 *DC1 NC1 VCC D1 *DO1 NO1 VCC D1 DO2 GND OUT D1 SDA1 NA1 A VCC GND SW2 SDB1 NB1 B VCC GND SW2 SDO1 NO1 OUT VCC GND SW2 .MODEL SW1 VSWITCH VON = {VCC_ABS_MAX} VOFF = {VCC_MAX} RON = 10 ROFF = 60e6 .MODEL SW2 VSWITCH VON = {0.55} VOFF = {0.45} RON = 10m ROFF = 100e6 .MODEL D1 D .ENDS *$ .SUBCKT LOGIC_INPUT_LVC_2i_OR_PP_CMOS OUT IN VCC VEE .PARAM STANDARD_INPUT_SELECT = 1 .PARAM SCHMITT_TRIGGER_INPUT_SELECT = 0 ESTD_THR VSTD_THR VEE TABLE {V(VCC,VEE)} = +(1,0.5) +(1.8,0.9) +(2.5,1.25) +(3.3,1.65) +(5,2.5) +(6,3) ETRP_P VTRP_P VEE TABLE {V(VCC,VEE)} = +(0.8,0.5) +(1.1,0.685) +(1.4,0.825) +(1.65,0.975) +(2.3,1.335) ETRP_N VTRP_N VEE TABLE {V(VCC,VEE)} = +(0.8,0.3) +(1.1,0.375) +(1.4,0.44) +(1.65,0.505) +(2.3,0.725) EHYST VHYST VEE TABLE {V(VCC,VEE)} = +(0.8,0.2) +(1.1,0.31) +(1.4,0.385) +(1.65,0.47) +(2.3,0.61) ETRUE NTRUE VEE VALUE = {V(VCC,VEE)} EFALSE NFALSE VEE VALUE = {0} EBETA BETA VEE VALUE = {V(VHYST,VEE)/(V(NTRUE,VEE) - V(NFALSE,VEE) + V(VHYST,VEE))} EFB NFB VEE VALUE = {(1 - V(BETA,VEE))*V(IN,VEE) + V(BETA,VEE)*V(CURR_OUT,VEE)} *EFB NFB VEE VALUE = {(1 - V(BETA,VEE))*V(IN,VEE) + V(BETA,VEE)*V(OUT,VEE)} EREF NREF VEE VALUE = {0.5*(1 - V(BETA,VEE))*(V(VTRP_P,VEE) + V(VTRP_N,VEE)) + + 0.5*V(BETA,VEE)*(V(NTRUE,VEE) + V(NFALSE,VEE))} EDIFF NDIFF VEE VALUE = {V(NFB,NREF)} *ECOMP OUT VEE VALUE = {0.5*V(VCC,VEE)*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))} GCOMP VEE CURR_OUT VALUE = {SCHMITT_TRIGGER_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(NDIFF,VEE)) + ABS(SGN(V(NDIFF,VEE))))} GSTD VEE CURR_OUT VALUE = {STANDARD_INPUT_SELECT*0.5*V(VCC,VEE)*(SGN(V(IN,VSTD_THR)) + ABS(SGN(V(IN,VSTD_THR))))} ROUT CURR_OUT VEE 1 EMID MID VEE VALUE = {0.5*(V(VCC,VEE) + V(VEE))} EARG NARG VEE VALUE = {V(CURR_OUT,VEE) - V(MID,VEE)} EOUT OUT VEE VALUE = {0.5*(SGN(V(NARG,VEE)) + ABS(SGN(V(NARG,VEE) ) ) )} *EOUT OUT VEE CURR_OUT VEE 1 .ENDS *$ .SUBCKT LOGIC_FUNCTION_2_LVC_2i_OR_PP_CMOS A B OUT VCC VEE .PARAM AND = 0 .PARAM NAND = 0 .PARAM OR = 1 .PARAM NOR = 0 .PARAM XOR = 0 .PARAM XNOR = 0 GAND VEE N1 VALUE = {AND*V(A,VEE)*V(B,VEE)} GNAND VEE N1 VALUE = {NAND*(1 - V(A,VEE)*V(B,VEE))} GOR VEE N1 VALUE = {OR*(MIN(V(A,VEE) + V(B,VEE),1))} GNOR VEE N1 VALUE = {NOR*(1 - MIN(V(A,VEE) + V(B,VEE),1))} GXOR VEE N1 VALUE = {XOR*((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE)))} GXNOR VEE N1 VALUE = {XNOR*(1 - ((1 - V(A,VEE))*V(B,VEE) + V(A,VEE)*(1 - V(B,VEE))))} RN1 N1 VEE 1 EOUT OUT VEE N1 VEE 1 .ENDS *$ *$ .SUBCKT TPD_LVC_2i_OR_PP_CMOS IN OUT VCC VEE .PARAM TPDELAY1 = 1N .PARAM RS = 10K .PARAM CS = {-TPDELAY1/(RS*LOG(0.5))} *ETPDNORM NTPDNORM VEE TABLE {V(VCC,VEE)} = *+({VCC1},{TPDELAY1/TPDELAY4}) *+({VCC2},{TPDELAY2/TPDELAY4}) *+({VCC3},{TPDELAY3/TPDELAY4}) *+({VCC4},{TPDELAY4/TPDELAY4}) ETPDNORM NTPDNORM VEE TABLE {V(VCC,VEE)} = +(5,4.5) +(3,4.9) +(2.5,6.25) +(1.8,10.75) *R1 IN N1 {RS} G1 IN N1 VALUE = {V(IN,N1)/(V(NTPDNORM,VEE)*RS)} RZ IN N1 10G C1 N1 VEE {CS} E1 N2 VEE VALUE = {0.5*(1 + SGN(V(N1,VEE) - 0.5))} EOUT OUT VEE N2 VEE 1 .ENDS *$ .SUBCKT LOGIC_PP_OUTPUT_LVC_2i_OR_PP_CMOS IN OUT VCC VEE * ROH1 = {(VCC1 - VOH1)/IOH1} * ROH2 = {(VCC2 - VOH2)/IOH2} * ROH3 = {(VCC3 - VOH3)/IOH3} * ROH4 = {(VCC4 - VOH4)/IOH4} * ROH5 = {(VCC5 - VOH5)/IOH5} * ROL1 = {(VOL1)/IOL1} * ROL2 = {(VOL2)/IOL2} * ROL3 = {(VOL3)/IOL3} * ROL4 = {(VOL4)/IOL4} * ROL5 = {(VOL5)/IOL5} *EROH NROH VEE TABLE {V(VCC,VEE)} = *+({VCC1},{ROH1}) *+({VCC2},{ROH2}) *+({VCC3},{ROH3}) *+({VCC4},{ROH4}) *+({VCC5},{ROH5}) *EROL NROL VEE TABLE {V(VCC,VEE)} = *+({VCC1},{ROL1}) *+({VCC2},{ROL2}) *+({VCC3},{ROL3}) *+({VCC4},{ROL4}) *+({VCC5},{ROL5}) EROH NROH VEE TABLE {V(VCC,VEE)} = +(1.65,185) +(2.3,99.9999999999999) +(3,72.7272727272727) +(4.5,50) EROL NROL VEE TABLE {V(VCC,VEE)} = +(1.65,100) +(2.3,50) +(3,36.3636363636364) +(4.5,37.5) E1 N1 VEE VALUE = {V(VCC,VEE)*V(IN,VEE)} GOUT N1 OUT VALUE = {V(N1,OUT)*(V(IN,VEE)/V(NROH,VEE) + (1 - V(IN,VEE))/V(NROL,VEE))} .ENDS *$ .SUBCKT LOGIC_OD_OUTPUT_LVC_2i_OR_PP_CMOS IN OUT VCC VEE .PARAM VCC1 = 1.65 .PARAM VCC2 = 2.3 .PARAM VCC3 = 3 .PARAM VCC4 = 4.5 .PARAM VOL1 = 0.45 .PARAM VOL2 = 0.3 .PARAM VOL3 = 0.4 .PARAM VOL4 = 0.55 .PARAM IOL1 = 0.004 .PARAM IOL2 = 0.008 .PARAM IOL3 = 0.016 .PARAM IOL4 = 0.032 .PARAM ROL1 = {(VOL1)/IOL1} .PARAM ROL2 = {(VOL2)/IOL2} .PARAM ROL3 = {(VOL3)/IOL3} .PARAM ROL4 = {(VOL4)/IOL4} .PARAM ROL5 = {(VOL5)/IOL5} *EROL NROLx VEE TABLE {V(VCC,VEE)} = *+({VCC1},{ROL1}) *+({VCC2},{ROL2}) *+({VCC4},{ROL4}) *+({VCC5},{ROL5}) EROL NROLx VEE TABLE {V(VCC,VEE)} = +(1.65,112.5) +(2.3,37.5) +(3,25) +(4.5,17.1875) GOUT OUT VEE VALUE = {V(OUT,VEE)*((1 - V(IN,VEE))/V(NROLx,VEE) + (1e-7)*(V(IN,VEE)))} .ENDS *$ .SUBCKT LOGIC_TRI_STATE_OUTPUT_LVC_2i_OR_PP_CMOS IN OUT OEZ VCC VEE .PARAM VCC1 = 1.65 .PARAM VCC2 = 2.3 .PARAM VCC3 = 3 .PARAM VCC4 = 3 .PARAM VCC5 = 4.5 .PARAM VOH1 = 1.2 .PARAM VOH2 = 1.9 .PARAM VOH3 = 2.4 .PARAM VOH4 = 2.3 .PARAM VOH5 = 3.8 .PARAM VOL1 = 0.45 .PARAM VOL2 = 0.3 .PARAM VOL3 = 0.4 .PARAM VOL4 = 0.55 .PARAM VOL5 = 0.55 .PARAM IOH1 = 0.004 .PARAM IOH2 = 0.008 .PARAM IOH3 = 0.016 .PARAM IOH4 = 0.024 .PARAM IOH5 = 0.032 .PARAM IOL1 = 0.004 .PARAM IOL2 = 0.008 .PARAM IOL3 = 0.016 .PARAM IOL4 = 0.024 .PARAM IOL5 = 0.032 .PARAM ROH1 = {(VCC1 - VOH1)/IOH1} .PARAM ROH2 = {(VCC2 - VOH2)/IOH2} .PARAM ROH3 = {(VCC3 - VOH3)/IOH3} .PARAM ROH4 = {(VCC4 - VOH4)/IOH4} .PARAM ROH5 = {(VCC5 - VOH5)/IOH5} .PARAM ROL1 = {(VOL1)/IOL1} .PARAM ROL2 = {(VOL2)/IOL2} .PARAM ROL3 = {(VOL3)/IOL3} .PARAM ROL4 = {(VOL4)/IOL4} .PARAM ROL5 = {(VOL5)/IOL5} *EROH NROH VEE TABLE {V(VCC,VEE)} = *+({VCC1},{ROH1}) *+({VCC2},{ROH2}) *+({VCC3},{ROH3}) *+({VCC4},{ROH4}) *+({VCC5},{ROH5}) *EROL NROL VEE TABLE {V(VCC,VEE)} = *+({VCC1},{ROL1}) *+({VCC2},{ROL2}) *+({VCC3},{ROL3}) *+({VCC4},{ROL4}) *+({VCC5},{ROL5}) EROH NROH VEE TABLE {V(VCC,VEE)} = +(1.65,112.5) +(2.3,50) +(3,37.5) +(3,29.1666666666667) +(4.5,21.875) EROL NROL VEE TABLE {V(VCC,VEE)} = +(1.65,112.5) +(2.3,37.5) +(3,25) +(3,22.9166666666667) +(4.5,17.1875) EOEZ N2 VEE VALUE = {1 - V(OEZ,VEE)} E1 N1 VEE VALUE = {V(VCC,VEE)*V(IN,VEE)*V(N2,VEE)} GOUT N1 OUT VALUE = {V(N1,OUT)*V(N2,VEE)*(V(IN,VEE)/V(NROH,VEE) + (1 - V(IN,VEE))/V(NROL,VEE))} ROUT OUT VEE 1E8 .ENDS *$ .SUBCKT LOGIC_ICC_LVC_2i_OR_PP_CMOS VCC VEE VIOUT .PARAM ICC = 2.5e-08 .PARAM VCC_MAX = 5.5 .PARAM VCC_MIN = 1.6 *GICC VCC VEE VALUE = {ICC*V(VCC,VEE)/VCC_MAX} GICC VCC VEE VALUE = {ICC*0.5*(1 + SGN(V(VCC,VEE) - VCC_MIN))} * * Floating ground at mid-rail EGNDF GNDF 0 VALUE = {0.5*(V(VCC) + V(VEE))} * GOUTP VCC GNDF VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))} GOUTN GNDF VEE VALUE = {V(VIOUT,VEE)*0.5*(SGN(V(VIOUT,VEE)) + ABS(SGN(V(VIOUT,VEE))))} * *GOUTP VCC GNDF VALUE = {IF(V(VIMON,GNDF) > 0, V(VIMON,GNDF),0)} *GOUTN GNDF VEE VALUE = {IF(V(VIMON,GNDF) <= 0, V(VIMON,GNDF),0)} .ENDS *$