//*****************************************************************************
//! @file       cc112x_easy_link_reg_config.h
//! @brief      Template for CC112x register export from SmartRF Studio 
//
//  Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
//
//  Redistribution and use in source and binary forms, with or without
//  modification, are permitted provided that the following conditions
//  are met:
//
//      Redistributions of source code must retain the above copyright
//      notice, this list of conditions and the following disclaimer.
//
//      Redistributions in binary form must reproduce the above copyright
//      notice, this list of conditions and the following disclaimer in the
//      documentation and/or other materials provided with the distribution.
//
//      Neither the name of Texas Instruments Incorporated nor the names of
//      its contributors may be used to endorse or promote products derived
//      from this software without specific prior written permission.
//
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
//  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
//  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
//  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
//  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
//  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
//  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
//  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
//  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//****************************************************************************/

#ifndef CC112X_EASY_LINK_REG_CONFIG_H
#define CC112X_EASY_LINK_REG_CONFIG_H

#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
 * INCLUDES
 */
#include "msp_wm430fr4_cc1120.h"

/******************************************************************************
 * VARIABLES
 */
// Carrier frequency = 869.525024
// Bit rate = 50
// Deviation = 24.963379
// Performance mode = High Performance
// Manchester enable = false
// Packet length = 30
// Packet length mode = Fixed
// Symbol rate = 50
// PA ramping = true
// Modulation format = 2-GFSK
// TX power = 15
// Device address = 0
// Whitening = false
// RX filter BW = 100.000000
// Packet bit length = 0
// Address config = No address check
static const registerSetting_t WMbusCC112xRfSettingsC2mode[] =
{
	    {CC112X_FS_DIG1           ,0x00},
		  {CC112X_FS_DIG0           ,0x5F},
 		   {CC112X_FS_CAL1,           0x40},
		  {CC112X_FS_CAL0           ,0x0E},
		  {CC112X_FS_DIVTWO         ,0x03},
		  {CC112X_FS_DSM0           ,0x33},
		  {CC112X_FS_DVC0           ,0x17},
		  {CC112X_FS_PFD            ,0x50},
		  {CC112X_FS_PRE            ,0x6E},
		  {CC112X_FS_REG_DIV_CML    ,0x14},
		  {CC112X_FS_SPARE          ,0xAC},
 		   {CC112X_FS_VCO4,           0x13},
 		   {CC112X_FS_VCO1,           0x9C},
 		   {CC112X_FS_VCO0,           0xB4},
		  {CC112X_XOSC5             ,0x0E},
		  {CC112X_XOSC4             ,0xA0},
		  {CC112X_XOSC3             ,0x03},
		  {CC112X_XOSC1             ,0x03},
		  {CC112X_ANALOG_SPARE      ,0x00},
		  {CC112X_FIFO_CFG          ,0x7C}, // TX FIFO Threshold = 124; RX FIFO = 4
		  {CC112X_SETTLING_CFG,      0x03},
		  {CC112X_FS_CFG,            0x12},
		  {CC112X_PKT_CFG2          ,0x04}, //Packet handling
		  {CC112X_PKT_CFG1          ,0x00}, //Packet handling: Status Byte appended, NO CRC in TX + RX
		  {CC112X_PKT_CFG0          ,0x00}, //Packet handling
		  {CC112X_PKT_LEN           ,0x15}, // Packet handler config.In fixed length mode this field indicates the packet length, and a value of 0 indicates the length to be 256 bytes. In variable length packet mode, this value indicates the maximum allowed length packets.
		  {CC112X_RFEND_CFG1        ,0x0F},
		  {CC112X_RFEND_CFG0        ,0x00},
		  {CC112X_FREQ2,             0x6C}, //869.525
		  {CC112X_FREQ1,             0xB0},
		  {CC112X_FREQ0,             0xCD}, //869.525
		  {CC112X_SYNC3             ,0x54}, // Sync Word
		  {CC112X_SYNC2             ,0x3D}, // Sync Word
		  {CC112X_SYNC1             ,0x54}, // Sync Word C-mode (not T)
		  {CC112X_SYNC0             ,0x3D}, // Sync Word Format B
		  {CC112X_SYNC_CFG1         ,0x05}, //0x5 reduces 54 3D flase detection; Sync Word Detection, less noise in SYNC Word
		  {CC112X_SYNC_CFG0         ,0x17}, //Sync Word Detection, 32 Bits SyncWord 0x543D 543D
		  {CC112X_DEVIATION_M       ,0x99},  //TX with 25kHz DEV
		  {CC112X_MODCFG_DEV_E      ,0x0D},  //2-GFSK
		  {CC112X_DCFILT_CFG        ,0x15},
		  {CC112X_PREAMBLE_CFG1     ,0x19}, //Preamble Length Programming: 4 Bytes of 0x55 + 4Bytes SYNC
		  {CC112X_PREAMBLE_CFG0     ,0x2A}, //Preamble Detection Programming Default
		  {CC112X_FREQ_IF_CFG       ,0x3A},
		  {CC112X_IQIC              ,0x00},
		  {CC112X_CHAN_BW           ,0x02},  //100kHz
		  {CC112X_MDMCFG1           ,0x46},
		  {CC112X_MDMCFG0           ,0x05},
		  {CC112X_SYMBOL_RATE2,      0x99}, //50kbps
		  {CC112X_SYMBOL_RATE1,      0x99},
		  {CC112X_SYMBOL_RATE0,      0x99},
		  {CC112X_AGC_REF           ,0x3C},
		  {CC112X_AGC_CS_THR        ,0xEF},
		  {CC112X_AGC_GAIN_ADJUST   ,0x00},
		  {CC112X_AGC_CFG3          ,0x91},
		  {CC112X_AGC_CFG2          ,0x20},
		  {CC112X_AGC_CFG1          ,0xA9},
		  {CC112X_AGC_CFG0          ,0xC0},
		  {CC112X_PA_CFG2           ,0x7F}, //Power Amplifier Level Programming: + 15 dBm
		  {CC112X_PA_CFG1           ,0x56}, //Power Amplifier Level Programming
		  {CC112X_PA_CFG0           ,0x7A}, //Power Amplifier Level Programming
		  {CC112X_IF_MIX_CFG        ,0x00},
		  {CC112X_FREQOFF_CFG       ,0x20},
		  {CC112X_TOC_CFG           ,0x0A},
		  {CC112X_IOCFG3,            0x01}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
					// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
					//  {CC112X_IOCFG2,            0x06},
		  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
					  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
					  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows
};

// Carrier frequency = 868.950
// Symbol rate = 66,67 kbps (due to 3-of-6 coding)
// Bit rate = 100kbps
// Deviation = 50kHz
// Manchester enable = false 
// Modulation format = 2-FSK 
// RX filter BW = 200.0000
// TX power = +10dBm
// PA ramping = true 
// Packet length mode = fixed
// Whitening = false 
// Address config = No address check. 
// Packet length = 20 Bytes (before coding)
// Device address = 0 
static const registerSetting_t WMbusCC112xRfSettingsTmode[] =
{
  {CC112X_IOCFG3,            0x01}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
				  	  	  	  	  	  	  	  	  	// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
				//  {CC112X_IOCFG2,            0x06},
  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
				  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
				  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows

  {CC112X_FS_DIG1           ,0x00},
  {CC112X_FS_DIG0           ,0x5F},
  {CC112X_FS_CAL0           ,0x0E},
  {CC112X_FS_DIVTWO         ,0x03},
  {CC112X_FS_DSM0           ,0x33},
  {CC112X_FS_DVC0           ,0x17},
  {CC112X_FS_PFD            ,0x50},
  {CC112X_FS_PRE            ,0x6E},
  {CC112X_FS_REG_DIV_CML    ,0x14},
  {CC112X_FS_SPARE          ,0xAC},
  {CC112X_XOSC5             ,0x0E},
  {CC112X_XOSC4             ,0xA0},
  {CC112X_XOSC3             ,0x03},
  {CC112X_XOSC1             ,0x03},
  {CC112X_ANALOG_SPARE      ,0x00},
  {CC112X_FIFO_CFG          ,0x7C}, // TX FIFO Threshold = 124; RX FIFO = 4
  {CC112X_DEV_ADDR          ,0x00},
  {CC112X_SETTLING_CFG      ,0x0B},
  {CC112X_FS_CFG            ,0x12},
  {CC112X_PKT_CFG2          ,0x04}, //Packet handling
  {CC112X_PKT_CFG1          ,0x00}, //Packet handling: Status Byte appended, NO CRC in TX + RX
  {CC112X_PKT_CFG0          ,0x00}, //Packet handling
  {CC112X_PKT_LEN           ,0x1F}, // Packet handler config.In fixed length mode this field indicates the packet length, and a value of 0 indicates the length to be 256 bytes. In variable length packet mode, this value indicates the maximum allowed length packets.
  {CC112X_RFEND_CFG1        ,0x0F},
  {CC112X_RFEND_CFG0        ,0x00},
  {CC112X_FREQ2             ,0x6C},	//868.95
  {CC112X_FREQ1             ,0x9E},
  {CC112X_FREQ0             ,0x66}, //868.85
  {CC112X_SYNC3             ,0x55},  // Sync Word
  {CC112X_SYNC2             ,0x55},  // Sync Word
  {CC112X_SYNC1             ,0x54},  // Sync Word
  {CC112X_SYNC0             ,0x3D},  // Sync Word
//  {CC112X_SYNC_CFG1         ,0x08},  //Sync Word Detection  98/100 received
  {CC112X_SYNC_CFG1         ,0x0a},  //Sync Word Detection
  {CC112X_SYNC_CFG0         ,0x14},  //Sync Word Detection 32-bits
  {CC112X_DEVIATION_M       ,0x9A},  //TX with 50kHz DEV
  {CC112X_MODCFG_DEV_E      ,0x06},  //2-FSK
  {CC112X_DCFILT_CFG        ,0x04},
  {CC112X_PREAMBLE_CFG1     ,0x11}, //Preamble Length Programming: 2 Bytes of 0x55
  {CC112X_PREAMBLE_CFG0     ,0x2A}, //Preamble Detection Programming
  {CC112X_FREQ_IF_CFG       ,0x00},
  {CC112X_IQIC              ,0x00},
  {CC112X_CHAN_BW           ,0x01},
  {CC112X_MDMCFG1           ,0x46},
  {CC112X_MDMCFG0           ,0x05},
  {CC112X_SYMBOL_RATE2           ,0xA9}, //Symbol Rate Programming Exponent:
  {CC112X_SYMBOL_RATE1           ,0x99}, //Symbol Rate Programming Exponent
  {CC112X_SYMBOL_RATE0           ,0x9A}, //Symbol Rate Programming Exponent:
  {CC112X_AGC_REF           ,0x40},
  {CC112X_AGC_CS_THR        ,0xFD},
  {CC112X_AGC_GAIN_ADJUST   ,0x00},
  {CC112X_AGC_CFG3          ,0x03},
  {CC112X_AGC_CFG2          ,0x20},
  {CC112X_AGC_CFG1          ,0xA9},
  {CC112X_AGC_CFG0          ,0xC0},
  {CC112X_PA_CFG2           ,0x7F}, //Power Amplifier Level Programming: + 15 dBm
  {CC112X_PA_CFG1           ,0x56}, //Power Amplifier Level Programming
  {CC112X_PA_CFG0           ,0x78}, //Power Amplifier Level Programming
  {CC112X_IF_MIX_CFG        ,0x00},
  {CC112X_FREQOFF_CFG       ,0x31},
  {CC112X_TOC_CFG           ,0x0B},
};


// C-mode CC112x settings
// Carrier frequency = 868.950
// Symbol rate = 100 kbps
// Bit rate = 100kbps
// Deviation = 45kHz
// Manchester enable = false
// Modulation format = 2-FSK
// RX filter BW = 200.0000
// TX power = +10 dBm
// PA ramping = true
// Packet length mode = FIXED
// Whitening = false
// Address config = No address check.
// Packet length = 21 Bytes (before coding)
// Device address = 0

static const registerSetting_t WMbusCC112xRfSettingsCmode[] =
{
		  {CC112X_IOCFG3,            0x01}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
				  	  	  	  	  	  	  	  	  	// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
				//  {CC112X_IOCFG2,            0x06},
		  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
				  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
				  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows
		  {CC112X_FS_DIG1           ,0x00},
		  {CC112X_FS_DIG0           ,0x5F},
		  {CC112X_FS_CAL0           ,0x0E},
		  {CC112X_FS_DIVTWO         ,0x03},
		  {CC112X_FS_DSM0           ,0x33},
		  {CC112X_FS_DVC0           ,0x17},
		  {CC112X_FS_PFD            ,0x50},
		  {CC112X_FS_PRE            ,0x6E},
		  {CC112X_FS_REG_DIV_CML    ,0x14},
		  {CC112X_FS_SPARE          ,0xAC},
		  {CC112X_XOSC5             ,0x0E},
		  {CC112X_XOSC4             ,0xA0},
		  {CC112X_XOSC3             ,0x03},
		  {CC112X_XOSC1             ,0x03},
		  {CC112X_ANALOG_SPARE      ,0x00},
		  {CC112X_FIFO_CFG          ,0x7C}, // TX FIFO Threshold = 124; RX FIFO = 4
		  {CC112X_DEV_ADDR          ,0x00},
		  {CC112X_SETTLING_CFG      ,0x0B},
		  {CC112X_FS_CFG            ,0x12},
		  {CC112X_PKT_CFG2          ,0x04}, //Packet handling
		  {CC112X_PKT_CFG1          ,0x01}, //Packet handling: Status Byte appended, NO CRC in TX + RX
		  {CC112X_PKT_CFG0          ,0x00}, //Packet handling
		  {CC112X_PKT_LEN           ,0x15}, // Packet handler config.In fixed length mode this field indicates the packet length, and a value of 0 indicates the length to be 256 bytes. In variable length packet mode, this value indicates the maximum allowed length packets.
		  {CC112X_RFEND_CFG1        ,0x0F},
		  {CC112X_RFEND_CFG0        ,0x00},
		  {CC112X_FREQ2             ,0x6C},	//868.95
		  {CC112X_FREQ1             ,0x9E},
		  {CC112X_FREQ0             ,0x66}, //868.85
		  {CC112X_SYNC3             ,0x54}, // Sync Word
		  {CC112X_SYNC2             ,0x3D}, // Sync Word
		  {CC112X_SYNC1             ,0x54}, // Sync Word C-mode (not T)
		  {CC112X_SYNC0             ,0x3D}, // Sync Word Format B
		  {CC112X_SYNC_CFG1         ,0x07}, //Sync Word Detection, LESS noise in Preamble
		  //{CC112X_SYNC_CFG1         ,0x0C}, //Sync Word Detection, more noise in Preamble
		  {CC112X_SYNC_CFG0         ,0x14}, //Sync Word Detection, 32 Bits SyncWord 0x543D 543D
		  {CC112X_DEVIATION_M       ,0x71},  //TX with 45kHz DEV (vs. 50kHz for T-mode)
		  {CC112X_MODCFG_DEV_E      ,0x06},  //2-FSK
		  {CC112X_DCFILT_CFG        ,0x0C},
		  {CC112X_PREAMBLE_CFG1     ,0x19}, //Preamble Length Programming: 2 Bytes + 4Bytes SYNC
		  {CC112X_PREAMBLE_CFG0     ,0x17}, //Preamble Detection Programming
		  {CC112X_FREQ_IF_CFG       ,0x00},
		  {CC112X_IQIC              ,0x00},
		  {CC112X_CHAN_BW           ,0x01},
		  {CC112X_MDMCFG1           ,0x46},
		  {CC112X_MDMCFG0           ,0x05},
		  {CC112X_SYMBOL_RATE2           ,0xA9}, //Symbol Rate Programming Exponent: 868.950MHz
		  {CC112X_SYMBOL_RATE1           ,0x99}, //Symbol Rate Programming Exponent
		  {CC112X_SYMBOL_RATE0           ,0x9A}, //Symbol Rate Programming Exponent: 868.950MHz
		  {CC112X_AGC_REF           ,0x3C},
		  {CC112X_AGC_CS_THR        ,0xF6},
		  {CC112X_AGC_GAIN_ADJUST   ,0x00},
		  {CC112X_AGC_CFG3          ,0x03},
		  {CC112X_AGC_CFG2          ,0x20},
		  {CC112X_AGC_CFG1          ,0xA9},
		  {CC112X_AGC_CFG0          ,0xC0},
		  {CC112X_PA_CFG2           ,0x7F}, //Power Amplifier Level Programming: + 10 dBm
		  {CC112X_PA_CFG1           ,0x56}, //Power Amplifier Level Programming
		  {CC112X_PA_CFG0           ,0x78}, //Power Amplifier Level Programming
		  {CC112X_IF_MIX_CFG        ,0x00},
		  {CC112X_FREQOFF_CFG       ,0x20},
		  {CC112X_TOC_CFG           ,0x0B},
};

//  Register settings for S-mode RX (both TX and RX) for CC1120 Test
// S-mode CC112x settings
// Carrier frequency = 868.300
// Symbol rate =  32.768kbps
// Bit rate = 16.384kbps
// Deviation = 45kHz
// Manchester enable = TRUE
// Modulation format = 2-FSK
// RX filter BW = 200.0000
// TX power = +10 dBm
// PA ramping = true
// Packet length mode = FIXED
// Whitening = false
// Address config = No address check.
// Packet length = 21 Bytes (before coding)
// Device address = 0
static const registerSetting_t WMbusCC112xRfSettingsSmode[] =
{
  {CC112X_IOCFG3,            0x01}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
		  	  	  	  	  	  	  	  	  	// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
		//  {CC112X_IOCFG2,            0x06},
  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
		  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
		  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows
  {CC112X_FIFO_CFG          ,0x7C},  //4 Bytes in RX FIFO
  {CC112X_FS_DIG1           ,0x00},
  {CC112X_FS_DIG0           ,0x5F},
  {CC112X_FS_CAL0           ,0x0E},
  {CC112X_FS_DIVTWO         ,0x03},
  {CC112X_FS_DSM0           ,0x33},
  {CC112X_FS_DVC0           ,0x1F},
  {CC112X_FS_PFD            ,0x50},
  {CC112X_FS_PRE            ,0x6F},
  {CC112X_FS_REG_DIV_CML    ,0x14},
  {CC112X_FS_SPARE          ,0xAC},
  {CC112X_XOSC5             ,0x0E},
  {CC112X_XOSC4             ,0xA0},
  {CC112X_XOSC3             ,0x03},
  {CC112X_XOSC1             ,0x03},
  {CC112X_ANALOG_SPARE      ,0x00},
  {CC112X_FIFO_CFG          ,0x03},  // Read first 3 bytes
  {CC112X_DEV_ADDR          ,0x00},
  {CC112X_SETTLING_CFG      ,0x0B},
  {CC112X_FS_CFG            ,0x12},
  {CC112X_PKT_CFG2          ,0x04},
  {CC112X_PKT_CFG1          ,0x00},
  {CC112X_PKT_CFG0          ,0x00},
  {CC112X_PKT_LEN           ,0x14}, // Packet handler config.In fixed length mode this field indicates the packet length, and a value of 0 indicates the length to be 256 bytes. In variable length packet mode, this value indicates the maximum allowed length packets.
  {CC112X_RFEND_CFG1        ,0x0F},
  {CC112X_RFEND_CFG0        ,0x00},
  {CC112X_FREQ2             ,0x6C},
  {CC112X_FREQ1             ,0x89},
  {CC112X_FREQ0             ,0x99},
  {CC112X_SYNC3             ,0x55},
  {CC112X_SYNC2             ,0x54},
  {CC112X_SYNC1             ,0x76},
  {CC112X_SYNC0             ,0x96},
  {CC112X_SYNC_CFG1         ,0x08},	//08
  {CC112X_SYNC_CFG0         ,0x17}, //
  {CC112X_DEVIATION_M       ,0x9A},  //50kHz
  {CC112X_MODCFG_DEV_E      ,0x0E},
  {CC112X_DCFILT_CFG        ,0x04},
  {CC112X_PREAMBLE_CFG1     ,0x15},
  {CC112X_PREAMBLE_CFG0     ,0x2A},  //3 Bytes preamble of 0x55 + 3 Bytes SYNC
  {CC112X_FREQ_IF_CFG       ,0x2E},
  {CC112X_IQIC              ,0x00},
  {CC112X_CHAN_BW           ,0x01},
  {CC112X_MDMCFG1           ,0x76}, //HW Manchester coding
  {CC112X_MDMCFG0           ,0x01},
  {CC112X_SYMBOL_RATE2            ,0x90},  //32.768kcps
  {CC112X_SYMBOL_RATE1            ,0xC6},
  {CC112X_SYMBOL_RATE0            ,0xF8},
  {CC112X_AGC_REF           ,0x3C},
  {CC112X_AGC_CS_THR        ,0xF6}, //-1zz Bm for CS
  {CC112X_AGC_GAIN_ADJUST   ,0x00},
  {CC112X_AGC_CFG3          ,0x03},
  {CC112X_AGC_CFG2          ,0x20},
  {CC112X_AGC_CFG1          ,0xA9},
  {CC112X_AGC_CFG0          ,0xC0},
  {CC112X_PA_CFG2           ,0x74},
  {CC112X_PA_CFG1           ,0x56},
  {CC112X_PA_CFG0           ,0x7A},
  {CC112X_IF_MIX_CFG        ,0x00},
  {CC112X_FREQOFF_CFG       ,0x20},
  {CC112X_TOC_CFG           ,0x0B},
};

/******************************************************************************
 * VARIABLES
 */

// Packet bit length = 0
// Packet length mode = Fixed
// Carrier frequency = 169.431250
// Manchester enable = false
// Bit rate = 2.4
// Performance mode = High Performance
// Symbol rate = 2.4
// Whitening = false
// Packet length = 31
// Device address = 0
// Modulation format = 2-GFSK
// TX power = 15
// RX filter BW = 7.812500
// PA ramping = true
// Deviation = 2.395630
// Address config = No address check

static const registerSetting_t WMbusCC112xRfSettingsNcd[]=
{
  {CC112X_IOCFG3,            0x06}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
		  	  	  	  	  	  	  	  	  	// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
		//  {CC112X_IOCFG2,            0x06},
  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
		  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
		  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows
  {CC112X_SYNC3,             0x55},
  {CC112X_SYNC2,             0x55},
  {CC112X_SYNC1,             0xF6},
  {CC112X_SYNC0,             0x72},
  {CC112X_SYNC_CFG1,         0x09},
  {CC112X_SYNC_CFG0,         0x0B}, //16-bit preamble
  {CC112X_DEVIATION_M,       0x3A}, //2.4kHz DEV
  {CC112X_MODCFG_DEV_E,      0x0A}, //GFSK
  {CC112X_DCFILT_CFG,        0x1C},
  {CC112X_PREAMBLE_CFG1,     0x11}, //2-Bytes 0x55
  {CC112X_IQIC,              0xC6},
  {CC112X_CHAN_BW,           0x50}, //7.8125 kHz
  {CC112X_MDMCFG0,           0x05},
  {CC112X_SYMBOL_RATE2,      0x53}, //2.4kbps
  {CC112X_SYMBOL_RATE1,      0xA9},
  {CC112X_SYMBOL_RATE0,      0x2A},  //2.4kbps
  {CC112X_AGC_REF,           0x18},
  {CC112X_AGC_CS_THR,        0xF2},
  {CC112X_AGC_CFG1,          0xA9},
  {CC112X_AGC_CFG0,          0xCB},
  {CC112X_FIFO_CFG,          0x7C},
  {CC112X_SETTLING_CFG,      0x03},
  {CC112X_FS_CFG,            0x1A},
  {CC112X_PKT_CFG2          ,0x04}, //Packet handling
  {CC112X_PKT_CFG1          ,0x00}, //Packet handling: Status Byte appended, NO CRC in TX + RX
  {CC112X_PKT_CFG0          ,0x00}, //Packet handling
  {CC112X_PKT_LEN           ,0x15}, // Packet handler config.In fixed length mode this field indicates the packet length, and a value of 0 indicates the length to be 256 bytes. In variable length packet mode, this value indicates the maximum allowed length packets.
  {CC112X_PA_CFG2           ,0x7F},	//+15 dBm
  {CC112X_PA_CFG1           ,0x56},
  {CC112X_PA_CFG0           ,0x7E}, //+15 dBm
  {CC112X_IF_MIX_CFG,        0x00},
  {CC112X_FREQOFF_CFG,       0x32},
  {CC112X_FREQ2,             0x69}, // 169,431250 MHz Nc-channel in EN13757-4:2014; Nd=169,443750
  {CC112X_FREQ1,             0xE5}, // 169,431250 MHz Nc-channel in EN13757-4:2014  -> use 0xE7 for Nd
  {CC112X_FS_DIG1,           0x00},
  {CC112X_FS_DIG0,           0x5F},
  {CC112X_FS_CAL1,           0x40},
  {CC112X_FS_CAL0,           0x0E},
  {CC112X_FS_DIVTWO,         0x03},
  {CC112X_FS_DSM0,           0x33},
  {CC112X_FS_DVC0,           0x17},
  {CC112X_FS_PFD,            0x50},
  {CC112X_FS_PRE,            0x6E},
  {CC112X_FS_REG_DIV_CML,    0x14},
  {CC112X_FS_SPARE,          0xAC},
  {CC112X_FS_VCO0,           0xB4},
  {CC112X_LNA,               0x03},
  {CC112X_XOSC5,             0x0E},
  {CC112X_XOSC2,             0x00},
  {CC112X_XOSC1,             0x03},
};


// RX filter BW = 10.526316
// Symbol rate = 4.8
// Device address = 0
// Bit rate = 4.8
// Modulation format = 2-GFSK
// PA ramping = true
// Address config = No address check
// Whitening = false
// Packet bit length = 0
// Performance mode = High Performance
// Packet length = 24
// Carrier frequency = 169.406250
// Deviation = 2.395630
// Manchester enable = false
// TX power = 15
// Packet length mode = Fixed
static const registerSetting_t WMbusCC112xRfSettingsNabef[]=
{
  {CC112X_IOCFG3,            0x06}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
		  	  	  	  	  	  	  	  	  	// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
		//  {CC112X_IOCFG2,            0x06},
  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
		  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
		  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows
  {CC112X_SYNC3,             0x55},
  {CC112X_SYNC2,             0x55},
  {CC112X_SYNC1,             0xF6},
  {CC112X_SYNC0,             0x72},
  {CC112X_SYNC_CFG1,         0x09},
  {CC112X_SYNC_CFG0,         0x0B},
  {CC112X_DEVIATION_M,       0x3A},
  {CC112X_MODCFG_DEV_E,      0x0A},
  {CC112X_DCFILT_CFG,        0x1C},
  {CC112X_PREAMBLE_CFG1,     0x11}, //2 Bytes preamble of 0x55
  {CC112X_IQIC,              0xC6},
  {CC112X_CHAN_BW,           0x13},	//10.5 kHz with FB2PLL
  {CC112X_MDMCFG0,           0x05},
  {CC112X_SYMBOL_RATE2,      0x63},  //4.8kbps
  {CC112X_AGC_REF,           0x18},
  {CC112X_AGC_CS_THR,        0xF2},
  {CC112X_AGC_CFG1,          0xA9},
  {CC112X_AGC_CFG0,          0xCB},
  {CC112X_SETTLING_CFG,      0x03},
  {CC112X_FS_CFG,            0x1A},
  {CC112X_FIFO_CFG,          0x7C}, // TX FIFO Threshold = 124; RX FIFO = 4
  {CC112X_PKT_CFG2          ,0x04},
  {CC112X_PKT_CFG1          ,0x00},
  {CC112X_PKT_CFG0,          0x00},
  {CC112X_PA_CFG0,           0x7E},
  {CC112X_PKT_LEN,           0x15},
  {CC112X_IF_MIX_CFG,        0x00},
  {CC112X_FREQOFF_CFG,       0x32},	//FB2PLL enabled
  {CC112X_FREQ2,             0x69}, //169.406250 MHz
  {CC112X_FREQ1,             0xE1}, //169.406250 MHz
  {CC112X_FREQ0,             0x00},
  {CC112X_FS_DIG1,           0x00},
  {CC112X_FS_DIG0,           0x5F},
  {CC112X_FS_CAL1,           0x40},
  {CC112X_FS_CAL0,           0x0E},
  {CC112X_FS_DIVTWO,         0x03},
  {CC112X_FS_DSM0,           0x33},
  {CC112X_FS_DVC0,           0x17},
  {CC112X_FS_PFD,            0x50},
  {CC112X_FS_PRE,            0x6E},
  {CC112X_FS_REG_DIV_CML,    0x14},
  {CC112X_FS_SPARE,          0xAC},
  {CC112X_FS_VCO0,           0xB4},
  {CC112X_LNA,               0x03},
  {CC112X_XOSC5,             0x0E},
  {CC112X_XOSC2,             0x00},
  {CC112X_XOSC1,             0x03},
};


// Carrier frequency = 169.437500
// Manchester enable = false
// Device address = 0
// Bit rate = 19.2
// Performance mode = High Performance
// Address config = No address check
// Packet length mode = Variable
// Whitening = false
// Modulation format = 4-GFSK
// TX power = 10
// Deviation = 7.202148
// RX filter BW = 50.000000
// Packet bit length = 0
// Symbol rate = 9.6
// Packet length = 255
// PA ramping = true
static const registerSetting_t WMbusCC112xRfSettingsNg[]=
{
  {CC112X_IOCFG3,            0x06}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
		  	  	  	  	  	  	  	  	  	// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
		//  {CC112X_IOCFG2,            0x06},
  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
		  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
		  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows
  {CC112X_SYNC3,             0x55},
  {CC112X_SYNC2,             0x55},
  {CC112X_SYNC1,             0xF6},
  {CC112X_SYNC0,             0x72},
  {CC112X_SYNC_CFG1,         0x08},
  {CC112X_SYNC_CFG0,         0x0B},
  {CC112X_DEVIATION_M,       0xD8},  //7.2 kHz outer Symbols
  {CC112X_MODCFG_DEV_E,      0x2B},
  {CC112X_DCFILT_CFG,        0x1C},
  {CC112X_IQIC,              0x00},
  {CC112X_CHAN_BW,           0x04}, 	//50kHz
  {CC112X_MDMCFG0,           0x05},
  {CC112X_SYMBOL_RATE2,      0x73},     //9.6ksps x 2 (thru 4GFSK)
  {CC112X_AGC_CFG1,          0xA9},
  {CC112X_AGC_CFG0,          0xCF},
  {CC112X_SETTLING_CFG,      0x03},
  {CC112X_FS_CFG,            0x1A},	//AUTOCAL enabled
  {CC112X_FIFO_CFG,          0x7C}, // TX FIFO Threshold = 124; RX FIFO = 4
  {CC112X_PKT_CFG2          ,0x04},
  {CC112X_PKT_CFG1          ,0x00},
  {CC112X_PKT_CFG0,          0x00},
  {CC112X_PA_CFG0,           0x7D},
  {CC112X_PKT_LEN,           0x15},  //21 Bytes
  {CC112X_IF_MIX_CFG,        0x00},
  {CC112X_FREQOFF_CFG,       0x32},
  {CC112X_CFM_DATA_CFG,      0x00},  //4-GFSK, Modulation as in EN13757-4
  {CC112X_FREQ2,             0x69},
  {CC112X_FREQ1,             0xE6}, //169,43750 MHz
  {CC112X_FS_DIG1,           0x00},
  {CC112X_FS_DIG0,           0x5F},
  {CC112X_FS_CAL1,           0x40},
  {CC112X_FS_CAL0,           0x0E},
  {CC112X_FS_DIVTWO,         0x03},
  {CC112X_FS_DSM0,           0x33},
  {CC112X_FS_DVC0,           0x17},
  {CC112X_FS_PFD,            0x50},
  {CC112X_FS_PRE,            0x6E},
  {CC112X_FS_REG_DIV_CML,    0x14},
  {CC112X_FS_SPARE,          0xAC},
  {CC112X_FS_VCO0,           0xB4},
  {CC112X_XOSC5,             0x0E},
  {CC112X_XOSC1,             0x03},
};


// Carrier frequency = 433.820007
// Manchester enable = false
// Device address = 0
// Bit rate = 2.4
// Performance mode = High Performance
// Address config = No address check
// Packet length mode = Variable
// Whitening = false
// Modulation format = 2-FSK
// TX power = 10
// Deviation = 5.493164
// RX filter BW = 40.000000
// Packet bit length = 0
// Symbol rate = 2.4
// Packet length = 255
// PA ramping = true
static const registerSetting_t WMbusCC112xRfSettingsFmode[]=
{
  {CC112X_IOCFG3,            0x01}, // RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
  	  	  	  	  	  	  	  	  	// FIFO_CFG.FIFO_THR or the end of packet is reached. De-asserted when the RX FIFO is empty
//  {CC112X_IOCFG2,            0x06},
  {CC112X_IOCFG0,            0x06},  //RX: Asserted when sync word has been received and de-asserted at the
  //end of the packet. Will de-assert when the optional address and/or length check fails or the RX FIFO overflows/underflows.
  // TX: Asserted when sync word has been sent, and de-asserted at the end of the packet. Will de-assert if the TX FIFO underflows/overflows
  {CC112X_SYNC3,             0x55},
  {CC112X_SYNC2,             0x55},
  {CC112X_SYNC1,             0xF6},
  {CC112X_SYNC0,             0x72},
  {CC112X_SYNC_CFG1,         0x0B},
  {CC112X_SYNC_CFG0,         0x17}, // 4 Bytes SYNC
  {CC112X_DEVIATION_M,       0x68}, //5.5kHz DEV
  {CC112X_DCFILT_CFG,        0x1C},
  {CC112X_IQIC,              0x46},
  {CC112X_CHAN_BW,           0x05},
  {CC112X_MDMCFG0,           0x05},
  {CC112X_SYMBOL_RATE2,      0x53}, //2.4kbps
  {CC112X_SYMBOL_RATE1,      0xA9}, //2.4kbps
  {CC112X_SYMBOL_RATE0,      0x2A}, //2.4kbps
  {CC112X_AGC_REF,           0x20},
  {CC112X_AGC_CS_THR,        0x19},
  {CC112X_AGC_CFG1,          0xA9},
  {CC112X_AGC_CFG0,          0xCF},
  {CC112X_FIFO_CFG,          0x7C}, // TX FIFO Threshold = 124; RX FIFO = 4
  {CC112X_PKT_CFG2          ,0x04},
  {CC112X_PKT_CFG1          ,0x00},
  {CC112X_PKT_CFG0          ,0x00},
  {CC112X_PKT_LEN           ,0x15}, // Packet handler config.In fixed length mode this field indicates the packet length, and a value of 0 indicates the length to be 256 bytes. In variable length packet mode, this value indicates the maximum allowed length packets.
  {CC112X_PREAMBLE_CFG1     ,0x2D}, //12Bytes preamble
  {CC112X_PREAMBLE_CFG0     ,0x2A},  //SYNC threshold
  {CC112X_PA_CFG2,           0x7F},	//+15 dBm
  {CC112X_PA_CFG1,           0x56},
  {CC112X_PA_CFG0,           0x7C}, //+15 dBm
  {CC112X_IF_MIX_CFG,        0x00},
  {CC112X_FREQOFF_CFG,       0x22},
  {CC112X_TOC_CFG           ,0x0B},
  {CC112X_FREQ2,             0x6C}, //433.8200 MHz
  {CC112X_FREQ1,             0x74}, //433.8200 MHz
  {CC112X_FREQ0,             0x7B}, //433.8200 MHz
  {CC112X_FS_CFG,            0x14}, //433.8200 MHz
  {CC112X_FS_DIG1,           0x00},
  {CC112X_FS_DIG0,           0x5F},
  {CC112X_FS_CAL1,           0x40},
  {CC112X_FS_CAL0,           0x0E},
  {CC112X_FS_DIVTWO,         0x03},
  {CC112X_FS_DSM0,           0x33},
  {CC112X_FS_DVC0,           0x17},
  {CC112X_FS_PFD,            0x50},
  {CC112X_FS_PRE,            0x6E},
  {CC112X_FS_REG_DIV_CML,    0x14},
  {CC112X_FS_SPARE,          0xAC},
  {CC112X_FS_VCO0,           0xB4},
  {CC112X_XOSC5,             0x0E},
  {CC112X_XOSC1,             0x03},
};


#ifdef  __cplusplus
}
#endif

#endif
