	TI_write_reg(CCxxx0_IOCFG2,0x29);  //GDO2 Output Pin Configuration
	TI_write_reg(CCxxx0_IOCFG1,0x2E);  //GDO1 Output Pin Configuration
	TI_write_reg(CCxxx0_IOCFG0,0x06);  //GDO0 Output Pin Configuration
	TI_write_reg(CCxxx0_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
	TI_write_reg(CCxxx0_SYNC1,0xD3);   //Sync Word, High Byte
	TI_write_reg(CCxxx0_SYNC0,0x91);   //Sync Word, Low Byte
	TI_write_reg(CCxxx0_PKTLEN,0xFF);  //Packet Length
	TI_write_reg(CCxxx0_PKTCTRL1,0x04);//Packet Automation Control
	TI_write_reg(CCxxx0_PKTCTRL0,0x01);//Packet Automation Control
	TI_write_reg(CCxxx0_ADDR,0x00);    //Device Address
	TI_write_reg(CCxxx0_CHANNR,0x00);  //Channel Number
	TI_write_reg(CCxxx0_FSCTRL1,0x06); //Frequency Synthesizer Control
	TI_write_reg(CCxxx0_FSCTRL0,0x00); //Frequency Synthesizer Control
	TI_write_reg(CCxxx0_FREQ2,0x10);   //Frequency Control Word, High Byte
	TI_write_reg(CCxxx0_FREQ1,0xB0);   //Frequency Control Word, Middle Byte
	TI_write_reg(CCxxx0_FREQ0,0x71);   //Frequency Control Word, Low Byte
	TI_write_reg(CCxxx0_MDMCFG4,0x19); //Modem Configuration
	TI_write_reg(CCxxx0_MDMCFG3,0x84); //Modem Configuration
	TI_write_reg(CCxxx0_MDMCFG2,0x0E); //Modem Configuration
	TI_write_reg(CCxxx0_MDMCFG1,0x22); //Modem Configuration
	TI_write_reg(CCxxx0_MDMCFG0,0xF8); //Modem Configuration
	TI_write_reg(CCxxx0_DEVIATN,0x45); //Modem Deviation Setting
	TI_write_reg(CCxxx0_MCSM2,0x07);   //Main Radio Control State Machine Configuration
	TI_write_reg(CCxxx0_MCSM1,0x30);   //Main Radio Control State Machine Configuration
	TI_write_reg(CCxxx0_MCSM0,0x18);   //Main Radio Control State Machine Configuration
	TI_write_reg(CCxxx0_FOCCFG,0x76);  //Frequency Offset Compensation Configuration
	TI_write_reg(CCxxx0_BSCFG,0x6D);   //Bit Synchronization Configuration
	TI_write_reg(CCxxx0_AGCCTRL2,0xC7);//AGC Control
	TI_write_reg(CCxxx0_AGCCTRL1,0x40);//AGC Control
	TI_write_reg(CCxxx0_AGCCTRL0,0x91);//AGC Control
	TI_write_reg(CCxxx0_WOREVT1,0x87); //High Byte Event0 Timeout
	TI_write_reg(CCxxx0_WOREVT0,0x6B); //Low Byte Event0 Timeout
	TI_write_reg(CCxxx0_WORCTRL,0xFB); //Wake On Radio Control
	TI_write_reg(CCxxx0_FREND1,0xB6);  //Front End RX Configuration
	TI_write_reg(CCxxx0_FREND0,0x10);  //Front End TX Configuration
	TI_write_reg(CCxxx0_FSCAL3,0xE9);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_FSCAL2,0x2A);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_FSCAL1,0x00);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_FSCAL0,0x1F);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_RCCTRL1,0x41); //RC Oscillator Configuration
	TI_write_reg(CCxxx0_RCCTRL0,0x00); //RC Oscillator Configuration
	TI_write_reg(CCxxx0_FSTEST,0x59);  //Frequency Synthesizer Calibration Control
	TI_write_reg(CCxxx0_PTEST,0x7F);   //Production Test
	TI_write_reg(CCxxx0_AGCTEST,0x3F); //AGC Test
	TI_write_reg(CCxxx0_TEST2,0x81);   //Various Test Settings
	TI_write_reg(CCxxx0_TEST1,0x35);   //Various Test Settings
	TI_write_reg(CCxxx0_IOCFG1,0x2E);  //GDO1 Output Pin Configuration
	TI_write_reg(CCxxx0_IOCFG0,0x06);  //GDO0 Output Pin Configuration
	TI_write_reg(CCxxx0_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
	TI_write_reg(CCxxx0_SYNC0,0x91);   //Sync Word, Low Byte
	TI_write_reg(CCxxx0_PKTCTRL1,0x04);//Packet Automation Control
	TI_write_reg(CCxxx0_PKTCTRL0,0x01);//Packet Automation Control
	TI_write_reg(CCxxx0_ADDR,0x00);    //Device Address
	TI_write_reg(CCxxx0_CHANNR,0x00);  //Channel Number
	TI_write_reg(CCxxx0_FSCTRL1,0x06); //Frequency Synthesizer Control
	TI_write_reg(CCxxx0_FSCTRL0,0x00); //Frequency Synthesizer Control
	TI_write_reg(CCxxx0_FREQ2,0x10);   //Frequency Control Word, High Byte
	TI_write_reg(CCxxx0_FREQ0,0x71);   //Frequency Control Word, Low Byte
	TI_write_reg(CCxxx0_MDMCFG4,0x19); //Modem Configuration
	TI_write_reg(CCxxx0_MDMCFG3,0x84); //Modem Configuration
	TI_write_reg(CCxxx0_MDMCFG1,0x22); //Modem Configuration
	TI_write_reg(CCxxx0_MDMCFG0,0xF8); //Modem Configuration
	TI_write_reg(CCxxx0_DEVIATN,0x45); //Modem Deviation Setting
	TI_write_reg(CCxxx0_MCSM2,0x07);   //Main Radio Control State Machine Configuration
	TI_write_reg(CCxxx0_MCSM1,0x30);   //Main Radio Control State Machine Configuration
	TI_write_reg(CCxxx0_MCSM0,0x18);   //Main Radio Control State Machine Configuration
	TI_write_reg(CCxxx0_FOCCFG,0x76);  //Frequency Offset Compensation Configuration
	TI_write_reg(CCxxx0_AGCCTRL1,0x40);//AGC Control
	TI_write_reg(CCxxx0_AGCCTRL0,0x91);//AGC Control
	TI_write_reg(CCxxx0_WOREVT1,0x87); //High Byte Event0 Timeout
	TI_write_reg(CCxxx0_WOREVT0,0x6B); //Low Byte Event0 Timeout
	TI_write_reg(CCxxx0_WORCTRL,0xFB); //Wake On Radio Control
	TI_write_reg(CCxxx0_FREND0,0x10);  //Front End TX Configuration
	TI_write_reg(CCxxx0_FSCAL3,0xE9);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_FSCAL2,0x2A);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_FSCAL1,0x00);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_FSCAL0,0x1F);  //Frequency Synthesizer Calibration
	TI_write_reg(CCxxx0_RCCTRL1,0x41); //RC Oscillator Configuration
	TI_write_reg(CCxxx0_RCCTRL0,0x00); //RC Oscillator Configuration
	TI_write_reg(CCxxx0_FSTEST,0x59);  //Frequency Synthesizer Calibration Control
	TI_write_reg(CCxxx0_PTEST,0x7F);   //Production Test
	TI_write_reg(CCxxx0_AGCTEST,0x3F); //AGC Test
	TI_write_reg(CCxxx0_TEST2,0x81);   //Various Test Settings
	TI_write_reg(CCxxx0_TEST1,0x35);   //Various Test Settings