/* * ======== ti_radio_config.c ======== * Configured RadioConfig module definitions * * DO NOT EDIT - This file is generated for the CC2755P105RHA * by the SysConfig tool. * * Tool Name: RadioConfig 8 * Tool Version: 9.11.00.02_ga * RF Settings Version: */ #include "ti_radio_config.h" #include DeviceFamily_constructPath(rf_patches/lrf_rfe_binary_ble5.h) #include DeviceFamily_constructPath(rf_patches/lrf_pbe_binary_ieee.h) #include DeviceFamily_constructPath(rf_patches/lrf_mce_binary_ieee_cohr.h) #include DeviceFamily_constructPath(rf_patches/lrf_rfe_binary_ieee.h) // **************************************************************** // PHY name: ADC Noise // PHY abbreviation/ID: adc_noise // PHY definition file: adc_noise_bt5_cc27xx.json // **************************************************************** // Configuration: Common static const uint32_t LRF_commonRegConfigAdcNoise[] = { 0x0000002E, // Segment length = 46 0x0000A003, // Data structure 32-bit region (start byte position = 0, count = 4) (uint32_t) &LRF_swConfigAdcNoise,// LRF_swParam : swConfig 0x00000000, // LRF_swParam : txPowerLimitTable 0x00000000, // LRF_swParam : txPowerTable (uint32_t) &(fcfg->appTrims), // LRF_swParam : trimDef 0x00003003, // HW sparse region (address/value pairs, count = 4) 0x30840000, // LRFDRFE.MAGNTHRCFG 0x308C0000, // LRFDRFE.RSSIOFFSET 0x3120D820, // LRFDRFE.MISC0 0x31300C07, // LRFDRFE.PHEDISC 0x30A41002, // HW 16-bit region (start address = 0x30A4, count = 3) 0x1F40A246, // LRFDRFE.SPARE3 LRFDRFE.SPARE2 0x00000000, // - LRFDRFE.SPARE4 0x30B41002, // HW 16-bit region (start address = 0x30B4, count = 3) 0x00060006, // LRFDRFE.IFAMPRFLDO LRFDRFE.LNA 0x00002940, // - LRFDRFE.PA0 0x30C40005, // HW zero region (start address = 0x30C4, count = 6) 0x30E4100C, // HW 16-bit region (start address = 0x30E4, count = 13) 0x00000200, // LRFDRFE.DCO LRFDRFE.ATSTREFH 0x00000008, // LRFDRFE.DIVLDO LRFDRFE.DIV 0x00000000, // LRFDRFE.DCOLDO0 LRFDRFE.TDCLDO 0x07060000, // LRFDRFE.PRE0 LRFDRFE.DCOLDO1 0x06050000, // LRFDRFE.PRE2 LRFDRFE.PRE1 0x40080603, // LRFDRFE.CAL0 LRFDRFE.PRE3 0x00007F00, // - LRFDRFE.CAL1 0x31381002, // HW 16-bit region (start address = 0x3138, count = 3) 0x047FDF7F, // LRFDRFE.PLLMON1 LRFDRFE.PLLMON0 0x00001804, // - LRFDRFE.MOD0 0x68046005, // RAM 32-bit region (start address = 0x6804, count = 6) 0x03000012, // RFE_COMMON_RAM.TDCCAL0 RFE_COMMON_RAM.SYNTHCTL 0x00100000, // RFE_COMMON_RAM.TDCCAL2 RFE_COMMON_RAM.TDCCAL1 0x569B0400, // RFE_COMMON_RAM.K1LSB RFE_COMMON_RAM.TDCPLL 0x012D010A, // RFE_COMMON_RAM.K2BL RFE_COMMON_RAM.K1MSB 0x132C0034, // RFE_COMMON_RAM.K3BL RFE_COMMON_RAM.K2AL 0x916F07AB, // RFE_COMMON_RAM.K5 RFE_COMMON_RAM.K3AL 0x68204001, // RAM zero region (start address = 0x16820, count = 2) 0x68286004, // RAM 32-bit region (start address = 0x6828, count = 5) 0x48080008, // RFE_COMMON_RAM.DIVF RFE_COMMON_RAM.DIVI 0x00000000, // RFE_COMMON_RAM.DIVLDOF RFE_COMMON_RAM.DIVLDOI 0x00470014, // RFE_COMMON_RAM.LDOSETTLE RFE_COMMON_RAM.DIVLDOIOFF 0x0005002E, // RFE_COMMON_RAM.DCOSETTLE RFE_COMMON_RAM.CHRGSETTLE 0x0000FE00, // RFE_COMMON_RAM.IFAMPRFLDODEFAULT RFE_COMMON_RAM.IFAMPRFLDOTX 0x68446001, // RAM 32-bit region (start address = 0x6844, count = 2) 0x00220051, // RFE_COMMON_RAM.SPARE0SHADOW RFE_COMMON_RAM.PHYRSSIOFFSET 0x00000045, // RFE_COMMON_RAM.AGCINFO RFE_COMMON_RAM.SPARE1SHADOW 0x684E4001 // RAM zero region (start address = 0x1684E, count = 2) }; // LRF register configuration list static const LRF_RegConfigList LRF_regConfigListAdcNoise = { .numEntries = 1, .entries = { (LRF_ConfigWord*)LRF_commonRegConfigAdcNoise } }; // LRF_SwConfig data structure const LRF_SwConfig LRF_swConfigAdcNoise = { .rxIntFrequency = 0, .rxFrequencyOffset = 0, .txFrequencyOffset = 0, .modFrequencyDeviation = 0x00000000, .txShape = (LRF_TxShape*) 0, .bwIndex = 0x01, .bwIndexDither = 0x01 }; // LRF_Config data structure const LRF_Config LRF_configAdcNoise = { .pbeImage = (LRF_TOPsmImage*) 0, .mceImage = (LRF_TOPsmImage*) 0, .rfeImage = (const LRF_TOPsmImage*) LRF_RFE_binary_ble5, .regConfigList = &LRF_regConfigListAdcNoise }; // **************************************************************** // PHY name: 250 kbps, O-QPSK // PHY abbreviation/ID: ieee_802_15_4 // PHY definition file: ieee_802_15_4_oqpsk_250k_cc27xx.json // **************************************************************** // PARAMETER SUMMARY // Channel - Frequency (MHz): 2405 // TX Power (dBm): 14 // Configuration: Common static const uint32_t LRF_commonRegConfigIeee802154[] = { 0x0000005E, // Segment length = 94 0x0000A003, // Data structure 32-bit region (start byte position = 0, count = 4) (uint32_t) &LRF_swConfig_ieee_802_15_4_t,// LRF_swParam : swConfig (uint32_t) &LRF_txPowerLimitTable_ieee_802_15_4_t,// LRF_swParam : txPowerLimitTable (uint32_t) &LRF_txPowerTable, // LRF_swParam : txPowerTable (uint32_t) &(fcfg->appTrims), // LRF_swParam : trimDef 0x14402000, // HW 32-bit region (start address = 0x1440, count = 1) 0x000000A7, // LRFDPBE.MDMSYNCAH LRFDPBE.MDMSYNCAL 0x10A00002, // HW zero region (start address = 0x10A0, count = 3) 0x10AC1006, // HW 16-bit region (start address = 0x10AC, count = 7) 0x00001021, // LRFDPBE.PHACFG LRFDPBE.POLY1H 0x01090033, // LRFDPBE.FCFG1 LRFDPBE.FCFG0 0x00C10028, // LRFDPBE.FCFG3 LRFDPBE.FCFG2 0x00000048, // - LRFDPBE.FCFG4 0x14682000, // HW 32-bit region (start address = 0x1468, count = 1) 0x00020004, // LRFDPBE.TXFWBTHRS LRFDPBE.RXFRBTHRS 0x10DC1001, // HW 16-bit region (start address = 0x10DC, count = 2) 0x0B0B0202, // LRFDPBE.TIMPRE LRFDPBE.TIMCTL 0x11141002, // HW 16-bit region (start address = 0x1114, count = 3) 0x00070007, // LRFDPBE.MDMFRDCTL LRFDPBE.MDMFWRCTL 0x00000707, // - LRFDPBE.MDMFCFG 0x00003007, // HW sparse region (address/value pairs, count = 8) 0x114C0007, // LRFDPBE.LFSR0N 0x206800A7, // LRFDMDM.CMDPAR2 0x22A00001, // LRFDMDM.BAUDCOMP 0x23248004, // LRFDMDM.DEMC1BE10 0x232C3200, // LRFDMDM.DEMC1BE12 0x308C0000, // LRFDRFE.RSSIOFFSET 0x3120D820, // LRFDRFE.MISC0 0x31300C07, // LRFDRFE.PHEDISC 0x20C01002, // HW 16-bit region (start address = 0x20C0, count = 3) 0x00000003, // LRFDMDM.MODPRECTRL LRFDMDM.ADCDIGCONF 0x0000001F, // - LRFDMDM.MODSYMMAP0 0x20D41002, // HW 16-bit region (start address = 0x20D4, count = 3) 0x00064000, // LRFDMDM.BAUDPRE LRFDMDM.BAUD 0x00000004, // - LRFDMDM.MODMAIN 0x20E41003, // HW 16-bit region (start address = 0x20E4, count = 4) 0x000B0011, // LRFDMDM.DEMMISC2 LRFDMDM.DEMMISC1 0x00001081, // LRFDMDM.DEMIQMC0 LRFDMDM.DEMMISC3 0x20FC100B, // HW 16-bit region (start address = 0x20FC, count = 12) 0x002C0FB0, // LRFDMDM.DEMFIDC0 LRFDMDM.DEMCODC0 0x0B600104, // LRFDMDM.DEMFIFE0 LRFDMDM.DEMFEXB0 0x40100000, // LRFDMDM.DEMMAFI1 LRFDMDM.DEMMAFI0 0x001C0040, // LRFDMDM.DEMC1BE0 LRFDMDM.DEMMAFI2 0x041E201E, // LRFDMDM.DEMC1BE2 LRFDMDM.DEMC1BE1 0x0014192C, // LRFDMDM.SPARE1 LRFDMDM.SPARE0 0x24D42000, // HW 32-bit region (start address = 0x24D4, count = 1) 0x00540005, // LRFDMDM.DEMD2XB0 LRFDMDM.DEMDSXB0 0x22781002, // HW 16-bit region (start address = 0x2278, count = 3) 0x40200209, // LRFDMDM.DEMCOHR1 LRFDMDM.DEMCOHR0 0x0000001F, // - LRFDMDM.DEMCOHR2 0x344C2000, // HW 32-bit region (start address = 0x344C, count = 1) 0x1242151F, // LRFDRFE.SPARE0 LRFDRFE.MAGNCTL1 0x30A41002, // HW 16-bit region (start address = 0x30A4, count = 3) 0x00003F13, // LRFDRFE.SPARE3 LRFDRFE.SPARE2 0x00000000, // - LRFDRFE.SPARE4 0x30B41002, // HW 16-bit region (start address = 0x30B4, count = 3) 0x00060006, // LRFDRFE.IFAMPRFLDO LRFDRFE.LNA 0x00002940, // - LRFDRFE.PA0 0x30C40005, // HW zero region (start address = 0x30C4, count = 6) 0x30E4100C, // HW 16-bit region (start address = 0x30E4, count = 13) 0x00000200, // LRFDRFE.DCO LRFDRFE.ATSTREFH 0x00000008, // LRFDRFE.DIVLDO LRFDRFE.DIV 0x00000000, // LRFDRFE.DCOLDO0 LRFDRFE.TDCLDO 0x07060000, // LRFDRFE.PRE0 LRFDRFE.DCOLDO1 0x06050000, // LRFDRFE.PRE2 LRFDRFE.PRE1 0x40080603, // LRFDRFE.CAL0 LRFDRFE.PRE3 0x00007F00, // - LRFDRFE.CAL1 0x31381002, // HW 16-bit region (start address = 0x3138, count = 3) 0x047FDF7F, // LRFDRFE.PLLMON1 LRFDRFE.PLLMON0 0x00001B00, // - LRFDRFE.MOD0 0x20205006, // RAM 16-bit region (start address = 0x2020, count = 7) 0xD18000B4, // PBE_IEEE_RAM.FIFOCFG PBE_IEEE_RAM.SYNTHCALTIMEOUT 0x03000006, // PBE_IEEE_RAM.PRETXIFS PBE_IEEE_RAM.EXTRABYTES 0x030002D8, // PBE_IEEE_RAM.PRETXIFSV2 PBE_IEEE_RAM.PRERXIFS 0x00000064, // - PBE_IEEE_RAM.PILOTLEN 0x68046005, // RAM 32-bit region (start address = 0x6804, count = 6) 0x03000012, // RFE_COMMON_RAM.TDCCAL0 RFE_COMMON_RAM.SYNTHCTL 0x00100000, // RFE_COMMON_RAM.TDCCAL2 RFE_COMMON_RAM.TDCCAL1 0x569B0400, // RFE_COMMON_RAM.K1LSB RFE_COMMON_RAM.TDCPLL 0x012D010A, // RFE_COMMON_RAM.K2BL RFE_COMMON_RAM.K1MSB 0x132C0034, // RFE_COMMON_RAM.K3BL RFE_COMMON_RAM.K2AL 0x916F07AB, // RFE_COMMON_RAM.K5 RFE_COMMON_RAM.K3AL 0x68204001, // RAM zero region (start address = 0x16820, count = 2) 0x68286004, // RAM 32-bit region (start address = 0x6828, count = 5) 0x48080008, // RFE_COMMON_RAM.DIVF RFE_COMMON_RAM.DIVI 0x00000000, // RFE_COMMON_RAM.DIVLDOF RFE_COMMON_RAM.DIVLDOI 0x00470014, // RFE_COMMON_RAM.LDOSETTLE RFE_COMMON_RAM.DIVLDOIOFF 0x0005002E, // RFE_COMMON_RAM.DCOSETTLE RFE_COMMON_RAM.CHRGSETTLE 0x0000FE00, // RFE_COMMON_RAM.IFAMPRFLDODEFAULT RFE_COMMON_RAM.IFAMPRFLDOTX 0x00007000, // RAM sparse region (address/value pairs, count = 1) 0x6844003D, // RFE_COMMON_RAM.PHYRSSIOFFSET 0x68486000, // RAM 32-bit region (start address = 0x6848, count = 1) 0x00010028, // RFE_COMMON_RAM.AGCINFO RFE_COMMON_RAM.SPARE1SHADOW 0x684E4001 // RAM zero region (start address = 0x1684E, count = 2) }; // LRF register configuration list static const LRF_RegConfigList LRF_regConfigList_ieee_802_15_4_t = { .numEntries = 1, .entries = { (LRF_ConfigWord*)LRF_commonRegConfigIeee802154 } }; // LRF_SwConfig data structure const LRF_SwConfig LRF_swConfig_ieee_802_15_4_t = { .rxIntFrequency = 0, .rxFrequencyOffset = 0, .txFrequencyOffset = 0, .modFrequencyDeviation = 0x0001E848, .txShape = (LRF_TxShape*) 0, .bwIndex = 0x00, .bwIndexDither = 0x01 }; // LRF_TxPowerTable data structure const LRF_TxPowerTable LRF_txPowerTable = { .numEntries = 0x0000001A, .powerTable = { { .power = { .fraction = 0, .dBm = -20 }, .tempCoeff = 0, .value = { .ibBoost = 0, .ib = 18, .gain = 0, .mode = 0, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = -16 }, .tempCoeff = 3, .value = { .ibBoost = 0, .ib = 26, .gain = 0, .mode = 0, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = -12 }, .tempCoeff = 8, .value = { .ibBoost = 0, .ib = 30, .gain = 1, .mode = 0, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = -8 }, .tempCoeff = 13, .value = { .ibBoost = 0, .ib = 27, .gain = 3, .mode = 0, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = -4 }, .tempCoeff = 35, .value = { .ibBoost = 0, .ib = 46, .gain = 3, .mode = 0, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 0 }, .tempCoeff = 30, .value = { .ibBoost = 0, .ib = 37, .gain = 4, .mode = 1, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 1 }, .tempCoeff = 35, .value = { .ibBoost = 0, .ib = 43, .gain = 4, .mode = 1, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 2 }, .tempCoeff = 35, .value = { .ibBoost = 0, .ib = 35, .gain = 5, .mode = 1, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 3 }, .tempCoeff = 45, .value = { .ibBoost = 0, .ib = 43, .gain = 5, .mode = 1, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 4 }, .tempCoeff = 50, .value = { .ibBoost = 0, .ib = 33, .gain = 6, .mode = 1, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 5 }, .tempCoeff = 10, .value = { .ibBoost = 0, .ib = 54, .gain = 3, .mode = 2, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 6 }, .tempCoeff = 6, .value = { .ibBoost = 1, .ib = 29, .gain = 3, .mode = 2, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 7 }, .tempCoeff = 5, .value = { .ibBoost = 1, .ib = 34, .gain = 3, .mode = 2, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 8 }, .tempCoeff = 8, .value = { .ibBoost = 1, .ib = 41, .gain = 3, .mode = 2, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 9 }, .tempCoeff = 20, .value = { .ibBoost = 1, .ib = 34, .gain = 4, .mode = 2, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 10 }, .tempCoeff = 30, .value = { .ibBoost = 1, .ib = 45, .gain = 4, .mode = 2, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 11 }, .tempCoeff = 65, .value = { .ibBoost = 1, .ib = 47, .gain = 5, .mode = 2, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 12 }, .tempCoeff = 15, .value = { .ibBoost = 1, .ib = 44, .gain = 3, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 13 }, .tempCoeff = 18, .value = { .ibBoost = 1, .ib = 49, .gain = 3, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 14 }, .tempCoeff = 25, .value = { .ibBoost = 1, .ib = 40, .gain = 4, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 15 }, .tempCoeff = 20, .value = { .ibBoost = 2, .ib = 48, .gain = 3, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 16 }, .tempCoeff = 40, .value = { .ibBoost = 1, .ib = 40, .gain = 5, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 17 }, .tempCoeff = 36, .value = { .ibBoost = 3, .ib = 39, .gain = 4, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 18 }, .tempCoeff = 40, .value = { .ibBoost = 3, .ib = 40, .gain = 5, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 19 }, .tempCoeff = 80, .value = { .ibBoost = 2, .ib = 49, .gain = 6, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } }, { .power = { .fraction = 0, .dBm = 20 }, .tempCoeff = 140, .value = { .ibBoost = 3, .ib = 47, .gain = 7, .mode = 3, .rtrimTxCompCtl = 0, .pa20dBmEsdCtl = 0, .noIfampRfLdoBypass = 0 } } } }; // LRF_TxPowerLimitTable data structure const LRF_TxPowerLimitTable LRF_txPowerLimitTable_ieee_802_15_4_t = { .numEntries = 0x00000003, .freqDiv = 0x0007A120, .limitTable = { { .minFreq = 4945, .maxFreq = 4955, .regulatoryMask = 0x02, .maxTxPower = { .fraction = 0, .dBm = 19 } }, { .minFreq = 4955, .maxFreq = 4965, .regulatoryMask = 0x01, .maxTxPower = { .fraction = 0, .dBm = 16 } }, { .minFreq = 4955, .maxFreq = 4965, .regulatoryMask = 0x02, .maxTxPower = { .fraction = 0, .dBm = 6 } } } }; // LRF_Config data structure const LRF_Config LRF_config_ieee_802_15_4_t = { .pbeImage = (const LRF_TOPsmImage*) LRF_PBE_binary_ieee, .mceImage = (const LRF_TOPsmImage*) LRF_MCE_binary_ieee_cohr, .rfeImage = (const LRF_TOPsmImage*) LRF_RFE_binary_ieee, .regConfigList = &LRF_regConfigList_ieee_802_15_4_t };