FILE COMPARISON
Produced: 2/13/2020 2:28:39 PM
   
Mode:  Differences with Context  
   
Left file: C:\ti\msp\UltrasonicGasFR6043_02_30_00_01\lib\USS\source\USS_HAL\USS_Lib_HAL.h  
Right file: C:\ti\msp\UltrasonicGasFR6043_02_30_00_01_golden\lib\USS\source\USS_HAL\USS_Lib_HAL.h  
109 * External Circuitry Control signals = 109 * External Circuitry Control signals
110 ******************************************************************************/   110 ******************************************************************************/
111 #define USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS                    (TIMER_A0_BASE)   111 #define USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS                    (TIMER_A0_BASE)
112     112  
113 #if(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS == TIMER_A0_BASE)   113 #if(USSSWLIB_HAL_RXEN_TIMER_BASE_ADDRESS == TIMER_A0_BASE)
114 // Defines for RxEn control lines   114 // Defines for RxEn control lines
115 // RxEn -> P6.0 <> 115 // RxEn -> P6.7
116 #define USSSWLIB_HAL_AFE_RXEN_PORT                                  P6OUT = 116 #define USSSWLIB_HAL_AFE_RXEN_PORT                                  P6OUT
117 #define USSSWLIB_HAL_AFE_RXEN_PORT_DIR                              P6DIR   117 #define USSSWLIB_HAL_AFE_RXEN_PORT_DIR                              P6DIR
118  #define USSSWLIB_HAL_AFE_RXEN_PIN                                    BIT0 <> 118  #define USSSWLIB_HAL_AFE_RXEN_PIN                                    BIT7
119 #else = 119 #else
120 #error "Define RxEn GPIO configurations"   120 #error "Define RxEn GPIO configurations"
121 // Defines for RxEn control lines   121 // Defines for RxEn control lines
122 // RxEn -> Px.y   122 // RxEn -> Px.y
123 #define USSSWLIB_HAL_AFE_RXEN_PORT                                  PxOUT   123 #define USSSWLIB_HAL_AFE_RXEN_PORT                                  PxOUT
124 #define USSSWLIB_HAL_AFE_RXEN_PORT_DIR                              PxDIR   124 #define USSSWLIB_HAL_AFE_RXEN_PORT_DIR                              PxDIR
125 #define USSSWLIB_HAL_AFE_RXEN_PORT_SEL0                             PxSEL0   125 #define USSSWLIB_HAL_AFE_RXEN_PORT_SEL0                             PxSEL0
126 #define USSSWLIB_HAL_AFE_RXEN_PORT_SEL1                             PxSEL1   126 #define USSSWLIB_HAL_AFE_RXEN_PORT_SEL1                             PxSEL1
127 #define USSSWLIB_HAL_AFE_RXEN_PIN                                    BITy   127 #define USSSWLIB_HAL_AFE_RXEN_PIN                                    BITy
128 #endif   128 #endif
129     129  
130 // Defines for RxSel1 and RxSel2 control lines   130 // Defines for RxSel1 and RxSel2 control lines
131 // RxSel1 -> P6.4 <> 131 // RxSel1 -> P3.6
132 // RxSel2 -> P6.5   132 // RxSel2 -> P3.7
133  #define USSSWLIB_HAL_AFE_RX_SELx_PORT                              P6OUT   133  #define USSSWLIB_HAL_AFE_RX_SELx_PORT                              P3OUT
134  #define USSSWLIB_HAL_AFE_RX_SELx_PORT_DIR                          P6DIR   134  #define USSSWLIB_HAL_AFE_RX_SELx_PORT_DIR                          P3DIR
135  #define USSSWLIB_HAL_AFE_RX_SEL1_PIN                               BIT4   135  #define USSSWLIB_HAL_AFE_RX_SEL1_PIN                               BIT6
136  #define USSSWLIB_HAL_AFE_RX_SEL2_PIN                               BIT5   136  #define USSSWLIB_HAL_AFE_RX_SEL2_PIN                               BIT7
137   = 137  
138 // Defines for RxPwr control lines   138 // Defines for RxPwr control lines
139 // RxPwr -> P2.2   139 // RxPwr -> P2.2
140 #define USSSWLIB_HAL_AFE_RXPWR_PORT                                  P2OUT   140 #define USSSWLIB_HAL_AFE_RXPWR_PORT                                  P2OUT
141 #define USSSWLIB_HAL_AFE_RXPWR_PORT_DIR                              P2DIR   141 #define USSSWLIB_HAL_AFE_RXPWR_PORT_DIR                              P2DIR
142 #define USSSWLIB_HAL_AFE_RXPWR_PIN                                   BIT2   142 #define USSSWLIB_HAL_AFE_RXPWR_PIN                                   BIT2