void platform_first_power_up(void) //First Function to call
{
    /* boot-loader problem workaround: TX pin is set to input state */
    P3DIR &= ~BIT0;
    POWER_DOWN_PIN_INIT;
    /* supply voltage supervisor */
    PMMCTL0_H = PMMPW_H;                /* Open PMM registers for write access */
    SVSMHCTL = SVSHE | SVSHRVL_3 | SVSMHRRL_5;  /* Set SVS/SVM high side level (Vcc) */
    SVSMLCTL = SVSLE | SVMLE | SVSMLRRL_0;      /* Set SVM low side level(core voltage) */
    PMMRIE = SVSHPE;
    UCSCTL6 = XT2OFF;                   /* XT1 On */
    PMMCTL0_H = 0;

    WATCHDOG_CLEAR_COUNT;
    usleep(10000);

    while(POWER_DOWN_PIN_TEST)
        {
        WATCHDOG_CLEAR_COUNT;
        __delay_cycles(1000);
        }

    WATCHDOG_CLEAR_COUNT;
    platform_init();
}

/* *****************************************************************************
*
* *************************************************************************** */
void platform_init(void) //Second Function to call
{

    platform_power_down = false;

    WATCHDOG_CLEAR_COUNT;

    /* platform initialization */
    UCSCTL6 = XT2OFF;                       /* XT1 On */

    /* Loop until XT1 fault flag is cleared */
    do
    {
        UCSCTL7 &= ~XT1LFOFFG;
        WATCHDOG_CLEAR_COUNT;
    } while (UCSCTL7 & XT1LFOFFG);

    /* Core voltage setting */
    platform_set_core_voltage(1);
    platform_set_core_voltage(2);
    platform_set_core_voltage(3);
    __delay_cycles(76563);

    /* Initialize DCO to 23.986176 MHz */
    __bis_SR_register(SCG0);
    UCSCTL0 = 0x0000;
    UCSCTL1 = DCORSEL_6;
    UCSCTL2 = FLLD_0 | 731;               /* (731 + 1) * 32768 = 23.986176 MHz */
    UCSCTL5 = DIVPA_3 | DIVA_0 | DIVS_1;  /* ACLK = 32.768 kHz, SMCLK = 11.993088 MHz */
    __bic_SR_register(SCG0);
    __delay_cycles(76563);

    /* Loop until XT1, XT2 & DCO fault flag is cleared */
    do
    {
        UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);
        SFRIFG1 &= ~OFIFG;
        WATCHDOG_CLEAR_COUNT;
    } while (SFRIFG1 & OFIFG);

    PMMCTL0_H = 0;

}

void platform_set_core_voltage (uint8_t level) //Third Function to call
{
    /* Open PMM registers for write access */
    PMMCTL0_H = PMMPW_H;

    /* Make sure no flags are set for iterative sequences */
    while ((PMMIFG & SVSMHDLYIFG) == 0) {};
    while ((PMMIFG & SVSMLDLYIFG) == 0) {};

    /* Set SVS/SVM high side new level */
    SVSMHCTL = SVSHE |SVSHRVL_3 | SVMHE | SVSMHRRL_5;

    /* Set SVM low side to new level */
    SVSMLCTL = SVSLE | SVMLE | (SVSMLRRL0 * level);

    /* Wait till SVM is settled */
    while ((PMMIFG & SVSMLDLYIFG) == 0) {};

    /* Clear already set flags */
    PMMIFG &= ~(SVMLVLRIFG | SVMLIFG);

    /* Set VCore to new level */
    PMMCTL0_L = (PMMCOREV0 * level);

    /* Wait till new level reached */
    if ((PMMIFG & SVMLIFG))
    {
        while ((PMMIFG & SVMLVLRIFG) == 0) {};
    }

    /* Set SVS/SVM low side to new level */
    SVSMLCTL = SVSLE | (SVSLRVL0 * level) | SVMLE | (SVSMLRRL0 * level);

    /* Lock PMM registers for write access */
    PMMCTL0_H = 0x00;
}