EFunctions with [@@@] are unused functions
EThe following content is a copy of the SFR when it was put into the LPM

Core Registers		Core Registers	
	PC	0x0114DC	Core	
	SP	0x002B1C	Core	
	SR	0x00D0	Core	
	R3	0x000000	Core	
	R4	0x00FFFF	Core	
	R5	0x00FFFF	Core	
	R6	0x00FFFF	Core	
	R7	0x00A55A	Core	
	R8	0x00FFFF	Core	
	R9	0x000112	Core	
	R10	0x000000	Core	
	R11	0x00FFFF	Core	
	R12	0x00015C	Core	
	R13	0x000000	Core	
	R14	0x000000	Core	
	R15	0x005AA4	Core	

ADC12_B			
Comment: Used to measure battery voltage. Halting when entering LPM3
	ADC12CTL0	0x0000	ADC12_B Control 0 [Memory Mapped]	
	ADC12CTL1	0x0000	ADC12_B Control 1 [Memory Mapped]	
	ADC12CTL2	0x0000	ADC12_B Control 2 [Memory Mapped]	
	ADC12CTL3	0x0000	ADC12_B Control 3 [Memory Mapped]	
	ADC12LO	0x0000	ADC12_B Window Comparator Low Threshold Register [Memory Mapped]	
	ADC12HI	0x0FFF	ADC12_B Window Comparator High Threshold Register [Memory Mapped]	
	ADC12IFGR0	0x0000	ADC12_B Interrupt Flag 0 [Memory Mapped]	
	ADC12IFGR1	0x0000	ADC12_B Interrupt Flag 1 [Memory Mapped]	
	ADC12IFGR2	0x0000	ADC12_B Interrupt Flag 2 [Memory Mapped]	
	ADC12IER0	0x0000	ADC12_B Interrupt Enable 0 [Memory Mapped]	
	ADC12IER1	0x0000	ADC12_B Interrupt Enable 1 [Memory Mapped]	
	ADC12IER2	0x0000	ADC12_B Interrupt Enable 2 [Memory Mapped]	
	ADC12IV	0x0000	ADC12_B Interrupt Vector [Memory Mapped]	
	ADC12MCTL0	0x011F	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL1	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL2	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL3	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL4	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL5	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL6	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL7	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL8	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL9	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL10	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL11	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL12	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL13	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL14	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL15	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL16	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL17	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL18	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL19	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL20	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL21	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL22	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL23	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL24	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL25	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL26	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL27	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL28	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL29	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL30	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MCTL31	0x0000	ADC12_B Memory Control 0 Register to ADC12_B Memory Control 31 Register [Memory Mapped]	
	ADC12MEM0	0x0B75	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM1	0x0404	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM2	0x0268	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM3	0x0220	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM4	0x0057	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM5	0x0820	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM6	0x031D	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM7	0x03B4	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM8	0x010C	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM9	0x0065	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM10	0x0141	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM11	0x04B4	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM12	0x001B	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM13	0x004C	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM14	0x0089	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM15	0x0C25	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM16	0x0005	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM17	0x0E31	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM18	0x0200	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM19	0x0100	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM20	0x0605	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM21	0x0819	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM22	0x0200	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM23	0x0D00	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM24	0x000D	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM25	0x0002	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM26	0x0011	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM27	0x0EC6	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM28	0x0141	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM29	0x0549	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM30	0x09A2	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	
	ADC12MEM31	0x0F85	ADC12_B Memory 0 Register to ADC12_B Memory 31 Register [Memory Mapped]	

AES256@@@		
	AESACTL0	0x0000	AES Accelerator Control Register 0 [Memory Mapped]	
	AESACTL1	0x0000	AES Accelerator Control Register 1 [Memory Mapped]	
	AESASTAT	0x0000	AES Accelerator Status Register [Memory Mapped]	
	AESAKEY	0x0000	AES Accelerator Key Register [Memory Mapped]	
	AESADIN	0x0000	AES Accelerator Data In Register [Memory Mapped]	
	AESADOUT	0x0000	AES Accelerator Data Out Register [Memory Mapped]	
	AESAXDIN	0x0000	AES Accelerator XORed Data In Register [Memory Mapped]	
	AESAXIN	0x0000	AES Accelerator XORed Data In Register [Memory Mapped]	
CAPTIO0@@@			
	CAPTIO0CTL	0x0000	Capacitive Touch IO 0 Control Register [Memory Mapped]	
CAPTIO1@@@			
	CAPTIO1CTL	0x0000	Capacitive Touch IO 0 Control Register [Memory Mapped]	
COMP_E@@@			
	CECTL0	0x0000	Comparator Control Register 0 [Memory Mapped]	
	CECTL1	0x0000	Comparator Control Register 1 [Memory Mapped]	
	CECTL2	0x0000	Comparator Control Register 2 [Memory Mapped]	
	CECTL3	0x0000	Comparator Control Register 3 [Memory Mapped]	
	CEINT	0x0000	Comparator Interrupt Control Register [Memory Mapped]	
	CEIV	0x0000	Comparator Interrupt Vector Word Register [Memory Mapped]	
CRC	
Comment: Used as parameter checksum	
	CRCDI	0x00FF	CRC Data In [Memory Mapped]	
	CRCDIRB	0x00FF	CRC Data In Reverse Byte [Memory Mapped]	
	CRCINIRES	0xF322	CRC Initialization and Result [Memory Mapped]	
	CRCRESR	0x44CF	CRC Result Reverse [Memory Mapped]	
CRC32@@@			
	CRC32DIW0	0x0000	CRC32 Data Input Word 0 [Memory Mapped]	
	CRC32DIW1	0x0000	CRC32 Data Input Word 1 [Memory Mapped]	
	CRC32DIRBW1	0x0000	CRC32 Data In Reverse Word 1 [Memory Mapped]	
	CRC32DIRBW0	0x0000	CRC32 Data In Reverse Word 0 [Memory Mapped]	
	CRC32INIRESW0	0xFFFF	CRC32 Initialization and Result Word 0 [Memory Mapped]	
	CRC32INIRESW1	0xFFFF	CRC32 Initialization and Result Word 1 [Memory Mapped]	
	CRC32RESRW1	0xFFFF	CRC32 Result Reverse Word 1 [Memory Mapped]	
	CRC32RESRW0	0xFFFF	CRC32 Result Reverse Word 0 [Memory Mapped]	
	CRC16DIW0	0x0000	CRC16 Data Input [Memory Mapped]	
	CRC16DIRBW0	0x0000	CRC16 Data In Reverse [Memory Mapped]	
	CRC16INIRESW0	0xFFFF	CRC16 Init and Result [Memory Mapped]	
	CRC16RESRW0	0xFFFF	CRC16 Result Reverse [Memory Mapped]	
CS
Comment: I am using it as MCLK8Mhz, SMCLK1MHz, ACLK32.768Khz (LFXT).
All clk switches to LFXT when entering LPM.
	CSCTL0	0x9600	Clock System Control 0 [Memory Mapped]	
	CSCTL1	0x000C	Clock System Control 1 [Memory Mapped]	
	CSCTL2	0x0000	Clock System Control 2 [Memory Mapped]	
	CSCTL3	0x0000	Clock System Control 3 [Memory Mapped]	
	CSCTL4	0xCDC8	Clock System Control 4 [Memory Mapped]	
	CSCTL5	0x00C0	Clock System Control 5 [Memory Mapped]	
	CSCTL6	0x0007	Clock System Control 6 [Memory Mapped]	
PA@@@
Comment: Please check except the port control system.
P1
	P1IV	0x0000	Port 1 Interrupt Vector Register [Memory Mapped]	
	P1IN	0x10	Port 1 Input [Memory Mapped]	
	P1OUT	0x10	Port 1 Output [Memory Mapped]	
	P1DIR	0x7F	Port 1 Direction [Memory Mapped]	
	P1REN	0x80	Port 1 Resistor Enable [Memory Mapped]	
	P1SEL0	0x00	Port 1 Select 0 [Memory Mapped]	
	P1SEL1	0x00	Port 1 Select 1 [Memory Mapped]	
	P1SELC	0x00	Port 1 Complement Select [Memory Mapped]	
	P1IES	0x00	Port 1 Interrupt Edge Select [Memory Mapped]	
	P1IE	0x00	Port 1 Interrupt Enable [Memory Mapped]	
	P1IFG	0xF0	Port 1 Interrupt Flag [Memory Mapped]	
P2
	P2IV	0x0000	Port 2 Interrupt Vector Register [Memory Mapped]	
	P2IN	0x03	Port 2 Input [Memory Mapped]	
	P2OUT	0x01	Port 2 Output [Memory Mapped]	
	P2DIR	0x05	Port 2 Direction [Memory Mapped]	
	P2REN	0x02	Port 2 Resistor Enable [Memory Mapped]	
	P2SEL0	0x00	Port 2 Select 0 [Memory Mapped]	
	P2SEL1	0x03	Port 2 Select 1 [Memory Mapped]	
	P2SELC	0x00	Port 2 Complement Select [Memory Mapped]	
	P2IES	0x00	Port 2 Interrupt Edge Select [Memory Mapped]	
	P2IE	0x00	Port 2 Interrupt Enable [Memory Mapped]	
	P2IFG	0x00	Port 2 Interrupt Flag [Memory Mapped]	
PB@@@			
P3			
	P3IV	0x0000	Port 3 Interrupt Vector Register [Memory Mapped]	
	P3IN	0x00	Port 3 Input [Memory Mapped]	
	P3OUT	0x00	Port 3 Output [Memory Mapped]	
	P3DIR	0x3A	Port 3 Direction [Memory Mapped]	
	P3REN	0x00	Port 3 Resistor Enable [Memory Mapped]	
	P3SEL0	0x00	Port 3 Select 0 [Memory Mapped]	
	P3SEL1	0x00	Port 3 Select 1 [Memory Mapped]	
	P3SELC	0x00	Port 3 Complement Select [Memory Mapped]	
	P3IES	0x00	Port 3 Interrupt Edge Select [Memory Mapped]	
	P3IE	0x00	Port 3 Interrupt Enable [Memory Mapped]	
	P3IFG	0x00	Port 3 Interrupt Flag [Memory Mapped]	
P4			
	P4IV	0x0000	Port 4 Interrupt Vector Register [Memory Mapped]	
	P4IN	0x00	Port 4 Input [Memory Mapped]	
	P4OUT	0x00	Port 4 Output [Memory Mapped]	
	P4DIR	0x10	Port 4 Direction [Memory Mapped]	
	P4REN	0x0F	Port 4 Resistor Enable [Memory Mapped]	
	P4SEL0	0x00	Port 4 Select 0 [Memory Mapped]	
	P4SEL1	0x00	Port 4 Select 1 [Memory Mapped]	
	P4SELC	0x00	Port 4 Complement Select [Memory Mapped]	
	P4IES	0x00	Port 4 Interrupt Edge Select [Memory Mapped]	
	P4IE	0x04	Port 4 Interrupt Enable [Memory Mapped]	
	P4IFG	0x00	Port 4 Interrupt Flag [Memory Mapped]	
PC@@@		
P5			
	P5IV	0x0000	Port 5 Interrupt Vector Register [Memory Mapped]	
	P5IN	0x82	Port 5 Input [Memory Mapped]	
	P5OUT	0x82	Port 5 Output [Memory Mapped]	
	P5DIR	0xB6	Port 5 Direction [Memory Mapped]	
	P5REN	0x49	Port 5 Resistor Enable [Memory Mapped]	
	P5SEL0	0x00	Port 5 Select 0 [Memory Mapped]	
	P5SEL1	0x00	Port 5 Select 1 [Memory Mapped]	
	P5SELC	0x00	Port 5 Complement Select [Memory Mapped]	
	P5IES	0x00	Port 5 Interrupt Edge Select [Memory Mapped]	
	P5IE	0x00	Port 5 Interrupt Enable [Memory Mapped]	
	P5IFG	0x82	Port 5 Interrupt Flag [Memory Mapped]	
P6			
	P6IV	0x0000	Port 6 Interrupt Vector Register [Memory Mapped]	
	P6IN	0x00	Port 6 Input [Memory Mapped]	
	P6OUT	0x00	Port 6 Output [Memory Mapped]	
	P6DIR	0x75	Port 6 Direction [Memory Mapped]	
	P6REN	0x00	Port 6 Resistor Enable [Memory Mapped]	
	P6SEL0	0x00	Port 6 Select 0 [Memory Mapped]	
	P6SEL1	0x00	Port 6 Select 1 [Memory Mapped]	
	P6SELC	0x00	Port 6 Complement Select [Memory Mapped]	
	P6IES	0x00	Port 6 Interrupt Edge Select [Memory Mapped]	
	P6IE	0x00	Port 6 Interrupt Enable [Memory Mapped]	
	P6IFG	0x00	Port 6 Interrupt Flag [Memory Mapped]	
PD@@@
P7			
	P7IV	0x0000	Port 7 Interrupt Vector Register [Memory Mapped]	
	P7IN	0x00	Port 7 Input [Memory Mapped]	
	P7OUT	0x00	Port 7 Output [Memory Mapped]	
	P7DIR	0x01	Port 7 Direction [Memory Mapped]	
	P7REN	0x00	Port 7 Resistor Enable [Memory Mapped]	
	P7SEL0	0x00	Port 7 Select 0 [Memory Mapped]	
	P7SEL1	0x00	Port 7 Select 1 [Memory Mapped]	
	P7SELC	0x00	Port 7 Complement Select [Memory Mapped]	
	P7IES	0x00	Port 7 Interrupt Edge Select [Memory Mapped]	
	P7IE	0x00	Port 7 Interrupt Enable [Memory Mapped]	
	P7IFG	0x00	Port 7 Interrupt Flag [Memory Mapped]	
P8@@@			
PE@@@			
P9@@@			
PJ			
	PJIN	0x0080	Port J Input [Memory Mapped]	
	PJOUT	0x0000	Port J Output [Memory Mapped]	
	PJDIR	0x0000	Port J Direction [Memory Mapped]	
	PJREN	0x0000	Port J Resistor Enable [Memory Mapped]	
	PJSEL0	0x0030	Port J Select 0 [Memory Mapped]	
	PJSEL1	0x0000	Port J Select 1 [Memory Mapped]	
	PJSELC	0x0000	Port J Complement Select [Memory Mapped]	
DMA	
Used for wireless and wired content transfer. Stopped when entering LPM
	DMACTL0	0x0000	DMA Control 0 [Memory Mapped]	
	DMACTL1	0x0000	DMA Control 1 [Memory Mapped]	
	DMACTL2	0x0000	DMA Control 2 [Memory Mapped]	
	DMACTL4	0x0000	DMA Control 4 [Memory Mapped]	
	DMAIV	0x0000	DMA Interrupt Vector [Memory Mapped]	
	DMA0CTL	0x0000	DMA Channel 0 Control [Memory Mapped]	
	DMA0SA	0x000000	DMA Channel 0 Source Address [Memory Mapped]	
	DMA0DA	0x000000	DMA Channel 0 Destination Address [Memory Mapped]	
	DMA0SZ	0x0000	DMA Channel 0 Transfer Size [Memory Mapped]	
	DMA1CTL	0x0000	DMA Channel 1 Control [Memory Mapped]	
	DMA1SA	0x0344A4	DMA Channel 1 Source Address [Memory Mapped]	
	DMA1DA	0x08D421	DMA Channel 1 Destination Address [Memory Mapped]	
	DMA1SZ	0xFA1F	DMA Channel 1 Transfer Size [Memory Mapped]	
	DMA2CTL	0x0000	DMA Channel 2 Control [Memory Mapped]	
	DMA2SA	0x006442	DMA Channel 2 Source Address [Memory Mapped]	
	DMA2DA	0x0007A8	DMA Channel 2 Destination Address [Memory Mapped]	
	DMA2SZ	0xC4D0	DMA Channel 2 Transfer Size [Memory Mapped]	
	DMA3CTL	0x0000	DMA Channel 3 Control [Memory Mapped]	
	DMA3SA	0x000100	DMA Channel 3 Source Address [Memory Mapped]	
	DMA3DA	0x05A000	DMA Channel 3 Destination Address [Memory Mapped]	
	DMA3SZ	0x7092	DMA Channel 3 Transfer Size [Memory Mapped]	
	DMA4CTL	0x0000	DMA Channel 4 Control [Memory Mapped]	
	DMA4SA	0x073C00	DMA Channel 4 Source Address [Memory Mapped]	
	DMA4DA	0x030218	DMA Channel 4 Destination Address [Memory Mapped]	
	DMA4SZ	0x1FF6	DMA Channel 4 Transfer Size [Memory Mapped]	
	DMA5CTL	0x0000	DMA Channel 5 Control [Memory Mapped]	
	DMA5SA	0x040885	DMA Channel 5 Source Address [Memory Mapped]	
	DMA5DA	0x0C1000	DMA Channel 5 Destination Address [Memory Mapped]	
	DMA5SZ	0x8A08	DMA Channel 5 Transfer Size [Memory Mapped]	
FRCTL_A	
Comment: Setting to retain RAM even when put in LPM
	FRCTL0	0x9600	FRAM Controller A Control Register 0 [Memory Mapped]	
	GCCTL0	0x0004	General Control Register 0 [Memory Mapped]	
	GCCTL1	0x0000	General Control Register 1 [Memory Mapped]	
HSPLL@@@
	HSPLLIIDX	0x0000	Interrupt Index Register [Memory Mapped]	
	HSPLLMIS	0x0000	Masked Interrupt Status Register. [Memory Mapped]	
	HSPLLRIS	0x0000	Raw Interrupt Status Register [Memory Mapped]	
	HSPLLIMSC	0x0000	Interrupt Mask Register [Memory Mapped]	
	HSPLLICR	0x0000	Interrupt Flag Clear Register. [Memory Mapped]	
	HSPLLISR	0x0000	Interrupt Flag Set Register. [Memory Mapped]	
	HSPLLDESCLO	0x0110	HSPLL Descriptor Register L. [Memory Mapped]	
	HSPLLDESCHI	0xBD10	HSPLL Descriptor Register H. [Memory Mapped]	
	HSPLLCTL	0x4000	HSPLL Control Register [Memory Mapped]	
	HSPLLUSSXTLCTL	0x0100	USSXT Control Register [Memory Mapped]	
LEA@@@
*The shared RAM is used as normal RAM by editing the cmd file.	
	LEACAP	0x00000001	LEA Capability Register [Memory Mapped]	
	LEACNF0	0x00000001	Configuration Register 0 [Memory Mapped]	
	LEACNF1	0x0000C000	Configuration Register 1 [Memory Mapped]	
	LEACNF2	0x00000000	Configuration Register 2 [Memory Mapped]	
	LEAMB	0x00004000	Memory Bottom Register [Memory Mapped]	
	LEAMT	0x00006000	Memory Top Register [Memory Mapped]	
	LEACMA	0x00000000	Code Memory Access Register [Memory Mapped]	
	LEACMCTL	0x00000020	Code Memory Control Register [Memory Mapped]	
	LEACMDSTAT	0x00000000	LEA Command Status Register [Memory Mapped]	
	LEAS1STAT	0x00000000	LEA Source 1 Status Register [Memory Mapped]	
	LEAS0STAT	0x00000000	LEA Source 0 Status Register [Memory Mapped]	
	LEADSTSTAT	0x00000001	LEA Result Status Register [Memory Mapped]	
	LEAPMCTL	0x00000000	PM Control Register [Memory Mapped]	
	LEAPMDST	0x00000000	PM Result Register [Memory Mapped]	
	LEAPMS1	0x00000000	PM Source 1 Register [Memory Mapped]	
	LEAPMS0	0x00000000	PM Source 0 Register [Memory Mapped]	
	LEAPMCB	0x00000000	PM Command Buffer Register [Memory Mapped]	
	LEAIFGSET	0x00000000	Interrupt Flag and Set Register [Memory Mapped]	
	LEAIE	0x00000000	Interrupt Enable Register [Memory Mapped]	
	LEAIFG	0x00000000	Interrupt Flag and Clear Register [Memory Mapped]	
	LEAIV	0x00000000	Interrupt Vector Register [Memory Mapped]	
MPU@@@
	MPUCTL0	0x9600	Memory Protection Unit Control 0 [Memory Mapped]	
	MPUCTL1	0x0000	Memory Protection Unit Control 1 [Memory Mapped]	
	MPUSEGB2	0x0000	Memory Protection Unit Segmentation Border 2 Register [Memory Mapped]	
	MPUSEGB1	0x0000	Memory Protection Unit Segmentation Border 1 Register [Memory Mapped]	
	MPUSAM	0x7777	Memory Protection Unit Segmentation Access Management Register [Memory Mapped]	
	MPUIPC0	0x0000	Memory Protection Unit IP Control 0 Register [Memory Mapped]	
	MPUIPSEGB2	0x0000	Memory Protection Unit IP Encapsulation Segment Border 2 Register [Memory Mapped]	
	MPUIPSEGB1	0x0000	Memory Protection Unit IP Encapsulation Segment Border 1 Register [Memory Mapped]	
MPY32@@@			
	MPY	0x2239	16-bit operand one  multiply [Memory Mapped]	
	MPYS	0x2239	16-bit operand one  signed multiply [Memory Mapped]	
	MAC	0x2239	16-bit operand one  multiply accumulate [Memory Mapped]	
	MACS	0x2239	16-bit operand one  signed multiply accumulate [Memory Mapped]	
	OP2	0x0049	16-bit operand two [Memory Mapped]	
	RESLO	0x0200	16x16-bit result low word [Memory Mapped]	
	RESHI	0xF902	16x16-bit result high word [Memory Mapped]	
	SUMEXT	0x0000	16x16-bit sum extension register [Memory Mapped]	
	MPY32L	0x2239	32-bit operand 1  multiply  low word [Memory Mapped]	
	MPY32H	0x4880	32-bit operand 1  multiply  high word [Memory Mapped]	
	MPYS32L	0x2239	32-bit operand 1  signed multiply  low word [Memory Mapped]	
	MPYS32H	0x4880	32-bit operand 1  signed multiply  high word [Memory Mapped]	
	MAC32L	0x2239	32-bit operand 1  multiply accumulate  low word [Memory Mapped]	
	MAC32H	0x4880	32-bit operand 1  multiply accumulate  high word [Memory Mapped]	
	MACS32L	0x2239	32-bit operand 1  signed multiply accumulate  low word [Memory Mapped]	
	MACS32H	0x4880	32-bit operand 1  signed multiply accumulate  high word [Memory Mapped]	
	OP2L	0x0049	32-bit operand 2  low word [Memory Mapped]	
	OP2H	0x8002	32-bit operand 2  high word [Memory Mapped]	
	RES0	0x0200	32x32-bit result 0  least significant word [Memory Mapped]	
	RES1	0xF902	32x32-bit result 1 [Memory Mapped]	
	RES2	0x90C1	32x32-bit result 2 [Memory Mapped]	
	RES3	0x0980	32x32-bit result 3  most significant word [Memory Mapped]	
	MPY32CTL0	0x0041	MPY32 control register 0 [Memory Mapped]	
MTIF@@@			
	MTIFPGCNF	0x6970	Pulse Generator Configuration Register [Memory Mapped]	
	MTIFPGKVAL	0x6900	Pulse Generator Value Register [Memory Mapped]	
	MTIFPGCTL	0x6900	Pulse Generator Control Register [Memory Mapped]	
	MTIFPGSR	0x0000	Pulse Generator Status Register [Memory Mapped]	
	MTIFPCCNF	0x9600	Pulse Counter Configuration Register [Memory Mapped]	
	MTIFPCR	0x0000	Pulse Counter Value Register [Memory Mapped]	
	MTIFPCCTL	0x0000	Pulse Counter Control Register [Memory Mapped]	
	MTIFPCSR	0x0000	Pulse Counter Status Register [Memory Mapped]	
	MTIFTPCTL	0x0F00	Measurement Test Port Control Register [Memory Mapped]	
PMM
Comment: Unlocking PMx.5
	PMMCTL0	0x9640	PMM control register 0 [Memory Mapped]	
	PMMIFG	0x2200	PMM interrupt flag register [Memory Mapped]	
	PM5CTL0	0x0000	Power mode 5 control register 0 [Memory Mapped]	
RAMCTL@@@			
	RCCTL0	0x6900	RAM Controller Control 0 [Memory Mapped]	
	RCCTL1	0x0000	RAM Controller Control 1 [Memory Mapped]	
REF_A
Comment: Used for AD conversion.		
	REFCTL0	0x0008	REF Control Register 0 [Memory Mapped]	
		REFBGRDY	0 - REFBGRDY_0	Buffered bandgap voltage ready status	
		REFGENRDY	0 - REFGENRDY_0	Variable reference voltage ready status	
		BGMODE	0 - BGMODE_0	Bandgap mode	
		REFGENBUSY	0 - REFGENBUSY_0	Reference generator busy	
		REFBGACT	0 - REFBGACT_0	Reference bandgap active	
		REFGENACT	0 - REFGENACT_0	Reference generator active	
		REFBGOT	0 - REFBGOT_0	Bandgap and bandgap buffer one-time trigger	
		REFGENOT	0 - REFGENOT_0	Reference generator one-time trigger	
		REFVSEL	00 - REFVSEL_0	Reference voltage level select	
		REFTCOFF	1 - REFTCOFF_1	Temperature sensor disabled	
		REFOUT	0 - REFOUT_0	Reference output buffer	
		REFON	0 - REFON_0	Reference enable	
RTC_C
Comment: Making a 1 second count. No vectored interrupts used.
	RTCCTL0	0x9608	RTCCTL0 Register [Memory Mapped]	
	RTCCTL13	0x000F	RTCCTL13 Register [Memory Mapped]	
	RTCOCAL	0x0000	RTCOCAL Register [Memory Mapped]	
	RTCTCMP	0x4000	RTCTCMP Register [Memory Mapped]	
	RTCPS0CTL	0x3801	Real-Time Clock Prescale Timer 0 Control Register [Memory Mapped]	
	RTCPS1CTL	0xF001	Real-Time Clock Prescale Timer 1 Control Register [Memory Mapped]	
	RTCPS	0x1990	Real-Time Clock Prescale Timer Counter Register [Memory Mapped]	
	RTCIV	0x0000	Real-Time Clock Interrupt Vector Register [Memory Mapped]	
	RTCTIM0	0x0024	RTCTIM0 Register  Hexadecimal Format [Memory Mapped]	
	RTCTIM0_BCD	0x0024	Real-Time Clock Seconds, Minutes Register - BCD Format [Memory Mapped]	
	RTCCNT12	0x0024	Real-Time Clock Counter 1 and 2  Register  Counter Mode [Memory Mapped]	
	RTCTIM1	0x0000	Real-Time Clock Hour, Day of Week [Memory Mapped]	
	RTCTIM1_BCD	0x0000	Real-Time Clock Hour, Day of Week - BCD Format [Memory Mapped]	
	RTCCNT34	0x0000	Real-Time Clock Counter 3 and 4  Register  Counter Mode [Memory Mapped]	
	RTCDATE	0x0000	RTCDATE - Hexadecimal Format [Memory Mapped]	
	RTCDATE_BCD	0x0000	Real-Time Clock Date - BCD Format [Memory Mapped]	
	RTCYEAR	0x0000	RTCYEAR Register  Hexadecimal Format [Memory Mapped]	
	RTCYEAR_BCD	0x0000	Real-Time Clock Year Register - BCD Format [Memory Mapped]	
	RTCAMINHR	0x0000	RTCMINHR - Hexadecimal Format [Memory Mapped]	
	RTCAMINHR_BCD	0x0000	Real-Time Clock Minutes, Hour Alarm - BCD Format [Memory Mapped]	
	RTCADOWDAY	0x0000	RTCADOWDAY - Hexadecimal Format [Memory Mapped]	
	RTCADOWDAY_BCD	0x0000	Real-Time Clock Day of Week, Day of Month Alarm - BCD Format [Memory Mapped]	
	BIN2BCD	0x0000	Binary-to-BCD Conversion Register [Memory Mapped]	
	BCD2BIN	0x0000	BCD-to-Binary Conversion Register [Memory Mapped]	
	RT0PS	0x90	Prescale timer 0 counter value [Memory Mapped]	
	RT1PS	0x19	Prescale timer 1 counter value [Memory Mapped]	
	RTCCNT1	0x24	The RTCCNT1 register is the count of RTCCNT1 [Memory Mapped]	
	RTCCNT2	0x00	The RTCCNT2 register is the count of RTCCNT2 [Memory Mapped]	
	RTCCNT3	0x00	The RTCCNT3 register is the count of RTCCNT3 [Memory Mapped]	
	RTCCNT4	0x00	The RTCCNT4 register is the count of RTCCNT4 [Memory Mapped]	
SAPH_A@@@
	SAPH_AIIDX	0x0000	Interrupt Index [Memory Mapped]	
	SAPH_AMIS	0x0000	Masked Interrupt Satus [Memory Mapped]	
	SAPH_ARIS	0x0000	Raw Interrupt Status [Memory Mapped]	
	SAPH_AIMSC	0x0000	Interrupt Mask [Memory Mapped]	
	SAPH_AICR	0x0000	Interrupt Clear [Memory Mapped]	
	SAPH_AISR	0x0000	Interrupt Set [Memory Mapped]	
	SAPH_ADESCLO	0x0010	Module-Descriptor Low Word [Memory Mapped]	
	SAPH_ADESCHI	0x5553	Module-Descriptor High Word [Memory Mapped]	
	SAPH_AKEY	0x0000	Key [Memory Mapped]	
	SAPH_AOCTL0	0x0000	Physical Interface Output Control #0 [Memory Mapped]	
	SAPH_AOCTL1	0x0000	Physical Interface Output Control #1 [Memory Mapped]	
	SAPH_AOSEL	0x0005	Physical Interface Output Function Select [Memory Mapped]	
	SAPH_ACH0PUT	0x000F	Channel 0 Pull UpTrim Register [Memory Mapped]	
	SAPH_ACH0PDT	0x000D	Channel 0 Pull DownTrim Register [Memory Mapped]	
	SAPH_ACH0TT	0x000D	Channel 0 Termination Trim [Memory Mapped]	
	SAPH_ACH1PUT	0x000F	Channel 1 Pull UpTrim [Memory Mapped]	
	SAPH_ACH1PDT	0x000D	Channel 1 Pull DownTrim [Memory Mapped]	
	SAPH_ACH1TT	0x000D	Channel 1 Termination Trim [Memory Mapped]	
	SAPH_AMCNF	0x0002	Mode Configuration Register [Memory Mapped]	
	SAPH_ATACTL	0x0000	Trim Access Control [Memory Mapped]	
	SAPH_AICTL0	0x0090	Physical Interface Input Control #0 [Memory Mapped]	
	SAPH_ABCTL	0x00A1	Bias Control [Memory Mapped]	
	SAPH_APGC	0x0000	PPG Count [Memory Mapped]	
	SAPH_APGLPER	0x0000	Pulse Generator Low Period [Memory Mapped]	
	SAPH_APGHPER	0x0000	Pulse Generator High Period [Memory Mapped]	
	SAPH_APGCTL	0x0011	PPG Control [Memory Mapped]	
	SAPH_APPGTRIG	0x0000	PPG Software Trigger [Memory Mapped]	
	SAPH_AXPGCTL	0x0000	Extended Pulse Control Register [Memory Mapped]	
	SAPH_AXPGLPER	0x0000	Extra Pulse Low Period Register [Memory Mapped]	
	SAPH_AXPGHPER	0x0000	Extra Pulse High Period Register [Memory Mapped]	
	SAPH_AASCTL0	0x0000	A-SEQ control register 0 [Memory Mapped]	
	SAPH_AASCTL1	0x0000	A-SEQ control register 1 [Memory Mapped]	
	SAPH_AASQTRIG	0x00	ASQ Software Trigger [Memory Mapped]	
	SAPH_AAPOL	0x0000	ASQ ping output polarity [Memory Mapped]	
	SAPH_AAPLEV	0x0000	ASQ ping pause level [Memory Mapped]	
	SAPH_AAPHIZ	0x0000	ASQ ping pause impedance [Memory Mapped]	
	SAPH_AATM_A	0x0000	A-SEQ start to 1st ping [Memory Mapped]	
	SAPH_AATM_B	0x0000	ASQ start to ADC arm [Memory Mapped]	
	SAPH_AATM_C	0x0000	Count for the TIMEMARK C Event [Memory Mapped]	
	SAPH_AATM_D	0x0000	ASQ start to ADC trig [Memory Mapped]	
	SAPH_AATM_E	0x0000	ASQ start to restart [Memory Mapped]	
	SAPH_AATM_F	0x0000	ASQ start to timeout [Memory Mapped]	
	SAPH_ATBCTL	0x0000	Time Base Control [Memory Mapped]	
	SAPH_AATIMLO	0x0000	Acquisition Timer Low Part [Memory Mapped]	
	SAPH_AATIMHI	0x0000	Acquisition Timer High Part [Memory Mapped]	
SDHS@@@
	SDHSIIDX	0x0000	Interrupt Index Register [Memory Mapped]	
	SDHSMIS	0x0000	Masked Interrupt Status and Clear Register [Memory Mapped]	
	SDHSRIS	0x0000	Raw Interrupt Status Register [Memory Mapped]	
	SDHSIMSC	0x0000	Interrupt Mask Register [Memory Mapped]	
	SDHSICR	0x0000	Interrupt Clear Register. [Memory Mapped]	
	SDHSISR	0x0000	Interrupt Set Register. [Memory Mapped]	
	SDHSDESCLO	0x0110	SDHS Descriptor Register L. [Memory Mapped]	
	SDHSDESCHI	0xBB10	SDHS Descriptor Register H. [Memory Mapped]	
	SDHSCTL0	0x8001	SDHS Control Register 0 [Memory Mapped]	
	SDHSCTL1	0x0000	SDHS Control Register 1 [Memory Mapped]	
	SDHSCTL2	0x0000	SDHS Control Register 2 [Memory Mapped]	
	SDHSCTL3	0x0000	SDHS Control Register 3 [Memory Mapped]	
	SDHSCTL4	0x0000	SDHS Control Register 4 [Memory Mapped]	
	SDHSCTL5	0x0000	SDHS Control Register 5 [Memory Mapped]	
	SDHSCTL6	0x0019	SDHS Control Register 6 [Memory Mapped]	
	SDHSCTL7	0x000F	SDHS Control Register 7 [Memory Mapped]	
	SDHSDT	0x0000	SDHS Data Converstion Register [Memory Mapped]	
	SDHSWINHITH	0x0000	SDHS Window Comparator High Threshold Register. [Memory Mapped]	
	SDHSWINLOTH	0x0000	SDHS Window Comparator Low Threshold Register. [Memory Mapped]	
	SDHSDTCDA	0x0000	DTC destination address register [Memory Mapped]	
SFR@@@			
	SFRIE1	0x0000	Interrupt Enable [Memory Mapped]	
	SFRIFG1	0x0080	Interrupt Flag [Memory Mapped]	
	SFRRPCR	0x001C	Reset Pin Control [Memory Mapped]	
SYS@@@			
	SYSCTL	0x0000	System Control [Memory Mapped]	
	SYSJMBC	0x000C	JTAG Mailbox Control [Memory Mapped]	
	SYSJMBI0	0x0000	JTAG Mailbox Input [Memory Mapped]	
	SYSJMBI1	0x0000	JTAG Mailbox Input [Memory Mapped]	
	SYSJMBO0	0x5AA4	JTAG Mailbox Output [Memory Mapped]	
	SYSJMBO1	0x0000	JTAG Mailbox Output [Memory Mapped]	
	SYSUNIV	0x0000	User NMI Vector Generator [Memory Mapped]	
	SYSSNIV	0x0000	System NMI Vector Generator [Memory Mapped]	
	SYSRSTIV	0x0004	Reset Vector Generator [Memory Mapped]	
TA0@@@			
	TA0CTL	0x0000	TimerAx Control Register [Memory Mapped]	
	TA0CCTL0	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA0CCTL1	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA0CCTL2	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA0R	0x0000	TimerA register [Memory Mapped]	
	TA0CCR0	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA0CCR1	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA0CCR2	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA0EX0	0x0000	TimerAx Expansion 0 Register [Memory Mapped]	
	TA0IV	0x0000	TimerAx Interrupt Vector Register [Memory Mapped]	
TA1
Comment: Interrupt at 1ms.		
	TA1CTL	0x0000	TimerAx Control Register [Memory Mapped]	
	TA1CCTL0	0x0001	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA1CCTL1	0x0001	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA1CCTL2	0x0001	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA1R	0x001A	TimerA register [Memory Mapped]	
	TA1CCR0	0x0020	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA1CCR1	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA1CCR2	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA1EX0	0x0000	TimerAx Expansion 0 Register [Memory Mapped]	
	TA1IV	0x0000	TimerAx Interrupt Vector Register [Memory Mapped]	
TA2@@@
	TA2CTL	0x0000	TimerAx Control Register [Memory Mapped]	
	TA2CCTL0	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA2CCTL1	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA2R	0x0000	TimerA register [Memory Mapped]	
	TA2CCR0	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA2CCR1	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA2EX0	0x0000	TimerAx Expansion 0 Register [Memory Mapped]	
	TA2IV	0x0000	TimerAx Interrupt Vector Register [Memory Mapped]	
TA3@@@			
	TA3CTL	0x0000	TimerAx Control Register [Memory Mapped]	
	TA3CCTL0	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA3CCTL1	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA3R	0x0000	TimerA register [Memory Mapped]	
	TA3CCR0	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA3CCR1	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA3EX0	0x0000	TimerAx Expansion 0 Register [Memory Mapped]	
	TA3IV	0x0000	TimerAx Interrupt Vector Register [Memory Mapped]	
TA4@@@			
	TA4CTL	0x0000	TimerAx Control Register [Memory Mapped]	
	TA4CCTL0	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA4CCTL1	0x0000	Timer_A Capture/Compare Control Register [Memory Mapped]	
	TA4R	0x0000	TimerA register [Memory Mapped]	
	TA4CCR0	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA4CCR1	0x0000	Timer_A Capture/Compare  Register [Memory Mapped]	
	TA4EX0	0x0000	TimerAx Expansion 0 Register [Memory Mapped]	
	TA4IV	0x0000	TimerAx Interrupt Vector Register [Memory Mapped]	
TB0@@@			
	TB0CTL	0x0000	Timer_B Control Register [Memory Mapped]	
	TB0CCTL0	0x0000	Timer_B Capture/Compare Control Register [Memory Mapped]	
	TB0CCTL1	0x0000	Timer_B Capture/Compare Control Register [Memory Mapped]	
	TB0CCTL2	0x0000	Timer_B Capture/Compare Control Register [Memory Mapped]	
	TB0CCTL3	0x0000	Timer_B Capture/Compare Control Register [Memory Mapped]	
	TB0CCTL4	0x0000	Timer_B Capture/Compare Control Register [Memory Mapped]	
	TB0CCTL5	0x0000	Timer_B Capture/Compare Control Register [Memory Mapped]	
	TB0CCTL6	0x0000	Timer_B Capture/Compare Control Register [Memory Mapped]	
	TB0R	0x0000	Timer_B count register [Memory Mapped]	
	TB0CCR0	0x0000	Timer_B Capture/Compare  Register [Memory Mapped]	
	TB0CCR1	0x0000	Timer_B Capture/Compare  Register [Memory Mapped]	
	TB0CCR2	0x0000	Timer_B Capture/Compare  Register [Memory Mapped]	
	TB0CCR3	0x0000	Timer_B Capture/Compare  Register [Memory Mapped]	
	TB0CCR4	0x0000	Timer_B Capture/Compare  Register [Memory Mapped]	
	TB0CCR5	0x0000	Timer_B Capture/Compare  Register [Memory Mapped]	
	TB0CCR6	0x0000	Timer_B Capture/Compare  Register [Memory Mapped]	
	TB0EX0	0x0000	Timer_Bx Expansion Register 0 [Memory Mapped]	
	TB0IV	0x0000	Timer_Bx Interrupt Vector Register [Memory Mapped]	
UUPS@@@			
	UUPSIIDX	0x0000	Interrupt Index Register [Memory Mapped]	
	UUPSMIS	0x0000	Masked Interrupt Status Register [Memory Mapped]	
	UUPSRIS	0x0000	Raw Interrupt Status Register [Memory Mapped]	
	UUPSIMSC	0x0000	Interrupt Mask Register [Memory Mapped]	
	UUPSICR	0x0000	Interrupt Clear Register. [Memory Mapped]	
	UUPSISR	0x0000	Interrupt Flag Set Register. [Memory Mapped]	
	UUPSDESCLO	0x0110	UUPS Descriptor Register L. [Memory Mapped]	
	UUPSDESCHI	0xBA10	UUPS Descriptor Register H. [Memory Mapped]	
	UUPSCTL	0x0800	UUPS Control [Memory Mapped]	
WDT_A
Comment: timeout of 1s. stop when entering LPM
	WDTCTL	0x69A4	Watchdog Timer Control Register [Memory Mapped]	
		WDTPW	01101001	Watchdog timer password	
		WDTHOLD	1 - HOLD	Watchdog timer hold	
		WDTSSEL	01 - ACLK	Watchdog timer clock source select	
		WDTTMSEL	0 - WDTTMSEL_0	Watchdog timer mode select	
		WDTCNTCL	0 - WDTCNTCL_0	Watchdog timer counter clear	
		WDTIS	100 - 32K	Watchdog timer interval select	
eUSCI_A0@@@			
	UCA0CTLW0	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA0CTLW0_SPI	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA0CTLW1	0x0003	eUSCI_Ax Control Word Register 1 [Memory Mapped]	
	UCA0BRW	0x0000	eUSCI_Ax Baud Rate Control Word Register [Memory Mapped]	
	UCA0BRW_SPI	0x0000	eUSCI_Ax Bit Rate Control Register 1 [Memory Mapped]	
	UCA0MCTLW	0x0000	eUSCI_Ax Modulation Control Word Register [Memory Mapped]	
	UCA0STATW	0x0000	eUSCI_Ax Status Register [Memory Mapped]	
	UCA0STATW_SPI	0x0000	Memory Mapped	
	UCA0RXBUF	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA0RXBUF_SPI	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA0TXBUF	0x0000	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA0TXBUF_SPI	0x0000	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA0ABCTL	0x0000	eUSCI_Ax Auto Baud Rate Control Register [Memory Mapped]	
	UCA0IRCTL	0x0000	eUSCI_Ax IrDA Control Word Register [Memory Mapped]	
	UCA0IE	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA0IE_SPI	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA0IFG	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA0IFG_SPI	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA0IV	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
	UCA0IV_SPI	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
eUSCI_A1@@@			
	UCA1CTLW0	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA1CTLW0_SPI	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA1CTLW1	0x0003	eUSCI_Ax Control Word Register 1 [Memory Mapped]	
	UCA1BRW	0x0000	eUSCI_Ax Baud Rate Control Word Register [Memory Mapped]	
	UCA1BRW_SPI	0x0000	eUSCI_Ax Bit Rate Control Register 1 [Memory Mapped]	
	UCA1MCTLW	0x0000	eUSCI_Ax Modulation Control Word Register [Memory Mapped]	
	UCA1STATW	0x0000	eUSCI_Ax Status Register [Memory Mapped]	
	UCA1STATW_SPI	0x0000	Memory Mapped	
	UCA1RXBUF	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA1RXBUF_SPI	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA1TXBUF	0x0000	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA1TXBUF_SPI	0x0000	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA1ABCTL	0x0000	eUSCI_Ax Auto Baud Rate Control Register [Memory Mapped]	
	UCA1IRCTL	0x0000	eUSCI_Ax IrDA Control Word Register [Memory Mapped]	
	UCA1IE	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA1IE_SPI	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA1IFG	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA1IFG_SPI	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA1IV	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
	UCA1IV_SPI	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
eUSCI_A2@@@			
	UCA2CTLW0	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA2CTLW0_SPI	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA2CTLW1	0x0003	eUSCI_Ax Control Word Register 1 [Memory Mapped]	
	UCA2BRW	0x0000	eUSCI_Ax Baud Rate Control Word Register [Memory Mapped]	
	UCA2BRW_SPI	0x0000	eUSCI_Ax Bit Rate Control Register 1 [Memory Mapped]	
	UCA2MCTLW	0x0000	eUSCI_Ax Modulation Control Word Register [Memory Mapped]	
	UCA2STATW	0x0000	eUSCI_Ax Status Register [Memory Mapped]	
	UCA2STATW_SPI	0x0000	Memory Mapped	
	UCA2RXBUF	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA2RXBUF_SPI	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA2TXBUF	0x0000	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA2TXBUF_SPI	0x0000	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA2ABCTL	0x0000	eUSCI_Ax Auto Baud Rate Control Register [Memory Mapped]	
	UCA2IRCTL	0x0000	eUSCI_Ax IrDA Control Word Register [Memory Mapped]	
	UCA2IE	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA2IE_SPI	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA2IFG	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA2IFG_SPI	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA2IV	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
	UCA2IV_SPI	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
eUSCI_A3
Comment: Used with uart. Stop when entering LPM
	UCA3CTLW0	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA3CTLW0_SPI	0x0001	eUSCI_Ax Control Word Register 0 [Memory Mapped]	
	UCA3CTLW1	0x0003	eUSCI_Ax Control Word Register 1 [Memory Mapped]	
	UCA3BRW	0x0068	eUSCI_Ax Baud Rate Control Word Register [Memory Mapped]	
	UCA3BRW_SPI	0x0068	eUSCI_Ax Bit Rate Control Register 1 [Memory Mapped]	
	UCA3MCTLW	0x0000	eUSCI_Ax Modulation Control Word Register [Memory Mapped]	
	UCA3STATW	0x0000	eUSCI_Ax Status Register [Memory Mapped]	
	UCA3STATW_SPI	0x0000	Memory Mapped	
	UCA3RXBUF	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA3RXBUF_SPI	0x0000	eUSCI_Ax Receive Buffer Register [Memory Mapped]	
	UCA3TXBUF	0x0003	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA3TXBUF_SPI	0x0003	eUSCI_Ax Transmit Buffer Register [Memory Mapped]	
	UCA3ABCTL	0x0000	eUSCI_Ax Auto Baud Rate Control Register [Memory Mapped]	
	UCA3IRCTL	0x0000	eUSCI_Ax IrDA Control Word Register [Memory Mapped]	
	UCA3IE	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA3IE_SPI	0x0000	eUSCI_Ax Interrupt Enable Register [Memory Mapped]	
	UCA3IFG	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA3IFG_SPI	0x0002	eUSCI_Ax Interrupt Flag Register [Memory Mapped]	
	UCA3IV	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
	UCA3IV_SPI	0x0000	eUSCI_Ax Interrupt Vector Register [Memory Mapped]	
eUSCI_B0@@@			
	UCB0CTLW0	0x01C1	eUSCI_Bx Control Word Register 0 [Memory Mapped]	
	UCB0CTLW0_SPI	0x01C1	eUSCI_Bx Control Word Register 0 [Memory Mapped]	
	UCB0CTLW1	0x0000	eUSCI_Bx Control Word Register 1 [Memory Mapped]	
	UCB0BRW	0x0000	eUSCI_Bx Baud Rate Control Word Register [Memory Mapped]	
	UCB0BRW_SPI	0x0000	eUSCI_Bx Bit Rate Control Register 1 [Memory Mapped]	
	UCB0STATW	0x0000	eUSCI_Bx Status Register [Memory Mapped]	
	UCB0TBCNT	0x0000	eUSCI_Bx Byte Counter Threshold Register [Memory Mapped]	
	UCB0RXBUF	0x0000	eUSCI_Bx Receive Buffer Register [Memory Mapped]	
	UCB0RXBUF_SPI	0x0000	eUSCI_Bx Receive Buffer Register [Memory Mapped]	
	UCB0TXBUF	0x0000	eUSCI_Bx Transmit Buffer Register [Memory Mapped]	
	UCB0TXBUF_SPI	0x0000	eUSCI_Bx Transmit Buffer Register [Memory Mapped]	
	UCB0I2COA0	0x0000	eUSCI_Bx I2C Own Address 0 Register [Memory Mapped]	
	UCB0I2COA1	0x0000	eUSCI_Bx I2C Own Address 1 Register [Memory Mapped]	
	UCB0I2COA2	0x0000	eUSCI_Bx I2C Own Address 2 Register [Memory Mapped]	
	UCB0I2COA3	0x0000	eUSCI_Bx I2C Own Address 3 Register [Memory Mapped]	
	UCB0ADDRX	0x0000	eUSCI_Bx I2C Received Address Register [Memory Mapped]	
	UCB0ADDMASK	0x03FF	eUSCI_Bx I2C Address Mask Register [Memory Mapped]	
	UCB0I2CSA	0x0000	eUSCI_Bx I2C Slave Address Register [Memory Mapped]	
	UCB0IE	0x0000	eUSCI_Bx Interrupt Enable Register [Memory Mapped]	
	UCB0IE_SPI	0x0000	eUSCI_Bx Interrupt Enable Register [Memory Mapped]	
	UCB0IFG	0x0002	eUSCI_Bx Interrupt Flag Register [Memory Mapped]	
	UCB0IFG_SPI	0x0002	eUSCI_Bx Interrupt Flag Register [Memory Mapped]	
eUSCI_B1@@@			
	UCB1CTLW0	0x01C1	eUSCI_Bx Control Word Register 0 [Memory Mapped]	
	UCB1CTLW0_SPI	0x01C1	eUSCI_Bx Control Word Register 0 [Memory Mapped]	
	UCB1CTLW1	0x0000	eUSCI_Bx Control Word Register 1 [Memory Mapped]	
	UCB1BRW	0x0000	eUSCI_Bx Baud Rate Control Word Register [Memory Mapped]	
	UCB1BRW_SPI	0x0000	eUSCI_Bx Bit Rate Control Register 1 [Memory Mapped]	
	UCB1STATW	0x0000	eUSCI_Bx Status Register [Memory Mapped]	
	UCB1STATW_SPI	0x0000	Memory Mapped	
	UCB1TBCNT	0x0000	eUSCI_Bx Byte Counter Threshold Register [Memory Mapped]	
	UCB1RXBUF	0x0000	eUSCI_Bx Receive Buffer Register [Memory Mapped]	
	UCB1RXBUF_SPI	0x0000	eUSCI_Bx Receive Buffer Register [Memory Mapped]	
	UCB1TXBUF	0x0000	eUSCI_Bx Transmit Buffer Register [Memory Mapped]	
	UCB1TXBUF_SPI	0x0000	eUSCI_Bx Transmit Buffer Register [Memory Mapped]	
	UCB1I2COA0	0x0000	eUSCI_Bx I2C Own Address 0 Register [Memory Mapped]	
	UCB1I2COA1	0x0000	eUSCI_Bx I2C Own Address 1 Register [Memory Mapped]	
	UCB1I2COA2	0x0000	eUSCI_Bx I2C Own Address 2 Register [Memory Mapped]	
	UCB1I2COA3	0x0000	eUSCI_Bx I2C Own Address 3 Register [Memory Mapped]	
	UCB1ADDRX	0x0000	eUSCI_Bx I2C Received Address Register [Memory Mapped]	
	UCB1ADDMASK	0x03FF	eUSCI_Bx I2C Address Mask Register [Memory Mapped]	
	UCB1I2CSA	0x0000	eUSCI_Bx I2C Slave Address Register [Memory Mapped]	
	UCB1IE	0x0000	eUSCI_Bx Interrupt Enable Register [Memory Mapped]	
	UCB1IE_SPI	0x0000	eUSCI_Bx Interrupt Enable Register [Memory Mapped]	
	UCB1IFG	0x0002	eUSCI_Bx Interrupt Flag Register [Memory Mapped]	
	UCB1IFG_SPI	0x0002	eUSCI_Bx Interrupt Flag Register [Memory Mapped]	
	UCB1IV	0x0000	eUSCI_Bx Interrupt Vector Register [Memory Mapped]	
	UCB1IV_SPI	0x0000	eUSCI_Bx Interrupt Vector Register [Memory Mapped]