//#############################################################################
//
// FILE:     psfbpcmc_hal.c
//
// TITLE:    solution hardware abstraction layer
//           This file consists of board related initialization
//           this file is used to make the
//           main file more readable
//
//#############################################################################
// $TI Release: TIDM_02000 v1.01.01.00 $
// $Release Date: Wed Oct  5 02:42:51 CDT 2022 $
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
//
// ALL RIGHTS RESERVED
// $
//#############################################################################

//#############################################################################
//
// FILE:        psfbpcmc_hal.h
//
// TITLE:       solution hardware abstraction layer header file
//              This file consists of common variables and functions
//              for a particular hardware board, like functions to read current
//              and voltage signals on the board and functions to setup the
//              basic peripherals of the board
//              This file must be settings independent, all settings dependent
//              code should reside in the parent solution project.
//
//#############################################################################
// $TI Release: TIDM_02000 v1.01.01.00 $
// $Release Date: Wed Oct  5 02:42:51 CDT 2022 $
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
//
// ALL RIGHTS RESERVED
// $
//#############################################################################




//
// Include files for device support
//
//###########################################################################
//
// FILE:   hw_types.h
//
// TITLE:  Type definitions used in driverlib functions.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// Macros for hardware access
//
//*****************************************************************************

//*****************************************************************************
//
// SUCCESS and FAILURE for API return value
//
//*****************************************************************************

//****************************************************************************
//
// For checking NULL pointers
//
//****************************************************************************

//*****************************************************************************
//
// 32-bit and 64-bit float type
//
//*****************************************************************************
typedef float         float32_t;
typedef double        float64_t;

//*****************************************************************************
//
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
// These are provided to satisfy static analysis tools. The #ifndef is required
// because the '&' is for a C++-style reference, and although it is the correct
// prototype, it will not build in C code.
//
//*****************************************************************************

//#############################################################################
//
// FILE:   driverlib.h
//
// TITLE:  Device setup for examples.
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//###########################################################################
//
// FILE:    hw_memmap.h
//
// TITLE:   Macros defining the memory map of the C28x.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   adc.h
//
// TITLE:  C28x ADC driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup adc_api ADC
//! @{
//
//*****************************************************************************

/*
 * Copyright (c) 2000 Jeroen Ruigrok van der Werven <asmodai@FreeBSD.org>
 * All rights reserved.
 *
 * Copyright (c) 2014-2014 Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $
 */

/* If this file is included in C99 mode, _Bool is a builtin, so no definition. */
/* If this is C89 mode and this file is included, _Bool is pre-defined in C89 */
/* relaxed mode by the EDG parser, so it needs to be defined in strict mode. */

/*****************************************************************************/
/* _ti_config.h                                                              */
/*                                                                           */
/* Copyright (c) 2017 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/


/*Unsupported pragmas are omitted */
# pragma diag_push
# pragma CHECK_MISRA("-19.7")
# pragma CHECK_MISRA("-19.4")
# pragma CHECK_MISRA("-19.1")
# pragma CHECK_MISRA("-19.15")
# pragma diag_pop

_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.4\")")
_Pragma("CHECK_MISRA(\"-19.1\")")
_Pragma("CHECK_MISRA(\"-19.6\")")

/* Hide uses of the TI proprietary macros behind other macros.
    Implementations that don't implement these features should leave
    these macros undefined. */



/* Common definitions */

/* C */
 /* C89/C99 */





/* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It
   is intended to be used for functions like abort and atexit that are supposed
   to be declared noexcept only in C++14 mode. */



/* Target-specific definitions */
/*****************************************************************************/
/* linkage.h                                                                  */
/*                                                                           */
/* Copyright (c) 1998 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/


#pragma diag_push
#pragma CHECK_MISRA("-19.4") /* macros required for implementation */

/* No modifiers needed to access code */


/*--------------------------------------------------------------------------*/
/* Define _DATA_ACCESS ==> how to access RTS global or static data          */
/*--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------*/
/* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space.                */
/*--------------------------------------------------------------------------*/

/*--------------------------------------------------------------------------*/
/* Define _IDECL ==> how inline functions are declared                      */
/*--------------------------------------------------------------------------*/

#pragma diag_pop


_Pragma("diag_pop")


_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.4\")")
_Pragma("CHECK_MISRA(\"-19.11\")")





_Pragma("diag_pop")

/*****************************************************************************/
/* STDINT.H                                                                  */
/*                                                                           */
/* Copyright (c) 2002 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/


_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.1\")") /* no code before #include */
_Pragma("CHECK_MISRA(\"-19.7\")") /* prefer functions to macros */

/*****************************************************************************/
/* _STDINT40.H                                                               */
/*                                                                           */
/* Copyright (c) 2018 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/

_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.7\")") /* prefer functions to macros */


/*
   According to footnotes in the 1999 C standard, "C++ implementations
   should define these macros only when __STDC_LIMIT_MACROS is defined
   before <stdint.h> is included."
*/



_Pragma("diag_pop")

/*-
 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
 *
 * Copyright (c) 2001 Mike Barcroft <mike@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD$
 */



/*-
 * SPDX-License-Identifier: BSD-3-Clause
 *
 * Copyright (c) 1991, 1993
 *	The Regents of the University of California.  All rights reserved.
 *
 * This code is derived from software contributed to Berkeley by
 * Berkeley Software Design, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the University nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *	@(#)cdefs.h	8.8 (Berkeley) 1/9/95
 * $FreeBSD$
 */



_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"none\")")

/*
 * Testing against Clang-specific extensions.
 */


/*
 * This code has been put in place to help reduce the addition of
 * compiler specific defines in FreeBSD code.  It helps to aid in
 * having a compiler-agnostic source tree.
 */







/*
 * Macro to test if we're using a specific version of gcc or later.
 */

/*
 * The __CONCAT macro is used to concatenate parts of symbol names, e.g.
 * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo.
 * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI
 * mode -- there must be no spaces between its arguments, and for nested
 * __CONCAT's, all the __CONCAT's must be at the left.  __CONCAT can also
 * concatenate double-quoted strings produced by the __STRING macro, but
 * this only works with ANSI C.
 *
 * __XSTRING is like __STRING, but it expands any macros in its argument
 * first.  It is only available with ANSI C.
 */



/*
 * Compiler-dependent macros to help declare dead (non-returning) and
 * pure (no side effects) functions, and unused variables.  They are
 * null except for versions of gcc that are known to support the features
 * properly (old versions of gcc-2 supported the dead and pure features
 * in a different (wrong) way).  If we do not provide an implementation
 * for a given compiler, let the compile fail if it is told to use
 * a feature that we cannot live without.
 */

/*
 * TI ADD - check that __GNUC__ is defined before referencing it to avoid
 *          generating an error when __GNUC__ treated as zero warning is
 *          promoted to an error via -pdse195 option.
 */



/*
 * Keywords added in C11.
 */




/*
 * No native support for _Atomic(). Place object in structure to prevent
 * most forms of direct non-atomic access.
 */



/*
 * XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode
 * without actually supporting the thread_local keyword. Don't check for
 * the presence of C++11 when defining _Thread_local.
 */


/*
 * Emulation of C11 _Generic().  Unlike the previously defined C11
 * keywords, it is not possible to implement this using exactly the same
 * syntax.  Therefore implement something similar under the name
 * __generic().  Unlike _Generic(), this macro can only distinguish
 * between a single type, so it requires nested invocations to
 * distinguish multiple cases.
 */


/*
 * C99 Static array indices in function parameter declarations.  Syntax such as:
 * void bar(int myArray[static 10]);
 * is allowed in C99 but not in C++.  Define __min_size appropriately so
 * headers using it can be compiled in either language.  Use like this:
 * void bar(int myArray[__min_size(10)]);
 */







/* XXX: should use `#if __STDC_VERSION__ < 199901'. */


/* C++11 exposes a load of C99 stuff */

/*
 * GCC 2.95 provides `__restrict' as an extension to C90 to support the
 * C99-specific `restrict' type qualifier.  We happen to use `__restrict' as
 * a way to define the `restrict' type qualifier without disturbing older
 * software that is unaware of C99 keywords.
 * The TI compiler supports __restrict in all compilation modes.
 */

/*
 * GNU C version 2.96 adds explicit branch prediction so that
 * the CPU back-end can hint the processor and also so that
 * code blocks can be reordered such that the predicted path
 * sees a more linear flow, thus improving cache behavior, etc.
 *
 * The following two macros provide us with a way to utilize this
 * compiler feature.  Use __predict_true() if you expect the expression
 * to evaluate to true, and __predict_false() if you expect the
 * expression to evaluate to false.
 *
 * A few notes about usage:
 *
 *	* Generally, __predict_false() error condition checks (unless
 *	  you have some _strong_ reason to do otherwise, in which case
 *	  document it), and/or __predict_true() `no-error' condition
 *	  checks, assuming you want to optimize for the no-error case.
 *
 *	* Other than that, if you don't know the likelihood of a test
 *	  succeeding from empirical or other `hard' evidence, don't
 *	  make predictions.
 *
 *	* These are meant to be used in places that are run `a lot'.
 *	  It is wasteful to make predictions in code that is run
 *	  seldomly (e.g. at subsystem initialization time) as the
 *	  basic block reordering that this affects can often generate
 *	  larger code.
 */


/*
 * We define this here since <stddef.h>, <sys/queue.h>, and <sys/types.h>
 * require it.
 */

/*
 * Given the pointer x to the member m of the struct s, return
 * a pointer to the containing structure.  When using GCC, we first
 * assign pointer x to a local variable, to check that its type is
 * compatible with member m.
 */

/*
 * Compiler-dependent macros to declare that functions take printf-like
 * or scanf-like arguments.  They are null except for versions of gcc
 * that are known to support the features properly (old versions of gcc-2
 * didn't permit keeping the keywords out of the application namespace).
 */

/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */



/*
 * The following definition might not work well if used in header files,
 * but it should be better than nothing.  If you want a "do nothing"
 * version, then it should generate some harmless declaration, such as:
 *    #define	__IDSTRING(name,string)	struct __hack
 */


/*
 * Embed the rcs id of a source file in the resulting library.  Note that in
 * more recent ELF binutils, we use .ident allowing the ID to be stripped.
 * Usage:
 *	__FBSDID("$FreeBSD$");
 */








/*-
 * The following definitions are an extension of the behavior originally
 * implemented in <sys/_posix.h>, but with a different level of granularity.
 * POSIX.1 requires that the macros we test be defined before any standard
 * header file is included.
 *
 * Here's a quick run-down of the versions:
 *  defined(_POSIX_SOURCE)		1003.1-1988
 *  _POSIX_C_SOURCE == 1		1003.1-1990
 *  _POSIX_C_SOURCE == 2		1003.2-1992 C Language Binding Option
 *  _POSIX_C_SOURCE == 199309		1003.1b-1993
 *  _POSIX_C_SOURCE == 199506		1003.1c-1995, 1003.1i-1995,
 *					and the omnibus ISO/IEC 9945-1: 1996
 *  _POSIX_C_SOURCE == 200112		1003.1-2001
 *  _POSIX_C_SOURCE == 200809		1003.1-2008
 *
 * In addition, the X/Open Portability Guide, which is now the Single UNIX
 * Specification, defines a feature-test macro which indicates the version of
 * that specification, and which subsumes _POSIX_C_SOURCE.
 *
 * Our macros begin with two underscores to avoid namespace screwage.
 */

/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */

/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */

/* Deal with various X/Open Portability Guides and Single UNIX Spec. */

/*
 * Deal with all versions of POSIX.  The ordering relative to the tests above is
 * important.
 */
/*-
 * Deal with _ANSI_SOURCE:
 * If it is defined, and no other compilation environment is explicitly
 * requested, then define our internal feature-test macros to zero.  This
 * makes no difference to the preprocessor (undefined symbols in preprocessing
 * expressions are defined to have value zero), but makes it more convenient for
 * a test program to print out the values.
 *
 * If a program mistakenly defines _ANSI_SOURCE and some other macro such as
 * _POSIX_C_SOURCE, we will assume that it wants the broader compilation
 * environment (and in fact we will never get here).
 */

/* User override __EXT1_VISIBLE */


/*
 * Old versions of GCC use non-standard ARM arch symbols; acle-compat.h
 * translates them to __ARM_ARCH and the modern feature symbols defined by ARM.
 */

/*
 * Nullability qualifiers: currently only supported by Clang.
 */

/*
 * Type Safety Checking
 *
 * Clang provides additional attributes to enable checking type safety
 * properties that cannot be enforced by the C type system. 
 */


/*
 * Lock annotations.
 *
 * Clang provides support for doing basic thread-safety tests at
 * compile-time, by marking which locks will/should be held when
 * entering/leaving a functions.
 *
 * Furthermore, it is also possible to annotate variables and structure
 * members to enforce that they are only accessed when certain locks are
 * held.
 */


/* Structure implements a lock. */

/* Function acquires an exclusive or shared lock. */

/* Function attempts to acquire an exclusive or shared lock. */

/* Function releases a lock. */

/* Function asserts that an exclusive or shared lock is held. */

/* Function requires that an exclusive or shared lock is or is not held. */

/* Function should not be analyzed. */

/* Guard variables and structure members by lock. */

_Pragma("diag_pop")

/*-
 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
 *
 * Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD$
 */


/*****************************************************************************/
/*  _TYPES.H                                                                 */
/*                                                                           */
/* Copyright (c) 2017 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/



#pragma diag_push
/* This file is required to use base types */
#pragma CHECK_MISRA("-6.3")


/*
 * Basic types upon which most other types are built.
 */
    typedef          int    __int16_t;
    typedef unsigned int   __uint16_t;
    typedef          long   __int32_t;
    typedef unsigned long  __uint32_t;


/* LONGLONG */
typedef	long long		__int64_t;

/* LONGLONG */
typedef	unsigned long long	__uint64_t;

/*
 * Standard type definitions.
 */
typedef	__uint32_t	__clock_t;		/* clock()... */
typedef	__int32_t	__critical_t;
typedef	double		__double_t;
typedef	float		__float_t;
typedef	__int32_t	__intfptr_t;
typedef	__int64_t	__intmax_t;
typedef __int32_t       __intptr_t;

typedef	__int16_t	__int_fast8_t;
typedef	__int16_t	__int_fast16_t;
typedef	__int32_t	__int_fast32_t;
typedef	__int64_t	__int_fast64_t;
typedef	__int16_t	__int_least8_t;
typedef	__int16_t	__int_least16_t;
typedef	__int32_t	__int_least32_t;
typedef	__int64_t	__int_least64_t;
typedef	long __ptrdiff_t;		/* ptr1 - ptr2 */
typedef	__int16_t	__register_t;
typedef	__int32_t	__segsz_t;		/* segment size (in pages) */
typedef	unsigned long	__size_t;		/* sizeof() */
typedef	__int32_t	__ssize_t;		/* byte count or error */
typedef	__int64_t	__time_t;		/* time()... */
typedef	__uint32_t	__uintfptr_t;
typedef	__uint64_t	__uintmax_t;
typedef	__uint32_t	__uintptr_t;

typedef	__uint16_t	__uint_fast8_t;
typedef	__uint16_t	__uint_fast16_t;
typedef	__uint32_t	__uint_fast32_t;
typedef	__uint64_t	__uint_fast64_t;
typedef	__uint16_t	__uint_least8_t;
typedef	__uint16_t	__uint_least16_t;
typedef	__uint32_t	__uint_least32_t;
typedef	__uint64_t	__uint_least64_t;
typedef	__uint16_t	__u_register_t;
typedef	__uint32_t	__vm_offset_t;
typedef	__uint32_t	__vm_paddr_t;
typedef	__uint32_t	__vm_size_t;

typedef	unsigned long ___wchar_t;


/*
 * POSIX target specific _off_t type definition
 */
typedef long int _off_t;

/*
 * Unusual type definitions.
 */
typedef char* __va_list;

#pragma diag_pop


_Pragma("diag_push")
/* This file is required to use types without size and signedness */
_Pragma("CHECK_MISRA(\"-6.3\")")

/*
 * Standard type definitions.
 */
typedef	__int32_t	__blksize_t;	/* file block size */
typedef	__int64_t	__blkcnt_t;	/* file block count */
typedef	__int32_t	__clockid_t;	/* clock_gettime()... */
typedef	__uint32_t	__fflags_t;	/* file flags */
typedef	__uint64_t	__fsblkcnt_t;
typedef	__uint64_t	__fsfilcnt_t;
typedef	__uint32_t	__gid_t;
typedef	__int64_t	__id_t;		/* can hold a gid_t, pid_t, or uid_t */
typedef	__uint64_t	__ino_t;	/* inode number */
typedef	long		__key_t;	/* IPC key (for Sys V IPC) */
typedef	__int32_t	__lwpid_t;	/* Thread ID (a.k.a. LWP) */
typedef	__uint16_t	__mode_t;	/* permissions */
typedef	int		__accmode_t;	/* access permissions */
typedef	int		__nl_item;
typedef	__uint64_t	__nlink_t;	/* link count */
typedef	_off_t	        __off_t;	/* file offset (target-specific)  */
typedef	__int64_t	__off64_t;	/* file offset (always 64-bit)    */
typedef	__int32_t	__pid_t;	/* process [group] */
typedef	__int64_t	__rlim_t;	/* resource limit - intentionally */
					/* signed, because of legacy code */
					/* that uses -1 for RLIM_INFINITY */
typedef	__uint16_t	__sa_family_t;
typedef	__uint32_t	__socklen_t;
typedef	long		__suseconds_t;	/* microseconds (signed) */
typedef	struct __timer	*__timer_t;	/* timer_gettime()... */
typedef	struct __mq	*__mqd_t;	/* mq_open()... */
typedef	__uint32_t	__uid_t;
typedef	unsigned int	__useconds_t;	/* microseconds (unsigned) */
typedef	int		__cpuwhich_t;	/* which parameter for cpuset. */
typedef	int		__cpulevel_t;	/* level parameter for cpuset. */
typedef int		__cpusetid_t;	/* cpuset identifier. */

/*
 * Unusual type definitions.
 */
/*
 * rune_t is declared to be an ``int'' instead of the more natural
 * ``unsigned long'' or ``long''.  Two things are happening here.  It is not
 * unsigned so that EOF (-1) can be naturally assigned to it and used.  Also,
 * it looks like 10646 will be a 31 bit standard.  This means that if your
 * ints cannot hold 32 bits, you will be in trouble.  The reason an int was
 * chosen over a long is that the is*() and to*() routines take ints (says
 * ANSI C), but they use __ct_rune_t instead of int.
 *
 * NOTE: rune_t is not covered by ANSI nor other standards, and should not
 * be instantiated outside of lib/libc/locale.  Use wchar_t.  wint_t and
 * rune_t must be the same type.  Also, wint_t should be able to hold all
 * members of the largest character set plus one extra value (WEOF), and
 * must be at least 16 bits.
 */
typedef	unsigned long	__ct_rune_t;	/* arg type for ctype funcs */

typedef	__ct_rune_t	__rune_t;	/* rune_t (see above) */
typedef	__ct_rune_t	__wint_t;	/* wint_t (see above) */

/* Clang already provides these types as built-ins, but only in C++ mode. */
typedef	__uint_least16_t __char16_t;
typedef	__uint_least32_t __char32_t;
/* In C++11, char16_t and char32_t are built-in types. */

typedef struct {
	long long __max_align1 __attribute__((aligned(__alignof__(long long))));
	long double __max_align2 __attribute__((aligned(__alignof__(long double))));
} __max_align_t;

typedef	__uint64_t	__dev_t;	/* device number */

typedef	__uint32_t	__fixpt_t;	/* fixed point number */

/*
 * mbstate_t is an opaque object to keep conversion state during multibyte
 * stream conversions.
 */

typedef int _Mbstatet;

typedef _Mbstatet __mbstate_t;

typedef __uintmax_t     __rman_res_t;

/*
 * When the following macro is defined, the system uses 64-bit inode numbers.
 * Programs can use this to avoid including <sys/param.h>, with its associated
 * namespace pollution.
 */

_Pragma("diag_pop")


/*****************************************************************************/
/*  _STDINT.H                                                                */
/*                                                                           */
/* Copyright (c) 2019 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/

/*-
 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
 *
 * Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org>
 * Copyright (c) 2001 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Klaus Klein.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD$
 */


#pragma diag_push
/* 19.4 is issued for macros that are defined in terms of other macros. */
#pragma CHECK_MISRA("-19.4")
#pragma CHECK_MISRA("-19.7")
#pragma CHECK_MISRA("-19.13")







/*
 * ISO/IEC 9899:1999
 * 7.18.2.1 Limits of exact-width integer types
 */
/* Minimum values of exact-width signed integer types. */

/* Maximum values of exact-width signed integer types. */

/* Maximum values of exact-width unsigned integer types. */

/*
 * ISO/IEC 9899:1999
 * 7.18.2.2  Limits of minimum-width integer types
 */
/* Minimum values of minimum-width signed integer types. */

/* Maximum values of minimum-width signed integer types. */

/* Maximum values of minimum-width unsigned integer types. */

/*
 * ISO/IEC 9899:1999
 * 7.18.2.3  Limits of fastest minimum-width integer types
 */
/* Minimum values of fastest minimum-width signed integer types. */

/* Maximum values of fastest minimum-width signed integer types. */

/* Maximum values of fastest minimum-width unsigned integer types. */

/*
 * ISO/IEC 9899:1999
 * 7.18.2.4  Limits of integer types capable of holding object pointers
 */

/*
 * ISO/IEC 9899:1999
 * 7.18.2.5  Limits of greatest-width integer types
 */

/*
 * ISO/IEC 9899:1999
 * 7.18.3  Limits of other integer types
 */
/* Limits of ptrdiff_t. */

/* Limits of sig_atomic_t. */

/* Limit of size_t. */

/* Limits of wint_t. */


#pragma diag_pop

/*-
 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
 *
 * Copyright (c) 2011 David E. O'Brien <obrien@FreeBSD.org>
 * Copyright (c) 2001 Mike Barcroft <mike@FreeBSD.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD$
 */



typedef	__int16_t		int16_t;

typedef	__int32_t		int32_t;

typedef	__int64_t		int64_t;


typedef	__uint16_t		uint16_t;

typedef	__uint32_t		uint32_t;

typedef	__uint64_t		uint64_t;

typedef	__intptr_t		intptr_t;
typedef	__uintptr_t		uintptr_t;
typedef	__intmax_t		intmax_t;
typedef	__uintmax_t		uintmax_t;


typedef	__int_least8_t		int_least8_t;
typedef	__int_least16_t		int_least16_t;
typedef	__int_least32_t		int_least32_t;
typedef	__int_least64_t		int_least64_t;

typedef	__uint_least8_t		uint_least8_t;
typedef	__uint_least16_t	uint_least16_t;
typedef	__uint_least32_t	uint_least32_t;
typedef	__uint_least64_t	uint_least64_t;

typedef	__int_fast8_t		int_fast8_t;
typedef	__int_fast16_t		int_fast16_t;
typedef	__int_fast32_t		int_fast32_t;
typedef	__int_fast64_t		int_fast64_t;

typedef	__uint_fast8_t		uint_fast8_t;
typedef	__uint_fast16_t		uint_fast16_t;
typedef	__uint_fast32_t		uint_fast32_t;
typedef	__uint_fast64_t		uint_fast64_t;

_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-10.1\")")
/* GNU and Darwin define this and people seem to think it's portable */
_Pragma("diag_pop")

_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.4\")")
/* Limits of wchar_t. */
_Pragma("diag_pop")

/* ISO/IEC 9899:2011 K.3.4.4 */


_Pragma("diag_pop")

//###########################################################################
//
// FILE:    hw_adc.h
//
// TITLE:   Definitions for the ADC registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the ADC register offsets
//
//*************************************************************************************************



//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCCTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCBURSTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTFLGCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTOVF register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTOVFCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSEL1N2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSEL3N4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCPRICTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSOCSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSOCSEL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCFLG1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCFRC1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCOVF1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCOVFCLR1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC0CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC1CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC2CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC3CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC4CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC5CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC6CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC7CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC8CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC9CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC10CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC11CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC12CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC13CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC14CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC15CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTSTAT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTINTSEL register
//
//*************************************************************************************************
                                             // Enable
                                             // Enable
                                             // Enable
                                             // Enable

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCOSDETECT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCCOUNTER register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCREV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCOFFTRIM register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1CONFIG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1STAMP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1OFFCAL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1TRIPHI register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1TRIPLO register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2CONFIG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2STAMP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2OFFCAL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2TRIPHI register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2TRIPLO register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3CONFIG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3STAMP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3OFFCAL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3TRIPHI register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3TRIPLO register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4CONFIG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4STAMP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4OFFCAL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4TRIPHI register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4TRIPLO register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1RESULT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2RESULT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3RESULT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4RESULT register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:    hw_asysctl.h
//
// TITLE:   Definitions for the ASYSCTL registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the ASYSCTL register offsets
//
//*************************************************************************************************
                                            // inputs. Refer to Pimux diagram for details.
                                            // inputs. Refer to Pimux diagram for details.
                                            // inputs. Refer to Pimux diagram for details.
                                            // inputs. Refer to Pimux diagram for details.


//*************************************************************************************************
//
// The following are defines for the bit fields in the CONFIGLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TSNSCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ANAREFCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the VMONCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPHPMXSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPLPMXSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPHNMXSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPLNMXSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCDACLOOPBACK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AGPIOCTRLA register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:   cpu.h
//
// TITLE:  Useful C28x CPU defines.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************


//
// External reference to the interrupt flag register (IFR) register
//
extern __cregister volatile uint16_t IFR;

//
// External reference to the interrupt enable register (IER) register
//
extern __cregister volatile uint16_t IER;

//
// Define to enable interrupts
//

//
// Define to disable interrupts
//

//
// Define to enable debug events
//

//
// Define to disable debug events
//

//
// Define to allow writes to protected registers
//

//
// Define to disable writes to protected registers
//

//
// Define for emulation stop
//

//
// Define for emulation stop
//

//
// Define for no operation
//

//
// Define for putting processor into a low-power mode
//

//*****************************************************************************
//
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
//
//*****************************************************************************
extern void __eallow(void);
extern void __edis(void);

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   debug.h
//
// TITLE:  Assert definition macro for debug.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API.  This is only used when doing a DEBUG build. It is the
// application's responsibility to define the __error__ function.
//
//*****************************************************************************
extern void __error__(char *filename, uint32_t line);

//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking.  Typically, this
// will be for procedure arguments.
//
//*****************************************************************************


//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************





//*****************************************************************************
//
// Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(),
// ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and
// ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also
// make up the enumerated bit field returned by ADC_getPPBEventStatus().
//
//*****************************************************************************

//*****************************************************************************
//
// Values that can be passed to ADC_forceMultipleSOC() as socMask parameter.
// These values can be OR'd together to trigger multiple SOCs at a time.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to ADC_setPrescaler() as the \e clkPrescale
//! parameter.
//
//*****************************************************************************
typedef enum
{
    ADC_CLK_DIV_1_0 = 0,            //!< ADCCLK = (input clock) / 1.0
    ADC_CLK_DIV_2_0 = 2,            //!< ADCCLK = (input clock) / 2.0
    ADC_CLK_DIV_3_0 = 4,            //!< ADCCLK = (input clock) / 3.0
    ADC_CLK_DIV_4_0 = 6,            //!< ADCCLK = (input clock) / 4.0
    ADC_CLK_DIV_5_0 = 8,            //!< ADCCLK = (input clock) / 5.0
    ADC_CLK_DIV_6_0 = 10,           //!< ADCCLK = (input clock) / 6.0
    ADC_CLK_DIV_7_0 = 12,           //!< ADCCLK = (input clock) / 7.0
    ADC_CLK_DIV_8_0 = 14            //!< ADCCLK = (input clock) / 8.0
} ADC_ClkPrescale;

//*****************************************************************************
//
//! Values that can be passed to ADC_setupSOC() as the \e trigger
//! parameter to specify the event that will trigger a conversion to start.
//! It is also used with ADC_setBurstModeConfig().
//
//*****************************************************************************
typedef enum
{
    ADC_TRIGGER_SW_ONLY     = 0,     //!< Software only
    ADC_TRIGGER_CPU1_TINT0  = 1,     //!< CPU1 Timer 0, TINT0
    ADC_TRIGGER_CPU1_TINT1  = 2,     //!< CPU1 Timer 1, TINT1
    ADC_TRIGGER_CPU1_TINT2  = 3,     //!< CPU1 Timer 2, TINT2
    ADC_TRIGGER_GPIO        = 4,     //!< GPIO, ADCEXTSOC
    ADC_TRIGGER_EPWM1_SOCA  = 5,     //!< ePWM1, ADCSOCA
    ADC_TRIGGER_EPWM1_SOCB  = 6,     //!< ePWM1, ADCSOCB
    ADC_TRIGGER_EPWM2_SOCA  = 7,     //!< ePWM2, ADCSOCA
    ADC_TRIGGER_EPWM2_SOCB  = 8,     //!< ePWM2, ADCSOCB
    ADC_TRIGGER_EPWM3_SOCA  = 9,     //!< ePWM3, ADCSOCA
    ADC_TRIGGER_EPWM3_SOCB  = 10,    //!< ePWM3, ADCSOCB
    ADC_TRIGGER_EPWM4_SOCA  = 11,    //!< ePWM4, ADCSOCA
    ADC_TRIGGER_EPWM4_SOCB  = 12,    //!< ePWM4, ADCSOCB
    ADC_TRIGGER_EPWM5_SOCA  = 13,    //!< ePWM5, ADCSOCA
    ADC_TRIGGER_EPWM5_SOCB  = 14,    //!< ePWM5, ADCSOCB
    ADC_TRIGGER_EPWM6_SOCA  = 15,    //!< ePWM6, ADCSOCA
    ADC_TRIGGER_EPWM6_SOCB  = 16,    //!< ePWM6, ADCSOCB
    ADC_TRIGGER_EPWM7_SOCA  = 17,    //!< ePWM7, ADCSOCA
    ADC_TRIGGER_EPWM7_SOCB  = 18,    //!< ePWM7, ADCSOCB
    ADC_TRIGGER_EPWM8_SOCA  = 19,    //!< ePWM8, ADCSOCA
    ADC_TRIGGER_EPWM8_SOCB  = 20    //!< ePWM8, ADCSOCB
} ADC_Trigger;

//*****************************************************************************
//
//! Values that can be passed to ADC_setupSOC() as the \e channel
//! parameter. This is the input pin on which the signal to be converted is
//! located.
//
//*****************************************************************************
typedef enum
{
    ADC_CH_ADCIN0,               //!< ADCIN0 is converted
    ADC_CH_ADCIN1,               //!< ADCIN1 is converted
    ADC_CH_ADCIN2,               //!< ADCIN2 is converted
    ADC_CH_ADCIN3,               //!< ADCIN3 is converted
    ADC_CH_ADCIN4,               //!< ADCIN4 is converted
    ADC_CH_ADCIN5,               //!< ADCIN5 is converted
    ADC_CH_ADCIN6,               //!< ADCIN6 is converted
    ADC_CH_ADCIN7,               //!< ADCIN7 is converted
    ADC_CH_ADCIN8,               //!< ADCIN8 is converted
    ADC_CH_ADCIN9,               //!< ADCIN9 is converted
    ADC_CH_ADCIN10,              //!< ADCIN10 is converted
    ADC_CH_ADCIN11,              //!< ADCIN11 is converted
    ADC_CH_ADCIN12,              //!< ADCIN12 is converted
    ADC_CH_ADCIN13,              //!< ADCIN13 is converted
    ADC_CH_ADCIN14,              //!< ADCIN14 is converted
    ADC_CH_ADCIN15               //!< ADCIN15 is converted
} ADC_Channel;

//*****************************************************************************
//
//! Values that can be passed to ADC_setInterruptPulseMode() as the
//! \e pulseMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Occurs at the end of the acquisition window
    ADC_PULSE_END_OF_ACQ_WIN = 0x00,
    //! Occurs at the end of the conversion
    ADC_PULSE_END_OF_CONV    = 0x04
} ADC_PulseMode;

//*****************************************************************************
//
//! Values that can be passed to ADC_enableInterrupt(), ADC_disableInterrupt(),
//! and ADC_getInterruptStatus() as the \e adcIntNum parameter.
//
//*****************************************************************************
typedef enum
{
    ADC_INT_NUMBER1,        //!< ADCINT1 Interrupt
    ADC_INT_NUMBER2,        //!< ADCINT2 Interrupt
    ADC_INT_NUMBER3,        //!< ADCINT3 Interrupt
    ADC_INT_NUMBER4         //!< ADCINT4 Interrupt
} ADC_IntNumber;

//*****************************************************************************
//
//! Values that can be passed in as the \e ppbNumber parameter for several
//! functions.
//
//*****************************************************************************
typedef enum
{
    ADC_PPB_NUMBER1,        //!< Post-processing block 1
    ADC_PPB_NUMBER2,        //!< Post-processing block 2
    ADC_PPB_NUMBER3,        //!< Post-processing block 3
    ADC_PPB_NUMBER4         //!< Post-processing block 4
} ADC_PPBNumber;

//*****************************************************************************
//
//! Values that can be passed in as the \e socNumber parameter for several
//! functions. This value identifies the start-of-conversion (SOC) that a
//! function is configuring or accessing. Note that in some cases (for example,
//! ADC_setInterruptSource()) \e socNumber is used to refer to the
//! corresponding end-of-conversion (EOC).
//
//*****************************************************************************
typedef enum
{
    ADC_SOC_NUMBER0,        //!< SOC/EOC number 0
    ADC_SOC_NUMBER1,        //!< SOC/EOC number 1
    ADC_SOC_NUMBER2,        //!< SOC/EOC number 2
    ADC_SOC_NUMBER3,        //!< SOC/EOC number 3
    ADC_SOC_NUMBER4,        //!< SOC/EOC number 4
    ADC_SOC_NUMBER5,        //!< SOC/EOC number 5
    ADC_SOC_NUMBER6,        //!< SOC/EOC number 6
    ADC_SOC_NUMBER7,        //!< SOC/EOC number 7
    ADC_SOC_NUMBER8,        //!< SOC/EOC number 8
    ADC_SOC_NUMBER9,        //!< SOC/EOC number 9
    ADC_SOC_NUMBER10,       //!< SOC/EOC number 10
    ADC_SOC_NUMBER11,       //!< SOC/EOC number 11
    ADC_SOC_NUMBER12,       //!< SOC/EOC number 12
    ADC_SOC_NUMBER13,       //!< SOC/EOC number 13
    ADC_SOC_NUMBER14,       //!< SOC/EOC number 14
    ADC_SOC_NUMBER15        //!< SOC/EOC number 15
} ADC_SOCNumber;

//*****************************************************************************
//
//! Values that can be passed in as the \e trigger parameter for the
//! ADC_setInterruptSOCTrigger() function.
//
//*****************************************************************************
typedef enum
{
    ADC_INT_SOC_TRIGGER_NONE,       //!< No ADCINT will trigger the SOC
    ADC_INT_SOC_TRIGGER_ADCINT1,    //!< ADCINT1 will trigger the SOC
    ADC_INT_SOC_TRIGGER_ADCINT2     //!< ADCINT2 will trigger the SOC
} ADC_IntSOCTrigger;

//*****************************************************************************
//
//! Values that can be passed to ADC_setSOCPriority() as the \e priMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    ADC_PRI_ALL_ROUND_ROBIN,        //!< Round robin mode is used for all
    ADC_PRI_SOC0_HIPRI,             //!< SOC 0 hi pri, others in round robin
    ADC_PRI_THRU_SOC1_HIPRI,        //!< SOC 0-1 hi pri, others in round robin
    ADC_PRI_THRU_SOC2_HIPRI,        //!< SOC 0-2 hi pri, others in round robin
    ADC_PRI_THRU_SOC3_HIPRI,        //!< SOC 0-3 hi pri, others in round robin
    ADC_PRI_THRU_SOC4_HIPRI,        //!< SOC 0-4 hi pri, others in round robin
    ADC_PRI_THRU_SOC5_HIPRI,        //!< SOC 0-5 hi pri, others in round robin
    ADC_PRI_THRU_SOC6_HIPRI,        //!< SOC 0-6 hi pri, others in round robin
    ADC_PRI_THRU_SOC7_HIPRI,        //!< SOC 0-7 hi pri, others in round robin
    ADC_PRI_THRU_SOC8_HIPRI,        //!< SOC 0-8 hi pri, others in round robin
    ADC_PRI_THRU_SOC9_HIPRI,        //!< SOC 0-9 hi pri, others in round robin
    ADC_PRI_THRU_SOC10_HIPRI,       //!< SOC 0-10 hi pri, others in round robin
    ADC_PRI_THRU_SOC11_HIPRI,       //!< SOC 0-11 hi pri, others in round robin
    ADC_PRI_THRU_SOC12_HIPRI,       //!< SOC 0-12 hi pri, others in round robin
    ADC_PRI_THRU_SOC13_HIPRI,       //!< SOC 0-13 hi pri, others in round robin
    ADC_PRI_THRU_SOC14_HIPRI,       //!< SOC 0-14 hi pri, SOC15 in round robin
    ADC_PRI_ALL_HIPRI               //!< All priorities based on SOC number
} ADC_PriorityMode;

//*****************************************************************************
//
//! Values that can be passed to ADC_getTemperatureC(), ADC_getTemperatureK(),
//! ADC_setVREF() and ADC_setOffsetTrimAll() as the \e refMode parameter.
//
//*****************************************************************************
typedef enum
{
    ADC_REFERENCE_INTERNAL,
    ADC_REFERENCE_EXTERNAL
} ADC_ReferenceMode;

//*****************************************************************************
//
//! Values that can be passed to ADC_setVREF() and ADC_setOffsetTrimAll() as the
//! \e refVoltage parameter.
//!
//
//*****************************************************************************
typedef enum
{
    ADC_REFERENCE_3_3V,
    ADC_REFERENCE_2_5V
} ADC_ReferenceVoltage;

//*****************************************************************************
//
//! Values that can be passed to ADC_configOSDetectMode() as the \e modeVal
//! parameter.
//
//*****************************************************************************
typedef enum
{
    ADC_OSDETECT_MODE_DISABLED            = 0x0, //!< Open/Shorts detection cir-
                                                 //!< cuit(O/S DC) is disabled
    ADC_OSDETECT_MODE_VSSA                = 0x1, //!< O/S DC is enabled at zero
                                                 //!< scale
    ADC_OSDETECT_MODE_VDDA                = 0x2, //!< O/S DC is enabled at full
                                                 //!< scale
    ADC_OSDETECT_MODE_5BY12_VDDA          = 0x3, //!< O/S DC is enabled at 5/12
                                                 //!< scale
    ADC_OSDETECT_MODE_7BY12_VDDA          = 0x4, //!< O/S DC is enabled at 7/12
                                                 //!< scale
    ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA = 0x5, //!< O/S DC is enabled at 5K
                                                 //!< pulldown to VSSA
    ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA   = 0x6, //!< O/S DC is enabled at 5K
                                                 //!< pullup to VDDA
    ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA = 0x7  //!< O/S DC is enabled at 7K
                                                 //!< pulldown to VSSA
} ADC_OSDetectMode;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an ADC base address.
//!
//! \param base specifies the ADC module base address.
//!
//! This function determines if a ADC module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Configures the analog-to-digital converter module prescaler.
//!
//! \param base is the base address of the ADC module.
//! \param clkPrescale is the ADC clock prescaler.
//!
//! This function configures the ADC module's ADCCLK.
//!
//! The \e clkPrescale parameter specifies the value by which the input clock
//! is divided to make the ADCCLK.  The clkPrescale value can be specified with
//! any of the following enum values:
//! \b ADC_CLK_DIV_1_0, \b ADC_CLK_DIV_2_0, \b ADC_CLK_DIV_3_0, ...,
//! \b ADC_CLK_DIV_6_0, \b ADC_CLK_DIV_7_0, or \b ADC_CLK_DIV_8_0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the configuration of the ADC module prescaler.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &
                                 ~0xFU) | (uint16_t)clkPrescale;
    __edis();
}

//*****************************************************************************
//
//! Configures a start-of-conversion (SOC) in the ADC.
//!
//! \param base is the base address of the ADC module.
//! \param socNumber is the number of the start-of-conversion.
//! \param trigger the source that will cause the SOC.
//! \param channel is the number associated with the input signal.
//! \param sampleWindow is the acquisition window duration.
//!
//! This function configures the a start-of-conversion (SOC) in the ADC module.
//!
//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number
//! from 0 to 15 specifying which SOC is to be configured on the ADC module
//! specified by \e base.
//!
//! The \e trigger specifies the event that causes the SOC such as software, a
//! timer interrupt, an ePWM event, or an ADC interrupt. It should be a value
//! in the format of \b ADC_TRIGGER_XXXX where XXXX is the event such as
//! \b ADC_TRIGGER_SW_ONLY, \b ADC_TRIGGER_CPU1_TINT0, \b ADC_TRIGGER_GPIO,
//! \b ADC_TRIGGER_EPWM1_SOCA, and so on.
//!
//! The \e channel parameter specifies the channel to be converted. In
//! single-ended mode this is a single pin given by \b ADC_CH_ADCINx where x is
//! the number identifying the pin between 0 and 15 inclusive.
//!
//! The \e sampleWindow parameter is the acquisition window duration in SYSCLK
//! cycles. It should be a value between 1 and 512 cycles inclusive. The
//! selected duration must be at least as long as one ADCCLK cycle. Also, the
//! datasheet will specify a minimum window duration requirement in
//! nanoseconds.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger,
             ADC_Channel channel, uint32_t sampleWindow)
{
    uint32_t ctlRegAddr;

    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Calculate address for the SOC control register.
    //
    ctlRegAddr = base + 0x10U + ((uint32_t)socNumber * 2U);

    //
    // Set the configuration of the specified SOC.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(ctlRegAddr)))) = ((uint32_t)channel << 15U) |
                        ((uint32_t)trigger << 20U) |
                        (sampleWindow - 1U);
    __edis();
}

//*****************************************************************************
//
//! Configures the interrupt SOC trigger of an SOC.
//!
//! \param base is the base address of the ADC module.
//! \param socNumber is the number of the start-of-conversion.
//! \param trigger the interrupt source that will cause the SOC.
//!
//! This function configures the interrupt start-of-conversion trigger in
//! the ADC module.
//!
//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number
//! from 0 to 15 specifying which SOC is to be configured on the ADC module
//! specified by \e base.
//!
//! The \e trigger specifies the interrupt that causes a start of conversion or
//! none. It should be one of the following values.
//!
//! - \b ADC_INT_SOC_TRIGGER_NONE
//! - \b ADC_INT_SOC_TRIGGER_ADCINT1
//! - \b ADC_INT_SOC_TRIGGER_ADCINT2
//!
//! This functionality is useful for creating continuous conversions.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber,
                           ADC_IntSOCTrigger trigger)
{
    uint16_t shiftVal;

    //
    // Check the arguments.
    //
    ;

    //
    // Each SOC has a 2-bit field in this register.
    //
    shiftVal = (uint16_t)socNumber << 1U;

    //
    // Set the configuration of the specified SOC. Not that we're treating
    // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))) = ((*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))) &
                                      ~((uint32_t)0x3U <<
                                        shiftVal)) |
                                     ((uint32_t)trigger << shiftVal);
    __edis();
}

//*****************************************************************************
//
//! Sets the timing of the end-of-conversion pulse
//!
//! \param base is the base address of the ADC module.
//! \param pulseMode is the generation mode of the EOC pulse.
//!
//! This function configures the end-of-conversion (EOC) pulse generated by ADC.
//! This pulse will be generated either at the end of the acquisition window
//! plus a number of SYSCLK cycles configured by ADC_setInterruptCycleOffset()
//! (pass \b ADC_PULSE_END_OF_ACQ_WIN into \e pulseMode) or at the end of the
//! voltage conversion, one cycle prior to the ADC result latching into it's
//! result register (pass \b ADC_PULSE_END_OF_CONV into \e pulseMode).
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the position of the pulse.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                 ~0x4U) | (uint16_t)pulseMode;
    __edis();
}

//*****************************************************************************
//
//! Sets the timing of early interrupt generation.
//!
//! \param base is the base address of the ADC module.
//! \param cycleOffset is the cycles from an SOC falling edge to an early
//! interrupt pulse.
//!
//! This function configures cycle offset between the negative edge of a sample
//! pulse and an early interrupt pulse being generated. This number of cycles
//! is specified with the \e cycleOffset parameter.
//!
//! This function only applies when early interrupt generation is enabled. That
//! means the ADC_setInterruptPulseMode() function \e pulseMode parameter is
//! configured as \b ADC_PULSE_END_OF_ACQ_WIN.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setInterruptCycleOffset(uint32_t base, uint16_t cycleOffset)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the position of the pulse.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6FU)))) = cycleOffset;
    __edis();
}

//*****************************************************************************
//
//! Powers up the analog-to-digital converter core.
//!
//! \param base is the base address of the ADC module.
//!
//! This function powers up the analog circuitry inside the analog core.
//!
//! \note Allow at least a 500us delay before sampling after calling this API.
//! If you enable multiple ADCs, you can delay after they all have begun
//! powering up.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_enableConverter(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that powers up the analog circuitry.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x80U;
    __edis();
}

//*****************************************************************************
//
//! Powers down the analog-to-digital converter module.
//!
//! \param base is the base address of the ADC module.
//!
//! This function powers down the analog circuitry inside the analog core.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_disableConverter(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the bit that powers down the analog circuitry.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x80U;
    __edis();
}

//*****************************************************************************
//
//! Forces a SOC flag to a 1 in the analog-to-digital converter.
//!
//! \param base is the base address of the ADC module.
//! \param socNumber is the number of the start-of-conversion.
//!
//! This function forces the SOC flag associated with the SOC specified by
//! \e socNumber. This initiates a conversion once that SOC is given
//! priority. This software trigger can be used whether or not the SOC has been
//! configured to accept some other specific trigger.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write to the register that will force a 1 to the corresponding SOC flag
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xDU)))) = (1U << (uint16_t)socNumber);
}

//*****************************************************************************
//
//! Forces multiple SOC flags to 1 in the analog-to-digital converter.
//!
//! \param base is the base address of the ADC module.
//! \param socMask is the SOCs to be forced through software
//!
//! This function forces the SOCFRC1 flags associated with the SOCs specified
//! by \e socMask. This initiates a conversion once the desired SOCs are given
//! priority. This software trigger can be used whether or not the SOC has been
//! configured to accept some other specific trigger.
//! Valid values for \e socMask parameter can be any of the individual
//! ADC_FORCE_SOCx values or any of their OR'd combination to trigger multiple
//! SOCs.
//!
//! \note To trigger SOC0, SOC1 and SOC2, value (ADC_FORCE_SOC0 |
//! ADC_FORCE_SOC1 | ADC_FORCE_SOC2) should be passed as socMask.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_forceMultipleSOC(uint32_t base, uint16_t socMask)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write to the register that will force a 1 to desired SOCs
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xDU)))) = socMask;
}

//*****************************************************************************
//
//! Gets the current ADC interrupt status.
//!
//! \param base is the base address of the ADC module.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function returns the interrupt status for the analog-to-digital
//! converter.
//!
//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1,
//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express
//! which of the four interrupts of the ADC module should be cleared.
//!
//! \return \b true if the interrupt flag for the specified interrupt number is
//! set and \b false if it is not.
//
//*****************************************************************************
static inline _Bool
ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the specified ADC interrupt status.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) & (1U << (uint16_t)adcIntNum)) != 0U);
}

//*****************************************************************************
//
//! Clears ADC interrupt sources.
//!
//! \param base is the base address of the ADC module.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function clears the specified ADC interrupt sources so that they no
//! longer assert. If not in continuous mode, this function must be called
//! before any further interrupt pulses may occur.
//!
//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1,
//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express
//! which of the four interrupts of the ADC module should be cleared.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the specified interrupt.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = 1U << (uint16_t)adcIntNum;
}

//*****************************************************************************
//
//! Gets the current ADC interrupt overflow status.
//!
//! \param base is the base address of the ADC module.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function returns the interrupt overflow status for the
//! analog-to-digital converter. An overflow condition is generated
//! irrespective of the continuous mode.
//!
//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1,
//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express
//! which of the four interrupts of the ADC module should be cleared.
//!
//! \return \b true if the interrupt overflow flag for the specified interrupt
//! number is set and \b false if it is not.
//
//*****************************************************************************
static inline _Bool
ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the specified ADC interrupt status.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) & (1U << (uint16_t)adcIntNum)) != 0U);
}

//*****************************************************************************
//
//! Clears ADC interrupt overflow sources.
//!
//! \param base is the base address of the ADC module.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function clears the specified ADC interrupt overflow sources so that
//! they no longer assert. If software tries to clear the overflow in the same
//! cycle that hardware tries to set the overflow, then hardware has priority.
//!
//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1,
//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express
//! which of the four interrupts of the ADC module should be cleared.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the specified interrupt overflow bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = 1U << (uint16_t)adcIntNum;
}

//*****************************************************************************
//
//! Reads the conversion result.
//!
//! \param resultBase is the base address of the ADC results.
//! \param socNumber is the number of the start-of-conversion.
//!
//! This function returns the conversion result that corresponds to the base
//! address passed into \e resultBase and the SOC passed into \e socNumber.
//!
//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number
//! from 0 to 15 specifying which SOC's result is to be read.
//!
//! \note Take care that you are using a base address for the result registers
//! (ADCxRESULT_BASE) and not a base address for the control registers.
//!
//! \return Returns the conversion result.
//
//*****************************************************************************
static inline uint16_t
ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber)
{
    //
    // Check the arguments.
    //
    ;
    //
    // Return the ADC result for the selected SOC.
    //
    return((*((volatile uint16_t *)((uintptr_t)(resultBase + 0x0U + socNumber)))));
}

//*****************************************************************************
//
//! Determines whether the ADC is busy or not.
//!
//! \param base is the base address of the ADC.
//!
//! This function allows the caller to determine whether or not the ADC is
//! busy and can sample another channel.
//!
//! \return Returns \b true if the ADC is sampling or \b false if all
//! samples are complete.
//
//*****************************************************************************
static inline _Bool
ADC_isBusy(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Determine if the ADC is busy.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & 0x2000U) != 0U);
}

//*****************************************************************************
//
//! Set SOC burst mode.
//!
//! \param base is the base address of the ADC.
//! \param trigger the source that will cause the burst conversion sequence.
//! \param burstSize is the number of SOCs converted during a burst sequence.
//!
//! This function configures the burst trigger and burstSize of an ADC module.
//! Burst mode allows a single trigger to walk through the round-robin SOCs one
//! or more at a time. When burst mode is enabled, the trigger selected by the
//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin
//! mode. Instead, the source specified through the \e trigger parameter will
//! cause a burst of \e burstSize conversions to occur.
//!
//! The \e trigger parameter takes the same values as the ADC_setupSOC() API
//! The \e burstSize parameter should be a value between 1 and 16 inclusive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize)
{
    uint16_t regValue;

    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Write the burst mode configuration to the register.
    //
    __eallow();

    regValue = (uint16_t)trigger | ((burstSize - 1U) <<
                                    8U);

    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) &
                                     ~((uint16_t)0x3FU |
                                       0xF00U)) | regValue;

    __edis();
}

//*****************************************************************************
//
//! Enables SOC burst mode.
//!
//! \param base is the base address of the ADC.
//!
//! This function enables SOC burst mode operation of the ADC. Burst mode
//! allows a single trigger to walk through the round-robin SOCs one or more at
//! a time. When burst mode is enabled, the trigger selected by the
//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin
//! mode. Use ADC_setBurstMode() to configure the burst trigger and size.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_enableBurstMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable burst mode.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) |= 0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Disables SOC burst mode.
//!
//! \param base is the base address of the ADC.
//!
//! This function disables SOC burst mode operation of the ADC. SOCs in
//! round-robin mode will be triggered by the trigger configured using the
//! ADC_setupSOC() API.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_disableBurstMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable burst mode.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) &= ~0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Sets the priority mode of the SOCs.
//!
//! \param base is the base address of the ADC.
//! \param priMode is the priority mode of the SOCs.
//!
//! This function sets the priority mode of the SOCs. There are three main
//! modes that can be passed in the \e priMode parameter
//!
//! - All SOCs are in round-robin mode. This means no SOC has an inherent
//! higher priority over another. This is selected by passing in the value
//! \b ADC_PRI_ALL_ROUND_ROBIN.
//! - All priorities are in high priority mode. This means that the priority of
//! the SOC is determined by its SOC number. This option is selected by passing
//! in the value \b ADC_PRI_ALL_HIPRI.
//! - A range of SOCs are assigned high priority, with all others in round
//! robin mode. High priority mode means that an SOC with high priority will
//! interrupt the round robin wheel and insert itself as the next conversion.
//! Passing in the value \b ADC_PRI_SOC0_HIPRI will make SOC0 highest priority,
//! \b ADC_PRI_THRU_SOC1_HIPRI will put SOC0 and SOC 1 in high priority, and so
//! on up to \b ADC_PRI_THRU_SOC14_HIPRI where SOCs 0 through 14 are in high
//! priority.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) &
                                      ~0x1FU) |
                                     (uint16_t)priMode;

    __edis();
}

//*****************************************************************************
//
//! Configures Open/Shorts Detection Circuit Mode.
//!
//! \param base is the base address of the ADC.
//! \param modeVal is the desired open/shorts detection circuit mode.
//!
//! This function configures the open/shorts detection circuit mode of the ADC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_configOSDetectMode(uint32_t base, ADC_OSDetectMode modeVal)
{
    //
    // Configure open/shorts detection circuit mode.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x38U)))) = (((*((volatile uint16_t *)((uintptr_t)(base + 0x38U)))) &
                                     (~0x7U)) | modeVal);
    __edis();
}

//*****************************************************************************
//
//! Configures a post-processing block (PPB) in the ADC.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param socNumber is the number of the start-of-conversion.
//!
//! This function associates a post-processing block with a SOC.
//!
//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to
//! 4 inclusive that identifies a PPB to be configured.  The \e socNumber
//! number is a value \b ADC_SOC_NUMBERX where X is a number from 0 to 15
//! specifying which SOC is to be configured on the ADC module specified by
//! \e base.
//!
//! \note You can have more that one PPB associated with the same SOC, but a
//! PPB can only be configured to correspond to one SOC at a time. Also note
//! that when you have multiple PPBs for the same SOC, the calibration offset
//! that actually gets applied will be that of the PPB with the highest number.
//! Since SOC0 is the default for all PPBs, look out for unintentional
//! overwriting of a lower numbered PPB's offset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U;

    //
    // Write the configuration to the register.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) = ((*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) &
                                ~0xFU) |
                               ((uint16_t)socNumber & 0xFU);
    __edis();
}

//*****************************************************************************
//
//! Enables individual ADC PPB event sources.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param evtFlags is a bit mask of the event sources to be enabled.
//!
//! This function enables the indicated ADC PPB event sources.  This will allow
//! the specified events to propagate through the X-BAR to a pin or to an ePWM
//! module.  The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI,
//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Enable the specified event.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) |= evtFlags << ((uint16_t)ppbNumber * 4U);
    __edis();
}

//*****************************************************************************
//
//! Disables individual ADC PPB event sources.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param evtFlags is a bit mask of the event sources to be enabled.
//!
//! This function disables the indicated ADC PPB event sources.  This will stop
//! the specified events from propagating through the X-BAR to other modules.
//! The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI,
//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Disable the specified event.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) &= ~(evtFlags << ((uint16_t)ppbNumber * 4U));
    __edis();
}

//*****************************************************************************
//
//! Enables individual ADC PPB event interrupt sources.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated ADC PPB interrupt sources.  Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.  The \e intFlags
//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, or
//! \b ADC_EVT_ZERO values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber,
                            uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Enable the specified event interrupts.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x36U)))) |= intFlags << ((uint16_t)ppbNumber * 4U);
    __edis();
}

//*****************************************************************************
//
//! Disables individual ADC PPB event interrupt sources.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param intFlags is a bit mask of the interrupt source to be disabled.
//!
//! This function disables the indicated ADC PPB interrupt sources.  Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.  The \e intFlags
//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, or
//! \b ADC_EVT_ZERO values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber,
                             uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Disable the specified event interrupts.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x36U)))) &= ~(intFlags <<
                                        ((uint16_t)ppbNumber * 4U));
    __edis();
}

//*****************************************************************************
//
//! Gets the current ADC event status.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//!
//! This function returns the event status for the analog-to-digital converter.
//!
//! \return Returns the current event status, enumerated as a bit field of
//! \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, and \b ADC_EVT_ZERO.
//
//*****************************************************************************
static inline uint16_t
ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the event status for the specified post-processing block.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x30U)))) >> ((uint16_t)ppbNumber * 4U)) &
           0x7U);
}

//*****************************************************************************
//
//! Clears ADC event flags.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param evtFlags is a bit mask of the event source to be cleared.
//!
//! This function clears the indicated ADC PPB event flags. After an event
//! occurs this function must be called to allow additional events to be
//! produced. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI,
//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber,
                        uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear the specified event interrupts.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x32U)))) |= evtFlags << ((uint16_t)ppbNumber * 4U);
}

//*****************************************************************************
//
//! Enables cycle-by-cycle clear of ADC PPB event flags.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//!
//! This function enables the automatic cycle-by-cycle clear of ADC PPB event
//! flags. When enabled, the desired PPB event flags are automatically cleared
//! on the next PPBxRESULT load, unless a set condition is also occurring at
//! the same time, in which case the set takes precedence.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_enablePPBEventCBCClear(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U;

    //
    // Set automatic cycle-by-cycle flag clear bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) |= 0x20U;
    __edis();
}

//*****************************************************************************
//
//! Disables cycle-by-cycle clear of ADC PPB event flags.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//!
//! This function disables the cycle-by-cycle clear of ADC PPB event flags. When
//! disabled, the desired PPB event flags are to be cleared explicitly in
//! software inorder to generate next set of interrupts/events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_disablePPBEventCBCClear(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U;

    //
    // Clear automatic cycle-by-cycle flag clear bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) &= ~0x20U;
    __edis();
}

//*****************************************************************************
//
//! Reads the processed conversion result from the PPB.
//!
//! \param resultBase is the base address of the ADC results.
//! \param ppbNumber is the number of the post-processing block.
//!
//! This function returns the processed conversion result that corresponds to
//! the base address passed into \e resultBase and the PPB passed into
//! \e ppbNumber.
//!
//! \note Take care that you are using a base address for the result registers
//! (ADCxRESULT_BASE) and not a base address for the control registers.
//!
//! \return Returns the signed 32-bit conversion result.
//
//*****************************************************************************
static inline int32_t
ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber)
{
    //
    // Check the arguments.
    //
    ;
    //
    // Return the result of selected PPB.
    //
    return((int32_t)(*((volatile uint32_t *)((uintptr_t)(resultBase + 0x10U + (ppbNumber * 2U))))));
}

//*****************************************************************************
//
//! Reads sample delay time stamp from a PPB.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//!
//! This function returns the sample delay time stamp. This delay is the number
//! of system clock cycles between the SOC being triggered and when it began
//! converting.
//!
//! \return Returns the delay time stamp.
//
//*****************************************************************************
static inline uint16_t
ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate delay.
    //
    ppbOffset = ((0x49U - 0x41U) * (uint32_t)ppbNumber) + 0x41U;

    //
    // Return the delay time stamp.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) & 0xFFFU);
}

//*****************************************************************************
//
//! Sets the post processing block offset correction.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param offset is the 10-bit signed value subtracted from ADC the output.
//!
//! This function sets the PPB offset correction value.  This value can be used
//! to digitally remove any system-level offset inherent in the ADCIN circuit
//! before it is stored in the appropriate result register. The \e offset
//! parameter is \b subtracted from the ADC output and is a signed value from
//! -512 to 511 inclusive. For example, when \e offset = 1, ADCRESULT = ADC
//! output - 1. When \e offset = -512, ADCRESULT = ADC output - (-512) or ADC
//! output + 512.
//!
//! Passing a zero in to the \e offset parameter will effectively disable the
//! calculation, allowing the raw ADC result to be passed unchanged into the
//! result register.
//!
//! \note If multiple PPBs are applied to the same SOC, the offset that will be
//! applied will be that of the PPB with the highest number.
//!
//! \return None
//
//*****************************************************************************
static inline void
ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber,
                            int16_t offset)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate offset register.
    //
    ppbOffset = ((0x4AU - 0x42U) * (uint32_t)ppbNumber) + 0x42U;

    //
    // Write the offset amount.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) = ((*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) &
                                ~0x3FFU) |
                               ((uint16_t)offset & 0x3FFU);
    __edis();
}

//*****************************************************************************
//
//! Sets the post processing block reference offset.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param offset is the 16-bit unsigned value subtracted from ADC the output.
//!
//! This function sets the PPB reference offset value. This can be used to
//! either calculate the feedback error or convert a unipolar signal to bipolar
//! by subtracting a reference value. The result will be stored in the
//! appropriate PPB result register which can be read using ADC_readPPBResult().
//!
//! Passing a zero in to the \e offset parameter will effectively disable the
//! calculation and will pass the ADC result to the PPB result register
//! unchanged.
//!
//! \note If in 12-bit mode, you may only pass a 12-bit value into the \e offset
//! parameter.
//!
//! \return None
//
//*****************************************************************************
static inline void
ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber,
                          uint16_t offset)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate offset register.
    //
    ppbOffset = ((0x4BU - 0x43U) * (uint32_t)ppbNumber) + 0x43U;

    //
    // Write the offset amount.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) = offset;
}

//*****************************************************************************
//
//! Enables two's complement capability in the PPB.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//!
//! This function enables two's complement in the post-processing block
//! specified by the \e ppbNumber parameter. When enabled, a two's complement
//! will be performed on the output of the offset subtraction before it is
//! stored in the appropriate PPB result register. In other words, the PPB
//! result will be the reference offset value minus the the ADC result value
//! (ADCPPBxRESULT = ADCSOCxOFFREF - ADCRESULTx).
//!
//! \return None
//
//*****************************************************************************
static inline void
ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U;

    //
    // Enable PPB two's complement.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) |= 0x10U;
    __edis();
}

//*****************************************************************************
//
//! Disables two's complement capability in the PPB.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//!
//! This function disables two's complement in the post-processing block
//! specified by the \e ppbNumber parameter. When disabled, a two's complement
//! will \b NOT be performed on the output of the offset subtraction before it
//! is stored in the appropriate PPB result register. In other words, the PPB
//! result will be the ADC result value minus the reference offset value
//! (ADCPPBxRESULT = ADCRESULTx - ADCSOCxOFFREF).
//!
//! \return None
//
//*****************************************************************************
static inline void
ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
{
    uint32_t ppbOffset;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the offset to the appropriate PPB configuration register.
    //
    ppbOffset = ((0x48U - 0x40U) * (uint32_t)ppbNumber) + 0x40U;

    //
    // Disable PPB two's complement.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + ppbOffset)))) &= ~0x10U;
    __edis();
}

//*****************************************************************************
//
//! Enables an ADC interrupt source.
//!
//! \param base is the base address of the ADC module.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function enables the indicated ADC interrupt source.  Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2,
//! \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express which of the four
//! interrupts of the ADC module should be enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;

    //
    // Check the arguments.
    //
    ;

    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1);
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;

    //
    // Enable the specified ADC interrupt.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(intRegAddr)))) |= 0x20U << shiftVal;

    __edis();
}

//*****************************************************************************
//
//! Disables an ADC interrupt source.
//!
//! \param base is the base address of the ADC module.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function disables the indicated ADC interrupt source.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt. Disabled sources have no effect on the processor.
//!
//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2,
//! \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express which of the four
//! interrupts of the ADC module should be disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;

    //
    // Check the arguments.
    //
    ;

    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1);
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;

    //
    // Disable the specified ADC interrupt.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(intRegAddr)))) &= ~(0x20U << shiftVal);

    __edis();
}

//*****************************************************************************
//
//! Sets the source EOC for an analog-to-digital converter interrupt.
//!
//! \param base is the base address of the ADC module.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//! \param socNumber is the number of the start-of-conversion.
//!
//! This function sets which conversion is the source of an ADC interrupt.
//!
//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number
//! from 0 to 15 specifying which EOC is to be configured on the ADC module
//! specified by \e base.
//!
//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2,
//! \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express which of the four
//! interrupts of the ADC module is being configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum,
                       ADC_SOCNumber socNumber)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;

    //
    // Check the arguments.
    //
    ;

    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1);
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;

    //
    // Set the specified ADC interrupt source.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(intRegAddr)))) =
        ((*((volatile uint16_t *)((uintptr_t)(intRegAddr)))) & ~(0xFU << shiftVal)) |
        ((uint16_t)socNumber << shiftVal);

    __edis();
}

//*****************************************************************************
//
//! Enables continuous mode for an ADC interrupt.
//!
//! \param base is the base address of the ADC.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function enables continuous mode for the ADC interrupt passed into
//! \e adcIntNum. This means that pulses will be generated for the specified
//! ADC interrupt whenever an EOC pulse is generated irrespective of whether or
//! not the flag bit is set.
//!
//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2,
//! \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express which of the four
//! interrupts of the ADC module is being configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;

    //
    // Check the arguments.
    //
    ;

    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1);
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;

    //
    // Enable continuous mode for the specified ADC interrupt.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(intRegAddr)))) |= 0x40U << shiftVal;

    __edis();
}

//*****************************************************************************
//
//! Disables continuous mode for an ADC interrupt.
//!
//! \param base is the base address of the ADC.
//! \param adcIntNum is interrupt number within the ADC wrapper.
//!
//! This function disables continuous mode for the ADC interrupt passed into
//! \e adcIntNum. This means that pulses will not be generated for the
//! specified ADC interrupt until the corresponding interrupt flag for the
//! previous interrupt occurrence has been cleared using
//! ADC_clearInterruptStatus().
//!
//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, \b ADC_INT_NUMBER2,
//! \b ADC_INT_NUMBER3, or \b ADC_INT_NUMBER4 to express which of the four
//! interrupts of the ADC module is being configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
{
    uint32_t intRegAddr;
    uint16_t shiftVal;

    //
    // Check the arguments.
    //
    ;

    //
    // Each INTSEL register manages two interrupts. If the interrupt number is
    // even, we'll be accessing the upper byte and will need to shift.
    //
    intRegAddr = base + 0x7U + ((uint32_t)adcIntNum >> 1);
    shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;

    //
    // Disable continuous mode for the specified ADC interrupt.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(intRegAddr)))) &= ~(0x40U << shiftVal);

    __edis();
}

//*****************************************************************************
//
//! Converts temperature from sensor reading to degrees C
//!
//! \param tempResult is the raw ADC A conversion result from the temp sensor.
//! \param vref is the reference voltage being used (for example 3.3 for 3.3V).
//! \param refMode is the reference mode being used (\b ADC_REFERENCE_INTERNAL
//!        or \b ADC_REFERENCE_EXTERNAL).
//!
//! This function converts temperature from temp sensor reading to degrees C.
//! Temp sensor values in production test are derived with 2.5V reference.
//! The \b vref argument in the function is used to scale the temp sensor
//! reading accordingly if temp sensor value is read at a different VREF
//! setting.
//!
//! \return Returns the temperature sensor reading converted to degrees C.
//
//*****************************************************************************
static inline int16_t
ADC_getTemperatureC(uint16_t tempResult, ADC_ReferenceMode refMode,
                        float32_t vref)
{
    float32_t temp;

    //
    // Read temp sensor slope and offset locations from OTP and convert
    //
    temp = (float32_t)tempResult * (vref / 2.5F);
    if (refMode == ADC_REFERENCE_INTERNAL)
    {
        return((int16_t)((((int32_t)temp - (*(int16_t *)((uintptr_t)0x701CB))) * 4096) /
                         (*(int16_t *)((uintptr_t)0x701CA))));
    }
    else
    {
        return((int16_t)((((int32_t)temp - (*(int16_t *)((uintptr_t)0x701C9))) * 4096) /
                         (*(int16_t *)((uintptr_t)0x701C8))));
    }
}

//*****************************************************************************
//
//! Converts temperature from sensor reading to degrees K
//!
//! \param tempResult is the raw ADC A conversion result from the temp sensor.
//! \param vref is the reference voltage being used (for example 3.3 for 3.3V).
//!
//! This function converts temperature from temp sensor reading to degrees K.
//! Temp sensor values in production test are derived with 2.5V reference.
//! The \b vref argument in the function is used to scale the temp sensor
//! reading accordingly if temp sensor value is read at a different VREF
//! setting.
//!
//! \return Returns the temperature sensor reading converted to degrees K.
//
//*****************************************************************************
static inline int16_t
ADC_getTemperatureK(uint16_t tempResult,ADC_ReferenceMode refMode,
                        float32_t vref)
{
    float32_t temp;

    //
    // Read temp sensor slope and offset locations from OTP and convert
    //
    temp = (float32_t)tempResult * (vref / 2.5F);
    if (refMode == ADC_REFERENCE_INTERNAL)
    {
        return((int16_t)(((((int32_t)temp - (*(int16_t *)((uintptr_t)0x701CB))) * 4096) /
                         (*(int16_t *)((uintptr_t)0x701CA))) + 273));
    }
    else
    {
        return((int16_t)(((((int32_t)temp - (*(int16_t *)((uintptr_t)0x701C9))) * 4096) /
                         (*(int16_t *)((uintptr_t)0x701C8))) + 273));
    }
}
//*****************************************************************************
//
//! Configures the ADC module's reference mode and offset trim
//!
//! \param base is the base address of the ADC module.
//! \param refMode is the reference mode being used (\b ADC_REFERENCE_INTERNAL
//!        or \b ADC_REFERENCE_EXTERNAL).
//! \param refVoltage is the reference voltage being used
//!        (\b ADC_REFERENCE_2_5V or \b ADC_REFERENCE_3_3V). This is ignored
//!        when the reference mode is external.
//!
//! This function configures the ADC module's reference mode and loads the
//! corresponding offset trims.
//!
//! \note In this device, the bandgaps are common for all the ADC instances,
//! hence common Vref configuration needs to be done for all the ADCs. This
//! API configures same Vref configuration for all the supported ADCs in the
//! device.
//!
//! \note When the \e refMode parameter is \b ADC_REFERENCE_EXTERNAL, the value
//! of the \e refVoltage parameter has no effect on the operation of the ADC.
//!
//! \return None.
//
//*****************************************************************************
extern void
ADC_setVREF(uint32_t base, ADC_ReferenceMode refMode,
            ADC_ReferenceVoltage refVoltage);

//*****************************************************************************
//
//! Configures the offset trim for all the ADC instances in a device
//!
//! \param refMode is the reference mode being used (\b ADC_REFERENCE_INTERNAL
//!        or \b ADC_REFERENCE_EXTERNAL).
//! \param refVoltage is the reference voltage being used
//!        (\b ADC_REFERENCE_2_5V or \b ADC_REFERENCE_3_3V). This is ignored
//!        when the reference mode is external.
//!
//! This function loads the offset trims of all the ADC instances available in
//! a device.
//!
//! \note When the \e refMode parameter is \b ADC_REFERENCE_EXTERNAL, the value
//! of the \e refVoltage parameter has no effect on the operation of the ADC.
//!
//! \return None.
//
//*****************************************************************************
extern void
ADC_setOffsetTrimAll(ADC_ReferenceMode refMode,
                ADC_ReferenceVoltage refVoltage);

//*****************************************************************************
//
//! Configures the offset trim for the desired ADC instance
//!
//! \param base is the base address of the ADC module.
//!
//! This function loads the offset trims for the desired ADC instance.
//!
//! \return None.
//
//*****************************************************************************
extern void
ADC_setOffsetTrim(uint32_t base);

//*****************************************************************************
//
//! Configures the INL trim for the desired ADC instance
//!
//! \param base is the base address of the ADC module.
//!
//! This function loads the INL trims for the desired ADC instance.
//!
//! \return None.
//
//*****************************************************************************
extern void
ADC_setINLTrim(uint32_t base);

//*****************************************************************************
//
//! Sets the windowed trip limits for a PPB.
//!
//! \param base is the base address of the ADC module.
//! \param ppbNumber is the number of the post-processing block.
//! \param tripHiLimit is the value is the digital comparator trip high limit.
//! \param tripLoLimit is the value is the digital comparator trip low limit.
//!
//! This function sets the windowed trip limits for a PPB. These values set
//! the digital comparator so that when one of the values is exceeded, either a
//! high or low trip event will occur.
//!
//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to
//! 4 inclusive that identifies a PPB to be configured.
//!
//! If using 16-bit mode, you may pass a 17-bit number into the \e tripHiLimit
//! and \e tripLoLimit parameters where the 17th bit is the sign bit (that is
//! a value from -65536 and 65535). In 12-bit mode, only bits 12:0 will be
//! compared against bits 12:0 of the PPB result.
//!
//!
//! \return None.
//
//*****************************************************************************
extern void
ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber,
                     int32_t tripHiLimit, int32_t tripLoLimit);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   aes.h
//
// TITLE:  Driver for the AES module.
//
//###########################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************


//*****************************************************************************
//
//! \addtogroup aes_api AES
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE:   interrupt.h
//
// TITLE:  C28x Interrupt (PIE) driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************


//*****************************************************************************
//
//! \addtogroup interrupt_api Interrupt
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:   hw_ints.h
//
// TITLE:  Definitions of interrupt numbers for use with interrupt.c.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// PIE Interrupt Numbers
//
// 0x00FF = PIE Table Row #
// 0xFF00 = PIE Table Column #
// 0xFFFF0000 = PIE Vector ID
//
//*****************************************************************************


//###########################################################################
//
// FILE:    hw_pie.h
//
// TITLE:   Definitions for the PIE registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the PIE register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the PIECTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEACK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER5 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR5 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER6 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR6 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER7 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR7 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER8 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR8 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER9 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR9 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER10 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR10 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER11 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR11 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER12 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR12 register
//
//*************************************************************************************************




//*****************************************************************************
//
// The following are values that can be passed to the Interrupt_enableInCPU()
// and Interrupt_disableInCPU() functions as the cpuInterrupt parameter.
//
//*****************************************************************************

//*****************************************************************************
//
// The following are values that can be passed to the Interrupt_clearACKGroup()
// function as the group parameter.
//
//*****************************************************************************

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler.  The Interrupt_initVectorTable()
//! function sets all vectors to this function.  Also, when an interrupt is
//! unregistered using the Interrupt_unregister() function, this handler takes
//! its place.  This should never be called during normal operation.
//!
//! The ESTOP0 statement is for debug purposes only. Remove and replace with an
//! appropriate error handling routine for your program.
//!
//! \return None.
//
//*****************************************************************************
static void Interrupt_defaultHandler(void)
{
    uint16_t pieVect;
    uint16_t vectID;

    //
    // Calculate the vector ID. If the vector is in the lower PIE, it's the
    // offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT)
    // divided by two.
    //
    pieVect = (*((volatile uint16_t *)((uintptr_t)(0x00000CE0U + 0x0U))));
    vectID = (pieVect & 0xFEU) >> 1U;

    //
    // If the vector is in the upper PIE, the vector ID is 128 or higher.
    //
    if(pieVect >= 0x0E00U)
    {
        vectID += 128U;
    }

    //
    // Something has gone wrong. An interrupt without a proper registered
    // handler function has occurred. To help you debug the issue, local
    // variable vectID contains the vector ID of the interrupt that occurred.
    //
    __asm(" ESTOP0");
    for(;;)
    {
        ;
    }
}

//*****************************************************************************
//
//! \internal
//! The default illegal instruction trap interrupt handler.
//!
//! This is the default interrupt handler for an illegal instruction trap
//! (ITRAP).  The Interrupt_initVectorTable() function sets the appropriate
//! vector to this function.  This should never be called during normal
//! operation.
//!
//! The ESTOP0 statement is for debug purposes only.  Remove and replace with
//! an appropriate error handling routine for your program.
//!
//! \return None.
//
//*****************************************************************************
static void Interrupt_illegalOperationHandler(void)
{
    //
    // Something has gone wrong.  The CPU has tried to execute an illegal
    // instruction, generating an illegal instruction trap (ITRAP).
    //
    __asm(" ESTOP0");
    for(;;)
    {
        ;
    }
}

//*****************************************************************************
//
//! \internal
//! The default non-maskable interrupt handler.
//!
//! This is the default interrupt handler for a non-maskable interrupt (NMI).
//! The Interrupt_initVectorTable() function sets the appropriate vector to
//! this function.  This should never be called during normal operation.
//!
//! The ESTOP0 statement is for debug purposes only. Remove and replace with an
//! appropriate error handling routine for your program.
//!
//! \return None.
//
//*****************************************************************************
static void Interrupt_nmiHandler(void)
{
    //
    // A non-maskable interrupt has occurred, indicating that a hardware error
    // has occurred in the system.  You can use SysCtl_getNMIFlagStatus() to
    // to read the NMIFLG register and determine what caused the NMI.
    //
    __asm(" ESTOP0");
    for(;;)
    {
        ;
    }
}

//*****************************************************************************
//
//! Allows the CPU to process interrupts.
//!
//! This function clears the global interrupt mask bit (INTM) in the CPU,
//! allowing the processor to respond to interrupts.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
static inline _Bool
Interrupt_enableMaster(void)
{
    //
    // Enable processor interrupts.
    //
    return(((__enable_interrupts() & 0x1U) != 0U) ? 1 : 0);
}

//*****************************************************************************
//
//! Stops the CPU from processing interrupts.
//!
//! This function sets the global interrupt mask bit (INTM) in the CPU,
//! preventing the processor from receiving maskable interrupts.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
static inline _Bool
Interrupt_disableMaster(void)
{
    //
    // Disable processor interrupts.
    //
    return(((__disable_interrupts() & 0x1U) != 0U) ? 1 : 0);
}

//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param interruptNumber specifies the interrupt in question.
//! \param handler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor.  When the interrupt occurs,
//! if it is enabled (via Interrupt_enable()), the handler function will be
//! called in interrupt context.  Since the handler function can preempt other
//! code, care must be taken to protect memory or peripherals that are accessed
//! by the handler and other non-handler code.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \note This function assumes that the PIE has been enabled. See
//! Interrupt_initModule().
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_register(uint32_t interruptNumber, void (*handler)(void))
{
    uint32_t address;

    //
    // Calculate appropriate address for the interrupt number
    //
    address = (uint32_t)0x00000D00U +
              (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U);

    //
    // Copy ISR address into PIE table
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(address)))) = (uint32_t)handler;
    __edis();
}

//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param interruptNumber specifies the interrupt in question.
//!
//! This function is used to indicate that a default handler
//! Interrupt_defaultHandler() should be called when the given interrupt is
//! asserted to the processor.  Call Interrupt_disable() to disable
//! the interrupt before calling this function.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \sa Interrupt_register() for important information about registering
//! interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_unregister(uint32_t interruptNumber)
{
    uint32_t address;

    //
    // Calculate appropriate address for the interrupt number
    //
    address = (uint32_t)0x00000D00U +
              (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U);

    //
    // Copy default ISR address into PIE table
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(address)))) = (uint32_t)Interrupt_defaultHandler;
    __edis();
}

//*****************************************************************************
//
//! Enables CPU interrupt channels
//!
//! \param cpuInterrupt specifies the CPU interrupts to be enabled.
//!
//! This function enables the specified interrupts in the CPU. The
//! \e cpuInterrupt parameter is a logical OR of the values
//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14,
//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT.
//!
//! \note Note that interrupts 1-12 correspond to the PIE groups with those
//! same numbers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_enableInCPU(uint16_t cpuInterrupt)
{
    //
    // Set the interrupt bits in the CPU.
    //
    IER |= cpuInterrupt;
}

//*****************************************************************************
//
//! Disables CPU interrupt channels
//!
//! \param cpuInterrupt specifies the CPU interrupts to be disabled.
//!
//! This function disables the specified interrupts in the CPU. The
//! \e cpuInterrupt parameter is a logical OR of the values
//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14,
//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT.
//!
//! \note Note that interrupts 1-12 correspond to the PIE groups with those
//! same numbers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_disableInCPU(uint16_t cpuInterrupt)
{
    //
    // Clear the interrupt bits in the CPU.
    //
    IER &= ~cpuInterrupt;
}

//*****************************************************************************
//
//! Acknowledges PIE Interrupt Group
//!
//! \param group specifies the interrupt group to be acknowledged.
//!
//! The specified interrupt group is acknowledged and clears any interrupt
//! flag within that respective group.
//!
//! The \e group parameter must be a logical OR of the following:
//! \b INTERRUPT_ACK_GROUP1, \b INTERRUPT_ACK_GROUP2, \b INTERRUPT_ACK_GROUP3
//! \b INTERRUPT_ACK_GROUP4, \b INTERRUPT_ACK_GROUP5, \b INTERRUPT_ACK_GROUP6
//! \b INTERRUPT_ACK_GROUP7, \b INTERRUPT_ACK_GROUP8, \b INTERRUPT_ACK_GROUP9
//! \b INTERRUPT_ACK_GROUP10, \b INTERRUPT_ACK_GROUP11,
//! \b INTERRUPT_ACK_GROUP12.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_clearACKGroup(uint16_t group)
{
    //
    // Set interrupt group acknowledge bits
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00000CE0U + 0x1U)))) = group;
}

//*****************************************************************************
//
//! Enables the PIE block.
//!
//! This function enables the vector fetching for the peripheral interrupts by
//! enabling the PIE block.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_enablePIE(void)
{
    (*((volatile uint16_t *)((uintptr_t)(0x00000CE0U + 0x0U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Disables the PIE block.
//!
//! This function disables the vector fetching for the peripheral interrupts by
//! disabling the PIE block. PIEACK, PIEIFR, and PIEIER registers can be
//! accessed even when the PIE block is disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_disablePIE(void)
{
    (*((volatile uint16_t *)((uintptr_t)(0x00000CE0U + 0x0U)))) &= ~0x1U;
}

//*****************************************************************************
//
//! Initializes the PIE control registers by setting them to a known state.
//!
//! This function initializes the PIE control registers. After globally
//! disabling interrupts and enabling the PIE, it clears all of the PIE
//! interrupt enable bits and interrupt flags.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_initModule(void);

//*****************************************************************************
//
//! Initializes the PIE vector table by setting all vectors to a default
//! handler function.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_initVectorTable(void);

//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller.  Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_enable(uint32_t interruptNumber);

//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller.  Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_disable(uint32_t interruptNumber);

//*****************************************************************************
//
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
//
//*****************************************************************************
extern uint16_t __disable_interrupts(void);
extern uint16_t __enable_interrupts(void);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************


//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_aes.h
//
// TITLE:   Definitions for the AES registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the AES register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_CTRL register
//
//*************************************************************************************************
                                              // Enable
                                              // operations

//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_SYSCONFIG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_SYSSTATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_IRQSTATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_IRQENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_DIRTY_BITS register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:    hw_aes_ss.h
//
// TITLE:   Definitions for the AES_SS registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the AES_SS register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_GLB_INT_FLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AES_GLB_INT_CLR register
//
//*************************************************************************************************
                                                    // Interrupt




//*****************************************************************************
//
// Interrupt flags for use with AES_enableInterrupt(), AES_disableInterrupt(),
// AES_clearInterruptStatus() & AES_getInterruptStatus() functions.
//
//*****************************************************************************

//*****************************************************************************
//
// Mask to specify AES-core related interrupts. It is the logical OR of all the
// AES only interrupts.
//
//*****************************************************************************

//*****************************************************************************
//
// Defines that can be used for enabling and disabling DMA requests in the
// AES_enableDMARequest() and AES_disableDMARequest() functions.
//
//*****************************************************************************

//*****************************************************************************
//
// Mask to specify all the possible DMA requests. It is the logical OR
// of all the individual DMA requests..
//
//*****************************************************************************

//*****************************************************************************
//
// Define to specify the mask for the AES configurations related fields.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to AES_configureModule() as the \e config
//! parameter's \e direction member.
//
//*****************************************************************************
typedef enum
{
    AES_DIRECTION_DECRYPT  = 0x00000000U, //!< Select Decryption Mode
    AES_DIRECTION_ENCRYPT  = 0x00000004U  //!< Select Encryption Mode
} AES_Direction;

//*****************************************************************************
//
//! Values that can be passed to AES_configureModule() as the \e config
//! parameter's \e keySize member.
//
//*****************************************************************************
typedef enum
{
    AES_KEY_SIZE_128BIT    = 0x00000008U, //!< Select 128-bit key
    AES_KEY_SIZE_192BIT    = 0x00000010U, //!< Select 192-bit key
    AES_KEY_SIZE_256BIT    = 0x00000018U  //!< Select 256-bit key
} AES_KeySize;

//*****************************************************************************
//
//! Values that can be passed to AES_configureModule() as the \e config
//! parameter's \e opMode member.
//
//*****************************************************************************
typedef enum
{
    AES_OPMODE_ECB             = 0x00000000U, //!< Select ECB mode
    AES_OPMODE_CBC             = 0x00000020U, //!< Select CBC mode
    AES_OPMODE_CTR             = 0x00000040U, //!< Select CTR mode
    AES_OPMODE_ICM             = 0x00000200U, //!< Select ICM mode
    AES_OPMODE_CFB             = 0x00000400U, //!< Select CFB mode
    AES_OPMODE_XTS_TWEAKJL     = 0x00000800U, //!< Select XTS TWEAKJL mode
    AES_OPMODE_XTS_K2NJL       = 0x00001000U, //!< Select XTS K2IJL mode
    AES_OPMODE_XTS_K2NLJ0      = 0x00001800U, //!< Select XTS K2ILJ0 mode
    AES_OPMODE_F8              = 0x00002000U, //!< Select F8 mode
    AES_OPMODE_F9              = 0x20004000U, //!< Select F9 mode
    AES_OPMODE_CBCMAC          = 0x20008000U, //!< Select CBC-MAC mode
    AES_OPMODE_GCM_HLY0ZERO    = 0x20010000U, //!< Select GCM HLY0ZERO mode
    AES_OPMODE_GCM_HLY0CALC    = 0x20020040U, //!< Select GCM HLY0CALC mode
    AES_OPMODE_GCM_HY0CALC     = 0x20030040U, //!< Select GCM HY0CALC mode
    AES_OPMODE_CCM             = 0x20040040U  //!< Select CCM mode
} AES_OpMode;

//*****************************************************************************
//
//! Values that can be passed to AES_configureModule() as the \e config
//! parameter's \e ctrWidth member.
//
//*****************************************************************************
typedef enum
{
    AES_CTR_WIDTH_32BIT     = 0x00000000U, //!< Select 32-bit counter
    AES_CTR_WIDTH_64BIT     = 0x00000080U, //!< Select 64-bit counter
    AES_CTR_WIDTH_96BIT     = 0x00000100U, //!< Select 96-bit counter
    AES_CTR_WIDTH_128BIT    = 0x00000180U  //!< Select 128-bit counter
} AES_CounterWidth;

//*****************************************************************************
//
//! Values that can be passed to AES_configureModule() as the \e config
//! parameter's \e ccmLenWidth member.
//
//*****************************************************************************
typedef enum
{
    AES_CCM_L_1     = 0x00000000U, //!< CCM Length width = 1 byte
    AES_CCM_L_2     = 0x00080000U, //!< CCM Length width = 2 bytes
    AES_CCM_L_4     = 0x00180000U, //!< CCM Length width = 4 bytes
    AES_CCM_L_8     = 0x00380000U  //!< CCM Length width = 8 bytes
} AES_CCMLenWidth;

//*****************************************************************************
//
//! Values that can be passed to AES_configureModule() as the \e config
//! parameter's \e ccmAuthLenWidth member.
//
//*****************************************************************************
typedef enum
{
    AES_CCM_M_0      = 0x00000000U, //!< CCM Auth Length width at reset
    AES_CCM_M_4      = 0x00400000U, //!< CCM Auth Length width = 4 bytes
    AES_CCM_M_6      = 0x00800000U, //!< CCM Auth Length width = 6 bytes
    AES_CCM_M_8      = 0x00C00000U, //!< CCM Auth Length width = 8 bytes
    AES_CCM_M_10     = 0x01000000U, //!< CCM Auth Length width = 10 bytes
    AES_CCM_M_12     = 0x01400000U, //!< CCM Auth Length width = 12 bytes
    AES_CCM_M_14     = 0x01800000U, //!< CCM Auth Length width = 14 bytes
    AES_CCM_M_16     = 0x01C00000U  //!< CCM Auth Length width = 16 bytes
} AES_CCMAuthLenWidth;

//*****************************************************************************
//
//! Values that can be passed to AES_configureModule() as the \e config
//! parameter.
//
//*****************************************************************************
typedef struct
{
    AES_Direction       direction;        //!< AES Direction Mode
    AES_KeySize         keySize;          //!< AES Key Size
    AES_OpMode          opMode;           //!< AES Mode
    AES_CounterWidth    ctrWidth;         //!< Counter Width (for CTR Mode)
    AES_CCMLenWidth     ccmLenWidth;      //!< Length Width (for CCM Mode)
    AES_CCMAuthLenWidth ccmAuthLenWidth;  //!< Auth Length Width (for CCM Mode)
} AES_ConfigParams;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks the AES module base address.
//!
//! \param base is the base address of the AES instance used.
//!
//! This function determines if AES module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! \internal
//! Checks AES module wrapper base address.
//!
//! \param configBase is the base address of the used AES wrapper instance.
//!
//! This function determines if AES wrapper base address is valid.
//!
//! \return Returns \b true if the wrapper address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Resets the AES module.
//!
//! \param base is the base address of the AES module.
//!
//! This function performs a soft-reset of the AES module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_performSoftReset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Trigger the reset.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x42U)) |= 0x2U;

    //
    // Wait for the reset to finish.
    //
    while((__byte_peripheral_32((uint32_t *)(base + 0x44U)) &
            0x1U) != 0x1U)
    {
    }
}

//*****************************************************************************
//
//! Used to set the write crypto data length in the AES module.
//!
//! \param base is the base address of the AES module.
//! \param length is the crypto data length in bytes.
//!
//! This function stores the cryptographic data length in blocks for all modes.
//! Data lengths up to (2^61 - 1) bytes are allowed.  For GCM, any value up
//! to (2^36 - 32) bytes are allowed because a 32-bit block counter is used.
//! For basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the
//! length field, indicating that the length is infinite.
//!
//! When this function is called, the engine is triggered to start using
//! this context.
//!
//! \note This length does not include the authentication-only data used in
//! some modes.  Use the AES_setAuthDataLength() function to specify the
//! authentication data length.
//!
//! \return None
//
//*****************************************************************************
static inline void
AES_setDataLength(uint32_t base, uint64_t length)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the length register by shifting the 64-bit length.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x2AU)) = (uint32_t)(length);
    __byte_peripheral_32((uint32_t *)(base + 0x2CU)) = (uint32_t)(length >> 32U);
}

//*****************************************************************************
//
//! Sets the authentication data length in the AES module.
//!
//! \param base is the base address of the AES module.
//! \param authLength is the authentication data length in bytes.
//!
//! This function is only used to write the authentication data length in the
//! combined modes (GCM or CCM) and XTS mode.  Supported AAD lengths for CCM
//! are from 0 to (2^16 - 2^8) bytes.  For GCM, any value up to (2^32 - 1) can
//! be used.  For XTS mode, this register is used to load j.  Loading of j is
//! only required if j != 0.  j represents the sequential number of the 128-bit
//! blocks inside the data unit.  Consequently, j must be multiplied by 16
//! before it is passed to this function, thereby placing the block number in
//! bits [31:4] of the register.
//!
//! When this function is called, the engine is triggered to start using
//! this context for GCM and CCM.
//!
//! \return None
//
//*****************************************************************************
static inline void
AES_setAuthDataLength(uint32_t base, uint32_t authLength)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the length into the register.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x2EU)) = authLength;
}

//*****************************************************************************
//
//! Enables AES core interrupts.
//!
//! \param base is the base address of the AES module.
//! \param intFlags is a bit mask of the interrupt sources to enable.
//!
//! This function enables the core interrupts in the AES module. The
//! \e intFlags parameter is the logical OR of any of the following:
//!
//! - \b AES_INT_CONTEXT_IN      - Context interrupt
//! - \b AES_INT_CONTEXT_OUT     - Authentication tag (and IV) interrupt
//! - \b AES_INT_DATA_IN         - Data input interrupt
//! - \b AES_INT_DATA_OUT        - Data output interrupt
//!
//! \note Interrupts that have been previously been enabled are not disabled
//! when this function is called.
//!
//! \sa AES_enableGlobalInterrupt() to enable global interrupt at wrapper level.
//! Global interrupt needs to be enabled along with core level interrupts to
//! enable interrupts at module level.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_enableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Enable the Interrupts.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x48U)) |= (intFlags & (0x00000001U | 0x00000008U | 0x00000002U | 0x00000004U));
}

//*****************************************************************************
//
//! Disables AES core interrupts.
//!
//! \param base is the base address of the AES module.
//! \param intFlags is a bit mask of the interrupt sources to disable.
//!
//! This function disables the core interrupt sources in the AES module. The
//! \e intFlags parameter is the logical OR of any of the following:
//!
//! - \b AES_INT_CONTEXT_IN      - Context interrupt
//! - \b AES_INT_CONTEXT_OUT     - Authentication tag (and IV) interrupt
//! - \b AES_INT_DATA_IN         - Data input interrupt
//! - \b AES_INT_DATA_OUT        - Data output interrupt
//!
//! \sa AES_disableGlobalInterrupt() to disable global interrupt at wrapper
//! level.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_disableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Disable the Interrupts.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x48U)) &= ~(intFlags & (0x00000001U | 0x00000008U | 0x00000002U | 0x00000004U));
}

//*****************************************************************************
//
//! Enables AES module global interrupt.
//!
//! \param wrapperBase is the base address of the AES module wrapper.
//!
//! This function enables the global interrupt in the AES module at wrappper
//! level.
//!
//! \note Global interrupts needs to be enabled along with individual AES
//! core interrupts like AES_INT_CONTEXT_IN, AES_INT_CONTEXT_OUT,
//! AES_INT_DATA_IN and AES_INT_DATA_OUT.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_enableGlobalInterrupt(uint32_t wrapperBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the AES global interrupt at wrapper level.
    //
    __byte_peripheral_32((uint32_t *)(wrapperBase + 0x2U)) |=
                                               0x1U;
}

//*****************************************************************************
//
//! Disables AES module global interrupt.
//!
//! \param wrapperBase is the base address of the AES module wrapper.
//!
//! This function disables the global interrupt in the AES module at wrapper
//! level.
//!
//! \note Global interrupts needs to be enabled along with individual AES
//! interrupts like AES_INT_CONTEXT_IN, AES_INT_CONTEXT_OUT, AES_INT_DATA_IN,
//! and AES_INT_DATA_OUT.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_disableGlobalInterrupt(uint32_t wrapperBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the AES global interrupt at wrapper level.
    //
    __byte_peripheral_32((uint32_t *)(wrapperBase + 0x2U)) &=
                                              ~0x1U;
}

//*****************************************************************************
//
//! Clears AES module global interrupt flag.
//!
//! \param wrapperBase is the base address of the AES module wrapper.
//!
//! This function clears the global interrupt flag in the AES module at wrapper
//! level.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_clearGlobalInterrupt(uint32_t wrapperBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the AES global interrupt flag at wrapper level.
    //
    __byte_peripheral_32((uint32_t *)(wrapperBase + 0x4U)) |=
                                            0x1U;
}

//*****************************************************************************
//
//! Returns the AES module global interrupt status.
//!
//! \param wrapperBase is the base address of the AES module wrapper.
//!
//! This function returns the AES global interrupt status flag at wrapper level.
//!
//! \return Returns the global interrupt status.
//! - \b true  - Global interrupt is flagged
//! - \b false - Global interrupt is not flagged
//
//*****************************************************************************
static inline _Bool
AES_getGlobalInterruptStatus(uint32_t wrapperBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the AES wrapper level global interrupt status.
    //
    return((__byte_peripheral_32((uint32_t *)(wrapperBase + 0x2U)) &
           0x1U) == 0x1U);
}

//*****************************************************************************
//
//! Registers an interrupt handler for the AES module.
//!
//! \param base is the base address of AES peripheral.
//! \param fnHandler is a pointer to the function to be called when the
//! enabled AES interrupts occur.
//!
//! This function registers the interrupt handler in the interrupt vector
//! table, and enables AES interrupts on the interrupt controller; specific AES
//! interrupt sources must be enabled using AES_enableInterrupt(). The interrupt
//! handler being registered must clear the source of the interrupt using
//! AES_clearInterruptStatus().
//!
//! If the application is using a static interrupt vector table stored in
//! flash, then it is not necessary to register the interrupt handler this way.
//! Instead, Interrupt_enable() is used to enable AES interrupts on the
//! interrupt controller.
//!
//! The \e base parameter can take following value: AESA_BASE
//!
//! \sa Interrupt_registerHandler() for important information about registering
//! interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_registerInterrupt(uint32_t base, void (*fnHandler)(void))
{
    //
    // Register the interrupt handler.
    //
    ;

    Interrupt_register(0x00DC0C0DU, fnHandler);

    //
    // Enable the interrupt
    //
    Interrupt_enable(0x00DC0C0DU);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the AES module.
//!
//! \param intNum is the interrupt number for AES interrupt.
//!
//! This function unregisters the previously registered interrupt handler and
//! disables the interrupt in the interrupt controller.
//!
//! The \e intNum parameter can take following value: AES_INT
//!
//! \sa Interrupt_registerHandler() for important information about registering
//! interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_unregisterInterrupt(uint32_t intNum)
{
    //
    // Disable the interrupt.
    //
    Interrupt_disable(intNum);

    //
    // Unregister the interrupt handler.
    //
    Interrupt_unregister(intNum);

}

//*****************************************************************************
//
//! Enables uDMA requests for the AES module.
//!
//! \param base is the base address of the AES module.
//! \param reqFlags is a bit mask of the uDMA requests to be enabled.
//!
//! This function enables the uDMA request sources in the AES module.
//! The \e reqFlags parameter is the logical OR of any of the following:
//!
//! - \b AES_DMA_EN_DATA_IN
//! - \b AES_DMA_EN_DATA_OUT
//! - \b AES_DMA_EN_CONTEXT_IN
//! - \b AES_DMA_EN_CONTEXT_OUT
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_enableDMARequest(uint32_t base, uint32_t reqFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Enable DMA requests.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x42U)) |= reqFlags;
}

//*****************************************************************************
//
//! Disables uDMA requests for the AES module.
//!
//! \param base is the base address of the AES module.
//! \param reqFlags is a bit mask of the uDMA requests to be disabled.
//!
//! This function disables the uDMA request sources in the AES module.
//! The \e reqFlags parameter is the logical OR of any of the
//! following:
//!
//! - \b AES_DMA_EN_DATA_IN
//! - \b AES_DMA_EN_DATA_OUT
//! - \b AES_DMA_EN_CONTEXT_IN
//! - \b AES_DMA_EN_CONTEXT_OUT
//!
//! \return None.
//
//*****************************************************************************
static inline void
AES_disableDMARequest(uint32_t base, uint32_t reqFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Disable DMA requests.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x42U)) &= ~reqFlags;
}

//*****************************************************************************
//
//! Configures the AES module.
//!
//! \param base is the base address of the AES module.
//! \param config is the configuration of the AES module.
//!
//! This function configures the AES module based on the specified parameters.
//! It does not change any DMA- or interrupt-related parameters.
//!
//! The config parameter is a structure with members specifying valid AES mode
//! configurations.
//!
//! The direction of the operation is specified with following enum members:
//!
//! - \b AES_DIRECTION_ENCRYPT - Encryption mode
//! - \b AES_DIRECTION_DECRYPT - Decryption mode
//!
//! The key size is specified with following enum members:
//!
//! - \b AES_KEY_SIZE_128BIT - Key size of 128 bits
//! - \b AES_KEY_SIZE_192BIT - Key size of 192 bits
//! - \b AES_KEY_SIZE_256BIT - Key size of 256 bits
//!
//! The mode of operation is specified with following enum members:
//!
//! - \b AES_OPMODE_ECB - Electronic codebook mode
//! - \b AES_OPMODE_CBC - Cipher-block chaining mode
//! - \b AES_OPMODE_CFB - Cipher feedback mode
//! - \b AES_OPMODE_CTR - Counter mode
//! - \b AES_OPMODE_ICM - Integer counter mode
//! - \b AES_OPMODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with
//!   ciphertext stealing with previous/intermediate tweak value and j loaded
//! - \b AES_OPMODE_XTS_K2IJL - XEX-based tweaked-codebook mode with
//!   ciphertext stealing with key2, i and j loaded
//! - \b AES_OPMODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with
//!   ciphertext stealing with key2 and i loaded, j = 0
//! - \b AES_OPMODE_F8 - F8 mode
//! - \b AES_OPMODE_F9 - F9 mode
//! - \b AES_OPMODE_CBCMAC - Cipher block chaining message authentication
//!   code mode
//! - \b AES_OPMODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H
//!   loaded, Y0-encrypted forced to zero and counter is not enabled.
//! - \b AES_OPMODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H
//!   loaded, Y0-encrypted calculated internally and counter is enabled.
//! - \b AES_OPMODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH
//!   (both H and Y0-encrypted calculated internally) and counter is enabled.
//! - \b AES_OPMODE_CCM - Counter with CBC-MAC mode
//!
//! The following enums are used to specify the counter width.  It is only
//! required to be defined when using CTR, CCM, or GCM modes, only one of the
//! following defines must be used to specify the counter width length:
//!
//! - \b AES_CTR_WIDTH_32BIT - Counter is 32 bits
//! - \b AES_CTR_WIDTH_64BIT - Counter is 64 bits
//! - \b AES_CTR_WIDTH_96BIT - Counter is 96 bits
//! - \b AES_CTR_WIDTH_128BIT - Counter is 128 bits
//!
//! Only one of the following defines must be used to specify the length field
//! for CCM operations (L):
//!
//! - \b AES_CCM_L_1 - 1 byte
//! - \b AES_CCM_L_2 - 2 bytes
//! - \b AES_CCM_L_4 - 4 bytes
//! - \b AES_CCM_L_8 - 8 bytes
//!
//! Only one of the following enum members must be used to specify the length
//! of authentication field for CCM operations (M) through the \e config
//! argument member in the AES_configureModule() function:
//!
//! - \b AES_CCM_M_0  - reset value
//! - \b AES_CCM_M_4  - 4 bytes
//! - \b AES_CCM_M_6  - 6 bytes
//! - \b AES_CCM_M_8  - 8 bytes
//! - \b AES_CCM_M_10 - 10 bytes
//! - \b AES_CCM_M_12 - 12 bytes
//! - \b AES_CCM_M_14 - 14 bytes
//! - \b AES_CCM_M_16 - 16 bytes
//!
//! \note When performing a basic GHASH operation for used with GCM mode, use
//! the \b AES_OPMODE_GCM_HLY0ZERO and do not specify a direction.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_configureModule(uint32_t base, const AES_ConfigParams *config);

//*****************************************************************************
//
//! Writes the key 1 configuration registers, which are used for encryption or
//! decryption.
//!
//! \param base is the base address for the AES module.
//! \param key is an array of 32-bit words, containing the key to be
//! configured.  The least significant word is at the 0th index. The key array
//! data values are expected to be in big-endian format.
//! \param keySize is the size of the key, which must be one of the
//! following enum values:  \b AES_KEY_SIZE_128BIT, \b AES_KEY_SIZE_192BIT, or
//! \b AES_KEY_SIZE_256BIT.
//!
//! This function writes key 1 configuration registers based on the key
//! size.  This function is used in all modes.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_setKey1(uint32_t base, const uint32_t key[], AES_KeySize keySize);

//*****************************************************************************
//
//! Writes the key 2 configuration registers, which are used for encryption or
//! decryption.
//!
//! \param base is the base address for the AES module.
//! \param key is an array of 32-bit words, containing the key to be
//! configured.  The least significant word in the 0th index. The key array
//! data values are expected to be in big-endian format.
//! \param keySize is the size of the key, which must be one of the
//! following enum values:  \b AES_KEY_SIZE_128BIT, \b AES_KEY_SIZE_192BIT, or
//! \b AES_KEY_SIZE_256BIT.
//!
//! This function writes the key 2 configuration registers based on the key
//! size.  This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_setKey2(uint32_t base, const uint32_t key[], AES_KeySize keySize);

//*****************************************************************************
//
//! Writes key 3 configuration registers, which are used for encryption or
//! decryption.
//!
//! \param base is the base address for the AES module.
//! \param key is a pointer to an array of 4 words (128 bits), containing
//! the key to be configured.  The least significant word is in the 0th index.
//! The key array data values are expected to be in big-endian format.
//!
//! This function writes the key 2 configuration registers with key 3 data
//! used in CBC-MAC and F8 modes.  This key is always 128 bits.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_setKey3(uint32_t base, const uint32_t key[]);

//*****************************************************************************
//
//! Writes the Initial Vector (IV) register, needed in some of the AES Modes.
//!
//! \param base is the base address of the AES module.
//! \param iniVector is an array of 4 words (128 bits), containing the IV
//! value to be configured.  The least significant word is in the 0th index.
//! The IV array data values are expected to be in big-endian format.
//!
//! This function writes the initial vector registers in the AES module.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_setInitializationVector(uint32_t base, const uint32_t iniVector[]);

//*****************************************************************************
//
//! Saves the Initial Vector (IV) registers to a user-defined location.
//!
//! \param base is the base address of the AES module.
//! \param iniVector is pointer to the location that stores the IV data. The
//! least significant word is in the 0th index. The IV data values are
//! expected to be in big-endian format.
//!
//! This function stores the IV for use in authenticated encryption and
//! decryption operations.  It is assumed that the AES_CTRL_SAVE_CONTEXT
//! bit is set in the AES_CTRL register.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_readInitializationVector(uint32_t base, uint32_t iniVector[]);

//*****************************************************************************
//
//! Saves the tag registers to a user-defined location.
//!
//! \param base is the base address of the AES module.
//! \param tagData is pointer to the location that stores the tag data. The
//! least significant word is in the 0th index. The tag array data values are
//! expected to be in big-endian format.
//!
//! This function stores the tag data for use in authenticated encryption and
//! decryption operations.  It is assumed that the AES_CTRL_SAVE_CONTEXT
//! bit is set in the AES_CTRL register.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_readTag(uint32_t base, uint32_t tagData[]);

//*****************************************************************************
//
//! Reads plaintext/ciphertext from data registers without blocking.
//!
//! \param base is the base address of the AES module.
//! \param destArray is a pointer to an array of words of data. The least
//! significant word is in the 0th index. The read data values are expected to
//! be in big-endian format.
//!
//! This function reads a block of either plaintext or ciphertext out of the
//! AES module.  If the output data is not ready, the function returns
//! false.  If the read completed successfully, the function returns true.
//! A block is 16 bytes or 4 words.
//!
//! \return Returns true or false.
//
//*****************************************************************************
extern _Bool
AES_readDataNonBlocking(uint32_t base, uint32_t destArray[]);

//*****************************************************************************
//
//! Reads plaintext/ciphertext from data registers with blocking.
//!
//! \param base is the base address of the AES module.
//! \param destArray is a pointer to an array of words. The least significant
//! word is in the 0th index. The read data values are expected to
//! be in big-endian format.
//!
//! This function reads a block of either plaintext or ciphertext out of the
//! AES module.  If the output is not ready, the function waits until it is
//! ready.  A block is 16 bytes or 4 words.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_readDataBlocking(uint32_t base, uint32_t destArray[]);

//*****************************************************************************
//
//! Writes plaintext/ciphertext to data registers without blocking.
//!
//! \param base is the base address of the AES module.
//! \param srcArray is a pointer to an array of words of data. The least
//! significant word is in the 0th index. The input data values are expected to
//! be in big-endian format.
//!
//! This function writes a block of either plaintext or ciphertext into the
//! AES module.  If the input is not ready, the function returns false.  If the
//! write completed successfully, the function returns true.  A block is 16
//! bytes or 4 words.
//!
//! \return True or false.
//
//*****************************************************************************
extern _Bool
AES_writeDataNonBlocking(uint32_t base, const uint32_t srcArray[]);

//*****************************************************************************
//
//! Writes plaintext/ciphertext to data registers with blocking.
//!
//! \param base is the base address of the AES module.
//! \param srcArray is a pointer to an array of bytes. The least significant
//! word is in the 0th index. The input data values are expected to
//! be in big-endian format.
//!
//! This function writes a block of either plaintext or ciphertext into the
//! AES module.  If the input is not ready, the function waits until it is
//! ready before performing the write.  A block is 16 bytes or 4 words.
//!
//! \return None.
//
//*****************************************************************************
extern void
AES_writeDataBlocking(uint32_t base, const uint32_t srcArray[]);

//*****************************************************************************
//
//! Used to process(transform) blocks of data, either encrypt or decrypt it.
//!
//! \param base is the base address of the AES module.
//! \param srcArray is a pointer to the memory location where the input data
//! is stored.  The data must be padded to the 16-byte boundary. The input data
//! values are expected to be in big-endian format.
//! \param destArray is a pointer to the memory location output is written.
//! The space for written data must be rounded up to the 16-byte boundary. The
//! output data values are expected to be in big-endian format.
//! \param dataLength is the length of the cryptographic data in bytes.
//!
//! This function iterates the encryption or decryption mechanism number over
//! the data length.  Before calling this function, ensure that the AES
//! module is properly configured the key, data size, mode, and so on.  Only
//! ECB, CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used.  The
//! data is processed in 4-word (16-byte) blocks.
//!
//! \return Returns true if data was processed successfully.  Returns false
//! if data processing failed.
//
//*****************************************************************************
extern _Bool
AES_processData(uint32_t base, const uint32_t srcArray[], uint32_t destArray[],
                uint64_t dataLength);

//*****************************************************************************
//
//! Used to authenticate blocks of data by generating a hash tag.
//!
//! \param base is the base address of the AES module.
//! \param srcArray is a pointer to the memory location where the input data
//! is stored.  The data must be padded to the 16-byte boundary. The input data
//! values are expected to be in big-endian format.
//! \param dataLength  is the length of the cryptographic data in bytes.
//! \param tagArray is a pointer to a 4-word array where the hash tag is
//! written. The output data values are to be expected in big-endian format.
//!
//! This function processes data to produce a hash tag that can be used tor
//! authentication.   Before calling this function, ensure that the AES
//! module is properly configured the key, data size, mode, and so on.  Only
//! CBC-MAC and F9 modes should be used.
//!
//! \return Returns true if data was processed successfully.  Returns false
//! if data processing failed.
//
//*****************************************************************************
extern _Bool
AES_authenticateData(uint32_t base, const uint32_t srcArray[],
                     uint64_t dataLength, uint32_t tagArray[]);

//*****************************************************************************
//
//! Processes and authenticates blocks of data, either encrypts it or decrypts
//! it.
//!
//! \param base  is the base address of the AES module.
//! \param srcArray is a pointer to the memory location where the input data
//! is stored.  The data must be padded to the 16-byte boundary. The input data
//! values are expected to be in big-endian format.
//! \param destArray is a pointer to the memory location where the output is
//! written. The space for written data must be rounded up to the 16-byte
//! boundary. The output data values are to be expected in big-endian format.
//! \param dataLength is the length of the cryptographic data in bytes.
//! \param authDataArray is a pointer to the memory location where the
//! additional authentication data is stored.  The data must be padded to the
//! 16-byte boundary. The output data values are to be expected in big-endian
//! format.
//! \param authDataLength is the length of the additional authentication
//! data in bytes.
//! \param tagArray is a pointer to a 4-word array where the hash tag is
//! written. The output data values are to be expected in big-endian format.
//!
//! This function encrypts or decrypts blocks of data in addition to
//! authentication data.  A hash tag is also produced.  Before calling this
//! function, ensure that the AES module is properly configured the key,
//! data size, mode, and so on.  Only CCM and GCM modes should be used.
//!
//! \return Returns true if data was processed successfully. Returns false
//! if data processing failed.
//
//*****************************************************************************
extern _Bool
AES_processDatainAuthMode(uint32_t base, const uint32_t srcArray[],
                          uint32_t destArray[], uint64_t dataLength,
                          const uint32_t authDataArray[],
                          uint32_t authDataLength, uint32_t tagArray[]);

//*****************************************************************************
//
//! Returns the current AES module core interrupt status.
//!
//! \param base is the base address of the AES module.
//! \param intMask is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! \return Returns a bit mask of the core interrupt sources, which is a logical
//! OR of any of the following:
//!
//! - \b AES_INT_CONTEXT_IN      - Context interrupt
//! - \b AES_INT_CONTEXT_OUT     - Authentication tag (and IV) interrupt.
//! - \b AES_INT_DATA_IN         - Data input interrupt
//! - \b AES_INT_DATA_OUT        - Data output interrupt
//
//*****************************************************************************
extern uint32_t
AES_getInterruptStatus(uint32_t base, _Bool intMask);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************


//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   asysctl.h
//
// TITLE:  C28x driver for Analog System Control.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup asysctl_api ASysCtl
//! @{
//
//*****************************************************************************


//*****************************************************************************
//
// Defines used for setting AnalogReference functions.
// ASysCtl_setAnalogReferenceInternal()
// ASysCtl_setAnalogReferenceExternal()
// ASysCtl_setAnalogReference2P5()
// ASysCtl_setAnalogReference1P65()
//
//*****************************************************************************

//*****************************************************************************
//
// Values used for function ASysCtl_selectCMPHNMux() and
// ASysCtl_selectCMPHNMuxValue().  These values can be OR-ed together and
// passed to ASysCtl_selectCMPHNMux().
//
//*****************************************************************************

//*****************************************************************************
//
// Values used for function ASysCtl_selectCMPLNMux() and
// ASysCtl_selectCMPLNMuxValue().  These values can be OR-ed together and
// passed to ASysCtl_selectCMPLNMux().
//
//*****************************************************************************

//*****************************************************************************
//
//! ASysCtl_CMPHPMuxSelect used for function ASysCtl_selectCMPHPMux().
//
//*****************************************************************************
typedef enum
{
    ASYSCTL_CMPHPMUX_SELECT_1 = 0U, //!< CMPHPMUX select 1
    ASYSCTL_CMPHPMUX_SELECT_2 = 3U, //!< CMPHPMUX select 2
    ASYSCTL_CMPHPMUX_SELECT_3 = 6U, //!< CMPHPMUX select 3
    ASYSCTL_CMPHPMUX_SELECT_4 = 9U  //!< CMPHPMUX select 4
} ASysCtl_CMPHPMuxSelect;

//*****************************************************************************
//
//! ASysCtl_CMPLPMuxSelect used for function ASysCtl_selectCMPLPMux().
//
//*****************************************************************************
typedef enum
{
    ASYSCTL_CMPLPMUX_SELECT_1 = 0U, //!< CMPLPMUX select 1
    ASYSCTL_CMPLPMUX_SELECT_2 = 3U, //!< CMPLPMUX select 2
    ASYSCTL_CMPLPMUX_SELECT_3 = 6U, //!< CMPLPMUX select 3
    ASYSCTL_CMPLPMUX_SELECT_4 = 9U  //!< CMPLPMUX select 4
} ASysCtl_CMPLPMuxSelect;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enable temperature sensor.
//!
//! This function enables the temperature sensor output to the ADC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_enableTemperatureSensor(void)
{
    __eallow();

    //
    // Set the temperature sensor enable bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x60U)))) |= 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Disable temperature sensor.
//!
//! This function disables the temperature sensor output to the ADC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_disableTemperatureSensor(void)
{
    __eallow();

    //
    // Clear the temperature sensor enable bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x60U)))) &= ~(0x1U);

    __edis();
}

//*****************************************************************************
//
//! Set the analog voltage reference selection to internal.
//!
//! \param reference is the analog reference.
//!
//! The parameter \e reference can be a combination of the following values:
//!
//! - \b ASYSCTL_VREFHI
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_setAnalogReferenceInternal(uint16_t reference)
{
    ;

    __eallow();

    //
    // Write selection to the Analog Internal Reference Select bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x68U)))) &= ~reference;

    __edis();
}

//*****************************************************************************
//
//! Set the analog voltage reference selection to external.
//!
//! \param reference is the analog reference.
//!
//! The parameter \e reference can be a combination of the following values:
//!
//! - \b ASYSCTL_VREFHI
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_setAnalogReferenceExternal(uint16_t reference)
{
    ;

    __eallow();

    //
    // Write selection to the Analog External Reference Select bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x68U)))) |= reference;

    __edis();
}
//*****************************************************************************
//
//! Set the internal analog voltage reference selection to 2.5V.
//!
//! \param reference is the analog reference.
//!
//! The parameter \e reference can be a combination of the following values:
//!
//! - \b ASYSCTL_VREFHI
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_setAnalogReference2P5(uint16_t reference)
{
    ;

    __eallow();

    //
    // Write selection to the Analog Voltage Reference Select bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x68U)))) |= (reference << 8U);

    __edis();
}

//*****************************************************************************
//
//! Set the internal analog voltage reference selection to 1.65V.
//!
//! \param reference is the analog reference.
//!
//! The parameter \e reference can be a combination of the following values:
//!
//! - \b ASYSCTL_VREFHI
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_setAnalogReference1P65(uint16_t reference)
{
    ;

    __eallow();

    //
    // Write selection to the Analog Voltage Reference Select bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x68U)))) &= ~(reference << 8U);

    __edis();
}

//*****************************************************************************
//
//! Select the value for CMPHNMXSEL.
//!
//! \param select is a combination of CMPHNMXSEL values.
//!
//! The parameter \e select can be a bitwise OR of the below values:
//!
//! - \b ASYSCTL_CMPHNMUX_SELECT_1
//! - \b ASYSCTL_CMPHNMUX_SELECT_2
//! - \b ASYSCTL_CMPHNMUX_SELECT_3
//! - \b ASYSCTL_CMPHNMUX_SELECT_4
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_selectCMPHNMux(uint16_t select)
{
    ;

    __eallow();

    //
    // Write a select to the mux select bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x86U)))) = select;

    __edis();
}

//*****************************************************************************
//
//! Select the value for individual CMPxHNMXSEL.
//!
//! \param select is the CMPxHNMXSEL to be set.
//! \param value is 0 or 1.
//!
//! The parameter \e select can be one of the below values:
//!
//! - \b ASYSCTL_CMPHNMUX_SELECT_1
//! - \b ASYSCTL_CMPHNMUX_SELECT_2
//! - \b ASYSCTL_CMPHNMUX_SELECT_3
//! - \b ASYSCTL_CMPHNMUX_SELECT_4
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_selectCMPHNMuxValue(uint16_t select, uint16_t value)
{
    ;
    ;

    __eallow();

    //
    // Write a select to the mux select bit.
    //
    if(value == 0U)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x86U)))) &= ~select;
    }
    else if(value == 1U)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x86U)))) |= select;
    }

    __edis();
}

//*****************************************************************************
//
//! Select the value for individual CMPxLNMXSEL.
//!
//! \param select is a combination of CMPLNMXSEL values.
//!
//! The parameter \e select can be the bitwise OR of the below values:
//!
//! - \b ASYSCTL_CMPLNMUX_SELECT_1
//! - \b ASYSCTL_CMPLNMUX_SELECT_2
//! - \b ASYSCTL_CMPLNMUX_SELECT_3
//! - \b ASYSCTL_CMPLNMUX_SELECT_4
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_selectCMPLNMux(uint16_t select)
{
    ;

    __eallow();

    //
    // Write a select to the mux select bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x87U)))) = select;

    __edis();
}

//*****************************************************************************
//
//! Select the value for CMPLNMXSEL.
//!
//! \param select is the CMPxHNMXSEL to be set.
//! \param value is 0 or 1.
//!
//! The parameter \e select can be one of the below values:
//!
//! - \b ASYSCTL_CMPLNMUX_SELECT_1
//! - \b ASYSCTL_CMPLNMUX_SELECT_2
//! - \b ASYSCTL_CMPLNMUX_SELECT_3
//! - \b ASYSCTL_CMPLNMUX_SELECT_4
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_selectCMPLNMuxValue(uint16_t select, uint16_t value)
{
    ;
    ;

    __eallow();

    //
    // Write a select to the mux select bit.
    //
    if(value == 0U)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x87U)))) &= ~select;
    }
    else if(value == 1U)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x87U)))) |= select;
    }

    __edis();
}

//*****************************************************************************
//
//! Select the value for CMPHPMXSEL.
//!
//! \param select is of type ASysCtl_CMPHPMuxSelect.
//! \param value is 0, 1, 2, 3, or 4.
//!
//! This function is used to write a value to one mux select at a time.
//! The parameter \e select can be one of the following values:
//!
//! - \b ASYSCTL_CMPHPMUX_SELECT_1
//! - \b ASYSCTL_CMPHPMUX_SELECT_2
//! - \b ASYSCTL_CMPHPMUX_SELECT_3
//! - \b ASYSCTL_CMPHPMUX_SELECT_4
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_selectCMPHPMux(ASysCtl_CMPHPMuxSelect select, uint32_t value)
{
    ;

    __eallow();

    //
    // Set the value for the appropriate Mux Select.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D700U + 0x82U)))) =
    ((*((volatile uint32_t *)((uintptr_t)(0x0005D700U + 0x82U)))) &
    ~((uint32_t)0x7U << (uint32_t)select)) |
    (value << (uint32_t)select);

    __edis();
}

//*****************************************************************************
//
//! Select the value for CMPLPMXSEL.
//!
//! \param select is of type ASysCtl_CMPLPMuxSelect.
//! \param value is 0, 1, 2, 3, or 4.
//!
//! This function is used to write a value to one mux select at a time.
//! The parameter \e select can be one of the following values:
//!
//! - \b ASYSCTL_CMPLPMUX_SELECT_1
//! - \b ASYSCTL_CMPLPMUX_SELECT_2
//! - \b ASYSCTL_CMPLPMUX_SELECT_3
//! - \b ASYSCTL_CMPLPMUX_SELECT_4
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_selectCMPLPMux(ASysCtl_CMPLPMuxSelect select, uint32_t value)
{
    ;

    __eallow();

    //
    // Set the value for the appropriate Mux Select.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D700U + 0x84U)))) =
    ((*((volatile uint32_t *)((uintptr_t)(0x0005D700U + 0x84U)))) &
    ~((uint32_t)0x7U << (uint32_t)select)) |
    (value << (uint32_t)select);

    __edis();
}

//*****************************************************************************
//
//! Locks the temperature sensor control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockTemperatureSensor(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Locks the analog reference control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockANAREF(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x2U;

    __edis();
}

//*****************************************************************************
//
//! Locks the voltage monitor control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockVMON(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x4U;

    __edis();
}

//*****************************************************************************
//
//! Locks the CMPHPMXSEL control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockCMPHPMux(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x20U;

    __edis();
}

//*****************************************************************************
//
//! Locks the CMPLPMXSEL control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockCMPLPMux(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x40U;

    __edis();
}

//*****************************************************************************
//
//! Locks the CMPHNMXSEL control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockCMPHNMux(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x80U;

    __edis();
}

//*****************************************************************************
//
//! Locks the CMPLNMXSEL control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockCMPLNMux(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x100U;

    __edis();
}

//*****************************************************************************
//
//! Locks the VREG control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockVREG(void)
{
    __eallow();

    //
    // Write a 1 to the lock bit in the LOCK register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D700U + 0x8EU)))) |= 0x200U;

    __edis();
}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   bgcrc.h
//
// TITLE:  C28x BGCRC driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup bgcrc_api BGCRC
//! \brief This module is used for configuring BGCRC.
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_bgcrc.h
//
// TITLE:   Definitions for the BGCRC registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the BGCRC register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_EN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_CTRL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_CTRL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_WD_CFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_NMIFLG register
//
//*************************************************************************************************
                                                 // read.
                                                 // data read.
                                                 // BGCRC_WD_MAX

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_NMICLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_NMIFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_INTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_INTFLG register
//
//*************************************************************************************************
                                                 // read.
                                                 // data read.
                                                 // BGCRC_WD_MAX

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_INTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_INTFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BGCRC_COMMIT register
//
//*************************************************************************************************






//*****************************************************************************
//
//! Values that can be passed to BGCRC_setConfig() as the \e nmiConfig
//! parameter
//
//*****************************************************************************
                                    //!<failure

//*****************************************************************************
//
//! Values that can be passed to BGCRC_setConfig() as the \e emuCtrl parameter
//
//*****************************************************************************
                                    //!< immediately on DEBUG SUSPEND
                                    //!< not affected by DEBUG HALT

//*****************************************************************************
//
//! Values that can be passed to BGCRC_setRegion() as the \e mode parameter
//
//*****************************************************************************
                                    //!< golden CRC. Error check is done using
                                    //!< the ECC/Parity logic.
                                    //!< at the end in addition to the data
                                    //!< correctness check by ECC/Parity logic

//*****************************************************************************
//
//! Values that can be passed to all interrupt/NMI functions as \e intflags or
//! \e nmiflags parameter
//
//*****************************************************************************




//*****************************************************************************
//
//! Values that can be passed to BGCRC_setRegion as the \e blockSize parameter
//! For example, to configure a region of size 2.5KB, set \e blockSize as
//! BGCRC_SIZE_KBYTES(2) + BGCRC_SIZE_BYTES_512
//
//*****************************************************************************


//*****************************************************************************
//
//! Values returned by the function BGCRC_getRunStatus
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to BGCRC_lockRegister(), BGCRC_unlockRegister()
//! and BGCRC_commitLockRegister() as the \e regs parameter
//!
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that are used by the BGCRC APIs
//
//*****************************************************************************

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an BGCRC base address.
//!
//! \param base is the BGCRC module base address.
//!
//! This function determines if a BGCRC module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets the NMI and emulation control configurations
//!
//! \param base is the BGCRC module base address.
//! \param nmiConfig specifies whether NMI needs to be enabled or not for
//!                  memory check failure
//! \param emuCtrl specifies the behaviour of CRC during emulation
//!
//! This function configures the NMI and emulation control configurations for
//! the BGCRC module.
//!
//! \e nmiConfig can take values \b BGCRC_NMI_ENABLE or \b BGCRC_NMI_DISABLE.
//! NMI is enabled by default for the memory check failures.
//!
//! \e emuCtrl can take values \b BGCRC_EMUCTRL_FREE or \b BGCRC_EMUCTRL_SOFT.
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_setConfig(uint32_t base, uint32_t nmiConfig, uint32_t emuCtrl)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Set emulation control and NMI configuration
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) = (nmiConfig << 16U) | emuCtrl;
    __edis();
}

//*****************************************************************************
//
//! Enables the watchdog
//!
//! \param base is the BGCRC module base address.
//!
//! This function enables the BGCRC watchdog timer. The counter is started
//! when the BGCRC test starts
//!
//! \note The watchDog window can be configured using the function
//! BGCRC_setWatchdogWindow()
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_enableWatchdog(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable watchdog
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x1CU)))) = 0x5U;
    __edis();
}

//*****************************************************************************
//
//! Disables the watchdog
//!
//! \param base is the BGCRC module base address.
//!
//! This function disables the BGCRC watchdog.
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_disableWatchdog(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable watchdog
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x1CU)))) = 0xAU;
    __edis();
}

//*****************************************************************************
//
//! Configures the BGCRC watchdog window
//!
//! \param base is the BGCRC module base address.
//! \param min is minimum value configuration for the windowed watchdog
//! \param max is maximum value configuration for the windowed watchdog
//!
//! This function configures the BGCRC windowed watchdog
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_setWatchdogWindow(uint32_t base, uint32_t min, uint32_t max)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set the min and max values
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x1EU)))) = min;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x20U)))) = max;
    __edis();
}
//*****************************************************************************
//
//! Configures the memory region for check
//!
//! \param base is the BGCRC module base address.
//! \param startAddr is the start address of the block
//! \param blockSize is the size of the block
//! \param mode is the BGCRC test mode
//!
//! This function configures the memory region to be checked
//!
//! \e blockSize can take values \b BGCRC_SIZE_KBYTES(x) and/or
//! \b BGCRC_SIZE_BYTES_x. For example, to configure a region of size 2.5KB,
//! set \e blockSize as BGCRC_SIZE_KBYTES(2) + BGCRC_SIZE_BYTES_512
//!
//! \e mode can take values \b BGCRC_SCRUB_MODE or \b BGCRC_CRC_MODE. In Scrub
//! mode, CRC of data is not compared with the golden CRC. Error check is done
//! using the ECC/Parity logic. In CRC mode, value is compared with golden CRC
//! at the end in addition to the data correctness check by ECC/Parity logic.
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_setRegion(uint32_t base, uint32_t startAddr,
                uint32_t blockSize, uint32_t mode)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Set the start address and size of the block. Set the mode of operation
    //

    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(base + 0x6U)))) = startAddr;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) =
                    ((blockSize - 1U) << 0U) |
                    (mode << 16U);
    __edis();
}

//*****************************************************************************
//
//! Gets the BGCRC watchdog counter value
//!
//! \param base is the BGCRC module base address.
//!
//! This function returns the BGCRC watchdog counter value
//!
//! \return Watchdog counter value.
//
//*****************************************************************************
static inline uint32_t
BGCRC_getWatchdogCounterValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x22U)))));
}

//*****************************************************************************
//
//! Enables individual BGCRC interrupt sources
//!
//! \param base is the BGCRC module base address.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function enables the indicated BGCRC interrupt sources.  Only the
//! sources that are enabled can be reflected to the processor interrupt,
//! disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//!
//!  - \b BGCRC_TEST_DONE    - Test done interrupt
//!  - \b BGCRC_CRC_FAIL     - CRC Fail Interrupt
//!  - \b BGCRC_UNCORR_ERR   - Uncorrectable Error Interrupt
//!  - \b BGCRC_CORR_ERR     - Correctable Error Interrupt
//!  - \b BGCRC_WD_UNDERFLOW - Watchdog Underflow Error Interrupt
//!  - \b BGCRC_WD_OVERFLOW  - Watchdog Overflow Error Interrupt
//!
//! \return None
//
//*****************************************************************************
static inline void
BGCRC_enableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x34U)))) |= intFlags;
    __edis();
}

//*****************************************************************************
//
//! Disables individual BGCRC interrupt sources.
//!
//! \param base is the BGCRC module base address.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated BGCRC interrupt sources.  Only the
//! sources that are enabled can be reflected to the processor interrupt
//! disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter has the same definition as the
//! \e intFlags parameter to BGCRC_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_disableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x34U)))) &= ~intFlags;
    __edis();
}

//*****************************************************************************
//
//! Gets the current BGCRC interrupt status
//!
//! \param base is the BGCRC module base address
//!
//! This function returns the status of the BGCRC interrupts
//!
//! \return The current interrupt status, which is a logical OR of any of the
//! following:
//!
//!  - \b BGCRC_GLOBAL_INT   - Global Interrupt
//!  - \b BGCRC_TEST_DONE    - Test done interrupt
//!  - \b BGCRC_CRC_FAIL     - CRC Fail Interrupt
//!  - \b BGCRC_UNCORR_ERR   - Uncorrectable Error Interrupt
//!  - \b BGCRC_CORR_ERR     - Correctable Error Interrupt
//!  - \b BGCRC_WD_UNDERFLOW - Watchdog Underflow Error Interrupt
//!  - \b BGCRC_WD_OVERFLOW  - Watchdog Overflow Error Interrupt
//
//*****************************************************************************
static inline uint32_t
BGCRC_getInterruptStatus(uint32_t base)
{
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x36U)))));
}

//*****************************************************************************
//
//! Clears the BGCRC interrupt sources
//!
//! \param base is the BGCRC module base address
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified BGCRC interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e intFlags parameter has the same definition as the
//! \e intFlags parameter to BGCRC_getInterruptStatus().
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_clearInterruptStatus(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x38U)))) = intFlags;
    __edis();
}

//*****************************************************************************
//
//! Force the BGCRC interrupt flag
//!
//! \param base is the BGCRC module base address
//! \param intFlags is a bit mask of the interrupt flags to be forced.
//!
//! This function forces the specified interrupt flags
//!
//! The \e intFlags parameter has the same definition as the
//! \e intFlags parameter to BGCRC_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_forceInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x3AU)))) = intFlags;
    __edis();
}

//*****************************************************************************
//
//! Gets the current BGCRC NMI status
//!
//! \param base is the BGCRC module base address
//!
//! This function returns the status of the BGCRC NMI flags
//!
//! \return The current NMI status, which is a logical OR of any of the
//! following:
//!
//!  - \b BGCRC_CRC_FAIL     - CRC Fail NMI
//!  - \b BGCRC_UNCORR_ERR   - Uncorrectable Error NMI
//!  - \b BGCRC_CORR_ERR     - Correctable Error NMI
//!  - \b BGCRC_WD_UNDERFLOW - Watchdog Underflow Error NMI
//!  - \b BGCRC_WD_OVERFLOW  - Watchdog Overflow Error NMI
//
//*****************************************************************************
static inline uint32_t
BGCRC_getNMIStatus(uint32_t base)
{
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x2AU)))));
}

//*****************************************************************************
//
//! Clears the BGCRC NMI sources
//!
//! \param base is the BGCRC module base address
//! \param nmiFlags is a bit mask of the NMI sources to be cleared.
//!
//! The specified BGCRC NMI sources are cleared, so that they no longer
//! assert. This function must be called in the NMI handler to keep the
//! NMI from being triggered again immediately upon exit.
//!
//! The \e nmiFlags parameter has the same definition as the
//! \e nmiFlags parameter to BGCRC_getNMIStatus().
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_clearNMIStatus(uint32_t base, uint32_t nmiFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2CU)))) = nmiFlags;
    __edis();
}

//*****************************************************************************
//
//! Force the BGCRC NMI flag
//!
//! \param base is the BGCRC module base address
//! \param nmiFlags is a bit mask of the NMI flags to be forced.
//!
//! This function forces the specified interrupt flags
//!
//! The \e nmiFlags parameter has the same definition as the
//! \e nmiFlags parameter to BGCRC_getNMIStatus().
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_forceNMI(uint32_t base, uint32_t nmiFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2EU)))) = nmiFlags;
    __edis();
}

//*****************************************************************************
//
//! Sets the golden CRC value
//!
//! \param base is the BGCRC module base address
//! \param crcVal is a golden CRC value to be programmed
//!
//! This function sets the golden CRC value of the memory block being tested.
//! If run in CRC mode, the calculated CRC value is compared with golden CRC
//! and status is updated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_setGoldenCRCValue(uint32_t base, uint32_t crcVal)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0xEU)))) = crcVal;
    __edis();
}

//*****************************************************************************
//
//! Starts the module operation
//!
//! \param base is the BGCRC module base address
//!
//! This function starts the module operation. Calling this function during
//! the CRC calculation will reset and re-start the CRC calculation.
//! This also resets the watchdog timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_start(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) = 0xAU;
    __edis();
}

//*****************************************************************************
//
//! Halts the module operation
//!
//! \param base is the BGCRC module base address
//!
//! This function halts the module operation. This function does not stall the
//! watchdog timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_halt(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) =
                ((*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) & ~0xF000U) |
                (0xAU << 12U);
    __edis();
}

//*****************************************************************************
//
//! Resumes the module operation
//!
//! \param base is the BGCRC module base address
//!
//! This function resumes the module operation. The CRC calculation will
//! continue/resume from where it was halted
//!
//! \return None.
//
//*****************************************************************************
static inline void
BGCRC_resume(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) &= ~0xF000U;
    __edis();
}

//*****************************************************************************
//
//! Gets the running status of the module
//!
//! \param base is the BGCRC module base address
//!
//! This function returns whether the module is in ACTIVE or IDLE state
//!
//! \return \b BGCRC_ACTIVE if CRC module is active,
//!         \b BGCRC_IDLE if CRC module is idle
//
//*****************************************************************************
static inline uint32_t
BGCRC_getRunStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) & 0x80000000U);
}
//*****************************************************************************
//
//! Sets the seed value for CRC calculations
//!
//! \param base is the BGCRC module base address
//! \param seed is the seed value to be set
//!
//! This function sets the seed value for the CRC calculations
//!
//! \return None
//
//*****************************************************************************
static inline void
BGCRC_setSeedValue(uint32_t base, uint32_t seed)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x8U)))) = seed;
    __edis();
}

//*****************************************************************************
//
//! Gets the calculated CRC value
//!
//! \param base is the BGCRC module base address
//!
//! This function returns the calculated CRC value
//!
//! \return 32-bit CRC result
//
//*****************************************************************************
static inline uint32_t
BGCRC_getResult(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x10U)))));
}

//*****************************************************************************
//
//! Gets the current address
//!
//! \param base is the BGCRC module base address
//!
//! This function returns the current address  from where the data is fetched
//!
//! \return 32-bit address
//
//*****************************************************************************
static inline uint32_t
BGCRC_getCurrentAddress(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x12U)))));
}

//*****************************************************************************
//
//! Locks the register configuration
//!
//! \param base is the BGCRC module base address
//! \param regs is the configuration registers to be locked
//!
//! This function locks the register configuration. The register once
//! locked, cannot be updated until the lock is removed
//!
//! The \e regs parameter is the logical OR of any of the following:
//!
//!  - \b BGCRC_REG_EN
//!  - \b BGCRC_REG_CTRL1
//!  - \b BGCRC_REG_CTRL2
//!  - \b BGCRC_REG_START_ADDR
//!  - \b BGCRC_REG_SEED
//!  - \b BGCRC_REG_GOLDEN
//!  - \b BGCRC_REG_WD_CFG
//!  - \b BGCRC_REG_WD_MIN
//!  - \b BGCRC_REG_WD_MAX
//!  - \b BGCRC_REG_NMIFRC
//!  - \b BGCRC_REG_INTEN
//!  - \b BGCRC_REG_INTFRC
//!  - \b BGCRC_REG_ALL
//!
//! \return None
//
//*****************************************************************************
static inline void
BGCRC_lockRegister(uint32_t base, uint32_t regs)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x3CU)))) |= regs;
    __edis();
}

//*****************************************************************************
//
//! Unlocks the register configuration
//!
//! \param base is the BGCRC module base address
//! \param regs is the configuration registers to be unlocked
//!
//! This function unlocks the register configuration.
//!
//! The \e regs parameter has the same definition as the \e regs parameter
//! to BGCRC_lockRegister().
//!
//! \return None
//
//*****************************************************************************
static inline void
BGCRC_unlockRegister(uint32_t base, uint32_t regs)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x3CU)))) &= ~regs;
    __edis();
}

//*****************************************************************************
//
//! Commits the register configuration
//!
//! \param base is the BGCRC module base address
//! \param regs is the configuration registers to be unlocked
//!
//! This function commits the register configuration. Once configuration is
//! committed, only reset can change the configuration.
//!
//! The \e regs parameter has the same definition as the \e regs parameter
//! to BGCRC_lockRegister().
//!
//! \return None
//
//*****************************************************************************
static inline void
BGCRC_commitRegisterLock(uint32_t base, uint32_t regs)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x3EU)))) |= regs;
    __edis();
}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   can.h
//
// TITLE:  C28x CAN driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************


//*****************************************************************************
//
//! \addtogroup can_api CAN
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_can.h
//
// TITLE:   Definitions for the CAN registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the CAN register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_ES register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_ERRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_BTR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_INT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_TEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_PERR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_RAM_INIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_EN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_FLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_CLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ_X register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_NDAT_X register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IPEN_X register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_MVAL_X register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1CMD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1MSK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1ARB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1MCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1DATA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1DATB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2CMD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2MSK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2ARB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2MCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2DATA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2DATB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3OBS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3MSK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3ARB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3MCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3DATA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3DATB register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:   sysctl.h
//
// TITLE:  C28x system control driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup sysctl_api SysCtl
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_nmi.h
//
// TITLE:   Definitions for the NMI registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the NMI register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the NMICFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the NMIFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the NMIFLGCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the NMIFLGFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the NMISHDFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERRORSTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERRORSTSCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERRORSTSFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERRORCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERRORLOCK register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:    hw_wwd.h
//
// TITLE:   Definitions for the SYSCTL registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the SYSCTL register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the SCSR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the WDCNTR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the WDKEY register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the WDCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the WDWCR register
//
//*************************************************************************************************
                                         // functionality



//###########################################################################
//
// FILE:    hw_sysctl.h
//
// TITLE:   Definitions for the SYSCTL registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the SYSCTL register offsets
//
//*************************************************************************************************


                                             // register


                                           // Access register.



                                           // in the system.


//*************************************************************************************************
//
// The following are defines for the bit fields in the PARTIDL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PARTIDH register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the REVID register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FUSEERR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES6 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES7 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES8 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES9 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES10 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES13 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES14 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES16 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES17 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES18 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES19 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES20 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES21 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES25 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES26 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTPRES27 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TAP_STATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAPTYPE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFMTYPE register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKCFGLOCK1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKSRCCTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKSRCCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKSRCCTL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYSPLLCTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYSPLLMULT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYSPLLSTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYSCLKDIVSEL register
//
//*************************************************************************************************
                                                        // sys clock divider

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXCLKDIVSEL register
//
//*************************************************************************************************
                                                     // CANFD Bit CLK

//*************************************************************************************************
//
// The following are defines for the bit fields in the XCLKOUTDIVSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LOSPCP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MCDCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the X1CNT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XTALCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XTALCR2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKFAILCFG register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CPUSYSLOCK1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CPUSYSLOCK2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEVERRADDR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR6 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR7 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR8 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR9 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR10 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR13 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR14 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR16 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR17 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR18 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR19 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR20 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR21 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR25 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR26 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCLKCR27 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SIMRESET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LPMCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPIOLPMSEL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPIOLPMSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TMR2CLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RESCCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RESC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MCANWAKESTATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MCANWAKESTATUSCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKSTOPREQ register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKSTOPACK register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CLA1TASKSRCSELLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DMACHSRCSELLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLA1TASKSRCSEL1 register
//
//*************************************************************************************************
                                                       // CLA1
                                                       // CLA1
                                                       // CLA1
                                                       // CLA1

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLA1TASKSRCSEL2 register
//
//*************************************************************************************************
                                                       // CLA1
                                                       // CLA1
                                                       // CLA1
                                                       // CLA1

//*************************************************************************************************
//
// The following are defines for the bit fields in the DMACHSRCSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DMACHSRCSEL2 register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCB_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCC_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPSS1_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPSS2_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPSS3_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPSS4_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACB_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM1_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM2_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM3_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM4_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM5_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM6_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM7_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWM8_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EQEP1_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EQEP2_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAP1_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAP2_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAP3_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFM1_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFM2_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB1_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB2_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB3_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB4_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIB_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIB_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CB_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBUS_A_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_A_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_B_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCANA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MCANA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FSIATX_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FSIARX_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRPWM_A_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HIC_A_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AESA_AC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PERIPH_AC_LOCK register
//
//*************************************************************************************************
                                                  // write.


//*************************************************************************************************
//
// The following are defines for the bit fields in the SYNCSELECT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCOUTSELECT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYNCSOCLOCK register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the LFUConfig register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LFUStatus register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LFU_LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LFU_COMMIT register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the SYS_ERR_INT_FLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYS_ERR_INT_CLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYS_ERR_INT_SET register
//
//*************************************************************************************************
                                                             // bit

//*************************************************************************************************
//
// The following are defines for the bit fields in the SYS_ERR_MASK register
//
//*************************************************************************************************





//*****************************************************************************
//
// Defines for system control functions. Not intended for use by application
// code.
//
//*****************************************************************************

//
// Shifted pattern for WDCR register's WDCHK field.
//

//
// Keys for WDKEY field. The first enables resets and the second resets.
//

//
// Values to help decode peripheral parameter
//

//
//Keys for the System control registers write protection
//

//
//Values to help access shifting of bits
//


//
// LPM defines for LPMCR.LPM
//

//
// Default internal oscillator frequency, 10 MHz
//


//
// Boot ROM Booting and Reset Status
//

//
// Device_cal function which is available in OTP memory
// This function is called in SysCtl_resetPeripheral after resetting
// analog peripherals
//

//*****************************************************************************
//
// The following are values that can be passed to the SysCtl_setClock() API as
// the config parameter.
//
//*****************************************************************************
//
// System clock divider (SYSDIV)
//

//
// Mask and shift for Reference Clock Divider value in config
//

//
// Mask and shift for Output Clock Divider value in config
//

//!
//! Macro to format Clock divider value. x is a number from 1 to 32.
//!

//!
//! Macro to format Clock divider value. x is a number from 1 to 32.
//!



//! Macro to format system clock divider value. x must be 1 or even values up
//! to 126.

//
// Integer multiplier (IMULT)
//
//
// Mask for IMULT value in config
//
//! Macro to format integer multiplier value. x is a number from 1 to 127.
//!

//
// Fractional multiplier (FMULT)
//

//
// DCC module selection for checking PLL clock validity
//
// Mask and shift for DCC module base address in config
//




//
// Oscillator source
//
// Also used with the SysCtl_selectOscSource(), SysCtl_turnOnOsc(),
// and SysCtl_turnOffOsc() functions as the oscSource parameter.
//
//! Internal oscillator INTOSC2
//! External oscillator (XTAL) in crystal mode
//! External oscillator (XTAL) in single-ended mode
//! Internal oscillator INTOSC1

//
// Enable/disable PLL
//

//
//Mask to check the PLL configuration selected
//


//
// Number of PLL retries for SW work around
//
//*****************************************************************************
//
// Values that can be passed to SysCtl_clearNMIStatus(),
// SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and
// SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by
// SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus().
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to/returned from SysCtl_getInterruptStatus()
// SysCtl_clearInterruptStatus() or SysCtl_setInterruptStatus()
// as the intFlags parameter
//
//*****************************************************************************


//*****************************************************************************
//
// The following are values that can be passed to the SysCtl_clearResetCause()
// API as rstCauses or returned by the SysCtl_getResetCause() API.
//
//*****************************************************************************
//*****************************************************************************
//
// The following values define the adcsocSrc parameter for
// SysCtl_enableExtADCSOCSource() and SysCtl_disableExtADCSOCSource().
//
//*****************************************************************************

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_enablePeripheral()
//! and SysCtl_disablePeripheral() as the \e peripheral parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_PERIPH_CLK_CLA1 = 0x0000, //!< CLA1 clock
    SYSCTL_PERIPH_CLK_DMA = 0x0200, //!< DMA clock
    SYSCTL_PERIPH_CLK_TIMER0 = 0x0300, //!< CPUTIMER0 clock
    SYSCTL_PERIPH_CLK_TIMER1 = 0x0400, //!< CPUTIMER1 clock
    SYSCTL_PERIPH_CLK_TIMER2 = 0x0500, //!< CPUTIMER2 clock
    SYSCTL_PERIPH_CLK_CPUBGCRC = 0x0D00, //!< CPUBGCRC clock
    SYSCTL_PERIPH_CLK_CLA1BGCRC = 0x0E00, //!< CLA1BGCRC clock
    SYSCTL_PERIPH_CLK_HRCAL = 0x1000, //!< HRCAL clock
    SYSCTL_PERIPH_CLK_TBCLKSYNC = 0x1200, //!< TBCLKSYNC clock
    SYSCTL_PERIPH_CLK_ERAD = 0x1800, //!< ERAD clock
    SYSCTL_PERIPH_CLK_EPWM1 = 0x0002, //!< EPWM1 clock
    SYSCTL_PERIPH_CLK_EPWM2 = 0x0102, //!< EPWM2 clock
    SYSCTL_PERIPH_CLK_EPWM3 = 0x0202, //!< EPWM3 clock
    SYSCTL_PERIPH_CLK_EPWM4 = 0x0302, //!< EPWM4 clock
    SYSCTL_PERIPH_CLK_EPWM5 = 0x0402, //!< EPWM5 clock
    SYSCTL_PERIPH_CLK_EPWM6 = 0x0502, //!< EPWM6 clock
    SYSCTL_PERIPH_CLK_EPWM7 = 0x0602, //!< EPWM7 clock
    SYSCTL_PERIPH_CLK_EPWM8 = 0x0702, //!< EPWM8 clock
    SYSCTL_PERIPH_CLK_ECAP1 = 0x0003, //!< ECAP1 clock
    SYSCTL_PERIPH_CLK_ECAP2 = 0x0103, //!< ECAP2 clock
    SYSCTL_PERIPH_CLK_ECAP3 = 0x0203, //!< ECAP3 clock
    SYSCTL_PERIPH_CLK_EQEP1 = 0x0004, //!< EQEP1 clock
    SYSCTL_PERIPH_CLK_EQEP2 = 0x0104, //!< EQEP2 clock
    SYSCTL_PERIPH_CLK_SD1 = 0x0006, //!< SD1 clock
    SYSCTL_PERIPH_CLK_SD2 = 0x0106, //!< SD2 clock
    SYSCTL_PERIPH_CLK_SCIA = 0x0007, //!< SCI_A clock
    SYSCTL_PERIPH_CLK_SCIB = 0x0107, //!< SCI_B clock
    SYSCTL_PERIPH_CLK_SPIA = 0x0008, //!< SPI_A clock
    SYSCTL_PERIPH_CLK_SPIB = 0x0108, //!< SPI_B clock
    SYSCTL_PERIPH_CLK_I2CA = 0x0009, //!< I2C_A clock
    SYSCTL_PERIPH_CLK_I2CB = 0x0109, //!< I2C_B clock
    SYSCTL_PERIPH_CLK_CANA = 0x000A, //!< CAN_A clock
    SYSCTL_PERIPH_CLK_MCANA = 0x040A, //!< MCAN_A clock
    SYSCTL_PERIPH_CLK_ADCA = 0x000D, //!< ADC_A clock
    SYSCTL_PERIPH_CLK_ADCB = 0x010D, //!< ADC_B clock
    SYSCTL_PERIPH_CLK_ADCC = 0x020D, //!< ADC_C clock
    SYSCTL_PERIPH_CLK_CMPSS1 = 0x000E, //!< CMPSS1 clock
    SYSCTL_PERIPH_CLK_CMPSS2 = 0x010E, //!< CMPSS2 clock
    SYSCTL_PERIPH_CLK_CMPSS3 = 0x020E, //!< CMPSS3 clock
    SYSCTL_PERIPH_CLK_CMPSS4 = 0x030E, //!< CMPSS4 clock
    SYSCTL_PERIPH_CLK_DACA = 0x1010, //!< DAC_A clock
    SYSCTL_PERIPH_CLK_DACB = 0x1110, //!< DAC_B clock
    SYSCTL_PERIPH_CLK_CLB1 = 0x0011, //!< CLB1 clock
    SYSCTL_PERIPH_CLK_CLB2 = 0x0111, //!< CLB2 clock
    SYSCTL_PERIPH_CLK_CLB3 = 0x0211, //!< CLB3 clock
    SYSCTL_PERIPH_CLK_CLB4 = 0x0311, //!< CLB4 clock
    SYSCTL_PERIPH_CLK_FSITXA = 0x0012, //!< FSITX_A clock
    SYSCTL_PERIPH_CLK_FSIRXA = 0x0112, //!< FSIRX_A clock
    SYSCTL_PERIPH_CLK_LINA = 0x0013, //!< LIN_A clock
    SYSCTL_PERIPH_CLK_LINB = 0x0113, //!< LIN_B clock
    SYSCTL_PERIPH_CLK_PMBUSA = 0x0014, //!< PMBUS_A clock
    SYSCTL_PERIPH_CLK_DCC0 = 0x0015, //!< DCC0 clock
    SYSCTL_PERIPH_CLK_DCC1 = 0x0115, //!< DCC1 clock
    SYSCTL_PERIPH_CLK_HICA = 0x0019, //!< HICA clock
    SYSCTL_PERIPH_CLK_AESA = 0x001A, //!< AESA clock
    SYSCTL_PERIPH_CLK_EPG1 = 0x001B  //!< EPG1 clock
} SysCtl_PeripheralPCLOCKCR;

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_resetPeripheral() as
//! the \e peripheral parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_PERIPH_RES_CPU1CLA1 = 0x0000, //!< Reset CPU1_CLA1 clock
    SYSCTL_PERIPH_RES_CPU1CPUBGCRC = 0x0D00, //!< Reset CPU1_CPUBGCRC clock
    SYSCTL_PERIPH_RES_CPU1CLA1BGCRC = 0x0E00, //!< Reset CPU1_CLA1BGCRC clock
    SYSCTL_PERIPH_RES_CPU1ERAD = 0x1800, //!< Reset CPU1_ERAD clock
    SYSCTL_PERIPH_RES_EPWM1 = 0x0002, //!< Reset EPWM1 clock
    SYSCTL_PERIPH_RES_EPWM2 = 0x0102, //!< Reset EPWM2 clock
    SYSCTL_PERIPH_RES_EPWM3 = 0x0202, //!< Reset EPWM3 clock
    SYSCTL_PERIPH_RES_EPWM4 = 0x0302, //!< Reset EPWM4 clock
    SYSCTL_PERIPH_RES_EPWM5 = 0x0402, //!< Reset EPWM5 clock
    SYSCTL_PERIPH_RES_EPWM6 = 0x0502, //!< Reset EPWM6 clock
    SYSCTL_PERIPH_RES_EPWM7 = 0x0602, //!< Reset EPWM7 clock
    SYSCTL_PERIPH_RES_EPWM8 = 0x0702, //!< Reset EPWM8 clock
    SYSCTL_PERIPH_RES_ECAP1 = 0x0003, //!< Reset ECAP1 clock
    SYSCTL_PERIPH_RES_ECAP2 = 0x0103, //!< Reset ECAP2 clock
    SYSCTL_PERIPH_RES_ECAP3 = 0x0203, //!< Reset ECAP3 clock
    SYSCTL_PERIPH_RES_EQEP1 = 0x0004, //!< Reset EQEP1 clock
    SYSCTL_PERIPH_RES_EQEP2 = 0x0104, //!< Reset EQEP2 clock
    SYSCTL_PERIPH_RES_SD1 = 0x0006, //!< Reset SD1 clock
    SYSCTL_PERIPH_RES_SD2 = 0x0106, //!< Reset SD2 clock
    SYSCTL_PERIPH_RES_SCIA = 0x0007, //!< Reset SCI_A clock
    SYSCTL_PERIPH_RES_SCIB = 0x0107, //!< Reset SCI_B clock
    SYSCTL_PERIPH_RES_SPIA = 0x0008, //!< Reset SPI_A clock
    SYSCTL_PERIPH_RES_SPIB = 0x0108, //!< Reset SPI_B clock
    SYSCTL_PERIPH_RES_I2CA = 0x0009, //!< Reset I2C_A clock
    SYSCTL_PERIPH_RES_I2CB = 0x0109, //!< Reset I2C_B clock
    SYSCTL_PERIPH_RES_CANA = 0x000A, //!< Reset CAN_A clock
    SYSCTL_PERIPH_RES_MCANA = 0x040A, //!< Reset MCAN_A clock
    SYSCTL_PERIPH_RES_ADCA = 0x000D, //!< Reset ADC_A clock
    SYSCTL_PERIPH_RES_ADCB = 0x010D, //!< Reset ADC_B clock
    SYSCTL_PERIPH_RES_ADCC = 0x020D, //!< Reset ADC_C clock
    SYSCTL_PERIPH_RES_CMPSS1 = 0x000E, //!< Reset CMPSS1 clock
    SYSCTL_PERIPH_RES_CMPSS2 = 0x010E, //!< Reset CMPSS2 clock
    SYSCTL_PERIPH_RES_CMPSS3 = 0x020E, //!< Reset CMPSS3 clock
    SYSCTL_PERIPH_RES_CMPSS4 = 0x030E, //!< Reset CMPSS4 clock
    SYSCTL_PERIPH_RES_DACA = 0x1010, //!< Reset DAC_A clock
    SYSCTL_PERIPH_RES_DACB = 0x1110, //!< Reset DAC_B clock
    SYSCTL_PERIPH_RES_CLB1 = 0x0011, //!< Reset CLB1 clock
    SYSCTL_PERIPH_RES_CLB2 = 0x0111, //!< Reset CLB2 clock
    SYSCTL_PERIPH_RES_CLB3 = 0x0211, //!< Reset CLB3 clock
    SYSCTL_PERIPH_RES_CLB4 = 0x0311, //!< Reset CLB4 clock
    SYSCTL_PERIPH_RES_FSITXA = 0x0012, //!< Reset FSITX_A clock
    SYSCTL_PERIPH_RES_FSIRXA = 0x0112, //!< Reset FSIRX_A clock
    SYSCTL_PERIPH_RES_LINA = 0x0013, //!< Reset LIN_A clock
    SYSCTL_PERIPH_RES_LINB = 0x0113, //!< Reset LIN_B clock
    SYSCTL_PERIPH_RES_PMBUSA = 0x0014, //!< Reset PMBUS_A clock
    SYSCTL_PERIPH_RES_DCC0 = 0x0015, //!< Reset DCC0 clock
    SYSCTL_PERIPH_RES_DCC1 = 0x0115, //!< Reset DCC1 clock
    SYSCTL_PERIPH_RES_HICA = 0x0019, //!< Reset HIC_A clock
    SYSCTL_PERIPH_RES_AESA = 0x001A, //!< Reset AESA clock
    SYSCTL_PERIPH_RES_EPG1 = 0x001B  //!< Reset EPG1 clock
} SysCtl_PeripheralSOFTPRES;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setWatchdogPredivider() as the \e predivider parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_WD_PREDIV_2    = 0x800,  //!< PREDIVCLK = INTOSC1 / 2
    SYSCTL_WD_PREDIV_4    = 0x900,  //!< PREDIVCLK = INTOSC1 / 4
    SYSCTL_WD_PREDIV_8    = 0xA00,  //!< PREDIVCLK = INTOSC1 / 8
    SYSCTL_WD_PREDIV_16   = 0xB00,  //!< PREDIVCLK = INTOSC1 / 16
    SYSCTL_WD_PREDIV_32   = 0xC00,  //!< PREDIVCLK = INTOSC1 / 32
    SYSCTL_WD_PREDIV_64   = 0xD00,  //!< PREDIVCLK = INTOSC1 / 64
    SYSCTL_WD_PREDIV_128  = 0xE00,  //!< PREDIVCLK = INTOSC1 / 128
    SYSCTL_WD_PREDIV_256  = 0xF00,  //!< PREDIVCLK = INTOSC1 / 256
    SYSCTL_WD_PREDIV_512  = 0x000,  //!< PREDIVCLK = INTOSC1 / 512
    SYSCTL_WD_PREDIV_1024 = 0x100,  //!< PREDIVCLK = INTOSC1 / 1024
    SYSCTL_WD_PREDIV_2048 = 0x200,  //!< PREDIVCLK = INTOSC1 / 2048
    SYSCTL_WD_PREDIV_4096 = 0x300   //!< PREDIVCLK = INTOSC1 / 4096
} SysCtl_WDPredivider;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setWatchdogPrescaler() as the \e prescaler parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_WD_PRESCALE_1  = 1,      //!< WDCLK = PREDIVCLK / 1
    SYSCTL_WD_PRESCALE_2  = 2,      //!< WDCLK = PREDIVCLK / 2
    SYSCTL_WD_PRESCALE_4  = 3,      //!< WDCLK = PREDIVCLK / 4
    SYSCTL_WD_PRESCALE_8  = 4,      //!< WDCLK = PREDIVCLK / 8
    SYSCTL_WD_PRESCALE_16 = 5,      //!< WDCLK = PREDIVCLK / 16
    SYSCTL_WD_PRESCALE_32 = 6,      //!< WDCLK = PREDIVCLK / 32
    SYSCTL_WD_PRESCALE_64 = 7       //!< WDCLK = PREDIVCLK / 64
} SysCtl_WDPrescaler;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setWatchdogMode() as the \e prescaler parameter.
//
//*****************************************************************************
typedef enum
{
    //! Watchdog can generate a reset signal
    SYSCTL_WD_MODE_RESET,
    //! Watchdog can generate an interrupt signal; reset signal is disabled
    SYSCTL_WD_MODE_INTERRUPT
} SysCtl_WDMode;

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_setLowSpeedClock() as
//! the \e prescaler parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_LSPCLK_PRESCALE_1    = 0,    //!< LSPCLK = SYSCLK / 1
    SYSCTL_LSPCLK_PRESCALE_2    = 1,    //!< LSPCLK = SYSCLK / 2
    SYSCTL_LSPCLK_PRESCALE_4    = 2,    //!< LSPCLK = SYSCLK / 4 (default)
    SYSCTL_LSPCLK_PRESCALE_6    = 3,    //!< LSPCLK = SYSCLK / 6
    SYSCTL_LSPCLK_PRESCALE_8    = 4,    //!< LSPCLK = SYSCLK / 8
    SYSCTL_LSPCLK_PRESCALE_10   = 5,    //!< LSPCLK = SYSCLK / 10
    SYSCTL_LSPCLK_PRESCALE_12   = 6,    //!< LSPCLK = SYSCLK / 12
    SYSCTL_LSPCLK_PRESCALE_14   = 7     //!< LSPCLK = SYSCLK / 14
} SysCtl_LSPCLKPrescaler;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setPeripheralAccessControl() and SysCtl_getPeripheralAccessControl()
//! as the \e peripheral parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_ACCESS_ADCA          = 0x0, //!< ADCA access
    SYSCTL_ACCESS_ADCB          = 0x2, //!< ADCB access
    SYSCTL_ACCESS_ADCC          = 0x4, //!< ADCC access
    SYSCTL_ACCESS_CMPSS1        = 0x10, //!< CMPSS1 access
    SYSCTL_ACCESS_CMPSS2        = 0x12, //!< CMPSS2 access
    SYSCTL_ACCESS_CMPSS3        = 0x14, //!< CMPSS3 access
    SYSCTL_ACCESS_CMPSS4        = 0x16, //!< CMPSS4 access
    SYSCTL_ACCESS_DACA          = 0x28, //!< DACA access
    SYSCTL_ACCESS_DACB          = 0x2A, //!< DACB access
    SYSCTL_ACCESS_EPWM1         = 0x48, //!< EPWM1 access
    SYSCTL_ACCESS_EPWM2         = 0x4A, //!< EPWM2 access
    SYSCTL_ACCESS_EPWM3         = 0x4C, //!< EPWM3 access
    SYSCTL_ACCESS_EPWM4         = 0x4E, //!< EPWM4 access
    SYSCTL_ACCESS_EPWM5         = 0x50, //!< EPWM5 access
    SYSCTL_ACCESS_EPWM6         = 0x52, //!< EPWM6 access
    SYSCTL_ACCESS_EPWM7         = 0x54, //!< EPWM7 access
    SYSCTL_ACCESS_EPWM8         = 0x56, //!< EPWM8 access
    SYSCTL_ACCESS_EQEP1         = 0x70, //!< EQEP1 access
    SYSCTL_ACCESS_EQEP2         = 0x72, //!< EQEP2 access
    SYSCTL_ACCESS_ECAP1         = 0x80, //!< ECAP1 access
    SYSCTL_ACCESS_ECAP2         = 0x82, //!< ECAP2 access
    SYSCTL_ACCESS_ECAP3         = 0x84, //!< ECAP3 access
    SYSCTL_ACCESS_SDFM1         = 0xA8, //!< SDFM1 access
    SYSCTL_ACCESS_SDFM2         = 0xAA, //!< SDFM2 access
    SYSCTL_ACCESS_CLB1          = 0xB0, //!< CLB1 access
    SYSCTL_ACCESS_CLB2          = 0xB2, //!< CLB2 access
    SYSCTL_ACCESS_CLB3          = 0xB4, //!< CLB3 access
    SYSCTL_ACCESS_CLB4          = 0xB6, //!< CLB4 access
    SYSCTL_ACCESS_SCIA          = 0x100, //!< SCIA access
    SYSCTL_ACCESS_SCIB          = 0x102, //!< SCIB access
    SYSCTL_ACCESS_SPIA          = 0x110, //!< SPIA access
    SYSCTL_ACCESS_SPIB          = 0x112, //!< SPIB access
    SYSCTL_ACCESS_I2CA          = 0x120, //!< I2CA access
    SYSCTL_ACCESS_I2CB          = 0x122, //!< I2CB access
    SYSCTL_ACCESS_PMBUSA       = 0x130, //!< PMBUS_A access
    SYSCTL_ACCESS_LINA         = 0x138, //!< LIN_A access
    SYSCTL_ACCESS_LINB         = 0x13A, //!< LIN_B access
    SYSCTL_ACCESS_CANA         = 0x140, //!< DCANA access
    SYSCTL_ACCESS_MCANA         = 0x148, //!< MCANA access
    SYSCTL_ACCESS_FSIATX        = 0x158, //!< FSIATX access
    SYSCTL_ACCESS_FSIARX        = 0x15A, //!< FSIARX access
    SYSCTL_ACCESS_HRPWMA       = 0x1AA, //!< HRPWM_A access
    SYSCTL_ACCESS_HICA         = 0x1AC, //!< HIC_A access
    SYSCTL_ACCESS_AESA          = 0x1AE  //!< AESA access
} SysCtl_AccessPeripheral;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setPeripheralAccessControl() and SysCtl_getPeripheralAccessControl()
//! as the \e master parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_ACCESS_CPU1       = 0U,   //!< CPU access to the peripheral
    SYSCTL_ACCESS_DMA1       = 4U,   //!< DMA access to the peripheral
    SYSCTL_ACCESS_HICMASTER  = 6U    //!< HICA access to the peripheral
} SysCtl_AccessMaster;
//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setPeripheralAccessControl() as the \e permission parameter.
//
//*****************************************************************************
typedef enum
{
    //! Full Access for both read and write.
    SYSCTL_ACCESS_FULL      = 3U,
    //! Protected RD access such that FIFOs. Clear on read, registers are not
    //! changed and no write access.
    SYSCTL_ACCESS_PROTECTED = 2U,
    //! No read or write access.
    SYSCTL_ACCESS_NONE      = 0U
} SysCtl_AccessPermission;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_selectClockOutSource() as the \e source parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_CLOCKOUT_PLLSYS     = 0U,   //!< PLL System Clock post SYSCLKDIV
    SYSCTL_CLOCKOUT_PLLRAW     = 1U,   //!< PLL Raw Clock
    SYSCTL_CLOCKOUT_SYSCLK     = 2U,   //!< CPU System Clock
    SYSCTL_CLOCKOUT_INTOSC1    = 5U,   //!< Internal Oscillator 1
    SYSCTL_CLOCKOUT_INTOSC2    = 6U,   //!< Internal Oscillator 2
    SYSCTL_CLOCKOUT_XTALOSC    = 7U,   //!< External Oscillator
} SysCtl_ClockOut;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setExternalOscMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_XTALMODE_CRYSTAL = 1U,   //!< XTAL Oscillator Crystal Mode
    SYSCTL_XTALMODE_SINGLE  = 2U    //!< XTAL Oscillator Single-Ended Mode
} SysCtl_ExternalOscMode;


//*****************************************************************************
//
//! The following values define the \e syncSrc parameter for
//! SysCtl_setSyncOutputConfig().
//
//*****************************************************************************
typedef enum
{
    SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT  = 0X0U,  //!< EPWM1SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_EPWM2SYNCOUT  = 0X1U,  //!< EPWM2SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_EPWM3SYNCOUT  = 0X2U,  //!< EPWM3SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT  = 0X3U,  //!< EPWM4SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_EPWM5SYNCOUT  = 0X4U,  //!< EPWM5SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_EPWM6SYNCOUT  = 0X5U,  //!< EPWM6SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT  = 0X6U,  //!< EPWM7SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_ECAP1SYNCOUT  = 0x18,  //!< ECAP1SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_ECAP2SYNCOUT  = 0x19,  //!< ECAP2SYNCOUT --> EXTSYNCOUT
    SYSCTL_SYNC_OUT_SRC_ECAP3SYNCOUT  = 0x20,  //!< ECAP3SYNCOUT --> EXTSYNCOUT

} SysCtl_SyncOutputSource;

//*****************************************************************************
//
//! The following values define the \e parametric parameter for
//! SysCtl_getDeviceParametric().
//
//*****************************************************************************
typedef enum
{
    SYSCTL_DEVICE_QUAL,       //!< Device Qualification Status
    SYSCTL_DEVICE_PINCOUNT,   //!< Device Pin Count
    SYSCTL_DEVICE_INSTASPIN,  //!< Device InstaSPIN Feature Set
    SYSCTL_DEVICE_FLASH,      //!< Device Flash size (KB)
    SYSCTL_DEVICE_FAMILY,     //!< Device Family
    SYSCTL_DEVICE_PARTNO,     //!< Device Part Number
    SYSCTL_DEVICE_CLASSID     //!< Device Class ID
} SysCtl_DeviceParametric;

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_configureType()
//! as the \e peripheral parameter.
//
//*****************************************************************************
typedef enum
{
    //!Configure ECAP Type for the device
    SYSCTL_ECAPTYPE = 0x1,
    //!Configure SDFM Type for the device
    SYSCTL_SDFMTYPE = 0x2,

}SysCtl_SelType;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setXClk() as \e divider parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_XCLKOUT_DIV_1  = 0,      //!<  XCLKOUT =  XCLKOUT / 1
    SYSCTL_XCLKOUT_DIV_2  = 1,      //!<  XCLKOUT =  XCLKOUT / 2
    SYSCTL_XCLKOUT_DIV_4  = 2,      //!<  XCLKOUT =  XCLKOUT / 4
    SYSCTL_XCLKOUT_DIV_8  = 3       //!<  XCLKOUT =  XCLKOUT / 8

}SysCtl_XClkDivider;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setMCANClk() as \e divider parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_MCANCLK_DIV_1  = 0x0,   //!<  MCAN clock =  MCAN clock / 1
    SYSCTL_MCANCLK_DIV_2  = 0x1,   //!<  MCAN clock =  MCAN clock / 2
    SYSCTL_MCANCLK_DIV_3  = 0x2,   //!<  MCAN clock =  MCAN clock / 3
    SYSCTL_MCANCLK_DIV_4  = 0x3,   //!<  MCAN clock =  MCAN clock / 4
    SYSCTL_MCANCLK_DIV_5  = 0x4,   //!<  MCAN clock =  MCAN clock / 5
    SYSCTL_MCANCLK_DIV_6  = 0x5,   //!<  MCAN clock =  MCAN clock / 6
    SYSCTL_MCANCLK_DIV_7  = 0x6,   //!<  MCAN clock =  MCAN clock / 7
    SYSCTL_MCANCLK_DIV_8  = 0x7,   //!<  MCAN clock =  MCAN clock / 8
    SYSCTL_MCANCLK_DIV_9  = 0x8,   //!<  MCAN clock =  MCAN clock / 9
    SYSCTL_MCANCLK_DIV_10 = 0x9,   //!<  MCAN clock =  MCAN clock / 10
    SYSCTL_MCANCLK_DIV_11 = 0xA,   //!<  MCAN clock =  MCAN clock / 11
    SYSCTL_MCANCLK_DIV_12 = 0xB,   //!<  MCAN clock =  MCAN clock / 12
    SYSCTL_MCANCLK_DIV_13 = 0xC,   //!<  MCAN clock =  MCAN clock / 13
    SYSCTL_MCANCLK_DIV_14 = 0xD,   //!<  MCAN clock =  MCAN clock / 14
    SYSCTL_MCANCLK_DIV_15 = 0xE,   //!<  MCAN clock =  MCAN clock / 15
    SYSCTL_MCANCLK_DIV_16 = 0xF,   //!<  MCAN clock =  MCAN clock / 16
    SYSCTL_MCANCLK_DIV_17 = 0x10,  //!<  MCAN clock =  MCAN clock / 17
    SYSCTL_MCANCLK_DIV_18 = 0x11,  //!<  MCAN clock =  MCAN clock / 18
    SYSCTL_MCANCLK_DIV_19 = 0x12,  //!<  MCAN clock =  MCAN clock / 19
    SYSCTL_MCANCLK_DIV_20 = 0x13   //!<  MCAN clock =  MCAN clock / 20

}SysCtl_MCANClkDivider;

//*****************************************************************************
//
//! The following are values that can be passed to
//! SysCtl_setCputimer2Clk() as \e divider parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_TMR2CLKPRESCALE_1,   //!<  Cputimer2 clock =  Cputimer2 clock / 1
    SYSCTL_TMR2CLKPRESCALE_2,   //!<  Cputimer2 clock =  Cputimer2 clock / 2
    SYSCTL_TMR2CLKPRESCALE_4,   //!<  Cputimer2 clock =  Cputimer2 clock / 4
    SYSCTL_TMR2CLKPRESCALE_8,   //!<  Cputimer2 clock =  Cputimer2 clock / 8
    SYSCTL_TMR2CLKPRESCALE_16   //!<  Cputimer2 clock =  Cputimer2 clock / 16

}SysCtl_Cputimer2ClkDivider;

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_setCputimer2Clk()
//! as \e source parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_TMR2CLKSRCSEL_SYSCLK     = 0U,   //!< System Clock
    SYSCTL_TMR2CLKSRCSEL_INTOSC1    = 1U,   //!< Internal Oscillator 1
    SYSCTL_TMR2CLKSRCSEL_INTOSC2    = 2U,   //!< Internal Oscillator 2
    SYSCTL_TMR2CLKSRCSEL_XTAL       = 3U,   //!< Crystal oscillator
    SYSCTL_TMR2CLKSRCSEL_AUXPLLCLK  = 6U    //!< Aux PLL CLock

}SysCtl_Cputimer2ClkSource;

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_lockClkConfig()
//! as the \e peripheral parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_REG_SEL_CLKSRCCTL1  = 0x0000,  //!< CLKSRCCTL1 lock
    SYSCTL_REG_SEL_CLKSRCCTL2  = 0x0100,  //!< CLKSRCCTL2 lock
    SYSCTL_REG_SEL_CLKSRCCTL3  = 0x0200,  //!< CLKSRCCTL3 lock
    SYSCTL_REG_SEL_SYSPLLCTL1  = 0x0300,  //!< SYSPLLCTL1 lock
    SYSCTL_REG_SEL_SYSPLLMULT  = 0x0600,  //!< SYSPLLMULT lock
    SYSCTL_REG_SEL_SYSCLKDIVSEL  = 0x0B00,  //!< SYSCLKDIVSEL lock
    SYSCTL_REG_SEL_AUXCLKDIVSEL  = 0x0C00,  //!< AUXCLKDIVSEL lock
    SYSCTL_REG_SEL_PERCLKDIVSEL  = 0x0D00,  //!< PERCLKDIVSEL lock
    SYSCTL_REG_SEL_LOSPCP  = 0x0F00,  //!< LOSPCP lock
    SYSCTL_REG_SEL_XTALCR  = 0x1000   //!< XTALCR lock
} SysCtl_ClkRegSel;

//*****************************************************************************
//
//! The following are values that can be passed to SysCtl_lockSysConfig()
//! as the \e peripheral parameter.
//
//*****************************************************************************
typedef enum
{
    SYSCTL_REG_SEL_PIEVERRADDR  = 0x0200,  //!< PIEVERRADDR lock
    SYSCTL_REG_SEL_PCLKCR0  = 0x0300,  //!< PCLKCR0 lock
    SYSCTL_REG_SEL_PCLKCR2  = 0x0500,  //!< PCLKCR2 lock
    SYSCTL_REG_SEL_PCLKCR3  = 0x0600,  //!< PCLKCR3 lock
    SYSCTL_REG_SEL_PCLKCR4  = 0x0700,  //!< PCLKCR4 lock
    SYSCTL_REG_SEL_PCLKCR6  = 0x0900,  //!< PCLKCR6 lock
    SYSCTL_REG_SEL_PCLKCR7  = 0x0A00,  //!< PCLKCR7 lock
    SYSCTL_REG_SEL_PCLKCR8  = 0x0B00,  //!< PCLKCR8 lock
    SYSCTL_REG_SEL_PCLKCR9  = 0x0C00,  //!< PCLKCR9 lock
    SYSCTL_REG_SEL_PCLKCR10  = 0x0D00,  //!< PCLKCR10 lock
    SYSCTL_REG_SEL_PCLKCR13  = 0x1000,  //!< PCLKCR13 lock
    SYSCTL_REG_SEL_PCLKCR14  = 0x1100,  //!< PCLKCR14 lock
    SYSCTL_REG_SEL_PCLKCR16  = 0x1300,  //!< PCLKCR16 lock
    SYSCTL_REG_SEL_LPMCR  = 0x1500,  //!< LPMCR lock
    SYSCTL_REG_SEL_GPIOLPMSEL0  = 0x1600,  //!< GPIOLPMSEL0 lock
    SYSCTL_REG_SEL_GPIOLPMSEL1  = 0x1700,  //!< GPIOLPMSEL1 lock
    SYSCTL_REG_SEL_PCLKCR17  = 0x1800,  //!< PCLKCR17 lock
    SYSCTL_REG_SEL_PCLKCR18  = 0x1900,  //!< PCLKCR18 lock
    SYSCTL_REG_SEL_PCLKCR19  = 0x1A00,  //!< PCLKCR19 lock
    SYSCTL_REG_SEL_PCLKCR20  = 0x1B00,  //!< PCLKCR20 lock
    SYSCTL_REG_SEL_PCLKCR21  = 0x1C00,  //!< PCLKCR21 lock
    SYSCTL_REG_SEL_PCLKCR22  = 0x1D00,  //!< PCLKCR22 lock
    SYSCTL_REG_SEL_PCLKCR25  = 0x0101,  //!< PCLKCR25 lock
    SYSCTL_REG_SEL_PCLKCR26  = 0x0201,  //!< PCLKCR26 lock
    SYSCTL_REG_SEL_PCLKCR27  = 0x0301   //!< PCLKCR27 lock
} SysCtl_CpuRegSel;


//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Wrapper function for Device_cal function
//!
//! \param None
//!
//! This is a wrapper function for the Device_cal function available in the OTP
//! memory.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_deviceCal(void)
{

    //
    // Call the Device_cal function
    //
    ((void (*)(void))((uintptr_t)0x003fce6c))();

}

//*****************************************************************************
//
//! Resets a peripheral
//!
//! \param peripheral is the peripheral to reset.
//!
//! This function uses the SOFTPRESx registers to reset a specified peripheral.
//! Module registers will be returned to their reset states.
//!
//! \note This includes registers containing trim values.The peripheral
//! software reset needed by CPU2 can be communicated to CPU1 via
//! IPC for all shared peripherals.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral)
{
    uint16_t regIndex;
    uint16_t bitIndex;

    //
    // Decode the peripheral variable.
    //
    regIndex = (uint16_t)2U * ((uint16_t)peripheral &
                               (uint16_t)0x001FU);
    bitIndex = ((uint16_t)peripheral & 0x1F00U) >>
               0x0008U;

    __eallow();

    //
    // Sets the appropriate reset bit and then clears it.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D000U + 0x82U + regIndex)))) |=
        ((uint32_t)1U << bitIndex);
    (*((volatile uint32_t *)((uintptr_t)(0x0005D000U + 0x82U + regIndex)))) &=
        ~((uint32_t)1U << bitIndex);

    //
    // Call Device_cal function
    //
    if(((peripheral & 0x001FU) == 0xDU) ||      // ADCx
       ((peripheral & 0x001FU) == 0x10U)        // DACx
       )
    {
        SysCtl_deviceCal();
    }

    __edis();
}

//*****************************************************************************
//
//! Enables a peripheral.
//!
//! \param peripheral is the peripheral to enable.
//!
//! Peripherals are enabled with this function.  At power-up, all peripherals
//! are disabled; they must be enabled in order to operate or respond to
//! register reads/writes.
//!
//! \note Note that there should be atleast 5 cycles delay between enabling the
//! peripheral clock and accessing the peripheral registers. The delay should be
//! added by the user if the peripheral is accessed immediately after this
//! function call.
//! Use asm(" RPT #5 || NOP"); to add 5 cycle delay post this function call.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral)
{
    uint16_t regIndex;
    uint16_t bitIndex;

    //
    // Decode the peripheral variable.
    //
    regIndex = (uint16_t)2U * ((uint16_t)peripheral &
                               (uint16_t)0x001FU);
    bitIndex = ((uint16_t)peripheral & 0x1F00U) >>
               0x0008U;

    __eallow();

    //
    // Turn on the module clock.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x22U + regIndex)))) |=
        ((uint32_t)1U << bitIndex);
    __edis();
}

//*****************************************************************************
//
//! Disables a peripheral.
//!
//! \param peripheral is the peripheral to disable.
//!
//! Peripherals are disabled with this function.  Once disabled, they will not
//! operate or respond to register reads/writes.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral)
{
    uint16_t regIndex;
    uint16_t bitIndex;

    //
    // Decode the peripheral variable.
    //
    regIndex = (uint16_t)2U * ((uint16_t)peripheral &
                               (uint16_t)0x001FU);
    bitIndex = ((uint16_t)peripheral & 0x1F00U) >>
               0x0008U;

    __eallow();

    //
    // Turn off the module clock.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x22U + regIndex)))) &=
        ~((uint32_t)1U << bitIndex);
    __edis();
}

//*****************************************************************************
//
//! Resets the device.
//!
//! This function performs a watchdog reset of the device.
//!
//! \return This function does not return.
//
//*****************************************************************************
static inline void
SysCtl_resetDevice(void)
{
    //
    // Write an incorrect check value to the watchdog control register
    // This will cause a device reset
    //
    __eallow();

    //
    // Enable the watchdog
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) = 0x0028U;

    //
    // Write a bad check value
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) = 0U;

    __edis();

    //
    // The device should have reset, so this should never be reached.  Just in
    // case, loop forever.
    //
    while(1)
    {
    }
}

//*****************************************************************************
//
//! Gets the reason for a reset.
//!
//! This function will return the reason(s) for a reset.  Since the reset
//! reasons are sticky until either cleared by software or an external reset,
//! multiple reset reasons may be returned if multiple resets have occurred.
//! The reset reason will be a logical OR of
//! - \b SYSCTL_CAUSE_POR - Power-on reset
//! - \b SYSCTL_CAUSE_XRS - External reset pin
//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset
//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset
//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM
//!
//! \note If you re-purpose the reserved boot ROM RAM, the POR and XRS reset
//! statuses won't be accurate.
//!
//! \return Returns the reason(s) for a reset.
//
//*****************************************************************************
static inline uint32_t
SysCtl_getResetCause(void)
{
    uint32_t resetCauses;

    //
    // Read CPU reset register
    //
    resetCauses = (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x80U)))) &
                  ((uint32_t)0x1U | (uint32_t)0x2U |
                   (uint32_t)0x4U |
                   (uint32_t)0x8U |
                   (uint32_t)0x100U
                   );

    //
    // Set POR and XRS Causes from boot ROM Status
    //
    if(((*((volatile uint32_t *)((uintptr_t)(0x0002U)))) & (uint32_t)0x2000U) ==
       (uint32_t)0x2000U)
    {
        resetCauses |= 0x1U;
    }
    if(((*((volatile uint32_t *)((uintptr_t)(0x0002U)))) & (uint32_t)0x1000U) ==
       (uint32_t)0x1000U)
    {
        resetCauses |= 0x2U;
    }

    //
    // Return the reset reasons.
    //
    return(resetCauses);
}

//*****************************************************************************
//
//! Clears reset reasons.
//!
//! \param rstCauses are the reset causes to be cleared; must be a logical
//! OR of \b SYSCTL_CAUSE_POR, \b SYSCTL_CAUSE_XRS, \b SYSCTL_CAUSE_WDRS,
//! \b SYSCTL_CAUSE_NMIWDRS,
//! and/or \b SYSCTL_CAUSE_SCCRESET.
//!
//! This function clears the specified sticky reset reasons.  Once cleared,
//! another reset for the same reason can be detected, and a reset for a
//! different reason can be distinguished (instead of having two reset causes
//! set).  If the reset reason is used by an application, all reset causes
//! should be cleared after they are retrieved with SysCtl_getResetCause().
//!
//! \note Some reset causes are cleared by the boot ROM.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearResetCause(uint32_t rstCauses)
{
    //
    // Clear the given reset reasons.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x7EU)))) = rstCauses;
}

//*****************************************************************************
//
//! Sets the low speed peripheral clock rate prescaler.
//!
//! \param prescaler is the LSPCLK rate relative to SYSCLK
//!
//! This function configures the clock rate of the low speed peripherals. The
//! \e prescaler parameter is the value by which the SYSCLK rate is divided to
//! get the LSPCLK rate. For example, a \e prescaler of
//! \b SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter
//! of the SYSCLK rate.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler)
{
    //
    // Write the divider selection to the appropriate register.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x0005D200U + 0x2CU)))) =
        ((*((volatile uint32_t *)((uintptr_t)(0x0005D200U + 0x2CU)))) &
         ~(uint32_t)0x7U) | (uint32_t)prescaler;
    __edis();
}

//*****************************************************************************
//
//! Selects a clock source to mux to an external GPIO pin (XCLKOUT).
//!
//! \param source is the internal clock source to be configured.
//!
//! This function configures the specified clock source to be muxed to an
//! external clock out (XCLKOUT) GPIO pin. The \e source parameter may take a
//! value of one of the following values:
//! - \b SYSCTL_CLOCKOUT_PLLSYS
//! - \b SYSCTL_CLOCKOUT_PLLRAW
//! - \b SYSCTL_CLOCKOUT_SYSCLK
//! - \b SYSCTL_CLOCKOUT_INTOSC1
//! - \b SYSCTL_CLOCKOUT_INTOSC2
//! - \b SYSCTL_CLOCKOUT_XTALOSC
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_selectClockOutSource(SysCtl_ClockOut source)
{
    __eallow();

    //
    // Clear clock out source
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0xCU)))) &=
        ~0xFU;

    //
    // Set clock out source
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0xCU)))) |= (uint16_t)source;

    __edis();
}

//*****************************************************************************
//
//! Set the external oscillator mode.
//!
//! \param mode is the external oscillator mode to be configured.
//!
//! This function sets the external oscillator mode specified by the \e mode
//! parameter which may take one of two values:
//! - \b SYSCTL_XTALMODE_CRYSTAL - Crystal Mode
//! - \b SYSCTL_XTALMODE_SINGLE  - Single-Ended Mode
//!
//! \note The external oscillator must be powered off before this configuration
//! can be performed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setExternalOscMode(SysCtl_ExternalOscMode mode)
{
    __eallow();

    switch(mode)
    {
        case SYSCTL_XTALMODE_CRYSTAL:
            //
            // Set mode to Crystal
            //
            (*((volatile uint32_t *)((uintptr_t)(0x0005D200U + 0x32U)))) &= ~(uint32_t)0x2U;
            break;

        case SYSCTL_XTALMODE_SINGLE:
            //
            // Set mode to Single-Ended
            //
            (*((volatile uint32_t *)((uintptr_t)(0x0005D200U + 0x32U)))) |= 0x2U;
            break;

        default:
            //
            // Do nothing. Not a valid mode value.
            //
            break;
    }

    __edis();
}

//*****************************************************************************
//
//! Gets the external oscillator counter value.
//!
//! This function returns the X1 clock counter value. When the return value
//! reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external
//! oscillator (XTAL), an application should call this function to make sure
//! the counter is saturated.
//!
//! \return Returns the value of the 10-bit X1 clock counter.
//
//*****************************************************************************
static inline uint16_t
SysCtl_getExternalOscCounterValue(void)
{
    return((*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x30U)))) & 0x7FFU);
}

//*****************************************************************************
//
//! Clears the external oscillator counter value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearExternalOscCounterValue(void)
{
    (*((volatile uint32_t *)((uintptr_t)(0x0005D200U + 0x30U)))) |= 0x10000U;
}

//*****************************************************************************
//
//! Turns on the specified oscillator sources.
//!
//! \param oscSource is the oscillator source to be configured.
//!
//! This function turns on the oscillator specified by the \e oscSource
//! parameter which may take a value of  \b SYSCTL_OSCSRC_XTAL
//! or \b SYSCTL_OSCSRC_OSC2.
//!
//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_turnOnOsc(uint32_t oscSource)
{
    ;

    __eallow();

    switch(oscSource)
    {
        case 0x00000000U:
            //
            // Turn on INTOSC2
            //
            (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x8U)))) &=
                ~0x8U;
            break;

        case 0x00010000U:
            //
            // Turn on XTALOSC
            //
            (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x32U)))) &= ~0x1U;

            break;

        default:
            //
            // Do nothing. Not a valid oscSource value.
            //
            break;
    }

    __edis();
}

//*****************************************************************************
//
//! Turns off the specified oscillator sources.
//!
//! \param oscSource is the oscillator source to be configured.
//!
//! This function turns off the oscillator specified by the \e oscSource
//! parameter which may take a value of  \b SYSCTL_OSCSRC_XTAL
//! or \b SYSCTL_OSCSRC_OSC2.
//!
//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_turnOffOsc(uint32_t oscSource)
{
    ;

    __eallow();

    switch(oscSource)
    {
        case 0x00000000U:
            //
            // Turn off INTOSC2
            //
            (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x8U)))) |=
                0x8U;
            break;

        case 0x00010000U:
            //
            // Turn off XTALOSC
            //
            (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x32U)))) |= 0x1U;
            break;

        default:
            //
            // Do nothing. Not a valid oscSource value.
            //
            break;
    }

    __edis();
}

//*****************************************************************************
//
//! Enters IDLE mode.
//!
//! This function puts the device into IDLE mode. The CPU clock is gated while
//! all peripheral clocks are left running. Any enabled interrupt will wake the
//! CPU up from IDLE mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enterIdleMode(void)
{
    __eallow();

    //
    // Configure the device to go into IDLE mode when IDLE is executed.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x76U)))) =
                ((*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x76U)))) &
                 ~(uint32_t)0x3U) | 0x0000U;

    __edis();

    __asm(" IDLE");
}

//*****************************************************************************
//
//! Enters STANDBY mode.
//!
//! This function puts the device into STANDBY mode. This will gate both the
//! CPU clock and any peripheral clocks derived from SYSCLK. The watchdog is
//! left active, and an NMI or an optional watchdog interrupt will wake the
//! CPU subsystem from STANDBY mode.
//!
//! GPIOs may be configured to wake the CPU subsystem. See
//! SysCtl_enableLPMWakeupPin().
//!
//! The CPU will receive an interrupt (WAKEINT) on wakeup.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enterStandbyMode(void)
{
    __eallow();

    //
    // Configure the device to go into STANDBY mode when IDLE is executed.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x76U)))) =
                ((*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x76U)))) &
                 ~(uint32_t)0x3U) | 0x0001U;

    __edis();

    __asm(" IDLE");
}

//*****************************************************************************
//
//! Enters HALT mode.
//!
//! This function puts the device into HALT mode. This will gate almost all
//! systems and clocks and allows for the power-down of oscillators and analog
//! blocks. The watchdog may be left clocked to produce a reset. See
//! SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be
//! configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin().
//!
//!
//! The CPU will receive an interrupt (WAKEINT) on wakeup.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enterHaltMode(void)
{
    __eallow();

    //
    // Configure the device to go into HALT mode when IDLE is executed.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x76U)))) =
                ((*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x76U)))) &
                 ~(uint32_t)0x3U) | 0x0002U;

    __edis();

    __asm(" IDLE");
}

//*****************************************************************************
//! Enables a pin to wake up the device from the following mode(s):
//!  - STANDBY
//!  - HALT
//!
//! \param pin is the identifying number of the pin.
//!
//! This function connects a pin to the LPM circuit, allowing an event on the
//! pin to wake up the device when when it is in following mode(s):
//!  - STANDBY
//!  - HALT
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are capable of
//! being connected to the LPM circuit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableLPMWakeupPin(uint32_t pin)
{
    uint32_t pinMask;

    //
    // Check the arguments.
    //
    ;

    pinMask = (uint32_t)1U << (uint32_t)(pin % 32U);

    __eallow();

    if(pin < 32U)
    {
        (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x78U)))) |= pinMask;
    }
    else
    {
        (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x7AU)))) |= pinMask;
    }

    __edis();
}

//*****************************************************************************
//! Disables a pin to wake up the device from the following mode(s):
//!  - STANDBY
//!  - HALT
//!
//! \param pin is the identifying number of the pin.
//!
//! This function disconnects a pin to the LPM circuit, disallowing an event on
//! the pin to wake up the device when when it is in following mode(s):
//!  - STANDBY
//!  - HALT
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are valid.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disableLPMWakeupPin(uint32_t pin)
{
    uint32_t pinMask;

    //
    // Check the arguments.
    //
    ;

    pinMask = (uint32_t)1U << (uint32_t)(pin % 32U);

    __eallow();

    if(pin < 32U)
    {
        (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x78U)))) &= ~pinMask;
    }
    else
    {
        (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x7AU)))) &= ~pinMask;
    }

    __edis();
}

//*****************************************************************************
//
//! Sets the number of cycles to qualify an input on waking from STANDBY mode.
//!
//! \param cycles is the number of OSCCLK cycles.
//!
//! This function sets the number of OSCCLK clock cycles used to qualify the
//! selected inputs when waking from STANDBY mode. The \e cycles parameter
//! should be passed a cycle count between 2 and 65 cycles inclusive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setStandbyQualificationPeriod(uint16_t cycles)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x76U)))) =
                ((*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x76U)))) &
                 ~(uint16_t)0xFCU) |
                ((cycles - (uint16_t)2U) << 2U);

    __edis();
}

//*****************************************************************************
//
//! Enable the device to wake from STANDBY mode upon a watchdog interrupt.
//!
//! \note In order to use this option, you must configure the watchdog to
//! generate an interrupt using SysCtl_setWatchdogMode().
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableWatchdogStandbyWakeup(void)
{
    __eallow();

    //
    // Set the bit enables the watchdog to wake up the device from STANDBY.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x76U)))) |= 0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Disable the device from waking from STANDBY mode upon a watchdog interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disableWatchdogStandbyWakeup(void)
{
    __eallow();

    //
    // Clear the bit enables the watchdog to wake up the device from STANDBY.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x76U)))) &= ~0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Enable the watchdog to run while in HALT mode.
//!
//! This function configures the watchdog to continue to run while in HALT
//! mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the
//! system enters HALT mode. By default the watchdog is gated when the system
//! enters HALT.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableWatchdogInHalt(void)
{
    __eallow();

    //
    // Set the watchdog HALT mode ignore bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x8U)))) |= 0x20U;

    __edis();
}

//*****************************************************************************
//
//! Disable the watchdog from running while in HALT mode.
//!
//! This function gates the watchdog when the system enters HALT mode. INTOSC1
//! and INTOSC2 will be powered down. This is the default behavior of the
//! device.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disableWatchdogInHalt(void)
{
    __eallow();

    //
    // Clear the watchdog HALT mode ignore bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x8U)))) &= ~0x20U;

    __edis();
}

//*****************************************************************************
//
//! Configures whether the watchdog generates a reset or an interrupt signal.
//!
//! \param mode is a flag to select the watchdog mode.
//!
//! This function configures the action taken when the watchdog counter reaches
//! its maximum value. When the \e mode parameter is
//! \b SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog
//! interrupt signal and disables the generation of a reset signal. This will
//! allow the watchdog module to wake up the device from IDLE
//! or STANDBY if desired (see SysCtl_enableWatchdogStandbyWakeup()).
//!
//! When the \e mode parameter is \b SYSCTL_WD_MODE_RESET, the watchdog will
//! be put into reset mode and generation of a watchdog interrupt signal will
//! be disabled. This is how the watchdog is configured by default.
//!
//! \note Check the status of the watchdog interrupt using
//! SysCtl_isWatchdogInterruptActive() before calling this function. If the
//! interrupt is still active, switching from interrupt mode to reset mode will
//! immediately reset the device.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setWatchdogMode(SysCtl_WDMode mode)
{
    __eallow();

    //
    // Either set or clear the WDENINT bit to that will determine whether the
    // watchdog will generate a reset signal or an interrupt signal. Take care
    // not to write a 1 to WDOVERRIDE.
    //
    if(mode == SYSCTL_WD_MODE_INTERRUPT)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x22U)))) =
                ((*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x22U)))) & ~0x1U) |
                0x2U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x22U)))) &= ~(0x2U |
                                             0x1U);
    }

    __edis();
}

//*****************************************************************************
//
//! Gets the status of the watchdog interrupt signal.
//!
//! This function returns the status of the watchdog interrupt signal. If the
//! interrupt is active, this function will return \b true. If \b false, the
//! interrupt is NOT active.
//!
//! \note Make sure to call this function to ensure that the interrupt is not
//! active before making any changes to the configuration of the watchdog to
//! prevent any unexpected behavior. For instance, switching from interrupt
//! mode to reset mode while the interrupt is active will immediately reset the
//! device.
//!
//! \return \b true if the interrupt is active and \b false if it is not.
//
//*****************************************************************************
static inline _Bool
SysCtl_isWatchdogInterruptActive(void)
{
    //
    // If the status bit is cleared, the WDINTn signal is active.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x22U)))) & 0x4U) == 0U);
}

//*****************************************************************************
//
//! Disables the watchdog.
//!
//! This function disables the watchdog timer. Note that the watchdog timer is
//! enabled on reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disableWatchdog(void)
{
    __eallow();

    //
    // Set the disable bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) |= 0x0028U | 0x40U;

    __edis();
}

//*****************************************************************************
//
//! Enables the watchdog.
//!
//! This function enables the watchdog timer. Note that the watchdog timer is
//! enabled on reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableWatchdog(void)
{
    __eallow();

    //
    // Clear the disable bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) = ((*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) &
                                       ~0x40U) | 0x0028U;

    __edis();
}

//*****************************************************************************
//
//! Services the watchdog.
//!
//! This function resets the watchdog.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_serviceWatchdog(void)
{
    __eallow();

    //
    // Enable the counter to be reset and then reset it.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x25U)))) = 0x0055U;
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x25U)))) = 0x00AAU;

    __edis();
}

//*****************************************************************************
//
//! Writes the first key to enter the watchdog reset.
//!
//! This function writes the first key to enter the watchdog reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableWatchdogReset(void)
{
    __eallow();

    //
    // Enable the counter to be reset
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x25U)))) = 0x0055U;

    __edis();
}

//*****************************************************************************
//
//! Writes the second key to reset the watchdog.
//!
//! This function writes the second key to reset the watchdog.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_resetWatchdog(void)
{
    __eallow();

    //
    // Reset the watchdog counter
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x25U)))) = 0x00AAU;
    __edis();
}

//*****************************************************************************
//
//! Sets up watchdog clock (WDCLK) pre-divider.
//!
//! \param predivider is the value that configures the pre-divider.
//!
//! This function sets up the watchdog clock (WDCLK) pre-divider. There are two
//! dividers that scale INTOSC1 to WDCLK. The \e predivider parameter divides
//! INTOSC1 down to PREDIVCLK and the prescaler (set by the
//! SysCtl_setWatchdogPrescaler() function) divides PREDIVCLK down to WDCLK.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setWatchdogPredivider(SysCtl_WDPredivider predivider)
{
    uint16_t regVal;

    regVal = (uint16_t)predivider | (uint16_t)0x0028U;

    __eallow();

    //
    // Write the predivider to the appropriate register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) = ((*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) &
                                       ~(0xF00U)) | regVal;

    __edis();
}

//*****************************************************************************
//
//! Sets up watchdog clock (WDCLK) prescaler.
//!
//! \param prescaler is the value that configures the watchdog clock relative
//! to the value from the pre-divider.
//!
//! This function sets up the watchdog clock (WDCLK) prescaler. There are two
//! dividers that scale INTOSC1 to WDCLK. The predivider (set with the
//! SysCtl_setWatchdogPredivider() function) divides INTOSC1 down to PREDIVCLK
//! and the \e prescaler parameter divides PREDIVCLK down to WDCLK.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler)
{
    uint16_t regVal;

    regVal = (uint16_t)prescaler | (uint16_t)0x0028U;

    __eallow();

    //
    // Write the prescaler to the appropriate register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) = ((*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x29U)))) &
                                       ~(0x7U)) | regVal;

    __edis();
}

//*****************************************************************************
//
//! Gets the watchdog counter value.
//!
//! \return Returns the current value of the 8-bit watchdog counter. If this
//! count value overflows, a watchdog output pulse is generated.
//
//*****************************************************************************
static inline uint16_t
SysCtl_getWatchdogCounterValue(void)
{
    //
    // Read and return the value of the watchdog counter.
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x23U)))));
}

//*****************************************************************************
//
//! Gets the watchdog reset status.
//!
//! This function returns the watchdog reset status. If this function returns
//! \b true, that indicates that a watchdog reset generated the last reset
//! condition. Otherwise, it was an external device or power-up reset
//! condition.
//!
//! \return Returns \b true if the watchdog generated the last reset condition.
//
//*****************************************************************************
static inline _Bool
SysCtl_getWatchdogResetStatus(void)
{
    //
    // Read and return the status of the watchdog reset status flag.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x80U)))) & 0x4U) != 0U);
}

//*****************************************************************************
//
//! Clears the watchdog reset status.
//!
//! This function clears the watchdog reset status. To check if it was set
//! first, see SysCtl_getWatchdogResetStatus().
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearWatchdogResetStatus(void)
{
    __eallow();

    //
    // Read and return the status of the watchdog reset status flag.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7EU)))) = 0x4U;

    __edis();
}

//*****************************************************************************
//
//! Set the minimum threshold value for windowed watchdog
//!
//! \param value is the value to set the window threshold
//!
//! This function sets the minimum threshold value used to define the lower
//! limit of the windowed watchdog functionality.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setWatchdogWindowValue(uint16_t value)
{
    __eallow();

    //
    // Clear the windowed value
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x2AU)))) &= ~0xFFU;

    //
    // Set the windowed value
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x2AU)))) |= (value & 0xFFU);

    __edis();
}

//*****************************************************************************
//
//! Clears the watchdog override.
//!
//! This function clears the watchdog override and locks the watchdog timer
//! module to remain in its prior state which could be either enable /disable.
//! The watchdog timer will remain in this state until the next system reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearWatchdogOverride(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x00007000U + 0x22U)))) |= 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Enable the NMI Global interrupt bit
//!
//! \b Note: This bit should be set after the device security related
//! initialization is complete.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableNMIGlobalInterrupt(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x0U)))) |= 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Read NMI interrupts.
//!
//! Read the current state of NMI interrupt.
//!
//! \return \b true if NMI interrupt is triggered, \b false if not.
//
//*****************************************************************************
static inline _Bool
SysCtl_getNMIStatus(void)
{
    //
    // Read and return the current value of the NMI flag register, masking out
    // all but the NMI bit.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x1U)))) & 0x1U) != 0U);
}

//*****************************************************************************
//
//! Read NMI Flags.
//!
//! Read the current state of individual NMI interrupts
//!
//! \return Value of NMIFLG register. These defines are provided to decode
//! the value:
//! - \b SYSCTL_NMI_NMIINT           -  NMI Interrupt Flag
//! - \b SYSCTL_NMI_CLOCKFAIL        -  Clock Fail Interrupt Flag
//! - \b SYSCTL_NMI_RAMUNCERR        -  RAM Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_FLUNCERR         -  Flash Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_CPU1HWBISTERR    -  HW BIST Error NMI Flag
//! - \b SYSCTL_NMI_SYSDBGNMI        -  System Debug Module NMI Flag
//! - \b SYSCTL_NMI_CLBNMI           -  Reconfigurable Logic NMI Flag
//! - \b SYSCTL_NMI_SWERR            -  SW Error Force NMI Flag
//! - \b SYSCTL_NMI_CRC_FAIL         -  BGCRC calculation failed.
//
//*****************************************************************************
static inline uint16_t
SysCtl_getNMIFlagStatus(void)
{
    //
    // Read and return the current value of the NMI flag register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x1U)))));
}

//*****************************************************************************
//
//! Check if the individual NMI interrupts are set.
//!
//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear.
//! The bit format of this parameter is same as of the NMIFLG register. These
//! defines are provided:
//! - \b SYSCTL_NMI_NMIINT           -  NMI Interrupt Flag
//! - \b SYSCTL_NMI_CLOCKFAIL        -  Clock Fail Interrupt Flag
//! - \b SYSCTL_NMI_RAMUNCERR        -  RAM Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_FLUNCERR         -  Flash Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_CPU1HWBISTERR    -  HW BIST Error NMI Flag
//! - \b SYSCTL_NMI_SYSDBGNMI        -  System Debug Module NMI Flag
//! - \b SYSCTL_NMI_CLBNMI           -  Reconfigurable Logic NMI Flag
//! - \b SYSCTL_NMI_SWERR            -  SW Error Force NMI Flag
//! - \b SYSCTL_NMI_CRC_FAIL         -  BGCRC calculation failed.
//!
//! Check if interrupt flags corresponding to the passed in bit mask are
//! asserted.
//!
//! \return \b true if any of the NMI asked for in the parameter bit mask
//! is set. \b false if none of the NMI requested in the parameter bit mask are
//! set.
//
//*****************************************************************************
static inline _Bool
SysCtl_isNMIFlagSet(uint32_t nmiFlags)
{
    //
    // Check the arguments.
    // Make sure if reserved bits are not set in nmiFlags.
    //
    ;

    //
    // Read the flag register and return true if any of them are set.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x1U)))) & nmiFlags) != 0U);
}

//*****************************************************************************
//
//! Function to clear individual NMI interrupts.
//!
//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear.
//! The bit format of this parameter is same as of the NMIFLG register. These
//! defines are provided:
//! - \b SYSCTL_NMI_NMIINT           -  NMI Interrupt Flag
//! - \b SYSCTL_NMI_CLOCKFAIL        -  Clock Fail Interrupt Flag
//! - \b SYSCTL_NMI_RAMUNCERR        -  RAM Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_FLUNCERR         -  Flash Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_CPU1HWBISTERR    -  HW BIST Error NMI Flag
//! - \b SYSCTL_NMI_SYSDBGNMI        -  System Debug Module NMI Flag
//! - \b SYSCTL_NMI_CLBNMI           -  Reconfigurable Logic NMI Flag
//! - \b SYSCTL_NMI_SWERR            -  SW Error Force NMI Flag
//! - \b SYSCTL_NMI_CRC_FAIL         -  BGCRC calculation failed.
//!
//! Clear NMI interrupt flags that correspond with the passed in bit mask.
//!
//! \b Note: The NMI Interrupt flag is always cleared by default and
//! therefore doesn't have to be included in the bit mask.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearNMIStatus(uint32_t nmiFlags)
{
    //
    // Check the arguments.
    // Make sure if reserved bits are not set in nmiFlags.
    //
    ;

    __eallow();

    //
    // Clear the individual flags as well as NMI Interrupt flag
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x2U)))) = nmiFlags;
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x2U)))) = 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Clear all the NMI Flags that are currently set.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearAllNMIFlags(void)
{
    uint16_t nmiFlags;

    //
    // Read the flag status register and then write to the clear register,
    // clearing all the flags that were returned plus the NMI flag.
    //
    __eallow();

    nmiFlags = SysCtl_getNMIFlagStatus();
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x2U)))) = nmiFlags;
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x2U)))) = 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Function to force individual NMI interrupt fail flags
//!
//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear.
//! The bit format of this parameter is same as of the NMIFLG register. These
//! defines are provided:
//! - \b SYSCTL_NMI_NMIINT           -  NMI Interrupt Flag
//! - \b SYSCTL_NMI_CLOCKFAIL        -  Clock Fail Interrupt Flag
//! - \b SYSCTL_NMI_RAMUNCERR        -  RAM Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_FLUNCERR         -  Flash Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_CPU1HWBISTERR    -  HW BIST Error NMI Flag
//! - \b SYSCTL_NMI_SYSDBGNMI        -  System Debug Module NMI Flag
//! - \b SYSCTL_NMI_CLBNMI           -  Reconfigurable Logic NMI Flag
//! - \b SYSCTL_NMI_SWERR            -  SW Error Force NMI Flag
//! - \b SYSCTL_NMI_CRC_FAIL         -  BGCRC calculation failed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_forceNMIFlags(uint32_t nmiFlags)
{
    //
    // Check the arguments.
    // Make sure if reserved bits are not set in nmiFlags.
    //
    ;

    __eallow();

    //
    // Set the Flags for the individual interrupts in the NMI flag
    // force register
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x3U)))) |= nmiFlags;

    __edis();
}

//*****************************************************************************
//
//! Gets the NMI watchdog counter value.
//!
//! \b Note: The counter is clocked at the SYSCLKOUT rate.
//!
//! \return Returns the NMI watchdog counter register's current value.
//
//*****************************************************************************
static inline uint16_t
SysCtl_getNMIWatchdogCounter(void)
{
    //
    // Read and return the NMI watchdog counter register's value.
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x4U)))));
}

//*****************************************************************************
//
//! Sets the NMI watchdog period value.
//!
//! \param wdPeriod is the 16-bit value at which a reset is generated.
//!
//! This function writes to the NMI watchdog period register that holds the
//! value to which the NMI watchdog counter is compared. When the two registers
//! match, a reset is generated. By default, the period is 0xFFFF.
//!
//! \note If a value smaller than the current counter value is passed into the
//! \e wdPeriod parameter, a NMIRSn will be forced.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod)
{
    __eallow();

    //
    // Write to the period register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x5U)))) = wdPeriod;

    __edis();
}

//*****************************************************************************
//
//! Gets the NMI watchdog period value.
//!
//! \return Returns the NMI watchdog period register's current value.
//
//*****************************************************************************
static inline uint16_t
SysCtl_getNMIWatchdogPeriod(void)
{
    //
    // Read and return the NMI watchdog period register's value.
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x5U)))));
}

//*****************************************************************************
//
//! Read NMI Shadow Flags.
//!
//! Read the current state of individual NMI interrupts
//!
//! \return Value of NMISHDFLG register. These defines are provided to decode
//! the value:
//! - \b SYSCTL_NMI_NMIINT           -  NMI Interrupt Flag
//! - \b SYSCTL_NMI_CLOCKFAIL        -  Clock Fail Interrupt Flag
//! - \b SYSCTL_NMI_RAMUNCERR        -  RAM Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_FLUNCERR         -  Flash Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_CPU1HWBISTERR    -  HW BIST Error NMI Flag
//! - \b SYSCTL_NMI_SYSDBGNMI        -  System Debug Module NMI Flag
//! - \b SYSCTL_NMI_CLBNMI           -  Reconfigurable Logic NMI Flag
//! - \b SYSCTL_NMI_SWERR            -  SW Error Force NMI Flag
//! - \b SYSCTL_NMI_CRC_FAIL         -  BGCRC calculation failed.
//
//*****************************************************************************
static inline uint32_t
SysCtl_getNMIShadowFlagStatus(void)
{
    //
    // Read and return the current value of the NMI shadow flag register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x6U)))));
}

//*****************************************************************************
//
//! Check if the individual NMI shadow flags are set.
//!
//! \param nmiFlags Bit mask of the NMI interrupts that user wants  to clear.
//! The bit format of this parameter is same as of the NMIFLG register. These
//! defines are provided:
//! - \b SYSCTL_NMI_NMIINT           -  NMI Interrupt Flag
//! - \b SYSCTL_NMI_CLOCKFAIL        -  Clock Fail Interrupt Flag
//! - \b SYSCTL_NMI_RAMUNCERR        -  RAM Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_FLUNCERR         -  Flash Uncorrectable Error NMI Flag
//! - \b SYSCTL_NMI_CPU1HWBISTERR    -  HW BIST Error NMI Flag
//! - \b SYSCTL_NMI_SYSDBGNMI        -  System Debug Module NMI Flag
//! - \b SYSCTL_NMI_CLBNMI           -  Reconfigurable Logic NMI Flag
//! - \b SYSCTL_NMI_SWERR            -  SW Error Force NMI Flag
//! - \b SYSCTL_NMI_CRC_FAIL         -  BGCRC calculation failed.
//!
//! Check if interrupt flags corresponding to the passed in bit mask are
//! asserted.
//!
//! \return \b true if any of the NMI asked for in the parameter bit mask
//! is set. \b false if none of the NMI requested in the parameter bit mask are
//! set.
//
//*****************************************************************************
static inline _Bool
SysCtl_isNMIShadowFlagSet(uint32_t nmiFlags)
{
    //
    // Check the arguments.
    // Make sure if reserved bits are not set in nmiFlags.
    //
    ;

    //
    // Read the flag register and return true if any of them are set.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x6U)))) & nmiFlags) != 0U);
}

//*****************************************************************************
//
//! Enable the missing clock detection (MCD) Logic
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableMCD(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x2EU)))) &= ~(0x4U);

    __edis();
}

//*****************************************************************************
//
//! Disable the missing clock detection (MCD) Logic
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disableMCD(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x2EU)))) |= 0x4U;

    __edis();
}

//*****************************************************************************
//
//! Get the missing clock detection Failure Status
//!
//! \note A failure means the oscillator clock is missing
//!
//! \return Returns \b true if a failure is detected or \b false if a
//! failure isn't detected
//
//*****************************************************************************
static inline _Bool
SysCtl_isMCDClockFailureDetected(void)
{
    //
    //  Check the status bit to determine failure
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x2EU)))) & 0x1U) != 0U);
}

//*****************************************************************************
//
//! Reset the missing clock detection logic after clock failure
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_resetMCD(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x2EU)))) |= 0x2U;

    __edis();
}

//*****************************************************************************
//
//! Re-connect missing clock detection clock source to stop simulating clock
//! failure
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_connectMCDClockSource(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x2EU)))) &= ~(0x8U);

    __edis();
}

//*****************************************************************************
//
//! Disconnect missing clock detection clock source to simulate clock failure.
//! This is for testing the MCD functionality.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disconnectMCDClockSource(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x2EU)))) |= 0x8U;

    __edis();
}

//*****************************************************************************
//
//! Lock the Access Control Registers
//!
//! This function locks the access control registers and puts them in a
//! read-only state.
//!
//! \note Only a reset can unlock the access control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_lockAccessControlRegs(void)
{
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D500U + 0x1FEU)))) |=
        0x1U;

    __edis();
}

//*****************************************************************************
//
//! Set the peripheral access control permissions
//!
//! \param peripheral is the selected peripheral
//! \param master is the selected master (CPU1, CLA1, or DMA1)
//! \param permission is the selected access permissions
//!
//! This function sets the specified peripheral access control permissions for
//! the the specified master (CPU1, CLA1, or DMA1)
//!
//! The \e peripheral parameter can have one enumerated value in the format of
//! \b SYSCTL_ACCESS_X where X is the name of the peripheral instance to be
//! configured such as \b SYSCTL_ACCESS_ADCA.
//!
//! The \e master parameter can have one the following enumerated values:
//! - \b SYSCTL_ACCESS_CPU1 - CPU1 Master
//! - \b SYSCTL_ACCESS_CLA1 - CLA1 Master
//! - \b SYSCTL_ACCESS_DMA1 - DMA1 Master
//!
//! The \e permission parameter can have one the following enumerated values:
//! - \b SYSCTL_ACCESS_FULL      - Full Access for both read and write
//! - \b SYSCTL_ACCESS_PROTECTED - Protected read access such that FIFOs, clear
//!                                on read registers are not changed, and no
//!                                write access
//! - \b SYSCTL_ACCESS_NONE      - No read or write access
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setPeripheralAccessControl(SysCtl_AccessPeripheral peripheral,
                                  SysCtl_AccessMaster master,
                                  SysCtl_AccessPermission permission)
{
    //
    // Set master permissions for specified peripheral. Each master has
    // two bits dedicated to its permission setting.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(0x0005D500U + (uint16_t)peripheral)))) =
        ((*((volatile uint16_t *)((uintptr_t)(0x0005D500U + (uint16_t)peripheral)))) &
         ~(0x3U << (uint16_t)master)) |
        ((uint32_t)permission << (uint16_t)master);

    __edis();
}

//*****************************************************************************
//
//! Get the peripheral access control permissions
//!
//! \param peripheral is the selected peripheral
//! \param master is the selected master (CPU1, CLA1, or DMA1)
//!
//! This function gets the specified peripheral access control permissions for
//! the the specified master (CPU1, CLA1, or DMA1)
//!
//! The \e peripheral parameter can have one enumerated value in the format of
//! \b SYSCTL_ACCESS_X where X is the name of the peripheral instance to be
//! configured such as \b SYSCTL_ACCESS_ADCA.
//!
//! The \e master parameter can have one the following enumerated values:
//! - \b SYSCTL_ACCESS_CPU1 - CPU1 Master
//! - \b SYSCTL_ACCESS_CLA1 - CLA1 Master
//! - \b SYSCTL_ACCESS_DMA1 - DMA1 Master
//!
//! \return Returns one of the following enumerated permission values:
//! - \b SYSCTL_ACCESS_FULL      - Full Access for both read and write
//! - \b SYSCTL_ACCESS_PROTECTED - Protected read access such that FIFOs, clear
//!                                on read registers are not changed, and no
//!                                write access
//! - \b SYSCTL_ACCESS_NONE      - No read or write access
//
//*****************************************************************************
static inline uint32_t
SysCtl_getPeripheralAccessControl(SysCtl_AccessPeripheral peripheral,
                                  SysCtl_AccessMaster master)
{
    //
    // Read master permissions for specified peripheral. Each master has
    // two bits dedicated to its permission setting.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x0005D500U + (uint16_t)peripheral)))) >> (uint16_t)master) &
           0x3U);
}

//*****************************************************************************
//
//! Configures the sync output source.
//!
//! \param syncSrc is sync output source selection.
//!
//! This function configures the sync output source from the ePWM modules. The
//! \e syncSrc parameter is a value \b SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is
//! a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc)
{
    //
    // Write the sync output source selection to the appropriate register.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00007940U + 0x0U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(0x00007940U + 0x0U)))) &
         ~((uint32_t)0x1F000000U)) |
        ((uint32_t)syncSrc << 24U);
    __edis();

}
//*****************************************************************************
//
//! Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal.
//!
//! \param adcsocSrc is a bit field of the selected signals to be enabled
//!
//! This function configures which ePWM SOC signals are enabled as a source for
//! either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical OR
//! of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different
//! signals.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc)
{
    //
    // Set the bits that correspond to signal to be enabled.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00007940U + 0x2U)))) |= adcsocSrc;
    __edis();
}

//*****************************************************************************
//
//! Disables ePWM SOC signals from driving an external ADCSOC signal.
//!
//! \param adcsocSrc is a bit field of the selected signals to be disabled
//!
//! This function configures which ePWM SOC signals are disabled as a source
//! for either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical
//! OR of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different
//! signals.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc)
{
    //
    // Clear the bits that correspond to signal to be disabled.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00007940U + 0x2U)))) &= ~adcsocSrc;
    __edis();
}

//*****************************************************************************
//
//! Locks the SOC Select of the Trig X-BAR.
//!
//! This function locks the external ADC SOC select of the Trig X-BAR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_lockExtADCSOCSelect(void)
{
    //
    // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00007940U + 0x4U)))) =
        0x2U;
    __edis();
}

//*****************************************************************************
//
//! Locks the Sync Select of the Trig X-BAR.
//!
//! This function locks Sync Input and Output Select of the Trig X-BAR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_lockSyncSelect(void)
{
    //
    // Lock the SYNCSELECT register.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00007940U + 0x4U)))) = 0x1U;
    __edis();
}
//*****************************************************************************
//
//! Get the Device Silicon Revision ID
//!
//! This function returns the silicon revision ID for the device.
//!
//! \note This API is applicable only for the CPU1 subsystem.
//!
//! \return Returns the silicon revision ID value.
//
//*****************************************************************************
static inline uint32_t
SysCtl_getDeviceRevision(void)
{
    //
    // Returns the device silicon revision ID
    //
    return((*((volatile uint32_t *)((uintptr_t)(0x0005D000U + 0xCU)))));
}


//*****************************************************************************
//
//! Gets the error status of the Efuse
//!
//! The function provides both the Efuse Autoload & the Efuse Self Test
//! Error Status.
//!
//! \note This API is applicable only for the CPU1 subsystem.
//!
//! \return Fuse Error status.
//
//*****************************************************************************
static inline uint16_t
SysCtl_getEfuseError(void)
{
    return((*((volatile uint16_t *)((uintptr_t)(0x0005D000U + 0x74U)))));
}

//*****************************************************************************
//
//! Sets up XCLK divider.
//!
//! \param divider is the value that configures the divider.
//!
//! This function sets up the XCLK divider. There is only one
//! divider that scales INTOSC1 to XCLK.
//!
//! The \e divider parameter can have one enumerated value from
//! SysCtl_XClkDivider
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setXClk(SysCtl_XClkDivider divider)
{
    //
    // Clears the divider then configures it.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x28U)))) =
                        ((*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x28U)))) &
                         ~(0x3U)) |
                        (uint16_t)divider;
    __edis();
}

//*****************************************************************************
//
//! Sets up PLLSYSCLK divider.
//!
//! \param divider is the value that configures the divider.
//!
//! This function sets up the PLLSYSCLK divider. There is only one
//! divider that scales PLLSYSCLK to generate the system clock.
//!
//! The \e divider parameter can have one value from the set below:
//!     0x0 = /1
//!     0x1 = /2
//!     0x2 = /4 (default on reset)
//!     0x3 = /6
//!     0x4 = /8
//!    ......
//!     0x3F =/126
//!
//! \return None.
//!
//! \note Please make sure to check if the PLL is locked and valid using the
//! SysCtl_isPLLValid() before setting the divider.
//
//*****************************************************************************
static inline void
SysCtl_setPLLSysClk(uint16_t divider)
{
    //
    // Clears the divider then configures it.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x22U)))) =
                    ((*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x22U)))) &
                     ~(0x3FU)) | divider;
    __edis();
}

//*****************************************************************************
//
//! Sets up MCAN Clk divider.
//!
//! \param divider is the value that configures the divider.
//!
//! This function sets up the MCANCLK divider. There is only one
//! divider that scales MCAN clock.
//!
//! The \e divider parameter can have one enumerated value from
//! SysCtl_MCANClkDivider
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setMCANClk(SysCtl_MCANClkDivider divider)
{
    //
    // Clears the divider then configures it.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x24U)))) =
                    ((*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0x24U)))) &
                     ~(0x1F00U)) |
                    ((uint16_t)divider << 8U);
    __edis();
}

//*****************************************************************************
//
//! Sets up CPU Timer 2  CLK source & divider.
//!
//! \param divider is the value that configures the divider.
//! \param source is the source for the clock divider
//!
//! This function sets up the CPU Timer 2 CLK divider based on the source that
//! is selected. There is only one divider that scales the "source" to
//! CPU Timer 2 CLK.
//!
//! The \e divider parameter can have one enumerated value from
//! SysCtl_Cputimer2ClkDivider
//! The \e source parameter can have one enumerated value from
//! SysCtl_Cputimer2ClkSource
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setCputimer2Clk(SysCtl_Cputimer2ClkDivider divider,
                               SysCtl_Cputimer2ClkSource source)
{
  //
    // Clears the divider & the source, then configures it.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7CU)))) =
                    ((*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7CU)))) &
                     ~(0x7U |
                       0x38U));

    (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7CU)))) |=
                    ((uint16_t)divider << 3U) |
                    ((uint16_t)source << 0U);
    __edis();
}

//*****************************************************************************
//
//! Gets the PIE Vector Fetch Error Handler Routine Address.
//!
//! The function indicates the address of the PIE Vector Fetch Error
//! handler routine.
//!
//! \return Error Handler Address.
//!
//! \note Its the responsibility of user to initialize this register. If this
//! register is not initialized, a default error handler at address
//! 0x3fffbe will get executed.
//
//*****************************************************************************
static inline uint32_t
SysCtl_getPIEVErrAddr(void)
{
    return((*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0xAU)))));
}

//*****************************************************************************
//
//! Simulates a reset to the CPU1
//!
//! \param rstCauses is the cause for the reset.
//!
//! The \e rstCauses parameter can be one/ more of these values:
//! SYSCTL_CAUSE_CPU1RSN or SYSCTL_CAUSE_XRS
//!
//! \return None.
//!
//! \note This API exists only on CPU1
//
//*****************************************************************************
static inline void
SysCtl_simulateReset(uint32_t rstCauses)
{
    //
    //Write will succeed only if a matching key value is written
    //to the KEY field
    //Sets the appropriate reset bit.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005D300U + 0x70U))))  = (rstCauses |
                                              (0xA5A50000U &
                                               0xFFFF0000U));
}

//*****************************************************************************
//
//! Gets the status of interrupts due to multiple different
//! errors in the system.
//!
//! \return the Interrupt generated on the system.
//! The values can be one/ more from:
//! - SYSCTL_STATUS_AES_BUS_ERROR
//! - SYSCTL_STATUS_EPG1_INT
//
//*****************************************************************************
static inline uint32_t
SysCtl_getInterruptStatus(void)
{
    return((*((volatile uint32_t *)((uintptr_t)(0x0005D400U + 0x10U)))));
}
//*****************************************************************************
//
//! Clears the interrupts due to multiple different errors in the system.
//!
//! \param intFlags is the interrupt that needs to be cleared.
//!
//! The \e intFlags parameter are the Interrupts generated on errors in
//! the system that need to be cleared. The values can be one or more from:
//! - SYSCTL_STATUS_GINT
//! - SYSCTL_STATUS_AES_BUS_ERROR
//! - SYSCTL_STATUS_EPG1_INT
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearInterruptStatus(uint32_t intFlags)
{
    (*((volatile uint16_t *)((uintptr_t)(0x0005D400U + 0x12U)))) |= intFlags;
}
//*****************************************************************************
//
//! Sets the interrupts for the multiple different errors in the system.
//!
//! \param intFlags is the interrupt that needs to be set.
//!
//! The \e intFlags parameter are the Interrupts that can be set
//! for the errors in the system. The values can be one/ more from:
//! - SYSCTL_STATUS_AES_BUS_ERROR
//! - SYSCTL_STATUS_EPG1_INT
//!
//! \return None.
//!
//! \note This API  is present only on CPU1.
//
//*****************************************************************************
static inline void
SysCtl_setInterruptStatus(uint32_t intFlags)
{
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x0005D400U + 0x14U)))) =
                (intFlags | (0xA5A50000U & 0xFF000000U));
    __edis();
}

//*****************************************************************************
//
//! Gets the masked interrupts due to multiple different
//! errors in the system.
//!
//! \return the Interrupt generated on the system.
//! The values can be one/ more from:
//! - SYSCTL_STATUS_AES_BUS_ERROR
//! - SYSCTL_STATUS_EPG1_INT
//
//*****************************************************************************
static inline uint32_t
SysCtl_getInterruptStatusMask(void)
{
    return((*((volatile uint32_t *)((uintptr_t)(0x0005D400U + 0x16U)))));
}

//*****************************************************************************
//
//! Masks the interrupts for the multiple different errors in the system.
//!
//! \param intFlags is the interrupt that needs to be set.
//!
//! The \e intFlags parameter are the Interrupts that can be masked
//! for the errors in the system. The values can be one/ more from:
//! - SYSCTL_STATUS_AES_BUS_ERROR
//! - SYSCTL_STATUS_EPG1_INT
//!
//! \return None.
//!
//! \note This API  is present only on CPU1.
//
//*****************************************************************************
static inline void
SysCtl_setInterruptStatusMask(uint32_t intFlags)
{
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x0005D400U + 0x16U)))) =
                (intFlags | (0xA5A50000U & 0xFF000000U));
    __edis();
}

//*****************************************************************************
//
//!  Check if One or more of the error sources triggered
//!
//!  Following are the events/triggers that can indicate an error:
//!1. nmi interrupt on C28x
//!2. Watchdog reset
//!3. Error on a Pie vector fetch
//!4. Efuse error
//!5. nmi interrupt on CM
//!
//! \return \b true if the error is triggered
//! \b false if the error is not triggered
//
//*****************************************************************************
static inline uint16_t
SysCtl_isErrorTriggered(void)
{
    return(((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x7U)))) & 0x1U) != 0U);
}

//*****************************************************************************
//
//!  Check if Error status pin is high or not
//!
//! \return \b true if the error status pin is high
//! \b false if the error status pin is low
//
//*****************************************************************************
static inline uint16_t
SysCtl_getErrorPinStatus(void)
{
    //
    // Read and return the status of the ErrorPin
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x7U)))) & 0x2U) != 0U);
}

//*****************************************************************************
//
//! Forces an error flag to set to indicate an error being generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_forceError(void)
{
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x9U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Clears any error flag set due to error generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearError(void)
{
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0x8U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Selects the polarity of the error pin
//!
//! \param pol is the ERROR pin polarity
//!
//! The \e pol parameter can take any of the below values:
//! 0x0U: If an error is already triggered, Error pin will be driven
//! with a value of 0, else 1.
//! 0x1U: If an error is already triggered, Error pin will be driven
//! with a value of 1, else 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_selectErrPinPolarity(uint16_t pol)
{
    __eallow();
    //
    //Configures the error pin polarity based on the provided polarity
    //
    if(pol == 1U)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0xAU)))) |= 0x1U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007060U + 0xAU)))) &= ~0x1U;
    }
    __edis();
}

//*****************************************************************************
//
//! Locks the Error control registers
//!
//! This function locks the Error configuration registers.
//!
//! \return None.
//!
//! \note The lock register is cleared only on a system reset.
//
//*****************************************************************************
static inline void
SysCtl_lockErrControl(void)
{
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00007060U + 0xBU)))) = 0x1U;
    __edis();
}

//*****************************************************************************
//
//!  Check if the MCAN wakeup event has occured.
//!
//! \return \b true if the MCAN wakeup event has occured.
//!  \b false if the MCAN wakeup event has not occured.
//
//*****************************************************************************
static inline _Bool
SysCtl_isMCANWakeStatusSet(void)
{
    //
    // Read the MCAN wakeup event status and return true if set.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x98U)))) &
            0x1U) != 0U);
}

//*****************************************************************************
//
//! Clears the MCAN wakeup event status.
//!
//! This function clears the MCAN wakeup event status. To check if it was set
//! first, see SysCtl_isMCANWakeStatusSet().
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_clearMCANWakeStatus(void)
{
    //
    // Clear the MCAN wakeup event status
    //
    (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x9AU)))) |=
                                        0x1U;
}

//*****************************************************************************
//
//! Delays for a fixed number of cycles.
//!
//! \param count is the number of delay loop iterations to perform.
//!
//! This function generates a constant length delay using assembly code. The
//! loop takes 5 cycles per iteration plus 9 cycles of overhead.
//!
//! \note If count is equal to zero, the loop will underflow and run for a
//! very long time.
//!
//! \note Refer to the macro DEVICE_DELAY_US(x) in device.h which can be used to
//! insert a delay in microseconds.
//!
//! \return None.
//
//*****************************************************************************
extern void
SysCtl_delay(uint32_t count);

//*****************************************************************************
//
//! Calculates the system clock frequency (SYSCLK).
//!
//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK).
//!
//! This function determines the frequency of the system clock based on the
//! frequency of the oscillator clock source (from \e clockInHz) and the PLL
//! and clock divider configuration registers.
//!
//! \return Returns the system clock frequency. If a missing clock is detected,
//! the function will return the INTOSC1 frequency. This needs to be
//! corrected and cleared (see SysCtl_resetMCD()) before trying to call this
//! function again.
//
//*****************************************************************************
extern uint32_t
SysCtl_getClock(uint32_t clockInHz);

//*****************************************************************************
//
//! Configures the clocking of the device.
//!
//! \param config is the required configuration of the device clocking.
//!
//! This function configures the clocking of the device.  The input crystal
//! frequency, oscillator to be used, use of the PLL, and the system clock
//! divider are all configured with this function.
//!
//! The \e config parameter is the OR of several different values, many of
//! which are grouped into sets where only one can be chosen.
//!
//! - The system clock divider is chosen with the macro \b SYSCTL_SYSDIV(x)
//!   where x is either 1 or an even value up to 126.
//!
//! - The use of the PLL is chosen with ONLY one of the below modes:
//!   \b SYSCTL_PLL_ENABLE - This is to Enable the PLL Clock to the System
//!    or
//!   \b SYSCTL_PLL_BYPASS -This is to Bypass the PLLCLK from the System,
//!    this will also power up the PLL if the user desires to power up the PLL
//!    but not use it for System.
//!    or
//!   \b SYSCTL_PLL_DISABLE-This is to Power Down the PLL and Bypass the
//!    PLLCLK to the System.
//!
//! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value
//!   from 1 to 127.
//!
//!
//! - The oscillator source chosen with \b SYSCTL_OSCSRC_OSC2,
//!   \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_XTAL_SE or \b SYSCTL_OSCSRC_OSC1.
//!
//! This function uses the DCC to check that the PLLRAWCLK is running at the
//! expected rate. If you are using the DCC, you must back up its configuration
//! before calling this function and restore it afterward.
//! Locking PLL sequence is only done if the multipliers are updated.
//!
//! \note See your device errata for more details about locking the PLL.
//!
//! \return Returns \b false if a missing clock error is detected. This needs
//! to be cleared (see SysCtl_resetMCD()) before trying to call this function
//! again. Also, returns \b false if the PLLRAWCLK is not running and its
//! expected rate. Otherwise, returns \b true.
//
//*****************************************************************************
extern _Bool
SysCtl_setClock(uint32_t config);

//*****************************************************************************
//
//! Validates PLL Raw Clock Frequency (PLLRAWCLK)
//!
//! \param base is the DCC module base address
//! \param oscSource is the Clock Source for the PLL that is also used for DCC
//! \param pllMultDiv has the PLL Multiplier Register configuration which
//!  include integer multiplier and divider values used to configure the
//!  DCC Counter1 clock
//!
//!  This function uses DCC module to validate the PLL clock frequency.
//!  It uses oscSource as a reference clock for DCC, and PLL is used as clock
//!  under test. As long as the Counter0 (running of oscSource) & Counter1
//!  (running of PLL) expire at the same time, DCC will not generate an Error.
//!  This function gives 100 attempts for PLL to lock and make sure frequency
//!  is as expected.
//!
//!  \note This function does not validate if PLL output frequency (PLLRAWCLK)
//!  is within the operating range as per the datasheet.
//!
//! - The \e oscSource parameter is the oscillator source chosen with
//!   \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_XTAL_SE
//!    or \b SYSCTL_OSCSRC_OSC1.
//!
//! - The \e pllMultDiv parameter is a bitwise OR of \b SYSCTL_IMULT(x)
//!   where x is a value from 1 to 127 and both of the following divider
//!   values which is chosen with the macro \b SYSCTL_REFDIV(x) and
//!   SYSCTL_ODIV(x) where x is a value from 1 to 32 and can be different
//!   for both macros.
//!
//!  \return Returns \b true if the DCCSTATUS error flag is not set.
//!    Otherwise, returns \b false.
//
//*****************************************************************************
extern _Bool
SysCtl_isPLLValid(uint32_t base, uint32_t oscSource, uint32_t pllMultDiv);
//*****************************************************************************
//
//! Configures the external oscillator for the clocking of the device.
//!
//! This function configures the external oscillator (XTAL) to be used for the
//! clocking of the device in crystal mode. It follows the procedure to turn on
//! the oscillator, wait for it to power up, and select it as the source of the
//! system clock.
//!
//! Please note that this function blocks while it waits for the XTAL to power
//! up. If the XTAL does not manage to power up properly, the function will
//! loop for a long time. It is recommended that you modify this function to
//! add an appropriate timeout and error-handling procedure.
//!
//! \return None.
//
//*****************************************************************************
extern void
SysCtl_selectXTAL(void);

//*****************************************************************************
//
//! Configures the external oscillator for the clocking of the device in
//! single-ended mode.
//!
//! This function configures the external oscillator (XTAL) to be used for the
//! clocking of the device in single-ended mode. It follows the procedure to
//! turn on the oscillator, wait for it to power up, and select it as the
//! source of the system clock.
//!
//! Please note that this function blocks while it waits for the XTAL to power
//! up. If the XTAL does not manage to power up properly, the function will
//! loop for a long time. It is recommended that you modify this function to
//! add an appropriate timeout and error-handling procedure.
//!
//! \return None.
//
//*****************************************************************************
extern void
SysCtl_selectXTALSingleEnded(void);

//*****************************************************************************
//
//! Selects the oscillator to be used for the clocking of the device.
//!
//! \param oscSource is the oscillator source to be configured.
//!
//! This function configures the oscillator to be used in the clocking of the
//! device. The \e oscSource parameter may take a value of
//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, \b SYSCTL_OSCSRC_XTAL_SE, or
//! \b SYSCTL_OSCSRC_OSC1.
//!
//! \sa SysCtl_turnOnOsc()
//!
//! \return None.
//
//*****************************************************************************
extern void
SysCtl_selectOscSource(uint32_t oscSource);

//*****************************************************************************
//
//! Calculates the low-speed peripheral clock frequency (LSPCLK).
//!
//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK).
//!
//! This function determines the frequency of the low-speed peripheral clock
//! based on the frequency of the oscillator clock source (from \e clockInHz)
//! and the PLL and clock divider configuration registers.
//!
//! \return Returns the low-speed peripheral clock frequency.
//
//*****************************************************************************
extern uint32_t
SysCtl_getLowSpeedClock(uint32_t clockInHz);

//*****************************************************************************
//
//! Get the device part parametric value
//!
//! \param parametric is the requested device parametric value
//!
//! This function gets the device part parametric value.
//!
//! The \e parametric parameter can have one the following enumerated values:
//! - \b SYSCTL_DEVICE_QUAL      - Device Qualification Status
//! - \b SYSCTL_DEVICE_PINCOUNT  - Device Pin Count
//! - \b SYSCTL_DEVICE_INSTASPIN - Device InstaSPIN Feature Set
//! - \b SYSCTL_DEVICE_FLASH     - Device Flash size (KB)
//! - \b SYSCTL_DEVICE_FAMILY    - Device Family
//! - \b SYSCTL_DEVICE_PARTNO    - Device Part Number
//! - \b SYSCTL_DEVICE_CLASSID   - Device Class ID
//!
//! \note This API is applicable only for the CPU1 subsystem.
//!
//! \return Returns the specified parametric value.
//
//*****************************************************************************
extern uint16_t
SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric);

//*****************************************************************************
//
//! Configures & locks/unlocks the peripheral type
//!
//! \param type is the peripheral type that needs to be configured.
//! \param config is the configuration done to the peripheral which is
//!  dependent on the peripheral type.
//! \param lock is to decide if writes for any further configuration is to
//!  be allowed or not.
//!
//! The \e type parameter can be a value from the enumeration
//! SysCtl_SelType
//! The \e config parameter can be a value from the ones below:
//! 0x0U : disables the feature for the type.
//! 0x1U : enables the feature for the type.
//!
//! For ECAP: ECAP registers are EALLOW protected or not.
//! For SDFM: Data Ready conditions do not generate the SDFMINT.
//!
//! The \e lock parameter can be a value from the ones below:
//! 0x1U : Write for any further configuration is not allowed.
//! 0x0U : Write for any further configuration is allowed.
//!
//! \note This API is applicable only for the CPU1 subsystem.
//!
//! \return None.
//
//*****************************************************************************
extern void
SysCtl_configureType(SysCtl_SelType type , uint16_t config, uint16_t lock);

//*****************************************************************************
//
//!  Check if writes for any further configuration of peripheral types is to
//!  be allowed or not.
//!
//! \param type is the peripheral type for which permissions are being checked
//!
//! \note This API is applicable only for the CPU1 subsystem.
//!
//! \return \b true if Write for any further configuration is not allowed.
//! \b false if Write for any further configuration is allowed.
//
//*****************************************************************************
extern _Bool
SysCtl_isConfigTypeLocked(SysCtl_SelType type);

//*****************************************************************************
//
//! Locks the Clock configuration registers
//!
//! \param registerName is clock configuration register which needs to
//! be locked.
//!
//! The \e registerName parameter can be a value from the enumeration
//! SysCtl_ClkRegSel
//!
//! \return None.
//!
//! \note The register is unlocked only on a system reset.
//
//*****************************************************************************

extern void
SysCtl_lockClkConfig(SysCtl_ClkRegSel registerName);

//*****************************************************************************
//
//! Locks the CPU system configuration registers
//!
//! \param registerName is CPU system configuration register which needs to
//! be locked.
//!
//! The \e registerName parameter can be a value from the enumeration
//! SysCtl_CpuRegSel
//!
//! \return None.
//!
//! \note The register is unlocked only on a system reset.
//
//*****************************************************************************

extern void
SysCtl_lockSysConfig (SysCtl_CpuRegSel registerName);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************


//
// The key value for RAM initialization
//

//
// RAM Initialization Register Mask
//

//
// The Parity disable key value
//

//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
// These are the flags used by the flags parameter when calling
// the CAN_setupMessageObject() function.
//
//*****************************************************************************

//! This indicates that transmit interrupts should be enabled, or are enabled.

//! This indicates that receive interrupts should be enabled, or are
//! enabled.

//! This indicates that a message object will use or is using filtering
//! based on the object's message identifier.

//! This indicates that a message object will use or is using filtering
//! based on the direction of the transfer.

//! This indicates that a message object will use or is using message
//! identifier filtering based on the extended identifier.

//! This indicates that this message object is part of a FIFO structure and
//! not the final message object in a FIFO.

//! This indicates that a message object has no flags set.

//*****************************************************************************
//
// These definitions are used to specify interrupt sources to
// CAN_enableInterrupt() and CAN_disableInterrupt().
//
//*****************************************************************************
//! This flag is used to allow a CAN controller to generate error
//! interrupts.

//! This flag is used to allow a CAN controller to generate status
//! interrupts.

//! This flag is used to allow a CAN controller to generate interrupts
//! on interrupt line 0

//! This flag is used to allow a CAN controller to generate interrupts
//! on interrupt line 1

//*****************************************************************************
//
// The following definitions contain all error or status indicators that can
// be returned when calling the CAN_getStatus() function.
//
//*****************************************************************************

//! CAN controller has detected a parity error.

//! CAN controller has entered a Bus Off state.

//! CAN controller error level has reached warning level.

//! CAN controller error level has reached error passive level.

//! A message was received successfully since the last read of this status.

//! A message was transmitted successfully since the last read of this
//! status.

//! This is the mask for the last error code field.

//! There was no error.

//! A bit stuffing error has occurred.

//! A formatting error has occurred.

//! An acknowledge error has occurred.

//! The bus remained a bit level of 1 for longer than is allowed.

//! The bus remained a bit level of 0 for longer than is allowed.

//! A CRC error has occurred.

//*****************************************************************************
//
// The following macros are added for the Global Interrupt EN/FLG/CLR
// register
//
//*****************************************************************************
//! CANINT0 global interrupt bit

//! CANINT1 global interrupt bit

//*****************************************************************************
//
// The following macros are added for accessing the interrupt register and
// the standard arbitration ID in the interface registers.
//
//*****************************************************************************
//! Status of INT0ID

//! IF1 Arbitration Standard ID Shift Offset

//! IF1 Arbitration Standard ID Mask

//! IF2 Arbitration Standard ID Shift Offset

//! IF2 Arbitration Standard ID Mask


//*****************************************************************************
//
//! This data type is used to decide between STD_ID or EXT_ID for a mailbox.
//! This is used when calling the CAN_setupMessageObject() function.
//
//*****************************************************************************
typedef enum
{
    //! Set the message ID frame to standard.
    CAN_MSG_FRAME_STD,

    //! Set the message ID frame to extended.
    CAN_MSG_FRAME_EXT
} CAN_MsgFrameType;

//*****************************************************************************
//
//! This definition is used to determine the type of message object that will
//! be set up via a call to the CAN_setupMessageObject() API.
//
//*****************************************************************************
typedef enum
{
    //! Transmit message object.
    CAN_MSG_OBJ_TYPE_TX,

    //! Transmit remote request message object
    CAN_MSG_OBJ_TYPE_TX_REMOTE,

    //! Receive message object.
    CAN_MSG_OBJ_TYPE_RX,

    //! Remote frame receive remote, with auto-transmit message object.
    CAN_MSG_OBJ_TYPE_RXTX_REMOTE
} CAN_MsgObjType;

//*****************************************************************************
//
//! This definition is used to determine the clock source that will
//! be set up via a call to the CAN_selectClockSource() API.
//
//*****************************************************************************
typedef enum
{
    //! Peripheral System Clock Source
    CAN_CLOCK_SOURCE_SYS    = 0x0,

    //! External Oscillator Clock Source
    CAN_CLOCK_SOURCE_XTAL   = 0x1,

    //! Auxiliary Clock Input Source
    CAN_CLOCK_SOURCE_AUX    = 0x2
} CAN_ClockSource;


//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//!
//! Checks a CAN base address.
//!
//! \param base is the base address of the CAN controller.
//!
//! This function determines if a CAN controller base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************


//*****************************************************************************
//
//! \internal
//!
//! Copies data from a buffer to the CAN Data registers.
//!
//! \param data is a pointer to the data to be written out to the CAN
//! controller's data registers.
//! \param address is a uint32_t value for the first register of the
//! CAN controller's data registers.  For example, in order to use the IF1
//! register set on CAN controller 0, the value would be: \b CANA_BASE \b +
//! \b CAN_O_IF1DATA.
//! \param size is the number of bytes to copy into the CAN controller.
//!
//! This function takes the steps necessary to copy data from a contiguous
//! buffer in memory into the non-contiguous data registers used by the CAN
//! controller.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_writeDataReg(const uint16_t *const data, uint32_t address,
                 uint32_t size)
{
    uint32_t idx;
    uint32_t dataReg = address;

    //
    // Check the dataReg.
    //
    ;

    //
    // Loop always copies 1 byte per iteration.
    //
    for(idx = 0U; idx < size; idx++)
    {
        //
        // Write out the data 8 bits at a time.
        //
        __byte((int16_t *)(dataReg),0) = data[idx];

        dataReg++;
    }
}

//*****************************************************************************
//
//! \internal
//!
//! Copies data from the CAN Data registers to a buffer.
//!
//! \param data is a pointer to the location to store the data read from the
//! CAN controller's data registers.
//! \param address is a uint32_t value for the first register of the
//! CAN controller's data registers.  For example, in order to use the IF1
//! register set on CAN controller 1, the value would be: \b CANA_BASE \b +
//! \b CAN_O_IF1DATA.
//! \param size is the number of bytes to copy from the CAN controller.
//!
//! This function takes the steps necessary to copy data to a contiguous buffer
//! in memory from the non-contiguous data registers used by the CAN
//! controller.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_readDataReg(uint16_t *data, const uint32_t address, uint32_t size)
{
    uint32_t idx;
    uint32_t dataReg = address;

    //
    // Loop always copies 1 byte per iteration.
    //
    for(idx = 0U; idx < size; idx++)
    {
        //
        // Read out the data
        //
        data[idx] = __byte((int16_t *)(dataReg),0);

        dataReg++;
    }
}

//*****************************************************************************
//
//! Initializes the CAN controller's RAM.
//!
//! \param base is the base address of the CAN controller.
//!
//! Performs the initialization of the RAM used for the CAN message objects.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_initRAM(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x40U)))) = 0x10U |
                                    (0xAU);

    while(!(((*((volatile uint16_t *)((uintptr_t)(base + 0x40U)))) & (0x003FU)) ==
            (0x20U | 0x4U |
             0x1U)))
    {
        //
        // Wait until RAM Init is complete
        //
    }
}

//*****************************************************************************
//
//! Select CAN Clock Source
//!
//! \param base is the base address of the CAN controller.
//! \param source is the clock source to use for the CAN controller.
//!
//! This function selects the specified clock source for the CAN controller.
//!
//! The \e source parameter can be any one of the following:
//! - \b CAN_CLOCK_SOURCE_SYS  - Peripheral System Clock
//! - \b CAN_CLOCK_SOURCE_XTAL - External Oscillator
//! - \b CAN_CLOCK_SOURCE_AUX  - Auxiliary Clock Input from GPIO
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_selectClockSource(uint32_t base, CAN_ClockSource source)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Determine the CAN controller and set specified clock source
    //
    __eallow();

    switch(base)
    {
        case 0x00048000U:
            (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0xAU)))) &=
                ~0xCU;

            (*((volatile uint16_t *)((uintptr_t)(0x0005D200U + 0xAU)))) |= ((uint16_t)source <<
                2U);
            break;

        default:

            //
            // Do nothing. Not a valid mode value.
            //
            break;
    }

    __edis();
}

//*****************************************************************************
//
//! Starts the CAN Module's Operations
//!
//! \param base is the base address of the CAN controller.
//!
//! This function starts the CAN module's operations after initialization,
//! which includes the CAN protocol controller state machine of the CAN core
//! and the message handler state machine to begin controlling the CAN's
//! internal data flow.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_startModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear Init and CCE bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~(0x1U | 0x40U);
}

//*****************************************************************************
//
//! Enables the CAN controller.
//!
//! \param base is the base address of the CAN controller to enable.
//!
//! Enables the CAN controller for message processing.  Once enabled, the
//! controller will automatically transmit any pending frames, and process any
//! received frames.  The controller can be stopped by calling
//! CAN_disableController().
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableController(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the init bit in the control register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x1U;
}

//*****************************************************************************
//
//! Disables the CAN controller.
//!
//! \param base is the base address of the CAN controller to disable.
//!
//! Disables the CAN controller for message processing.  When disabled, the
//! controller will no longer automatically process data on the CAN bus.  The
//! controller can be restarted by calling CAN_enableController().  The state
//! of the CAN controller and the message objects in the controller are left as
//! they were before this call was made.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableController(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the init bit in the control register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Enables the test modes of the CAN controller.
//!
//! \param base is the base address of the CAN controller.
//! \param mode are the the test modes to enable.
//!
//! Enables test modes within the controller.  The following valid options for
//! \e mode can be OR'ed together:
//! - \b CAN_TEST_SILENT - Silent Mode
//! - \b CAN_TEST_LBACK  - Loopback Mode
//! - \b CAN_TEST_EXL    - External Loopback Mode
//!
//! \note Loopback mode and external loopback mode \b can \b not be
//! enabled at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableTestMode(uint32_t base, uint16_t mode)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear the bits in the test register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &= ~((uint16_t)0x8U |
                                   (uint16_t)0x10U |
                                   (uint16_t)0x100U);

    //
    // Enable test mode and set the bits in the test register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x80U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= mode;
}

//*****************************************************************************
//
//! Disables the test modes of the CAN controller.
//!
//! \param base is the base address of the CAN controller.
//!
//! Disables test modes within the controller and clears the test bits.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableTestMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the bits in the test register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &= ~((uint16_t)0x8U |
                                   (uint16_t)0x10U |
                                   (uint16_t)0x100U);

    //
    // Clear the test mode enable bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x80U;
}

//*****************************************************************************
//
//! Get the current settings for the CAN controller bit timing.
//!
//! \param base is the base address of the CAN controller.
//!
//! This function reads the current configuration of the CAN controller bit
//! clock timing.
//!
//! \return Returns the value of the bit timing register.
//
//*****************************************************************************
static inline uint32_t
CAN_getBitTiming(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read and return BTR register
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0xCU)));
}

//*****************************************************************************
//
//! Enables direct access to the RAM.
//!
//! \param base is the base address of the CAN controller.
//!
//! Enables direct access to the RAM while in Test mode.
//!
//! \note Test Mode must first be enabled to use this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableMemoryAccessMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the RAM direct access bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= 0x200U;
}

//*****************************************************************************
//
//! Disables direct access to the RAM.
//!
//! \param base is the base address of the CAN controller.
//!
//! Disables direct access to the RAM while in Test mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableMemoryAccessMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the RAM direct access bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &= ~0x200U;
}

//*****************************************************************************
//
//! Sets the interruption debug mode of the CAN controller.
//!
//! \param base is the base address of the CAN controller.
//! \param enable is a flag to enable or disable the interruption debug mode.
//!
//! This function sets the interruption debug mode of the CAN controller. When
//! the \e enable parameter is \b true, CAN will be configured to interrupt any
//! transmission or reception and enter debug mode immediately after it is
//! requested. When \b false, CAN will wait for a started transmission or
//! reception to be completed before entering debug mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_setInterruptionDebugMode(uint32_t base, _Bool enable)
{
    //
    // Check the arguments.
    //
    ;

    if(enable)
    {
        //
        // Enable interrupt debug support
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x100U;
    }
    else
    {
        //
        // Disable interrupt debug support
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x100U;
    }
}

//*****************************************************************************
//
//! Enables DMA Requests from the CAN controller.
//!
//! \param base is the base address of the CAN controller to enable.
//!
//! Enables the CAN controller DMA request lines for each of the 3 interface
//! register sets.  To actually assert the request line, the DMA Active bit
//! must be set in the corresponding interface CMD register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableDMARequests(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the DMA enable bits in the control register.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x0U)) |=
    (0x40000U | (uint32_t)0x80000U | (uint32_t)0x100000U);
}

//*****************************************************************************
//
//! Disables DMA Requests from the CAN controller.
//!
//! \param base is the base address of the CAN controller to enable.
//!
//! Disables the CAN controller DMA request lines for each of the 3 interface
//! register sets.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableDMARequests(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the DMA enable bits in the control register.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x0U)) &=
    ~(0x40000U | (uint32_t)0x80000U | (uint32_t)0x100000U);
}

//*****************************************************************************
//
//! Disables Auto-Bus-On.
//!
//! \param base is the base address of the CAN controller.
//!
//! Disables the Auto-Bus-On feature of the CAN controller.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableAutoBusOn(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the ABO bit in the control register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x200U;
}

//*****************************************************************************
//
//! Enables Auto-Bus-On.
//!
//! \param base is the base address of the CAN controller.
//!
//! Enables the Auto-Bus-On feature of the CAN controller.  Be sure to also
//! configure the Auto-Bus-On time using the CAN_setAutoBusOnTime function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableAutoBusOn(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the ABO bit in the control register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x200U;
}

//*****************************************************************************
//
//! Sets the time before a Bus-Off recovery sequence is started.
//!
//! \param base is the base address of the CAN controller.
//! \param time is number of clock cycles before a Bus-Off recovery sequence
//!        is started.
//!
//! This function sets the number of clock cycles before a Bus-Off recovery
//! sequence is started by clearing the Init bit.
//!
//! \note To enable this functionality, use CAN_enableAutoBusOn().
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_setAutoBusOnTime(uint32_t base, uint32_t time)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set bus-off timer value
    //
    __byte_peripheral_32((uint32_t *)(base + 0x80U)) = time;
}

//*****************************************************************************
//
//! Enables individual CAN controller interrupt sources.
//!
//! \param base is the base address of the CAN controller.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables specific interrupt sources of the CAN controller.  Only enabled
//! sources will cause a processor interrupt.
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//! - \b CAN_INT_ERROR - a controller error condition has occurred
//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has
//! been detected
//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt
//! line 0
//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt
//! line 1
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Enable the specified interrupts.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x0U)) |= intFlags;
}

//*****************************************************************************
//
//! Disables individual CAN controller interrupt sources.
//!
//! \param base is the base address of the CAN controller.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the specified CAN controller interrupt sources.  Only enabled
//! interrupt sources can cause a processor interrupt.
//!
//! The \e intFlags parameter has the same definition as in the
//! CAN_enableInterrupt() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Disable the specified interrupts.
    //
    __byte_peripheral_32((uint32_t *)(base + 0x0U)) &= ~(intFlags);
}

//*****************************************************************************
//
//! Get the CAN controller Interrupt Line set for each mailbox
//!
//! \param base is the base address of the CAN controller.
//!
//! Gets which interrupt line each message object should assert when an
//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits
//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that
//! are asserted indicate the message object should generate an interrupt on
//! interrupt line 1, while bits that are not asserted indicate the message
//! object should generate an interrupt on line 0.
//!
//! \return Returns the value of the interrupt muxing register.
//
//*****************************************************************************
static inline uint32_t
CAN_getInterruptMux(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the interrupt muxing for the CAN peripheral
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0xD8U)));
}

//*****************************************************************************
//
//! Set the CAN controller Interrupt Line for each mailbox
//!
//! \param base is the base address of the CAN controller.
//! \param mux bit packed representation of which message objects should
//!        generate an interrupt on a given interrupt line.
//!
//! Selects which interrupt line each message object should assert when an
//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits
//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that
//! are asserted indicate the message object should generate an interrupt on
//! interrupt line 1, while bits that are not asserted indicate the message
//! object should generate an interrupt on line 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_setInterruptMux(uint32_t base, uint32_t mux)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the interrupt muxing for the CAN peripheral
    //
    __byte_peripheral_32((uint32_t *)(base + 0xD8U)) = mux;
}

//*****************************************************************************
//
//! Enables the CAN controller automatic retransmission behavior.
//!
//! \param base is the base address of the CAN controller.
//!
//! Enables the automatic retransmission of messages with detected errors.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableRetry(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clearing the DAR bit tells the controller to not disable the
    // auto-retry of messages which were not transmitted or received
    // correctly.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x20U;
}

//*****************************************************************************
//
//! Disables the CAN controller automatic retransmission behavior.
//!
//! \param base is the base address of the CAN controller.
//!
//! Disables the automatic retransmission of messages with detected errors.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableRetry(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Setting the DAR bit tells the controller to disable the auto-retry
    // of messages which were not transmitted or received correctly.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x20U;
}

//*****************************************************************************
//
//! Returns the current setting for automatic retransmission.
//!
//! \param base is the base address of the CAN controller.
//!
//! Reads the current setting for the automatic retransmission in the CAN
//! controller and returns it to the caller.
//!
//! \return Returns \b true if automatic retransmission is enabled, \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
CAN_isRetryEnabled(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the disable automatic retry setting from the CAN controller.
    //
    return((_Bool)(((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & 0x20U) != 0x20U));
}

//*****************************************************************************
//
//! Reads the CAN controller error counter register.
//!
//! \param base is the base address of the CAN controller.
//! \param rxCount is a pointer to storage for the receive error counter.
//! \param txCount is a pointer to storage for the transmit error counter.
//!
//! Reads the error counter register and returns the transmit and receive error
//! counts to the caller along with a flag indicating if the controller receive
//! counter has reached the error passive limit.  The values of the receive and
//! transmit error counters are returned through the pointers provided as
//! parameters.
//!
//! After this call, \e rxCount will hold the current receive error count
//! and \e txCount will hold the current transmit error count.
//!
//! \return Returns \b true if the receive error count has reached the error
//! passive limit, and \b false if the error count is below the error passive
//! limit.
//
//*****************************************************************************
static inline _Bool
CAN_getErrorCount(uint32_t base, uint32_t *rxCount, uint32_t *txCount)
{
    uint32_t canError = 0U;

    //
    // Check the arguments.
    //
    ;

    //
    // Read the current count of transmit/receive errors.
    //
    canError = __byte_peripheral_32((uint32_t *)(base + 0x8U));

    //
    // Extract the error numbers from the register value.
    //
    *rxCount = (canError & 0x7F00U) >> 8U;
    *txCount = (canError & 0xFFU) >> 0U;

    return((_Bool)((canError & 0x8000U) != 0U));
}

//*****************************************************************************
//
//! Reads the CAN controller error and status register.
//!
//! \param base is the base address of the CAN controller.
//!
//! Reads the error and status register of the CAN controller.
//!
//! \return Returns the value of the register.
//
//*****************************************************************************
static inline uint16_t
CAN_getStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return error and status register value
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))));
}

//*****************************************************************************
//
//! Reads the CAN controller TX request register.
//!
//! \param base is the base address of the CAN controller.
//!
//! Reads the TX request register of the CAN controller.
//!
//! \return Returns the value of the register.
//
//*****************************************************************************
static inline uint32_t
CAN_getTxRequests(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return Tx requests register value
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0x88U)));
}

//*****************************************************************************
//
//! Reads the CAN controller new data status register.
//!
//! \param base is the base address of the CAN controller.
//!
//! Reads the new data status register of the CAN controller for all message
//! objects.
//!
//! \return Returns the value of the register.
//
//*****************************************************************************
static inline uint32_t
CAN_getNewDataFlags(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return new data register value
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0x9CU)));
}

//*****************************************************************************
//
//! Reads the CAN controller valid message object register.
//!
//! \param base is the base address of the CAN controller.
//!
//! Reads the valid message object register of the CAN controller.
//!
//! \return Returns the value of the register.
//
//*****************************************************************************
static inline uint32_t
CAN_getValidMessageObjects(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the valid message register value
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0xC4U)));
}

//*****************************************************************************
//
//! Get the CAN controller interrupt cause.
//!
//! \param base is the base address of the CAN controller.
//!
//! This function returns the value of the interrupt register that indicates
//! the cause of the interrupt.
//!
//! \return Returns the value of the interrupt register.
//
//*****************************************************************************
static inline uint32_t
CAN_getInterruptCause(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read interrupt identifier status
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0x10U)));
}

//*****************************************************************************
//
//! Get the CAN controller pending interrupt message source.
//!
//! \param base is the base address of the CAN controller.
//!
//! Returns the value of the pending interrupts register that indicates
//! which messages are the source of pending interrupts.
//!
//! \return Returns the value of the pending interrupts register.
//
//*****************************************************************************
static inline uint32_t
CAN_getInterruptMessageSource(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read message object interrupt status
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0xB0U)));
}

//*****************************************************************************
//
//! CAN Global interrupt Enable function.
//!
//! \param base is the base address of the CAN controller.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables specific CAN interrupt in the global interrupt enable register
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//! - \b CAN_GLOBAL_INT_CANINT0  - Global Interrupt Enable bit for CAN INT0
//! - \b CAN_GLOBAL_INT_CANINT1  - Global Interrupt Enable bit for CAN INT1
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_enableGlobalInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Enable the requested interrupts
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x50U)))) |= intFlags;
}

//*****************************************************************************
//
//! CAN Global interrupt Disable function.
//!
//! \param base is the base address of the CAN controller.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the specific CAN interrupt in the global interrupt enable register
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0
//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_disableGlobalInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Disable the requested interrupts
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x50U)))) &= ~intFlags;
}

//*****************************************************************************
//
//! CAN Global interrupt Clear function.
//!
//! \param base is the base address of the CAN controller.
//! \param intFlags is the bit mask of the interrupt sources to be cleared.
//!
//! Clear the specific CAN interrupt bit in the global interrupt flag register.
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0
//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1
//!
//! \return None.
//
//*****************************************************************************
static inline void
CAN_clearGlobalInterruptStatus(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear the requested interrupts
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x58U)))) |= intFlags;
}

//*****************************************************************************
//
//! Get the CAN Global Interrupt status.
//!
//! \param base is the base address of the CAN controller.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Check if any interrupt bit is set in the global interrupt flag register.
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0
//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1
//!
//! \return True if any of the requested interrupt bits are set. False, if
//! none of the requested bits are set.
//
//*****************************************************************************
static inline _Bool
CAN_getGlobalInterruptStatus(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read and return the global interrupt flag register
    //
    return((_Bool)(((*((volatile uint16_t *)((uintptr_t)(base + 0x54U)))) & intFlags) != 0U));
}

//*****************************************************************************
//
//! Initializes the CAN controller
//!
//! \param base is the base address of the CAN controller.
//!
//! This function initializes the message RAM, which also clears all the
//! message objects, and places the CAN controller in an init state. Write
//! access to the configuration registers is available as a result, allowing
//! the bit timing and message objects to be setup.
//!
//! \note To exit the initialization mode and start the CAN module, use the
//! CAN_startModule() function.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_initModule(uint32_t base);

//*****************************************************************************
//
//! Sets the CAN Bit Timing based on requested Bit Rate.
//!
//! \param base is the base address of the CAN controller.
//! \param clock is the CAN module clock frequency before the bit rate
//!        prescaler (Hertz)
//! \param bitRate is the desired bit rate (bits/sec)
//! \param bitTime is the number of time quanta per bit required for desired
//!        bit time (Tq) and must be in the range from 8 to 25
//!
//! This function sets the CAN bit timing values for the bit rate passed in the
//! \e bitRate and \e bitTime parameters based on the \e clock parameter.  The
//! CAN bit clock is calculated to be an average timing value that should work
//! for most systems.  If tighter timing requirements are needed, then the
//! CAN_setBitTiming() function is available for full customization of all of
//! the CAN bit timing values.
//!
//! \note Not all bit-rate and bit-time combinations are valid.
//!       For combinations that would yield the correct bit-rate,
//!       refer to the DCAN_CANBTR_values.xlsx file in the "docs" directory.
//!       The CANBTR register values calculated by the function CAN_setBitRate
//!       may not be suitable for your network parameters. If this is the case
//!       and you have computed the correct values for your network, you could
//!       directly write those parameters in CANBTR register using the
//!       function CAN_setBitTiming.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_setBitRate(uint32_t base, uint32_t clock, uint32_t bitRate,
               uint16_t bitTime);

//*****************************************************************************
//
//! Manually set the CAN controller bit timing.
//!
//! \param base is the base address of the CAN controller.
//! \param prescaler is the baud rate prescaler
//! \param prescalerExtension is the baud rate prescaler extension
//! \param tSeg1 is the time segment 1
//! \param tSeg2 is the time segment 2
//! \param sjw is the synchronization jump width
//!
//! This function sets the various timing parameters for the CAN bus bit
//! timing: baud rate prescaler, prescaler extension, time segment 1,
//! time segment 2, and the Synchronization Jump Width.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_setBitTiming(uint32_t base, uint16_t prescaler,
                 uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2,
                 uint16_t sjw);


//*****************************************************************************
//
//! Clears a CAN interrupt source.
//!
//! \param base is the base address of the CAN controller.
//! \param intClr is a value indicating which interrupt source to clear.
//!
//! This function can be used to clear a specific interrupt source.  The
//! \e intClr parameter should be either a number from 1 to 32 to clear a
//! specific message object interrupt or can be the following:
//! - \b CAN_INT_INT0ID_STATUS - Clears a status interrupt.
//!
//! It is not necessary to use this function to clear an interrupt.  This
//! should only be used if the application wants to clear an interrupt source
//! without taking the normal interrupt action.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_clearInterruptStatus(uint32_t base, uint32_t intClr);

//*****************************************************************************
//
//! Setup a Message Object
//!
//! \param base is the base address of the CAN controller.
//! \param objID is the message object number to configure (1-32).
//! \param msgID is the CAN message identifier used for the 11 or 29 bit
//!        identifiers
//! \param frame is the CAN ID frame type
//! \param msgType is the message object type
//! \param msgIDMask is the CAN message identifier mask used when identifier
//!        filtering is enabled
//! \param flags is the various flags and settings to be set for the message
//!        object
//! \param msgLen is the number of bytes of data in the message object (0-8)
//!
//! This function sets the various values required for a message object.
//!
//! The \e frame parameter can be one of the following values:
//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier
//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier
//!
//! The \e msgType parameter can be one of the following values:
//! - \b CAN_MSG_OBJ_TYPE_TX          - Transmit Message
//! - \b CAN_MSG_OBJ_TYPE_TX_REMOTE   - Transmit Remote Message
//! - \b CAN_MSG_OBJ_TYPE_RX          - Receive Message
//! - \b CAN_MSG_OBJ_TYPE_RXTX_REMOTE - Receive Remote message with
//!                                     auto-transmit
//!
//! The \e flags parameter can be set as \b CAN_MSG_OBJ_NO_FLAGS if no flags
//! are required or the parameter can be a logical OR of any of the following
//! values:
//! - \b CAN_MSG_OBJ_TX_INT_ENABLE    - Enable Transmit Interrupts
//! - \b CAN_MSG_OBJ_RX_INT_ENABLE    - Enable Receive Interrupts
//! - \b CAN_MSG_OBJ_USE_ID_FILTER    - Use filtering based on the Message ID
//! - \b CAN_MSG_OBJ_USE_EXT_FILTER   - Use filtering based on the Extended
//!                                     Message ID
//! - \b CAN_MSG_OBJ_USE_DIR_FILTER   - Use filtering based on the direction of
//!                                     the transfer
//! - \b CAN_MSG_OBJ_FIFO             - Message object is part of a FIFO
//!                                     structure and isn't the final message
//!                                     object in FIFO
//!
//! If filtering is based on message identifier, the value
//! \b CAN_MSG_OBJ_USE_ID_FILTER has to be logically ORed with the \e flag
//! parameter and \b CAN_MSG_OBJ_USE_EXT_FILTER also has to be ORed for
//! message identifier filtering to be based on the extended identifier.
//!
//! \note The \b msgLen Parameter for the Receive Message Object is a "don't
//!       care" but its value should be between 0-8 due to the assert.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID,
                       CAN_MsgFrameType frame, CAN_MsgObjType msgType,
                       uint32_t msgIDMask, uint32_t flags, uint16_t msgLen);

//*****************************************************************************
//
//! Sends a Message Object
//!
//! \param base is the base address of the CAN controller.
//! \param objID is the object number to configure (1-32).
//! \param msgLen is the number of bytes of data in the message object (0-8)
//! \param msgData is a pointer to the message object's data
//!
//! This function is used to transmit a message object and the message data,
//! if applicable.
//!
//! \note The message object requested by the \e objID must first be setup
//! using the CAN_setupMessageObject() function.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen,
                const uint16_t *msgData);

//*****************************************************************************
//
//! Sends a Remote Request Message Object
//!
//! \param base is the base address of the CAN controller.
//! \param objID is the object number to configure (1-32).
//!
//! This function is used to transmit a remote request message object.
//!
//! \note The message object requested by the \e objID must first be setup
//! using the CAN_setupMessageObject() function with CAN_MSG_OBJ_TYPE_TX_REMOTE
//! as msgType flag.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID);

//*****************************************************************************
//
//! Reads the data in a Message Object
//!
//! \param base is the base address of the CAN controller.
//! \param objID is the object number to read (1-32).
//! \param msgData is a pointer to the array to store the message data
//!
//! This function is used to read the data contents of the specified message
//! object in the CAN controller. The data returned is stored in the
//! \e msgData parameter.
//!
//! \note
//! -# The message object requested by the \e objID must first be setup
//! using the CAN_setupMessageObject() function.
//! -# If the DLC of the received message is larger than the \e msgData
//! buffer provided, then it is possible for a buffer overflow to occur.
//!
//! \return Returns \b true if new data was retrieved, else returns
//! \b false to indicate no new data was retrieved.
//
//*****************************************************************************
extern _Bool
CAN_readMessage(uint32_t base, uint32_t objID,
                uint16_t *msgData);

//*****************************************************************************
//
//! Reads the data and Message ID in a Message Object
//!
//! \param base is the base address of the CAN controller.
//! \param objID is the object number to read (1-32).
//! \param frameType is a pointer to the CAN_MsgFrameType to store the message
//!        type that has been received in the mailbox
//! The \e frameType parameter shall be filled as of the following values:
//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier
//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier
//! This parameter is filled when return value is true for this function.
//! \param msgID is a pointer to storage for the received Message ID
//! Filled when the return value is true for this function.
//! \param msgData is a pointer to the array to store the message data
//! Filled with read Data when the return value is true for this function.
//!
//! This function is used to read the data contents and the Message ID
//! of the specified message object in the CAN controller.The Message returned
//! is stored in the \e msgID parameter and its type in \e frameType parameter.
//! The data returned is stored in the \e msgData parameter.
//!
//! \note
//! -# The message object requested by the \e objID must first be setup
//! using the CAN_setupMessageObject() function.
//!
//! \return Returns \b true if new data was retrieved, else returns
//! \b false to indicate no new data was retrieved.
//
//*****************************************************************************
extern _Bool CAN_readMessageWithID(uint32_t base,
                                  uint32_t objID,
                                  CAN_MsgFrameType *frameType,
                                  uint32_t *msgID,
                                  uint16_t *msgData);


//*****************************************************************************
//
//! Transfers a CAN message between the IF registers and Message RAM.
//!
//! \param base is the base address of the CAN controller.
//! \param interface is the interface to use for the transfer. Valid value are
//!        1 or 2.
//! \param objID is the object number to transfer (1-32).
//! \param direction is the of the transfer. False is Message RAM to IF, True
//!        is IF to Message RAM.
//! \param dmaRequest asserts the DMA request line after a transfer if
//!        set to True.
//!
//! This function transfers the contents of the interface registers to message
//! RAM or vice versa depending on the value passed to direction.  This
//! function is designed to be used with DMA transfers.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID,
                    _Bool direction, _Bool dmaRequest);


//*****************************************************************************
//
//! Clears a message object so that it is no longer used.
//!
//! \param base is the base address of the CAN controller.
//! \param objID is the message object number to disable (1-32).
//!
//! This function frees(disables) the specified message object from use. Once
//! a message object has been cleared, it will no longer automatically send or
//! receive messages, or generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_clearMessage(uint32_t base, uint32_t objID);

//*****************************************************************************
//
//! Disables all message objects
//!
//! \param base is the base address of the CAN controller.
//!
//! This function disables all message objects. Once a message object
//! has been disabled it will be ignored by the message handler until it
//! is configured again. All message objects are disabled automatically on
//! reset, however this function can be used to restart CAN operations
//! without an external reset.
//!
//! \return None.
//
//*****************************************************************************
extern void
CAN_disableAllMessageObjects(uint32_t base);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************


//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   cla.h
//
// TITLE:  CLA Driver Implementation File
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup cla_api CLA
//! \brief This module is used for configurating CLA.
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_cla.h
//
// TITLE:   Definitions for the CLA registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the CLA register offsets
//
//*************************************************************************************************



//*************************************************************************************************
//
// The following are defines for the bit fields in the MCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTINTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the _MSTSBGRND register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the _MCTLBGRND register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MIFR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MIOVF register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MIFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MICLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MICLROVF register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MIER register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MIRUN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the _MSTF register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the _MPSACTL register
//
//*************************************************************************************************
                                         // changes.





//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to CLA_getBackgroundTaskStatus() as the
//! \e stsFlag parameter.
//
//*****************************************************************************
typedef enum
{
    //! Run status
    CLA_BGSTS_RUNNING          = 0x1U,
    //! Can BG task be interrupted?
    CLA_BGSTS_CANNOT_INTERRUPT = 0x2U,
    //! BG task hardware trigger overflow - if a second trigger occurs
    //! while the BG is already running, the overflow is set
    CLA_BGSTS_OVERFLOW         = 0x4U
} CLA_BGTaskStatus;

//*****************************************************************************
//
// Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(),
// and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt()
// as the taskFlags parameter.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to CLA_getPendingTaskFlag(),
//! CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(),
//! CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt()
//! as the taskNumber parameter.
//
//*****************************************************************************
typedef enum
{
    CLA_TASK_1,  //!< CLA Task 1
    CLA_TASK_2,  //!< CLA Task 2
    CLA_TASK_3,  //!< CLA Task 3
    CLA_TASK_4,  //!< CLA Task 4
    CLA_TASK_5,  //!< CLA Task 5
    CLA_TASK_6,  //!< CLA Task 6
    CLA_TASK_7,  //!< CLA Task 7
    CLA_TASK_8   //!< CLA Task 8
} CLA_TaskNumber;

//*****************************************************************************
//
//! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect
//! parameter.
//
//*****************************************************************************
typedef enum
{
    CLA_MVECT_1 = 0x0U,     //!< Task Interrupt Vector 1
    CLA_MVECT_2 = 0x1U,     //!< Task Interrupt Vector 2
    CLA_MVECT_3 = 0x2U,     //!< Task Interrupt Vector 3
    CLA_MVECT_4 = 0x3U,     //!< Task Interrupt Vector 4
    CLA_MVECT_5 = 0x4U,     //!< Task Interrupt Vector 5
    CLA_MVECT_6 = 0x5U,     //!< Task Interrupt Vector 6
    CLA_MVECT_7 = 0x6U,     //!< Task Interrupt Vector 7
    CLA_MVECT_8 = 0x7U      //!< Task Interrupt Vector 8
} CLA_MVECTNumber;

//*****************************************************************************
//
//! Values that can be passed to CLA_setTriggerSource() as the \e trigger
//! parameter.
//
//*****************************************************************************
typedef enum
{
    CLA_TRIGGER_SOFTWARE    = 0U,   //!< CLA Task Trigger Source is Software

    CLA_TRIGGER_ADCA1       = 1U,   //!< CLA Task Trigger Source is ADCA1
    CLA_TRIGGER_ADCA2       = 2U,   //!< CLA Task Trigger Source is ADCA2
    CLA_TRIGGER_ADCA3       = 3U,   //!< CLA Task Trigger Source is ADCA3
    CLA_TRIGGER_ADCA4       = 4U,   //!< CLA Task Trigger Source is ADCA4
    CLA_TRIGGER_ADCAEVT     = 5U,   //!< CLA Task Trigger Source is ADCAEVT
    CLA_TRIGGER_ADCB1       = 6U,   //!< CLA Task Trigger Source is ADCB1
    CLA_TRIGGER_ADCB2       = 7U,   //!< CLA Task Trigger Source is ADCB2
    CLA_TRIGGER_ADCB3       = 8U,   //!< CLA Task Trigger Source is ADCB3
    CLA_TRIGGER_ADCB4       = 9U,   //!< CLA Task Trigger Source is ADCB4
    CLA_TRIGGER_ADCBEVT     = 10U,  //!< CLA Task Trigger Source is ADCBEVT
    CLA_TRIGGER_ADCC1       = 11U,  //!< CLA Task Trigger Source is ADCC1
    CLA_TRIGGER_ADCC2       = 12U,  //!< CLA Task Trigger Source is ADCC2
    CLA_TRIGGER_ADCC3       = 13U,  //!< CLA Task Trigger Source is ADCC3
    CLA_TRIGGER_ADCC4       = 14U,  //!< CLA Task Trigger Source is ADCC4
    CLA_TRIGGER_ADCCEVT     = 15U,  //!< CLA Task Trigger Source is ADCCEVT

    CLA_TRIGGER_XINT1       = 29U,  //!< CLA Task Trigger Source is XINT1
    CLA_TRIGGER_XINT2       = 30U,  //!< CLA Task Trigger Source is XINT2
    CLA_TRIGGER_XINT3       = 31U,  //!< CLA Task Trigger Source is XINT3
    CLA_TRIGGER_XINT4       = 32U,  //!< CLA Task Trigger Source is XINT4
    CLA_TRIGGER_XINT5       = 33U,  //!< CLA Task Trigger Source is XINT5

    CLA_TRIGGER_EPWM1INT    = 36U,  //!< CLA Task Trigger Source is EPWM1INT
    CLA_TRIGGER_EPWM2INT    = 37U,  //!< CLA Task Trigger Source is EPWM2INT
    CLA_TRIGGER_EPWM3INT    = 38U,  //!< CLA Task Trigger Source is EPWM3INT
    CLA_TRIGGER_EPWM4INT    = 39U,  //!< CLA Task Trigger Source is EPWM4INT
    CLA_TRIGGER_EPWM5INT    = 40U,  //!< CLA Task Trigger Source is EPWM5INT
    CLA_TRIGGER_EPWM6INT    = 41U,  //!< CLA Task Trigger Source is EPWM6INT
    CLA_TRIGGER_EPWM7INT    = 42U,  //!< CLA Task Trigger Source is EPWM7INT
    CLA_TRIGGER_EPWM8INT    = 43U,  //!< CLA Task Trigger Source is EPWM8INT

    CLA_TRIGGER_MCANA_FEVT0 = 52U,  //!< CLA Task Trigger Source is MCANAFEVT0
    CLA_TRIGGER_MCANA_FEVT1 = 53U,  //!< CLA Task Trigger Source is MCANAFEVT1
    CLA_TRIGGER_MCANA_FEVT2 = 54U,  //!< CLA Task Trigger Source is MCANAFEVT2

    CLA_TRIGGER_TINT0       = 68U,  //!< CLA Task Trigger Source is TINT0
    CLA_TRIGGER_TINT1       = 69U,  //!< CLA Task Trigger Source is TINT1
    CLA_TRIGGER_TINT2       = 70U,  //!< CLA Task Trigger Source is TINT2


    CLA_TRIGGER_ECAP1INT    = 75U,  //!< CLA Task Trigger Source is ECAP1INT
    CLA_TRIGGER_ECAP2INT    = 76U,  //!< CLA Task Trigger Source is ECAP2INT
    CLA_TRIGGER_ECAP3INT    = 77U,  //!< CLA Task Trigger Source is ECAP3INT

    CLA_TRIGGER_EQEP1INT    = 83U,  //!< CLA Task Trigger Source is EQEP1INT
    CLA_TRIGGER_EQEP2INT    = 84U,  //!< CLA Task Trigger Source is EQEP2INT

    CLA_TRIGGER_ECAP3INT2   = 89U,  //!< CLA Task Trigger Source is ECAP3INT2

    CLA_TRIGGER_SDFM1INT    = 95U,  //!< CLA Task Trigger Source is SDFM1INT
    CLA_TRIGGER_SDFM1DRINT1 = 96U,  //!< CLA Task Trigger Srce is SDFM1DRINT1
    CLA_TRIGGER_SDFM1DRINT2 = 97U,  //!< CLA Task Trigger Srce is SDFM1DRINT2
    CLA_TRIGGER_SDFM1DRINT3 = 98U,  //!< CLA Task Trigger Srce is SDFM1DRINT3
    CLA_TRIGGER_SDFM1DRINT4 = 99U,  //!< CLA Task Trigger Srce is SDFM1DRINT4
    CLA_TRIGGER_SDFM2INT    = 100U,  //!< CLA Task Trigger Source is SDFM2INT
    CLA_TRIGGER_SDFM2DRINT1 = 101U,  //!< CLA Task Trigger Srce is SDFM2DRINT1
    CLA_TRIGGER_SDFM2DRINT2 = 102U,  //!< CLA Task Trigger Srce is SDFM2DRINT2
    CLA_TRIGGER_SDFM2DRINT3 = 103U,  //!< CLA Task Trigger Srce is SDFM2DRINT3
    CLA_TRIGGER_SDFM2DRINT4 = 104U,  //!< CLA Task Trigger Srce is SDFM2DRINT4


    CLA_TRIGGER_PMBUSAINT   = 105U, //!< CLA Task Trigger Source is PMBUSAINT


    CLA_TRIGGER_SPITXAINT   = 109U, //!< CLA Task Trigger Source is SPITXAINT
    CLA_TRIGGER_SPIRXAINT   = 110U, //!< CLA Task Trigger Source is SPIRXAINT
    CLA_TRIGGER_SPITXBINT   = 111U, //!< CLA Task Trigger Source is SPITXBINT
    CLA_TRIGGER_SPIRXBINT   = 112U, //!< CLA Task Trigger Source is SPIRXBINT

    CLA_TRIGGER_LINAINT1    = 117U, //!< CLA Task Trigger Source is LINAINT1
    CLA_TRIGGER_LINAINT0    = 118U, //!< CLA Task Trigger Source is LINAINT0
    CLA_TRIGGER_LINBINT1    = 119U, //!< CLA Task Trigger Source is LINAINT1
    CLA_TRIGGER_LINBINT0    = 120U, //!< CLA Task Trigger Source is LINAINT0


    CLA_TRIGGER_CLA1CRCINT  = 121U, //!< CLA Task Trigger Srce is CLA1CRCINT

    CLA_TRIGGER_FSITXAINT1  = 123U, //!< CLA Task Trigger Source is FSITXAINT1
    CLA_TRIGGER_FSITXAINT2  = 124U, //!< CLA Task Trigger Source is FSITXAINT2
    CLA_TRIGGER_FSIRXAINT1  = 125U, //!< CLA Task Trigger Source is FSIRXAINT1
    CLA_TRIGGER_FSIRXAINT2  = 126U, //!< CLA Task Trigger Source is FSIRXAINT2

    CLA_TRIGGER_CLB1INT      = 127, //!< CLA Task Trigger Source is CLB1INT
    CLA_TRIGGER_CLB2INT      = 128, //!< CLA Task Trigger Source is CLB2INT
    CLA_TRIGGER_CLB3INT      = 129, //!< CLA Task Trigger Source is CLB3INT
    CLA_TRIGGER_CLB4INT      = 130, //!< CLA Task Trigger Source is CLB4INT

    CLA_TRIGGER_HICAINT    = 179U,  //!< CLA Task Trigger Source is HICA_INT

    CLA_TRIGGER_DMACH1INT  = 184U,  //!< CLA Task Trigger Source is DMA_CH1INT
    CLA_TRIGGER_DMACH2INT  = 185U,  //!< CLA Task Trigger Source is DMA_CH2INT
    CLA_TRIGGER_DMACH3INT  = 186U,  //!< CLA Task Trigger Source is DMA_CH3INT
    CLA_TRIGGER_DMACH4INT  = 187U,  //!< CLA Task Trigger Source is DMA_CH4INT
    CLA_TRIGGER_DMACH5INT  = 188U,  //!< CLA Task Trigger Source is DMA_CH5INT
    CLA_TRIGGER_DMACH6INT  = 189U,  //!< CLA Task Trigger Source is DMA_CH6INT
} CLA_Trigger;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a CLA base address.
//!
//! \param base is the base address of the CLA controller.
//!
//! This function determines if a CLA controller base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Map CLA Task Interrupt Vector
//!
//! \param base is the base address of the CLA controller.
//! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8)
//! the value of claIntVect can be any of the following:
//! - \b CLA_MVECT_1 - Task Interrupt Vector 1
//! - \b CLA_MVECT_2 - Task Interrupt Vector 2
//! - \b CLA_MVECT_3 - Task Interrupt Vector 3
//! - \b CLA_MVECT_4 - Task Interrupt Vector 4
//! - \b CLA_MVECT_5 - Task Interrupt Vector 5
//! - \b CLA_MVECT_6 - Task Interrupt Vector 6
//! - \b CLA_MVECT_7 - Task Interrupt Vector 7
//! - \b CLA_MVECT_8 - Task Interrupt Vector 8
//! \param claTaskAddr is the start address of the code for task
//!
//! Each CLA Task (1 to 8) has its own MVECTx register. When a task is
//! triggered, the CLA loads the MVECTx register of the task in question
//! to the MPC (CLA program counter) and begins execution from that point.
//! The CLA has a 16-bit address bus, and can therefore, access the lower
//! 64 KW space. The MVECTx registers take an address anywhere in this space.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect,
                  uint16_t claTaskAddr)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + (uint16_t)claIntVect)))) = claTaskAddr;

    __edis();
}

//*****************************************************************************
//
//! Hard Reset
//!
//! \param base is the base address of the CLA controller.
//!
//! This function will cause a hard reset of the CLA and set all CLA registers
//! to their default state.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_performHardReset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Hard reset of the CLA
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) |= 0x1U;

    __edis();

    //
    // Wait for few cycles till the reset is complete
    //
    __asm(" NOP");
    __asm(" NOP");
    __asm(" NOP");
}

//*****************************************************************************
//
//! Soft Reset
//!
//! \param base is the base address of the CLA controller.
//!
//! This function will cause a soft reset of the CLA. This will stop the
//! current task, clear the MIRUN flag and clear all bits in the MIER register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_performSoftReset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Soft reset of the CLA
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) |= 0x2U;

    __edis();

    //
    // Wait for few cycles till the reset is complete
    //
    __asm(" NOP");
    __asm(" NOP");
    __asm(" NOP");
}

//*****************************************************************************
//
//! IACK enable
//!
//! \param base is the base address of the CLA controller.
//!
//! This function enables the main CPU to use the IACK #16bit instruction to
//! set MIFR bits in the same manner as writing to the MIFRC register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_enableIACK(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Enable the main CPU to use the IACK #16bit instruction
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) |= 0x4U;

    __edis();
}

//*****************************************************************************
//
//! IACK disable
//!
//! \param base is the base address of the CLA controller.
//!
//! This function disables the main CPU to use the IACK #16bit instruction to
//! set MIFR bits in the same manner as writing to the MIFRC register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_disableIACK(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Enable the main CPU to use the IACK #16bit instruction
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) &= ~0x4U;

    __edis();
}

//*****************************************************************************
//
//! Query task N to see if it is flagged and pending execution
//!
//! \param base is the base address of the CLA controller.
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
//!
//! This function gets the status of each bit in the interrupt flag register
//! corresponds to a CLA task.  The corresponding bit is automatically set
//! when the task is triggered (either from a peripheral, through software, or
//! through the MIFRC register). The bit gets cleared when the CLA starts to
//! execute the flagged task.
//!
//! \return \b True if the queried task has been triggered but pending
//! execution.
//
//*****************************************************************************
static inline _Bool
CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the run status register and return the appropriate value.
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) >> (uint16_t)taskNumber) & 1U) != 0U);
}

//*****************************************************************************
//
//! Get status of All Task Interrupt Flag
//!
//! \param base is the base address of the CLA controller.
//!
//! This function gets the value of the interrupt flag register (MIFR)
//!
//! \return the value of Interrupt Flag Register (MIFR)
//
//*****************************************************************************
static inline uint16_t
CLA_getAllPendingTaskFlags(uint32_t base)
{
    uint16_t status;

    //
    // Check the arguments.
    //
    ;

    //
    // Just return the Interrupt Flag Register (MIFR) since that is what was
    // requested.
    //
    status = (*((volatile uint16_t *)((uintptr_t)(base + 0x20U))));

    //
    // Return the Interrupt Flag Register value
    //
    return(status);
}

//*****************************************************************************
//
//! Get status of Task n Interrupt Overflow Flag
//!
//! \param base is the base address of the CLA controller.
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
//!
//! This function gets the status of each bit in the overflow flag register
//! corresponds to a CLA task, This bit is set when an interrupt overflow event
//! has occurred for the specific task.
//!
//! \return True if any of task interrupt overflow has occurred.
//
//*****************************************************************************
static inline _Bool
CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the run status register and return the appropriate value.
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x21U)))) >> (uint16_t)taskNumber) & 1U) != 0U);
}

//*****************************************************************************
//
//! Get status of All Task Interrupt Overflow Flag
//!
//! \param base is the base address of the CLA controller.
//!
//! This function gets the value of the Interrupt Overflow Flag Register
//!
//! \return the value of Interrupt Overflow Flag Register(MIOVF)
//
//*****************************************************************************
static inline uint16_t
CLA_getAllTaskOverflowFlags(uint32_t base)
{
    uint16_t status;

    //
    // Check the arguments.
    //
    ;

    //
    // Just return Interrupt Overflow Flag Register(MIOVF) since that is what
    // was requested.
    //
    status = (*((volatile uint16_t *)((uintptr_t)(base + 0x21U))));

    //
    // Return the Interrupt Overflow Flag Register
    //
    return(status);
}

//*****************************************************************************
//
//! Clear the task interrupt flag
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be cleared
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to clear all flags.
//!
//! This function is used to manually clear bits in the interrupt
//! flag (MIFR) register
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    //Modify protected register
    //
    __eallow();

    //
    // Clear the task interrupt flag
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x23U)))) |= taskFlags;

    __edis();
}

//*****************************************************************************
//
//! Force a CLA Task
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be forced
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to force all tasks.
//!
//! This function forces a task through software.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_forceTasks(uint32_t base, uint16_t taskFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Force the task interrupt.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x22U)))) |= taskFlags;

    __edis();
}

//*****************************************************************************
//
//! Enable CLA task(s)
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be enabled
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to enable all tasks
//!
//! This function allows an incoming interrupt or main CPU software to
//! start the corresponding CLA task.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_enableTasks(uint32_t base, uint16_t taskFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Enable CLA task
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x25U)))) |= taskFlags;

    __edis();
}

//*****************************************************************************
//
//! Disable CLA task interrupt
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be disabled
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to disable all tasks
//!
//! This function disables CLA task interrupt by setting the MIER register bit
//! to 0, while the corresponding task is executing this will have no effect
//! on the task. The task will continue to run until it hits the MSTOP
//! instruction.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_disableTasks(uint32_t base, uint16_t taskFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Disable CLA task interrupt
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x25U)))) &= ~taskFlags;

    __edis();
}

//*****************************************************************************
//
//! Get the value of a task run status
//!
//! \param base is the base address of the CLA controller.
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
//!
//! This function gets the status of each bit in the Interrupt Run Status
//! Register which indicates whether the task is currently executing
//!
//! \return True if the task is executing.
//
//*****************************************************************************
static inline _Bool
CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the run status register and return the appropriate value.
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x26U)))) >> (uint16_t)taskNumber) & 1U) != 0U);
}

//*****************************************************************************
//
//! Get the value of all task run status
//!
//! \param base is the base address of the CLA controller.
//!
//! This function indicates which task is currently executing.
//!
//! \return the value of Interrupt Run Status Register (MIRUN)
//
//*****************************************************************************
static inline uint16_t
CLA_getAllTaskRunStatus(uint32_t base)
{
    uint16_t status;

    //
    // Check the arguments.
    //
    ;

    //
    // Just return the Interrupt Run Status Register since that is what was
    // requested.
    //
    status = (*((volatile uint16_t *)((uintptr_t)(base + 0x26U))));

    //
    // Return the Interrupt Run Status Register (MIRUN)
    //
    return(status);
}
//*****************************************************************************
//
//! Get the value of Active register for MVECTBGRNDACTIVE
//!
//! \param base is the base address of the CLA controller.
//!
//! This function gives the current interrupted MPC value of the background
//! task.
//!
//! \return the value of Active register for the Background Task Vector
//
//*****************************************************************************
static inline uint16_t
CLA_getBackgroundActiveVector(uint32_t base)
{
    uint16_t status;

    //
    // Check the arguments.
    //
    ;

    //
    // Just return the Active register for the Background Task Vector since
    // that is what was requested.
    //
    status = (*((volatile uint16_t *)((uintptr_t)(base + 0x1BU))));

    //
    // Return the value of Active register for the Background Task Vector
    //
    return(status);
}

//*****************************************************************************
//
//! Enable the background task
//!
//! \param base is the base address of the CLA controller.
//!
//! This function enables the background task
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_enableBackgroundTask(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Enable background task
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) |= 0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Disable background task
//!
//! \param base is the base address of the CLA controller.
//!
//! This function disables the background task
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_disableBackgroundTask(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Disables background task
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) &= ~0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Start background task
//!
//! \param base is the base address of the CLA controller.
//!
//! This function will start the background task, provided there are no other
//! pending tasks.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_startBackgroundTask(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Start background task
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) |= 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Enable background task hardware trigger
//!
//! \param base is the base address of the CLA controller.
//!
//! This function enables hardware trigger for background task
//! \note Trigger source for the background task will be MPERINT8.1.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_enableHardwareTrigger(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Enable background task hardware trigger
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) |= 0x2U;

    __edis();
}

//*****************************************************************************
//
//! Disable background task hardware trigger
//!
//! \param base is the base address of the CLA controller.
//!
//! This function disables hardware trigger for background task
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_disableHardwareTrigger(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    //
    // Disables hardware trigger for background task
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) &= ~0x2U;

    __edis();
}

//*****************************************************************************
//
//! Map background task vector
//!
//! \param base is the base address of the CLA controller.
//! \param claTaskAddr is the start address of the code for task
//!
//! This function specifies the start address for the background task
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_mapBackgroundTaskVector(uint32_t base, uint16_t claTaskAddr)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Modify protected register
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x1FU)))) = (uint16_t)claTaskAddr;

    __edis();
}

//*****************************************************************************
//
//! Get Status register for the back ground task.
//!
//! \param base is the base address of the CLA controller.
//! \param stsFlag is status item to be returned.
//!
//! The value of \e stsFlag can be any of the following:
//! - \b CLA_BGSTS_RUNNING
//! - \b CLA_BGSTS_CANNOT_INTERRUPT
//! - \b CLA_BGSTS_OVERFLOW
//!
//! This function gets the status of background task
//!
//! \return Based on the value of \e stsFlag, the function will return:
//! - \b CLA_BGSTS_RUNNING - The function will return \b true if the background
//!   task is running.
//! - \b CLA_BGSTS_CANNOT_INTERRUPT - The function will return \b true if the
//!   background task will not be interrupted (when MSETC BGINTM is executed).
//! - \b CLA_BGSTS_OVERFLOW - This function will return \b true if an enabled
//!   hardware trigger occurred while _MCTLBGRND.BGSTART is set.
//
//*****************************************************************************
static inline _Bool
CLA_getBackgroundTaskStatus(uint32_t base, CLA_BGTaskStatus stsFlag)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Return the background task status value
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1DU)))) & (uint16_t)stsFlag) != 0U);
}


//
// These functions are accessible only from the CLA (Type - 1/2)
//

//
// These functions can only be called from the C28x
//

//*****************************************************************************
//
//! Configures CLA task triggers.
//!
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8.
//! \param trigger is the trigger source to be assigned to the selected task.
//!
//! This function configures the trigger source of a CLA task. The
//! \e taskNumber parameter indicates which task is being configured, and the
//! \e trigger parameter is the interrupt source from a specific peripheral
//! interrupt (or software) that will trigger the task.
//!
//! \return None.
//
//*****************************************************************************
extern void
CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   clb.h
//
// TITLE:  C28x CLB driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup clb_api CLB
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_clb.h
//
// TITLE:   Definitions for the CLB registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the CLB register offsets
//
//*************************************************************************************************
                                            // controller

                                           // synchronizers
                                           // register
                                           // outputs



//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_RESET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_MODE_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_MODE_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_EVENT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_LUT_FN1_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_LUT_FN2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_FN1_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_FN2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_MISC_CONTROL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_5 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_6 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_7 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_HLC_EVENT_SEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_MATCH_TAP_SEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_5 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_6 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_COND_CTRL_7 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_MISC_ACCESS_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_SPI_DATA_CTRL_HI register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LOAD_EN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LOAD_ADDR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_INPUT_FILTER register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_IN_MUX_SEL_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_BUF_PTR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_GP_REG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_PRESCALE_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_INTR_TAG_REG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_HLC_INSTR_READ_PTR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_HLC_INSTR_VALUE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_DBG_OUT_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_DBG_OUT register
//
//*************************************************************************************************





//*****************************************************************************
//
// Address offsets from LOGICCFG to LOGICCTL and DATAEXCH register memory maps
//
//*****************************************************************************

//*****************************************************************************
//
// Address offsets for CLB-internal memory space
//
//*****************************************************************************





//*****************************************************************************
//
// PUSH/PULL FIFO size (32-bit registers)
//
//*****************************************************************************

//*****************************************************************************
//
// Key to enable writes to the CLB registers
//
//*****************************************************************************

//*****************************************************************************
//
// Shift and masks needed by the API for Input selection
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to control the CLB output enable signal. It can
//! be passed to CLB_setOutputMask() as the \e outputMask parameter.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to select CLB input signal
//
//*****************************************************************************
typedef enum
{
    CLB_IN0 = 0,                    //!< Input 0
    CLB_IN1 = 1,                    //!< Input 1
    CLB_IN2 = 2,                    //!< Input 2
    CLB_IN3 = 3,                    //!< Input 3
    CLB_IN4 = 4,                    //!< Input 4
    CLB_IN5 = 5,                    //!< Input 5
    CLB_IN6 = 6,                    //!< Input 6
    CLB_IN7 = 7                     //!< Input 7
} CLB_Inputs;

//*****************************************************************************
//
//! Values that can be passed to select CLB output signal. It can be passed to
//! CLB_configOutputLUT() as the \e outID parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_OUT0 = 0,                   //!< Output 0
    CLB_OUT1 = 1,                   //!< Output 1
    CLB_OUT2 = 2,                   //!< Output 2
    CLB_OUT3 = 3,                   //!< Output 3
    CLB_OUT4 = 4,                   //!< Output 4
    CLB_OUT5 = 5,                   //!< Output 5
    CLB_OUT6 = 6,                   //!< Output 6
    CLB_OUT7 = 7                    //!< Output 7
} CLB_Outputs;

//*****************************************************************************
//
//! Values that can be passed to select CLB AOC signal. It can be passed to
//! CLB_configAOC() as the \e aocID parameter.
//! AOC is the Asynchronous Output Conditioning block.
//
//*****************************************************************************
typedef enum
{
    CLB_AOC0 = 0,                   //!< AOC 0
    CLB_AOC1 = 1,                   //!< AOC 1
    CLB_AOC2 = 2,                   //!< AOC 2
    CLB_AOC3 = 3,                   //!< AOC 3
    CLB_AOC4 = 4,                   //!< AOC 4
    CLB_AOC5 = 5,                   //!< AOC 5
    CLB_AOC6 = 6,                   //!< AOC 6
    CLB_AOC7 = 7                    //!< AOC 7
} CLB_AOCs;

//*****************************************************************************
//
//! Values that can be passed to set/clear CLB SW release signals. It can
//! be passed to CLB_writeSWReleaseControl() as the \e inID parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_SW_RLS_CTRL0 = 0,           //!< SW RLS CTRL 0
    CLB_SW_RLS_CTRL1 = 1,           //!< SW RLS CTRL 1
    CLB_SW_RLS_CTRL2 = 2,           //!< SW RLS CTRL 2
    CLB_SW_RLS_CTRL3 = 3,           //!< SW RLS CTRL 3
    CLB_SW_RLS_CTRL4 = 4,           //!< SW RLS CTRL 4
    CLB_SW_RLS_CTRL5 = 5,           //!< SW RLS CTRL 5
    CLB_SW_RLS_CTRL6 = 6,           //!< SW RLS CTRL 6
    CLB_SW_RLS_CTRL7 = 7            //!< SW RLS CTRL 7
} CLB_SWReleaseCtrl;

//*****************************************************************************
//
//! Values that can be passed to set/clear CLB SW release signals. It can
//! be passed to CLB_writeSWGateControl() as the \e inID parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_SW_GATE_CTRL0 = 0,           //!< SW GATE CTRL 0
    CLB_SW_GATE_CTRL1 = 1,           //!< SW GATE CTRL 1
    CLB_SW_GATE_CTRL2 = 2,           //!< SW GATE CTRL 2
    CLB_SW_GATE_CTRL3 = 3,           //!< SW GATE CTRL 3
    CLB_SW_GATE_CTRL4 = 4,           //!< SW GATE CTRL 4
    CLB_SW_GATE_CTRL5 = 5,           //!< SW GATE CTRL 5
    CLB_SW_GATE_CTRL6 = 6,           //!< SW GATE CTRL 6
    CLB_SW_GATE_CTRL7 = 7            //!< SW GATE CTRL 7
} CLB_SWGateCtrl;

//*****************************************************************************
//
//! Values that can be passed to select CLB counter. It can be passed to
//! CLB_configCounterLoadMatch() as the \e counterID parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_CTR0 = 0,                   //!< Counter 0
    CLB_CTR1 = 1,                   //!< Counter 1
    CLB_CTR2 = 2                    //!< Counter 2
} CLB_Counters;

//*****************************************************************************
//
//! Values that can be passed to CLB_getRegister() as the \e registerID
//! parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_REG_HLC_R0 = 0x30U,  //!< HLC R0 register
    CLB_REG_HLC_R1 = 0x32U,  //!< HLC R1 register
    CLB_REG_HLC_R2 = 0x34U,  //!< HLC R2 register
    CLB_REG_HLC_R3 = 0x36U,  //!< HLC R3 register
    CLB_REG_CTR_C0 = 0x38U,  //!< Counter 0 register
    CLB_REG_CTR_C1 = 0x3AU,  //!< Counter 1 register
    CLB_REG_CTR_C2 = 0x3CU   //!< Counter 2 register
} CLB_Register;

//*****************************************************************************
//
//! Values that can be passed to CLB_selectInputFilter() as the \e filterType
//! parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_FILTER_NONE         = 0,    //!< No filtering
    CLB_FILTER_RISING_EDGE  = 1,    //!< Rising edge detect
    CLB_FILTER_FALLING_EDGE = 2,    //!< Falling edge detect
    CLB_FILTER_ANY_EDGE     = 3     //!< Any edge detect
} CLB_FilterType;

//*****************************************************************************
//
//! Values that can be passed to CLB_configGPInputMux() as the \e gpMuxCfg
//! parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_GP_IN_MUX_EXTERNAL  = 0,    //!< Use external input path
    CLB_GP_IN_MUX_GP_REG    = 1     //!< Use CLB_GP_REG bit value as input
} CLB_GPInputMux;

//*****************************************************************************
//
//! Values that can be passed to CLB_configLocalInputMux() as the
//! \e localMuxCfg parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_LOCAL_IN_MUX_GLOBAL_IN          = 0,   //!< Global input mux selection
    CLB_LOCAL_IN_MUX_EPWM_DCAEVT1       = 1,   //!< EPWMx DCAEVT1
    CLB_LOCAL_IN_MUX_EPWM_DCAEVT2       = 2,   //!< EPWMx DCAEVT2
    CLB_LOCAL_IN_MUX_EPWM_DCBEVT1       = 3,   //!< EPWMx DCBEVT1
    CLB_LOCAL_IN_MUX_EPWM_DCBEVT2       = 4,   //!< EPWMx DCBEVT2
    CLB_LOCAL_IN_MUX_EPWM_DCAH          = 5,   //!< EPWMx DCAH
    CLB_LOCAL_IN_MUX_EPWM_DCAL          = 6,   //!< EPWMx DCAL
    CLB_LOCAL_IN_MUX_EPWM_DCBH          = 7,   //!< EPWMx DCBH
    CLB_LOCAL_IN_MUX_EPWM_DCBL          = 8,   //!< EPWMx DCBL
    CLB_LOCAL_IN_MUX_EPWM_OST           = 9,   //!< EPWMx OST
    CLB_LOCAL_IN_MUX_EPWM_CBC           = 10,  //!< EPWMx CBC
    CLB_LOCAL_IN_MUX_ECAP_ECAPIN        = 11,  //!< ECAPx ECAPIN
    CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT      = 12,  //!< ECAPx ECAP_OUT
    CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN   = 13,  //!< ECAPx ECAP_OUT_EN
    CLB_LOCAL_IN_MUX_ECAP_CEVT1         = 14,  //!< ECAPx CEVT1
    CLB_LOCAL_IN_MUX_ECAP_CEVT2         = 15,  //!< ECAPx CEVT2
    CLB_LOCAL_IN_MUX_ECAP_CEVT3         = 16,  //!< ECAPx CEVT3
    CLB_LOCAL_IN_MUX_ECAP_CEVT4         = 17,  //!< ECAPx CEVT4
    CLB_LOCAL_IN_MUX_EQEP_EQEPA         = 18,  //!< EQEPx EQEPA
    CLB_LOCAL_IN_MUX_EQEP_EQEPB         = 19,  //!< EQEPx EQEPB
    CLB_LOCAL_IN_MUX_EQEP_EQEPI         = 20,  //!< EQEPx EQEPI
    CLB_LOCAL_IN_MUX_EQEP_EQEPS         = 21,  //!< EQEPx EQEPS
    CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC     = 22,  //!< CPU1.TBCLKSYNC
    CLB_LOCAL_IN_MUX_CPU1_HALT          = 24,  //!< CPU1.HALT
    CLB_LOCAL_IN_MUX_SPISIMO_MASTER     = 25,  //!< SPISIMO Master Output
    CLB_LOCAL_IN_MUX_SPICLK             = 26,  //!< SPI Clock
    CLB_LOCAL_IN_MUX_SPISIMO_SLAVE      = 27,  //!< SPISIMO Slave Input
    CLB_LOCAL_IN_MUX_SPISTE             = 28,  //!< SPI STE
    CLB_LOCAL_IN_MUX_SCI_TX             = 29,  //!< SCI TX
    CLB_LOCAL_IN_MUX_SPISOMI_OUT        = 30,  //!< SPISOMI(OUT)
    CLB_LOCAL_IN_MUX_CLB_PSCLK          = 31,  //!< CLB prescaled clock
    CLB_LOCAL_IN_MUX_EPWM5A             = 32,  //!< EPWM5A (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM5A_OE          = 33,  //!< EPWM5A trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM5B             = 34,  //!< EPWM5B (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM5B_OE          = 35,  //!< EPWM5B trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM6A             = 36,  //!< EPWM6A (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM6A_OE          = 37,  //!< EPWM6A trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM6B             = 38,  //!< EPWM6B (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM6B_OE          = 39,  //!< EPWM6B trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM7A             = 40,  //!< EPWM7A (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM7A_OE          = 41,  //!< EPWM7A trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM7B             = 42,  //!< EPWM7B (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM7B_OE          = 43,  //!< EPWM7B trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM8A             = 44,  //!< EPWM8A (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM8A_OE          = 45,  //!< EPWM8A trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM8B             = 46,  //!< EPWM8B (CLB 1-4)
    CLB_LOCAL_IN_MUX_EPWM8B_OE          = 47,  //!< EPWM8B trip output (CLB 1-4)
    CLB_LOCAL_IN_MUX_INPUT1             = 48,  //!< CLBINPUTXBAR INPUT1
    CLB_LOCAL_IN_MUX_INPUT2             = 49,  //!< CLBINPUTXBAR INPUT2
    CLB_LOCAL_IN_MUX_INPUT3             = 50,  //!< CLBINPUTXBAR INPUT3
    CLB_LOCAL_IN_MUX_INPUT4             = 51,  //!< CLBINPUTXBAR INPUT4
    CLB_LOCAL_IN_MUX_INPUT5             = 52,  //!< CLBINPUTXBAR INPUT5
    CLB_LOCAL_IN_MUX_INPUT6             = 53,  //!< CLBINPUTXBAR INPUT6
    CLB_LOCAL_IN_MUX_INPUT7             = 54,  //!< CLBINPUTXBAR INPUT7
    CLB_LOCAL_IN_MUX_INPUT8             = 55,  //!< CLBINPUTXBAR INPUT8
    CLB_LOCAL_IN_MUX_INPUT9             = 56,  //!< CLBINPUTXBAR INPUT9
    CLB_LOCAL_IN_MUX_INPUT10            = 57,  //!< CLBINPUTXBAR INPUT10
    CLB_LOCAL_IN_MUX_INPUT11            = 58,  //!< CLBINPUTXBAR INPUT11
    CLB_LOCAL_IN_MUX_INPUT12            = 59,  //!< CLBINPUTXBAR INPUT12
    CLB_LOCAL_IN_MUX_INPUT13            = 60,  //!< CLBINPUTXBAR INPUT13
    CLB_LOCAL_IN_MUX_INPUT14            = 61,  //!< CLBINPUTXBAR INPUT14
    CLB_LOCAL_IN_MUX_INPUT15            = 62,  //!< CLBINPUTXBAR INPUT15
    CLB_LOCAL_IN_MUX_INPUT16            = 63   //!< CLBINPUTXBAR INPUT16
} CLB_LocalInputMux;

//*****************************************************************************
//
//! Values that can be passed to CLB_configGlobalInputMux() as the
//! \e globalMuxCfg parameter.
//
//*****************************************************************************
typedef enum
{
    CLB_GLOBAL_IN_MUX_EPWM1A            = 0,   //!< EPWM1A
    CLB_GLOBAL_IN_MUX_EPWM1A_OE         = 1,   //!< EPWM1A trip output
    CLB_GLOBAL_IN_MUX_EPWM1B            = 2,   //!< EPWM1B
    CLB_GLOBAL_IN_MUX_EPWM1B_OE         = 3,   //!< EPWM1B trip output
    CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO    = 4,   //!< EPWM1 TBCTR = Zero
    CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD     = 5,   //!< EPWM1 TBCTR = TBPRD
    CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR      = 6,   //!< EPWM1 CTRDIR
    CLB_GLOBAL_IN_MUX_EPWM1_TBCLK       = 7,   //!< EPWM1 TBCLK
    CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA    = 8,   //!< EPWM1 TBCTR = CMPA
    CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB    = 9,   //!< EPWM1 TBCTR = CMPB
    CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC    = 10,  //!< EPWM1 TBCTR = CMPC
    CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD    = 11,  //!< EPWM1 TBCTR = CMPD
    CLB_GLOBAL_IN_MUX_EPWM1A_AQ         = 12,  //!< EPWM1A AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM1B_AQ         = 13,  //!< EPWM1B AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM1A_DB         = 14,  //!< EPWM1A DB submodule output
    CLB_GLOBAL_IN_MUX_EPWM1B_DB         = 15,  //!< EPWM1B DB submodule output

    CLB_GLOBAL_IN_MUX_EPWM2A            = 16,  //!< EPWM2A
    CLB_GLOBAL_IN_MUX_EPWM2A_OE         = 17,  //!< EPWM2A trip output
    CLB_GLOBAL_IN_MUX_EPWM2B            = 18,  //!< EPWM2B
    CLB_GLOBAL_IN_MUX_EPWM2B_OE         = 19,  //!< EPWM2B trip output
    CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO    = 20,  //!< EPWM2 TBCTR = Zero
    CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD     = 21,  //!< EPWM2 TBCTR = TBPRD
    CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR      = 22,  //!< EPWM2 CTRDIR
    CLB_GLOBAL_IN_MUX_EPWM2_TBCLK       = 23,  //!< EPWM2 TBCLK
    CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA    = 24,  //!< EPWM2 TBCTR = CMPA
    CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB    = 25,  //!< EPWM2 TBCTR = CMPB
    CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC    = 26,  //!< EPWM2 TBCTR = CMPC
    CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD    = 27,  //!< EPWM2 TBCTR = CMPD
    CLB_GLOBAL_IN_MUX_EPWM2A_AQ         = 28,  //!< EPWM2A AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM2B_AQ         = 29,  //!< EPWM2B AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM2A_DB         = 30,  //!< EPWM2A DB submodule output
    CLB_GLOBAL_IN_MUX_EPWM2B_DB         = 31,  //!< EPWM2B DB submodule output

    CLB_GLOBAL_IN_MUX_EPWM3A            = 32,  //!< EPWM3A
    CLB_GLOBAL_IN_MUX_EPWM3A_OE         = 33,  //!< EPWM3A trip output
    CLB_GLOBAL_IN_MUX_EPWM3B            = 34,  //!< EPWM3B
    CLB_GLOBAL_IN_MUX_EPWM3B_OE         = 35,  //!< EPWM3B trip output
    CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO    = 36,  //!< EPWM3 TBCTR = Zero
    CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD     = 37,  //!< EPWM3 TBCTR = TBPRD
    CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR      = 38,  //!< EPWM3 CTRDIR
    CLB_GLOBAL_IN_MUX_EPWM3_TBCLK       = 39,  //!< EPWM3 TBCLK
    CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA    = 40,  //!< EPWM3 TBCTR = CMPA
    CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB    = 41,  //!< EPWM3 TBCTR = CMPB
    CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC    = 42,  //!< EPWM3 TBCTR = CMPC
    CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD    = 43,  //!< EPWM3 TBCTR = CMPD
    CLB_GLOBAL_IN_MUX_EPWM3A_AQ         = 44,  //!< EPWM3A AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM3B_AQ         = 45,  //!< EPWM3B AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM3A_DB         = 46,  //!< EPWM3A DB submodule output
    CLB_GLOBAL_IN_MUX_EPWM3B_DB         = 47,  //!< EPWM3B DB submodule output

    CLB_GLOBAL_IN_MUX_EPWM4A            = 48,  //!< EPWM4A
    CLB_GLOBAL_IN_MUX_EPWM4A_OE         = 49,  //!< EPWM4A trip output
    CLB_GLOBAL_IN_MUX_EPWM4B            = 50,  //!< EPWM4B
    CLB_GLOBAL_IN_MUX_EPWM4B_OE         = 51,  //!< EPWM4B trip output
    CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO    = 52,  //!< EPWM4 TBCTR = Zero
    CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD     = 53,  //!< EPWM4 TBCTR = TBPRD
    CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR      = 54,  //!< EPWM4 CTRDIR
    CLB_GLOBAL_IN_MUX_EPWM4_TBCLK       = 55,  //!< EPWM4 TBCLK
    CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA    = 56,  //!< EPWM4 TBCTR = CMPA
    CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB    = 57,  //!< EPWM4 TBCTR = CMPB
    CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC    = 58,  //!< EPWM4 TBCTR = CMPC
    CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD    = 59,  //!< EPWM4 TBCTR = CMPD
    CLB_GLOBAL_IN_MUX_EPWM4A_AQ         = 60,  //!< EPWM4A AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM4B_AQ         = 61,  //!< EPWM4B AQ submodule output
    CLB_GLOBAL_IN_MUX_EPWM4A_DB         = 62,  //!< EPWM4A DB submodule output
    CLB_GLOBAL_IN_MUX_EPWM4B_DB         = 63,  //!< EPWM4B DB submodule output

    CLB_GLOBAL_IN_MUX_CLB_AUXSIG0       = 64,  //!< CLB X-BAR AUXSIG0
    CLB_GLOBAL_IN_MUX_CLB_AUXSIG1       = 65,  //!< CLB X-BAR AUXSIG1
    CLB_GLOBAL_IN_MUX_CLB_AUXSIG2       = 66,  //!< CLB X-BAR AUXSIG2
    CLB_GLOBAL_IN_MUX_CLB_AUXSIG3       = 67,  //!< CLB X-BAR AUXSIG3
    CLB_GLOBAL_IN_MUX_CLB_AUXSIG4       = 68,  //!< CLB X-BAR AUXSIG4
    CLB_GLOBAL_IN_MUX_CLB_AUXSIG5       = 69,  //!< CLB X-BAR AUXSIG5
    CLB_GLOBAL_IN_MUX_CLB_AUXSIG6       = 70,  //!< CLB X-BAR AUXSIG6
    CLB_GLOBAL_IN_MUX_CLB_AUXSIG7       = 71,  //!< CLB X-BAR AUXSIG7

    CLB_GLOBAL_IN_MUX_CLB1_OUT16         = 72,  //!< CLB1 OUT16
    CLB_GLOBAL_IN_MUX_CLB1_OUT17         = 73,  //!< CLB1 OUT17
    CLB_GLOBAL_IN_MUX_CLB1_OUT18         = 74,  //!< CLB1 OUT18
    CLB_GLOBAL_IN_MUX_CLB1_OUT19         = 75,  //!< CLB1 OUT19
    CLB_GLOBAL_IN_MUX_CLB1_OUT20         = 76,  //!< CLB1 OUT20
    CLB_GLOBAL_IN_MUX_CLB1_OUT21         = 77,  //!< CLB1 OUT21
    CLB_GLOBAL_IN_MUX_CLB1_OUT22         = 78,  //!< CLB1 OUT22
    CLB_GLOBAL_IN_MUX_CLB1_OUT23         = 79,  //!< CLB1 OUT23

    CLB_GLOBAL_IN_MUX_CLB2_OUT16         = 80,  //!< CLB2 OUT16
    CLB_GLOBAL_IN_MUX_CLB2_OUT17         = 81,  //!< CLB2 OUT17
    CLB_GLOBAL_IN_MUX_CLB2_OUT18         = 82,  //!< CLB2 OUT18
    CLB_GLOBAL_IN_MUX_CLB2_OUT19         = 83,  //!< CLB2 OUT19
    CLB_GLOBAL_IN_MUX_CLB2_OUT20         = 84,  //!< CLB2 OUT20
    CLB_GLOBAL_IN_MUX_CLB2_OUT21         = 85,  //!< CLB2 OUT21
    CLB_GLOBAL_IN_MUX_CLB2_OUT22         = 86,  //!< CLB2 OUT22
    CLB_GLOBAL_IN_MUX_CLB2_OUT23         = 87,  //!< CLB2 OUT23

    CLB_GLOBAL_IN_MUX_CLB3_OUT16         = 88,  //!< CLB3 OUT16
    CLB_GLOBAL_IN_MUX_CLB3_OUT17         = 89,  //!< CLB3 OUT17
    CLB_GLOBAL_IN_MUX_CLB3_OUT18         = 90,  //!< CLB3 OUT18
    CLB_GLOBAL_IN_MUX_CLB3_OUT19         = 91,  //!< CLB3 OUT19
    CLB_GLOBAL_IN_MUX_CLB3_OUT20         = 92,  //!< CLB3 OUT20
    CLB_GLOBAL_IN_MUX_CLB3_OUT21         = 93,  //!< CLB3 OUT21
    CLB_GLOBAL_IN_MUX_CLB3_OUT22         = 94,  //!< CLB3 OUT22
    CLB_GLOBAL_IN_MUX_CLB3_OUT23         = 95,  //!< CLB3 OUT23

    CLB_GLOBAL_IN_MUX_CLB4_OUT16         = 96,   //!< CLB4 OUT16
    CLB_GLOBAL_IN_MUX_CLB4_OUT17         = 97,   //!< CLB4 OUT17
    CLB_GLOBAL_IN_MUX_CLB4_OUT18         = 98,   //!< CLB4 OUT18
    CLB_GLOBAL_IN_MUX_CLB4_OUT19         = 99,   //!< CLB4 OUT19
    CLB_GLOBAL_IN_MUX_CLB4_OUT20         = 100,  //!< CLB4 OUT20
    CLB_GLOBAL_IN_MUX_CLB4_OUT21         = 101,  //!< CLB4 OUT21
    CLB_GLOBAL_IN_MUX_CLB4_OUT22         = 102,  //!< CLB4 OUT22
    CLB_GLOBAL_IN_MUX_CLB4_OUT23         = 103,  //!< CLB4 OUT23

    CLB_GLOBAL_IN_MUX_ERAD_EVENT0       = 104,  //!< ERAD Event 0 (BUSCOMP1)
    CLB_GLOBAL_IN_MUX_ERAD_EVENT1       = 105,  //!< ERAD Event 1 (BUSCOMP2)
    CLB_GLOBAL_IN_MUX_ERAD_EVENT2       = 106,  //!< ERAD Event 2 (BUSCOMP3)
    CLB_GLOBAL_IN_MUX_ERAD_EVENT3       = 107,  //!< ERAD Event 3 (BUSCOMP4)
    CLB_GLOBAL_IN_MUX_ERAD_EVENT4       = 108,  //!< ERAD Event 4 (BUSCOMP5)
    CLB_GLOBAL_IN_MUX_ERAD_EVENT5       = 109,  //!< ERAD Event 5 (BUSCOMP6)
    CLB_GLOBAL_IN_MUX_ERAD_EVENT6       = 110,  //!< ERAD Event 6 (BUSCOMP7)
    CLB_GLOBAL_IN_MUX_ERAD_EVENT7       = 111,  //!< ERAD Event 7 (BUSCOMP8)

    CLB_GLOBAL_IN_MUX_FSIRXA_DATA_PACKET_RCVD  = 112,  //!< FSIRXA Data Packet Received
    CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_PACKET_RCVD = 113,  //!< FSIRXA Error Packet Received
    CLB_GLOBAL_IN_MUX_FSIRXA_PING_PACKET_RCVD  = 114,  //!< FSIRXA PING Packet Received
    CLB_GLOBAL_IN_MUX_FSIRXA_OUTPUT_FRAME_DONE = 115,  //!< FSIRXA Output Frame Done
    CLB_GLOBAL_IN_MUX_FSIRXA_PING_TAG_MATCH    = 116,  //!< FSIRXA PING TAG Match
    CLB_GLOBAL_IN_MUX_FSIRXA_DATA_TAG_MATCH    = 117,  //!< FSIRXA DATA TAG Match
    CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_TAG_MATCH   = 118,  //!< FSIRXA ERROR TAG Match
    CLB_GLOBAL_IN_MUX_FSIRXA_RX_TRIG2          = 119,  //!< FSIRXA RX Trig 2

    CLB_GLOBAL_IN_MUX_SPI1_SPICLK           = 120,  //!< SPI1 SPICLK OUT
    CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER   = 121,  //!< SPI1 SPISOMI Master IN
    CLB_GLOBAL_IN_MUX_SPI1_SPISTE           = 122,  //!< SPI1 SPISTE OUT
    CLB_GLOBAL_IN_MUX_SPI2_SPICLK           = 123,  //!< SPI2 SPICLK OUT
    CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER   = 124,  //!< SPI2 SPISOMI Master IN
    CLB_GLOBAL_IN_MUX_SPI2_SPISTE           = 125,  //!< SPI2 SPISTE OUT

    CLB_GLOBAL_IN_MUX_FSIRXA_RX_TRIG3          = 127,  //!< FSIRXA RX Trig 3
} CLB_GlobalInputMux;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//
//!
//! Checks the CLB base address.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function determines if a CLB base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Set global enable.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the CLB via global enable register.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableCLB(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x0U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Clear global enable.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function disables the CLB via global enable register.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_disableCLB(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x0U)))) &= ~0x2U;
    __edis();
}

//*****************************************************************************
//
//! Enable HLC NMI.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the CLB HLC NMI.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableNMI(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x0U)))) |= 0x8U;
    __edis();
}

//*****************************************************************************
//
//! Disable HLC NMI.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function disables the CLB HLC NMI.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_disableNMI(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x0U)))) &= ~0x8U;
    __edis();
}

//*****************************************************************************
//
//! Configure Clock Prescalar.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables and configures the CLB Clock Precalar.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configureClockPrescalar(uint32_t base, uint16_t prescl)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x18U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x18U)))) &
         ~(0xFFFF0000U)) |
        ((uint32_t)prescl << 16U);
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x18U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Configures Clock Precalar Strobe Mode.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables and configures the CLB Clock Precalar Strobe Mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configureStrobeMode(uint32_t base, uint16_t strb)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x18U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x18U)))) &
         ~((uint32_t)0x3CU)) |
        ((uint32_t)strb << 2U);
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x18U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Configures the general purpose SW release control value.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB SW Release input signal.
//! \param val is the value of the SW RLS control.
//!
//! This function configures the general purpose SW release control value.
//! The \e inID parameter can have one enumeration value from CLB_SWReleaseCtrl.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_writeSWReleaseControl(uint32_t base,
                                            CLB_SWReleaseCtrl inID, _Bool val)
{
    ;


    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x10U)))) =
            ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x10U)))) &
                ~(0x1000000U << inID)) |
                    (((uint32_t)val) << (24U + inID));
}


//*****************************************************************************
//
//! Configures the general purpose SW gate control value.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB SW Release input signal.
//! \param val is the value of the SW GATE control.
//!
//! This function configures the general purpose SW release control value.
//! The \e inID parameter can have one enumeration value from CLB_SWGateCtrl.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_writeSWGateControl(uint32_t base,
                                            CLB_SWGateCtrl inID, _Bool val)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x10U)))) =
            ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x10U)))) &
                ~(0x10000U << inID)) |
                    (((uint32_t)val) << (16U + inID));

}


//*****************************************************************************
//
//! Configures Counter TAP Selects.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param miscCtrl is the value to represent counter tap selects.
//!        Generated by tool as \b TILEx_CFG_TAP_SELL.
//!
//! This function configures the counter tap selects.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configCounterTapSelects(uint32_t base, uint32_t tapSel)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x3EU)))) = tapSel;
    __edis();
}

//*****************************************************************************
//
//! Configures AOC (Asynchronous Output Conditioning) functions.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param aocID is the specified CLB tile AOC signal.
//! \param aocCfg is the value for the AOC signal function and input
//!        signal selections. Generated by tool as \b TILEx_OUTPUT_COND_CTR_n
//!        where n is the output number.
//!
//! This function configures the input signals and equations of the aoc LUT
//! corresponding to the /e aocID parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configAOC(uint32_t base, CLB_AOCs aocID,
                                     uint32_t aocCfg)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x40U + (sizeof(uint32_t) * aocID))))) = aocCfg;
    __edis();
}

//*****************************************************************************
//
//! Enable CLB lock.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the lock bit of the lock register. The lock can only
//! be set once and can only be cleared by a device reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableLock(uint32_t base)
{
    ;

    //
    // Setting the lock bit requires key 0x5A5A to be written at the same time
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x22U)))) =
        (uint32_t)0x1U | ((uint32_t)0x5A5AU << 16U);
    __edis();
}

//*****************************************************************************
//
//! Write value to address.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param address is the address of CLB internal memory.
//! \param value is the value to write to specified address.
//!
//! This function writes the specified value to CLB internal memory.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_writeInterface(uint32_t base, uint32_t address,
                                      uint32_t value)
{
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x2U)))) = address;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x4U)))) =  value;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x0U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Select input filter type.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB tile input signal.
//! \param filterType is the selected type of filter applied to the input.
//!
//! This function configures the filter selection for the specified input.
//! The \e inID parameter can have one enumeration value from CLB_Inputs.
//! The \e filterType parameter can have one enumeration value from
//! CLB_FilterType.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_selectInputFilter(uint32_t base, CLB_Inputs inID,
                                         CLB_FilterType filterType)
{
    uint16_t shiftVal;

    ;

    //
    // Each input has a 2-bit field in this register so need to calculate
    // shift amount accordingly.
    //
    shiftVal = (uint16_t)inID << 1;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x6U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x6U)))) &
         ~(0x3U << shiftVal)) |
        ((uint16_t)filterType << shiftVal);
}

//*****************************************************************************
//
//! Enables synchronization of an input signal.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB tile input signal.
//!
//! This function enables synchronization on the specified input signal.
//! The \e inID parameter can have one enumeration value from CLB_Inputs.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableSynchronization(uint32_t base, CLB_Inputs inID)
{
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x6U + 1U)))) |=
                                                    (1U << (uint16_t)inID);
}

//*****************************************************************************
//
//! Disables synchronization of an input signal.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB tile input signal.
//!
//! This function disables synchronization on the specified input signal.
//! The \e inID parameter can have one enumeration value from CLB_Inputs.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_disableSynchronization(uint32_t base, CLB_Inputs inID)
{
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x6U + 1U)))) &=
                                                    ~(1U << (uint16_t)inID);
}

//*****************************************************************************
//
//! Configures the general purpose input mux.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB tile input signal.
//! \param gpMuxCfg is the mux selection for the general purpose input mux.
//!
//! This function configures the general purpose input mux. The \e gpMuxCfg
//! parameter can select either the use of an external input signal
//! (\b CLB_GP_IN_MUX_EXTERNAL) or the use of the corresponding CLB_GP_REG bit
//! as an input (\b CLB_GP_IN_MUX_GP_REG).
//! The \e inID parameter can have one enumeration value from CLB_Inputs.
//!
//! \sa CLB_setGPREG() to write to the CLB_GP_REG.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configGPInputMux(uint32_t base, CLB_Inputs inID,
                                        CLB_GPInputMux gpMuxCfg)
{
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x8U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x8U)))) &
         ~(0x1U << inID)) | (gpMuxCfg << inID);
}

//*****************************************************************************
//
//! Sets the CLB_GP_REG register value.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param gpRegVal is the value to be written to CLB_GP_REG.
//!
//! This function writes to the CLB_GP_REG register. When the general purpose
//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal
//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and
//! so on).
//!
//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for
//! an input signal.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_setGPREG(uint32_t base, uint32_t gpRegVal)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x10U)))) = gpRegVal;
}

//*****************************************************************************
//
//! Gets the CLB_GP_REG register value.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function writes to the CLB_GP_REG register. When the general purpose
//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal
//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and
//! so on).
//!
//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for
//! an input signal.
//!
//! \return CLB_GP_REG value.
//
//*****************************************************************************
static inline uint32_t CLB_getGPREG(uint32_t base)
{
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x10U)))));
}

//*****************************************************************************
//
//! Configures the local input mux.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB tile input signal.
//! \param localMuxCfg is the mux selection for the local input mux.
//!
//! This function configures the local input mux for the specified input
//! signal.
//!
//! The \e inID parameter can have one enumeration value from CLB_Inputs.
//! The \e localMuxCfg parameter can have one enumeration value from
//! CLB_LocalInputMux.
//!
//! \note The local input mux options' peripheral sources depend on which
//! instance of the CLB (\e base) you are using. For example, for CLB1 the
//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2.
//! See your technical reference manual for details.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configLocalInputMux(uint32_t base, CLB_Inputs inID,
                                            CLB_LocalInputMux localMuxCfg)
{
    uint16_t shiftVal;
    uint32_t miscShiftVal, inputMuxSel;

    ;

    //
    // Each local input has a 5-bit field in this register so need to calculate
    // shift amount accordingly.
    //
    shiftVal = (uint16_t)inID * 5U;

    //
    // If the local inputs are selected then only 5-bits are used in this
    // register but if miscellaneous inputs are selected then another 1-bit is
    // used along with the above 5. So we need to calculate this accordingly.
    //

    //
    // Each miscellaneous input has a 1-bit field in this register so
    // need to calculate shift amount accordingly.
    //
    miscShiftVal = (uint32_t)inID + 28U;

    //
    // Check if input < input4
    //
    if(inID < CLB_IN4)
    {
        //
        // Each miscellaneous input has an extra 1-bit to be set
        // apart from the local input bits
        //
        inputMuxSel =
       ((((uint32_t)localMuxCfg & 0x1FU) <<
        shiftVal) |
       ((((uint32_t)localMuxCfg & 0x20U) >>
        5U) << miscShiftVal));

        //
        //Update the local / misc input mux selections
        //
        (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0xAU)))) =
       ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0xAU)))) &
        ~(((uint32_t)0x1FU << shiftVal) |
         ((uint32_t)1U << miscShiftVal))) |
        inputMuxSel;
    }
    else
    {
        //
        //Adjust the previously calculated shifts for the inputs >3
        //
        shiftVal -= 4U * 5U;
        miscShiftVal -= 4U;

        //
        // Each miscellaneous input has an extra 1-bit to be set
        // apart from the local input bits
        //
        inputMuxSel =
        (((uint32_t)(localMuxCfg & 0x1FU) <<
        shiftVal) |
        ((((uint32_t)localMuxCfg & 0x20U) >>
        5U) << miscShiftVal));

        (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0xCU)))) =
       ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0xCU)))) &
        ~(((uint32_t)0x1FU << shiftVal) |
         ((uint32_t)1U << miscShiftVal))) |
        inputMuxSel;

    }
}

//*****************************************************************************
//
//! Configures the global input mux.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param inID is the specified CLB tile input signal.
//! \param globalMuxCfg is the mux selection for the global input mux.
//!
//! This function configures the global input mux for the specified input
//! signal.
//! The \e inID parameter can have one enumeration value from CLB_Inputs.
//! The \e globalMuxCfg parameter can have one enumeration value from
//! CLB_GlobalInputMux.
//!
//! \note The global input mux options' peripheral sources depend on which
//! instance of the CLB (\e base) you are using. For example, for CLB1 the
//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2.
//! See your technical reference manual for details.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configGlobalInputMux(uint32_t base, CLB_Inputs inID,
                                            CLB_GlobalInputMux globalMuxCfg)
{
    uint16_t shiftVal;

    ;

    //
    // Each input has a 5-bit field in this register so need to calculate
    // shift amount accordingly.
    //
    shiftVal = (uint16_t)inID * 7U;

    if(inID < CLB_IN4)
    {
        (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x14U)))) =
            ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x14U)))) &
             ~((uint32_t)0x7FU << shiftVal)) |
            ((uint32_t)globalMuxCfg << shiftVal);
    }
    else
    {
        shiftVal -= 4U * 7U;
        (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x16U)))) =
            ((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x16U)))) &
             ~((uint32_t)0x7FU << shiftVal)) |
            ((uint32_t)globalMuxCfg << shiftVal);
    }
}

//*****************************************************************************
//
//! Controls the output enable.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param outputMask is a mask of the outputs to be enabled.
//! \param enable is a switch to decide if the CLB outputs need to be enabled
//!  or not.
//!
//! This function is used to enable and disable CLB outputs by writing a mask
//! to CLB_OUT_EN. Each bit corresponds to a CLB output. When a bit is 1, the
//! corresponding output is enabled; when a bit is 0, the output is disabled.
//!
//! The \e outputMask parameter takes a logical OR of any of the CLB_OUTPUT_0x
//! values that correspond to the CLB OUTPUT ENABLE for the respective outputs.
//! The \e enable parameter can have one of the values from:
//! false: Disable the respective CLB outputs
//! true: Enable the respective CLB outputs
//!
//! \note Note that the 8 CLB outputs are replicated to create more output
//!  paths. See your technical reference manual for more details.
//!  If no further modifications are expected, then it is advised to set the
//!  block writes bit of the MISC_ACCESS_CTRL Register. This will prevent
//!  accidental writes.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_setOutputMask(uint32_t base, uint32_t outputMask ,
                                             _Bool enable)
{
    ;

    if(enable == 1)
     {
        (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x12U)))) |= outputMask;
     }
    else
     {
        (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x12U)))) &= ~outputMask;
     }
}

//*****************************************************************************
//
//! Reads the interrupt tag register.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! \return Returns the value in the interrupt tag register which is a 6-bit
//!         constant set by the HLC.
//
//*****************************************************************************
static inline uint16_t CLB_getInterruptTag(uint32_t base)
{
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x20U)))));
}

//*****************************************************************************
//
//! Clears the interrupt tag register.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function clears the interrupt tag register, setting it to 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_clearInterruptTag(uint32_t base)
{
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x20U)))) = 0U;
}

//*****************************************************************************
//
//! Selects LUT4 inputs.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param lut4In0 is the value for LUT4 input signal 0. Generated by tool as
//!        \b TILEx_CFG_LUT4_IN0.
//! \param lut4In1 is the value for LUT4 input signal 1. Generated by tool as
//!        \b TILEx_CFG_LUT4_IN1.
//! \param lut4In2 is the value for LUT4 input signal 2. Generated by tool as
//!        \b TILEx_CFG_LUT4_IN2.
//! \param lut4In3 is the value for LUT4 input signal 3. Generated by tool as
//!        \b TILEx_CFG_LUT4_IN3.
//!
//! This function configures the LUT4 block's input signals.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_selectLUT4Inputs(uint32_t base, uint32_t lut4In0,
                                        uint32_t lut4In1, uint32_t lut4In2,
                                        uint32_t lut4In3)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x12U)))) = lut4In0;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x14U)))) = lut4In1;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x16U)))) = lut4In2;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x18U)))) = lut4In3;
    __edis();
}

//*****************************************************************************
//
//! Configures LUT4 functions.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param lut4Fn10 is the equation value for LUT4 blocks 0 and 1. Generated by
//!        tool as \b TILEx_CFG_LUT4_FN10.
//! \param lut4Fn2 is the equation value for LUT4 block2. Generated by tool as
//!        \b TILEx_CFG_LUT4_FN2.
//!
//! This function configures the LUT4 block's equations.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configLUT4Function(uint32_t base, uint32_t lut4Fn10,
                                          uint32_t lut4Fn2)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x20U)))) = lut4Fn10;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x22U)))) = lut4Fn2;
    __edis();
}

//*****************************************************************************
//
//! Selects FSM inputs.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param external0 is the value for FSM external 0 input. Generated by tool
//!        as \b TILEx_CFG_FSM_EXT_IN0.
//! \param external1 is the value for FSM external 1 input. Generated by tool
//!        as \b TILEx_CFG_FSM_EXT_IN1.
//! \param extra0 is the value for FSM extra 0 input. Generated by tool
//!        as \b TILEx_CFG_FSM_EXTRA_IN0.
//! \param extra1 is the value for FSM extra 1 input. Generated by tool
//!        as \b TILEx_CFG_FSM_EXTRA_IN1.
//!
//! This function configures the FSM block's external inputs and extra external
//! inputs.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_selectFSMInputs(uint32_t base, uint32_t external0,
                                       uint32_t external1, uint32_t extra0,
                                       uint32_t extra1)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0xCU)))) = external0;
    (*((volatile uint32_t *)((uintptr_t)(base + 0xEU)))) = external1;
    (*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))) = extra0;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x10U)))) = extra1;
    __edis();
}

//*****************************************************************************
//
//! Configures FSM LUT function.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param fsmLutFn10 is the value for FSM 0 & FSM 1 LUT function. Generated
//!        by tool as \b TILEx_CFG_FSM_LUT_FN10.
//! \param fsmLutFn2 is the value for FSM 2 LUT function. Generated by tool as
//!        \b TILEx_CFG_FSM_LUT_FN2.
//!
//! This function configures the FSM block's LUT equations.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configFSMLUTFunction(uint32_t base, uint32_t fsmLutFn10,
                                            uint32_t fsmLutFn2)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x1CU)))) = fsmLutFn10;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x1EU)))) = fsmLutFn2;
    __edis();
}

//*****************************************************************************
//
//! Configures FSM next state.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param nextState0 is the value for FSM 0's next state. Generated by tool as
//!        \b TILEx_CFG_FSM_NEXT_STATE_0.
//! \param nextState1 is the value for FSM 1's next state. Generated by tool as
//!        \b TILEx_CFG_FSM_NEXT_STATE_1.
//! \param nextState2 is the value for FSM 2's next state. Generated by tool as
//!        \b TILEx_CFG_FSM_NEXT_STATE_2.
//!
//! This function configures the FSM's next state equation.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configFSMNextState(uint32_t base, uint32_t nextState0,
                                          uint32_t nextState1,
                                          uint32_t nextState2)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x24U)))) = nextState0;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x26U)))) = nextState1;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x28U)))) = nextState2;
    __edis();
}

//*****************************************************************************
//
//! Selects Counter inputs.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param reset is the value for counter's reset inputs. Generated by tool as
//!        \b TILEx_CFG_COUNTER_RESET.
//! \param event is the value for counter's event inputs. Generated by tool as
//!        \b TILEx_CFG_COUNTER_EVENT.
//! \param mode0 is the value for counter's mode 0 inputs. Generated by tool as
//!        \b TILEx_CFG_COUNTER_MODE_0.
//! \param mode1 is the value for counter's mode 1 inputs. Generated by tool as
//!        \b TILEx_CFG_COUNTER_MODE_1.
//!
//! This function selects the input signals to the counter block.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_selectCounterInputs(uint32_t base, uint32_t reset,
                                           uint32_t event, uint32_t mode0,
                                           uint32_t mode1)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) = reset;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x8U)))) = event;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x6U)))) = mode0;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) = mode1;
    __edis();
}

//*****************************************************************************
//
//! Configures Counter and FSM modes.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param miscCtrl is the value to represent counter and FSM modes.
//!        Generated by tool as \b TILEx_CFG_MISC_CONTROL.
//!
//! This function configures the counter mode, particularly add/shift, load
//! modes. The function also configures whether the FSM should use state inputs
//! or an extra external input.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configMiscCtrlModes(uint32_t base, uint32_t miscCtrl)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2AU)))) = miscCtrl;
    __edis();
}

//*****************************************************************************
//
//! Configures Output LUT functions.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param outID is the specified CLB tile output signal.
//! \param outputCfg is the value for the output LUT signal function and input
//!        signal selections. Generated by tool as \b TILEx_CFG_OUTLUT_n where
//!        n is the output number.
//!
//! This function configures the input signals and equations of the output LUT
//! corresponding to the /e outID parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configOutputLUT(uint32_t base, CLB_Outputs outID,
                                       uint32_t outputCfg)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2CU + (sizeof(uint32_t) * outID))))) = outputCfg;
    __edis();
}

//*****************************************************************************
//
//! Configures HLC event selection.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param eventSel is the value for HLC event selection. Generated by tool as
//!        \b TILEx_HLC_EVENT_SEL.
//!
//! This function configures the event selection for the High Level Controller.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configHLCEventSelect(uint32_t base, uint32_t eventSel)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x3CU)))) = eventSel;
    __edis();
}

//*****************************************************************************
//
//! Program HLC instruction.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param instructionNum is the index into the HLC instruction memory. For
//!        example, a value of 0 corresponds to instruction 0 of event 0,
//!        a value of 1 corresponds to instruction 1 of event 0, and so on up
//!        to a value of 31 which corresponds to instruction 7 of event 3.
//! \param instruction is the instruction to be programmed. Generated by tool
//!        as \b TILEx_HLCINSTR_n where n is the instruction number.
//!
//! This function configures the CLB internal memory corresponding to the
//! specified HLC instruction number with the given instruction.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_programHLCInstruction(uint32_t base,
                                             uint32_t instructionNum,
                                             uint32_t instruction)
{
    ;
    ;

    CLB_writeInterface(base, 0x20U + instructionNum, instruction);
}

//*****************************************************************************
//
//! Set HLC registers.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param r0Init is the value to write to HLC register R0. Generated by tool
//!        as \b TILEx_HLC_R0_INIT.
//! \param r1Init is the value to write to HLC register R1. Generated by tool
//!        as \b TILEx_HLC_R1_INIT.
//! \param r2Init is the value to write to HLC register R2. Generated by tool
//!        as \b TILEx_HLC_R2_INIT.
//! \param r3Init is the value to write to HLC register R3. Generated by tool
//!        as \b TILEx_HLC_R3_INIT.
//!
//! This function configures the CLB internal memory corresponding to the HLC
//! registers R0-R3 with the specified values.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_setHLCRegisters(uint32_t base, uint32_t r0Init,
                                       uint32_t r1Init, uint32_t r2Init,
                                       uint32_t r3Init)
{
    ;

    CLB_writeInterface(base, 0xCU, r0Init);
    CLB_writeInterface(base, 0xDU, r1Init);
    CLB_writeInterface(base, 0xEU, r2Init);
    CLB_writeInterface(base, 0xFU, r3Init);
}

//*****************************************************************************
//
//! Get HLC or counter register values.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param registerID is the internal register from which to read. Can be
//!        either an HLC register (\b CLB_REG_HLC_Rn) or a counter value
//!        (\b CLB_REG_CTR_Cn).
//!
//! \return Returns the value in the specified HLC register or counter.
//
//*****************************************************************************
static inline uint32_t CLB_getRegister(uint32_t base, CLB_Register registerID)
{
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + (uint32_t)registerID)))));
}

//*****************************************************************************
//
//! Get output status.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! \return Returns the output status of various components within the CLB tile
//!         such as a counter match or LUT output. Use the \b CLB_DBG_OUT_*
//!         masks from <tt>hw_clb.h</tt> to decode the bits.
//
//*****************************************************************************
static inline uint32_t CLB_getOutputStatus(uint32_t base)
{
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x3EU)))));
}

//*****************************************************************************
//
//! Enable CLB Pipeline Mode.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the CLB Pipeline Mode
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enablePipelineMode(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x0U)))) |= 0x10U;
    __edis();
}

//*****************************************************************************
//
//! Disable CLB Pipeline Mode.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function disables the CLB Pipeline Mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_disablePipelineMode(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0100U + 0x0U)))) &= ~0x10U;
    __edis();
}

//*****************************************************************************
//
//! Disable CLB Output Mask Updates.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function disables the CLB Output Mask updates
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_disableOutputMaskUpdates(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x50U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Enable CLB Output Mask Updates.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the CLB Output Mask updates
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableOutputMaskUpdates(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x50U)))) &= ~0x2U;
    __edis();
}

//*****************************************************************************
//
//! Enable Input Pipeline Mode.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the CLB Input Pipeline mode
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableInputPipelineMode(uint32_t base, CLB_Inputs inID)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x6U)))) |=
            (0x1000000U << (uint32_t)inID);
}

//*****************************************************************************
//
//! Disable Input Pipeline Mode.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function disables the CLB Input Pipeline mode
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_disableInputPipelineMode(uint32_t base, CLB_Inputs inID)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x0100U + 0x6U)))) &=
            ~(0x1000000U << (uint32_t)inID);
}

//*****************************************************************************
//
//! Disable SPI RX Buffer Access.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function disables the CLB SPI RX Buffer access
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_disableSPIBufferAccess(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x50U)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! Enable SPI RX Buffer Access.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the CLB SPI RX Buffer access
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableSPIBufferAccess(uint32_t base)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x50U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Configures SPI RX Buffer Load Signal event selection.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param eventSel is the value for HLC event selection. Generated by tool as
//!        \b TILEx_SPI_BUF_EVENT_SEL.
//!
//! This function configures the event selection for the SPI RX Buffer.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configSPIBufferLoadSignal(uint32_t base, uint16_t eventSel)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x51U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x51U)))) &
         ~((uint16_t)0x1FU << 0U)) |
        ((uint16_t)eventSel << 0U);
    __edis();
}

//*****************************************************************************
//
//! Configures SPI Export HLC R0 Shift value.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param shiftVal is the value for SPI export HLC R0 bit range selection.
//!
//! This function configures the SPI Export HLC R0 Shift value.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_configSPIBufferShift(uint32_t base, uint16_t shiftVal)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x51U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x51U)))) &
         ~((uint16_t)0x1F00U << 8U)) |
        ((uint16_t)shiftVal << 8U);
    __edis();
}

//*****************************************************************************
//
//! Configures Counter load and match.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param counterID is the specified counter unit.
//! \param load is the value for counter's load mode. Generated by tool as
//!        \b TILEx_COUNTER_n_LOAD_VAL where n is the counter number.
//! \param match1 is the value for counter's match 1. Generated by tool as
//!        \b TILEx_COUNTER_n_MATCH1_VAL where n is the counter number.
//! \param match2 is the value for counter's match 2. Generated by tool as
//!        \b TILEx_COUNTER_n_MATCH2_VAL where n is the counter number.
//!
//! This function configures the CLB internal memory corresponding to the
//! counter block's load and match values.
//!
//! \return None.
//
//*****************************************************************************
extern void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID,
                                       uint32_t load, uint32_t match1,
                                       uint32_t match2);

//*****************************************************************************
//
//! Clear FIFO registers.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function clears the PUSH/PULL FIFOs as well as its pointers.
//!
//! \return None.
//
//*****************************************************************************
extern void CLB_clearFIFOs(uint32_t base);

//*****************************************************************************
//
//! Configure the FIFO registers.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param pullData[] is a pointer to an array of bytes which needs to be
//! written into the FIFO. The 0th FIFO data is in the 0th index.
//!
//! This function writes to the PULL FIFO. This also clears the FIFOs and
//! its pointer using the CLB_clearFIFOs() API prior to writing to
//! the FIFO.
//!
//! \return None.
//
//*****************************************************************************
extern void CLB_writeFIFOs(uint32_t base, const uint32_t pullData[]);

//*****************************************************************************
//
//! Read FIFO registers.
//!
//! \param base is the base address of a CLB tile's logic config register.
//! \param pushData[] is a pointer to an array of bytes which needs to be
//! read from the FIFO.
//!
//! This function reads from the PUSH FIFO. The 0th FIFO data would be in
//! the 0th index.
//!
//! \return None.
//
//*****************************************************************************
extern void CLB_readFIFOs(uint32_t base , uint32_t pushData[]);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   cmpss.h
//
// TITLE:  C28x CMPSS driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup cmpss_api CMPSS
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_cmpss.h
//
// TITLE:   Definitions for the CMPSS registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the CMPSS register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPHYSCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPSTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPSTSCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPDACCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACHVALS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACHVALA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLVALS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLVALA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPDLYA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPDLYS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPLFILCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPHFILCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPLOCK register
//
//*************************************************************************************************




//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************


//*****************************************************************************
//
// Values that can be passed to CMPSS_configLowComparator() and
// CMPSS_configHighComparator() as the config parameter.
//
//*****************************************************************************
//
// Comparator negative input source
//
//! Input driven by internal DAC
//! Input driven by external pin

//
// Extra options
//
//! Comparator output is inverted
//! Asynch comparator output feeds into OR with latched digital filter output

//*****************************************************************************
//
// Values that can be passed to CMPSS_configOutputsLow() and
// CMPSS_configOutputsHigh() as the config parameter.
//
//*****************************************************************************
//
// Signal driving CTRIPOUT
//
//! Asynchronous comparator output drives CTRIPOUT
//! Synchronous comparator output drives CTRIPOUT
//! Filter output drives CTRIPOUT
//! Latched filter output drives CTRIPOUT

//
// Signal driving CTRIP
//
//! Asynchronous comparator output drives CTRIP
//! Synchronous comparator output drives CTRIP
//! Filter output drives CTRIP
//! Latched filter output drives CTRIP

//*****************************************************************************
//
// Values that can be returned by CMPSS_getStatus().
//
//*****************************************************************************
//! High digital filter output
//! Latched value of high digital filter output
//! Low digital filter output
//! Latched value of low digital filter output

//*****************************************************************************
//
// Values that can be passed to CMPSS_configDAC() the config parameter.
//
//*****************************************************************************
//
// When is DAC value loaded from shadow register
//
//! DAC value updated from SYSCLK
//! DAC value updated from PWMSYNC

//
// DAC reference voltage
//
//! VDDA is the voltage reference
//! VDAC is the voltage reference

//
// DAC value source
//
//! DAC value updated from shadow register
//! DAC value is updated from the ramp register

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks the CMPSS base address.
//!
//! \param base is the base address of the CMPSS module.
//!
//! This function determines if a CMPSS base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enables the CMPSS module.
//!
//! \param base is the base address of the CMPSS module.
//!
//! This function enables the CMPSS module passed into the \e base parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_enableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that enables the CMPSS module.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Disables the CMPSS module.
//!
//! \param base is the base address of the CMPSS module.
//!
//! This function disables the CMPSS module passed into the \e base parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_disableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the bit that enables the CMPSS module.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Sets the configuration for the high comparator.
//!
//! \param base is the base address of the CMPSS module.
//! \param config is the configuration of the high comparator.
//!
//! This function configures a comparator.  The \e config parameter is the
//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if
//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values.
//!
//! The \b CMPSS_INSRC_xxx term can take on the following values to specify
//! the high comparator negative input source:
//! - \b CMPSS_INSRC_DAC - The internal DAC.
//! - \b CMPSS_INSRC_PIN - An external pin.
//!
//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output
//! should be inverted.
//!
//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the
//! asynchronous comparator output should be fed into an OR gate with the
//! latched digital filter output before it is made available for CTRIPH or
//! CTRIPOUTH.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_configHighComparator(uint32_t base, uint16_t config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the high comparator configuration to the appropriate register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & ~(0x1U | 0x2U | 0x40U)) | config;

    __edis();
}

//*****************************************************************************
//
//! Sets the configuration for the low comparator.
//!
//! \param base is the base address of the CMPSS module.
//! \param config is the configuration of the low comparator.
//!
//! This function configures a comparator.  The \e config parameter is the
//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if
//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values.
//!
//! The \b CMPSS_INSRC_xxx term can take on the following values to specify
//! the low comparator negative input source:
//! - \b CMPSS_INSRC_DAC - The internal DAC.
//! - \b CMPSS_INSRC_PIN - An external pin.
//!
//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output
//! should be inverted.
//!
//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the
//! asynchronous comparator output should be fed into an OR gate with the
//! latched digital filter output before it is made available for CTRIPL or
//! CTRIPOUTL.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_configLowComparator(uint32_t base, uint16_t config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the low comparator configuration to the appropriate register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & ~(0x100U | 0x200U | 0x4000U)) | (config << 8U);

    __edis();
}

//*****************************************************************************
//
//! Sets the output signal configuration for the high comparator.
//!
//! \param base is the base address of the CMPSS module.
//! \param config is the configuration of the high comparator output signals.
//!
//! This function configures a comparator's output signals CTRIP and CTRIPOUT.
//! The \e config parameter is the result of a logical OR operation between the
//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values.
//!
//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify
//! which signal drives CTRIPOUTH:
//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output.
//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output.
//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter.
//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter.
//!
//! The \b CMPSS_TRIP_xxx term can take on the following values to specify
//! which signal drives CTRIPH:
//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output.
//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output.
//! - \b CMPSS_TRIP_FILTER - The output of the digital filter.
//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_configOutputsHigh(uint32_t base, uint16_t config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the high comparator output settings to the appropriate register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                      ~(0x30U |
                                        0xCU))  |
                                     config;

    __edis();
}

//*****************************************************************************
//
//! Sets the output signal configuration for the low comparator.
//!
//! \param base is the base address of the CMPSS module.
//! \param config is the configuration of the low comparator output signals.
//!
//! This function configures a comparator's output signals CTRIP and CTRIPOUT.
//! The \e config parameter is the result of a logical OR operation between the
//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values.
//!
//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify
//! which signal drives CTRIPOUTL:
//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output.
//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output.
//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter.
//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter.
//!
//! The \b CMPSS_TRIP_xxx term can take on the following values to specify
//! which signal drives CTRIPL:
//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output.
//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output.
//! - \b CMPSS_TRIP_FILTER - The output of the digital filter.
//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_configOutputsLow(uint32_t base, uint16_t config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the low comparator output settings to the appropriate register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                      ~(0x3000U |
                                        0xC00U)) |
                                     (config << 8U);

    __edis();
}

//*****************************************************************************
//
//! Gets the current comparator status.
//!
//! \param base is the base address of the comparator module.
//!
//! This function returns the current status for the comparator, specifically
//! the digital filter output and latched digital filter output.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! the following values:
//! - \b CMPSS_STS_HI_FILTOUT - High digital filter output
//! - \b CMPSS_STS_HI_LATCHFILTOUT - Latched value of high digital filter
//!   output
//! - \b CMPSS_STS_LO_FILTOUT - Low digital filter output
//! - \b CMPSS_STS_LO_LATCHFILTOUT - Latched value of low digital filter output
//
//*****************************************************************************
static inline uint16_t
CMPSS_getStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return contents of the status register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))));
}

//*****************************************************************************
//
//! Sets the configuration for the internal comparator DACs.
//!
//! \param base is the base address of the CMPSS module.
//! \param config is the configuration of the internal DAC.
//!
//! This function configures the comparator's internal DAC.  The \e config
//! parameter is the result of a logical OR operation between the
//! \b CMPSS_DACVAL_xxx, \b CMPSS_DACREF_xxx, and \b CMPSS_DACSRC_xxx.
//!
//! The \b CMPSS_DACVAL_xxx term can take on the following values to specify
//! when the DAC value is loaded from its shadow register:
//! - \b CMPSS_DACVAL_SYSCLK - Value register updated on system clock.
//! - \b CMPSS_DACVAL_PWMSYNC - Value register updated on PWM sync.
//!
//! The \b CMPSS_DACREF_xxx term can take on the following values to specify
//! which voltage supply is used as reference for the DACs:
//! - \b CMPSS_DACREF_VDDA - VDDA is the voltage reference for the DAC.
//! - \b CMPSS_DACREF_VDAC - VDAC is the voltage reference for the DAC.
//!
//! The \b CMPSS_DACSRC_xxx term can take on the following values to specify
//! the DAC value source for the high comparator's internal DAC:
//! - \b CMPSS_DACSRC_SHDW - The user-programmed DACVALS register.
//! - \b CMPSS_DACSRC_RAMP - The ramp generator RAMPSTS register
//!
//! \note The \b CMPSS_DACVAL_xxx and \b CMPSS_DACREF_xxx terms apply to
//! both the high and low comparators. \b CMPSS_DACSRC_xxx will only affect
//! the high comparator's internal DAC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_configDAC(uint32_t base, uint16_t config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the DAC configuration to the appropriate register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) =
                    ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                     ~(0x80U | 0x20U |
                       0x1U)) | config;

    __edis();
}

//*****************************************************************************
//
//! Sets the value of the internal DAC of the high comparator.
//!
//! \param base is the base address of the comparator module.
//! \param value is the value actively driven by the DAC.
//!
//! This function sets the 12-bit value driven by the internal DAC of the high
//! comparator. This function will load the value into the shadow register from
//! which the actual DAC value register will be loaded. To configure which
//! event causes this shadow load to take place, use CMPSS_configDAC().
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_setDACValueHigh(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Write the DAC value to the DAC value shadow register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = value;
}

//*****************************************************************************
//
//! Sets the value of the internal DAC of the low comparator.
//!
//! \param base is the base address of the comparator module.
//! \param value is the value actively driven by the DAC.
//!
//! This function sets the 12-bit value driven by the internal DAC of the low
//! comparator. This function will load the value into the shadow register from
//! which the actual DAC value register will be loaded. To configure which
//! event causes this shadow load to take place, use CMPSS_configDAC().
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_setDACValueLow(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Write the DAC value to the DAC value shadow register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x12U)))) = value;
}

//*****************************************************************************
//
//! Initializes the digital filter of the high comparator.
//!
//! \param base is the base address of the comparator module.
//!
//! This function initializes all the samples in the high comparator digital
//! filter to the filter input value.
//!
//! \note See CMPSS_configFilterHigh() for the proper initialization sequence
//! to avoid glitches.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_initFilterHigh(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the high comparator filter initialization bit.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) |= 0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Initializes the digital filter of the low comparator.
//!
//! \param base is the base address of the comparator module.
//!
//! This function initializes all the samples in the low comparator digital
//! filter to the filter input value.
//!
//! \note See CMPSS_configFilterLow() for the proper initialization sequence
//! to avoid glitches.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_initFilterLow(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the low comparator filter initialization bit.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) |= 0x8000U;

    __edis();
}

//*****************************************************************************
//
//! Gets the value of the internal DAC of the high comparator.
//!
//! \param base is the base address of the comparator module.
//!
//! This function gets the value of the internal DAC of the high comparator.
//! The value is read from the \e active register--not the shadow register to
//! which CMPSS_setDACValueHigh() writes.
//!
//! \return Returns the value driven by the internal DAC of the high comparator.
//
//*****************************************************************************
static inline uint16_t
CMPSS_getDACValueHigh(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the DAC value to the DAC value shadow register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))));
}

//*****************************************************************************
//
//! Gets the value of the internal DAC of the low comparator.
//!
//! \param base is the base address of the comparator module.
//!
//! This function gets the value of the internal DAC of the low comparator.
//! The value is read from the \e active register--not the shadow register to
//! which CMPSS_setDACValueLow() writes.
//!
//! \return Returns the value driven by the internal DAC of the low comparator.
//
//*****************************************************************************
static inline uint16_t
CMPSS_getDACValueLow(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the DAC value to the DAC value shadow register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x13U)))));
}

//*****************************************************************************
//
//! Causes a software reset of the high comparator digital filter output latch.
//!
//! \param base is the base address of the comparator module.
//!
//! This function causes a software reset of the high comparator digital filter
//! output latch. It will generate a single pulse of the latch reset signal.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_clearFilterLatchHigh(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that generates a reset pulse to the digital filter latch.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) |= 0x2U;

    __edis();
}

//*****************************************************************************
//
//! Causes a software reset of the low comparator digital filter output latch.
//!
//! \param base is the base address of the comparator module.
//!
//! This function causes a software reset of the low comparator digital filter
//! output latch. It will generate a single pulse of the latch reset signal.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_clearFilterLatchLow(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that generates a reset pulse to the digital filter latch.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) |= 0x200U;

    __edis();
}

//*****************************************************************************
//
//! Sets the ramp generator maximum reference value.
//!
//! \param base is the base address of the comparator module.
//! \param value the ramp maximum reference value.
//!
//! This function sets the ramp maximum reference value that will be loaded
//! into the ramp generator.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_setMaxRampValue(uint32_t base,  uint16_t value)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the maximum ramp value to the shadow register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) = value;
}

//*****************************************************************************
//
//! Gets the ramp generator maximum reference value.
//!
//! \param base is the base address of the comparator module.
//!
//! \return Returns the latched ramp maximum reference value that will be
//! loaded into the ramp generator.
//
//*****************************************************************************
static inline uint16_t
CMPSS_getMaxRampValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the maximum ramp value from the register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))));
}

//*****************************************************************************
//
//! Sets the ramp generator decrement value.
//!
//! \param base is the base address of the comparator module.
//! \param value is the ramp decrement value.
//!
//! This function sets the value that is subtracted from the ramp value on
//! every system clock cycle.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_setRampDecValue(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the ramp decrement value to the shadow register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xEU)))) = value;
}

//*****************************************************************************
//
//! Gets the ramp generator decrement value.
//!
//! \param base is the base address of the comparator module.
//!
//! \return Returns the latched ramp decrement value that is subtracted from
//! the ramp value on every system clock cycle.
//
//*****************************************************************************
static inline uint16_t
CMPSS_getRampDecValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the ramp decrement value from the register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))));
}

//*****************************************************************************
//
//! Sets the ramp generator delay value.
//!
//! \param base is the base address of the comparator module.
//! \param value is the 13-bit ramp delay value.
//!
//! This function sets the value that configures the number of system clock
//! cycles to delay the start of the ramp generator decrementer after a PWMSYNC
//! event is received. Delay value can be no greater than 8191.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_setRampDelayValue(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Write the ramp delay value to the shadow register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) = value;
}

//*****************************************************************************
//
//! Gets the ramp generator delay value.
//!
//! \param base is the base address of the comparator module.
//!
//! \return Returns the latched ramp delay value that is subtracted from
//! the ramp value on every system clock cycle.
//
//*****************************************************************************
static inline uint16_t
CMPSS_getRampDelayValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the ramp delay value from the register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))));
}

//*****************************************************************************
//
//! Sets the comparator hysteresis settings.
//!
//! \param base is the base address of the comparator module.
//! \param value is the amount of hysteresis on the comparator inputs.
//!
//! This function sets the amount of hysteresis on the comparator inputs. The
//! \e value parameter indicates the amount of hysteresis desired. Passing in 0
//! results in none, passing in 1 results in typical hysteresis, passing in 2
//! results in 2x of typical hysteresis, and so on where \e value x of typical
//! hysteresis is the amount configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_setHysteresis(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read the ramp delay value from the register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) = value;

    __edis();
}

//*****************************************************************************
//
//! Enables reset of HIGH comparator digital filter output latch on PWMSYNC
//!
//! \param base is the base address of the comparator module.
//!
//! This function enables EPWMSYNCPER reset of High comparator digital filter
//! output latch
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_enableLatchResetOnPWMSYNCHigh(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) |= 0x4U;

    __edis();
}

//*****************************************************************************
//
//! Disables reset of HIGH comparator digital filter output latch on PWMSYNC
//!
//! \param base is the base address of the comparator module.
//!
//! This function disables EPWMSYNCPER reset of High comparator digital filter
//! output latch
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_disableLatchResetOnPWMSYNCHigh(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) &= ~0x4U;

    __edis();
}

//*****************************************************************************
//
//! Enables reset of LOW comparator digital filter output latch on PWMSYNC
//!
//! \param base is the base address of the comparator module.
//!
//! This function enables EPWMSYNCPER reset of Low comparator digital filter
//! output latch
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_enableLatchResetOnPWMSYNCLow(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) |= 0x400U;

    __edis();
}

//*****************************************************************************
//
//! Disables reset of LOW comparator digital filter output latch on PWMSYNC
//!
//! \param base is the base address of the comparator module.
//!
//! This function disables EPWMSYNCPER reset of Low comparator digital filter
//! output latch
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_disableLatchResetOnPWMSYNCLow(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) &= ~0x400U;

    __edis();
}

//*****************************************************************************
//
//! Sets the ePWM module blanking signal that holds trip in reset.
//!
//! \param base is the base address of the comparator module.
//! \param pwmBlankSrc is the number of the PWMBLANK source.
//!
//! This function configures which PWMBLANK signal from the ePWM module will
//! hold trip in reset when blanking is enabled.
//!
//! The number of the PWMBLANK signal to be used to reset the ramp generator
//! should be specified by passing it into the \e pwmBlankSrc parameter. For
//! instance, passing a 2 into \e pwmBlankSrc will select PWMBLANK2.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_configBlanking(uint32_t base, uint16_t pwmBlankSrc)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Write the blank source number to the appropriate register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & ~0xF00U) |
        ((pwmBlankSrc - 1U) << 8U);

    __edis();
}

//*****************************************************************************
//
//! Enables an ePWM blanking signal to hold trip in reset.
//!
//! \param base is the base address of the comparator module.
//!
//! This function enables a selected ePWM blanking signal to hold trip in
//! reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_enableBlanking(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that enables the PWMBLANK signal.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x1000U;
    __edis();
}

//*****************************************************************************
//
//! Disables an ePWM blanking signal from holding trip in reset.
//!
//! \param base is the base address of the comparator module.
//!
//! This function disables a selected ePWM blanking signal from holding trip in
//! reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CMPSS_disableBlanking(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the bit that enables the PWMBLANK signal.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x1000U;
    __edis();
}

//*****************************************************************************
//
//! Configures the digital filter of the high comparator.
//!
//! \param base is the base address of the comparator module.
//! \param samplePrescale is the number of system clock cycles between samples.
//! \param sampleWindow is the number of FIFO samples to monitor.
//! \param threshold is the majority threshold of samples to change state.
//!
//! This function configures the operation of the digital filter of the high
//! comparator.
//!
//! The \e samplePrescale parameter specifies the number of system clock cycles
//! between samples. It is a 16-bit value so a number higher than 65535 should
//! not be passed as this parameter. The prescaler used by digital filter is 1
//! more than \e samplePrescale value. So, the input provided should be 1 less
//! than the expected prescaler.
//!
//! The \e sampleWindow parameter configures the size of the window of FIFO
//! samples taken from the input that will be monitored to determine when to
//! change the filter output. This sample window may be no larger than 32
//! samples.
//!
//! The \e threshold parameter configures the threshold value to be used by
//! the digital filter.
//!
//! The filter output resolves to the majority value of the sample window where
//! majority is defined by the value passed into the \e threshold parameter.
//! For proper operation, the value of \e threshold must be greater than
//! sampleWindow / 2.
//!
//! To ensure proper operation of the filter, the following is the recommended
//! function call sequence for initialization:
//!
//! -# Configure and enable the comparator using CMPSS_configHighComparator()
//!    and CMPSS_enableModule()
//! -# Configure the digital filter using CMPSS_configFilterHigh()
//! -# Initialize the sample values using CMPSS_initFilterHigh()
//! -# Configure the module output signals CTRIP and CTRIPOUT using
//!    CMPSS_configOutputsHigh()
//!
//! \return None.
//
//*****************************************************************************
extern void
CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale,
                       uint16_t sampleWindow, uint16_t threshold);

//*****************************************************************************
//
//! Configures the digital filter of the low comparator.
//!
//! \param base is the base address of the comparator module.
//! \param samplePrescale is the number of system clock cycles between samples.
//! \param sampleWindow is the number of FIFO samples to monitor.
//! \param threshold is the majority threshold of samples to change state.
//!
//! This function configures the operation of the digital filter of the low
//! comparator.
//!
//! The \e samplePrescale parameter specifies the number of system clock cycles
//! between samples. It is a 16-bit value so a number higher than 65535 should
//! not be passed as this parameter. The prescaler used by digital filter is 1
//! more than \e samplePrescale value. So, the input provided should be 1 less
//! than the expected prescaler.
//!
//! The \e sampleWindow parameter configures the size of the window of FIFO
//! samples taken from the input that will be monitored to determine when to
//! change the filter output. This sample window may be no larger than 32
//! samples.
//!
//! The \e threshold parameter configures the threshold value to be used by
//! the digital filter.
//!
//! The filter output resolves to the majority value of the sample window where
//! majority is defined by the value passed into the \e threshold parameter.
//! For proper operation, the value of \e threshold must be greater than
//! sampleWindow / 2.
//!
//! To ensure proper operation of the filter, the following is the recommended
//! function call sequence for initialization:
//!
//! -# Configure and enable the comparator using CMPSS_configLowComparator()
//!    and CMPSS_enableModule()
//! -# Configure the digital filter using CMPSS_configFilterLow()
//! -# Initialize the sample values using CMPSS_initFilterLow()
//! -# Configure the module output signals CTRIP and CTRIPOUT using
//!    CMPSS_configOutputsLow()
//!
//! \return None.
//
//*****************************************************************************
extern void
CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale,
                      uint16_t sampleWindow, uint16_t threshold);

//*****************************************************************************
//
//! Configures whether or not the digital filter latches are reset by PWMSYNC
//!
//! \param base is the base address of the comparator module.
//! \param highEnable indicates filter latch settings in the high comparator.
//! \param lowEnable indicates filter latch settings in the low comparator.
//!
//! This function configures whether or not the digital filter latches in both
//! the high and low comparators should be reset by PWMSYNC. If the
//! \e highEnable parameter is \b true, the PWMSYNC will be allowed to reset
//! the high comparator's digital filter latch. If it is false, the ability of
//! the PWMSYNC to reset the latch will be disabled. The \e lowEnable parameter
//! has the same effect on the low comparator's digital filter latch.
//!
//! \return None.
//
//*****************************************************************************
extern void
CMPSS_configLatchOnPWMSYNC(uint32_t base, _Bool highEnable, _Bool lowEnable);

//*****************************************************************************
//
//! Configures the comparator subsystem's ramp generator.
//!
//! \param base is the base address of the comparator module.
//! \param maxRampVal is the ramp maximum reference value.
//! \param decrementVal value is the ramp decrement value.
//! \param delayVal is the ramp delay value.
//! \param pwmSyncSrc is the number of the PWMSYNC source.
//! \param useRampValShdw indicates if the max ramp shadow should be used.
//!
//! This function configures many of the main settings of the comparator
//! subsystem's ramp generator. The \e maxRampVal parameter should be passed
//! the ramp maximum reference value that will be loaded into the ramp
//! generator. The \e decrementVal parameter should be passed the decrement
//! value that will be subtracted from the ramp generator on each system clock
//! cycle. The \e delayVal parameter should be passed the 13-bit number of
//! system clock cycles the ramp generator should delay before beginning to
//! decrement the ramp generator after a PWMSYNC signal is received.
//!
//! These three values may be be set individually using the
//! CMPSS_setMaxRampValue(), CMPSS_setRampDecValue(), and
//! CMPSS_setRampDelayValue() APIs.
//!
//! The number of the PWMSYNC signal to be used to reset the ramp generator
//! should be specified by passing it into the \e pwmSyncSrc parameter. For
//! instance, passing a 2 into \e pwmSyncSrc will select PWMSYNC2.
//!
//! To indicate whether the ramp generator should reset with the value from the
//! ramp max reference value shadow register or with the latched ramp max
//! reference value, use the \e useRampValShdw parameter. Passing it \b true
//! will result in the latched value being bypassed. The ramp generator will be
//! loaded right from the shadow register. A value of \b false will load the
//! ramp generator from the latched value.
//!
//! \return None.
//
//*****************************************************************************
extern void
CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal,
                 uint16_t delayVal, uint16_t pwmSyncSrc, _Bool useRampValShdw);


//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//#############################################################################
//
// FILE:   cputimer.h
//
// TITLE:   C28x CPU timer Driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************


//*****************************************************************************
//
//! \addtogroup cputimer_api CPUTimer
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_cputimer.h
//
// TITLE:   Definitions for the CPUTIMER registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the CPUTIMER register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the TIM register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PRD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TPR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TPRH register
//
//*************************************************************************************************




//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to CPUTimer_setEmulationMode() as the
//! \e mode parameter.
//
//****************************************************************************
typedef enum
{
  //! Denotes that the timer will stop after the next decrement
  CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000,
  //! Denotes that the timer will stop when it reaches zero
  CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400,
  //! Denotes that the timer will run free
  CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800
}CPUTimer_EmulationMode;

//*****************************************************************************
//
//! The following are values that can be passed to
//! CPUTimer_selectClockSource() as the \e source parameter.
//
//*****************************************************************************
typedef enum
{
    //! System Clock Source
    CPUTIMER_CLOCK_SOURCE_SYS     = 0x0,
    //! Internal Oscillator 1 Clock Source
    CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1,
    //! Internal Oscillator 2 Clock Source
    CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2,
    //! External Clock Source
    CPUTIMER_CLOCK_SOURCE_XTAL    = 0x3,
} CPUTimer_ClockSource;

//*****************************************************************************
//
//! The following are values that can be passed to
//! CPUTimer_selectClockSource() as the \e prescaler parameter.
//
//*****************************************************************************
typedef enum
{
    CPUTIMER_CLOCK_PRESCALER_1  = 0,      //!< Prescaler value of / 1
    CPUTIMER_CLOCK_PRESCALER_2  = 1,      //!< Prescaler value of / 2
    CPUTIMER_CLOCK_PRESCALER_4  = 2,      //!< Prescaler value of / 4
    CPUTIMER_CLOCK_PRESCALER_8  = 3,      //!< Prescaler value of / 8
    CPUTIMER_CLOCK_PRESCALER_16 = 4       //!< Prescaler value of / 16
} CPUTimer_Prescaler;

//*****************************************************************************
//
//! \internal
//! Checks CPU timer base address.
//!
//! \param base specifies the Timer module base address.
//!
//! This function determines if a CPU timer module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Clears CPU timer overflow flag.
//!
//! \param base is the base address of the timer module.
//!
//! This function clears the CPU timer overflow flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_clearOverflowFlag(uint32_t base)
{
    ;

    //
    // Set TIF bit of TCR register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x8000U;
}

//*****************************************************************************
//
//! Disables CPU timer interrupt.
//!
//! \param base is the base address of the timer module.
//!
//! This function disables the CPU timer interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_disableInterrupt(uint32_t base)
{
    ;

    //
    // Clear TIE bit of TCR register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x4000U;
}

//*****************************************************************************
//
//! Enables CPU timer interrupt.
//!
//! \param base is the base address of the timer module.
//!
//! This function enables the CPU timer interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_enableInterrupt(uint32_t base)
{
    uint16_t tcrValue = 0;
    ;

    //
    // Set TIE bit of TCR register
    //
    tcrValue = (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & (~0x8000U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = tcrValue | 0x4000U;
}

//*****************************************************************************
//
//! Reloads CPU timer counter.
//!
//! \param base is the base address of the timer module.
//!
//! This function reloads the CPU timer counter with the values contained in
//! the CPU timer period register.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_reloadTimerCounter(uint32_t base)
{
    uint16_t tcrValue = 0;
    ;

    //
    // Set TRB bit of register TCR
    //
    tcrValue = (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & (~0x8000U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = tcrValue | 0x20U;
}

//*****************************************************************************
//
//! Stops CPU timer.
//!
//! \param base is the base address of the timer module.
//!
//! This function stops the CPU timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_stopTimer(uint32_t base)
{
    uint16_t tcrValue = 0;
    ;

    //
    // Set TSS bit of register TCR
    //
    tcrValue = (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & (~0x8000U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = tcrValue | 0x10U;
}

//*****************************************************************************
//
//! Starts(restarts) CPU timer.
//!
//! \param base is the base address of the timer module.
//!
//! This function starts (restarts) the CPU timer.
//!
//! \b Note: This function doesn't reset the timer counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_resumeTimer(uint32_t base)
{
    ;

    //
    // Clear TSS bit of register TCR
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x10U;
}

//*****************************************************************************
//
//! Starts(restarts) CPU timer.
//!
//! \param base is the base address of the timer module.
//!
//! This function starts (restarts) the CPU timer.
//!
//! \b Note: This function reloads the timer counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_startTimer(uint32_t base)
{
    uint16_t tcrValue = 0;
    ;

    //
    // Reload the timer counter
    //
    tcrValue = (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & (~0x8000U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = tcrValue | 0x20U;

    //
    // Clear TSS bit of register TCR
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x10U;
}

//*****************************************************************************
//
//! Sets CPU timer period.
//!
//! \param base is the base address of the timer module.
//! \param periodCount is the CPU timer period count.
//!
//! This function sets the CPU timer period count.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount)
{
    ;

    //
    // Load the MSB period Count
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) = periodCount;
}

//*****************************************************************************
//
//! Returns the current CPU timer counter value.
//!
//! \param base is the base address of the timer module.
//!
//! This function returns the current CPU timer counter value.
//!
//! \return Returns the current CPU timer count value.
//
//*****************************************************************************
static inline uint32_t CPUTimer_getTimerCount(uint32_t base)
{
    ;

    //
    // Get the TIMH:TIM registers value
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))));
}

//*****************************************************************************
//
//! Set CPU timer pre-scaler value.
//!
//! \param base is the base address of the timer module.
//! \param prescaler is the CPU timer pre-scaler value.
//!
//! This function sets the pre-scaler value for the CPU timer. For every value
//! of (prescaler + 1), the CPU timer counter decrements by 1.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler)
{
    ;

    //
    // Writes to TPR.TDDR and TPRH.TDDRH bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) = prescaler >> 8U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = (prescaler & 0xFFU) ;
}

//*****************************************************************************
//
//! Return the CPU timer overflow status.
//!
//! \param base is the base address of the timer module.
//!
//! This function returns the CPU timer overflow status.
//!
//! \return Returns true if the CPU timer has overflowed, false if not.
//
//*****************************************************************************
static inline _Bool CPUTimer_getTimerOverflowStatus(uint32_t base)
{
    ;

    //
    // Check if TIF bits of register TCR are set
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & 0x8000U) ==
            0x8000U) ? 1 : 0);
}

//*****************************************************************************
//
//! Select CPU Timer 2 Clock Source and Prescaler
//!
//! \param base is the base address of the timer module.
//! \param source is the clock source to use for CPU Timer 2
//! \param prescaler is the value that configures the selected clock source
//! relative to the system clock
//!
//! This function selects the specified clock source and prescaler value
//! for the CPU timer (CPU timer 2 only).
//!
//! The \e source parameter can be any one of the following:
//! - \b CPUTIMER_CLOCK_SOURCE_SYS     - System Clock
//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock
//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock
//! - \b CPUTIMER_CLOCK_SOURCE_XTAL    - External Clock
//!
//! The \e prescaler parameter can be any one of the following:
//! - \b CPUTIMER_CLOCK_PRESCALER_1  - Prescaler value of / 1
//! - \b CPUTIMER_CLOCK_PRESCALER_2  - Prescaler value of / 2
//! - \b CPUTIMER_CLOCK_PRESCALER_4  - Prescaler value of / 4
//! - \b CPUTIMER_CLOCK_PRESCALER_8  - Prescaler value of / 8
//! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_selectClockSource(uint32_t base,
                                              CPUTimer_ClockSource source,
                                              CPUTimer_Prescaler prescaler)
{
    ;

    //
    // Set source and prescaler for CPU Timer 2
    //
    if(base == 0x00000C10U)
    {
        __eallow();

        //
        // Set Clock Source
        //
        (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7CU)))) &=
            ~0x7U;

        (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7CU)))) |= (uint16_t)source;

        //
        // Set Clock Prescaler
        //
        (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7CU)))) &=
            ~0x38U;

        (*((volatile uint16_t *)((uintptr_t)(0x0005D300U + 0x7CU)))) |= ((uint16_t)prescaler <<
                3U);

        __edis();
    }
}

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets Emulation mode for CPU timer.
//!
//! \param base is the base address of the timer module.
//! \param mode is the emulation mode of the timer.
//!
//! This function sets the behaviour of CPU timer during emulation. Valid
//! values mode are: CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT,
//! CPUTIMER_EMULATIONMODE_STOPATZERO and CPUTIMER_EMULATIONMODE_RUNFREE.
//!
//! \return None.
//
//*****************************************************************************
extern void CPUTimer_setEmulationMode(uint32_t base,
                                      CPUTimer_EmulationMode mode);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************


//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   dac.h
//
// TITLE:  C28x DAC driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup dac_api DAC
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_dac.h
//
// TITLE:   Definitions for the DAC registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the DAC register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the DACREV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACVALA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACVALS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACOUTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACTRIM register
//
//*************************************************************************************************




//
// A 8-bit register mask
//

//
// Lock Key
//

//*****************************************************************************
//
// The following are defines for the reg parameter of the
// DAC_lockRegister() and DAC_isRegisterLocked() functions.
//
//*****************************************************************************


//*****************************************************************************
//
//! Values that can be passed to DAC_setReferenceVoltage() as the \e source
//! parameter.
//
//*****************************************************************************
typedef enum
{
    DAC_REF_VDAC        = 0,  //!< VDAC reference voltage
    DAC_REF_ADC_VREFHI  = 1   //!< ADC VREFHI reference voltage
}DAC_ReferenceVoltage;

//*****************************************************************************
//
//! Values that can be passed to DAC_setGainMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    DAC_GAIN_ONE = 0,     //!< Gain set to 1
    DAC_GAIN_TWO = 2      //!< Gain set to 2
}DAC_GainMode;

//*****************************************************************************
//
//! Values that can be passed to DAC_setLoadMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    DAC_LOAD_SYSCLK  = 0,     //!< Load on next SYSCLK
    DAC_LOAD_PWMSYNC = 4      //!< Load on next PWMSYNC specified by SYNCSEL
}DAC_LoadMode;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks DAC base address.
//!
//! \param base specifies the DAC module base address.
//!
//! This function determines if an DAC module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Get the DAC Revision value
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC revision value.
//!
//! \return Returns the DAC revision value.
//
//*****************************************************************************
static inline uint16_t
DAC_getRevision(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the revision value.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & 0xFFU);
}

//*****************************************************************************
//
//! Sets the DAC Reference Voltage
//!
//! \param base is the DAC module base address
//! \param source is the selected reference voltage
//!
//! This function sets the DAC reference voltage.
//!
//! The \e source parameter can have one of two values:
//! - \b DAC_REF_VDAC       - The VDAC reference voltage
//! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the reference  voltage
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &
                                ~0x1U) | (uint16_t)source;

    __edis();
}

//*****************************************************************************
//
//! Sets the DAC Gain Mode
//!
//! \param base is the DAC module base address
//! \param mode is the selected gain mode
//!
//! This function sets the DAC gain mode for the buffered output.
//!
//! The \e mode parameter can have one of two values:
//! - \b DAC_GAIN_ONE  - Gain is set to 1
//! - \b DAC_GAIN_TWO  - Gain is set to 2
//!
//! \note This value is only used when \e DAC_REF_ADC_VREFHI is set using
//! DAC_setReferenceVoltage() and internal ADC reference mode is selected.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setGainMode(uint32_t base, DAC_GainMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the gain mode
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &
                                ~0x2U) | (uint16_t)mode;

    __edis();
}

//*****************************************************************************
//
//! Sets the DAC Load Mode
//!
//! \param base is the DAC module base address
//! \param mode is the selected load mode
//!
//! This function sets the DAC load mode.
//!
//! The \e mode parameter can have one of two values:
//! - \b DAC_LOAD_SYSCLK   - Load on next SYSCLK
//! - \b DAC_LOAD_PWMSYNC  - Load on next PWMSYNC specified by SYNCSEL
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setLoadMode(uint32_t base, DAC_LoadMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the load mode
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &
                                ~0x4U) | (uint16_t)mode;

    __edis();
}

//*****************************************************************************
//
//! Sets the DAC PWMSYNC Signal
//!
//! \param base is the DAC module base address
//! \param signal is the selected PWM signal
//!
//! This function sets the DAC PWMSYNC signal.
//!
//! The \e signal parameter must be set to a number that represents the PWM
//! signal that will be set. For instance, passing 2 into \e signal will
//! select PWM sync signal 2.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setPWMSyncSignal(uint32_t base, uint16_t signal)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set the PWM sync signal
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &
                                ~0xF0U) |
                               ((uint16_t)(signal - 1U) << 4U);

    __edis();
}

//*****************************************************************************
//
//! Get the DAC Active Output Value
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC active output value.
//!
//! \return Returns the DAC active output value.
//
//*****************************************************************************
static inline uint16_t
DAC_getActiveValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the active value
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) & 0xFFFU);
}

//*****************************************************************************
//
//! Set the DAC Shadow Output Value
//!
//! \param base is the DAC module base address
//! \param value is the 12-bit code to be loaded into the active value register
//!
//! This function sets the DAC shadow output value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setShadowValue(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set the shadow value
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) &
                                 ~0xFFFU) |
                                (uint16_t)(value & 0xFFFU);
}

//*****************************************************************************
//
//! Get the DAC Shadow Output Value
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC shadow output value.
//!
//! \return Returns the DAC shadow output value.
//
//*****************************************************************************
static inline uint16_t
DAC_getShadowValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the shadow value
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) & 0xFFFU);
}

//*****************************************************************************
//
//! Enable the DAC Output
//!
//! \param base is the DAC module base address
//!
//! This function enables the DAC output.
//!
//! \note A delay is required after enabling the DAC. Further details
//! regarding the exact delay time length can be found in the device datasheet.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_enableOutput(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the output
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Disable the DAC Output
//!
//! \param base is the DAC module base address
//!
//! This function disables the DAC output.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_disableOutput(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the output
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x1U;

    __edis();
}

//*****************************************************************************
//
//! Set DAC Offset Trim
//!
//! \param base is the DAC module base address
//! \param offset is the specified value for the offset trim
//!
//! This function sets the DAC offset trim. The \e offset value should be a
//! signed number in the range of -128 to 127.
//!
//! \note The offset should not be modified unless specifically indicated by
//! TI Errata or other documentation. Modifying the offset value could cause
//! this module to operate outside of the datasheet specifications.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setOffsetTrim(uint32_t base, int16_t offset)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set the offset trim value
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) &
                                 ~0xFFU) | (int16_t)offset;

    __edis();
}

//*****************************************************************************
//
//! Get DAC Offset Trim
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC offset trim value.
//!
//! \return None.
//
//*****************************************************************************
static inline int16_t
DAC_getOffsetTrim(uint32_t base)
{
    uint16_t value;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the sign-extended offset trim value
    //
    value = ((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) & 0xFFU);
    value = ((value & (uint16_t)(0xFFU)) ^ (uint16_t)0x80) -
            (uint16_t)0x80;

    return((int16_t)value);
}

//*****************************************************************************
//
//! Lock write-access to DAC Register
//!
//! \param base is the DAC module base address
//! \param reg is the selected DAC registers
//!
//! This function locks the write-access to the specified DAC register. Only a
//! system reset can unlock the register once locked.
//!
//! The \e reg parameter can be an ORed combination of any of the following
//! values:
//! - \b DAC_LOCK_CONTROL  - Lock the DAC control register
//! - \b DAC_LOCK_SHADOW   - Lock the DAC shadow value register
//! - \b DAC_LOCK_OUTPUT   - Lock the DAC output enable/disable register
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_lockRegister(uint32_t base, uint16_t reg)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Lock the specified registers
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) |= ((0xA000U) | reg);

    __edis();
}

//*****************************************************************************
//
//! Check if DAC Register is locked
//!
//! \param base is the DAC module base address
//! \param reg is the selected DAC register locks to check
//!
//! This function checks if write-access has been locked on the specified DAC
//! register.
//!
//! The \e reg parameter can be an ORed combination of any of the following
//! values:
//! - \b DAC_LOCK_CONTROL  - Lock the DAC control register
//! - \b DAC_LOCK_SHADOW   - Lock the DAC shadow value register
//! - \b DAC_LOCK_OUTPUT   - Lock the DAC output enable/disable register
//!
//! \return Returns \b true if any of the registers specified are locked, and
//! \b false if all specified registers aren't locked.
//
//*****************************************************************************
static inline _Bool
DAC_isRegisterLocked(uint32_t base, uint16_t reg)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Return the lock status on the specified registers
    //
    return((_Bool)(((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) & reg) != 0U));
}

//*****************************************************************************
//
//! Tune DAC Offset Trim
//!
//! \param base is the DAC module base address
//! \param referenceVoltage is the reference voltage the DAC
//! module is operating at.
//!
//! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage
//! value should be a floating point number in the range specified in the
//! device data manual.
//!
//! \note Use this function to adjust the DAC offset trim if operating
//! at a reference voltage other than 2.5v. Since this function modifies
//! the DAC offset trim register, it should only be called once after
//! Device_cal. If it is called multiple times after Device_cal, the offset
//! value scaled would be the wrong value.
//!
//! \return None.
//
//*****************************************************************************
extern void
DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   dcc.h
//
// TITLE:  C28x DCC driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup dcc_api DCC
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_dcc.h
//
// TITLE:   Definitions for the DCC registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the DCC register offsets
//
//*************************************************************************************************
                                   // 0.


//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCGCTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCCNTSEED0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCVALIDSEED0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCCNTSEED1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCSTATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCCNT0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCVALID0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCCNT1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCCLKSRC1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCCLKSRC0 register
//
//*************************************************************************************************




//
// Minimum and maximum values of valid seed value
//

//
// Minimum and maximum values of counter0/1 seed value
//

//
// The reset value required to start or enable specific DCC operations
//

//
// The reset value required to stop or disable specific DCC operations
//

//
// A 16-bit register mask
//

//
// A 7-bit register mask
//

//
// A mask for the DCC counter seed registers
//

//
// A mask for the DCC counter seed value
//

//*****************************************************************************
//
//! The following are defines for the mode parameter of the
//! DCC_enableSingleShotMode() function.
//
//*****************************************************************************
typedef enum
{
    //! Use to stop counting when counter0 and valid0 both reach zero
    DCC_MODE_COUNTER_ZERO = 0xA00U,

    //! Use to stop counting when counter1 reaches zero
    DCC_MODE_COUNTER_ONE  = 0xB00U
} DCC_SingleShotMode;


//*****************************************************************************
//
//! The following are defines for the source parameter of the
//! DCC_setCounter1ClkSource() function.
//
//*****************************************************************************
typedef enum
{
    DCC_COUNT1SRC_PLL             = 0x0U, //!< PLLRAWCLK Clock Out Source
    DCC_COUNT1SRC_INTOSC1         = 0x2U, //!< Internal Oscillator1 Clock Source
    DCC_COUNT1SRC_INTOSC2         = 0x3U, //!< Internal Oscillator2 Clock Source
    DCC_COUNT1SRC_SYSCLK          = 0x6U, //!< SYSCLK (System Clock) Source
    DCC_COUNT1SRC_AUXCLKIN        = 0xAU, //!< AUXCLKIN (Auxilary Clock) input Source
    DCC_COUNT1SRC_EPWM            = 0xBU, //!< EPWM Clock Source
    DCC_COUNT1SRC_ADCCLK          = 0xDU, //!< ADC Clock Source
    DCC_COUNT1SRC_WDCLK           = 0xEU, //!< Watch Dog Clock Source
    DCC_COUNT1SRC_CANX            = 0xFU, //!< CANxBIT Clock Source
    DCC_COUNT1SRC_SYSAPLL_CLK_AUX = 0x16U, //!< System APLL Aux Clk
} DCC_Count1ClockSource;

//*****************************************************************************
//
//! The following are defines for the source parameter of the
//! DCC_setCounter0ClkSource() function.
//
//*****************************************************************************
typedef enum
{
    DCC_COUNT0SRC_XTAL       = 0x0U,    //!< XTAL Clock Source
    DCC_COUNT0SRC_INTOSC1    = 0x1U,    //!< Internal Oscillator1 Clock Source
    DCC_COUNT0SRC_INTOSC2    = 0x2U,    //!< Internal Oscillator2 Clock Source
    DCC_COUNT0SRC_SYSCLK     = 0x5U,    //!< System Clock Source
    DCC_COUNT0SRC_AUXCLK     = 0x8U,    //!< AUX Clock Source
} DCC_Count0ClockSource;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks DCC base address.
//!
//! \param base specifies the DCC module base address.
//!
//! This function determines if an DCC module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enables the DCC module.
//!
//! \param base is the DCC module base address
//!
//! This function starts the DCC counter operation.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_enableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set DCC enable bit field.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                  ~(0xFU)) | (0xAU);

    __edis();
}

//*****************************************************************************
//
//! Disable the DCC module.
//!
//! \param base is the DCC module base address
//!
//! This function stops the DCC counter operation.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_disableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Reset DCC enable bit field.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                  ~(0xFU)) | (0x5U);

    __edis();
}

//*****************************************************************************
//
//! Enable DCC Error Signal
//!
//! \param base is the DCC module base address
//!
//! This function enables the error signal interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_enableErrorSignal(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the error signal
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                  ~(0xF0U)) |
                                  ((0xAU) << 4U);

    __edis();
}

//*****************************************************************************
//
//! Enable DCC Done Signal
//!
//! \param base is the DCC module base address
//!
//! This function enables the done signal interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_enableDoneSignal(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the done interrupt signal
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                  ~(0xF000U)) |
                                  ((0xAU) << 12U);

    __edis();
}

//*****************************************************************************
//
//! Disable DCC Error Signal
//!
//! \param base is the DCC module base address
//!
//! This function disables the error signal interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_disableErrorSignal(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the error signal
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                  ~(0xF0U)) |
                                 ((0x5U) << 4U);

    __edis();
}

//*****************************************************************************
//
//! Disable DCC Done Signal
//!
//! \param base is the DCC module base address
//!
//! This function disables the done signal interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_disableDoneSignal(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the done interrupt signal
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                  ~(0xF000U)) |
                                 ((0x5U) << 12U);

    __edis();
}

//*****************************************************************************
//
//! Enable DCC Single-Shot Mode
//!
//! \param base is the DCC module base address
//! \param mode is the selected Single-Shot operation mode
//!
//! This function enables the single-shot mode and sets the operation mode.
//!
//! The \e mode parameter can have one of two values:
//! - \b DCC_MODE_COUNTER_ZERO - Stops counting when counter0 and valid0 both
//!   reach zero
//! - \b DCC_MODE_COUNTER_ONE  - Stops counting when counter1 reaches zero
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_enableSingleShotMode(uint32_t base, DCC_SingleShotMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set Single-Shot mode value to the appropriate register
    //
    if(mode == DCC_MODE_COUNTER_ZERO)
    {
        __eallow();

        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                      ~(0xF00U)) |
                                     (uint16_t)DCC_MODE_COUNTER_ZERO;

        __edis();
    }
    else
    {
        __eallow();

        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                      ~(0xF00U)) |
                                     (uint16_t)DCC_MODE_COUNTER_ONE;

        __edis();
    }
}

//*****************************************************************************
//
//! Disable DCC Single-Shot Mode
//!
//! \param base is the DCC module base address
//!
//! This function disables the DCC Single-Shot operation mode
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_disableSingleShotMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Reset Single-Shot enable bit field.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                  ~(0xF00U)) |
                                 ((0x5U) << 8U);

    __edis();
}

//*****************************************************************************
//
//! Get Error Flag Status
//!
//! \param base is the DCC module base address
//!
//! This function gets the error flag status.
//!
//! \return Returns \b true if an error has occurred, \b false if no errors
//! have occurred.
//
//*****************************************************************************
static inline _Bool
DCC_getErrorStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the error flag
    //
    return((_Bool)(((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) & 0x1U) ==
                  0x1U));
}

//*****************************************************************************
//
//! Get Single-Shot Done Flag Status
//!
//! \param base is the DCC module base address
//!
//! This function gets the single-shot done flag status.
//!
//! \return Returns \b true if single-shot mode has completed, \b false if
//! single-shot mode has not completed.
//
//*****************************************************************************
static inline _Bool
DCC_getSingleShotStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the done flag
    //
    return((_Bool)(((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) & 0x2U) ==
                  0x2U));
}

//*****************************************************************************
//
//! Clear Error Status Flag
//!
//! \param base is the DCC module base address
//!
//! This function clears the DCC error status flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_clearErrorFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear error status flag
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= 0x1U;

    __edis();
}

//*****************************************************************************
//
//! Clear Single-Shot Done Status Flag
//!
//! \param base is the DCC module base address
//!
//! This function clears the DCC single-shot done status flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_clearDoneFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear done status flag
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= 0x2U;

    __edis();
}

//*****************************************************************************
//
//! Get Current Value of Counter 0
//!
//! \param base is the DCC module base address
//!
//! This function gets current value of counter 0.
//!
//! \note Reads of the counter value may not be exact since the read operation
//! is synchronized to the vbus clock.
//!
//! \return Returns the current value of counter 0.
//
//*****************************************************************************
static inline uint32_t
DCC_getCounter0Value(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the current counter 0 value
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x18U)))));
}

//*****************************************************************************
//
//! Get Current Value of the Valid Duration Counter for Counter 0
//!
//! \param base is the DCC module base address
//!
//! This function gets current value of the valid duration counter for
//! counter 0.
//!
//! \note Reads of the counter value may not be exact since the read operation
//! is synchronized to the vbus clock.
//!
//! \return Returns the current value of the valid duration counter.
//
//*****************************************************************************
static inline uint16_t
DCC_getValidCounter0Value(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the current valid duration counter value
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))));
}

//*****************************************************************************
//
//! Get Current Value of Counter 1
//!
//! \param base is the DCC module base address
//!
//! This function gets current value of counter 1.
//!
//! \note Reads of the counter value may not be exact since the read operation
//! is synchronized to the vbus clock.
//!
//! \return Returns the current value of counter 1.
//
//*****************************************************************************
static inline uint32_t
DCC_getCounter1Value(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the current counter 1 value
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x20U)))));
}

//*****************************************************************************
//
//! Set Counter 1 Clock Source
//!
//! \param base is the DCC module base address
//! \param source is the selected clock source for counter 1
//!
//! This function sets the counter 1 clock source.
//!
//! The \e source parameter can have one of following values:
//! - \b DCC_COUNT1SRC_PLL             - PLL021SSP Clock Out Source
//! - \b DCC_COUNT1SRC_INTOSC1         - Internal Oscillator1 Clock Source
//! - \b DCC_COUNT1SRC_INTOSC2         - Internal Oscillator2 Clock Source
//! - \b DCC_COUNT1SRC_SYSCLK          - System Clock Source
//! - \b DCC_COUNT1SRC_AUXCLKIN        - AUX Clock input Source
//! - \b DCC_COUNT1SRC_EPWM            - EPWM Clock Source
//! - \b DCC_COUNT1SRC_ADCCLK          - ADC Clock Source
//! - \b DCC_COUNT1SRC_WDCLK           - Watch Dog Clock Source
//! - \b DCC_COUNT1SRC_CANX            - CANxBIT Clock Source
//! - \b DCC_COUNT1SRC_SYSAPLL_CLK_AUX - System APLL Aux Clk
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_setCounter1ClkSource(uint32_t base, DCC_Count1ClockSource source)
{
    //
    // Check the arguments.
    //
    ;

    //
    //  Set the specified clock source
    //
    __eallow();

    //
    //  DCC Clk source is of 5bits DCCCLKSRC1[4:0]
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x24U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x24U)))) &
                                   ((0x7FU) << 5U)) |
                                   (((0xAU) << 12U) |
                                   (uint16_t)source);

    __edis();
}

//*****************************************************************************
//
//! Set Counter 0 Clock Source
//!
//! \param base is the DCC module base address
//! \param source is the selected clock source for counter 0
//!
//! This function sets the counter 0 clock source.
//!
//! The \e source parameter can have one of following values:
//! - \b DCC_COUNT0SRC_XTAL         - Accurate Clock Source
//! - \b DCC_COUNT0SRC_INTOSC1      - Internal Oscillator1 Clock Source
//! - \b DCC_COUNT0SRC_INTOSC2      - Internal Oscillator2 Clock Source
//! - \b DCC_COUNT0SRC_TCK          - Preliminary Clock Source
//! - \b DCC_COUNT0SRC_SYSCLK       - System Clock Source
//! - \b DCC_COUNT0SRC_AUXCLK       - AUX Clock Source
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCC_setCounter0ClkSource(uint32_t base, DCC_Count0ClockSource source)
{
    //
    // Check the arguments.
    //
    ;

    //
    //  Set the specified clock source
    //
    __eallow();

    //
    //  DCC Clk source is of 5bits DCCCLKSRC0[4:0]
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &
                                   ((0x7FU) << 5U)) |
                                   (((0xAU) << 12U) |
                                   (uint16_t)source);

    __edis();
}

//*****************************************************************************
//
//! Get Counter 1 Clock Source
//!
//! \param base is the DCC module base address
//!
//! This function gets the counter 1 clock source.
//!
//! \return Returns one of the following enumerated source values:
//! - \b DCC_COUNT1SRC_PLL             - PLL021SSP Clock Out Source
//! - \b DCC_COUNT1SRC_INTOSC1         - Internal Oscillator1 Clock Source
//! - \b DCC_COUNT1SRC_INTOSC2         - Internal Oscillator2 Clock Source
//! - \b DCC_COUNT1SRC_SYSCLK          - System Clock Source
//! - \b DCC_COUNT1SRC_AUXCLKIN        - AUX Clock input Source
//! - \b DCC_COUNT1SRC_EPWM            - EPWM Clock Source
//! - \b DCC_COUNT1SRC_ADCCLK          - ADC Clock Source
//! - \b DCC_COUNT1SRC_WDCLK           - Watch Dog Clock Source
//! - \b DCC_COUNT1SRC_CANX            - CANxBIT Clock Source
//! - \b DCC_COUNT1SRC_SYSAPLL_CLK_AUX - System APLL Aux Clk

//
//*****************************************************************************
static inline uint16_t
DCC_getCounter1ClkSource(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    //  Get the specified clock source
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x24U)))) & 0x1FU);
}

//*****************************************************************************
//
//! Get Counter 0 Clock Source
//!
//! \param base is the DCC module base address
//!
//! This function gets the counter 0 clock source.
//!
//! \return Returns one of the following enumerated source values:
//! - \b DCC_COUNT0SRC_XTAL         - Accurate Clock Source
//! - \b DCC_COUNT0SRC_INTOSC1      - Internal Oscillator1 Clock Source
//! - \b DCC_COUNT0SRC_INTOSC2      - Internal Oscillator2 Clock Source
//! - \b DCC_COUNT0SRC_TCK          - Preliminary Clock Source
//! - \b DCC_COUNT0SRC_SYSCLK       - System Clock Source
//! - \b DCC_COUNT0SRC_AUXCLK       - AUX Clock Source
//
//*****************************************************************************
static inline uint16_t
DCC_getCounter0ClkSource(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    //  Get the specified clock source
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) & 0xFU);
}

//*****************************************************************************
//
//! Set the seed values
//!
//! \param base is the DCC module base address
//! \param counter0 sets the seed value that gets loaded into Counter 0
//! \param validCounter0 sets the seed value that gets loaded into the valid
//!  duration counter for Counter 0
//! \param counter1 sets the seed value that gets loaded into Counter 1
//!
//! This function sets the seed values for Counter 0, Valid Duration Counter 0,
//! and Counter 1.
//!
//! \note
//! -# Operating DCC with '0' set as the seed value for Counter 0, Valid
//! Duration Counter 0, and/or Counter 1 will result in undefined operation.
//! -# The Valid Duration Counter 0 is designed to be at least four cycles
//! wide and shouldn't be programmed with a value less than '4'.
//!
//! \return None.
//
//*****************************************************************************


static inline void
DCC_setCounterSeeds(uint32_t base, uint32_t counter0, uint32_t validCounter0,
                    uint32_t counter1)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;
    ;
    ;
    ;
    ;

    __eallow();

    //
    // Set Counter 0 Seed
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) = counter0 & (0xFFFFU);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U + 2U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x8U + 2U)))) &
                                          (0xFFF0U)) |
                                         ((uint32_t)(counter0 &
                                          (0xF0000U)) >> 16U);

    //
    // Set Valid Duration Counter 0 Seed
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) = validCounter0;

    //
    // Set Counter 1 Seed
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) = counter1 & (0xFFFFU);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U + 2U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x10U + 2U)))) &
                                          (0xFFF0U)) |
                                         ((uint32_t)(counter1 &
                                          (0xF0000U)) >> 16U);

    __edis();
}


//*****************************************************************************
//
//! Verify the frequency of a clock source using a reference clock
//!
//! \param base is the DCC module base address
//! \param clock1 is the clock source to be verified
//! \param freq1 is the frequency of the clock source to be verified
//! \param clock0 is the reference clock
//! \param freq0 is the frequency of the reference clock
//! \param tolerance is the DCC error tolerance in percentage
//! \param freqerr is the allowable Frequency Tolerance in percentage
//! \param freq_sysclk is the frequency of the system clock
//!
//! This function verifies the frequency of the specified clock using a
//! reference clock.
//!
//! \note Make sure that the frequency of all the clocks are in the same unit
//!
//! \return Returns \b true if the actual frequency of clock1 is matching
//! freq1, \b false otherwise
//
//*****************************************************************************
extern _Bool
DCC_verifyClockFrequency(uint32_t base,
                         DCC_Count1ClockSource clock1,
                         float32_t freq1,
                         DCC_Count0ClockSource clock0,
                         float32_t freq0,
                         float32_t tolerance,
                         float32_t freqerr,
                         float32_t freq_sysclk);

//*****************************************************************************
//
//! Measure the frequency of a clock source using a reference clock
//!
//! \param base is the DCC module base address
//! \param clock1 is the clock source to be measured
//! \param clock0 is the reference clock
//! \param freq0 is the frequency of the reference clock
//! \param tolerance is the DCC error tolerance in percentage
//! \param freqerr is the allowable Frequency Tolerance in percentage
//! \param freq_sysclk is the frequency of the system clock
//!
//! This function measures the frequency of the specified clock using a
//! reference clock.
//!
//! \note Make sure that the frequency of all the clocks are in the same unit
//!
//! \return Measured clock frequency
//
//*****************************************************************************
extern float32_t
DCC_measureClockFrequency(uint32_t base,
                          DCC_Count1ClockSource clock1,
                          DCC_Count0ClockSource clock0,
                          float32_t freq0,
                          float32_t tolerance,
                          float32_t freqerr,
                          float32_t freq_sysclk);

//*****************************************************************************
//
//! Continuously monitor the frequency of a clock source using a reference clock
//!
//! \param base is the DCC module base address
//! \param clock1 is the clock source to be verified
//! \param freq1 is the frequency of the clock source to be verified
//! \param clock0 is the reference clock
//! \param freq0 is the frequency of the reference clock
//! \param tolerance is the DCC error tolerance in percentage
//! \param freqerr is the allowable Frequency Tolerance in percentage
//! \param freq_sysclk is the frequency of the system clock
//!
//! This function continuously monitors the frequency of the specified clock
//! using a reference clock. An error signal is generated if the frequency
//! ratio is altered.
//!
//! \note Make sure that the frequency of all the clocks are in the same unit
//!
//! \note This function does not enable the DCC interrupt. The user application
//! must enable it to trigger an intetrupt when an error is detected.
//!
//! \return Returns None
//
//*****************************************************************************
extern void
DCC_continuousMonitor(uint32_t base,
                      DCC_Count1ClockSource clock1,
                      float32_t freq1,
                      DCC_Count0ClockSource clock0,
                      float32_t freq0,
                      float32_t tolerance,
                      float32_t freqerr,
                      float32_t freq_sysclk);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   dma.h
//
// TITLE:  C28x DMA driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup dma_api DMA
//! \brief This module is used for DMA configurations.
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_dma.h
//
// TITLE:   Definitions for the DMA registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the DMA register offsets
//
//*************************************************************************************************



//*************************************************************************************************
//
// The following are defines for the bit fields in the DMACTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DEBUGCTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PRIORITYCTRL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PRIORITYSTAT register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the MODE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CONTROL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BURST_SIZE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BURST_COUNT register
//
//*************************************************************************************************




//*****************************************************************************
//
// Values that can be passed to DMA_configMode() as the config parameter.
//
//*****************************************************************************
//! Only one burst transfer performed per trigger.
//! Burst transfers occur without additional event triggers after the first.

//! DMA channel will be disabled at the end of a transfer.
//! DMA reinitializes when the transfer count is zero and waits for a trigger.

//! DMA transfers 16 bits at a time.
//! DMA transfers 32 bits at a time.

//*****************************************************************************
//
//! Values that can be passed to DMA_configMode() as the \e trigger parameter.
//
//*****************************************************************************
typedef enum
{
    DMA_TRIGGER_SOFTWARE   = 0,

    DMA_TRIGGER_ADCA1      = 1,
    DMA_TRIGGER_ADCA2      = 2,
    DMA_TRIGGER_ADCA3      = 3,
    DMA_TRIGGER_ADCA4      = 4,
    DMA_TRIGGER_ADCAEVT    = 5,
    DMA_TRIGGER_ADCB1      = 6,
    DMA_TRIGGER_ADCB2      = 7,
    DMA_TRIGGER_ADCB3      = 8,
    DMA_TRIGGER_ADCB4      = 9,
    DMA_TRIGGER_ADCBEVT    = 10,
    DMA_TRIGGER_ADCC1      = 11,
    DMA_TRIGGER_ADCC2      = 12,
    DMA_TRIGGER_ADCC3      = 13,
    DMA_TRIGGER_ADCC4      = 14,
    DMA_TRIGGER_ADCCEVT    = 15,

    DMA_TRIGGER_XINT1      = 29,
    DMA_TRIGGER_XINT2      = 30,
    DMA_TRIGGER_XINT3      = 31,
    DMA_TRIGGER_XINT4      = 32,
    DMA_TRIGGER_XINT5      = 33,

    DMA_TRIGGER_EPWM1SOCA  = 36,
    DMA_TRIGGER_EPWM1SOCB  = 37,
    DMA_TRIGGER_EPWM2SOCA  = 38,
    DMA_TRIGGER_EPWM2SOCB  = 39,
    DMA_TRIGGER_EPWM3SOCA  = 40,
    DMA_TRIGGER_EPWM3SOCB  = 41,
    DMA_TRIGGER_EPWM4SOCA  = 42,
    DMA_TRIGGER_EPWM4SOCB  = 43,
    DMA_TRIGGER_EPWM5SOCA  = 44,
    DMA_TRIGGER_EPWM5SOCB  = 45,
    DMA_TRIGGER_EPWM6SOCA  = 46,
    DMA_TRIGGER_EPWM6SOCB  = 47,
    DMA_TRIGGER_EPWM7SOCA  = 48,
    DMA_TRIGGER_EPWM7SOCB  = 49,
    DMA_TRIGGER_EPWM8SOCA  = 50,
    DMA_TRIGGER_EPWM8SOCB  = 51,

    DMA_TRIGGER_TINT0      = 68,
    DMA_TRIGGER_TINT1      = 69,
    DMA_TRIGGER_TINT2      = 70,

    DMA_TRIGGER_ECAP1      = 75,
    DMA_TRIGGER_ECAP2      = 76,
    DMA_TRIGGER_ECAP3      = 77,

    DMA_TRIGGER_SDFM1FLT1  = 96,
    DMA_TRIGGER_SDFM1FLT2  = 97,
    DMA_TRIGGER_SDFM1FLT3  = 98,
    DMA_TRIGGER_SDFM1FLT4  = 99,
    DMA_TRIGGER_SDFM2FLT1  = 101,
    DMA_TRIGGER_SDFM2FLT2  = 102,
    DMA_TRIGGER_SDFM2FLT3  = 103,
    DMA_TRIGGER_SDFM2FLT4  = 104,

    DMA_TRIGGER_SPIATX     = 109,
    DMA_TRIGGER_SPIARX     = 110,
    DMA_TRIGGER_SPIBTX     = 111,
    DMA_TRIGGER_SPIBRX     = 112,

    DMA_TRIGGER_LINATX     = 117,
    DMA_TRIGGER_LINARX     = 118,
    DMA_TRIGGER_LINBTX     = 119,
    DMA_TRIGGER_LINBRX     = 120,

    DMA_TRIGGER_FSITXA     = 123,
    DMA_TRIGGER_FSI_DATA_TAG_MATCH  = 124,
    DMA_TRIGGER_FSIRXA     = 125,
    DMA_TRIGGER_FSI_PING_DATA_MATCH = 126,

    DMA_TRIGGER_CLB1INT    = 127,
    DMA_TRIGGER_CLB2INT    = 128,
    DMA_TRIGGER_CLB3INT    = 129,
    DMA_TRIGGER_CLB4INT    = 130,

    DMA_TRIGGER_CANAIF1    = 167,
    DMA_TRIGGER_CANAIF2    = 168,
    DMA_TRIGGER_CANAIF3    = 169,

    DMA_TRIGGER_HICA       = 179,

    DMA_TRIGGER_AESA_CONTEXTIN  = 180,
    DMA_TRIGGER_AESA_DATAIN     = 181,
    DMA_TRIGGER_AESA_CONTEXTOUT = 182,
    DMA_TRIGGER_AESA_DATAOUT    = 183,

    DMA_TRIGGER_EPG1       = 184
} DMA_Trigger;

//*****************************************************************************
//
//! Values that can be passed to DMA_setInterruptMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! DMA interrupt is generated at the beginning of a transfer
    DMA_INT_AT_BEGINNING,
    //! DMA interrupt is generated at the end of a transfer
    DMA_INT_AT_END
} DMA_InterruptMode;

//*****************************************************************************
//
//! Values that can be passed to DMA_setEmulationMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Transmission stops after current read-write access is completed
    DMA_EMULATION_STOP,
    //! Continue DMA operation regardless of emulation suspend
    DMA_EMULATION_FREE_RUN
} DMA_EmulationMode;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an DMA channel base address.
//!
//! \param base specifies the DMA channel base address.
//!
//! This function determines if a DMA channel base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Initializes the DMA controller to a known state.
//!
//! This function configures does a hard reset of the DMA controller in order
//! to put it into a known state. The function also sets the DMA to run free
//! during an emulation suspend (see the field DEBUGCTRL.FREE for more info).
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_initController(void)
{
    __eallow();

    //
    // Set the hard reset bit. One NOP is required after HARDRESET.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00001000U + 0x0U)))) |= 0x1U;
    __asm(" NOP");

    __edis();
}

//*****************************************************************************
//
//! Channel Soft Reset
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function does a soft reset to place the channel into its default state
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_triggerSoftReset(uint32_t base)
{
    __eallow();

    //
    // Set the soft reset bit. One NOP is required after SOFTRESET.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x4U;
    __asm(" NOP");

    __edis();
}

//*****************************************************************************
//
//! Sets DMA emulation mode.
//!
//! \param mode is the emulation mode to be selected.
//!
//! This function sets the behavior of the DMA operation when an emulation
//! suspend occurs. The \e mode parameter can be one of the following:
//!
//! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is
//!   completed.
//! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a
//!   the suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_setEmulationMode(DMA_EmulationMode mode)
{
    __eallow();

    //
    // Set emulation mode
    //
    if(mode == DMA_EMULATION_STOP)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00001000U + 0x1U)))) &= ~0x8000U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00001000U + 0x1U)))) |= 0x8000U;
    }

    __edis();
}

//*****************************************************************************
//
//! Enables peripherals to trigger a DMA transfer.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function enables the selected peripheral trigger to start a DMA
//! transfer on the specified channel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_enableTrigger(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the peripheral interrupt trigger enable bit.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x100U;
    __edis();
}

//*****************************************************************************
//
//! Disables peripherals from triggering a DMA transfer.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function disables the selected peripheral trigger from starting a DMA
//! transfer on the specified channel. This also disables the use of the
//! software force using the DMA_forceTrigger() API.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_disableTrigger(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the peripheral interrupt trigger enable bit.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x100U;
    __edis();
}

//*****************************************************************************
//
//! Force a peripheral trigger to a DMA channel.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function sets the peripheral trigger flag and if triggering a DMA
//! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be
//! forced.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_forceTrigger(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the peripheral interrupt trigger force bit.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x8U;
    __edis();
}

//*****************************************************************************
//
//! Clears a DMA channel's peripheral trigger flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function clears the peripheral trigger flag. Normally, you would use
//! this function when initializing the DMA for the first time. The flag is
//! cleared automatically when the DMA starts the first burst of a transfer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_clearTriggerFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write a one to the clear bit to clear the peripheral trigger flag.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x10U;
    __edis();
}

//*****************************************************************************
//
//! Gets the status of a DMA channel's Transfer Status Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Transfer Status Flag is set, which
//! means a DMA transfer has begun.
//! This flag is cleared when TRANSFER_COUNT reaches zero, or when the
//! HARDRESET or SOFTRESET bit is set.
//!
//! \return Returns \b true if the Transfer Status Flag is set. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getTransferStatusFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the Transfer Status Flag and return appropriately.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) & 0x800U) != 0U);
}

//*****************************************************************************
//
//! Gets the status of a DMA channel's Burst Status Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Burst Status Flag is set, which
//! means a DMA burst has begun.
//! This flag is cleared when BURST_COUNT reaches zero, or when the
//! HARDRESET or SOFTRESET bit is set.
//!
//! \return Returns \b true if the Burst Status Flag is set. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getBurstStatusFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the Burst Status Flag and return appropriately.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) & 0x1000U) != 0U);
}

//*****************************************************************************
//
//! Gets the status of a DMA channel's Run Status Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Run Status Flag is set, which
//! means the DMA channel is enabled.
//! This flag is cleared when a transfer completes (TRANSFER_COUNT = 0) and
//! continuous mode is disabled, or when the HARDRESET, SOFTRESET, or HALT bit
//! is set.
//!
//! \return Returns \b true if the channel is enabled. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getRunStatusFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the Run Status Flag and return appropriately.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) & 0x2000U) != 0U);
}

//*****************************************************************************
//
//! Gets the status of a DMA channel's Overflow Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Overflow Flag is set, which
//! means peripheral event trigger was received while Peripheral Event Trigger
//! Flag was already set.
//! This flag can be cleared by writing to ERRCLR bit, using the function
//! DMA_clearErrorFlag().
//!
//! \return Returns \b true if the channel is enabled. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getOverflowFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the Overflow Flag and return appropriately.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) & 0x4000U) != 0U);
}

//*****************************************************************************
//
//! Gets the status of a DMA channel's peripheral trigger flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if a peripheral trigger event has occurred
//! The flag is automatically cleared when the first burst transfer begins, but
//! if needed, it can be cleared using DMA_clearTriggerFlag().
//!
//! \return Returns \b true if a peripheral trigger event has occurred and its
//! flag is set. Returns \b false otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getTriggerFlagStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the peripheral trigger flag and return appropriately.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) & 0x100U) != 0U);
}

//*****************************************************************************
//
//! Starts a DMA channel.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function starts the DMA running, typically after you have configured
//! it. It will wait for the first trigger event to start operation. To halt
//! the channel use DMA_stopChannel().
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_startChannel(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the run bit.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Halts a DMA channel.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function halts the DMA at its current state and any current read-write
//! access is completed. To start the channel again use DMA_startChannel().
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_stopChannel(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the halt bit.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Enables a DMA channel interrupt source.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function enables the indicated DMA channel interrupt source.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_enableInterrupt(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the specified DMA channel interrupt.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Disables a DMA channel interrupt source.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function disables the indicated DMA channel interrupt source.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_disableInterrupt(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the specified DMA channel interrupt.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Enables the DMA channel overrun interrupt.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function enables the indicated DMA channel's ability to generate an
//! interrupt upon the detection of an overrun. An overrun is when a peripheral
//! event trigger is received by the DMA before a previous trigger on that
//! channel had been serviced and its flag had been cleared.
//!
//! Note that this is the same interrupt signal as the interrupt that gets
//! generated at the beginning/end of a transfer. That interrupt must first be
//! enabled using DMA_enableInterrupt() in order for the overrun interrupt to
//! be generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_enableOverrunInterrupt(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the specified DMA channel interrupt.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x80U;
    __edis();
}

//*****************************************************************************
//
//! Disables the DMA channel overrun interrupt.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function disables the indicated DMA channel's ability to generate an
//! interrupt upon the detection of an overrun.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_disableOverrunInterrupt(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the specified DMA channel interrupt.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x80U;
    __edis();
}

//*****************************************************************************
//
//! Clears the DMA channel error flags.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function clears both the DMA channel's sync error flag and its
//! overrun error flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_clearErrorFlag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write to the error clear bit.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x80U;
    __edis();
}

//*****************************************************************************
//
//! Sets the interrupt generation mode of a DMA channel interrupt.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param mode is a flag to indicate the channel interrupt mode.
//!
//! This function sets the channel interrupt mode. When the \e mode parameter
//! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the
//! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be
//! generated at the beginning of a new transfer. Generating at the beginning
//! of a new transfer is the default behavior.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Write the selected interrupt generation mode to the register.
    //
    if(mode == DMA_INT_AT_END)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x200U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x200U;
    }

    __edis();
}

//*****************************************************************************
//
//! Sets the DMA channel priority mode.
//!
//! \param ch1IsHighPri is a flag to indicate the channel interrupt mode.
//!
//! This function sets the channel interrupt mode. When the \e ch1IsHighPri
//! parameter is \b false, the DMA channels are serviced in round-robin mode.
//! This is the default behavior.
//!
//! If \b true, channel 1 will be given higher priority than the other
//! channels. This means that if a channel 1 trigger occurs, the current word
//! transfer on any other channel is completed and channel 1 is serviced for
//! the complete burst count. The lower-priority channel's interrupted transfer
//! will then resume.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_setPriorityMode(_Bool ch1IsHighPri)
{
    __eallow();

    //
    // Write the selected priority mode to the register.
    //
    if(ch1IsHighPri)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00001000U + 0x4U)))) |=
            0x1U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00001000U + 0x4U)))) &=
            ~0x1U;
    }

    __edis();
}

//*****************************************************************************
//
//! Configures the source address for the DMA channel
//!
//! \param base is the base address of the DMA channel control registers.
//! \param *srcAddr is a source address.
//!
//! This function configures the source address of a DMA
//! channel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_configSourceAddress(uint32_t base, const void *srcAddr)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set up SOURCE address.
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x10U)))) = (uint32_t)srcAddr;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x12U))))     = (uint32_t)srcAddr;

    __edis();
}

//*****************************************************************************
//
//! Configures the destination address for the DMA channel
//!
//! \param base is the base address of the DMA channel control registers.
//! \param *destAddr is the destination address.
//!
//! This function configures the destinaton address of a DMA
//! channel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_configDestAddress(uint32_t base, const void *destAddr)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set up DESTINATION address.
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x18U)))) = (uint32_t)destAddr;
    (*((volatile uint32_t *)((uintptr_t)(base + 0x1AU))))     = (uint32_t)destAddr;

    __edis();
}

//*****************************************************************************
//
//! Configures the DMA channel
//!
//! \param base is the base address of the DMA channel control registers.
//! \param *destAddr is the destination address.
//! \param *srcAddr is a source address.
//!
//! This function configures the source and destination addresses of a DMA
//! channel. The parameters are pointers to the data to be transferred.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr);

//*****************************************************************************
//
//! Configures the DMA channel's burst settings.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param size is the number of words transferred per burst.
//! \param srcStep is the amount to increment or decrement the source address
//! after each word of a burst.
//! \param destStep is the amount to increment or decrement the destination
//! address after each word of a burst.
//!
//! This function configures the size of each burst and the address step size.
//!
//! The \e size parameter is the number of words that will be transferred
//! during a single burst. Possible amounts range from 1 word to 32 words.
//!
//! The \e srcStep and \e destStep parameters specify the address step that
//! should be added to the source and destination addresses after each
//! transferred word of a burst. Only signed values from -4096 to 4095 are
//! valid.
//!
//! \note Note that regardless of what data size (configured by
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
//!
//! \return None.
//
//*****************************************************************************
extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep,
                            int16_t destStep);

//*****************************************************************************
//
//! Configures the DMA channel's transfer settings.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param transferSize is the number of bursts per transfer.
//! \param srcStep is the amount to increment or decrement the source address
//! after each burst of a transfer unless a wrap occurs.
//! \param destStep is the amount to increment or decrement the destination
//! address after each burst of a transfer unless a wrap occurs.
//!
//! This function configures the transfer size and the address step that is
//! made after each burst.
//!
//! The \e transferSize parameter is the number of bursts per transfer. If DMA
//! channel interrupts are enabled, they will occur after this number of bursts
//! have completed. The maximum number of bursts is 65536.
//!
//! The \e srcStep and \e destStep parameters specify the address step that
//! should be added to the source and destination addresses after each
//! transferred burst of a transfer. Only signed values from -4096 to 4095 are
//! valid. If a wrap occurs, these step values will be ignored. Wrapping is
//! configured with DMA_configWrap().
//!
//! \note Note that regardless of what data size (configured by
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep,
                   int16_t destStep);

//*****************************************************************************
//
//! Configures the DMA channel's wrap settings.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param srcWrapSize is the number of bursts to be transferred before a wrap
//! of the source address occurs.
//! \param srcStep is the amount to increment or decrement the source address
//! after each burst of a transfer unless a wrap occurs.
//! \param destWrapSize is the number of bursts to be transferred before a wrap
//! of the destination address occurs.
//! \param destStep is the amount to increment or decrement the destination
//! address after each burst of a transfer unless a wrap occurs.
//!
//! This function configures the DMA channel's wrap settings.
//!
//! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts
//! that are to be transferred before their respective addresses are wrapped.
//! The maximum wrap size is 65536 bursts.
//!
//! The \e srcStep and \e destStep parameters specify the address step that
//! should be added to the source and destination addresses when the wrap
//! occurs.  Only signed values from -4096 to 4095 are valid.
//!
//! \note Note that regardless of what data size (configured by
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep,
               uint32_t destWrapSize, int16_t destStep);

//*****************************************************************************
//
//! Configures the DMA channel trigger and mode.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param trigger is the interrupt source that triggers a DMA transfer.
//! \param config is a bit field of several configuration selections.
//!
//! This function configures the DMA channel's trigger and mode.
//!
//! The \e trigger parameter is the interrupt source that will trigger the
//! start of a DMA transfer.
//!
//! The \e config parameter is the logical OR of the following values:
//! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled,
//!   the subsequent burst transfers occur without additional event triggers
//!   after the first event trigger. If disabled, only one burst transfer is
//!   performed per event trigger.
//! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled
//!   the DMA reinitializes when the transfer count is zero and waits for the
//!   next interrupt event trigger. If disabled, the DMA stops and clears the
//!   run status bit.
//! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects
//!   whether the databus width is 16 or 32 bits.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE: ecap.h
//
// TITLE: C28x ECAP driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup ecap_api eCAP
//! @{
//
//*****************************************************************************

//*****************************************************************************
//
// Includes
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_ecap.h
//
// TITLE:   Definitions for the ECAP registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the ECAP register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL2 register
//
//*************************************************************************************************
                                             // flags.

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECEINT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAPSYNCINSEL register
//
//*************************************************************************************************




//*****************************************************************************
//
// eCAP minimum and maximum values
//
//*****************************************************************************

//*****************************************************************************
//
// Values that can be passed to ECAP_enableInterrupt(),
// ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as
// the intFlags parameter and returned by ECAP_getInterruptSource().
//
//*****************************************************************************
//! Event 1 ISR source
//!
//! Event 2 ISR source
//!
//! Event 3 ISR source
//!
//! Event 4 ISR source
//!
//! Counter overflow ISR source
//!
//! Counter equals period ISR source
//!
//! Counter equals compare ISR source
//!

//*****************************************************************************
//
//! Values that can be passed to ECAP_setEmulationMode() as the
//! \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    //! TSCTR is stopped on emulation suspension
    ECAP_EMULATION_STOP             = 0x0U,
    //! TSCTR runs until 0 before stopping on emulation suspension
    ECAP_EMULATION_RUN_TO_ZERO      = 0x1U,
    //! TSCTR is not affected by emulation suspension
    ECAP_EMULATION_FREE_RUN         = 0x2U
}ECAP_EmulationMode;

//*****************************************************************************
//
//! Values that can be passed to ECAP_setCaptureMode() as the
//! \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    //! eCAP operates in continuous capture mode
    ECAP_CONTINUOUS_CAPTURE_MODE    = 0U,
    //! eCAP operates in one shot capture mode
    ECAP_ONE_SHOT_CAPTURE_MODE      = 1U
}ECAP_CaptureMode;

//*****************************************************************************
//
//! Values that can be passed to ECAP_setEventPolarity(),ECAP_setCaptureMode(),
//! ECAP_enableCounterResetOnEvent(),ECAP_disableCounterResetOnEvent(),
//! ECAP_getEventTimeStamp(),ECAP_setDMASource() as the \e event parameter.
//
//*****************************************************************************
typedef enum
{
    ECAP_EVENT_1 = 0U,   //!< eCAP event 1
    ECAP_EVENT_2 = 1U,   //!< eCAP event 2
    ECAP_EVENT_3 = 2U,   //!< eCAP event 3
    ECAP_EVENT_4 = 3U    //!< eCAP event 4
}ECAP_Events;

//*****************************************************************************
//
//! Values that can be passed to ECAP_setSyncOutMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! sync out on the sync in signal and software force
    ECAP_SYNC_OUT_SYNCI         = 0x00,
    //! sync out on counter equals period
    ECAP_SYNC_OUT_COUNTER_PRD   = 0x40,
    //! Disable sync out signal
    ECAP_SYNC_OUT_DISABLED      = 0x80
}ECAP_SyncOutMode;

//*****************************************************************************
//
//! Values that can be passed to ECAP_setAPWMPolarity() as the \e polarity
//! parameter.
//
//*****************************************************************************
typedef enum
{
    ECAP_APWM_ACTIVE_HIGH   = 0x000, //!< APWM is active high
    ECAP_APWM_ACTIVE_LOW    = 0x400  //!< APWM is active low
}ECAP_APWMPolarity;

//*****************************************************************************
//
//! Values that can be passed to ECAP_setEventPolarity() as the \e polarity
//! parameter.
//
//*****************************************************************************
typedef enum
{
    ECAP_EVNT_RISING_EDGE   = 0U, //!< Rising edge polarity
    ECAP_EVNT_FALLING_EDGE  = 1U  //!< Falling edge polarity
}ECAP_EventPolarity;

//*****************************************************************************
//
//! Values that can be passed to ECAP_selectECAPInput() as the \e input
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! GPIO Input Crossbar output signal-1
    ECAP_INPUT_INPUTXBAR1 = 0,
    //! GPIO Input Crossbar output signal-2
    ECAP_INPUT_INPUTXBAR2 = 1,
    //! GPIO Input Crossbar output signal-3
    ECAP_INPUT_INPUTXBAR3 = 2,
    //! GPIO Input Crossbar output signal-4
    ECAP_INPUT_INPUTXBAR4 = 3,
    //! GPIO Input Crossbar output signal-5
    ECAP_INPUT_INPUTXBAR5 = 4,
    //! GPIO Input Crossbar output signal-6
    ECAP_INPUT_INPUTXBAR6 = 5,
    //! GPIO Input Crossbar output signal-7
    ECAP_INPUT_INPUTXBAR7 = 6,
    //! GPIO Input Crossbar output signal-8
    ECAP_INPUT_INPUTXBAR8 = 7,
    //! GPIO Input Crossbar output signal-9
    ECAP_INPUT_INPUTXBAR9 = 8,
    //! GPIO Input Crossbar output signal-10
    ECAP_INPUT_INPUTXBAR10 = 9,
    //! GPIO Input Crossbar output signal-11
    ECAP_INPUT_INPUTXBAR11 = 10,
    //! GPIO Input Crossbar output signal-12
    ECAP_INPUT_INPUTXBAR12 = 11,
    //! GPIO Input Crossbar output signal-13
    ECAP_INPUT_INPUTXBAR13 = 12,
    //! GPIO Input Crossbar output signal-14
    ECAP_INPUT_INPUTXBAR14 = 13,
    //! GPIO Input Crossbar output signal-15
    ECAP_INPUT_INPUTXBAR15 = 14,
    //! GPIO Input Crossbar output signal-16
    ECAP_INPUT_INPUTXBAR16 = 15,
    //! CLB1 CLBOUT14 input for ECAP1 instance
    ECAP_INPUT_ECAP1_CLB1_CLBOUT14 = 16,
    //! CLB2 CLBOUT14 input for ECAP2 instance
    ECAP_INPUT_ECAP2_CLB2_CLBOUT14 = 16,
    //! CLB1 CLBOUT14 input for ECAP3 instance
    ECAP_INPUT_ECAP3_CLB1_CLBOUT14 = 16,
    //! CLB1 CLBOUT15 input for ECAP1 instance
    ECAP_INPUT_ECAP1_CLB1_CLBOUT15 = 17,
    //! CLB2 CLBOUT15 input for ECAP2 instance
    ECAP_INPUT_ECAP2_CLB2_CLBOUT15 = 17,
    //! CLB1 CLBOUT15 input for ECAP3 instance
    ECAP_INPUT_ECAP3_CLB1_CLBOUT15 = 17,
    //! CLB2 CLBOUT14 input for ECAP1 instance
    ECAP_INPUT_ECAP1_CLB2_CLBOUT14 = 18,
    //! CLB1 CLBOUT14 input for ECAP2 instance
    ECAP_INPUT_ECAP2_CLB1_CLBOUT14 = 18,
    //! CLB2 CLBOUT14 input for ECAP3 instance
    ECAP_INPUT_ECAP3_CLB2_CLBOUT14 = 18,
    //! CLB2 CLBOUT15 input for ECAP1 instance
    ECAP_INPUT_ECAP1_CLB2_CLBOUT15 = 19,
    //! CLB1 CLBOUT15 input for ECAP2 instance
    ECAP_INPUT_ECAP2_CLB1_CLBOUT15 = 19,
    //! CLB2 CLBOUT15 input for ECAP3 instance
    ECAP_INPUT_ECAP3_CLB2_CLBOUT15 = 19,
    //! CANA INT0 Input
    ECAP_INPUT_CANA_INT0 = 20,
    //! Output Xbar Output-1
    ECAP_INPUT_OUTPUTXBAR1 = 24,
    //! Output Xbar Output-2
    ECAP_INPUT_OUTPUTXBAR2 = 25,
    //! Output Xbar Output-3
    ECAP_INPUT_OUTPUTXBAR3 = 26,
    //! Output Xbar Output-4
    ECAP_INPUT_OUTPUTXBAR4 = 27,
    //! Output Xbar Output-5
    ECAP_INPUT_OUTPUTXBAR5 = 28,
    //! Output Xbar Output-6
    ECAP_INPUT_OUTPUTXBAR6 = 29,
    //! Output Xbar Output-7
    ECAP_INPUT_OUTPUTXBAR7 = 30,
    //! Output Xbar Output-8
    ECAP_INPUT_OUTPUTXBAR8 = 31,
    //! ADCC Event4
    ECAP_INPUT_ADC_C_EVENT4 = 36,
    //! ADCC Event3
    ECAP_INPUT_ADC_C_EVENT3 = 37,
    //! ADCC Event2
    ECAP_INPUT_ADC_C_EVENT2 = 38,
    //! ADCC Event1
    ECAP_INPUT_ADC_C_EVENT1 = 39,
    //! ADCB Event4
    ECAP_INPUT_ADC_B_EVENT4 = 40,
    //! ADCB Event3
    ECAP_INPUT_ADC_B_EVENT3 = 41,
    //! ADCB Event2
    ECAP_INPUT_ADC_B_EVENT2 = 42,
    //! ADCB Event1
    ECAP_INPUT_ADC_B_EVENT1 = 43,
    //! ADCA Event4
    ECAP_INPUT_ADC_A_EVENT4 = 44,
    //! ADCA Event3
    ECAP_INPUT_ADC_A_EVENT3 = 45,
    //! ADCA Event2
    ECAP_INPUT_ADC_A_EVENT2 = 46,
    //! ADCA Event1
    ECAP_INPUT_ADC_A_EVENT1 = 47,
    //! FSIA Rx MSR Line
    ECAP_INPUT_FSIA_RX_MSR_LINE = 48,
    //! FSIA Rx MSR Line Rise
    ECAP_INPUT_FSIA_RX_MSR_LINE_RISE = 49,
    //! FSIA Rx MSR Line Fall
    ECAP_INPUT_FSIA_RX_MSR_LINE_FALL = 50,
    //! SDFM-2 Filter-1 Compare Low Trip
    ECAP_INPUT_SDFM2_FLT1_COMPARE_LOW = 60,
    //! SDFM-2 Filter-2 Compare Low Trip
    ECAP_INPUT_SDFM2_FLT2_COMPARE_LOW = 61,
    //! SDFM-2 Filter-3 Compare Low Trip
    ECAP_INPUT_SDFM2_FLT3_COMPARE_LOW = 62,
    //! SDFM-2 Filter-4 Compare Low Trip
    ECAP_INPUT_SDFM2_FLT4_COMPARE_LOW = 63,
    //! SDFM-1 Filter-1 Compare Low Trip
    ECAP_INPUT_SDFM1_FLT1_COMPARE_LOW = 64,
    //! SDFM-1 Filter-2 Compare Low Trip
    ECAP_INPUT_SDFM1_FLT2_COMPARE_LOW = 65,
    //! SDFM-1 Filter-3 Compare Low Trip
    ECAP_INPUT_SDFM1_FLT3_COMPARE_LOW = 66,
    //! SDFM-1 Filter-4 Compare Low Trip
    ECAP_INPUT_SDFM1_FLT4_COMPARE_LOW = 67,
    //! SDFM-2 Filter-1 Compare Z Trip
    ECAP_INPUT_SDFM2_FLT1_COMPARE_Z = 68,
    //! SDFM-2 Filter-2 Compare Low Trip
    ECAP_INPUT_SDFM2_FLT2_COMPARE_Z = 69,
    //! SDFM-2 Filter-3 Compare Low Trip
    ECAP_INPUT_SDFM2_FLT3_COMPARE_Z = 70,
    //! SDFM-2 Filter-4 Compare Low Trip
    ECAP_INPUT_SDFM2_FLT4_COMPARE_Z = 71,
    //! SDFM-1 Filter-1 Compare Z Trip
    ECAP_INPUT_SDFM1_FLT1_COMPARE_Z = 72,
    //! SDFM-1 Filter-2 Compare Low Trip
    ECAP_INPUT_SDFM1_FLT2_COMPARE_Z = 73,
    //! SDFM-1 Filter-3 Compare Low Trip
    ECAP_INPUT_SDFM1_FLT3_COMPARE_Z = 74,
    //! SDFM-1 Filter-4 Compare Low Trip
    ECAP_INPUT_SDFM1_FLT4_COMPARE_Z = 75,
    //! SDFM-2 Filter-1 Compare High Trip
    ECAP_INPUT_SDFM2_FLT1_COMPARE_HIGH = 76,
    //! SDFM-2 Filter-2 Compare High Trip
    ECAP_INPUT_SDFM2_FLT2_COMPARE_HIGH = 77,
    //! SDFM-2 Filter-3 Compare High Trip
    ECAP_INPUT_SDFM2_FLT3_COMPARE_HIGH = 78,
    //! SDFM-2 Filter-4 Compare High Trip
    ECAP_INPUT_SDFM2_FLT4_COMPARE_HIGH = 79,
    //! SDFM-1 Filter-1 Compare High Trip
    ECAP_INPUT_SDFM1_FLT1_COMPARE_HIGH = 80,
    //! SDFM-1 Filter-2 Compare High Trip
    ECAP_INPUT_SDFM1_FLT2_COMPARE_HIGH = 81,
    //! SDFM-1 Filter-3 Compare High Trip
    ECAP_INPUT_SDFM1_FLT3_COMPARE_HIGH = 82,
    //! SDFM-1 Filter-4 Compare High Trip
    ECAP_INPUT_SDFM1_FLT4_COMPARE_HIGH = 83,
    //! SDFM-2 Filter-1 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM2_FLT1_COMPARE_HIGH_OR_LOW = 84,
    //! SDFM-2 Filter-2 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM2_FLT2_COMPARE_HIGH_OR_LOW = 85,
    //! SDFM-2 Filter-3 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM2_FLT3_COMPARE_HIGH_OR_LOW = 86,
    //! SDFM-2 Filter-4 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM2_FLT4_COMPARE_HIGH_OR_LOW = 87,
    //! SDFM-1 Filter-1 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM1_FLT1_COMPARE_HIGH_OR_LOW = 88,
    //! SDFM-1 Filter-2 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM1_FLT2_COMPARE_HIGH_OR_LOW = 89,
    //! SDFM-1 Filter-3 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM1_FLT3_COMPARE_HIGH_OR_LOW = 90,
    //! SDFM-1 Filter-4 Compare High Trip or Low Trip
    ECAP_INPUT_SDFM1_FLT4_COMPARE_HIGH_OR_LOW = 91,
    //! Compare Subsystem-1 Low Trip
    ECAP_INPUT_CMPSS1_CTRIP_LOW = 96,
    //! Compare Subsystem-2 Low Trip
    ECAP_INPUT_CMPSS2_CTRIP_LOW = 97,
    //! Compare Subsystem-3 Low Trip
    ECAP_INPUT_CMPSS3_CTRIP_LOW = 98,
    //! Compare Subsystem-4 Low Trip
    ECAP_INPUT_CMPSS4_CTRIP_LOW = 99,
    //! Compare Subsystem-1 High Trip
    ECAP_INPUT_CMPSS1_CTRIP_HIGH = 108,
    //! Compare Subsystem-2 High Trip
    ECAP_INPUT_CMPSS2_CTRIP_HIGH = 109,
    //! Compare Subsystem-3 High Trip
    ECAP_INPUT_CMPSS3_CTRIP_HIGH = 110,
    //! Compare Subsystem-4 High Trip
    ECAP_INPUT_CMPSS4_CTRIP_HIGH = 111,
    //! GPIO8
    ECAP_INPUT_GPIO8 = 115,
    //! GPIO9
    ECAP_INPUT_GPIO9 = 116,
    //! GPIO22
    ECAP_INPUT_GPIO22 = 117,
    //! GPIO23
    ECAP_INPUT_GPIO23 = 118,
    //! Compare Subsystem-1 High Trip or Low Trip
    ECAP_INPUT_CMPSS1_CTRIP_HIGH_OR_LOW = 120,
    //! Compare Subsystem-2 High Trip or Low Trip
    ECAP_INPUT_CMPSS2_CTRIP_HIGH_OR_LOW = 121,
    //! Compare Subsystem-3 High Trip or Low Trip
    ECAP_INPUT_CMPSS3_CTRIP_HIGH_OR_LOW = 122,
    //! Compare Subsystem-4 High Trip or Low Trip
    ECAP_INPUT_CMPSS4_CTRIP_HIGH_OR_LOW = 123,
    //! GPTRIP7 input for instance ECAP1
    ECAP_INPUT_ECAP1_GPTRIP7 = 127,
    //! GPTRIP8 input for instance ECAP2
    ECAP_INPUT_ECAP2_GPTRIP8 = 127,
    //! GPTRIP9 input for instance ECAP3
    ECAP_INPUT_ECAP3_GPTRIP9 = 127,
}ECAP_InputCaptureSignals;

//*****************************************************************************
//
//! Values that can be passed to ECAP_setSyncInPulseSource() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Disable Sync-in
    ECAP_SYNC_IN_PULSE_SRC_DISABLE         = 0x0,
    //! Sync-in source is EPWM1 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1   = 0x1,
    //! Sync-in source is EPWM2 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2   = 0x2,
    //! Sync-in source is EPWM3 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3   = 0x3,
    //! Sync-in source is EPWM4 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4   = 0x4,
    //! Sync-in source is EPWM5 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5   = 0x5,
    //! Sync-in source is EPWM6 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6   = 0x6,
    //! Sync-in source is EPWM7 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7   = 0x7,
    //! Sync-in source is EPWM8 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8   = 0x8,
    //! Sync-in source is ECAP1 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1   = 0x11,
    //! Sync-in source is ECAP2 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2   = 0x12,
    //! Sync-in source is ECAP3 sync-out signal
    ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3   = 0x13,
    //! Sync-in source is Input XBAR out5 signal
    ECAP_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT5 = 0x18,
    //! Sync-in source is Input XBAR out6 signal
    ECAP_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT6 = 0x19,
}ECAP_SyncInPulseSource;

//*****************************************************************************
//
//! \internal
//! Checks eCAP base address.
//!
//! \param base specifies the eCAP module base address.
//!
//! This function determines if an eCAP module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets the input prescaler.
//!
//! \param base is the base address of the ECAP module.
//! \param preScalerValue is the pre scaler value for ECAP input
//!
//! This function divides the ECAP input scaler. The pre scale value is
//! doubled inside the module. For example a preScalerValue of 5 will divide
//! the scaler by 10. Use a value of 1 to divide the pre scaler by 1.
//! The \e preScalerValue should be less than \b ECAP_MAX_PRESCALER_VALUE.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setEventPrescaler(uint32_t base,
                                          uint16_t preScalerValue)
{
    ;

    ;

    __eallow();

    //
    // Write to PRESCALE bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) =
                 (((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) & (~0x3E00U)) |
                  (preScalerValue << 9U));
    __edis();
}

//*****************************************************************************
//
//! Sets the Capture event polarity.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number.
//! \param polarity is the polarity of the event.
//!
//! This function sets the polarity of a given event. The value of event
//! is between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 inclusive corresponding to
//! the four available events.For each event the polarity value determines the
//! edge on which the capture is activated. For a rising edge use a polarity
//! value of \b ECAP_EVNT_RISING_EDGE and for a falling edge use a polarity of
//! \b ECAP_EVNT_FALLING_EDGE.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setEventPolarity(uint32_t base,
                                         ECAP_Events event,
                                         ECAP_EventPolarity polarity)
{

    uint16_t shift;

    ;

    shift = ((uint16_t)event) << 1U;

    __eallow();

    //
    // Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) =
                         ((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) & ~(1U << shift)) |
                         ((uint16_t)polarity << shift);
    __edis();
}

//*****************************************************************************
//
//! Sets the capture mode.
//!
//! \param base is the base address of the ECAP module.
//! \param mode is the capture mode.
//! \param event is the event number at which the counter stops or wraps.
//!
//! This function sets the eCAP module to a continuous or one-shot mode.
//! The value of mode should be either \b ECAP_CONTINUOUS_CAPTURE_MODE or
//! \b ECAP_ONE_SHOT_CAPTURE_MODE corresponding to continuous or one-shot mode
//! respectively.
//!
//! The value of event determines the event number at which the counter stops
//! (in one-shot mode) or the counter wraps (in continuous mode). The value of
//! event should be between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 corresponding
//! to the valid event numbers.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setCaptureMode(uint32_t base,
                                       ECAP_CaptureMode mode,
                                       ECAP_Events event)
{
    ;

    __eallow();

    //
    // Write to CONT/ONESHT
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) =
               (((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) & (~0x1U)) |
                (uint16_t)mode);

    //
    // Write to STOP_WRAP
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) =
               (((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) & (~0x6U)) |
                (((uint16_t)event) << 1U ));
    __edis();
}

//*****************************************************************************
//
//! Re-arms the eCAP module.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function re-arms the eCAP module.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_reArm(uint32_t base)
{
    ;

    __eallow();

    //
    // Write to RE-ARM bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x8U;
    __edis();
}

//*****************************************************************************
//
//! Enables interrupt source.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source to be enabled.
//!
//! This function sets and enables eCAP interrupt source. The following are
//! valid interrupt sources.
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_PERIOD   - Counter equal period generates
//!                                       interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_COMPARE  - Counter equal compare generates
//!                                       interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableInterrupt(uint32_t base,
                                        uint16_t intFlags)
{
    ;
    ;


    __eallow();

    //
    // Set bits in ECEINT register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) |= intFlags;
    __edis();
}

//*****************************************************************************
//
//! Disables interrupt source.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source to be disabled.
//!
//! This function clears and disables eCAP interrupt source. The following are
//! valid interrupt sources.
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_1   - Event 1 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_2   - Event 2 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_3   - Event 3 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_4   - Event 4 generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_OVERFLOW  - Counter overflow generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_PERIOD    - Counter equal period generates
//!                                        interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_COMPARE   - Counter equal compare generates
//!                                        interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableInterrupt(uint32_t base,
                                         uint16_t intFlags)
{

    ;
    ;

    __eallow();

    //
    // Clear bits in ECEINT register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) &= ~intFlags;
    __edis();
}

//*****************************************************************************
//
//! Returns the interrupt flag.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the eCAP interrupt flag. The following are valid
//! interrupt sources corresponding to the eCAP interrupt flag.
//!
//! \return Returns the eCAP interrupt that has occurred. The following are
//!  valid return values.
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_1   - Event 1 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_2   - Event 2 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_3   - Event 3 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_4   - Event 4 generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_OVERFLOW  - Counter overflow generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_PERIOD    - Counter equal period generates
//!                                        interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_COMPARE   - Counter equal compare generates
//!                                        interrupt
//!
//! \note - User can check if a combination of various interrupts have occurred
//!         by ORing the above return values.
//
//*****************************************************************************
static inline uint16_t ECAP_getInterruptSource(uint32_t base)
{
    ;

    //
    // Return contents of ECFLG register
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) & 0xFEU);
}

//*****************************************************************************
//
//! Returns the Global interrupt flag.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the eCAP Global interrupt flag.
//!
//! \return Returns true if there is a global eCAP interrupt, false otherwise.
//
//*****************************************************************************
static inline _Bool ECAP_getGlobalInterruptStatus(uint32_t base)
{
    ;

    //
    // Return contents of Global interrupt bit
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) & 0x1U) == 0x1U);
}

//*****************************************************************************
//
//! Clears interrupt flag.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source.
//!
//! This function clears eCAP interrupt flags. The following are valid
//! interrupt sources.
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_PERIOD   - Counter equal period generates
//!                                       interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_COMPARE  - Counter equal compare generates
//!                                       interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_clearInterrupt(uint32_t base,
                                       uint16_t intFlags)
{
    ;
    ;

    //
    // Write to ECCLR register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) = intFlags;
}

//*****************************************************************************
//
//! Clears global interrupt flag
//!
//! \param base is the base address of the ECAP module.
//!
//! This function clears the global interrupt bit.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_clearGlobalInterrupt(uint32_t base)
{
    ;

    //
    // Write to INT bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) = 0x1U;
}

//*****************************************************************************
//
//! Forces interrupt source.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source.
//!
//! This function forces and enables eCAP interrupt source. The following are
//! valid interrupt sources.
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//!  - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_PERIOD   - Counter equal period generates
//!                                       interrupt
//!  - ECAP_ISR_SOURCE_COUNTER_COMPARE  - Counter equal compare generates
//!                                       interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_forceInterrupt(uint32_t base,
                                       uint16_t intFlags)
{
    ;
    ;

    __eallow();

    //
    // Write to ECFRC register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x19U)))) = intFlags;
    __edis();
}

//*****************************************************************************
//
//! Sets eCAP in Capture mode.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function sets the eCAP module to operate in Capture mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableCaptureMode(uint32_t base)
{
    ;

    __eallow();

    //
    // Clear CAP/APWM bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &= ~0x200U;
    __edis();
}

//*****************************************************************************
//
//! Sets eCAP in APWM mode.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function sets the eCAP module to operate in APWM mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableAPWMMode(uint32_t base)
{
    ;

    __eallow();

    //
    // Set CAP/APWM bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x200U;
    __edis();
}

//*****************************************************************************
//
//! Enables counter reset on an event.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number the time base gets reset.
//!
//! This function enables the base timer, TSCTR, to be reset on capture
//! event provided by the variable event. Valid inputs for event are
//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableCounterResetOnEvent(uint32_t base,
                                                  ECAP_Events event)
{
    ;

    __eallow();

    //
    // Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= 1U << ((2U * (uint16_t)event) + 1U);
    __edis();
}

//*****************************************************************************
//
//! Disables counter reset on events.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number the time base gets reset.
//!
//! This function disables the base timer, TSCTR, from being reset on capture
//! event provided by the variable event. Valid inputs for event are
//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableCounterResetOnEvent(uint32_t base,
                                                   ECAP_Events event)
{
    ;
    ;

    __eallow();

    //
    // Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &= ~(1U << ((2U * (uint16_t)event) + 1U));
    __edis();
}

//*****************************************************************************
//
//! Enables time stamp capture.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function enables time stamp count to be captured
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableTimeStampCapture(uint32_t base)
{
    ;

    __eallow();

    //
    // Set CAPLDEN bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= 0x100U;
    __edis();
}

//*****************************************************************************
//
//! Disables time stamp capture.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function disables time stamp count to be captured
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableTimeStampCapture(uint32_t base)
{
    ;

    __eallow();

    //
    // Clear CAPLDEN bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &= ~0x100U;
    __edis();
}

//*****************************************************************************
//
//! Sets a phase shift value count.
//!
//! \param base is the base address of the ECAP module.
//! \param shiftCount is the phase shift value.
//!
//! This function writes a phase shift value to be loaded into the main time
//! stamp counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount)
{
    ;

    //
    // Write to CTRPHS
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) = shiftCount;
}

//*****************************************************************************
//
//! Set up the source for sync-in pulse.
//!
//! \param base is the base address of the ECAP module.
//! \param source is the sync-in pulse source.
//!
//! This function set the sync out pulse mode.
//! Valid values for mode are:
//!  - ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWMx - sync-in pulse source can be
//!                                           any of the EPWMx sync-out
//!                                           signal
//!  - ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAPx - sync-in pulse source can be
//!                                           selected as any of the ECAPx
//!                                           sync-out signal
//!  - ECAP_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT5-6 - sync-in pulse source can be
//!                                              selected as any of the Input
//!                                              xbar out5-6 signal
//!  - ECAP_SYNC_IN_PULSE_SRC_DISABLE - sync-in pulse is disabled for the
//!                                     ECAP module
//!
//! \return None.
//
//*****************************************************************************
static inline void
ECAP_setSyncInPulseSource(uint32_t base, ECAP_SyncInPulseSource source)
{
    ;

    __eallow();

    //
    // Set ECAP Sync-In Source Mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) =
            ((*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) & (~0x1FU)) |
            ((uint16_t)source & 0x1FU);

    __edis();
}

//*****************************************************************************
//
//! Enable counter loading with phase shift value.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function enables loading of the counter with the value present in the
//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableLoadCounter(uint32_t base)
{

    ;

    __eallow();

    //
    // Write to SYNCI_EN
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x20U;
    __edis();
}

//*****************************************************************************
//
//! Disable counter loading with phase shift value.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function disables loading of the counter with the value present in the
//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableLoadCounter(uint32_t base)
{

    ;

    __eallow();

    //
    // Write to SYNCI_EN
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &= ~0x20U;
    __edis();
}

//*****************************************************************************
//
//! Load time stamp counter
//!
//! \param base is the base address of the ECAP module.
//!
//! This function forces the value in the phase shift counter register to be
//! loaded into Time stamp counter register.
//! Make sure to enable loading of Time stamp counter by calling
//! ECAP_enableLoadCounter() function before calling this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_loadCounter(uint32_t base)
{
    ;

    __eallow();

    //
    // Write to SWSYNC
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x100U;
    __edis();
}

//*****************************************************************************
//
//! Configures Sync out signal mode.
//!
//! \param base is the base address of the ECAP module.
//! \param mode is the sync out mode.
//!
//! This function sets the sync out mode. Valid parameters for mode are:
//! - ECAP_SYNC_OUT_SYNCI - Trigger sync out on sync-in event.
//! - ECAP_SYNC_OUT_COUNTER_PRD - Trigger sync out when counter equals period.
//! - ECAP_SYNC_OUT_DISABLED - Disable sync out.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setSyncOutMode(uint32_t base,
                                       ECAP_SyncOutMode mode)
{
    ;

    __eallow();

    //
    // Write to SYNCO_SEL
    //
     (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) & (~0xC0U)) |
                 (uint16_t)mode);
    __edis();
}

//*****************************************************************************
//
//! Stops Time stamp counter.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function stops the time stamp counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_stopCounter(uint32_t base)
{
    ;

    __eallow();

    //
    // Clear TSCTR
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &= ~0x10U;
    __edis();
}

//*****************************************************************************
//
//! Starts Time stamp counter.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function starts the time stamp counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_startCounter(uint32_t base)
{
    ;

    __eallow();

    //
    // Set TSCTR
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x10U;
    __edis();
}

//*****************************************************************************
//
//! Set eCAP APWM polarity.
//!
//! \param base is the base address of the ECAP module.
//! \param polarity is the polarity of APWM
//!
//! This function sets the polarity of the eCAP in APWM mode. Valid inputs for
//! polarity are:
//!  - ECAP_APWM_ACTIVE_HIGH - For active high.
//!  - ECAP_APWM_ACTIVE_LOW - For active low.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMPolarity(uint32_t base,
                                        ECAP_APWMPolarity polarity)
{
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) =
               (((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) & ~0x400U) |
                (uint16_t)polarity);
    __edis();
}

//*****************************************************************************
//
//! Set eCAP APWM period.
//!
//! \param base is the base address of the ECAP module.
//! \param periodCount is the period count for APWM.
//!
//! This function sets the period count of the APWM waveform.
//! periodCount takes the actual count which is written to the register. The
//! user is responsible for converting the desired frequency or time into
//! the period count.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount)
{
    ;

    //
    // Write to CAP1
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) = periodCount;
}

//*****************************************************************************
//
//! Set eCAP APWM on or off time count.
//!
//! \param base is the base address of the ECAP module.
//! \param compareCount is the on or off count for APWM.
//!
//! This function sets the on or off time count of the APWM waveform depending
//! on the polarity of the output. If the output , as set by
//! ECAP_setAPWMPolarity(), is active high then compareCount determines the on
//! time. If the output is active low then compareCount determines the off
//! time. compareCount takes the actual count which is written to the register.
//! The user is responsible for converting the desired frequency or time into
//! the appropriate count value.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount)
{
    ;

    //
    // Write to CAP2
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x6U)))) = compareCount;
}

//*****************************************************************************
//
//! Load eCAP APWM shadow period.
//!
//! \param base is the base address of the ECAP module.
//! \param periodCount is the shadow period count for APWM.
//!
//! This function sets the shadow period count of the APWM waveform.
//! periodCount takes the actual count which is written to the register. The
//! user is responsible for converting the desired frequency or time into
//! the period count.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMShadowPeriod(uint32_t base,
                                            uint32_t periodCount)
{
    ;

    //
    // Write to CAP3
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x8U)))) = periodCount;
}

//*****************************************************************************
//
//! Set eCAP APWM shadow on or off time count.
//!
//! \param base is the base address of the ECAP module.
//! \param compareCount is the on or off count for APWM.
//!
//! This function sets the shadow on or off time count of the APWM waveform
//! depending on the polarity of the output. If the output , as set by
//! ECAP_setAPWMPolarity() , is active high then compareCount determines the
//! on time. If the output is active low then compareCount determines the off
//! time. compareCount takes the actual count which is written to the register.
//! The user is responsible for converting the desired frequency or time into
//! the appropriate count value.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMShadowCompare(uint32_t base,
                                             uint32_t compareCount)
{
    ;

    //
    // Write to CAP4
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))) = compareCount;
}

//*****************************************************************************
//
//! Returns the time base counter value.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the time base counter value.
//!
//! \return Returns the time base counter value.
//
//*****************************************************************************
static inline uint32_t ECAP_getTimeBaseCounter(uint32_t base)
{
    ;

    //
    // Read the Time base counter value
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))));
}

//*****************************************************************************
//
//! Returns event time stamp.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number.
//!
//! This function returns the current time stamp count of the given event.
//! Valid values for event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return Event time stamp value or 0 if \e event is invalid.
//
//*****************************************************************************
static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event)
{
    uint32_t count;

    ;


    switch(event)
    {
        case ECAP_EVENT_1:

            //
            // Read CAP1 register
            //
            count = (*((volatile uint32_t *)((uintptr_t)(base + 0x4U))));
        break;

        case ECAP_EVENT_2:
            //
            // Read CAP2 register
            //
            count = (*((volatile uint32_t *)((uintptr_t)(base + 0x6U))));
        break;

        case ECAP_EVENT_3:

            //
            // Read CAP3 register
            //
            count = (*((volatile uint32_t *)((uintptr_t)(base + 0x8U))));
        break;

        case ECAP_EVENT_4:

            //
            // Read CAP4 register
            //
            count = (*((volatile uint32_t *)((uintptr_t)(base + 0xAU))));
        break;

        default:

            //
            // Invalid event parameter
            //
            count = 0U;
        break;
    }

    return(count);
}

//*****************************************************************************
//
//! Select eCAP input.
//!
//! \param base is the base address of the ECAP module.
//! \param input is the eCAP input signal.
//!
//! This function selects the eCAP input signal.
//!
//! Please refer to the ::ECAP_InputCaptureSignals Enum for the valid values
//! to be passed to \e input parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_selectECAPInput(uint32_t base,
                                        ECAP_InputCaptureSignals input)
{
    ;

    __eallow();

    //
    // Write to ECCTL0
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x12U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0x12U)))) & ~0x7FU) |
                 (uint16_t)input);
    __edis();
}

//*****************************************************************************
//
//! Resets eCAP counters and flags.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function resets the main counter (TSCTR register), event filter,
//! modulo counter, capture events and counter overflow flags
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_resetCounters(uint32_t base)
{
    ;

    __eallow();

    //
    // Write to ECCTL2
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x800U;
    __edis();
}

//*****************************************************************************
//
//! Sets the eCAP DMA source.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the eCAP event for the DMA
//!
//! This function sets the eCAP event source for the DMA trigger.
//! Valid values for \e event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setDMASource(uint32_t base, ECAP_Events event)
{
    ;

    __eallow();

    //
    // Write to ECCTL2
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) =
               (((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) & ~0x3000U) |
                ((uint16_t)event << 12U));
    __edis();
}

//*****************************************************************************
//
//! Return the Modulo counter status.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the modulo counter status, indicating which register
//! gets loaded on the next capture event.
//!
//! \return Returns an \b ECAP_EVENT_n value indicating that CAPn is the
//! register to be loaded on the next event.
//
//*****************************************************************************
static inline ECAP_Events ECAP_getModuloCounterStatus(uint32_t base)
{
    uint16_t counterStatusValue;

    ;

    counterStatusValue = ((((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &
                          0xC000U) >>
                         14U));

    //
    // Read MODCNTRSTS bit
    //
    return((ECAP_Events)(counterStatusValue));
}

//*****************************************************************************
//
//! Configures emulation mode.
//!
//! \param base is the base address of the ECAP module.
//! \param mode is the emulation mode.
//!
//! This function configures the eCAP counter, TSCTR,  to the desired emulation
//! mode when emulation suspension occurs. Valid inputs for mode are:
//! - ECAP_EMULATION_STOP  - Counter is stopped immediately.
//! - ECAP_EMULATION_RUN_TO_ZERO - Counter runs till it reaches 0.
//! - ECAP_EMULATION_FREE_RUN - Counter is not affected.
//!
//! \return None.
//
//*****************************************************************************
extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   epg.h
//
// TITLE:  C28x EPG driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################



//###########################################################################
//
// FILE:    hw_epg.h
//
// TITLE:   Definitions for the EPG registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the EPG register offsets
//
//*************************************************************************************************



//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL2 register
//
//*************************************************************************************************
                                                      // output 0.
                                                      // output 1.
                                                      // output 2.
                                                      // output 3.
                                                      // output 4.
                                                      // output 5.
                                                      // output 6.
                                                      // output 7.

//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGCOMMIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTSTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV0_CTL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV0_CLKOFFSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV1_CTL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV1_CLKOFFSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SIGGEN0_CTL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SIGGEN0_CTL1 register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGMXSEL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGMXSELLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGMXSELCOMMIT register
//
//*************************************************************************************************




//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to EPG_selectGlobalOutput() as the \e gPinOutSel
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_OUT_SEL_SIG = 0x0U,    //!< Signal Generator mux output
    EPG_OUT_SEL_CLK = 0x1U     //!< Clock Generator mux output
} EPG_OutputSelect;

//*****************************************************************************
//
//! Values that can be passed to EPG_selectSignalOutput() as the
//! \e sigGenOutput parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_SIGGEN0_DATATRANOUT0 = 0x0U, //!< Signal Generator 0 Data Transform out 0
    EPG_SIGGEN0_DATATRANOUT1 = 0x1U, //!< Signal Generator 0 Data Transform out 1
    EPG_SIGGEN0_DATATRANOUT2 = 0x2U, //!< Signal Generator 0 Data Transform out 2
    EPG_SIGGEN0_DATATRANOUT3 = 0x3U, //!< Signal Generator 0 Data Transform out 3
    EPG_SIGGEN0_DATATRANOUT4 = 0x4U, //!< Signal Generator 0 Data Transform out 4
    EPG_SIGGEN0_DATATRANOUT5 = 0x5U, //!< Signal Generator 0 Data Transform out 5
    EPG_SIGGEN0_DATATRANOUT6 = 0x6U, //!< Signal Generator 0 Data Transform out 6
    EPG_SIGGEN0_DATATRANOUT7 = 0x7U, //!< Signal Generator 0 Data Transform out 7
} EPG_SignalGenOut;

//*****************************************************************************
//
//! Values that can be passed to EPG_selectClkOutput()
//! as the \e clkGenOutput parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_CLKGEN0_CLKOUT0_DCLK = 0x0U, //!< Clock Generator 0 Clk output 0 DCLK
    EPG_CLKGEN0_CLKOUT1_DCLK = 0x1U, //!< Clock Generator 0 Clk output 1 DCLK
    EPG_CLKGEN0_CLKOUT2_DCLK = 0x2U, //!< Clock Generator 0 Clk output 2 DCLK
    EPG_CLKGEN0_CLKOUT3_DCLK = 0x3U, //!< Clock Generator 0 Clk output 3 DCLK
    EPG_CLKGEN1_CLKOUT0_DCLK = 0x4U, //!< Clock Generator 1 Clk output 0 DCLK
    EPG_CLKGEN1_CLKOUT1_DCLK = 0x5U, //!< Clock Generator 1 Clk output 1 DCLK
    EPG_CLKGEN1_CLKOUT2_DCLK = 0x6U, //!< Clock Generator 1 Clk output 2 DCLK
    EPG_CLKGEN1_CLKOUT3_DCLK = 0x7U, //!< Clock Generator 1 Clk output 3 DCLK
} EPG_ClockGenOut;

//*****************************************************************************
//
//! Values that can be passed to EPG_selectSigGenClkSource()
//! as the \e clkGenOutput parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_CLKGEN0_CLKOUT0_GCLK = 0x0U, //!< Clock Generator 0 Clk output 0 GCLK
    EPG_CLKGEN0_CLKOUT1_GCLK = 0x1U, //!< Clock Generator 0 Clk output 1 GCLK
    EPG_CLKGEN0_CLKOUT2_GCLK = 0x2U, //!< Clock Generator 0 Clk output 2 GCLK
    EPG_CLKGEN0_CLKOUT3_GCLK = 0x3U, //!< Clock Generator 0 Clk output 3 GCLK
    EPG_CLKGEN1_CLKOUT0_GCLK = 0x4U, //!< Clock Generator 1 Clk output 0 GCLK
    EPG_CLKGEN1_CLKOUT1_GCLK = 0x5U, //!< Clock Generator 1 Clk output 1 GCLK
    EPG_CLKGEN1_CLKOUT2_GCLK = 0x6U, //!< Clock Generator 1 Clk output 2 GCLK
    EPG_CLKGEN1_CLKOUT3_GCLK = 0x7U, //!< Clock Generator 1 Clk output 3 GCLK
} EPG_ClockGenGclkOut;

//*****************************************************************************
//
//! Values that can be passed to EPG_setClkGenStopEdge(),
//! as the \e stopEdge parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_CLK_STOP_EDGE_CLKOUT0 = 0x000U,    //!< Stop on Clk output 0
    EPG_CLK_STOP_EDGE_CLKOUT1 = 0x010U,    //!< Stop on Clk output 1
    EPG_CLK_STOP_EDGE_CLKOUT2 = 0x100U,    //!< Stop on Clk output 2
    EPG_CLK_STOP_EDGE_CLKOUT3 = 0x110U,    //!< Stop on Clk output 3
} EPG_ClockStopEdge;

//*****************************************************************************
//
//! Values that can be passed to EPG_setSignalGenMode(),
//! as the \e sigGenMode parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_SIGGEN_MODE_BIT_BANG            = 0x0U,    //!< BIT BANG MODE
    EPG_SIGGEN_MODE_SHIFT_RIGHT_ONCE    = 0x1U,    //!< SHIFT RIGHT ONCE MODE
    EPG_SIGGEN_MODE_ROTATE_RIGHT_ONCE   = 0x2U,    //!< ROTATE RIGHT ONCE MODE
    EPG_SIGGEN_MODE_ROTATE_RIGHT_REPEAT = 0x3U,    //!< ROTATE RIGHT REPEAT MODE
    EPG_SIGGEN_MODE_SHIFT_LEFT_ONCE     = 0x4U,    //!< SHIFT LEFT ONCE MODE
    EPG_SIGGEN_MODE_ROTATE_LEFT_ONCE    = 0x5U,    //!< ROTATE LEFT ONCE MODE
    EPG_SIGGEN_MODE_ROTATE_LEFT_REPEAT  = 0x6U,    //!< ROTATE LEFT REPEAT
    EPG_SIGGEN_MODE_SHIFT_RIGHT_REPEAT  = 0x7U,    //!< SHIFT RIGHT REPEAT MODE
    EPG_SIGGEN_MODE_SHIFT_LEFT_REPEAT   = 0x8U,    //!< SHIGT LEFT REPEAT MODE
} EPG_SignalGenMode;

//*****************************************************************************
//
//! Values that can be passed to EPG_setData0In(),
//! as the \e data0Input parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_SIGGEN_DATA0_DATA_NEXT0 = 0x0U,    //!< DATA TRANSFORM NEXT[0]
    EPG_SIGGEN_DATA0_EPGIN0     = 0x1U,    //!< EPG Input 0
    EPG_SIGGEN_DATA0_EPGIN1     = 0x2U,    //!< EPG Input 1
    EPG_SIGGEN_DATA0_EPGIN2     = 0x3U,    //!< EPG Input 2
    EPG_SIGGEN_DATA0_EPGIN3     = 0x4U,    //!< EPG Input 3
    EPG_SIGGEN_DATA0_EPGIN4     = 0x5U,    //!< EPG Input 4
    EPG_SIGGEN_DATA0_EPGIN5     = 0x6U,    //!< EPG Input 5
    EPG_SIGGEN_DATA0_EPGIN6     = 0x7U,    //!< EPG Input 6
    EPG_SIGGEN_DATA0_EPGIN7     = 0x8U,    //!< EPG Input 7
} EPG_SignalGenData0In;

//*****************************************************************************
//
//! Values that can be passed to EPG_setData63In(),
//! as the \e data63Input parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_SIGGEN_DATA63_DATA_NEXT63   = 0x0U,    //!< DATA TRANSFORM NEXT[63]
    EPG_SIGGEN_DATA63_EPGIN0        = 0x1U,    //!< EPG Input 0
    EPG_SIGGEN_DATA63_EPGIN1        = 0x2U,    //!< EPG Input 1
    EPG_SIGGEN_DATA63_EPGIN2        = 0x3U,    //!< EPG Input 2
    EPG_SIGGEN_DATA63_EPGIN3        = 0x4U,    //!< EPG Input 3
    EPG_SIGGEN_DATA63_EPGIN4        = 0x5U,    //!< EPG Input 4
    EPG_SIGGEN_DATA63_EPGIN5        = 0x6U,    //!< EPG Input 5
    EPG_SIGGEN_DATA63_EPGIN6        = 0x7U,    //!< EPG Input 6
    EPG_SIGGEN_DATA63_EPGIN7        = 0x8U,    //!< EPG Input 7
} EPG_SignalGenData63In;

//*****************************************************************************
//
//! Values that can be passed to EPG_selectEPGOutput(), EPG_selectClkOutput,
//! EPG_selectSignalOutput as the \e gPinNum parameter.
//
//*****************************************************************************
typedef enum
{
	EPG_OUT0 = 0x0U,    //!< EPG Output 0
	EPG_OUT1 = 0x1U,    //!< EPG Output 1
	EPG_OUT2 = 0x2U,    //!< EPG Output 2
	EPG_OUT3 = 0x3U,    //!< EPG Output 3
	EPG_OUT4 = 0x4U,    //!< EPG Output 4
	EPG_OUT5 = 0x5U,    //!< EPG Output 5
	EPG_OUT6 = 0x6U,    //!< EPG Output 6
} EPG_OUT;

//*****************************************************************************
//
//! Values that can be used for \e sigGenNum parameter.
//
//*****************************************************************************
typedef enum
{
	EPG_SIGGEN0 = 0x0U,    //!< Signal Generator 0
} EPG_SIGGEN;

//*****************************************************************************
//
//! Values that can be used for \e clkGenNum parameter.
//
//*****************************************************************************
typedef enum
{
    EPG_CLKGEN0 = 0x0U,    //!< Clock Generator 0
    EPG_CLKGEN1 = 0x1U,    //<! Clock Generator 1
} EPG_CLKGEN;

//*****************************************************************************
//
//! Values that can be passed to EPG_selectEPGDataOut(),
//! as the \e dataIn parameter.
//
//*****************************************************************************
typedef enum{
    EPG_DATAIN_CANARX = 0,    //!< CANA Receive input (RX)
    EPG_DATAIN_MCANARX = 1,   //!< MCANA Receive input (RX)
    EPG_DATAIN_SD1C1 = 19,    //!< SDFM1 C1 input
    EPG_DATAIN_SD1C2 = 20,    //!< SDFM1 C2 input
    EPG_DATAIN_SD1C3 = 21,    //!< SDFM1 C3 input
    EPG_DATAIN_SD1C4 = 22,    //!< SDFM1 C4 input
    EPG_DATAIN_SD2C1 = 23,    //!< SDFM2 C1 input
    EPG_DATAIN_SD2C2 = 24,    //!< SDFM2 C2 input
    EPG_DATAIN_SD2C3 = 25,    //!< SDFM2 C3 input
    EPG_DATAIN_SD2C4 = 26,    //!< SDFM2 C4 input
} EPG_DataIn;

//*****************************************************************************
//
//! Interrupt Flags that can be passed to EPG_enableInterruptFlag(),
//! EPG_diableInterruptFlag, EPG_forceInterruptFlag, EPG_clearInterruptFlag
//! as \e intFlags parameter.
//
//*****************************************************************************

//*****************************************************************************
//
//! Register Flags that can be passed to EPG_releaseLockReg,
//! EPG_LockReg, EPG_commitRegLock as \e regFlags parameter.
//
//*****************************************************************************

//*****************************************************************************
//
//! Register Flags that can be passed to EPG_releaseLockMXSelReg,
//! EPG_lockMXSelReg, EPG_commitMXSelRegLock as \e regFlags parameter.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to EPG_selectEPGDataOut(),
//! as the \e dataOutSel parameter.
//
//*****************************************************************************
typedef enum
{
   EPG_DATAOUT_DATAIN  = 0x0U,    //!< Input Data
   EPG_DATAOUT_EPGOUT  = 0x1U,    //!< EPG output
} EPG_DataOutSel;

//*****************************************************************************
//
//! \internal
//! Check a EPG base address.
//!
//! \param base is the base address of the EPG.
//!
//! This function determines if a EPG base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! \internal
//! Check a EPGMUX base address.
//!
//! \param muxbase is the base address of the EPG MUX.
//!
//! This function determines if EPGMUX base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enable EPG and starts signal and clock generator
//!
//! \param base is the base address of the EPG module.
//!
//! This function enables the EPG module and starts signal and clock generator.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_enableGlobal(uint32_t base)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Disable EPG and stops signal and clock generator
//!
//! \param base is the base address of the EPG module.
//!
//! This function disables the EPG module and stops signal and clock generator.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_disableGlobal(uint32_t base)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) &= ~(uint32_t)0x1U;
}

//*****************************************************************************
//
//! Select the EPG output source
//!
//! \param base is the base address of the EPG module.
//! \param gPinNum is the global EPG Output number.
//! \param gPinOutSel is the mux output of the \e gPinNum.
//!
//! This function selects the global EPG output source to be clock or signal.
//! This output can then be routed to any GPIO through xbar, mux sel.
//!
//! The \e gPinNum can take any of EPG_OUTX. The \e gPinOutSel can
//! take any of the EPG_OUT_SEL_CLK, EPG_OUT_SEL_SIG values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_selectEPGOutput(uint32_t base, EPG_OUT gPinNum,
                       EPG_OutputSelect gPinOutSel)
{
    uint32_t regValue, bitFieldLoc, bitFieldVal;

    ;
    ;

    bitFieldLoc = 1U << (gPinNum + 8U);
    bitFieldVal = (uint32_t)gPinOutSel << (gPinNum + 8U);

    regValue = ((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) & (~bitFieldLoc));
    regValue |= bitFieldVal;

    (*((volatile uint32_t *)((uintptr_t)((base + 0x0U))))) = regValue;
}

//*****************************************************************************
//
//! Select the individual EPG pin signal data output
//!
//! \param base is the base address of the EPG module.
//! \param gPinNum is the global EPG Output number.
//! \param sigGenOutput is the mux output of the \e gPinNum signal generators
//!        data output.
//!
//! This function selects the individual EPG pin's signal generator data output.
//! This output can then be routed to EPG global output by selecting signal
//! generator as source for that pin.
//!
//! The \e gPinNum can take any of EPG_OUTX. The \e sigGenOutput
//! can take any of the EPG_SIG_GEN0_DATATRANX values where X is a number
//! from 0 to 7 specifying which data ouput of sig gen to be used.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_selectSignalOutput(uint32_t base, EPG_OUT gPinNum,
                       EPG_SignalGenOut sigGenOutput)
{
    uint32_t regValue, bitFieldLoc, bitFieldVal;

    ;
    ;

    bitFieldLoc = 0xFU <<
                  (gPinNum * 4U);

    bitFieldVal = (uint32_t)sigGenOutput <<
                  (gPinNum * 4U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + 0x6U)))) & ~bitFieldLoc;
    regValue |= bitFieldVal;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x6U)))) = regValue;
}

//*****************************************************************************
//
//! Select the individual EPG pin clock data output
//!
//! \param base is the base address of the EPG module.
//! \param gPinNum is the global EPG Output number.
//! \param clkGenOutput is the mux output of the \e gPinNum clock generator's
//!        data output.
//!
//! This function selects the individual EPG pin's clock generator data output.
//! This output can then be routed to EPG global output by selecting clock
//! generator as source for that pin.
//!
//! The \e gPinNum can take any of EPG_OUTX.
//! The \e clkGenOutput can take any of the EPG_CLK_GENY_CLKOUTX_DCLK values
//! where X is a number from 0 to 3 specifying which data ouput of clock gen
//! and Y can be 0 or 1 specifying which clock generator to be used to be used
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_selectClkOutput(uint32_t base, EPG_OUT gPinNum,
                    EPG_ClockGenOut clkGenOutput)
{
    uint32_t regValue, bitFieldLoc, bitFieldVal;

    ;
    ;

    bitFieldLoc = 0x7U <<
                  (gPinNum * 4U);

    bitFieldVal = (uint32_t)clkGenOutput <<
                  (gPinNum * 4U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) & ~bitFieldLoc;
    regValue |= bitFieldVal;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) = regValue;
}

//*****************************************************************************
//
//! Select the signal generator's clock source
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number whose clk source is being
//!        configured based on the availability.
//! \param clkGenOutput is the mux output of the clock generator's data
//!        output to be selected as source.
//!
//! This function selects the signal generator's clock source.
//! This clock source is used to generate the periodic or aperiodic signals by
//! the signal generator.
//!
//! The \e sigGenNum can take value of 0.
//! The \e clkGenOutput can take any of the EPG_CLK_GENY_CLKOUTX_DCLK values
//! where X is a number from 0 to 3 specifying which data ouput of clock gen
//! to be used and Y can be 0 or 1 specifying which clock generator to be used
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_selectSigGenClkSource(uint32_t base, EPG_SIGGEN sigGenNum,
                          EPG_ClockGenGclkOut clkGenOutput)
{
    uint32_t regValue, bitFieldLoc, bitFieldVal;

    ;
    ;

    bitFieldLoc = 0x7U <<
                  (sigGenNum * 4U);

    bitFieldVal = (uint32_t)clkGenOutput <<
                  (sigGenNum * 4U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) & ~bitFieldLoc;
    regValue |= bitFieldVal;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) |= regValue;
}

//*****************************************************************************
//
//! Set the clock generator period
//!
//! \param base is the base address of the EPG module.
//! \param clkGenNum is the clock generator number whose period is being set.
//! \param periodValue is the period value in number of system clk cycles
//!
//! This function Sets the clock generator's period
//! Clock divider counter counts up to \e periodValue and snaps back to 0.
//!
//! The \e clkGenNum can take values from 0 to 1 inclusive.
//! The \e periodValue can take a maximum value of EPG_CLKDIV0_CTL0_PRD_M.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setClkGenPeriod(uint32_t base, EPG_CLKGEN clkGenNum,
                         uint32_t periodValue)
{
    uint32_t regValue, regLoc;

    ;
    ;
    ;

    regLoc = 0x18U + (clkGenNum * 12U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) & ~(uint32_t)0xFFU;
    regValue |= periodValue;

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) = regValue;
}

//*****************************************************************************
//
//! Set the clock generator stop value
//!
//! \param base is the base address of the EPG module.
//! \param clkGenNum is the clock generator number which is being configured.
//! \param stopEdge is the Edge signal at which clock stops.
//!
//! This function Sets the clock generator's stop value
//! This Determines on which of the CLKOUTs edge clock generation is stopped
//! following a clear of SIGGEN1_CTL0.EN.
//!
//! The \e clkGenNum can take values from 0 to 1 inclusive.
//! The \e stopEdge can take any of EPG_CLK_STOP_EDGE_CLKOUTX value where X
//! signifies the clock out number varying from 0 to 3 inclusive
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setClkGenStopEdge(uint32_t base, EPG_CLKGEN clkGenNum,
                      EPG_ClockStopEdge stopEdge)
{
    uint32_t regValue, regLoc;

    ;
    ;

    regLoc = 0x18U + (clkGenNum * 12U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) & ~(uint32_t)0x70000U;
    regValue |= ((uint32_t)stopEdge << 16U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) = regValue;
}

//*****************************************************************************
//
//! Set the clock generator clock offset
//!
//! \param base is the base address of the EPG module.
//! \param clkGenNum is the clock generator number which is being configured.
//! \param clkGenOutputNum is the output number of particular clock generator
//!        whose offset is being set.
//! \param offsetValue is the offset value in number of system clk cycles
//!
//! This function Sets the clock generator output's offset.
//! This Determines number of source clock cycles by which the divided clock
//! output is delayed.
//!
//! The \e clkGenNum can take values from 0 to 1 inclusive.
//! The \e clkGenOutputNum can take values from 0 to 3 inclusive.
//! The \e offsetValue can take a maximum value of
//! EPG_CLKDIV0_CLKOFFSET_CLK0OFFSET_M.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setClkGenOffset(uint32_t base, EPG_CLKGEN clkGenNum,
                    uint32_t clkGenOutputNum, uint32_t offsetValue)
{
    uint32_t regValue, regLoc, bitFieldLoc, bitFieldVal;

    ;
    ;
    ;
    ;

    bitFieldLoc = 0xFFU <<
                  (clkGenOutputNum * 8U);

    bitFieldVal = offsetValue << (clkGenOutputNum * 8U);

    regLoc = 0x1EU + (clkGenNum  * 12U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) & ~bitFieldLoc;
    regValue |= bitFieldVal;

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) = regValue;
}

//*****************************************************************************
//
//! Enable EPG signal generator
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is enabled.
//!
//! This function enables the Signal generator after which the signal generator
//! functions as per the mode definition.
//!
//! The \e sigGenNum can take value of 0.
//! \return None.
//
//*****************************************************************************
static inline void
EPG_enableSignalGen(uint32_t base, EPG_SIGGEN sigGenNum)
{
    uint32_t regLoc;

    ;
    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) |= 0x10U;
}

//*****************************************************************************
//
//! Disable EPG signal generator
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is disabled.
//!
//! This function Disables the Signal generator and stops its operation.
//!
//! The \e sigGenNum can take value of 0.
//! \return None.
//
//*****************************************************************************
static inline void
EPG_disableSignalGen(uint32_t base, EPG_SIGGEN sigGenNum)
{
    uint32_t regLoc;

    ;
    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) &= ~(uint32_t)0x10U;
}

//*****************************************************************************
//
//! Set EPG signal generator Mode
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//! \param sigGenMode is the Signal generator mode being set.
//!
//! This function Sets the EPG signal generator's Mode.
//! This mode effects the operation of the signal generator on the DATA input.
//!
//! The \e sigGenNum can take value of 0.
//! The \e sigGenMode can take any of the EPG_SIGGEN_MODE_BIT_BANG,
//! EPG_SIGGEN_MODE_SHIFT_RIGHT_ONCE, EPG_SIGGEN_MODE_ROTATE_RIGHT_ONCE,
//! EPG_SIGGEN_MODE_ROTATE_RIGHT_REPEAT, EPG_SIGGEN_MODE_SHIFT_LEFT_ONCE,
//! EPG_SIGGEN_MODE_ROTATE_LEFT_ONCE, EPG_SIGGEN_MODE_ROTATE_LEFT_REPEAT,
//! EPG_SIGGEN_MODE_SHIFT_RIGHT_REPEAT, EPG_SIGGEN_MODE_SHIFT_LEFT_REPEAT
//! values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setSignalGenMode(uint32_t base, EPG_SIGGEN sigGenNum,
                     EPG_SignalGenMode sigGenMode)
{
    uint32_t regValue, regLoc;

    ;
    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) & ~(uint32_t)0xFU;
    regValue |= (uint32_t)sigGenMode << 0U;

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) = regValue;
}

//*****************************************************************************
//
//! Perform bit reversal on input of signal generator
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//!
//! This function set's signal generator to Perform bit reversal on input.
//! This results in bit reversal on data input of data transform block.
//!
//! The \e sigGenNum can take value of 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_enableBitRevOnDataIn(uint32_t base, EPG_SIGGEN sigGenNum)
{
    uint32_t regLoc;

    ;
    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) |= 0x20U;
}

//*****************************************************************************
//
//! Disable bit reversal on input of signal generator
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//!
//! This function set's signal generator to disable bit reversal on input.
//! This results in no bit reversal on data input of data transform block.
//!
//! The \e sigGenNum can take value of 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_disableBitRevOnDataIn(uint32_t base, EPG_SIGGEN sigGenNum)
{
    uint32_t regLoc;

    ;
    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) &= ~(uint32_t)0x20U;
}

//*****************************************************************************
//
//! Perform bit reversal on output of signal generator
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//!
//! This function set's signal generator to Perform bit reversal on output.
//! This results in bit reversal on data output of data transform block.
//!
//! The \e sigGenNum can take value of 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_enableBitRevOnDataOut(uint32_t base, EPG_SIGGEN sigGenNum)
{
    uint32_t regLoc;

    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) |= 0x40U;
}

//*****************************************************************************
//
//! Disable bit reversal on output of signal generator
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//!
//! This function set's signal generator to disable bit reversal on output.
//! This results in no bit reversal on data output of data transform block.
//!
//! The \e sigGenNum can take value of 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_disableBitRevOnDataOut(uint32_t base, EPG_SIGGEN sigGenNum)
{
    uint32_t regLoc;

    ;
    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) &= ~(uint32_t)0x40U;
}

//*****************************************************************************
//
//! Set EPG signal generators data bit length
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//! \param bitLength is the number of bits of the signal generator input data.
//!
//! This function Sets EPG signal generators data bit length.
//! This defines the number bits which participates in the shift rotate
//! operations.
//!
//! The \e sigGenNum can take value of 0.
//! The \e bitLength can have a maximum value of 64.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setDataBitLen(uint32_t base, EPG_SIGGEN sigGenNum, uint32_t bitLength)
{
    uint32_t regValue, regLoc;

    ;
    ;
    ;

    regLoc = 0x30U + (sigGenNum * 32U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) & ~(uint32_t)0xFF0000U;
    regValue |= (bitLength << 16U);

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) = regValue;
}

//*****************************************************************************
//
//! Set EPG signal generator data bit 0 input
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//! \param data0Input is the source input of bit 0 of Data Register.
//!
//! This function Sets EPG signal generator data bit 0 input.
//! This provides the ability to capture the data.
//!
//! The \e sigGenNum can take value of 0.
//! The \e data0Input can take any of the EPG_SIGGEN_DATA0_DATA_NEXT0,
//! EPG_SIGGEN_DATA0_EPGINX values where X can be from 0 to 7 which signifies
//! signal input to the EPG.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setData0In(uint32_t base, EPG_SIGGEN sigGenNum,
               EPG_SignalGenData0In data0Input)
{
    uint32_t regValue, regLoc;

    ;
    ;

    regLoc = 0x32U + (sigGenNum * 32U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) & ~(uint32_t)0xFU;
    regValue |= (uint32_t)data0Input;

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) = regValue;
}

//*****************************************************************************
//
//! Set EPG signal generator data bit 63 input
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//! \param data0Input is the source input of bit 63 of Data Register.
//!
//! This function Sets EPG signal generator data bit 63 input.
//! This provides the ability to capture the data.
//!
//! The \e sigGenNum can take value of 0.
//! The \e data63Input can take any of the EPG_SIGGEN_DATA63_DATA_NEXT63,
//! EPG_SIGGEN_DATA63_EPGINX values where X can be from 0 to 7 which signifies
//! signal input to the EPG.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setData63In(uint32_t base, EPG_SIGGEN sigGenNum,
                EPG_SignalGenData63In data63Input)
{
    uint32_t regValue, regLoc;

    ;
    ;

    regLoc = 0x32U + (sigGenNum * 32U);

    regValue = (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) & ~(uint32_t)0xF0000000U;
    regValue |= (uint32_t)data63Input << 28U;

    (*((volatile uint32_t *)((uintptr_t)(base + regLoc)))) = regValue;
}

//*****************************************************************************
//
//! Write EPG signal generator data 0 [0:31] input
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//! \param data0 is the first 32 bits of Data Register.
//!
//! This function Writes EPG signal generator data 0 [0:31] input.
//! This is the Data used in signal bit stream.
//!
//! The \e sigGenNum can take value of 0.
//! The \e data0 can take any 32 bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setData0Word(uint32_t base, EPG_SIGGEN sigGenNum, uint32_t data0)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x38U + (sigGenNum * 32U))))) = data0;
}

//*****************************************************************************
//
//! Write EPG signal generator data 1 [32:63] input
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//! \param data0 is the last 32 bits of 63 bit Data Register.
//!
//! This function Writes EPG signal generator data 1 [32:63] input.
//! This is the Data used in signal bit stream.
//!
//! The \e sigGenNum can take value of 0.
//! The \e data1 can take any 32 bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_setData1Word(uint32_t base, EPG_SIGGEN sigGenNum, uint32_t data1)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x3AU + (sigGenNum * 32U))))) = data1;
}

//*****************************************************************************
//
//! Get EPG signal generator data 0 active register [0:31] value
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//!
//! This function Reads EPG signal generator data 0 active [0:31] value
//! which is the Data resulted from the transformation.
//!
//! The \e sigGenNum can take value of 0.
//!
//! \return Returns the Data 0 Active register value.
//
//*****************************************************************************
static inline uint32_t
EPG_getData0ActiveReg(uint32_t base, EPG_SIGGEN sigGenNum)
{
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x3CU + (sigGenNum * 32U))))));
}

//*****************************************************************************
//
//! Get EPG signal generator data 1 active register [32:64] value
//!
//! \param base is the base address of the EPG module.
//! \param sigGenNum is the Signal generator number which is beign configured.
//!
//! This function Reads EPG signal generator data 1 active [32:64] value
//! which is the Data resulted from the transformation.
//!
//! The \e sigGenNum can take value of 0.
//!
//! \return Returns the Data 1 Active register value.
//
//*****************************************************************************
static inline uint32_t
EPG_getData1ActiveReg(uint32_t base, EPG_SIGGEN sigGenNum)
{
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x3EU + (sigGenNum * 32U))))));
}

//*****************************************************************************
//
//! Enable the EPG interrupt sources
//!
//! \param base is the base address of the EPG module.
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated EPG interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter can be any of the \b EPG_INT_GLOBAL_INT,
//! \b EPG_INT_SIGGEN0_DONE, or \b EPG_INT_SIGGEN0_FILL values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_enableInterruptFlag(uint32_t base, uint32_t intFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0xEU)))) |= intFlags;
}

//*****************************************************************************
//
//! Disables the EPG interrupt sources
//!
//! \param base is the base address of the EPG module.
//! \param intFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function enables the indicated EPG interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter can be any of the \b EPG_INT_GLOBAL_INT,
//! \b EPG_INT_SIGGEN0_DONE, or \b EPG_INT_SIGGEN0_FILL values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_disableInterruptFlag(uint32_t base, uint32_t intFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0xEU)))) &= ~intFlags;
}

//*****************************************************************************
//
//! Get the EPG interrupt sources
//!
//! \param base is the base address of the EPG module.
//!
//! This function returns the EPG interrupt sources that are active.
//!
//! \return Returns the bit mask of the interrupt sources which are currently
//!         triggered.
//
//*****************************************************************************
static inline uint32_t
EPG_getInterruptStatus(uint32_t base)
{
    uint32_t status = 0U;

    ;

    status = (*((volatile uint32_t *)((uintptr_t)(base + 0xCU))));

    return(status);
}

//*****************************************************************************
//
//! Clear EPG Interrupt Sources
//!
//! \param base is the base address of the EPG module.
//! \param intFlags is a bit mask of the interrupt sources to be clear.
//!
//! This function clears the indicated EPG interrupt sources if pending.
//!
//! The \e intFlags parameter can be any of the \b EPG_INT_GLOBAL_INT,
//! \b EPG_INT_SIGGEN0_DONE, or \b EPG_INT_SIGGEN0_FILL values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_clearInterruptFlag(uint32_t base, uint32_t intFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x10U)))) = intFlags;
}

//*****************************************************************************
//
//! Force EPG Interrupt Sources
//!
//! \param base is the base address of the EPG module.
//! \param intFlags is a bit mask of the interrupt sources to be trigger.
//!
//! This function triggers the indicated EPG interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter can be any of the \b EPG_INT_GLOBAL_INT,
//! \b EPG_INT_SIGGEN0_DONE, or \b EPG_INT_SIGGEN0_FILL values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_forceInterruptFlag(uint32_t base, uint32_t intFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x12U)))) = intFlags;
}

//*****************************************************************************
//
//! Lock EPG Register
//!
//! \param base is the base address of the EPG module.
//! \param regFlags is a bit mask of the EPG registers that need to locked.
//!
//! This function Locks EPG Register from being written further.
//!
//! The \e regFlags parameter can be any of the \b EPG_LOCK_REG_GCTL0,
//! \b EPG_LOCK_REG_GCTL1, \b EPG_LOCK_REG_GCTL2 \b EPG_LOCK_REG_GCTL3,
//! \b EPG_LOCK_REG_CLKDIV0_CTL0, \b EPG_LOCK_REG_CLKDIV1_CTL0,
//! \b EPG_LOCK_REG_SIGGEN0_CTL0, \b EPG_LOCK_REG_SIGGEN0_CTL1 values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_lockReg(uint32_t base, uint32_t regFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x8U)))) |= regFlags;
}

//*****************************************************************************
//
//! Release Locks of EPG Register
//!
//! \param base is the base address of the EPG module.
//! \param regFlags is a bit mask of EPG registers whose lock to be released.
//!
//! This function Releases Locks of EPG Register so they can be overwritten.
//!
//! The \e regFlags parameter can be any of the \b EPG_LOCK_REG_GCTL0,
//! \b EPG_LOCK_REG_GCTL1, \b EPG_LOCK_REG_GCTL2 \b EPG_LOCK_REG_GCTL3,
//! \b EPG_LOCK_REG_CLKDIV0_CTL0, \b EPG_LOCK_REG_CLKDIV1_CTL0,
//! \b EPG_LOCK_REG_SIGGEN0_CTL0, \b EPG_LOCK_REG_SIGGEN0_CTL1 values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_releaseLockReg(uint32_t base, uint32_t regFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x8U)))) &= ~regFlags;
}

//*****************************************************************************
//
//! Commit EPG registers Lock
//!
//! \param base is the base address of the EPG module.
//! \param regFlags is a bit mask of EPG registers whose locks to be commited.
//!
//! This function Commits Locks of EPG lock register so that the EPG locks
//! cannot be removed.
//!
//! The \e regFlags parameter can be any of the \b EPG_LOCK_REG_GCTL0,
//! \b EPG_LOCK_REG_GCTL1, \b EPG_LOCK_REG_GCTL2 \b EPG_LOCK_REG_GCTL3,
//! \b EPG_LOCK_REG_CLKDIV0_CTL0, \b EPG_LOCK_REG_CLKDIV1_CTL0,
//! \b EPG_LOCK_REG_SIGGEN0_CTL0, \b EPG_LOCK_REG_SIGGEN0_CTL1 values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_commitRegLock(uint32_t base, uint32_t regFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))) |= regFlags;
}

//*****************************************************************************
//
//! Lock EPG Mux Select Register
//!
//! \param muxbase is the base address of the EPG Mux module.
//! \param regFlags is a bit mask of the EPG Mux Select registers.
//!
//! This function Locks EPG Mux Select Register from being written further.
//!
//! The \e regFlags parameter can be of the \b EPG_MX_SEL_LOCK_REG_MXSEL0
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_lockMXSelReg(uint32_t muxbase, uint32_t regFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(muxbase + 0xCU)))) |= regFlags;
}

//*****************************************************************************
//
//! Release Locks of EPG Mux Select Register
//!
//! \param muxbase is the base address of the EPG Mux module.
//! \param regFlags is a bit mask of the EPG Mux Select registers.
//!
//! This function Releases Locks of EPG Mux Sel Registers to allow overwriting
//! the registers.
//!
//! The \e regFlags parameter can be of the \b EPG_MX_SEL_LOCK_REG_MXSEL0
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_releaseLockMXSelReg(uint32_t muxbase, uint32_t regFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(muxbase + 0xCU)))) &= ~regFlags;
}

//*****************************************************************************
//
//! Commit EPG Mux Select Registers Lock
//!
//! \param muxbase is the base address of the EPG Mux module.
//! \param regFlags is a bit mask of the EPG Mux Select registers.
//!
//! This function Commits the Locks of EPG Mux Sel Registers so that the locks
//! cannot be updated further.
//!
//! The \e regFlags parameter can be of the \b EPG_MX_SEL_LOCK_REG_MXSEL0
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPG_commitMXSelRegLock(uint32_t muxbase, uint32_t regFlags)
{
    ;

    (*((volatile uint32_t *)((uintptr_t)(muxbase + 0xEU)))) |= regFlags;
}

//*****************************************************************************
//
//! Select EPG Data Output
//!
//! \param muxbase is the base address of the EPG MUX module.
//! \param dataIn is the bit of EPG Data Input to be configured.
//! \param dataOutSel is the source of \e dataOutBit to configure.
//!
//! This function selects EPG Modules's Final Data Output which can be used to
//! feed EPG outputs to inputs of certain IPs or bypass the IP's input as is.
//!
//! The \e dataIn can take EPG_DATAIN.
//! The \e dataOutSel can take any of the EPG_DATA_OUT_DATA_IN,
//! EPG_DATA_OUT_EPG_OUT values.
//!
//! \return None.
//
//*****************************************************************************
extern void
EPG_selectEPGDataOut(uint32_t muxbase, EPG_DataIn dataIn,
                     EPG_DataOutSel dataOutSel);

//
// EPG External References & Function Declarations:
//


//#############################################################################
//
// FILE:   epwm.h
//
// TITLE:   C28x EPWM Driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup epwm_api ePWM
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_epwm.h
//
// TITLE:   Definitions for the EPWM registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the EPWM register offsets
//
//*************************************************************************************************
                                          // Output A
                                          // Output B
                                          // Mirror Register
                                          // Mirror Register
                                          // Register


//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMSYNCINSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBSTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMSYNCOUTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQTSRCSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the VCAPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the VCNTCFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCNFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRPWR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRMSTEP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCNFG2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRREM register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMXLINK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLA2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLB2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQSFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCSFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBREDHR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBRED register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBFEDHR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBFED register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBPHS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZDCSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCA register
//
//*************************************************************************************************
                                            // DOWN
                                            // DOWN

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCB register
//
//*************************************************************************************************
                                            // DOWN
                                            // DOWN

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZEINT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCBCFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZOSTFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCBCCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZOSTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETPS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETINTPS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETSOCPS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCNTINITCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCNTINIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCACTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCFCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCAPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BLANKPULSEMIXSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCAHTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCALTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBHTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBLTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMLOCK register
//
//*************************************************************************************************




//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Define to specify mask for source parameter for
// EPWM_enableSyncOutPulseSource() & EPWM_disableSyncOutPulseSource()
//
//*****************************************************************************

//*****************************************************************************
//
// Values that can be passed to EPWM_enableSyncOutPulseSource() &
// EPWM_disableSyncOutPulseSource() as the \e mode parameter.
//
//*****************************************************************************
//! Software force generated EPWM sync-out pulse
//! Counter zero event generates EPWM sync-out pulse
//! Counter equal to CMPB event generates EPWM sync-out pulse
//! Counter equal to CMPC event generates EPWM sync-out pulse
//! Counter equal to CMPD event generates EPWM sync-out pulse
//! DCA Event 1 Sync signal generates EPWM sync-out pulse
//! DCB Event 1 Sync signal generates EPWM sync-out pulse
//! Enable all the above sources

//
// Time Base Module
//
//*****************************************************************************
//
//! Values that can be passed to EPWM_setEmulationMode() as the
//! \e emulationMode parameter.
//
//*****************************************************************************
typedef enum
{
   //! Stop after next Time Base counter increment or decrement
   EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0,
   //! Stop when counter completes whole cycle
   EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1,
   //! Free run
   EPWM_EMULATION_FREE_RUN = 2
} EPWM_EmulationMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setCountModeAfterSync() as the
//! \e mode parameter.
//
//*****************************************************************************
typedef enum
{
   EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0, //!< Count down after sync event
   EPWM_COUNT_MODE_UP_AFTER_SYNC = 1    //!< Count up after sync event
} EPWM_SyncCountMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setClockPrescaler() as the
//! \e prescaler parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_CLOCK_DIVIDER_1 = 0,     //!< Divide clock by 1
    EPWM_CLOCK_DIVIDER_2 = 1,     //!< Divide clock by 2
    EPWM_CLOCK_DIVIDER_4 = 2,     //!< Divide clock by 4
    EPWM_CLOCK_DIVIDER_8 = 3,     //!< Divide clock by 8
    EPWM_CLOCK_DIVIDER_16 = 4,    //!< Divide clock by 16
    EPWM_CLOCK_DIVIDER_32 = 5,    //!< Divide clock by 32
    EPWM_CLOCK_DIVIDER_64 = 6,    //!< Divide clock by 64
    EPWM_CLOCK_DIVIDER_128 = 7    //!< Divide clock by 128
} EPWM_ClockDivider;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setClockPrescaler() as the
//! \e highSpeedPrescaler parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_HSCLOCK_DIVIDER_1 = 0,     //!< Divide clock by 1
    EPWM_HSCLOCK_DIVIDER_2 = 1,     //!< Divide clock by 2
    EPWM_HSCLOCK_DIVIDER_4 = 2,     //!< Divide clock by 4
    EPWM_HSCLOCK_DIVIDER_6 = 3,     //!< Divide clock by 6
    EPWM_HSCLOCK_DIVIDER_8 = 4,     //!< Divide clock by 8
    EPWM_HSCLOCK_DIVIDER_10 = 5,    //!< Divide clock by 10
    EPWM_HSCLOCK_DIVIDER_12 = 6,    //!< Divide clock by 12
    EPWM_HSCLOCK_DIVIDER_14 = 7     //!< Divide clock by 14
} EPWM_HSClockDivider;


//*****************************************************************************
//
//! Values that can be passed to EPWM_setSyncInPulseSource() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Disable Sync-in
    EPWM_SYNC_IN_PULSE_SRC_DISABLE         = 0x0,
    //! Sync-in source is EPWM1 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1   = 0x1,
    //! Sync-in source is EPWM2 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2   = 0x2,
    //! Sync-in source is EPWM3 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3   = 0x3,
    //! Sync-in source is EPWM4 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4   = 0x4,
    //! Sync-in source is EPWM5 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5   = 0x5,
    //! Sync-in source is EPWM6 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6   = 0x6,
    //! Sync-in source is EPWM7 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7   = 0x7,
    //! Sync-in source is EPWM8 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8   = 0x8,
    //! Sync-in source is ECAP1 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1   = 0x11,
    //! Sync-in source is ECAP2 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2   = 0x12,
    //! Sync-in source is ECAP3 sync-out signal
    EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3   = 0x13,
    //! Sync-in source is Input XBAR out5 signal
    EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT5 = 0x18,
    //! Sync-in source is Input XBAR out6 signal
    EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT6 = 0x19,
    //! Sync-in source is FSI RX trigger1 signal
    EPWM_SYNC_IN_PULSE_SRC_FSIRX_TRIG1   = 0x1F,
} EPWM_SyncInPulseSource;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setOneShotSyncOutTrigger() as the
//! \e trigger parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_OSHT_SYNC_OUT_TRIG_SYNC   = 0x0, //!< Trigger is OSHT sync
    EPWM_OSHT_SYNC_OUT_TRIG_RELOAD = 0x1  //!< Trigger is OSHT reload
} EPWM_OneShotSyncOutTrigger;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setPeriodLoadMode()  as the
//! \e loadMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! PWM Period register access is through shadow register
    EPWM_PERIOD_SHADOW_LOAD = 0,
    //! PWM Period register access is directly
    EPWM_PERIOD_DIRECT_LOAD = 1
} EPWM_PeriodLoadMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTimeBaseCounterMode() as the
//! \e counterMode parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_COUNTER_MODE_UP = 0,         //!< Up - count mode
    EPWM_COUNTER_MODE_DOWN = 1,       //!< Down - count mode
    EPWM_COUNTER_MODE_UP_DOWN = 2,    //!< Up - down - count mode
    EPWM_COUNTER_MODE_STOP_FREEZE = 3 //!< Stop - Freeze counter
} EPWM_TimeBaseCountMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_selectPeriodLoadEvent() as the
//! \e shadowLoadMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Shadow to active load occurs when time base counter reaches 0
    EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0,
    //! Shadow to active load occurs when time base counter reaches 0 and a
    //! SYNC occurs
    EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1,
    //! Shadow to active load occurs only when a SYNC occurs
    EPWM_SHADOW_LOAD_MODE_SYNC         = 2
} EPWM_PeriodShadowLoadMode;

//*****************************************************************************
//
// Values that can be returned by the EPWM_getTimeBaseCounterDirection()
//
//*****************************************************************************
//! Time base counter is counting up
//!
//! Time base counter is counting down
//!

//*****************************************************************************
//
//! Values that can be passed to EPWM_setupEPWMLinks() as the \e epwmLink
//! parameter.
//
//*****************************************************************************
typedef enum
{
     EPWM_LINK_WITH_EPWM_1 = 0,   //!< link current ePWM with ePWM1
     EPWM_LINK_WITH_EPWM_2 = 1,   //!< link current ePWM with ePWM2
     EPWM_LINK_WITH_EPWM_3 = 2,   //!< link current ePWM with ePWM3
     EPWM_LINK_WITH_EPWM_4 = 3,   //!< link current ePWM with ePWM4
     EPWM_LINK_WITH_EPWM_5 = 4,   //!< link current ePWM with ePWM5
     EPWM_LINK_WITH_EPWM_6 = 5,   //!< link current ePWM with ePWM6
     EPWM_LINK_WITH_EPWM_7 = 6,   //!< link current ePWM with ePWM7
     EPWM_LINK_WITH_EPWM_8 = 7    //!< link current ePWM with ePWM8
} EPWM_CurrentLink;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setupEPWMLinks() as the \e linkComp
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_LINK_TBPRD   = 0,  //!< Link TBPRD:TBPRDHR registers
    EPWM_LINK_COMP_A  = 4,  //!< Link COMPA registers
    EPWM_LINK_COMP_B  = 8,  //!< Link COMPB registers
    EPWM_LINK_COMP_C  = 12, //!< Link COMPC registers
    EPWM_LINK_COMP_D  = 16, //!< Link COMPD registers
    EPWM_LINK_GLDCTL2 = 28  //!< Link GLDCTL2 registers
} EPWM_LinkComponent;

//
// Counter Compare Module
//
//*****************************************************************************
//
//! Values that can be passed to the EPWM_getCounterCompareShadowStatus(),
//! EPWM_setCounterCompareValue(), EPWM_setCounterCompareShadowLoadMode(),
//! EPWM_disableCounterCompareShadowLoadMode()
//! as the \e compModule parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_COUNTER_COMPARE_A = 0, //!< Counter compare A
    EPWM_COUNTER_COMPARE_B = 2, //!< Counter compare B
    EPWM_COUNTER_COMPARE_C = 5, //!< Counter compare C
    EPWM_COUNTER_COMPARE_D = 7  //!< Counter compare D
} EPWM_CounterCompareModule;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setCounterCompareShadowLoadMode() as the
//! \e loadMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Load when counter equals zero
    EPWM_COMP_LOAD_ON_CNTR_ZERO = 0,
    //! Load when counter equals period
    EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1,
    //! Load when counter equals zero or period
    EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    //! Freeze shadow to active load
    EPWM_COMP_LOAD_FREEZE = 3,
    //! Load on sync or when counter equals zero
    EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4,
    //! Load on sync or when counter equals period
    EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5,
    //! Load on sync or when counter equals zero or period
    EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6,
    //! Load on sync only
    EPWM_COMP_LOAD_ON_SYNC_ONLY = 8
} EPWM_CounterCompareLoadMode;

//
// Action Qualifier Module
//
//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() and
//! EPWM_disableActionQualifierShadowLoadMode() as the \e aqModule parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_ACTION_QUALIFIER_A = 0, //!< Action Qualifier A
    EPWM_ACTION_QUALIFIER_B = 2  //!< Action Qualifier B
} EPWM_ActionQualifierModule;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() as the
//! \e loadMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Load when counter equals zero
    EPWM_AQ_LOAD_ON_CNTR_ZERO = 0,
    //! Load when counter equals period
    EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1,
    //! Load when counter equals zero or period
    EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    //! Freeze shadow to active load
    EPWM_AQ_LOAD_FREEZE = 3,
    //! Load on sync or when counter equals zero
    EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4,
    //! Load on sync or when counter equals period
    EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5,
    //! Load on sync or when counter equals zero or period
    EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6,
    //! Load on sync only
    EPWM_AQ_LOAD_ON_SYNC_ONLY = 8
} EPWM_ActionQualifierLoadMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierT1TriggerSource() and
//! EPWM_setActionQualifierT2TriggerSource() as the \e trigger parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0,      //!< Digital compare event A 1
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1,      //!< Digital compare event A 2
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2,      //!< Digital compare event B 1
    EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3,      //!< Digital compare event B 2
    EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1  = 4,      //!< Trip zone 1
    EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2  = 5,      //!< Trip zone 2
    EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3  = 6,      //!< Trip zone 3
    EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7,//!< ePWM sync
    EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT = 8  //!< Digital compare filter event
} EPWM_ActionQualifierTriggerSource;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierAction() as the \e
//! event parameter.
//
//*****************************************************************************
typedef enum
{
    //! Time base counter equals zero
    EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO       = 0,
    //! Time base counter equals period
    EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD     = 2,
    //! Time base counter up equals COMPA
    EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA    = 4,
    //! Time base counter down equals COMPA
    EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA  = 6,
    //! Time base counter up equals COMPB
    EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB    = 8,
    //! Time base counter down equals COMPB
    EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB  = 10,
    //! T1 event on count up
    EPWM_AQ_OUTPUT_ON_T1_COUNT_UP         = 1,
    //! T1 event on count down
    EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN       = 3,
    //! T2 event on count up
    EPWM_AQ_OUTPUT_ON_T2_COUNT_UP         = 5,
    //! T2 event on count down
    EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN       = 7
} EPWM_ActionQualifierOutputEvent;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierSWAction(),
//! EPWM_setActionQualifierAction() as the \e outPut parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_NO_CHANGE = 0,  //!< No change in the output pins
    EPWM_AQ_OUTPUT_LOW       = 1,  //!< Set output pins to low
    EPWM_AQ_OUTPUT_HIGH      = 2,  //!< Set output pins to High
    EPWM_AQ_OUTPUT_TOGGLE    = 3   //!< Toggle the output pins
} EPWM_ActionQualifierOutput;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierContSWForceAction()
//! as the \e outPut parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_SW_DISABLED         = 0,  //!< Software forcing disabled
    EPWM_AQ_SW_OUTPUT_LOW       = 1,  //!< Set output pins to low
    EPWM_AQ_SW_OUTPUT_HIGH      = 2   //!< Set output pins to High
} EPWM_ActionQualifierSWOutput;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierActionComplete()
//! as the \e action parameter.
//
//*****************************************************************************
typedef enum
{
    //! Time base counter equals zero and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0,
    //! Time base counter equals zero and set output pins to low
    EPWM_AQ_OUTPUT_LOW_ZERO = 0x1,
    //! Time base counter equals zero and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2,
    //! Time base counter equals zero and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3,
    //! Time base counter equals period and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0,
    //! Time base counter equals period and set output pins to low
    EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4,
    //! Time base counter equals period and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8,
    //! Time base counter equals period and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC,
    //! Time base counter up equals COMPA and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00,
    //! Time base counter up equals COMPA and set output pins to low
    EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10,
    //! Time base counter up equals COMPA and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20,
    //! Time base counter up equals COMPA and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30,
    //! Time base counter down equals COMPA and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00,
    //! Time base counter down equals COMPA and set output pins to low
    EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40,
    //! Time base counter down equals COMPA and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80,
    //! Time base counter down equals COMPA and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0,
    //! Time base counter up equals COMPB and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000,
    //! Time base counter up equals COMPB and set output pins to low
    EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100,
    //! Time base counter up equals COMPB and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200,
    //! Time base counter up equals COMPB and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300,
    //! Time base counter down equals COMPB and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000,
    //! Time base counter down equals COMPB and set output pins to low
    EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400,
    //! Time base counter down equals COMPB and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800,
    //! Time base counter down equals COMPB and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00
} EPWM_ActionQualifierEventAction;

//*****************************************************************************
//
//! Values that can be passed to
//! EPWM_setAdditionalActionQualifierActionComplete()  as the \e action
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! T1 event on count up and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0,
    //! T1 event on count up and set output pins to low
    EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1,
    //! T1 event on count up and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2,
    //! T1 event on count up and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3,
    //! T1 event on count down and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0,
    //! T1 event on count down and set output pins to low
    EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4,
    //! T1 event on count down and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8,
    //! T1 event on count down and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC,
    //! T2 event on count up and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00,
    //! T2 event on count up and set output pins to low
    EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10,
    //! T2 event on count up and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20,
    //! T2 event on count up and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30,
    //! T2 event on count down and no change in the output pins
    EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00,
    //! T2 event on count down and set output pins to low
    EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40,
    //! T2 event on count down and set output pins to high
    EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80,
    //! T2 event on count down and toggle the output pins
    EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0
} EPWM_AdditionalActionQualifierEventAction;

//*****************************************************************************
//
//! Values that can be passed to EPWM_forceActionQualifierSWAction(),
//! EPWM_setActionQualifierSWAction(), EPWM_setActionQualifierAction()
//! EPWM_setActionQualifierContSWForceAction() as the \e epwmOutput parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_AQ_OUTPUT_A = 0, //!< ePWMxA output
    EPWM_AQ_OUTPUT_B = 2  //!< ePWMxB output
} EPWM_ActionQualifierOutputModule;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setActionQualifierContSWForceShadowMode()
//! as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Shadow mode load when counter equals zero
    EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO        = 0,
    //! Shadow mode load when counter equals period
    EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD      = 1,
    //! Shadow mode load when counter equals zero or period
    EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    //! No shadow load mode. Immediate mode only.
    EPWM_AQ_SW_IMMEDIATE_LOAD   = 3
} EPWM_ActionQualifierContForce;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDeadBandOutputSwapMode()
//! as the \e output parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_OUTPUT_A = 1, //!< DB output is ePWMA
    EPWM_DB_OUTPUT_B = 0  //!< DB output is ePWMB
} EPWM_DeadBandOutput;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDeadBandDelayPolarity(),
//! EPWM_setDeadBandDelayMode() as the \e delayMode parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_RED = 1, //!< DB RED (Rising Edge Delay) mode
    EPWM_DB_FED = 0  //!< DB FED (Falling Edge Delay) mode
} EPWM_DeadBandDelayMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDeadBandDelayPolarity as the
//! \e polarity parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DB_POLARITY_ACTIVE_HIGH = 0, //!< DB polarity is not inverted
    EPWM_DB_POLARITY_ACTIVE_LOW  = 1  //!< DB polarity is inverted
} EPWM_DeadBandPolarity;

//*****************************************************************************
//
// Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(),
// EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter.
//
//*****************************************************************************
//! Input signal is ePWMA
//!
//! Input signal is ePWMB
//!
//! Input signal is the output of Rising Edge delay
//!

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDeadBandControlShadowLoadMode() as
//! the \e loadMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Load when counter equals zero
    EPWM_DB_LOAD_ON_CNTR_ZERO        = 0,
    //! Load when counter equals period
    EPWM_DB_LOAD_ON_CNTR_PERIOD      = 1,
    //! Load when counter equals zero or period
    EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    //! Freeze shadow to active load
    EPWM_DB_LOAD_FREEZE = 3
} EPWM_DeadBandControlLoadMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setRisingEdgeDelayCountShadowLoadMode()
//! as the \e loadMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Load when counter equals zero
    EPWM_RED_LOAD_ON_CNTR_ZERO        = 0,
    //! Load when counter equals period
    EPWM_RED_LOAD_ON_CNTR_PERIOD      = 1,
    //! Load when counter equals zero or period
    EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    //! Freeze shadow to active load
    EPWM_RED_LOAD_FREEZE = 3
} EPWM_RisingEdgeDelayLoadMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setFallingEdgeDelayCountShadowLoadMode()
//! as the \e loadMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Load when counter equals zero
    EPWM_FED_LOAD_ON_CNTR_ZERO        = 0,
    //! Load when counter equals period
    EPWM_FED_LOAD_ON_CNTR_PERIOD      = 1,
    //! Load when counter equals zero or period
    EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2,
    //! Freeze shadow to active load
    EPWM_FED_LOAD_FREEZE = 3
} EPWM_FallingEdgeDelayLoadMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDeadBandCounterClock() as the
//! \e clockMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Dead band counter runs at TBCLK rate
    EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0,
    //! Dead band counter runs at 2*TBCLK rate
    EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1
} EPWM_DeadBandClockMode;

//
// Trip Zone
//
//*****************************************************************************
//
// Values that can be passed to EPWM_enableTripZoneSignals() and
// EPWM_disableTripZoneSignals() as the tzSignal parameter.
//
//*****************************************************************************
//! TZ1 Cycle By Cycle
//!
//! TZ2 Cycle By Cycle
//!
//! TZ3 Cycle By Cycle
//!
//! TZ4 Cycle By Cycle
//!
//! TZ5 Cycle By Cycle
//!
//! TZ6 Cycle By Cycle
//!
//! DCAEVT2 Cycle By Cycle
//!
//! DCBEVT2 Cycle By Cycle
//!
//! One-shot TZ1
//!
//! One-shot TZ2
//!
//! One-shot TZ3
//!
//! One-shot TZ4
//!
//! One-shot TZ5
//!
//! One-shot TZ6
//!
//! One-shot DCAEVT1
//!
//! One-shot DCBEVT1
//!

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition()
//! as the \e dcType parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_DC_OUTPUT_A1 = 0, //!< Digital Compare output 1 A
    EPWM_TZ_DC_OUTPUT_A2 = 3, //!< Digital Compare output 2 A
    EPWM_TZ_DC_OUTPUT_B1 = 6, //!< Digital Compare output 1 B
    EPWM_TZ_DC_OUTPUT_B2 = 9  //!< Digital Compare output 2 B
} EPWM_TripZoneDigitalCompareOutput;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition()
//! as the \e dcEvent parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_EVENT_DC_DISABLED = 0,       //!< Event is disabled
    EPWM_TZ_EVENT_DCXH_LOW    = 1,       //!< Event when DCxH low
    EPWM_TZ_EVENT_DCXH_HIGH   = 2,       //!< Event when DCxH high
    EPWM_TZ_EVENT_DCXL_LOW    = 3,       //!< Event when DCxL low
    EPWM_TZ_EVENT_DCXL_HIGH   = 4,       //!< Event when DCxL high
    EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5 //!< Event when DCxL high DCxH low
} EPWM_TripZoneDigitalCompareOutputEvent;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTripZoneAction() as the \e tzEvent
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ACTION_EVENT_TZA = 0,     //!< TZ1 - TZ6, DCAEVT2, DCAEVT1
    EPWM_TZ_ACTION_EVENT_TZB = 2,     //!< TZ1 - TZ6, DCBEVT2, DCBEVT1
    EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4, //!< DCAEVT1 (Digital Compare A event 1)
    EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6, //!< DCAEVT2 (Digital Compare A event 2)
    EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8, //!< DCBEVT1 (Digital Compare B event 1)
    EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10 //!< DCBEVT2 (Digital Compare B event 2)
} EPWM_TripZoneEvent;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTripZoneAction() as the
//! \e tzAction parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ACTION_HIGH_Z  = 0, //!< High impedance output
    EPWM_TZ_ACTION_HIGH    = 1, //!< High voltage state
    EPWM_TZ_ACTION_LOW     = 2, //!< Low voltage state
    EPWM_TZ_ACTION_DISABLE = 3  //!< Disable action
} EPWM_TripZoneAction;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTripZoneAdvAction() as the
//! \e tzAdvEvent parameter.
//
//*****************************************************************************
typedef enum
{
    //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down
    EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9,
    //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up
    EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6,
    //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down
    EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3,
    //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up
    EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0
} EPWM_TripZoneAdvancedEvent;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA(),
//! EPWM_setTripZoneAdvDigitalCompareActionB(),EPWM_setTripZoneAdvAction()
//! as the \e tzAdvDCAction parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_TZ_ADV_ACTION_HIGH_Z  = 0, //!< High impedance output
    EPWM_TZ_ADV_ACTION_HIGH    = 1, //!< High voltage state
    EPWM_TZ_ADV_ACTION_LOW     = 2, //!< Low voltage state
    EPWM_TZ_ADV_ACTION_TOGGLE  = 3, //!< Toggle the output
    EPWM_TZ_ADV_ACTION_DISABLE = 7  //!< Disable action
} EPWM_TripZoneAdvancedAction;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA() and
//! EPWM_setTripZoneAdvDigitalCompareActionB() as the \e tzAdvDCEvent
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Digital Compare event A/B 1 while counting up
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0,
    //! Digital Compare event A/B 1 while counting down
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3,
    //! Digital Compare event A/B 2 while counting up
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6,
    //! Digital Compare event A/B 2 while counting down
    EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D =  9
} EPWM_TripZoneAdvDigitalCompareEvent;

//*****************************************************************************
//
// Values that can be passed to EPWM_enableTripZoneInterrupt()and
// EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter .
//
//*****************************************************************************
//! Trip Zones Cycle By Cycle interrupt
//!
//! Trip Zones One Shot interrupt
//!
//! Digital Compare A Event 1 interrupt
//!
//! Digital Compare A Event 2 interrupt
//!
//! Digital Compare B Event 1 interrupt
//!
//! Digital Compare B Event 2 interrupt
//!

//*****************************************************************************
//
// Values that can be returned by EPWM_getTripZoneFlagStatus() .
//
//*****************************************************************************
//! Trip Zones Cycle By Cycle flag
//!
//! Trip Zones One Shot flag
//!
//! Digital Compare A Event 1 flag
//!
//! Digital Compare A Event 2 flag
//!
//! Digital Compare B Event 1 flag
//!
//! Digital Compare B Event 2 flag
//!

//*****************************************************************************
//
// Value can be passed to EPWM_clearTripZoneFlag() as the
// tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus().
//
//*****************************************************************************
//! Trip Zone interrupt
//!

//*****************************************************************************
//
// Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag()
// as the tzCbcFlag parameter and returned by
// EPWM_getCycleByCycleTripZoneFlagStatus().
//
//*****************************************************************************
//! CBC flag 1
//!
//! CBC flag 2
//!
//! CBC flag 3
//!
//! CBC flag 4
//!
//! CBC flag 5
//!
//! CBC flag 6
//!
//! CBC flag Digital compare event A2
//!
//! CBC flag Digital compare event B2
//!

//*****************************************************************************
//
// Values that can be passed to EPWM_clearOneShotTripZoneFlag() as
// the tzCbcFlag parameter and returned by the
// EPWM_getOneShotTripZoneFlagStatus() .
//
//*****************************************************************************
//! OST flag OST1
//!
//! OST flag OST2
//!
//! OST flag OST3
//!
//! OST flag OST4
//!
//! OST flag OST5
//!
//! OST flag OST6
//!
//! OST flag Digital compare event A1
//!
//! OST flag Digital compare event B1
//!

//*****************************************************************************
//
//! Values that can be passed to EPWM_selectCycleByCycleTripZoneClearEvent() as
//! the \e clearMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Clear CBC pulse when counter equals zero
    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0,
    //! Clear CBC pulse when counter equals period
    EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1,
    //! Clear CBC pulse when counter equals zero or period
    EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2
} EPWM_CycleByCycleTripZoneClearMode;

//*****************************************************************************
//
// Values that can be passed to EPWM_forceTripZoneEvent() as the
// tzForceEvent parameter.
//
//*****************************************************************************
//! Force Cycle By Cycle trip event
//!
//! Force a One-Shot Trip Event
//!
//! ForceDigital Compare Output A Event 1
//!
//! ForceDigital Compare Output A Event 2
//!
//! ForceDigital Compare Output B Event 1
//!
//! ForceDigital Compare Output B Event 2
//!

//*****************************************************************************
//
// Values that can be passed to EPWM_setInterruptSource() as the
// interruptSource parameter.
//
//*****************************************************************************
//! Time-base counter is disabled
//!
//! Time-base counter equal to zero
//!
//! Time-base counter equal to period
//!
//! Time-base counter equal to zero or period
//!
//! time-base counter equal to CMPA when the timer is incrementing
//!
//! time-base counter equal to CMPC when the timer is incrementing
//!
//! time-base counter equal to CMPA when the timer is decrementing
//!
//! time-base counter equal to CMPC when the timer is decrementing
//!
//! time-base counter equal to CMPB when the timer is incrementing
//!
//! time-base counter equal to CMPD when the timer is incrementing
//!
//! time-base counter equal to CMPB when the timer is decrementing
//!
//! time-base counter equal to CMPD when the timer is decrementing
//!

//*****************************************************************************
//
//! Values that can be passed to EPWM_enableADCTrigger(),
//! EPWM_disableADCTrigger(),EPWM_setADCTriggerSource(),
//! EPWM_setADCTriggerEventPrescale(),EPWM_getADCTriggerFlagStatus(),
//! EPWM_clearADCTriggerFlag(),EPWM_enableADCTriggerEventCountInit(),
//! EPWM_disableADCTriggerEventCountInit(),EPWM_forceADCTriggerEventCountInit(),
//! EPWM_setADCTriggerEventCountInitValue(),EPWM_getADCTriggerEventCount(),
//! EPWM_forceADCTrigger() as the \e adcSOCType parameter
//
//*****************************************************************************
typedef enum
{
    EPWM_SOC_A = 0,  //!< SOC A
    EPWM_SOC_B = 1   //!< SOC B
} EPWM_ADCStartOfConversionType;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setADCTriggerSource() as the
//! \e socSource parameter.
//
//*****************************************************************************
typedef enum
{
    //! Event is based on DCxEVT1
    EPWM_SOC_DCxEVT1 = 0,
    //! Time-base counter equal to zero
    EPWM_SOC_TBCTR_ZERO = 1,
    //! Time-base counter equal to period
    EPWM_SOC_TBCTR_PERIOD = 2,
    //! Time-base counter equal to zero or period
    EPWM_SOC_TBCTR_ZERO_OR_PERIOD = 3,
    //! Time-base counter equal to CMPA when the timer is incrementing
    EPWM_SOC_TBCTR_U_CMPA = 4,
    //! Time-base counter equal to CMPC when the timer is incrementing
    EPWM_SOC_TBCTR_U_CMPC = 8,
    //! Time-base counter equal to CMPA when the timer is decrementing
    EPWM_SOC_TBCTR_D_CMPA = 5,
    //! Time-base counter equal to CMPC when the timer is decrementing
    EPWM_SOC_TBCTR_D_CMPC = 10,
    //! Time-base counter equal to CMPB when the timer is incrementing
    EPWM_SOC_TBCTR_U_CMPB = 6,
    //! Time-base counter equal to CMPD when the timer is incrementing
    EPWM_SOC_TBCTR_U_CMPD = 12,
    //! Time-base counter equal to CMPB when the timer is decrementing
    EPWM_SOC_TBCTR_D_CMPB = 7,
    //! Time-base counter equal to CMPD when the timer is decrementing
    EPWM_SOC_TBCTR_D_CMPD = 14
} EPWM_ADCStartOfConversionSource;

//
// Digital Compare Module
//
//*****************************************************************************
//
//! Values that can be passed to EPWM_selectDigitalCompareTripInput(),
//! EPWM_enableDigitalCompareTripCombinationInput(),
//! EPWM_disableDigitalCompareTripCombinationInput() as the \e dcType
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_TYPE_DCAH = 0,  //!< Digital Compare A High
    EPWM_DC_TYPE_DCAL = 1,  //!< Digital Compare A Low
    EPWM_DC_TYPE_DCBH = 2,  //!< Digital Compare B High
    EPWM_DC_TYPE_DCBL = 3   //!< Digital Compare B Low
} EPWM_DigitalCompareType;

//*****************************************************************************
//
//! Values that can be passed to EPWM_selectDigitalCompareTripInput() as the
//! \e tripSource parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_TRIP_TRIPIN1 = 0,   //!< Trip 1
    EPWM_DC_TRIP_TRIPIN2 = 1,   //!< Trip 2
    EPWM_DC_TRIP_TRIPIN3 = 2,   //!< Trip 3
    EPWM_DC_TRIP_TRIPIN4 = 3,   //!< Trip 4
    EPWM_DC_TRIP_TRIPIN5 = 4,   //!< Trip 5
    EPWM_DC_TRIP_TRIPIN6 = 5,   //!< Trip 6
    EPWM_DC_TRIP_TRIPIN7 = 6,   //!< Trip 7
    EPWM_DC_TRIP_TRIPIN8 = 7,   //!< Trip 8
    EPWM_DC_TRIP_TRIPIN9 = 8,   //!< Trip 9
    EPWM_DC_TRIP_TRIPIN10 = 9,  //!< Trip 10
    EPWM_DC_TRIP_TRIPIN11 = 10, //!< Trip 11
    EPWM_DC_TRIP_TRIPIN12 = 11, //!< Trip 12
    EPWM_DC_TRIP_TRIPIN14 = 13, //!< Trip 14
    EPWM_DC_TRIP_TRIPIN15 = 14, //!< Trip 15
    EPWM_DC_TRIP_COMBINATION = 15 //!< All Trips (Trip1 - Trip 15) are selected
} EPWM_DigitalCompareTripInput;

//*****************************************************************************
//
// Values that can be passed to EPWM_enableDigitalCompareTripCombinationInput(),
// EPWM_disableDigitalCompareTripCombinationInput() as the tripInput
// parameter.
//
//*****************************************************************************
//! Combinational Trip 1 input
//!
//! Combinational Trip 2 input
//!
//! Combinational Trip 3 input
//!
//! Combinational Trip 4 input
//!
//! Combinational Trip 5 input
//!
//! Combinational Trip 6 input
//!
//! Combinational Trip 7 input
//!
//! Combinational Trip 8 input
//!
//! Combinational Trip 9 input
//!
//! Combinational Trip 10 input
//!
//! Combinational Trip 11 input
//!
//! Combinational Trip 12 input
//!
//! Combinational Trip 14 input
//!
//! Combinational Trip 15 input
//!

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareBlankingEvent() as the
//! the \e blankingPulse parameter.
//
//*****************************************************************************
typedef enum
{
    //! Time base counter equals period
    EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0,
    //! Time base counter equals zero
    EPWM_DC_WINDOW_START_TBCTR_ZERO   = 1,
    //! Time base counter equals zero or period
    EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD  = 2,
    //! Blank pulse mix
    EPWM_DC_WINDOW_START_BLANK_PULSE_MIX  = 3
} EPWM_DigitalCompareBlankingPulse;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareFilterInput()
//! as the \e filterInput parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0, //!< DC filter signal source is DCAEVT1
    EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1, //!< DC filter signal source is DCAEVT2
    EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2, //!< DC filter signal source is DCBEVT1
    EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3  //!< DC filter signal source is DCBEVT2
} EPWM_DigitalCompareFilterInput;

//*****************************************************************************
//
//! Values that can be assigned to EPWM_setDigitalCompareEventSource(),
//! EPWM_setDigitalCompareEventSyncMode(),EPWM_enableDigitalCompareSyncEvent()
//! EPWM_enableDigitalCompareADCTrigger(),EPWM_disableDigitalCompareSyncEvent()
//! EPWM_disableDigitalCompareADCTrigger() as the \e dcModule parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_MODULE_A = 0, //!< Digital Compare Module A
    EPWM_DC_MODULE_B = 1  //!< Digital Compare Module B
} EPWM_DigitalCompareModule;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareEventSource(),
//! EPWM_setDigitalCompareEventSyncMode as the \e dcEvent parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EVENT_1 = 0, //!< Digital Compare Event number 1
    EPWM_DC_EVENT_2 = 1  //!< Digital Compare Event number 2
} EPWM_DigitalCompareEvent;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareEventSource() as the
//! \e dcEventSource parameter.
//
//*****************************************************************************
typedef enum
{
    //! Signal source is unfiltered (DCAEVT1/2)
    EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0,
    //! Signal source is filtered (DCEVTFILT)
    EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1
} EPWM_DigitalCompareEventSource;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareEventSyncMode() as the
//! \e syncMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! DC input signal is synced with TBCLK
    EPWM_DC_EVENT_INPUT_SYNCED = 0,
    //! DC input signal is not synced with TBCLK
    EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1
} EPWM_DigitalCompareSyncMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareCBCLatchMode() as the
//! \e latchMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! DC cycle-by-cycle(CBC) latch is disabled
    EPWM_DC_CBC_LATCH_DISABLED = 0x0,
    //! DC cycle-by-cycle(CBC) latch is enabled
    EPWM_DC_CBC_LATCH_ENABLED  = 0x1
} EPWM_DigitalCompareCBCLatchMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_selectDigitalCompareCBCLatchClearEvent()
//! as the \e latchMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Clear CBC latch when counter equals zero
    EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO           = 0x0,
    //! Clear CBC latch when counter equals period
    EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD      = 0x1,
    //! Clear CBC latch when counter equals zero or period
    EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD = 0x2
} EPWM_DigitalCompareCBCLatchClearEvent;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setGlobalLoadTrigger() as the
//! \e loadTrigger parameter.
//
//*****************************************************************************
typedef enum
{
    //! Load when counter is equal to zero
    EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0,
    //! Load when counter is equal to period
    EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1,
    //! Load when counter is equal to zero or period
    EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2,
    //! Load on sync event
    EPWM_GL_LOAD_PULSE_SYNC = 0x3,
    //! Load on sync event or when counter  is equal to zero
    EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4,
    //! Load on sync event or when counter  is equal to period
    EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5,
    //! Load on sync event or when counter is equal to period or zero
    EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6,
    //! Load on global force
    EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF
} EPWM_GlobalLoadTrigger;

//*****************************************************************************
//
// Values that can be passed to EPWM_enableGlobalLoadRegisters(),
// EPWM_disableGlobalLoadRegisters() as theloadRegister parameter.
//
//*****************************************************************************
//! Global load TBPRD:TBPRDHR
//!
//! Global load CMPA:CMPAHR
//!
//! Global load CMPB:CMPBHR
//!
//! Global load CMPC
//!
//! Global load CMPD
//!
//! Global load DBRED:DBREDHR
//!
//! Global load DBFED:DBFEDHR
//!
//! Global load DBCTL
//!
//! Global load AQCTLA/A2
//!
//! Global load AQCTLB/B2
//!
//! Global load AQCSFRC
//!

//*****************************************************************************
//
//! Values that can be passed to EPWM_setValleyTriggerSource() as the \e
//! trigger parameter.
//
//*****************************************************************************
typedef enum
{
    //! Valley capture trigged by software
    EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U,
    //! Valley capture trigged by when counter is equal to zero
    EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U,
    //! Valley capture trigged by when counter is equal period
    EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U,
    //! Valley capture trigged when counter is equal to zero or period
    EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U,
    //! Valley capture trigged by DCAEVT1 (Digital Compare A event 1)
    EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U,
    //! Valley capture trigged by DCAEVT2 (Digital Compare A event 2)
    EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U,
    //! Valley capture trigged by DCBEVT1 (Digital Compare B event 1)
    EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U,
    //! Valley capture trigged by DCBEVT2 (Digital Compare B event 2)
    EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U
} EPWM_ValleyTriggerSource;

//*****************************************************************************
//
//! Values that can be passed to EPWM_getValleyCountEdgeStatus() as the \e edge
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_VALLEY_COUNT_START_EDGE = 0, //!< Valley count start edge
    EPWM_VALLEY_COUNT_STOP_EDGE  = 1  //!< Valley count stop edge
} EPWM_ValleyCounterEdge;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setValleyDelayValue() as the \e delayMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Delay value equals the offset value defines by software
    EPWM_VALLEY_DELAY_MODE_SW_DELAY   = 0U,
    //! Delay value equals the sum of the Hardware counter value and the offset
    //! value defines by software
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U,
    //! Delay value equals the the Hardware counter shifted by
    //! (1 + the offset value defines by software)
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U,
    //! Delay value equals the the Hardware counter shifted by
    //! (2 + the offset value defines by software)
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U,
    //! Delay value equals the the Hardware counter shifted by
    //! (4 + the offset value defines by software)
    EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U
} EPWM_ValleyDelayMode;

//
// DC Edge Filter
//
//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterMode()
//! as the \e edgeMode parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EDGEFILT_MODE_RISING  = 0, //!< Digital Compare Edge filter low
                                       //!< to high edge mode
    EPWM_DC_EDGEFILT_MODE_FALLING = 1, //!< Digital Compare Edge filter high
                                       //!< to low edge mode
    EPWM_DC_EDGEFILT_MODE_BOTH    = 2  //!< Digital Compare Edge filter both
                                       //!< edges mode
} EPWM_DigitalCompareEdgeFilterMode;

//*****************************************************************************
//
//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterEdgeCount()
//! as the \e edgeCount parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_DC_EDGEFILT_EDGECNT_0  = 0, //!< Digital Compare Edge filter edge
                                     //!< count = 0
    EPWM_DC_EDGEFILT_EDGECNT_1  = 1, //!< Digital Compare Edge filter edge
                                     //!< count = 1
    EPWM_DC_EDGEFILT_EDGECNT_2  = 2, //!< Digital Compare Edge filter edge
                                     //!< count = 2
    EPWM_DC_EDGEFILT_EDGECNT_3  = 3, //!< Digital Compare Edge filter edge
                                     //!< count = 3
    EPWM_DC_EDGEFILT_EDGECNT_4  = 4, //!< Digital Compare Edge filter edge
                                     //!< count = 4
    EPWM_DC_EDGEFILT_EDGECNT_5  = 5, //!< Digital Compare Edge filter edge
                                     //!< count = 5
    EPWM_DC_EDGEFILT_EDGECNT_6  = 6, //!< Digital Compare Edge filter edge
                                     //!< count = 6
    EPWM_DC_EDGEFILT_EDGECNT_7  = 7  //!< Digital Compare Edge filter edge
                                     //!< count = 7
} EPWM_DigitalCompareEdgeFilterEdgeCount;

//*****************************************************************************
//
//! Values that can be passed to EPWM_lockRegisters() as the \e registerGroup
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2,     //!< Global load register group
    EPWM_REGISTER_GROUP_TRIP_ZONE = 0x4,       //!< Trip zone register group
    EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group
    EPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group
} EPWM_LockRegisterGroup;

//*****************************************************************************
//
//! Values that can be passed to EPWM_configureSignal() as the
//! \e signalParams parameter.
//
//*****************************************************************************
typedef struct
{
    float32_t              freqInHz;    //!< Desired Signal Frequency(in Hz)
    float32_t              dutyValA;    //!< Desired ePWMxA Signal Duty
    float32_t              dutyValB;    //!< Desired ePWMxB Signal Duty
    _Bool                   invertSignalB; //!< Invert ePWMxB Signal if true
    float32_t              sysClkInHz;  //!< SYSCLK Frequency(in Hz)
    EPWM_TimeBaseCountMode tbCtrMode;   //!< Time Base Counter Mode
    EPWM_ClockDivider      tbClkDiv;    //!< Time Base Counter Clock Divider
    EPWM_HSClockDivider    tbHSClkDiv;  //!< Time Base Counter HS Clock Divider
} EPWM_SignalParams;

//*****************************************************************************
//
// Prototypes for the API.
//
//*****************************************************************************

//*****************************************************************************
//
//! \internal
//! Checks ePWM base address.
//!
//! \param base specifies the ePWM module base address.
//!
//! This function determines if an ePWM module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//
// Time Base Sub Module related APIs
//
//*****************************************************************************
//
//! Set the time base count
//!
//! \param base is the base address of the EPWM module.
//! \param count is the time base count value.
//!
//! This function sets the 16 bit counter value of the time base counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to TBCTR register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = count;
}

//*****************************************************************************
//
//! Set count mode after phase shift sync
//!
//! \param base is the base address of the EPWM module.
//! \param mode is the count mode.
//!
//! This function sets the time base count to count up or down after a new
//! phase value set by the EPWM_setPhaseShift(). The count direction is
//! determined by the variable mode. Valid inputs for mode are:
//!  - EPWM_COUNT_MODE_UP_AFTER_SYNC      - Count up after sync
//!  - EPWM_COUNT_MODE_DOWN_AFTER_SYNC    - Count down after sync
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
{
    //
    // Check the arguments
    //
    ;

    if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC)
    {
        //
        // Set PHSDIR bit
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x2000U;
    }
    else
    {
        //
        // Clear PHSDIR bit
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x2000U;
    }
}

//*****************************************************************************
//
//! Set the time base clock and the high speed time base clock count pre-scaler
//!
//! \param base is the base address of the EPWM module.
//! \param prescaler is the time base count pre scale value.
//! \param highSpeedPrescaler is the high speed time base count pre scale
//!        value.
//!
//! This function sets the pre scaler(divider)value for the time base clock
//! counter and the high speed time base clock counter.
//! Valid values for pre-scaler and highSpeedPrescaler are EPWM_CLOCK_DIVIDER_X,
//! where X is 1,2,4,8,16, 32,64 or 128.
//! The actual numerical values for these macros represent values 0,1...7.
//! The equation for the output clock is:
//!   TBCLK = EPWMCLK/(highSpeedPrescaler * pre-scaler)
//!
//! \b Note: EPWMCLK is a scaled version of SYSCLK. At reset EPWMCLK is half
//!          SYSCLK.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler,
                       EPWM_HSClockDivider highSpeedPrescaler)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to CLKDIV and HSPCLKDIV bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0x0U))))  &
                ~(0x1C00U | 0x380U)) |
                (((uint16_t)prescaler << 10U) |
                ((uint16_t)highSpeedPrescaler << 7U)));
}

//*****************************************************************************
//
//! Force a software sync pulse
//!
//! \param base is the base address of the EPWM module.
//!
//! This function causes a single software initiated sync pulse. Make sure the
//! appropriate mode is selected using EPWM_setupSyncOutputMode() before using
//! this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceSyncPulse(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set SWFSYNC bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x40U;
}

//*****************************************************************************
//
//! Set up the source for sync-in pulse.
//!
//! \param base is the base address of the EPWM module.
//! \param source is the sync-in pulse source.
//!
//! This function set the sync out pulse mode.
//! Valid values for mode are:
//!  - EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1-16 - sync-in pulse source can be
//!                                              any of the EPWM1-16 sync-out
//!                                              signal
//!  - EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1-7 - sync-in pulse source can be
//!                                             selected as any of the ECAP1-16
//!                                             sync-out signal
//!  - EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT5-6 - sync-in pulse source can be
//!                                              selected as any of the Input
//!                                              xbar out5-6 signal
//!  - EPWM_SYNC_IN_PULSE_SRC_ETHERCAT_SYNC0-1 - sync-in pulse source can be
//!                                              selected as any of the Ethercat
//!                                              sync0-1 signal
//!  - EPWM_SYNC_IN_PULSE_SRC_DISABLE - sync-in pulse is disabled for the
//!                                     EPWM module
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set EPWM Sync-In Source Mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) =
            ((*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) & (~0x1FU)) |
            ((uint16_t)source & 0x1FU);
}

//*****************************************************************************
//
//! Enables sync-out pulse source.
//!
//! \param base is the base address of the EPWM module.
//! \param source is the sync-out pulse source.
//!
//! This function enables the sync-out pulse source.
//! Below valid values for param \b source can be OR'd together to enable
//! multiple sync-out sources:
//! - EPWM_SYNC_OUT_PULSE_ON_SOFTWARE - sync-out pulse is generated by
//!                                     software when EPWM_forceSyncPulse()
//!                                     function is called or by EPWMxSYNCI
//!                                     signal.
//! - EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO - sync-out pulse is generated when
//!                                      time base counter equals zero.
//! - EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B - sync-out pulse is generated when
//!                                           time base counter equals compare
//!                                           B value.
//! - EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C - sync-out pulse is generated when
//!                                           time base counter equals compare
//!                                           C value.
//! - EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D - sync-out pulse is generated when
//!                                           time base counter equals compare
//!                                           D value.
//! - EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC - sync-out pulse is generated by DCA
//!                                          event1 sync signal
//! - EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC - sync-out pulse is generated by DCB
//!                                          event1 sync signal
//! - EPWM_SYNC_OUT_PULSE_ON_ALL  - sync-out pulse is generated by all
//!                                 the above sources
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Enable selected EPWM Sync-Out Sources.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) |
                                      (uint16_t)source;
}

//*****************************************************************************
//
//! Disables sync-out pulse source.
//!
//! \param base is the base address of the EPWM module.
//! \param source is the sync-out pulse source.
//!
//! This function disables the sync-out pulse source.
//! Below valid values for param \b source can be OR'd together to disable
//! multiple sync-out sources:
//!  - EPWM_SYNC_OUT_PULSE_ON_SOFTWARE - disables software as sync-out source
//!
//!  - EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO - disables counter equal to zero event
//!                                       as sync-out source
//!  - EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B - disables counter equal to cmpb
//!                                            event as sync-out source
//!  - EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C - disables counter equal to cmpc
//!                                            event as sync-out source
//!  - EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D - disables counter equal to cmpd
//!                                            event as sync-out source
//!  - EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC - disables DCA event1 sync signal as
//!                                           sync-out source
//!  - EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC - disables DCB event1 sync signal as
//!                                           sync-out source
//!  - EPWM_SYNC_OUT_PULSE_ON_ALL - disables all the above sync-out sources
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Disable EPWM Sync-Out Sources.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) &
                                      ~((uint16_t)source);
}

//*****************************************************************************
//
//! Set up the one-shot sync-out trigger source.
//!
//! \param base is the base address of the EPWM module.
//! \param trigger is the one-shot sync-out signal trigger source.
//!
//! This function sets the one-shot sync-out trigger source.
//! Valid values for param \b trigger are:
//!  - EPWM_OSHT_SYNC_OUT_TRIG_SYNC - Trigger for one-shot sync-out signal is
//!                                    one-shot sync event.
//!  - EPWM_OSHT_SYNC_OUT_TRIG_RELOAD - Trigger for one-shot sync-out signal is
//!                                     one-shot reload event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setOneShotSyncOutTrigger(uint32_t base,
                              EPWM_OneShotSyncOutTrigger trigger)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set source for One-Shot Sync-Out Pulse.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) =
            ((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) & ~(0x1U)) |
            (uint16_t)trigger;
}

//*****************************************************************************
//
//! Set PWM period load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadMode is the PWM period load mode.
//!
//! This function sets the load mode for the PWM period. If loadMode is set to
//! EPWM_PERIOD_SHADOW_LOAD, a write or read to the TBPRD (PWM Period count
//! register) accesses the shadow register. If loadMode is set to
//! EPWM_PERIOD_DIRECT_LOAD, a write or read to the TBPRD register accesses the
//! register directly.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
{
    //
    // Check the arguments
    //
    ;

    if(loadMode == EPWM_PERIOD_SHADOW_LOAD)
    {
        //
        // Clear PRDLD
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x8U;
    }
    else
    {
        //
        // Set PRDLD
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x8U;
    }
}

//*****************************************************************************
//
//! Enable phase shift load
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables loading of phase shift when the appropriate sync
//! event occurs.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enablePhaseShiftLoad(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set PHSEN bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x4U;
}

//*****************************************************************************
//
//! Disable phase shift load
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables loading of phase shift.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disablePhaseShiftLoad(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear PHSEN bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x4U;
}

//*****************************************************************************
//
//! Set time base counter mode
//!
//! \param base is the base address of the EPWM module.
//! \param counterMode is the time base counter mode.
//!
//! This function sets up the time base counter mode.
//! Valid values for counterMode are:
//!  - EPWM_COUNTER_MODE_UP          - Up - count mode.
//!  - EPWM_COUNTER_MODE_DOWN        - Down - count mode.
//!  - EPWM_COUNTER_MODE_UP_DOWN     - Up - down - count mode.
//!  - EPWM_COUNTER_MODE_STOP_FREEZE - Stop - Freeze counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to CTRMODE bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & ~(0x3U)) |
             ((uint16_t)counterMode));
}

//*****************************************************************************
//
//! Set shadow to active period load on sync mode
//!
//! \param base is the base address of the EPWM module.
//! \param shadowLoadMode is the shadow to active load mode.
//!
//! This function sets up the shadow to active Period register load mode with
//! respect to a sync event. Valid values for shadowLoadMode are:
//!  - EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO - shadow to active load occurs when
//!                                         time base counter reaches 0.
//!  - EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC - shadow to active load occurs when
//!                                         time base counter reaches 0 and a
//!                                         SYNC occurs.
//!  - EPWM_SHADOW_LOAD_MODE_SYNC         - shadow to active load occurs only
//!                                         when a SYNC occurs.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_selectPeriodLoadEvent(uint32_t base,
                           EPWM_PeriodShadowLoadMode shadowLoadMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to PRDLDSYNC bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) & ~(0xC000U)) |
                 ((uint16_t)shadowLoadMode << 14U));
}
//*****************************************************************************
//
//! Enable one shot sync mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables one shot sync mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableOneShotSync(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set OSHTSYNCMODE bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x40U;
}

//*****************************************************************************
//
//! Disable one shot sync mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables one shot sync mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableOneShotSync(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear OSHTSYNCMODE bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &= ~0x40U;
}

//*****************************************************************************
//
//! Start one shot sync mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function propagates a one shot sync pulse.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_startOneShotSync(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set OSHTSYNC bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x80U;
}

//*****************************************************************************
//
//! Returns time base counter value.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the current value of the time base counter.
//!
//! \return returns time base counter value
//
//*****************************************************************************
static inline uint16_t
EPWM_getTimeBaseCounterValue(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Returns TBCTR value
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))));
}

//*****************************************************************************
//
//! Return time base counter maximum status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the status of the time base max counter.
//!
//! \return Returns true if the counter has reached 0xFFFF.
//!         Returns false if the counter hasn't reached 0xFFFF.
//
//*****************************************************************************
static inline _Bool
EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return true if CTRMAX bit is set, false otherwise
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) & 0x4U) ==
            0x4U) ? 1 : 0);
}

//*****************************************************************************
//
//! Clear max time base counter event.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function clears the max time base counter latch event. The latch event
//! occurs when the time base counter reaches its maximum value of 0xFFFF.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set CTRMAX bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) = 0x4U;
}

//*****************************************************************************
//
//! Return external sync signal status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the external sync signal status.
//!
//! \return Returns true if if an external sync signal event
//!         Returns false if there is no event.
//
//*****************************************************************************
static inline _Bool
EPWM_getSyncStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return true if SYNCI bit is set, false otherwise
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) & 0x2U) ==
            0x2U) ? 1 : 0);
}

//*****************************************************************************
//
//! Clear external sync signal event.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function clears the external sync signal latch event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_clearSyncEvent(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set SYNCI bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) = 0x2U;
}

//*****************************************************************************
//
//! Return time base counter direction.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the direction of the time base counter.
//!
//! \return returns EPWM_TIME_BASE_STATUS_COUNT_UP if the counter is counting
//!                 up or EPWM_TIME_BASE_STATUS_COUNT_DOWN if the counter is
//!                 counting down.
//
//*****************************************************************************
static inline uint16_t
EPWM_getTimeBaseCounterDirection(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return CTRDIR bit
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) & 0x1U);
}

//*****************************************************************************
//
//! Sets the phase shift offset counter value.
//!
//! \param base is the base address of the EPWM module.
//! \param phaseCount is the phase shift count value.
//!
//! This function sets the 16 bit time-base counter phase of the ePWM relative
//! to the time-base that is supplying the synchronization input signal. Call
//! the EPWM_enablePhaseShiftLoad() function to enable loading of the
//! phaseCount phase shift value when a sync event occurs.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to TBPHS bit
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x60U)))) =
                   (((*((volatile uint32_t *)((uintptr_t)(base + 0x60U)))) &
                    ~((uint32_t)0xFFFF0000U)) |
                    ((uint32_t)phaseCount << 16U));
}

//*****************************************************************************
//
//! Sets the PWM period count.
//!
//! \param base is the base address of the EPWM module.
//! \param periodCount is period count value.
//!
//! This function sets the period of the PWM count. The value of periodCount is
//! the value written to the register. User should map the desired period or
//! frequency of the waveform into the correct periodCount.
//! Invoke the function EPWM_selectPeriodLoadEvent() with the appropriate
//! parameter to set the load mode of the Period count. periodCount has a
//! maximum valid value of 0xFFFF
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to TBPRD bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x63U)))) = periodCount;
}

//*****************************************************************************
//
//! Gets the PWM period count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function gets the period of the PWM count.
//!
//! \return The period count value.
//
//*****************************************************************************
static inline uint16_t
EPWM_getTimeBasePeriod(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Read from TBPRD bit
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x63U)))));
}

//*****************************************************************************
//
//! Sets the EPWM links.
//!
//! \param base is the base address of the EPWM module.
//! \param epwmLink is the ePWM instance to link with.
//! \param linkComp is the ePWM component to link.
//!
//! This function links the component defined in linkComp in the current ePWM
//! instance with the linkComp component of the ePWM instance defined by
//! epwmLink. A change (a write) in the value of linkComp component of epwmLink
//! instance, causes a change in the current ePWM linkComp component.
//! For example if the current ePWM is ePWM3 and the values of epwmLink and
//! linkComp are EPWM_LINK_WITH_EPWM_1 and EPWM_LINK_COMP_C respectively,
//! then a write to COMPC register in ePWM1, will result in a simultaneous
//! write to COMPC register in ePWM3.
//! Valid values for epwmLink are:
//!   - EPWM_LINK_WITH_EPWM_1  - link current ePWM with ePWM1
//!   - EPWM_LINK_WITH_EPWM_2  - link current ePWM with ePWM2
//!   - EPWM_LINK_WITH_EPWM_3  - link current ePWM with ePWM3
//!   - EPWM_LINK_WITH_EPWM_4  - link current ePWM with ePWM4
//!   - EPWM_LINK_WITH_EPWM_5  - link current ePWM with ePWM5
//!   - EPWM_LINK_WITH_EPWM_6  - link current ePWM with ePWM6
//!   - EPWM_LINK_WITH_EPWM_7  - link current ePWM with ePWM7
//!   - EPWM_LINK_WITH_EPWM_8  - link current ePWM with ePWM8
//!
//! Valid values for linkComp are:
//!   - EPWM_LINK_TBPRD   - link TBPRD:TBPRDHR registers
//!   - EPWM_LINK_COMP_A   - link COMPA registers
//!   - EPWM_LINK_COMP_B   - link COMPB registers
//!   - EPWM_LINK_COMP_C   - link COMPC registers
//!   - EPWM_LINK_COMP_D   - link COMPD registers
//!   - EPWM_LINK_GLDCTL2  - link GLDCTL2 registers
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink,
                    EPWM_LinkComponent linkComp)
{
    //
    // Check the arguments
    //
    ;

    //
    // Configure EPWM links
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x38U)))) =
              (((*((volatile uint32_t *)((uintptr_t)(base + 0x38U)))) & ~((uint32_t)0xFU << linkComp)) |
               ((uint32_t)epwmLink << linkComp));
}

//*****************************************************************************
//
//! Sets up the Counter Compare shadow load mode
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the counter compare module.
//! \param loadMode is the shadow to active load mode.
//!
//! This function enables and sets up the counter compare shadow load mode.
//! Valid values for the variables are:
//!  - compModule
//!      - EPWM_COUNTER_COMPARE_A - counter compare A.
//!      - EPWM_COUNTER_COMPARE_B - counter compare B.
//!      - EPWM_COUNTER_COMPARE_C - counter compare C.
//!      - EPWM_COUNTER_COMPARE_D - counter compare D.
//!  - loadMode
//!      - EPWM_COMP_LOAD_ON_CNTR_ZERO - load when counter equals zero
//!      - EPWM_COMP_LOAD_ON_CNTR_PERIOD - load when counter equals period
//!      - EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals
//!                                             zero or period
//!      - EPWM_COMP_LOAD_FREEZE  - Freeze shadow to active load
//!      - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO - load when counter equals zero
//!      - EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD -load when counter equals period
//!      - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load when counter equals
//!                                                  zero or period
//!      - EPWM_COMP_LOAD_ON_SYNC_ONLY - load on sync only
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setCounterCompareShadowLoadMode(uint32_t base,
                                     EPWM_CounterCompareModule compModule,
                                     EPWM_CounterCompareLoadMode loadMode)
{
    uint16_t syncModeOffset;
    uint16_t loadModeOffset;
    uint16_t shadowModeOffset;
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    if((compModule == EPWM_COUNTER_COMPARE_A) ||
       (compModule == EPWM_COUNTER_COMPARE_C))
    {
        syncModeOffset = 10U;
        loadModeOffset = 0U;
        shadowModeOffset = 4U;
    }
    else
    {
        syncModeOffset = 12U;
        loadModeOffset = 2U;
        shadowModeOffset = 6U;
    }

    //
    // Get the register offset.  EPWM_O_CMPCTL for A&B or
    // EPWM_O_CMPCTL2 for C&D
    //
    registerOffset = base + 0x8U + ((uint32_t)compModule & 0x1U);

    //
    // Set the appropriate sync and load mode bits and also enable shadow
    // load mode. Shadow to active load can also be frozen.
    //
    (*((volatile uint16_t *)((uintptr_t)(registerOffset)))) = (((*((volatile uint16_t *)((uintptr_t)(registerOffset)))) &
                         ~((0x3U << syncModeOffset) | // Clear sync mode
                           (0x3U << loadModeOffset) | // Clear load mode
                           (0x1U << shadowModeOffset))) | // shadow mode
                         ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
                         (((uint16_t)loadMode & 0x3U) << loadModeOffset)));
}

//*****************************************************************************
//
//! Disable Counter Compare shadow load mode
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the counter compare module.
//!
//! This function disables counter compare shadow load mode.
//! Valid values for the variables are:
//!  - compModule
//!      - EPWM_COUNTER_COMPARE_A - counter compare A.
//!      - EPWM_COUNTER_COMPARE_B - counter compare B.
//!      - EPWM_COUNTER_COMPARE_C - counter compare C.
//!      - EPWM_COUNTER_COMPARE_D - counter compare D.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableCounterCompareShadowLoadMode(uint32_t base,
                                         EPWM_CounterCompareModule compModule)
{
    uint16_t shadowModeOffset;
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    if((compModule == EPWM_COUNTER_COMPARE_A) ||
       (compModule == EPWM_COUNTER_COMPARE_C))
    {
        shadowModeOffset = 4U;
    }
    else
    {
        shadowModeOffset = 6U;
    }

    //
    // Get the register offset.  EPWM_O_CMPCTL for A&B or
    // EPWM_O_CMPCTL2 for C&D
    //
    registerOffset = base + 0x8U + ((uint32_t)compModule & 0x1U);

    //
    // Disable shadow load mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(registerOffset)))) = ((*((volatile uint16_t *)((uintptr_t)(registerOffset)))) |
                             (0x1U << shadowModeOffset));
}

//*****************************************************************************
//
//! Set counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare value module.
//! \param compCount is the counter compare count value.
//!
//! This function sets the counter compare value for counter compare registers.
//! The maximum value for compCount is 0xFFFF.
//! Valid values for compModule are:
//!   - EPWM_COUNTER_COMPARE_A - counter compare A.
//!   - EPWM_COUNTER_COMPARE_B - counter compare B.
//!   - EPWM_COUNTER_COMPARE_C - counter compare C.
//!   - EPWM_COUNTER_COMPARE_D - counter compare D.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule,
                            uint16_t compCount)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    //
    // Get the register offset for the Counter compare
    //
    registerOffset = 0x6AU + (uint16_t)compModule;

    //
    // Write to the counter compare registers.
    //
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
        (compModule == EPWM_COUNTER_COMPARE_B))
    {
        //
        // Write to COMPA or COMPB bits
        //
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset + 0x1U)))) = compCount;
    }
    else
    {
        //
        // Write to COMPC or COMPD bits
        //
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) = compCount;
    }
}

//*****************************************************************************
//
//! Get counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare value module.
//!
//! This function gets the counter compare value for counter compare registers.
//! Valid values for compModule are:
//!   - EPWM_COUNTER_COMPARE_A - counter compare A.
//!   - EPWM_COUNTER_COMPARE_B - counter compare B.
//!   - EPWM_COUNTER_COMPARE_C - counter compare C.
//!   - EPWM_COUNTER_COMPARE_D - counter compare D.
//!
//! \return The counter compare count value.
//
//*****************************************************************************
static inline uint16_t
EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
{
    uint32_t registerOffset;
    uint16_t compCount;

    //
    // Check the arguments
    //
    ;

    //
    // Get the register offset for the Counter compare
    //
    registerOffset = 0x6AU + (uint16_t)compModule;

    //
    // Read from the counter compare registers.
    //
    if((compModule == EPWM_COUNTER_COMPARE_A) ||
        (compModule == EPWM_COUNTER_COMPARE_B))
    {
        //
        // Read COMPA or COMPB bits
        //
        compCount = (uint16_t)(((*((volatile uint32_t *)((uintptr_t)(base + registerOffset)))) &
                     (uint32_t)0xFFFF0000U) >> 16U);
    }
    else
    {
        //
        // Read COMPC or COMPD bits
        //
        compCount = (*((volatile uint16_t *)((uintptr_t)(base + registerOffset))));
    }
    return(compCount);
}

//*****************************************************************************
//
//! Return the counter compare shadow register full status.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare value module.
//!
//! This function returns the counter Compare shadow register full status flag.
//! Valid values for compModule are:
//!   - EPWM_COUNTER_COMPARE_A - counter compare A.
//!   - EPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \return Returns true if the shadow register is full.
//!         Returns false if the shadow register is not full.
//
//*****************************************************************************
static inline _Bool
EPWM_getCounterCompareShadowStatus(uint32_t base,
                                   EPWM_CounterCompareModule compModule)
{
    //
    // Check the arguments
    //
    ;

    //
    // Check the validity of input.
    // COMPA and COMPB are valid input arguments.
    //
    ;

    //
    // Read the value of SHDWAFULL or SHDWBFULL bit
    //
    return(((((*((volatile uint32_t *)((uintptr_t)(base + 0x8U)))) >>
              ((((uint16_t)compModule >> 1U) & 0x1U) + 8U)) &
              0x1U) == 0x1U) ? 1:0);
}

//
// Action Qualifier module related APIs
//
//*****************************************************************************
//
//! Sets the Action Qualifier shadow load mode
//!
//! \param base is the base address of the EPWM module.
//! \param aqModule is the Action Qualifier module value.
//! \param loadMode is the shadow to active load mode.
//!
//! This function enables and sets the Action Qualifier shadow load mode.
//! Valid values for the variables are:
//!  - aqModule
//!      - EPWM_ACTION_QUALIFIER_A - Action Qualifier A.
//!      - EPWM_ACTION_QUALIFIER_B - Action Qualifier B.
//!  - loadMode
//!      - EPWM_AQ_LOAD_ON_CNTR_ZERO - load when counter equals zero
//!      - EPWM_AQ_LOAD_ON_CNTR_PERIOD - load when counter equals period
//!      - EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals
//!                                               zero or period
//!      - EPWM_AQ_LOAD_FREEZE  - Freeze shadow to active load
//!      - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO - load on sync or when counter
//!                                          equals zero
//!      - EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD - load on sync or when counter
//!                                           equals period
//!      - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load on sync or when
//!                                               counter equals zero or period
//!      - EPWM_AQ_LOAD_ON_SYNC_ONLY - load on sync only
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierShadowLoadMode(uint32_t base,
                                      EPWM_ActionQualifierModule aqModule,
                                      EPWM_ActionQualifierLoadMode loadMode)
{
    uint16_t syncModeOffset;
    uint16_t shadowModeOffset;

    //
    // Check the arguments
    //
    ;

    syncModeOffset = 8U + (uint16_t)aqModule;
    shadowModeOffset = 4U + (uint16_t)aqModule;

    //
    // Set the appropriate sync and load mode bits and also enable shadow
    // load mode. Shadow to active load can also be frozen.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) = (((*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) &
                                   (~((0x3U << (uint16_t)aqModule) |
                                   (0x3U << (uint16_t)syncModeOffset))) |
                                   (0x1U << shadowModeOffset)) |
                                   ((((uint16_t)loadMode >> 2U) <<
                                     syncModeOffset) | (((uint16_t)loadMode &
                                    0x3U) << (uint16_t)aqModule)));
}

//*****************************************************************************
//
//! Disable Action Qualifier shadow load mode
//!
//! \param base is the base address of the EPWM module.
//! \param aqModule is the Action Qualifier module value.
//!
//! This function disables the Action Qualifier  shadow load mode.
//! Valid values for the variables are:
//!  - aqModule
//!      - EPWM_ACTION_QUALIFIER_A - Action Qualifier A.
//!      - EPWM_ACTION_QUALIFIER_B - Action Qualifier B.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableActionQualifierShadowLoadMode(uint32_t base,
                                          EPWM_ActionQualifierModule aqModule)
{
    uint16_t shadowModeOffset;

    //
    // Check the arguments
    //
    ;

    shadowModeOffset = 4U + (uint16_t)aqModule;

    //
    // Disable shadow load mode. Action qualifier is loaded on
    // immediate mode only.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) &= ~(1U << shadowModeOffset);
}

//*****************************************************************************
//
//! Set up Action qualifier trigger source for event T1
//!
//! \param base is the base address of the EPWM module.
//! \param trigger sources for Action Qualifier triggers.
//!
//! This function sets up the sources for Action Qualifier event T1.
//! Valid values for trigger are:
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1       - Digital compare event A 1
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2       - Digital compare event A 2
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1       - Digital compare event B 1
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2       - Digital compare event B 2
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1        - Trip zone 1
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2        - Trip zone 2
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3        - Trip zone 3
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierT1TriggerSource(uint32_t base,
                                     EPWM_ActionQualifierTriggerSource trigger)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set T1 trigger source
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U)))) =
         (((*((volatile uint16_t *)((uintptr_t)(base + 0x11U)))) & (~0xFU)) |
          ((uint16_t)trigger));
}

//*****************************************************************************
//
//! Set up Action qualifier trigger source for event T2
//!
//! \param base is the base address of the EPWM module.
//! \param trigger sources for Action Qualifier triggers.
//!
//! This function sets up the sources for Action Qualifier event T2.
//! Valid values for trigger are:
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1       - Digital compare event A 1
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2       - Digital compare event A 2
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1       - Digital compare event B 1
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2       - Digital compare event B 2
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1        - Trip zone 1
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2        - Trip zone 2
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3        - Trip zone 3
//!   - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierT2TriggerSource(uint32_t base,
                                      EPWM_ActionQualifierTriggerSource trigger)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set T2 trigger source
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0x11U)))) & (~0xF0U)) |
           ((uint16_t)trigger << 4U));
}

//*****************************************************************************
//
//! Set up Action qualifier outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param output is the Action Qualifier output.
//! \param event is the event that causes a change in output.
//!
//! This function sets up the Action Qualifier output on ePWM A or ePWMB,
//! depending on the value of epwmOutput, to a value specified by outPut based
//! on the input events - specified by event.
//! The following are valid values for the parameters.
//!   - epwmOutput
//!       - EPWM_AQ_OUTPUT_A          - ePWMxA output
//!       - EPWM_AQ_OUTPUT_B          - ePWMxB output
//!   - output
//!       - EPWM_AQ_OUTPUT_NO_CHANGE  - No change in the output pins
//!       - EPWM_AQ_OUTPUT_LOW        - Set output pins to low
//!       - EPWM_AQ_OUTPUT_HIGH       - Set output pins to High
//!       - EPWM_AQ_OUTPUT_TOGGLE     - Toggle the output pins
//!   - event
//!       - EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO       - Time base counter equals
//!                                                 zero
//!       - EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD     - Time base counter equals
//!                                                 period
//!       - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA    - Time base counter up equals
//!                                                 COMPA
//!       - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA  - Time base counter down
//!                                                 equals COMPA
//!       - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB    - Time base counter up equals
//!                                                 COMPB
//!       - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB  - Time base counter down
//!                                                 equals COMPB
//!       - EPWM_AQ_OUTPUT_ON_T1_COUNT_UP         - T1 event on count up
//!       - EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN       - T1 event on count down
//!       - EPWM_AQ_OUTPUT_ON_T2_COUNT_UP         - T2 event on count up
//!       - EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN       - T2 event on count down
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierAction(uint32_t base,
                              EPWM_ActionQualifierOutputModule epwmOutput,
                              EPWM_ActionQualifierOutput output,
                              EPWM_ActionQualifierOutputEvent event)
{
    uint32_t registerOffset;
    uint32_t registerTOffset;

    //
    // Check the arguments
    //
    ;

    //
    // Get the register offset
    //
    registerOffset = 0x40U + (uint16_t)epwmOutput;
    registerTOffset = 0x41U + (uint16_t)epwmOutput;

    //
    // If the event occurs on T1 or T2 events
    //
    if(((uint16_t)event & 0x1U) == 1U)
    {
        //
        // Write to T1U,T1D,T2U or T2D of AQCTLA2 register
        //
        (*((volatile uint16_t *)((uintptr_t)(base + registerTOffset)))) =
         (((*((volatile uint16_t *)((uintptr_t)(base + registerTOffset)))) & ~(3U << ((uint16_t)event - 1U))) |
          ((uint16_t)output << ((uint16_t)event - 1U)));
    }
    else
    {
        //
        // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register
        //
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~(3U << (uint16_t)event)) |
                 ((uint16_t)output << (uint16_t)event));
    }
}

//*****************************************************************************
//
//! Set up Action qualifier event outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param action is the desired action when the specified event occurs
//!
//! This function sets up the Action Qualifier output on ePWMA or ePWMB,
//! depending on the value of epwmOutput, to a value specified by action.
//! Valid action param values from different time base counter scenarios
//! should be OR'd together to configure complete action for a pwm output.
//! The following are valid values for the parameters.
//!   - epwmOutput
//!       - EPWM_AQ_OUTPUT_A          - ePWMxA output
//!       - EPWM_AQ_OUTPUT_B          - ePWMxB output
//!
//!   - action
//!       - When time base counter equals zero
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_ZERO   - Time base counter equals zero
//!                                             and no change in output pins
//!         - EPWM_AQ_OUTPUT_LOW_ZERO         - Time base counter equals zero
//!                                             and set output pins to low
//!         - EPWM_AQ_OUTPUT_HIGH_ZERO        - Time base counter equals zero
//!                                             and set output pins to high
//!         - EPWM_AQ_OUTPUT_TOGGLE_ZERO      - Time base counter equals zero
//!                                             and toggle the output pins
//!       - When time base counter equals period
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD - Time base counter equals period
//!                                             and no change in output pins
//!         - EPWM_AQ_OUTPUT_LOW_PERIOD       - Time base counter equals period
//!                                             and set output pins to low
//!         - EPWM_AQ_OUTPUT_HIGH_PERIOD      - Time base counter equals period
//!                                             and set output pins to high
//!         - EPWM_AQ_OUTPUT_TOGGLE_PERIOD    - Time base counter equals period
//!                                             and toggle the output pins
//!       - When time base counter equals CMPA during up-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA  - Time base counter up equals
//!                                               COMPA and no change in the
//!                                               output pins
//!         - EPWM_AQ_OUTPUT_LOW_UP_CMPA        - Time base counter up equals
//!                                               COMPA and set output pins low
//!         - EPWM_AQ_OUTPUT_HIGH_UP_CMPA       - Time base counter up equals
//!                                               COMPA and set output pins high
//!         - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA     - Time base counter up equals
//!                                               COMPA and toggle output pins
//!       - When time base counter equals CMPA during down-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA - Time base counter down equals
//!                                                COMPA and no change in the
//!                                                output pins
//!         - EPWM_AQ_OUTPUT_LOW_DOWN_CMPA      - Time base counter down equals
//!                                               COMPA and set output pins low
//!         - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA     - Time base counter down equals
//!                                               COMPA and set output pins high
//!         - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA   - Time base counter down equals
//!                                               COMPA and toggle output pins
//!       - When time base counter equals CMPB during up-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB  - Time base counter up equals
//!                                               COMPB and no change in the
//!                                               output pins
//!         - EPWM_AQ_OUTPUT_LOW_UP_CMPB        - Time base counter up equals
//!                                               COMPB and set output pins low
//!         - EPWM_AQ_OUTPUT_HIGH_UP_CMPB       - Time base counter up equals
//!                                               COMPB and set output pins high
//!         - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB     - Time base counter up equals
//!                                               COMPB and toggle output pins
//!       - When time base counter equals CMPB during down-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB- Time base counter down equals
//!                                               COMPB and no change in the
//!                                               output pins
//!         - EPWM_AQ_OUTPUT_LOW_DOWN_CMPB      - Time base counter down equals
//!                                               COMPB and set output pins low
//!         - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB     - Time base counter down equals
//!                                               COMPB and set output pins high
//!         - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB   - Time base counter down equals
//!                                               COMPB and toggle output pins
//!
//! \b note:  A logical OR of the valid values should be passed as the action
//!           parameter. Single action should be configured for each time base
//!           counter scenario.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierActionComplete(uint32_t base,
                                   EPWM_ActionQualifierOutputModule epwmOutput,
                                   uint16_t action)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    //
    // Get the register offset
    //
    registerOffset = 0x40U + (uint16_t)epwmOutput;

    //
    // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) = (uint16_t)action;
}

//*****************************************************************************
//
//! Set up Additional action qualifier event outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param action is the desired action when the specified event occurs
//!
//! This function sets up the Additional Action Qualifier output on ePWMA or
//! ePWMB depending on the value of epwmOutput, to a value specified by action.
//! Valid action param values from different event scenarios should be OR'd
//! together to configure complete action for a pwm output.
//! The following are valid values for the parameters.
//!   - epwmOutput
//!       - EPWM_AQ_OUTPUT_A          - ePWMxA output
//!       - EPWM_AQ_OUTPUT_B          - ePWMxB output
//!   - action
//!       - When T1 event occurs during up-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1  - T1 event on count up
//!                                             and no change in output pins
//!         - EPWM_AQ_OUTPUT_LOW_UP_T1        - T1 event on count up
//!                                           and set output pins to low
//!         - EPWM_AQ_OUTPUT_HIGH_UP_T1       - T1 event on count up
//!                                           and set output pins to high
//!         - EPWM_AQ_OUTPUT_TOGGLE_UP_T1     - T1 event on count up
//!                                           and toggle the output pins
//!       - When T1 event occurs during down-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1- T1 event on count down
//!                                           and no change in output pins
//!         - EPWM_AQ_OUTPUT_LOW_DOWN_T1      - T1 event on count down
//!                                           and set output pins to low
//!         - EPWM_AQ_OUTPUT_HIGH_DOWN_T1     - T1 event on count down
//!                                           and set output pins to high
//!         - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1   - T1 event on count down
//!                                           and toggle the output pins
//!       - When T2 event occurs during up-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2  - T2 event on count up
//!                                             and no change in output pins
//!         - EPWM_AQ_OUTPUT_LOW_UP_T2        - T2 event on count up
//!                                             and set output pins to low
//!         - EPWM_AQ_OUTPUT_HIGH_UP_T2       - T2 event on count up
//!                                             and set output pins to high
//!         - EPWM_AQ_OUTPUT_TOGGLE_UP_T2     - T2 event on count up
//!                                             and toggle the output pins
//!       - When T2 event occurs during down-count
//!         - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 - T2 event on count down
//!                                              and no change in output pins
//!         - EPWM_AQ_OUTPUT_LOW_DOWN_T2       - T2 event on count down
//!                                              and set output pins to low
//!         - EPWM_AQ_OUTPUT_HIGH_DOWN_T2      - T2 event on count down
//!                                              and set output pins to high
//!         - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2    - T2 event on count down
//!                                              and toggle the output pins
//!
//! \b note:  A logical OR of the valid values should be passed as the action
//!           parameter. Single action should be configured for each event
//!           scenario.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setAdditionalActionQualifierActionComplete(uint32_t base,
                               EPWM_ActionQualifierOutputModule epwmOutput,
                               uint16_t action)
{
    uint32_t registerTOffset;

    //
    // Check the arguments
    //
    ;

    //
    // Get the register offset
    //
    registerTOffset = 0x41U + (uint16_t)epwmOutput;

    //
    // Write to T1U, T1D, T2U or T2D of AQCTLA2 register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + registerTOffset)))) = (uint16_t)action;
}

//*****************************************************************************
//
//! Sets up Action qualifier continuous software load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param mode is the mode for shadow to active load mode.
//!
//! This function sets up the AQCFRSC register load mode for continuous
//! software force reload mode. The software force actions are determined by
//! the EPWM_setActionQualifierContSWForceAction() function.
//! Valid values for mode are:
//!   - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO        - shadow mode load when counter
//!                                               equals zero
//!   - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD      - shadow mode load when counter
//!                                               equals period
//!   - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter
//!                                               equals zero or period
//!   - EPWM_AQ_SW_IMMEDIATE_LOAD               - immediate mode load only
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierContSWForceShadowMode(uint32_t base,
                                             EPWM_ActionQualifierContForce mode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the Action qualifier software action reload mode.
    // Write to RLDCSF bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) & ~0xC0U) |
             ((uint16_t)mode << 6U));
}

//*****************************************************************************
//
//! Triggers a continuous software forced event.
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param output is the Action Qualifier output.
//!
//! This function triggers a continuous software forced Action Qualifier output
//! on ePWM A or B based on the value of epwmOutput.
//! Valid values for the parameters are:
//!   - epwmOutput
//!       - EPWM_AQ_OUTPUT_A          - ePWMxA output
//!       - EPWM_AQ_OUTPUT_B          - ePWMxB output
//!   - output
//!       - EPWM_AQ_SW_DISABLED       - Software forcing disabled.
//!       - EPWM_AQ_SW_OUTPUT_LOW     - Set output pins to low
//!       - EPWM_AQ_SW_OUTPUT_HIGH    - Set output pins to High
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierContSWForceAction(uint32_t base,
                                    EPWM_ActionQualifierOutputModule epwmOutput,
                                    EPWM_ActionQualifierSWOutput output)
{
    //
    // Check the arguments
    //
    ;

    //
    // Initiate a continuous software forced output
    //
    if(epwmOutput == EPWM_AQ_OUTPUT_A)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x49U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0x49U)))) & ~0x3U) |
                 ((uint16_t)output));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x49U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0x49U)))) & ~0xCU) |
                 ((uint16_t)output << 2U)) ;
    }
}

//*****************************************************************************
//
//! Set up one time software forced Action qualifier outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param output is the Action Qualifier output.
//!
//! This function sets up the one time software forced Action Qualifier output
//! on ePWM A or ePWMB, depending on the value of epwmOutput to a value
//! specified by outPut.
//! The following are valid values for the parameters.
//!   - epwmOutput
//!       - EPWM_AQ_OUTPUT_A          - ePWMxA output
//!       - EPWM_AQ_OUTPUT_B          - ePWMxB output
//!   - output
//!       - EPWM_AQ_OUTPUT_NO_CHANGE  - No change in the output pins
//!       - EPWM_AQ_OUTPUT_LOW        - Set output pins to low
//!       - EPWM_AQ_OUTPUT_HIGH       - Set output pins to High
//!       - EPWM_AQ_OUTPUT_TOGGLE     - Toggle the output pins
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierSWAction(uint32_t base,
                                EPWM_ActionQualifierOutputModule epwmOutput,
                                EPWM_ActionQualifierOutput output)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the one time software forced action
    //
    if(epwmOutput == EPWM_AQ_OUTPUT_A)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) =
                    (((*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) & ~0x3U) |
                     ((uint16_t)output));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) =
                    (((*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) & ~0x18U) |
                     ((uint16_t)output << 3U));
    }
}

//*****************************************************************************
//
//! Triggers a one time software forced event on Action qualifier
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//!
//! This function triggers a one time software forced Action Qualifier event
//! on ePWM A or B based on the value of epwmOutput.
//! Valid values for epwmOutput are:
//!   - EPWM_AQ_OUTPUT_A          - ePWMxA output
//!   - EPWM_AQ_OUTPUT_B          - ePWMxB output
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceActionQualifierSWAction(uint32_t base,
                                  EPWM_ActionQualifierOutputModule epwmOutput)
{
    //
    // Check the arguments
    //
    ;

    //
    // Initiate a software forced event
    //
    if(epwmOutput == EPWM_AQ_OUTPUT_A)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) |= 0x4U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x47U)))) |= 0x20U;
    }
}

//
// Dead Band Module related APIs
//
//*****************************************************************************
//
//! Sets Dead Band signal output swap mode.
//!
//! \param base is the base address of the EPWM module.
//! \param output is the ePWM Dead Band output.
//! \param enableSwapMode is the output swap mode.
//!
//! This function sets up the output signal swap mode. For example if the
//! output variable is set to EPWM_DB_OUTPUT_A and enableSwapMode is true, then
//! the ePWM A output gets its signal from the ePWM B signal path. Valid values
//! for the input variables are:
//!  - output
//!      - EPWM_DB_OUTPUT_A   - ePWM output A
//!      - EPWM_DB_OUTPUT_B   - ePWM output B
//!  - enableSwapMode
//!      - true     - the output is swapped
//!      - false    - the output and the signal path are the same.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output,
                               _Bool enableSwapMode)
{
    uint16_t mask;

    //
    // Check the arguments
    //
    ;

    mask = (uint16_t)1U << ((uint16_t)output + 12U);

    if(enableSwapMode)
    {
        //
        // Set the appropriate outswap bit to swap output
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) | mask);
    }
    else
    {
        //
        // Clear the appropriate outswap bit to disable output swap
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~mask);
    }
}

//*****************************************************************************
//
//! Sets Dead Band signal output mode.
//!
//! \param base is the base address of the EPWM module.
//! \param delayMode is the Dead Band delay type.
//! \param enableDelayMode is the dead band delay mode.
//!
//! This function sets up the dead band delay mode. The delayMode variable
//! determines if the applied delay is Rising Edge or Falling Edge. The
//! enableDelayMode determines if a dead band delay should be applied.
//! Valid values for the variables are:
//!  - delayMode
//!      - EPWM_DB_RED   - Rising Edge delay
//!      - EPWM_DB_FED   - Falling Edge delay
//!  - enableDelayMode
//!      - true     - Falling edge or Rising edge delay is applied.
//!      - false    - Dead Band delay is bypassed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode,
                          _Bool enableDelayMode)
{
    uint16_t mask;

    //
    // Check the arguments
    //
    ;

    mask = 1U << ((uint16_t)(delayMode + 0U));

    if(enableDelayMode)
    {
         //
         // Set the appropriate outmode bit to enable Dead Band delay
         //
         (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) | mask);
    }
    else
    {
        //
        // Clear the appropriate outswap bit to disable output swap
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~ mask);
    }
}

//*****************************************************************************
//
//! Sets Dead Band delay polarity.
//!
//! \param base is the base address of the EPWM module.
//! \param delayMode is the Dead Band delay type.
//! \param polarity is the polarity of the delayed signal.
//!
//! This function sets up the polarity as determined by the variable polarity
//! of the Falling Edge or Rising Edge delay depending on the value of
//! delayMode. Valid values for the variables are:
//!   - delayMode
//!       - EPWM_DB_RED   - Rising Edge delay
//!       - EPWM_DB_FED   - Falling Edge delay
//!   - polarity
//!       - EPWM_DB_POLARITY_ACTIVE_HIGH   - polarity is not inverted.
//!       - EPWM_DB_POLARITY_ACTIVE_LOW    - polarity is inverted.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandDelayPolarity(uint32_t base,
                              EPWM_DeadBandDelayMode delayMode,
                              EPWM_DeadBandPolarity polarity)
{
    uint16_t shift;

    //
    // Check the arguments
    //
    ;

    shift = (((uint16_t)delayMode ^ 0x1U) + 2U);

    //
    // Set the appropriate polsel bits for dead band polarity
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
                       (((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~ (1U << shift)) |
                        ((uint16_t)polarity << shift));
}

//*****************************************************************************
//
//! Sets Rising Edge Dead Band delay input.
//!
//! \param base is the base address of the EPWM module.
//! \param input is the input signal to the dead band.
//!
//! This function sets up the rising Edge delay input signal.
//! Valid values for input are:
//!     - EPWM_DB_INPUT_EPWMA   - Input signal is ePWMA( Valid for both Falling
//!                                  Edge and Rising Edge)
//!     - EPWM_DB_INPUT_EPWMB   - Input signal is ePWMB( Valid for both Falling
//!                                  Edge and Rising Edge)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the Rising Edge Delay input
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~(1U << (4U))) |
             (input << 4U));
}

//*****************************************************************************
//
//! Sets Dead Band delay input.
//!
//! \param base is the base address of the EPWM module.
//! \param input is the input signal to the dead band.
//!
//! This function sets up the rising Edge delay input signal.
//! Valid values for input are:
//!   - EPWM_DB_INPUT_EPWMA   - Input signal is ePWMA(Valid for both Falling
//!                                Edge and Rising Edge)
//!   - EPWM_DB_INPUT_EPWMB   - Input signal is ePWMB(Valid for both Falling
//!                                Edge and Rising Edge)
//!   - EPWM_DB_INPUT_DB_RED  - Input signal is the output of Rising
//!                                Edge delay.
//!                               (Valid only for Falling Edge delay)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
{
    //
    // Check the arguments
    //
    ;
    ;

    if(input == 2U)
    {
        //
        // Set the Falling Edge Delay input
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) |= 0x4000U;
    }
    else
    {
        //
        // Set the Falling Edge Delay input
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) &= ~0x4000U;

        //
        // Set the Rising Edge Delay input
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
        (((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~(1U << (4U + 1U))) |
         (input << (4U + 1U)));
    }
}

//*****************************************************************************
//
//! Set the Dead Band control shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadMode is the shadow to active load mode.
//!
//! This function enables and sets the Dead Band control register shadow
//! load mode.
//! Valid values for the \e loadMode parameter are:
//!     - EPWM_DB_LOAD_ON_CNTR_ZERO         - load when counter equals zero.
//!     - EPWM_DB_LOAD_ON_CNTR_PERIOD       - load when counter equals period.
//!     - EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD  - load when counter equals zero or
//!                                            period.
//!     - EPWM_DB_LOAD_FREEZE                - Freeze shadow to active load.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandControlShadowLoadMode(uint32_t base,
                                      EPWM_DeadBandControlLoadMode loadMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable the shadow mode and setup the load event
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xDU)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0xDU)))) & ~0x3U) |
           (0x4U | (uint16_t)loadMode));
}

//*****************************************************************************
//
//! Disable Dead Band control shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Dead Band control register shadow
//! load mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable the shadow load mode. Only immediate load mode only.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xDU)))) =
                 ((*((volatile uint16_t *)((uintptr_t)(base + 0xDU)))) & ~0x4U);
}

//*****************************************************************************
//
//! Set the RED (Rising Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadMode is the shadow to active load event.
//!
//! This function sets the Rising Edge Delay register shadow load mode.
//! Valid values for the \e loadMode parameter are:
//!     - EPWM_RED_LOAD_ON_CNTR_ZERO        - load when counter equals zero.
//!     - EPWM_RED_LOAD_ON_CNTR_PERIOD      - load when counter equals period.
//!     - EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or
//!                                           period.
//!     - EPWM_RED_LOAD_FREEZE               - Freeze shadow to active load.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base,
                                         EPWM_RisingEdgeDelayLoadMode loadMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable the shadow mode. Set-up the load mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
               (((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~0xC0U) |
                ((uint16_t)0x400U |
                ((uint16_t)loadMode << 6U)));

}

//*****************************************************************************
//
//! Disable the RED (Rising Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Rising Edge Delay register shadow load mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable the shadow mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
                   ((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~0x400U);

}

//*****************************************************************************
//
//! Set the FED (Falling Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadMode is the shadow to active load event.
//!
//! This function enables and sets the Falling Edge Delay register shadow load
//! mode. Valid values for the \e loadMode parameters are:
//!     - EPWM_FED_LOAD_ON_CNTR_ZERO        - load when counter equals zero.
//!     - EPWM_FED_LOAD_ON_CNTR_PERIOD      - load when counter equals period.
//!     - EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or
//!                                            period.
//!     - EPWM_FED_LOAD_FREEZE               - Freeze shadow to active load.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base,
                                        EPWM_FallingEdgeDelayLoadMode loadMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable the shadow mode. Setup the load mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~0x300U) |
                (0x800U |
                ((uint16_t)loadMode << 8U)));

}

//*****************************************************************************
//
//! Disables the FED (Falling Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Falling Edge Delay register shadow load mode.
//! Valid values for the parameters are:
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable the shadow mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
              ((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~0x800U);
}

//*****************************************************************************
//
//! Sets Dead Band Counter clock rate.
//!
//! \param base is the base address of the EPWM module.
//! \param clockMode is the Dead Band counter clock mode.
//!
//! This function sets up the Dead Band counter clock rate with respect to
//! TBCLK (ePWM time base counter).
//! Valid values for clockMode are:
//!   - EPWM_DB_COUNTER_CLOCK_FULL_CYCLE  -Dead band counter runs at TBCLK
//!                                           (ePWM Time Base Counter) rate.
//!   - EPWM_DB_COUNTER_CLOCK_HALF_CYCLE  -Dead band counter runs at 2*TBCLK
//!                                         (twice ePWM Time Base Counter)rate.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandCounterClock(uint32_t base,
                             EPWM_DeadBandClockMode clockMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the DB clock mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & ~0x8000U) |
                 ((uint16_t)clockMode << 15U));
}

//*****************************************************************************
//
//! Set ePWM RED count
//!
//! \param base is the base address of the EPWM module.
//! \param redCount is the RED(Rising Edge Delay) count.
//!
//! This function sets the RED (Rising Edge Delay) count value.
//! The value of redCount should be less than 0x4000U.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the RED (Rising Edge Delay) count
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x51U)))) = redCount;
}

//*****************************************************************************
//
//! Set ePWM FED count
//!
//! \param base is the base address of the EPWM module.
//! \param fedCount is the FED(Falling Edge Delay) count.
//!
//! This function sets the FED (Falling Edge Delay) count value.
//! The value of fedCount should be less than 0x4000U.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the RED (Rising Edge Delay) count
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x53U)))) = fedCount;
}

//
// Chopper module related APIs
//
//*****************************************************************************
//
//! Enable chopper mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables ePWM chopper module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableChopper(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set CHPEN bit. Enable Chopper
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Disable chopper mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables ePWM chopper module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableChopper(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear CHPEN bit. Disable Chopper
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &= ~0x1U;
}

//*****************************************************************************
//
//! Set chopper duty cycle.
//!
//! \param base is the base address of the EPWM module.
//! \param dutyCycleCount is the chopping clock duty cycle count.
//!
//! This function sets the chopping clock duty cycle. The value of
//! dutyCycleCount should be less than 7. The dutyCycleCount value is converted
//! to the actual chopper duty cycle value base on the following equation:
//!   chopper duty cycle = (dutyCycleCount + 1) / 8
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the chopper duty cycle
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) =
               (((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) & ~0x700U) |
                (dutyCycleCount << 8U));
}

//*****************************************************************************
//
//! Set chopper clock frequency scaler.
//!
//! \param base is the base address of the EPWM module.
//! \param freqDiv is the chopping clock frequency divider.
//!
//! This function sets the scaler for the chopping clock frequency. The value
//! of freqDiv should be less than 8. The chopping clock frequency is altered
//! based on the following equation.
//!   chopper clock frequency = SYSCLKOUT / ( 1 + freqDiv)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the chopper clock
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) =
                    (((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &
                      ~(uint16_t)0xE0U) |
                       (freqDiv << 5U));
}

//*****************************************************************************
//
//! Set chopper clock frequency scaler.
//!
//! \param base is the base address of the EPWM module.
//! \param firstPulseWidth is the width of the first pulse.
//!
//! This function sets the first pulse width of chopper output waveform. The
//! value of firstPulseWidth should be less than 0x10. The value of the first
//! pulse width in seconds is given using the following equation:
//!     first pulse width = 1 / (((firstPulseWidth + 1) * SYSCLKOUT)/8)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the chopper clock
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) =
              (((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &
               ~(uint16_t)0x1EU) |
               (firstPulseWidth << 1U));
}

//
// Trip Zone module related APIs
//
//*****************************************************************************
//
//! Enables Trip Zone signal.
//!
//! \param base is the base address of the EPWM module.
//! \param tzSignal is the Trip Zone signal.
//!
//! This function enables the Trip Zone signals specified by tzSignal as a
//! source for the Trip Zone module.
//! Valid values for tzSignal are:
//!   - EPWM_TZ_SIGNAL_CBC1       - TZ1 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC2       - TZ2 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC3       - TZ3 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC4       - TZ4 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC5       - TZ5 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC6       - TZ6 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_DCAEVT2    - DCAEVT2 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_DCBEVT2    - DCBEVT2 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_OSHT1      - One-shot TZ1
//!   - EPWM_TZ_SIGNAL_OSHT2      - One-shot TZ2
//!   - EPWM_TZ_SIGNAL_OSHT3      - One-shot TZ3
//!   - EPWM_TZ_SIGNAL_OSHT4      - One-shot TZ4
//!   - EPWM_TZ_SIGNAL_OSHT5      - One-shot TZ5
//!   - EPWM_TZ_SIGNAL_OSHT6      - One-shot TZ6
//!   - EPWM_TZ_SIGNAL_DCAEVT1    - One-shot DCAEVT1
//!   - EPWM_TZ_SIGNAL_DCBEVT1    - One-shot DCBEVT1
//!
//! \b note:  A logical OR of the valid values can be passed as the tzSignal
//!           parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneSignals(uint32_t base, uint16_t tzSignal)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the trip zone bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x80U)))) |= tzSignal;
    __edis();
}

//*****************************************************************************
//
//! Disables Trip Zone signal.
//!
//! \param base is the base address of the EPWM module.
//! \param tzSignal is the Trip Zone signal.
//!
//! This function disables the Trip Zone signal specified by tzSignal as a
//! source for the Trip Zone module.
//! Valid values for tzSignal are:
//!   - EPWM_TZ_SIGNAL_CBC1       - TZ1 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC2       - TZ2 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC3       - TZ3 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC4       - TZ4 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC5       - TZ5 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_CBC6       - TZ6 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_DCAEVT2    - DCAEVT2 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_DCBEVT2    - DCBEVT2 Cycle By Cycle
//!   - EPWM_TZ_SIGNAL_OSHT1      - One-shot TZ1
//!   - EPWM_TZ_SIGNAL_OSHT2      - One-shot TZ2
//!   - EPWM_TZ_SIGNAL_OSHT3      - One-shot TZ3
//!   - EPWM_TZ_SIGNAL_OSHT4      - One-shot TZ4
//!   - EPWM_TZ_SIGNAL_OSHT5      - One-shot TZ5
//!   - EPWM_TZ_SIGNAL_OSHT6      - One-shot TZ6
//!   - EPWM_TZ_SIGNAL_DCAEVT1    - One-shot DCAEVT1
//!   - EPWM_TZ_SIGNAL_DCBEVT1    - One-shot DCBEVT1
//!
//! \b note:  A logical OR of the valid values can be passed as the tzSignal
//!           parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableTripZoneSignals(uint32_t base, uint16_t tzSignal)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear the trip zone bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x80U)))) &= ~tzSignal;
    __edis();
}

//*****************************************************************************
//
//! Set Digital compare conditions that cause Trip Zone event.
//!
//! \param base is the base address of the EPWM module.
//! \param dcType is the Digital compare output type.
//! \param dcEvent is the Digital Compare output event.
//!
//! This function sets up the Digital Compare output Trip Zone event sources.
//! The dcType variable specifies the event source to be whether Digital
//! Compare output A or Digital Compare output B. The dcEvent parameter
//! specifies the event that causes Trip Zone.
//! Valid values for the parameters are:
//!  - dcType
//!      - EPWM_TZ_DC_OUTPUT_A1     - Digital Compare output 1 A
//!      - EPWM_TZ_DC_OUTPUT_A2     - Digital Compare output 2 A
//!      - EPWM_TZ_DC_OUTPUT_B1     - Digital Compare output 1 B
//!      - EPWM_TZ_DC_OUTPUT_B2     - Digital Compare output 2 B
//!  - dcEvent
//!      - EPWM_TZ_EVENT_DC_DISABLED         - Event Trigger is disabled
//!      - EPWM_TZ_EVENT_DCXH_LOW            - Trigger event when DCxH low
//!      - EPWM_TZ_EVENT_DCXH_HIGH           - Trigger event when DCxH high
//!      - EPWM_TZ_EVENT_DCXL_LOW            - Trigger event when DCxL low
//!      - EPWM_TZ_EVENT_DCXL_HIGH           - Trigger event when DCxL high
//!      - EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW  - Trigger event when DCxL high
//!                                            DCxH low
//!
//!  \note x in DCxH/DCxL represents DCAH/DCAL or DCBH/DCBL
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base,
                                 EPWM_TripZoneDigitalCompareOutput dcType,
                                 EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set Digital Compare Events conditions that cause a Digital Compare trip
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x82U)))) =
           (((*((volatile uint16_t *)((uintptr_t)(base + 0x82U)))) & ~(0x7U << (uint16_t)dcType)) |
            ((uint16_t)dcEvent << (uint16_t)dcType));
    __edis();
}

//*****************************************************************************
//
//! Enable advanced Trip Zone event Action.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the advanced actions of the Trip Zone events. The
//! advanced features combine the trip zone events with the direction of the
//! counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneAdvAction(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable Advanced feature. Set ETZE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x85U)))) |= 0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Disable advanced Trip Zone event Action.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the advanced actions of the Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableTripZoneAdvAction(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable Advanced feature. clear ETZE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x85U)))) &= ~0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Set Trip Zone Action.
//!
//! \param base is the base address of the EPWM module.
//! \param tzEvent is the Trip Zone event type.
//! \param tzAction is the Trip zone Action.
//!
//! This function sets the Trip Zone Action to be taken when a Trip Zone event
//! occurs.
//! Valid values for the parameters are:
//!  - tzEvent
//!      - EPWM_TZ_ACTION_EVENT_DCBEVT2  - DCBEVT2 (Digital Compare B event 2)
//!      - EPWM_TZ_ACTION_EVENT_DCBEVT1  - DCBEVT1 (Digital Compare B event 1)
//!      - EPWM_TZ_ACTION_EVENT_DCAEVT2  - DCAEVT2 (Digital Compare A event 2)
//!      - EPWM_TZ_ACTION_EVENT_DCAEVT1  - DCAEVT1 (Digital Compare A event 1)
//!      - EPWM_TZ_ACTION_EVENT_TZB      - TZ1 - TZ6, DCBEVT2, DCBEVT1
//!      - EPWM_TZ_ACTION_EVENT_TZA      - TZ1 - TZ6, DCAEVT2, DCAEVT1
//!  - tzAction
//!      - EPWM_TZ_ACTION_HIGH_Z         - high impedance output
//!      - EPWM_TZ_ACTION_HIGH           - high output
//!      - EPWM_TZ_ACTION_LOW            - low low
//!      - EPWM_TZ_ACTION_DISABLE        - disable action
//!
//! \note Disable the advanced Trip Zone event using
//!       EPWM_disableTripZoneAdvAction()  before calling this function.
//! \note This function operates on both ePWMA and ePWMB depending on the
//!       tzEvent parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent,
                       EPWM_TripZoneAction tzAction)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the Action for Trip Zone events
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x84U)))) =
         (((*((volatile uint16_t *)((uintptr_t)(base + 0x84U)))) & ~(0x3U << (uint16_t)tzEvent)) |
          ((uint16_t)tzAction << (uint16_t)tzEvent)) ;
    __edis();
}

//*****************************************************************************
//
//! Set Advanced Trip Zone Action.
//!
//! \param base is the base address of the EPWM module.
//! \param tzAdvEvent is the Trip Zone event type.
//! \param tzAdvAction is the Trip zone Action.
//!
//! This function sets the Advanced Trip Zone Action to be taken when an
//! advanced Trip Zone event occurs.
//!
//! Valid values for the parameters are:
//!  - tzAdvEvent
//!      - EPWM_TZ_ADV_ACTION_EVENT_TZB_D  - TZ1 - TZ6, DCBEVT2, DCBEVT1 while
//!                                             counting down
//!      - EPWM_TZ_ADV_ACTION_EVENT_TZB_U  - TZ1 - TZ6, DCBEVT2, DCBEVT1 while
//!                                             counting up
//!      - EPWM_TZ_ADV_ACTION_EVENT_TZA_D  - TZ1 - TZ6, DCAEVT2, DCAEVT1 while
//!                                             counting down
//!      - EPWM_TZ_ADV_ACTION_EVENT_TZA_U  - TZ1 - TZ6, DCAEVT2, DCAEVT1 while
//!                                             counting up
//!  - tzAdvAction
//!      - EPWM_TZ_ADV_ACTION_HIGH_Z    - high impedance output
//!      - EPWM_TZ_ADV_ACTION_HIGH      - high voltage state
//!      - EPWM_TZ_ADV_ACTION_LOW       - low voltage state
//!      - EPWM_TZ_ADV_ACTION_TOGGLE    - Toggle output
//!      - EPWM_TZ_ADV_ACTION_DISABLE   - disable action
//!
//! \note This function enables the advanced Trip Zone event.
//!
//! \note This function operates on both ePWMA and ePWMB depending on the
//!       tzAdvEvent  parameter.
//! \note Advanced Trip Zone events take into consideration the direction of
//!       the counter in addition to Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent,
                          EPWM_TripZoneAdvancedAction tzAdvAction)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the Advanced Action for Trip Zone events
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x85U)))) =
       (((*((volatile uint16_t *)((uintptr_t)(base + 0x85U)))) & ~(0x7U << (uint16_t)tzAdvEvent)) |
        ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent));

    (*((volatile uint16_t *)((uintptr_t)(base + 0x85U)))) |= 0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Set Advanced Digital Compare Trip Zone Action on ePWMA.
//!
//! \param base is the base address of the EPWM module.
//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type.
//! \param tzAdvDCAction is the Digital Compare Trip zone Action.
//!
//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be
//! taken on ePWMA when an advanced Digital Compare Trip Zone A event occurs.
//! Valid values for the parameters are:
//!  - tzAdvDCEvent
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D  - Digital Compare event A2 while
//!                                                 counting down
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U  - Digital Compare event A2 while
//!                                                 counting up
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D  - Digital Compare event A1 while
//!                                                 counting down
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U  - Digital Compare event A1 while
//!                                                 counting up
//!  - tzAdvDCAction
//!      - EPWM_TZ_ADV_ACTION_HIGH_Z    - high impedance output
//!      - EPWM_TZ_ADV_ACTION_HIGH      - high voltage state
//!      - EPWM_TZ_ADV_ACTION_LOW       - low voltage state
//!      - EPWM_TZ_ADV_ACTION_TOGGLE    - Toggle output
//!      - EPWM_TZ_ADV_ACTION_DISABLE   - disable action
//!
//! \note This function enables the advanced Trip Zone event.
//!
//! \note Advanced Trip Zone events take into consideration the direction of
//!       the counter in addition to Digital Compare Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base,
                              EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
                              EPWM_TripZoneAdvancedAction tzAdvDCAction)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the Advanced Action for Trip Zone events
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x86U)))) =
      (((*((volatile uint16_t *)((uintptr_t)(base + 0x86U)))) & ~(0x7U << (uint16_t)tzAdvDCEvent)) |
       ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent));

    (*((volatile uint16_t *)((uintptr_t)(base + 0x85U)))) |= 0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Set Advanced Digital Compare Trip Zone Action on ePWMB.
//!
//! \param base is the base address of the EPWM module.
//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type.
//! \param tzAdvDCAction is the Digital Compare Trip zone Action.
//!
//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be
//! taken on ePWMB when an advanced Digital Compare Trip Zone B event occurs.
//! Valid values for the parameters are:
//!  - tzAdvDCEvent
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D  - Digital Compare event B2 while
//!                                                 counting down
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U  - Digital Compare event B2 while
//!                                                 counting up
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D  - Digital Compare event B1 while
//!                                                 counting down
//!      - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U  - Digital Compare event B1 while
//!                                                 counting up
//!  - tzAdvDCAction
//!      - EPWM_TZ_ADV_ACTION_HIGH_Z    - high impedance output
//!      - EPWM_TZ_ADV_ACTION_HIGH      - high voltage state
//!      - EPWM_TZ_ADV_ACTION_LOW       - low voltage state
//!      - EPWM_TZ_ADV_ACTION_TOGGLE    - Toggle output
//!      - EPWM_TZ_ADV_ACTION_DISABLE   - disable action
//!
//! \note This function enables the advanced Trip Zone event.
//!
//! \note Advanced Trip Zone events take into consideration the direction of
//!       the counter in addition to Digital Compare Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base,
                              EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
                              EPWM_TripZoneAdvancedAction tzAdvDCAction)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the Advanced Action for Trip Zone events
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x87U)))) =
     (((*((volatile uint16_t *)((uintptr_t)(base + 0x87U)))) & ~(0x7U << (uint16_t)tzAdvDCEvent)) |
      ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent));

    (*((volatile uint16_t *)((uintptr_t)(base + 0x85U)))) |= 0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Enable Trip Zone interrupts.
//!
//! \param base is the base address of the EPWM module.
//! \param tzInterrupt is the Trip Zone interrupt.
//!
//! This function enables the Trip Zone interrupts.
//! Valid values for tzInterrupt are:
//!   - EPWM_TZ_INTERRUPT_CBC     - Trip Zones Cycle By Cycle interrupt
//!   - EPWM_TZ_INTERRUPT_OST     - Trip Zones One Shot interrupt
//!   - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt
//!   - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt
//!   - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt
//!   - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt
//!
//! \b note:  A logical OR of the valid values can be passed as the tzInterrupt
//!           parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Enable Trip zone interrupts
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8DU)))) |= tzInterrupt;
    __edis();
}

//*****************************************************************************
//
//! Disable Trip Zone interrupts.
//!
//! \param base is the base address of the EPWM module.
//! \param tzInterrupt is the Trip Zone interrupt.
//!
//! This function disables the Trip Zone interrupts.
//! Valid values for tzInterrupt are:
//!   - EPWM_TZ_INTERRUPT_CBC     - Trip Zones Cycle By Cycle interrupt
//!   - EPWM_TZ_INTERRUPT_OST    - Trip Zones One Shot interrupt
//!   - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt
//!   - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt
//!   - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt
//!   - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt
//!
//! \b note:  A logical OR of the valid values can be passed as the tzInterrupt
//!           parameter.
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Disable Trip zone interrupts
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8DU)))) &= ~tzInterrupt;
    __edis();
}

//*****************************************************************************
//
//! Gets the Trip Zone status flag
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the Trip Zone status flag.
//!
//! \return The function returns the following or the bitwise OR value
//!         of the following values.
//!         - EPWM_TZ_INTERRUPT    - Trip Zone interrupt was generated
//!                                  due to the following TZ events.
//!         - EPWM_TZ_FLAG_CBC     - Trip Zones Cycle By Cycle event status flag
//!         - EPWM_TZ_FLAG_OST     - Trip Zones One Shot event status flag
//!         - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 status flag
//!         - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 status flag
//!         - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 status flag
//!         - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 status flag
//
//***************************************************************************
static inline uint16_t
EPWM_getTripZoneFlagStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the Trip zone flag status
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x93U)))) & 0x7FU);
}

//*****************************************************************************
//
//! Gets the Trip Zone Cycle by Cycle flag status
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the specific Cycle by Cycle Trip Zone flag
//! status.
//!
//! \return The function returns the following values.
//!           - EPWM_TZ_CBC_FLAG_1     - CBC 1 status flag
//!           - EPWM_TZ_CBC_FLAG_2     - CBC 2 status flag
//!           - EPWM_TZ_CBC_FLAG_3     - CBC 3 status flag
//!           - EPWM_TZ_CBC_FLAG_4     - CBC 4 status flag
//!           - EPWM_TZ_CBC_FLAG_5     - CBC 5 status flag
//!           - EPWM_TZ_CBC_FLAG_6     - CBC 6 status flag
//!           - EPWM_TZ_CBC_FLAG_DCAEVT2  - CBC status flag for Digital compare
//!                                                event A2
//!           - EPWM_TZ_CBC_FLAG_DCBEVT2  - CBC status flag for Digital compare
//!                                                event B2
//
//***************************************************************************
static inline uint16_t
EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the Cycle By Cycle Trip zone flag status
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x94U)))) & 0xFFU);
}

//*****************************************************************************
//
//! Gets the Trip Zone One Shot flag status
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the specific One Shot Trip Zone flag status.
//!
//! \return The function returns the bitwise OR of the following flags.
//!           - EPWM_TZ_OST_FLAG_OST1     - OST status flag for OST1
//!           - EPWM_TZ_OST_FLAG_OST2     - OST status flag for OST2
//!           - EPWM_TZ_OST_FLAG_OST3     - OST status flag for OST3
//!           - EPWM_TZ_OST_FLAG_OST4     - OST status flag for OST4
//!           - EPWM_TZ_OST_FLAG_OST5     - OST status flag for OST5
//!           - EPWM_TZ_OST_FLAG_OST6     - OST status flag for OST6
//!           - EPWM_TZ_OST_FLAG_DCAEVT1  - OST status flag for Digital
//!                                                 compare event A1
//!           - EPWM_TZ_OST_FLAG_DCBEVT1  - OST status flag for Digital
//!                                                 compare event B1
//
//***************************************************************************
static inline uint16_t
EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the One Shot Trip zone flag status
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x95U)))) & 0xFFU);
}

//*****************************************************************************
//
//! Set the Trip Zone CBC pulse clear event.
//!
//! \param base is the base address of the EPWM module.
//! \param clearEvent is the CBC trip zone clear event.
//!
//! This function set the event which automatically clears the
//! CBC (Cycle by Cycle) latch.
//! Valid values for clearEvent are:
//!   - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO         - Clear CBC pulse when counter
//!                                                  equals zero
//!   - EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD       - Clear CBC pulse when counter
//!                                                  equals period
//!   - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD  - Clear CBC pulse when counter
//!                                                  equals zero or period
//!
//!  \return None.
//
//**************************************************************************
static inline void
EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base,
                                 EPWM_CycleByCycleTripZoneClearMode clearEvent)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the Cycle by Cycle Trip Latch mode
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x97U)))) =
                 (((*((volatile uint16_t *)((uintptr_t)(base + 0x97U)))) & ~0xC000U) |
                  ((uint16_t)clearEvent << 14U));
    __edis();
}

//*****************************************************************************
//
//! Clear Trip Zone flag
//!
//! \param base is the base address of the EPWM module.
//! \param tzFlags is the Trip Zone flags.
//!
//! This function clears the Trip Zone flags
//! Valid values for tzFlags are:
//!   - EPWM_TZ_INTERRUPT    - Global Trip Zone interrupt flag
//!   - EPWM_TZ_FLAG_CBC     - Trip Zones Cycle By Cycle flag
//!   - EPWM_TZ_FLAG_OST     - Trip Zones One Shot flag
//!   - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 flag
//!   - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 flag
//!   - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 flag
//!   - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 flag
//!
//! \b note: A bitwise OR of the valid values can be passed as the tzFlags
//! parameter.
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Clear Trip zone event flag
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x97U)))) |= tzFlags;
    __edis();
}

//*****************************************************************************
//
//! Clear the Trip Zone Cycle by Cycle flag.
//!
//! \param base is the base address of the EPWM module.
//! \param tzCBCFlags is the CBC flag to be cleared.
//!
//! This function clears the specific Cycle by Cycle Trip Zone flag.
//! The following are valid values for tzCBCFlags.
//!   - EPWM_TZ_CBC_FLAG_1     - CBC 1 flag
//!   - EPWM_TZ_CBC_FLAG_2     - CBC 2 flag
//!   - EPWM_TZ_CBC_FLAG_3     - CBC 3 flag
//!   - EPWM_TZ_CBC_FLAG_4     - CBC 4 flag
//!   - EPWM_TZ_CBC_FLAG_5     - CBC 5 flag
//!   - EPWM_TZ_CBC_FLAG_6     - CBC 6 flag
//!   - EPWM_TZ_CBC_FLAG_DCAEVT2  - CBC flag Digital compare
//!                                         event A2
//!   - EPWM_TZ_CBC_FLAG_DCBEVT2  - CBC flag Digital compare
//!                                         event B2
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Clear the Cycle By Cycle Trip zone flag
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x98U)))) |= tzCBCFlags;
    __edis();
}

//*****************************************************************************
//
//! Clear the Trip Zone One Shot flag.
//!
//! \param base is the base address of the EPWM module.
//! \param tzOSTFlags is the OST flags to be cleared.
//!
//! This function clears the specific One Shot (OST) Trip Zone flag.
//! The following are valid values for tzOSTFlags.
//!  - EPWM_TZ_OST_FLAG_OST1      - OST flag for OST1
//!  - EPWM_TZ_OST_FLAG_OST2      - OST flag for OST2
//!  - EPWM_TZ_OST_FLAG_OST3      - OST flag for OST3
//!  - EPWM_TZ_OST_FLAG_OST4      - OST flag for OST4
//!  - EPWM_TZ_OST_FLAG_OST5      - OST flag for OST5
//!  - EPWM_TZ_OST_FLAG_OST6      - OST flag for OST6
//!  - EPWM_TZ_OST_FLAG_DCAEVT1   - OST flag for Digital compare event A1
//!  - EPWM_TZ_OST_FLAG_DCBEVT1   - OST flag for Digital compare event B1
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Clear the Cycle By Cycle Trip zone flag
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x99U)))) |= tzOSTFlags;
    __edis();
}

//*****************************************************************************
//
//! Force Trip Zone events.
//!
//! \param base is the base address of the EPWM module.
//! \param tzForceEvent is the forced Trip Zone event.
//!
//! This function forces a Trip Zone event.
//! Valid values for tzForceEvent are:
//!   - EPWM_TZ_FORCE_EVENT_CBC     - Force Trip Zones Cycle By Cycle event
//!   - EPWM_TZ_FORCE_EVENT_OST     - Force Trip Zones One Shot Event
//!   - EPWM_TZ_FORCE_EVENT_DCAEVT1 - Force Digital Compare A Event 1
//!   - EPWM_TZ_FORCE_EVENT_DCAEVT2 - Force Digital Compare A Event 2
//!   - EPWM_TZ_FORCE_EVENT_DCBEVT1 - Force Digital Compare B Event 1
//!   - EPWM_TZ_FORCE_EVENT_DCBEVT2 - Force Digital Compare B Event 2
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Force a Trip Zone event
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9BU)))) |= tzForceEvent;
    __edis();
}

//
// Event Trigger related APIs
//
//*****************************************************************************
//
//! Enable ePWM interrupt.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the ePWM interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableInterrupt(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable ePWM interrupt
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) |= 0x8U;
}

//*****************************************************************************
//
//! disable ePWM interrupt.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the ePWM interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableInterrupt(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable ePWM interrupt
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) &= ~0x8U;
}

//*****************************************************************************
//
//! Sets the ePWM interrupt source.
//!
//! \param base is the base address of the EPWM module.
//! \param interruptSource is the ePWM interrupt source.
//!
//! This function sets the ePWM interrupt source.
//! Valid values for interruptSource are:
//!   - EPWM_INT_TBCTR_DISABLED       - Time-base counter is disabled
//!   - EPWM_INT_TBCTR_ZERO           - Time-base counter equal to zero
//!   - EPWM_INT_TBCTR_PERIOD         - Time-base counter equal to period
//!   - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or
//!                                     period
//!   - EPWM_INT_TBCTR_U_CMPx         - Where x is A,B,C or D
//!                                     Time-base counter equal to CMPA, CMPB,
//!                                     CMPC or CMPD (depending the value of x)
//!                                     when the timer is incrementing
//!   - EPWM_INT_TBCTR_D_CMPx         - Where x is A,B,C or D
//!                                     Time-base counter equal to CMPA, CMPB,
//!                                     CMPC or CMPD (depending the value of x)
//!                                     when the timer is decrementing
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource)
{
    uint16_t intSource;

    //
    // Check the arguments
    //
    ;
    ;

    if((interruptSource == 8U) ||
       (interruptSource == 12U) ||
       (interruptSource == 10U) ||
       (interruptSource == 14U))
    {
          //
          // Shift the interrupt source by 1
          //
          intSource = interruptSource >> 1U;

          //
          // Enable events based on comp C or comp D
          //
          (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) |= 0x40U;
    }
    else if((interruptSource == 4U) ||
            (interruptSource == 6U) ||
            (interruptSource == 5U) ||
            (interruptSource == 7U))
    {
        intSource = interruptSource;

        //
        // Enable events based on comp A or comp B
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) &= ~0x40U;
    }
    else
    {
        intSource = interruptSource;
    }

    //
    // Set the interrupt source
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) & ~0x7U) | intSource);
}

//*****************************************************************************
//
//! Sets the ePWM interrupt event counts.
//!
//! \param base is the base address of the EPWM module.
//! \param eventCount is the event count for interrupt scale
//!
//! This function sets the interrupt event count that determines the number of
//! events that have to occur before an interrupt is issued.
//! Maximum value for eventCount is 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Enable advanced feature of interrupt every up to 15 events
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xA6U)))) |= 0x10U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAEU)))) =
         (((*((volatile uint16_t *)((uintptr_t)(base + 0xAEU)))) & ~0xFU) |
           eventCount);
}

//*****************************************************************************
//
//! Return the interrupt status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the ePWM interrupt status.
//! \b Note This function doesn't return the Trip Zone status.
//!
//! \return Returns true if ePWM interrupt was generated.
//!         Returns false if no interrupt was generated
//
//*****************************************************************************
static inline _Bool
EPWM_getEventTriggerInterruptStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return INT bit of ETFLG register
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0xA8U)))) & 0x1U) == 0x1U) ? 1 : 0);
}

//*****************************************************************************
//
//! Clear interrupt flag.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function clears the ePWM interrupt flag.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_clearEventTriggerInterruptFlag(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear INT bit of ETCLR register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAAU)))) |= 0x1U;
}

//*****************************************************************************
//
//! Enable Pre-interrupt count load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the ePWM interrupt counter to be pre-interrupt loaded
//! with a count value.
//!
//! \note This is valid only for advanced/expanded interrupt mode
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableInterruptEventCountInit(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable interrupt event count initializing/loading
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xB2U)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Disable interrupt count load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the ePWM interrupt counter from being loaded with
//! pre-interrupt count value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableInterruptEventCountInit(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable interrupt event count initializing/loading
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xB2U)))) &= ~0x2000U;
}

//*****************************************************************************
//
//! Force a software pre interrupt event counter load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function forces the ePWM interrupt counter to be loaded with the
//! contents set by EPWM_setPreInterruptEventCount().
//!
//! \note make sure the EPWM_enablePreInterruptEventCountLoad() function is
//!       is called before invoking this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceInterruptEventCountInit(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Load the Interrupt Event counter value
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xB2U)))) |= 0x400U;
}

//*****************************************************************************
//
//! Set interrupt count.
//!
//! \param base is the base address of the EPWM module.
//! \param eventCount is the ePWM interrupt count value.
//!
//! This function sets the ePWM interrupt count. eventCount is the value of the
//! pre-interrupt value that is to be loaded. The maximum value of eventCount
//! is 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the Pre-interrupt event count
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xB4U)))) =
         (((*((volatile uint16_t *)((uintptr_t)(base + 0xB4U)))) & ~0xFU) |
          (uint16_t)(eventCount & 0xFU));
}

//*****************************************************************************
//
//! Get the interrupt count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the ePWM interrupt event count.
//!
//! \return The interrupt event counts that have occurred.
//
//*****************************************************************************
static inline uint16_t
EPWM_getInterruptEventCount(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the interrupt event count
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0xAEU)))) & 0xF0U) >>
             4U));
}

//*****************************************************************************
//
//! Force ePWM interrupt.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function forces an ePWM interrupt.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_forceEventTriggerInterrupt(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set INT bit of ETFRC register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xACU)))) |= 0x1U;
}

//
// ADC SOC configuration related APIs
//
//*****************************************************************************
//
//! Enable ADC SOC event.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function enables the ePWM module to trigger an ADC SOC event.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable an SOC
    //
    if(adcSOCType == EPWM_SOC_A)
    {
         (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) |= 0x800U;
    }
    else
    {
         (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) |= 0x8000U;
    }
}

//*****************************************************************************
//
//! Disable ADC SOC event.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function disables the ePWM module from triggering an ADC SOC event.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable an SOC
    //
    if(adcSOCType == EPWM_SOC_A)
    {
         (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) &= ~0x800U;
    }
    else
    {
         (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) &= ~0x8000U;
    }
}

//*****************************************************************************
//
//! Sets the ePWM SOC source.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//! \param socSource is the SOC source.
//!
//! This function sets the ePWM ADC SOC source.
//! Valid values for socSource are:
//!  - adcSOCType
//!     - EPWM_SOC_A  - SOC A
//!     - EPWM_SOC_B  - SOC B
//!  - socSource
//!     - EPWM_SOC_DCxEVT1              - Event is based on DCxEVT1
//!     - EPWM_SOC_TBCTR_ZERO           - Time-base counter equal to zero
//!     - EPWM_SOC_TBCTR_PERIOD         - Time-base counter equal to period
//!     - EPWM_SOC_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or
//!                                       period
//!     - EPWM_SOC_TBCTR_U_CMPx         - Where x is A,B,C or D
//!                                       Time-base counter equal to CMPA, CMPB,
//!                                       CMPC or CMPD(depending the value of x)
//!                                       when the timer is incrementing
//!     - EPWM_SOC_TBCTR_D_CMPx         - Where x is A,B,C or D
//!                                       Time-base counter equal to CMPA, CMPB,
//!                                       CMPC or CMPD(depending the value of x)
//!                                       when the timer is decrementing
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerSource(uint32_t base,
                         EPWM_ADCStartOfConversionType adcSOCType,
                         EPWM_ADCStartOfConversionSource socSource)
{
    uint16_t source;

    //
    // Check the arguments
    //
    ;

    if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
       (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
       (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
       (socSource == EPWM_SOC_TBCTR_D_CMPD))
    {
        source = (uint16_t)socSource >> 1U;
    }
    else
    {
        source = (uint16_t)socSource;
    }

    if(adcSOCType == EPWM_SOC_A)
    {
        //
        // Set the SOC source
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) & ~0x700U) |
                 (source << 8U));

        //
        // Enable the comparator selection
        //
        if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_U_CMPB) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPB))
        {
            //
            // Enable events based on comp A or comp B
            //
            (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) &= ~0x10U;
        }
        else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPD))
        {
            //
            // Enable events based on comp C or comp D
            //
            (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) |= 0x10U;
        }
        else
        {
            //
            // No action required for the other socSource options
            //
        }
    }
    else
    {
        //
        // Enable the comparator selection
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) & ~0x7000U) |
                 (source << 12U));

        //
        // Enable the comparator selection
        //
        if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_U_CMPB) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPA) ||
           (socSource == EPWM_SOC_TBCTR_D_CMPB))
        {
            //
            // Enable events based on comp A or comp B
            //
            (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) &= ~0x20U;
        }
        else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_U_CMPD) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPC) ||
                (socSource == EPWM_SOC_TBCTR_D_CMPD))
        {
            //
            // Enable events based on comp C or comp D
            //
            (*((volatile uint16_t *)((uintptr_t)(base + 0xA4U)))) |= 0x20U;
        }
        else
        {
            //
            // No action required for the other socSource options
            //
        }
    }
}

//*****************************************************************************
//
//! Sets the ePWM SOC event counts.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//! \param preScaleCount is the event count number.
//!
//! This function sets the SOC event count that determines the number of
//! events that have to occur before an SOC is issued.
//!  Valid values for the parameters are:
//!   - adcSOCType
//!       - EPWM_SOC_A  - SOC A
//!       - EPWM_SOC_B  - SOC B
//!   - preScaleCount
//!        - [1 - 15]  -  Generate SOC pulse every preScaleCount
//!                       up to 15 events.
//!
//! \note A preScaleCount value of 0 disables the prescale.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerEventPrescale(uint32_t base,
                                EPWM_ADCStartOfConversionType adcSOCType,
                                uint16_t preScaleCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Enable advanced feature of SOC every up to 15 events
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xA6U)))) |= 0x20U;
    if(adcSOCType == EPWM_SOC_A)
    {
        //
        // Set the count for SOC A
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xB0U)))) =
           (((*((volatile uint16_t *)((uintptr_t)(base + 0xB0U)))) & ~0xFU) |
             preScaleCount);
    }
    else
    {
        //
        // Set the count for SOC B
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xB0U)))) =
             (((*((volatile uint16_t *)((uintptr_t)(base + 0xB0U)))) & ~0xF00U) |
              (preScaleCount << 8U));
    }
}

//*****************************************************************************
//
//! Return the SOC event status.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function returns the ePWM SOC status.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \return Returns true if the selected adcSOCType SOC was generated.
//!         Returns false if the selected adcSOCType SOC was not generated.
//
//*****************************************************************************
static inline _Bool
EPWM_getADCTriggerFlagStatus(uint32_t base,
                             EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the SOC A/ B status
    //
    return(((((*((volatile uint16_t *)((uintptr_t)(base + 0xA8U)))) >>
              ((uint16_t)adcSOCType + 2U)) & 0x1U) == 0x1U) ? 1 : 0);
}

//*****************************************************************************
//
//! Clear SOC flag.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function clears the ePWM SOC flag.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_clearADCTriggerFlag(uint32_t base,
                         EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear SOC A/B bit of ETCLR register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAAU)))) |= 1U << ((uint16_t)adcSOCType + 2U);
}

//*****************************************************************************
//
//! Enable Pre-SOC event count load.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function enables the ePWM SOC event counter which is set by the
//! EPWM_setADCTriggerEventCountInitValue() function to be loaded before
//! an SOC event.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \note This is valid only for advanced/expanded SOC mode
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableADCTriggerEventCountInit(uint32_t base,
                                    EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable SOC event count initializing/loading
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xB2U)))) |= 1U << ((uint16_t)adcSOCType + 14U);
}

//*****************************************************************************
//
//! Disable Pre-SOC event count load.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function disables the ePWM SOC event counter from being loaded before
//! an SOC event (only an SOC event causes an increment of the counter value).
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \note This is valid only for advanced/expanded SOC mode
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableADCTriggerEventCountInit(uint32_t base,
                                     EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable SOC event count initializing/loading
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xB2U)))) &=
                                  ~(1U << ((uint16_t)adcSOCType + 14U));
}

//*****************************************************************************
//
//! Force a software pre SOC event counter load.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type
//!
//! This function forces the ePWM SOC counter to be loaded with the
//! contents set by EPWM_setPreADCStartOfConversionEventCount().
//!
//! \note make sure the EPWM_enableADCTriggerEventCountInit()
//!       function is called before invoking this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceADCTriggerEventCountInit(uint32_t base,
                                   EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Load the Interrupt Event counter value
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xB2U)))) |= 1U << ((uint16_t)adcSOCType + 11U);
}

//*****************************************************************************
//
//! Set ADC Trigger count values.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//! \param eventCount is the ePWM interrupt count value.
//!
//! This function sets the ePWM ADC Trigger count values.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//! The eventCount has a maximum value of 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerEventCountInitValue(uint32_t base,
                                      EPWM_ADCStartOfConversionType adcSOCType,
                                      uint16_t eventCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the ADC Trigger event count
    //
    if(adcSOCType == EPWM_SOC_A)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0xB4U)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0xB4U)))) & ~0xF0U) |
             (uint16_t)(eventCount << 4U));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0xB4U)))) =
             (((*((volatile uint16_t *)((uintptr_t)(base + 0xB4U)))) & ~0xF00U) |
              (eventCount << 8U));
    }
}

//*****************************************************************************
//
//! Get the SOC event count.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function returns the ePWM SOC event count.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \return The SOC event counts that have occurred.
//
//*****************************************************************************
static inline uint16_t
EPWM_getADCTriggerEventCount(uint32_t base,
                             EPWM_ADCStartOfConversionType adcSOCType)
{
    uint16_t eventCount;

    //
    // Check the arguments
    //
    ;

    //
    // Return the SOC event count
    //
    if(adcSOCType == EPWM_SOC_A)
    {
        eventCount = ((*((volatile uint16_t *)((uintptr_t)(base + 0xB0U)))) >>
                                         4U) & 0xFU;
    }
    else
    {
        eventCount = ((*((volatile uint16_t *)((uintptr_t)(base + 0xB0U)))) >>
                                        12U) & 0xFU;
    }
    return(eventCount);
}

//*****************************************************************************
//
//! Force SOC event.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function forces an ePWM SOC event.
//! Valid values for adcSOCType are:
//!   - EPWM_SOC_A  - SOC A
//!   - EPWM_SOC_B  - SOC B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set SOC A/B bit of ETFRC register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xACU)))) |= 1U << ((uint16_t)adcSOCType + 2U);
}

//
// Digital Compare module related APIs
//
//*****************************************************************************
//
//! Set the DC trip input.
//!
//! \param base is the base address of the EPWM module.
//! \param tripSource is the tripSource.
//! \param dcType is the Digital Compare type.
//!
//! This function sets the trip input to the Digital Compare (DC). For a given
//! dcType the function sets the tripSource to be the input to the DC.
//! Valid values for the parameter are:
//!  - tripSource
//!     - EPWM_DC_TRIP_TRIPINx - Trip x,where x ranges from 1 to 15 excluding 13
//!     - EPWM_DC_TRIP_COMBINATION - selects all the Trip signals whose input
//!                                  is enabled by the following function
//!                              EPWM_enableDigitalCompareTripCombinationInput()
//!  - dcType
//!     - EPWM_DC_TYPE_DCAH  - Digital Compare A High
//!     - EPWM_DC_TYPE_DCAL  - Digital Compare A Low
//!     - EPWM_DC_TYPE_DCBH  - Digital Compare B High
//!     - EPWM_DC_TYPE_DCBL  - Digital Compare B Low
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_selectDigitalCompareTripInput(uint32_t base,
                                   EPWM_DigitalCompareTripInput tripSource,
                                   EPWM_DigitalCompareType dcType)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the DC trip input
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC0U)))) =
     (((*((volatile uint16_t *)((uintptr_t)(base + 0xC0U)))) & ~(0xFU << ((uint16_t)dcType << 2U))) |
      ((uint16_t)tripSource << ((uint16_t)dcType << 2U)));
    __edis();
}

//
// DCFILT
//
//*****************************************************************************
//
//! Enable DC filter blanking window.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the DC filter blanking window.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable DC filter blanking window
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) |= 0x4U;
    __edis();
}

//*****************************************************************************
//
//! Disable DC filter blanking window.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the DC filter blanking window.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable DC filter blanking window
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) &= ~0x4U;
    __edis();
}

//*****************************************************************************
//
//! Enable Digital Compare Window inverse mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the Digital Compare Window inverse mode. This will
//! invert the blanking window.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable DC window inverse mode.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) |= 0x8U;
    __edis();
}

//*****************************************************************************
//
//! Disable Digital Compare Window inverse mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Digital Compare Window inverse mode.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable DC window inverse mode.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) &= ~0x8U;
    __edis();
}

//*****************************************************************************
//
//! Set the Digital Compare filter blanking pulse.
//!
//! \param base is the base address of the EPWM module.
//! \param blankingPulse is Pulse that starts blanking window.
//!
//! This function sets the input pulse that starts the Digital Compare blanking
//! window.
//! Valid values for blankingPulse are:
//!   - EPWM_DC_WINDOW_START_TBCTR_PERIOD - Time base counter equals period
//!   - EPWM_DC_WINDOW_START_TBCTR_ZERO   - Time base counter equals zero
//!   - EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD - Time base counter equals zero
//!                                              or period.
//!   - EPWM_DC_WINDOW_START_BLANK_PULSE_MIX - Blanking pulse mix
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareBlankingEvent(uint32_t base,
                                EPWM_DigitalCompareBlankingPulse blankingPulse)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set DC blanking event
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) & ~0x30U) |
             ((uint16_t)((uint32_t)blankingPulse << 4U)));
    __edis();
}

//*****************************************************************************
//
//! Set up the Digital Compare filter input.
//!
//! \param base is the base address of the EPWM module.
//! \param filterInput is Digital Compare signal source.
//!
//! This function sets the signal input source that will be filtered by the
//! Digital Compare module.
//! Valid values for filterInput are:
//!   - EPWM_DC_WINDOW_SOURCE_DCAEVT1  - DC filter signal source is DCAEVT1
//!   - EPWM_DC_WINDOW_SOURCE_DCAEVT2  - DC filter signal source is DCAEVT2
//!   - EPWM_DC_WINDOW_SOURCE_DCBEVT1  - DC filter signal source is DCBEVT1
//!   - EPWM_DC_WINDOW_SOURCE_DCBEVT2  - DC filter signal source is DCBEVT2
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareFilterInput(uint32_t base,
                                  EPWM_DigitalCompareFilterInput filterInput)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the signal source that will be filtered
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) =
                  (((*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) & ~0x3U) |
                   ((uint16_t)filterInput));
    __edis();
}

//
// DC Edge Filter
//
//*****************************************************************************
//
//! Enable Digital Compare Edge Filter.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the Digital Compare Edge filter to generate event
//! after configured number of edges.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable DC Edge Filter
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) |= 0x40U;
    __edis();
}

//*****************************************************************************
//
//! Disable Digital Compare Edge Filter.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Digital Compare Edge filter.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable DC Edge Filter
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) &= ~0x40U;
    __edis();
}

//*****************************************************************************
//
//! Set the Digital Compare Edge Filter Mode.
//!
//! \param base is the base address of the EPWM module.
//! \param edgeMode is Digital Compare Edge filter mode.
//!
//! This function sets the Digital Compare Event filter mode. Valid values
//! for edgeMode are:
//!   - EPWM_DC_EDGEFILT_MODE_RISING  - DC edge filter mode is rising edge
//!   - EPWM_DC_EDGEFILT_MODE_FALLING - DC edge filter mode is falling edge
//!   - EPWM_DC_EDGEFILT_MODE_BOTH    - DC edge filter mode is both edges
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEdgeFilterMode(uint32_t base,
                                     EPWM_DigitalCompareEdgeFilterMode edgeMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set DC Edge filter mode
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) &
                                    ~0x300U) |
                                   (edgeMode << 8U);
    __edis();
}

//*****************************************************************************
//
//! Set the Digital Compare Edge Filter Edge Count.
//!
//! \param base is the base address of the EPWM module.
//! \param edgeCount is Digital Compare event filter count
//!
//! This function sets the Digital Compare Event filter Edge Count to generate
//! events. Valid values for edgeCount can be:
//!  - EPWM_DC_EDGEFILT_EDGECNT_0 - No edge is required to generate event
//!  - EPWM_DC_EDGEFILT_EDGECNT_1 - 1 edge is required for event generation
//!  - EPWM_DC_EDGEFILT_EDGECNT_2 - 2 edges are required for event generation
//!  - EPWM_DC_EDGEFILT_EDGECNT_3 - 3 edges are required for event generation
//!  - EPWM_DC_EDGEFILT_EDGECNT_4 - 4 edges are required for event generation
//!  - EPWM_DC_EDGEFILT_EDGECNT_5 - 5 edges are required for event generation
//!  - EPWM_DC_EDGEFILT_EDGECNT_6 - 6 edges are required for event generation
//!  - EPWM_DC_EDGEFILT_EDGECNT_7 - 7 edges are required for event generation
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, uint16_t edgeCount)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set DC Edge filter edge count
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) &
                                    ~0x1C00U) |
                                   (edgeCount << 10U);
    __edis();
}

//*****************************************************************************
//
//! Returns the Digital Compare Edge Filter Edge Count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the configured Digital Compare Edge filter edge
//! count required to generate events. It can return values from 0-7.
//!
//! \return Returns the configured DigitalCompare Edge filter edge count.
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return configured DC edge filter edge count
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) & 0x1C00U) >>
           10U);
}

//*****************************************************************************
//
//! Returns the Digital Compare Edge filter captured edge count status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the count of edges captured by Digital Compare Edge
//! filter. It can return values from 0-7.
//!
//! \return Returns the count of captured edges
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return captured edge count by DC Edge filter
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xC7U)))) & 0xE000U) >>
           13U);
}

//*****************************************************************************
//
//! Set up the Digital Compare filter window offset
//!
//! \param base is the base address of the EPWM module.
//! \param windowOffsetCount is blanking window offset length.
//!
//! This function sets the offset between window start pulse and blanking
//! window in TBCLK count.
//! The function take a 16bit count value for the offset value.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the blanking window offset in TBCLK counts
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC9U)))) = windowOffsetCount;
}

//*****************************************************************************
//
//! Set up the Digital Compare filter window length
//!
//! \param base is the base address of the EPWM module.
//! \param windowLengthCount is blanking window length.
//!
//! This function sets up the Digital Compare filter blanking window length in
//! TBCLK count.The function takes a 16bit count value for the window length.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the blanking window length in TBCLK counts
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCBU)))) = windowLengthCount;
}

//*****************************************************************************
//
//! Return DC filter blanking window offset count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns DC filter blanking window offset count.
//!
//! \return None
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the Blanking Window Offset count
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0xCAU)))));
}

//*****************************************************************************
//
//! Return DC filter blanking window length count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns DC filter blanking window length count.
//!
//! \return None
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the Blanking Window Length count
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0xCCU)))));
}

//*****************************************************************************
//
//! Set up the Digital Compare Event source.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param dcEventSource is the - Digital Compare Event source.
//!
//! This function sets up the Digital Compare module Event sources.
//! The following are valid values for the parameters.
//!  - dcModule
//!      - EPWM_DC_MODULE_A  - Digital Compare Module A
//!      - EPWM_DC_MODULE_B  - Digital Compare Module B
//!  - dcEvent
//!      - EPWM_DC_EVENT_1   - Digital Compare Event number 1
//!      - EPWM_DC_EVENT_2   - Digital Compare Event number 2
//!  - dcEventSource
//!      - EPWM_DC_EVENT_SOURCE_FILT_SIGNAL  - signal source is filtered
//!            \note The signal source for this option is DCxEVTy, where the
//!                  value of x is dependent on dcModule and the value of y is
//!                  dependent on dcEvent. Possible signal sources are DCAEVT1,
//!                  DCBEVT1, DCAEVT2 or DCBEVT2 depending on the value of both
//!                  dcModule and dcEvent.
//!      - EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL  - signal source is unfiltered
//!                   The signal source for this option is DCEVTFILT.
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEventSource(uint32_t base,
                                  EPWM_DigitalCompareModule dcModule,
                                  EPWM_DigitalCompareEvent dcEvent,
                                  EPWM_DigitalCompareEventSource dcEventSource)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Set the DC event 1 source source
    //
    __eallow();
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x1U) |
                 (uint16_t)dcEventSource);
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                 (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x100U) |
                  ((uint16_t)dcEventSource << 8U));
    }
    __edis();
}

//*****************************************************************************
//
//! Set up the Digital Compare input sync mode.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param syncMode is the Digital Compare Event sync mode.
//!
//! This function sets up the Digital Compare module Event sources.
//! The following are valid values for the parameters.
//!  - dcModule
//!      - EPWM_DC_MODULE_A  - Digital Compare Module A
//!      - EPWM_DC_MODULE_B  - Digital Compare Module B
//!  - dcEvent
//!      - EPWM_DC_EVENT_1   - Digital Compare Event number 1
//!      - EPWM_DC_EVENT_2   - Digital Compare Event number 2
//!  - syncMode
//!      - EPWM_DC_EVENT_INPUT_SYNCED      - DC input signal is synced with
//!                                          TBCLK
//!      - EPWM_DC_EVENT_INPUT_NOT SYNCED  - DC input signal is not synced with
//!                                          TBCLK
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEventSyncMode(uint32_t base,
                                    EPWM_DigitalCompareModule dcModule,
                                    EPWM_DigitalCompareEvent dcEvent,
                                    EPWM_DigitalCompareSyncMode syncMode)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Set the DC event sync mode
    //
    __eallow();
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
           (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x2U) |
            ((uint16_t)syncMode << 1U));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x200U) |
             ((uint16_t)syncMode << 9U));
    }
    __edis();
}

//*****************************************************************************
//
//! Enable Digital Compare to generate Start of Conversion.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function enables the Digital Compare Event 1 to generate Start of
//! Conversion.
//! The following are valid values for the \e dcModule parameter.
//!     - EPWM_DC_MODULE_A  - Digital Compare Module A
//!     - EPWM_DC_MODULE_B  - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareADCTrigger(uint32_t base,
                                    EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Enable Digital Compare start of conversion generation
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                       ((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) | 0x4U);
    __edis();
}

//*****************************************************************************
//
//! Disable Digital Compare from generating Start of Conversion.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function disables the Digital Compare Event 1 from generating Start of
//! Conversion.
//! The following are valid values for the \e dcModule parameter.
//!     - EPWM_DC_MODULE_A  - Digital Compare Module A
//!     - EPWM_DC_MODULE_B  - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareADCTrigger(uint32_t base,
                                     EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Disable Digital Compare start of conversion generation
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                      ((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x4U);
    __edis();
}

//*****************************************************************************
//
//! Enable Digital Compare to generate sync out pulse.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function enables the Digital Compare Event 1 to generate sync out
//! pulse
//! The following are valid values for the \e dcModule parameter.
//!     - EPWM_DC_MODULE_A  - Digital Compare Module A
//!     - EPWM_DC_MODULE_B  - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareSyncEvent(uint32_t base,
                                   EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Enable Digital Compare sync out pulse generation
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                     ((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) | 0x8U);
    __edis();
}

//*****************************************************************************
//
//! Disable Digital Compare from generating Start of Conversion.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function disables the Digital Compare Event 1 from generating synch
//! out pulse.
//! The following are valid values for the \e dcModule parameters.
//!     - EPWM_DC_MODULE_A  - Digital Compare Module A
//!     - EPWM_DC_MODULE_B  - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareSyncEvent(uint32_t base,
                                    EPWM_DigitalCompareModule dcModule)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Disable Digital Compare sync out pulse generation
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                      ((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x8U);
    __edis();
}

//*****************************************************************************
//
//! Set up the Digital Compare CBC latch mode.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param latchMode is the Digital Compare CBC latch mode.
//!
//! This function sets up the Digital Compare CBC latch mode.
//! The following are valid values for the parameters.
//!  - dcModule
//!      - EPWM_DC_MODULE_A  - Digital Compare Module A
//!      - EPWM_DC_MODULE_B  - Digital Compare Module B
//!  - dcEvent
//!      - EPWM_DC_EVENT_1   - Digital Compare Event number 1
//!      - EPWM_DC_EVENT_2   - Digital Compare Event number 2
//!  - latchMode
//!      - EPWM_DC_CBC_LATCH_DISABLED - DC cycle-by-cycle(CBC) latch is disabled
//!      - EPWM_DC_CBC_LATCH_ENABLED  - DC cycle-by-cycle(CBC) latch is enabled
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareCBCLatchMode(uint32_t base,
                                   EPWM_DigitalCompareModule dcModule,
                                   EPWM_DigitalCompareEvent dcEvent,
                                   EPWM_DigitalCompareCBCLatchMode latchMode)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Set the DC CBC Latch Mode
    //
    __eallow();
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
           (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x10U) |
            ((uint16_t)latchMode << 4U));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x1000U) |
             ((uint16_t)latchMode << 12U));
    }
    __edis();
}

//*****************************************************************************
//
//! Sets the Digital Compare CBC latch clear event.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param clearEvent is the Digital Compare CBC latch clear event.
//!
//! This function sets the Digital Compare CBC latch clear event.
//! The following are valid values for the parameters.
//!  - dcModule
//!      - EPWM_DC_MODULE_A  - Digital Compare Module A
//!      - EPWM_DC_MODULE_B  - Digital Compare Module B
//!  - dcEvent
//!      - EPWM_DC_EVENT_1   - Digital Compare Event number 1
//!      - EPWM_DC_EVENT_2   - Digital Compare Event number 2
//!  - clearEvent
//!      - EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO - DC CBC latch is cleared when
//!                                          counter is zero
//!      - EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD - DC CBC latch is cleared when
//!                                               counter is equal to period
//!      - EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD - DC CBC latch is cleared
//!                                                    when either counter is
//!                                                    zero or equal to period
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base,
                              EPWM_DigitalCompareModule dcModule,
                              EPWM_DigitalCompareEvent dcEvent,
                              EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Set the DC CBC Latch Clear Event
    //
    __eallow();
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
           (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x60U) |
            ((uint16_t)clearEvent << 5U));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~0x6000U) |
             ((uint16_t)clearEvent << 13U));
    }
    __edis();
}

//*****************************************************************************
//
//! Gets the Digital Compare CBC latch status
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//!
//! This function returns the Digital Compare module cycle-by-cycle(CBC) latch
//! status.
//! The following are valid values for the parameters.
//!  - dcModule
//!      - EPWM_DC_MODULE_A  - Digital Compare Module A
//!      - EPWM_DC_MODULE_B  - Digital Compare Module B
//!  - dcEvent
//!      - EPWM_DC_EVENT_1   - Digital Compare Event number 1
//!      - EPWM_DC_EVENT_2   - Digital Compare Event number 2
//!
//! \return Returns Digital Compare CBC latch status.
//! -\b true  - CBC latch is enabled
//! -\b false - CBC latch is disabled
//
//*****************************************************************************
static inline _Bool
EPWM_getDigitalCompareCBCLatchStatus(uint32_t base,
                                     EPWM_DigitalCompareModule dcModule,
                                     EPWM_DigitalCompareEvent dcEvent)
{
    uint32_t registerOffset;
    uint16_t status;

    //
    // Check the arguments
    //
    ;

    registerOffset = 0xC3U + (uint16_t)dcModule;

    //
    // Get DC CBC Latch Clear Event
    //
    if(dcEvent == EPWM_DC_EVENT_1)
    {
        status = (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & 0x80U;
    }
    else
    {
        status = (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & 0x8000U;
    }
    return(status != 0U);
}

//
// DC capture mode
//
//*****************************************************************************
//
//! Enables the Time Base Counter Capture controller.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the time Base Counter Capture.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareCounterCapture(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable Time base counter capture
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC8U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Disables the Time Base Counter Capture controller.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disable the time Base Counter Capture.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareCounterCapture(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable Time base counter capture
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC8U)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! Set the Time Base Counter Capture mode.
//!
//! \param base is the base address of the EPWM module.
//! \param enableShadowMode is the shadow read mode flag.
//!
//! This function sets the mode the Time Base Counter value is read from. If
//! enableShadowMode is true, CPU reads of the DCCAP register will return the
//! shadow register contents.If enableShadowMode is false, CPU reads of the
//! DCCAP register will return the active register contents.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareCounterShadowMode(uint32_t base, _Bool enableShadowMode)
{
    //
    // Check the arguments
    //
    ;

    __eallow();
    if(enableShadowMode)
    {
        //
        // Enable DC counter shadow mode
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0xC8U)))) &= ~0x2U;
    }
    else
    {
       //
       // Disable DC counter shadow mode
       //
       (*((volatile uint16_t *)((uintptr_t)(base + 0xC8U)))) |= 0x2U;
    }
    __edis();
}

//*****************************************************************************
//
//! Return the DC Capture event status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the DC capture event status.
//!
//! \return Returns true if a DC capture event has occurs.
//!         Returns false if no DC Capture event has occurred.
//!
//! \return None.
//
//*****************************************************************************
static inline _Bool
EPWM_getDigitalCompareCaptureStatus(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the DC compare status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xC8U)))) & 0x2000U) ==
                                                        0x2000U);
}

//*****************************************************************************
//
//! Return the DC Time Base Counter capture value.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the DC Time Base Counter capture value. The value
//! read is determined by the mode as set in the
//! EPWM_setTimeBaseCounterReadMode() function.
//!
//! \return Returns the DC Time Base Counter Capture count value.
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareCaptureCount(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the DC Time Base Counter Capture count value
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0xCFU)))));
}

//*****************************************************************************
//
//! Enable DC TRIP combinational input.
//!
//! \param base is the base address of the EPWM module.
//! \param tripInput is the Trip number.
//! \param dcType is the Digital Compare module.
//!
//! This function enables the specified Trip input.
//! Valid values for the parameters are:
//!  - tripInput
//!      - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15
//!  - dcType
//!      - EPWM_DC_TYPE_DCAH  - Digital Compare A High
//!      - EPWM_DC_TYPE_DCAL  - Digital Compare A Low
//!      - EPWM_DC_TYPE_DCBH  - Digital Compare B High
//!      - EPWM_DC_TYPE_DCBL  - Digital Compare B Low
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareTripCombinationInput(uint32_t base,
                                              uint16_t tripInput,
                                              EPWM_DigitalCompareType dcType)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    //
    // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
    // offset with respect to DCAHTRIPSEL
    //
    registerOffset = 0xD2U + (uint16_t)dcType;

    //
    // Set the DC trip input
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                           ((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) | tripInput);

    //
    // Enable the combination input
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xC0U)))) =
      ((*((volatile uint16_t *)((uintptr_t)(base + 0xC0U)))) | (0xFU << ((uint16_t)dcType << 2U)));
    __edis();
}

//*****************************************************************************
//
//! Disable DC TRIP combinational input.
//!
//! \param base is the base address of the EPWM module.
//! \param tripInput is the Trip number.
//! \param dcType is the Digital Compare module.
//!
//! This function disables the specified Trip input.
//! Valid values for the parameters are:
//!  - tripInput
//!      - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15
//!  - dcType
//!      - EPWM_DC_TYPE_DCAH  - Digital Compare A High
//!      - EPWM_DC_TYPE_DCAL  - Digital Compare A Low
//!      - EPWM_DC_TYPE_DCBH  - Digital Compare B High
//!      - EPWM_DC_TYPE_DCBL  - Digital Compare B Low
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareTripCombinationInput(uint32_t base,
                                               uint16_t tripInput,
                                               EPWM_DigitalCompareType dcType)
{
    uint32_t registerOffset;

    //
    // Check the arguments
    //
    ;

    //
    // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
    // offset with respect to DCAHTRIPSEL
    //
    registerOffset = 0xD2U + (uint16_t)dcType;

    //
    // Set the DC trip input
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) =
                           ((*((volatile uint16_t *)((uintptr_t)(base + registerOffset)))) & ~tripInput);
    __edis();
}

//
// Valley switching
//
//*****************************************************************************
//
//! Enable valley capture mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables Valley Capture mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableValleyCapture(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set VCAPE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Disable valley capture mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables Valley Capture mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableValleyCapture(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear VCAPE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! Start valley capture mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function starts Valley Capture sequence.
//!
//! \b Make sure you invoke EPWM_setValleyTriggerSource with the trigger
//!    variable set to EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE before calling this
//!    function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_startValleyCapture(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set VCAPSTART bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Set valley capture trigger.
//!
//! \param base is the base address of the EPWM module.
//! \param trigger is the Valley counter trigger.
//!
//! This function sets the trigger value that initiates Valley Capture sequence
//!
//! \b Set the number of Trigger source events for starting and stopping the
//!    valley capture using EPWM_setValleyTriggerEdgeCounts().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to TRIGSEL bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) =
             (((*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) & ~0x1CU) |
              ((uint16_t)trigger << 2U));
    __edis();
}

//*****************************************************************************
//
//! Set valley capture trigger source count.
//!
//! \param base is the base address of the EPWM module.
//! \param startCount
//! \param stopCount
//!
//! This function sets the number of trigger events required to start and stop
//! the valley capture count.
//! Maximum values for both startCount and stopCount is 15 corresponding to the
//! 15th edge of the trigger event.
//!
//! \b Note:
//!    A startCount value of 0 prevents starting the valley counter.
//!    A stopCount value of 0 prevents the valley counter from stopping.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount,
                                uint16_t stopCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Write to STARTEDGE and STOPEDGE bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x19U)))) =
                    (((*((volatile uint16_t *)((uintptr_t)(base + 0x19U)))) &
                      ~(0xFU | 0xF00U)) |
                      (startCount | (stopCount << 8U)));
    __edis();
}

//*****************************************************************************
//
//! Enable valley switching delay.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables Valley switching delay.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableValleyHWDelay(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set EDGEFILTDLYSEL bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) |= 0x400U;
    __edis();
}

//*****************************************************************************
//
//! Disable valley switching delay.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables Valley switching delay.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableValleyHWDelay(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear EDGEFILTDLYSEL bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) &= ~0x400U;
    __edis();
}

//*****************************************************************************
//
//! Set Valley delay values.
//!
//! \param base is the base address of the EPWM module.
//! \param delayOffsetValue is the software defined delay offset value.
//!
//! This function sets the Valley delay value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to SWVDELVAL bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x77U)))) = delayOffsetValue;
}

//*****************************************************************************
//
//! Set Valley delay mode.
//!
//! \param base is the base address of the EPWM module.
//! \param delayMode is the Valley delay mode.
//!
//! This function sets the Valley delay mode values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write to VDELAYDIV bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) =
         (((*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) & ~0x380U) |
          ((uint16_t)delayMode << 7U));
    __edis();
}

//*****************************************************************************
//
//! Get the valley edge status bit.
//!
//! \param base is the base address of the EPWM module.
//! \param edge is the start or stop edge.
//!
//! This function returns the status of the start or stop valley status
//! depending on the value of edge.
//! If a start or stop edge has occurred, the function returns true, if not it
//! returns false.
//!
//! \return Returns true if the specified edge has occurred,
//!         Returns false if the specified edge has not occurred.
//
//*****************************************************************************
static inline _Bool
EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
{
    //
    // Check the arguments
    //
    ;

    if(edge == EPWM_VALLEY_COUNT_START_EDGE)
    {
        //
        // Returns STARTEDGESTS status
        //
        return((((*((volatile uint16_t *)((uintptr_t)(base + 0x19U)))) & 0x80U) ==
                   0x80U ) ? 1 : 0);
    }
    else
    {
        //
        // Returns STOPEDGESTS status
        //
        return((((*((volatile uint16_t *)((uintptr_t)(base + 0x19U)))) & 0x8000U) ==
                0x8000U) ? 1 : 0);
    }
}

//*****************************************************************************
//
//! Get the Valley Counter value.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the valley time base count value which is captured
//! upon occurrence of the stop edge condition selected by
//! EPWM_setValleyTriggerSource() and by the stopCount variable of the
//! EPWM_setValleyTriggerEdgeCounts() function.
//!
//! \return Returns the valley base time count.
//
//*****************************************************************************
static inline uint16_t
EPWM_getValleyCount(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Read VCNTVAL register
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0xFEU)))));
}

//*****************************************************************************
//
//! Get the Valley delay value.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the hardware valley delay count.
//!
//! \return Returns the valley delay count.
//
//*****************************************************************************
static inline uint16_t
EPWM_getValleyHWDelay(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Read HWVDELVAL  register
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0xFDU)))));
}

//*****************************************************************************
//
//! Enable Global shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables Global shadow to active load mode of registers.
//! The trigger source for loading shadow to active is determined by
//! EPWM_setGlobalLoadTrigger() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoad(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Shadow to active load is controlled globally
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Disable Global shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables Global shadow to active load mode of registers.
//! Loading shadow to active is determined individually.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoad(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Shadow to active load is controlled individually
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! Set the Global shadow load pulse.
//!
//! \param base is the base address of the EPWM module.
//! \param loadTrigger is the pulse that causes global shadow load.
//!
//! This function sets the pulse that causes Global shadow to active load.
//! Valid values for the loadTrigger parameter are:
//!
//!   - EPWM_GL_LOAD_PULSE_CNTR_ZERO              - load when counter is equal
//!                                                 to zero
//!   - EPWM_GL_LOAD_PULSE_CNTR_PERIOD            - load when counter is equal
//!                                                 to period
//!   - EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD       - load when counter is equal
//!                                                 to zero or period
//!   - EPWM_GL_LOAD_PULSE_SYNC                    - load on sync event
//!   - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO      - load on sync event or when
//!                                                 counter is equal to zero
//!   - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD    - load on sync event or when
//!                                                 counter is equal to period
//!   - EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD  - load on sync event or when
//!                                                 counter is equal to period
//!                                                 or zero
//!   - EPWM_GL_LOAD_PULSE_GLOBAL_FORCE            - load on global force
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the Global shadow to active load pulse
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) =
               (((*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) & ~0x1EU) |
                ((uint16_t)loadTrigger << 1U));
    __edis();
}

//*****************************************************************************
//
//! Set the number of Global load pulse event counts
//!
//! \param base is the base address of the EPWM module.
//! \param prescalePulseCount is the pulse event counts.
//!
//! This function sets the number of Global Load pulse events that have to
//! occurred before a global load pulse is issued. Valid values for
//! prescaleCount range from 0 to 7. 0 being no event (disables counter), and 7
//! representing 7 events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the number of counts that have to occur before
    // a load strobe is issued
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) =
                (((*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) & ~0x380U) |
                 (prescalePulseCount << 7U));
    __edis();
}

//*****************************************************************************
//
//! Return the number of Global load pulse event counts
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the number of Global Load pulse events that have
//! occurred. These pulse events are set by the EPWM_setGlobalLoadTrigger()
//! function.
//!
//! \return None.
//
//*****************************************************************************
static inline uint16_t
EPWM_getGlobalLoadEventCount(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Return the number of events that have occurred
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) >> 10U) & 0x7U);
}

//*****************************************************************************
//
//! Enable continuous global shadow to active load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables global continuous shadow to active load. Register
//! load happens every time the event set by the
//! EPWM_setGlobalLoadTrigger() occurs.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoadOneShotMode(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable global continuous shadow to active load
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) &= ~0x20U;
    __edis();
}

//*****************************************************************************
//
//! Enable One shot global shadow to active load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables a one time global shadow to active load. Register
//! load happens every time the event set by the
//! EPWM_setGlobalLoadTrigger() occurs.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoadOneShotMode(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable global continuous shadow to active load
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) |= 0x20U;
    __edis();
}

//*****************************************************************************
//
//! Set One shot global shadow to active load pulse.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function sets a one time global shadow to active load pulse. The pulse
//! propagates to generate a load signal if any of the events set by
//! EPWM_setGlobalLoadTrigger() occur.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadOneShotLatch(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set a one shot Global shadow load pulse.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x74U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Force a software One shot global shadow to active load pulse.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function forces a software a one time global shadow to active load
//! pulse.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Force a Software Global shadow load pulse
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x74U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Enable a register to be loaded Globally.
//!
//! \param base is the base address of the EPWM module.
//! \param loadRegister is the register.
//!
//! This function enables the register specified by loadRegister to be globally
//! loaded.
//! Valid values for loadRegister are:
//!  - EPWM_GL_REGISTER_TBPRD_TBPRDHR  - Register TBPRD:TBPRDHR
//!  - EPWM_GL_REGISTER_CMPA_CMPAHR    - Register CMPA:CMPAHR
//!  - EPWM_GL_REGISTER_CMPB_CMPBHR    - Register CMPB:CMPBHR
//!  - EPWM_GL_REGISTER_CMPC           - Register CMPC
//!  - EPWM_GL_REGISTER_CMPD           - Register CMPD
//!  - EPWM_GL_REGISTER_DBRED_DBREDHR  - Register DBRED:DBREDHR
//!  - EPWM_GL_REGISTER_DBFED_DBFEDHR  - Register DBFED:DBFEDHR
//!  - EPWM_GL_REGISTER_DBCTL          - Register DBCTL
//!  - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2
//!  - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2
//!  - EPWM_GL_REGISTER_AQCSFRC        - Register AQCSFRC
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // The register specified by loadRegister is loaded globally
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x35U)))) |= loadRegister;
    __edis();
}

//*****************************************************************************
//
//! Disable a register to be loaded Globally.
//!
//! \param base is the base address of the EPWM module.
//! \param loadRegister is the register.
//!
//! This function disables the register specified by loadRegister from being
//! loaded globally. The shadow to active load happens as specified by the
//! register control
//! Valid values for loadRegister are:
//!  - EPWM_GL_REGISTER_TBPRD_TBPRDHR  - Register TBPRD:TBPRDHR
//!  - EPWM_GL_REGISTER_CMPA_CMPAHR    - Register CMPA:CMPAHR
//!  - EPWM_GL_REGISTER_CMPB_CMPBHR    - Register CMPB:CMPBHR
//!  - EPWM_GL_REGISTER_CMPC           - Register CMPC
//!  - EPWM_GL_REGISTER_CMPD           - Register CMPD
//!  - EPWM_GL_REGISTER_DBRED_DBREDHR  - Register DBRED:DBREDHR
//!  - EPWM_GL_REGISTER_DBFED_DBFEDHR  - Register DBFED:DBFEDHR
//!  - EPWM_GL_REGISTER_DBCTL          - Register DBCTL
//!  - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2
//!  - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2
//!  - EPWM_GL_REGISTER_AQCSFRC        - Register AQCSFRC
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // The register specified by loadRegister is loaded by individual
    // register configuration setting
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x35U)))) &= ~loadRegister;
    __edis();
}

//*****************************************************************************
//
//! Lock EALLOW protected register groups
//!
//! \param base is the base address of the EPWM module.
//! \param registerGroup is the EALLOW register groups.
//!
//! This functions locks the EALLOW protected register groups specified by
//! the registerGroup variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write the Key to EPWMLOCK register
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0xFAU)))) =
            ((uint32_t)0xA5A50000U | ((uint32_t)registerGroup));
}

//*****************************************************************************
//
//! Set emulation mode
//!
//! \param base is the base address of the EPWM module.
//! \param emulationMode is the emulation mode.
//!
//! This function sets the emulation behaviours of the time base counter. Valid
//! values for emulationMode are:
//!  - EPWM_EMULATION_STOP_AFTER_NEXT_TB    - Stop after next Time Base counter
//!                                           increment or decrement.
//!  - EPWM_EMULATION_STOP_AFTER_FULL_CYCLE - Stop when counter completes whole
//!                                           cycle.
//!  - EPWM_EMULATION_FREE_RUN               - Free run.
//!
//! \return None.
//
//*****************************************************************************
extern void
EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode);

//*****************************************************************************
//
//! Configures ePWM signal with desired frequency & duty
//!
//! \param base is the base address of the EPWM module.
//! \param signalParams is the desired signal parameters.
//!
//! This function configures the ePWM module to generate a signal with
//! desired frequency & duty.
//!
//! \return None.
//
//*****************************************************************************
extern void
EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   eqep.h
//
// TITLE:  C28x eQEP driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup eqep_api eQEP
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_eqep.h
//
// TITLE:   Definitions for the EQEP registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the EQEP register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the QDECCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QCAPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QPOSCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QEINT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPSTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the REV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPSTROBESEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QMACTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPSRCSEL register
//
//*************************************************************************************************




//*****************************************************************************
//
// Values that can be passed to EQEP_setDecoderConfig() as the config
// parameter.
//
//*****************************************************************************

//
// Operation Mode
//

//
// Resolution
//

//
// Swap QEPA and QEPB
//

//
// Index pulse gating option
//

//*****************************************************************************

//
// Values that can be passed to EQEP_setCompareConfig() as the config
// parameter.
//
//*****************************************************************************

//
// Sync pulse pin
//

//
// Shadow register use
//

//*****************************************************************************
//
// Values that can be passed to EQEP_enableInterrupt(),
// EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the
// intFlags parameter and returned by EQEP_clearInterruptStatus().
//
//*****************************************************************************

//*****************************************************************************
//
// Values that can be returned by EQEP_getStatus().
//
//*****************************************************************************
//! Unit position event detected
//! Direction was clockwise on first index event
//! Direction is CW (forward)
//! Direction was CW on index
//! Capture timer overflow
//! Direction changed between position capture events
//! First index pulse occurred
//! Position counter error

//*****************************************************************************
//
// Values that can be passed to EQEP_setLatchMode() as the latchMode parameter.
//
//*****************************************************************************

//
// Position counter latch event
//

//
// Strobe position counter latch event
//
//! On rising edge of strobe
//! On rising edge when clockwise, on falling when counter clockwise

//
// Index position counter latch event
//


//*****************************************************************************
//
// Values that can be passed to EQEP_setPositionInitMode() as the initMode
// parameter.
//
//*****************************************************************************

//
// Strobe events
//
//! On rising edge of strobe
//! On rising edge when clockwise, on falling when counter clockwise

//
// Index events
//

//*****************************************************************************
//
//! Values that can be passed to EQEP_setPositionCounterConfig() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Reset position on index pulse
    EQEP_POSITION_RESET_IDX             = 0x0000,
    //! Reset position on maximum position
    EQEP_POSITION_RESET_MAX_POS         = 0x1000,
    //! Reset position on the first index pulse
    EQEP_POSITION_RESET_1ST_IDX         = 0x2000,
    //! Reset position on a unit time event
    EQEP_POSITION_RESET_UNIT_TIME_OUT   = 0x3000
} EQEP_PositionResetMode;

//*****************************************************************************
//
//! Values that can be passed to EQEP_setCaptureConfig() as the \e capPrescale
//! parameter. CAPCLK is the capture timer clock frequency.
//
//*****************************************************************************
typedef enum
{
    EQEP_CAPTURE_CLK_DIV_1   = 0x00,    //!< CAPCLK = SYSCLKOUT/1
    EQEP_CAPTURE_CLK_DIV_2   = 0x10,    //!< CAPCLK = SYSCLKOUT/2
    EQEP_CAPTURE_CLK_DIV_4   = 0x20,    //!< CAPCLK = SYSCLKOUT/4
    EQEP_CAPTURE_CLK_DIV_8   = 0x30,    //!< CAPCLK = SYSCLKOUT/8
    EQEP_CAPTURE_CLK_DIV_16  = 0x40,    //!< CAPCLK = SYSCLKOUT/16
    EQEP_CAPTURE_CLK_DIV_32  = 0x50,    //!< CAPCLK = SYSCLKOUT/32
    EQEP_CAPTURE_CLK_DIV_64  = 0x60,    //!< CAPCLK = SYSCLKOUT/64
    EQEP_CAPTURE_CLK_DIV_128 = 0x70     //!< CAPCLK = SYSCLKOUT/128
} EQEP_CAPCLKPrescale;

//*****************************************************************************
//
//! Values that can be passed to EQEP_setCaptureConfig() as the \e evntPrescale
//! parameter. UPEVNT is the unit position event frequency.
//
//*****************************************************************************
typedef enum
{
    EQEP_UNIT_POS_EVNT_DIV_1,           //!< UPEVNT = QCLK/1
    EQEP_UNIT_POS_EVNT_DIV_2,           //!< UPEVNT = QCLK/2
    EQEP_UNIT_POS_EVNT_DIV_4,           //!< UPEVNT = QCLK/4
    EQEP_UNIT_POS_EVNT_DIV_8,           //!< UPEVNT = QCLK/8
    EQEP_UNIT_POS_EVNT_DIV_16,          //!< UPEVNT = QCLK/16
    EQEP_UNIT_POS_EVNT_DIV_32,          //!< UPEVNT = QCLK/32
    EQEP_UNIT_POS_EVNT_DIV_64,          //!< UPEVNT = QCLK/64
    EQEP_UNIT_POS_EVNT_DIV_128,         //!< UPEVNT = QCLK/128
    EQEP_UNIT_POS_EVNT_DIV_256,         //!< UPEVNT = QCLK/256
    EQEP_UNIT_POS_EVNT_DIV_512,         //!< UPEVNT = QCLK/512
    EQEP_UNIT_POS_EVNT_DIV_1024,        //!< UPEVNT = QCLK/1024
    EQEP_UNIT_POS_EVNT_DIV_2048         //!< UPEVNT = QCLK/2048
} EQEP_UPEVNTPrescale;

//*****************************************************************************
//
//! Values that can be passed to EQEP_setStrobeSource() as the \e strobeSrc
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EQEP_STROBE_FROM_GPIO  = 0,         //!< Strobe signal comes from GPIO
    EQEP_STROBE_OR_ADCSOCA = 2,         //!< Strobe signal is OR'd with ADCSOCA
    EQEP_STROBE_OR_ADCSOCB = 3          //!< Strobe signal is OR'd with ADCSOCB
} EQEP_StrobeSource;

//*****************************************************************************
//
//! Values that can be passed to EQEP_setQMAModuleMode() as the \e qmaMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    EQEP_QMA_MODE_BYPASS,               //!< QMA module is bypassed
    EQEP_QMA_MODE_1,                    //!< QMA mode-1 operation is selected
    EQEP_QMA_MODE_2                     //!< QMA mode-2 operation is selected
} EQEP_QMAMode;



//*****************************************************************************
//
//! Possible values of sources for QEPA,QEPB and Index signal which are passed
//! as a structure to EQEP_selectSource() as \e sourceConfig
//
//*****************************************************************************
typedef enum
{
    EQEP_SOURCE_DEVICE_PIN  = 0x0000U,   //!<  signal comes from Device Pin
    EQEP_SOURCE_CMPSS1 = 0x0001U,        //!<  signal comes from CMPSS1
    EQEP_SOURCE_CMPSS2 = 0x0002U,        //!<  signal comes from CMPSS2
    EQEP_SOURCE_CMPSS3 = 0x0003U,        //!<  signal comes from CMPSS3
    EQEP_SOURCE_CMPSS4 = 0x0004U,        //!<  signal comes from CMPSS4
    EQEP_SOURCE_ZERO   = 0x0008U,        //!<  signal tied to zero
    EQEP_SOURCE_PWMXBAR1 = 0x0009U,      //!<  signal comes from PWMXBAR1
    EQEP_SOURCE_PWMXBAR2 = 0x000AU,      //!<  signal comes from PWMXBAR2
    EQEP_SOURCE_PWMXBAR3 = 0x000BU,      //!<  signal comes from PWMXBAR3
    EQEP_SOURCE_PWMXBAR4 = 0x000CU,      //!<  signal comes from PWMXBAR4
    EQEP_SOURCE_PWMXBAR5 = 0x000DU,      //!<  signal comes from PWMXBAR5
    EQEP_SOURCE_PWMXBAR6 = 0x000EU,      //!<  signal comes from PWMXBAR6
    EQEP_SOURCE_PWMXBAR7 = 0x000FU,      //!<  signal comes from PWMXBAR7
} EQEP_Source;

//*****************************************************************************
//
//! Structure to be passed to EQEP_selectSource() as \e sourceConfig
//
//*****************************************************************************
typedef struct {
    EQEP_Source sourceA;
    EQEP_Source sourceB;
    EQEP_Source sourceIndex;
}EQEP_SourceSelect;

//*****************************************************************************
//
//! Values that can be passed to EQEP_setEmulationMode() as the \e emuMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
  EQEP_EMULATIONMODE_STOPIMMEDIATELY,   //!< Counters stop immediately
  EQEP_EMULATIONMODE_STOPATROLLOVER,    //!< Counters stop at period rollover
  EQEP_EMULATIONMODE_RUNFREE            //!< Counter unaffected by suspend
}EQEP_EmulationMode;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an eQEP base address.
//!
//! \param base specifies the eQEP module base address.
//!
//! This function determines if a eQEP module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enables the eQEP module.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables operation of the enhanced quadrature encoder pulse
//! (eQEP) module.  The module must be configured before it is enabled.
//!
//! \sa EQEP_setConfig()
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the eQEP module.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x8U;
}

//*****************************************************************************
//
//! Disables the eQEP module.
//!
//! \param base is the base address of the enhanced quadrature encoder pulse
//! (eQEP) module
//!
//! This function disables operation of the eQEP module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the eQEP module.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &= ~(0x8U);
}

//*****************************************************************************
//
//! Configures eQEP module's quadrature decoder unit.
//!
//! \param base is the base address of the eQEP module.
//! \param config is the configuration for the eQEP module decoder unit.
//!
//! This function configures the operation of the eQEP module's quadrature
//! decoder unit.  The \e config parameter provides the configuration
//! of the decoder and is the logical OR of several values:
//!
//! - \b EQEP_CONFIG_2X_RESOLUTION or \b EQEP_CONFIG_1X_RESOLUTION specify
//!   if both rising and falling edges should be counted or just rising edges.
//! - \b EQEP_CONFIG_QUADRATURE, \b EQEP_CONFIG_CLOCK_DIR,
//!   \b EQEP_CONFIG_UP_COUNT, or \b EQEP_CONFIG_DOWN_COUNT specify if
//!   quadrature signals are being provided on QEPA and QEPB, if a direction
//!   signal and a clock are being provided, or if the direction should be
//!   hard-wired for a single direction with QEPA used for input.
//! - \b EQEP_CONFIG_NO_SWAP or \b EQEP_CONFIG_SWAP to specify if the
//!   signals provided on QEPA and QEPB should be swapped before being
//!   processed.
//! - \b EQEP_CONFIG_IGATE_DISABLE or \b EQEP_CONFIG_IGATE_ENABLE to specify
//!   if the gating of the index pulse should be enabled or disabled
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setDecoderConfig(uint32_t base, uint16_t config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the new decoder configuration to the hardware.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &
                                     ~(0x400U |
                                       0x800U |
                                       0xC000U |
                                       0x200U)) | config;
}

//*****************************************************************************
//
//! Configures eQEP module position counter unit.
//!
//! \param base is the base address of the eQEP module.
//! \param mode is the configuration for the eQEP module position counter.
//! \param maxPosition specifies the maximum position value.
//!
//! This function configures the operation of the eQEP module position
//! counter.  The \e mode parameter determines the event on which the position
//! counter gets reset. It should be passed one of the following values:
//! \b EQEP_POSITION_RESET_IDX, \b EQEP_POSITION_RESET_MAX_POS,
//! \b EQEP_POSITION_RESET_1ST_IDX, or \b EQEP_POSITION_RESET_UNIT_TIME_OUT.
//!
//! \e maxPosition is the maximum value of the position counter and is
//! the value used to reset the position capture when moving in the reverse
//! (negative) direction.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode,
                              uint32_t maxPosition)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the position counter reset configuration to the hardware.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &
                                    ~0x3000U) | (uint16_t)mode;

    //
    // Set the maximum position.
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) = maxPosition;
}

//*****************************************************************************
//
//! Gets the current encoder position.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the current position of the encoder.  Depending upon
//! the configuration of the encoder, and the incident of an index pulse, this
//! value may or may not contain the expected data (that is, if in reset on
//! index mode, if an index pulse has not been encountered, the position
//! counter is not yet aligned with the index pulse).
//!
//! \return The current position of the encoder.
//
//*****************************************************************************
static inline uint32_t
EQEP_getPosition(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current position counter.
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))));
}

//*****************************************************************************
//
//! Sets the current encoder position.
//!
//! \param base is the base address of the eQEP module.
//! \param position is the new position for the encoder.
//!
//! This function sets the current position of the encoder; the encoder
//! position is then measured relative to this value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setPosition(uint32_t base, uint32_t position)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the position counter.
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) = position;
}

//*****************************************************************************
//
//! Gets the current direction of rotation.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the current direction of rotation.  In this case,
//! current means the most recently detected direction of the encoder; it may
//! not be presently moving but this is the direction it last moved before it
//! stopped.
//!
//! \return Returns 1 if moving in the forward direction or -1 if moving in the
//! reverse direction.
//
//*****************************************************************************
static inline int16_t
EQEP_getDirection(uint32_t base)
{
    int16_t direction;

    //
    // Check the arguments.
    //
    ;

    //
    // Return the direction of rotation.
    //
    if(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x20U) != 0U)
    {
        direction = 1;
    }
    else
    {
        direction = -1;
    }

    return(direction);
}

//*****************************************************************************
//
//! Enables individual eQEP module interrupt sources.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables eQEP module interrupt sources. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the specified interrupts.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) |= intFlags;
}

//*****************************************************************************
//
//! Disables individual eQEP module interrupt sources.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables eQEP module interrupt sources. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the specified interrupts.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) &= ~(intFlags);
}

//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the interrupt status for the eQEP module
//! module.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! the following values:
//! - \b EQEP_INT_GLOBAL - Global interrupt flag
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//
//*****************************************************************************
static inline uint16_t
EQEP_getInterruptStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0x19U)))));
}

//*****************************************************************************
//
//! Clears eQEP module interrupt sources.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears eQEP module interrupt flags. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_GLOBAL - Global interrupt flag
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//!
//! Note that the \b EQEP_INT_GLOBAL value is the global interrupt flag. In
//! order to get any further eQEP interrupts, this flag must be cleared.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the requested interrupt sources.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1AU)))) = intFlags;
}

//*****************************************************************************
//
//! Forces individual eQEP module interrupts.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be forced.
//!
//! This function forces eQEP module interrupt flags. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_POS_CNT_ERROR
//! - \b EQEP_INT_PHASE_ERROR
//! - \b EQEP_INT_DIR_CHANGE
//! - \b EQEP_INT_WATCHDOG
//! - \b EQEP_INT_UNDERFLOW
//! - \b EQEP_INT_OVERFLOW
//! - \b EQEP_INT_POS_COMP_READY
//! - \b EQEP_INT_POS_COMP_MATCH
//! - \b EQEP_INT_STROBE_EVNT_LATCH
//! - \b EQEP_INT_INDEX_EVNT_LATCH
//! - \b EQEP_INT_UNIT_TIME_OUT
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_forceInterrupt(uint32_t base, uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Force the specified interrupts.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1BU)))) |= intFlags;
}

//*****************************************************************************
//
//! Gets the encoder error indicator.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the error indicator for the eQEP module.  It is an
//! error for both of the signals of the quadrature input to change at the same
//! time.
//!
//! \return Returns \b true if an error has occurred and \b false otherwise.
//
//*****************************************************************************
static inline _Bool
EQEP_getError(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the error indicator.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x19U)))) & 0x4U) != 0U);
}

//*****************************************************************************
//
//! Returns content of the eQEP module status register
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the contents of the status register.  The value it
//! returns is an OR of the following values:
//!
//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected
//! - \b EQEP_STS_DIR_ON_1ST_IDX - If set, clockwise rotation (forward
//!   movement) occurred on the first index event
//! - \b EQEP_STS_DIR_FLAG - If set, movement is clockwise rotation
//! - \b EQEP_STS_DIR_LATCH - If set, clockwise rotation occurred on last
//!   index event marker
//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer
//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position
//!   capture events
//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index
//!   pulse
//! - \b EQEP_STS_POS_CNT_ERROR - Position counter error occurred
//!
//! \return Returns the value of the QEP status register.
//
//*****************************************************************************
static inline uint16_t
EQEP_getStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the status register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x00FFU);
}

//*****************************************************************************
//
//! Clears selected fields of the eQEP module status register
//!
//! \param base is the base address of the eQEP module.
//! \param statusFlags is the bit mask of the status flags to be cleared.
//!
//! This function clears the status register fields indicated by
//! \e statusFlags. The \e statusFlags parameter is the logical OR of any of
//! the following:
//!
//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected
//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer
//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position
//!   capture events
//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index
//!   pulse
//!
//! \note Only the above status fields can be cleared. All others are
//! read-only, non-sticky fields.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_clearStatus(uint32_t base, uint16_t statusFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the requested interrupt sources.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) = statusFlags;
}

//*****************************************************************************
//
//! Configures eQEP module edge-capture unit.
//!
//! \param base is the base address of the eQEP module.
//! \param capPrescale is the prescaler setting of the eQEP capture timer clk.
//! \param evntPrescale is the prescaler setting of the unit position event
//! frequency.
//!
//! This function configures the operation of the eQEP module edge-capture
//! unit.  The \e capPrescale parameter provides the configuration of the eQEP
//! capture timer clock rate. It determines by which power of 2 between 1 and
//! 128 inclusive SYSCLKOUT is divided. The macros for this parameter are in
//! the format of EQEP_CAPTURE_CLK_DIV_X, where X is the divide value. For
//! example, \b EQEP_CAPTURE_CLK_DIV_32 will give a capture timer clock
//! frequency that is SYSCLKOUT/32.
//!
//! The \e evntPrescale parameter determines how frequently a unit position
//! event occurs. The macro that can be passed this parameter is in the format
//! EQEP_UNIT_POS_EVNT_DIV_X, where X is the number of quadrature clock
//! periods between unit position events. For example,
//! \b EQEP_UNIT_POS_EVNT_DIV_16 will result in a unit position event
//! frequency of QCLK/16.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale,
                      EQEP_UPEVNTPrescale evntPrescale)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write new prescaler configurations to the appropriate registers.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) =
                            ((*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) &
                             ~(0xFU | 0x70U)) |
                            ((uint16_t)evntPrescale | (uint16_t)capPrescale);
}

//*****************************************************************************
//
//! Enables the eQEP module edge-capture unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables operation of the eQEP module's edge-capture unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableCapture(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable edge capture.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) |= 0x8000U;
}

//*****************************************************************************
//
//! Disables the eQEP module edge-capture unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's edge-capture unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableCapture(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable edge capture.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) &= ~(0x8000U);
}

//*****************************************************************************
//
//! Gets the encoder capture period.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the period count value between the last successive
//! eQEP position events.
//!
//! \return The period count value between the last successive position events.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCapturePeriod(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the capture period.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))));
}

//*****************************************************************************
//
//! Gets the encoder capture timer value.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the time base for the edge capture unit.
//!
//! \return The capture timer value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCaptureTimer(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the capture timer value.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x1DU)))));
}

//*****************************************************************************
//
//! Enables the eQEP module position-compare unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables operation of the eQEP module's position-compare unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableCompare(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable position compare.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) |= 0x1000U;
}

//*****************************************************************************
//
//! Disables the eQEP module position-compare unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's position-compare
//! unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableCompare(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable position compare.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) &= ~(0x1000U);
}

//*****************************************************************************
//
//! Configures the position-compare unit's sync output pulse width.
//!
//! \param base is the base address of the eQEP module.
//! \param cycles is the width of the pulse that can be generated on a
//! position-compare event.  It is in units of 4 SYSCLKOUT cycles.
//!
//! This function configures the width of the sync output pulse.  The width of
//! the pulse will be \e cycles * 4 * the width of a SYSCLKOUT cycle.  The
//! maximum width is 4096 * 4 * SYSCLKOUT cycles.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set the pulse width.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) &
                                     ~(uint16_t)0xFFFU) |
                                    (cycles - 1U);
}

//*****************************************************************************
//
//! Loads the eQEP module unit timer period as number of SYSCLK cycles.
//!
//! \param base is the base address of the eQEP module.
//! \param period is period value at which a unit time-out interrupt is set.
//!
//! This function sets the unit time-out interrupt when it matches the value
//! specified by \e period
//! The unit timer is clocked by SYSCLKOUT
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_loadUnitTimer(uint32_t base, uint32_t period)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the period of the unit timer.
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x10U)))) = period;
}

//*****************************************************************************
//
//! Enables the eQEP module unit timer.
//!
//! \param base is the base address of the eQEP module.
//! \param period is period value at which a unit time-out interrupt is set.
//!
//! This function enables operation of the eQEP module's peripheral unit timer.
//! The unit timer is clocked by SYSCLKOUT and will set the unit time-out
//! interrupt when it matches the value specified by \e period.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableUnitTimer(uint32_t base, uint32_t period)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the period of the unit timer.
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x10U)))) = period;

    //
    // Enable peripheral unit timer.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x2U;
}

//*****************************************************************************
//
//! Disables the eQEP module unit timer.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's peripheral
//! unit timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableUnitTimer(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable peripheral unit timer.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &= ~(0x2U);
}

//*****************************************************************************
//
//! Enables the eQEP module watchdog timer.
//!
//! \param base is the base address of the eQEP module.
//! \param period is watchdog period value at which a time-out will occur if
//! no quadrature-clock event is detected.
//!
//! This function enables operation of the eQEP module's peripheral watchdog
//! timer.
//!
//! \note When selecting \e period, note that the watchdog timer is clocked
//! from SYSCLKOUT/64.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableWatchdog(uint32_t base, uint16_t period)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the timeout count for the eQEP peripheral watchdog timer.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x13U)))) = period;

    //
    // Enable peripheral watchdog.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Disables the eQEP module watchdog timer.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's peripheral watchdog
//! timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableWatchdog(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable peripheral watchdog.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &= ~(0x1U);
}

//*****************************************************************************
//
//! Sets the eQEP module watchdog timer value.
//!
//! \param base is the base address of the eQEP module.
//! \param value is the value to be written to the watchdog timer.
//!
//! This function sets the eQEP module's watchdog timer value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the value to the watchdog timer register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x12U)))) = value;
}

//*****************************************************************************
//
//! Gets the eQEP module watchdog timer value.
//!
//! \param base is the base address of the eQEP module.
//!
//! \return Returns the current watchdog timer value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getWatchdogTimerValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the value from the watchdog timer register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x12U)))));
}

//*****************************************************************************
//
//! Configures the mode in which the position counter is initialized.
//!
//! \param base is the base address of the eQEP module.
//! \param initMode is the configuration for initializing the position count.
//! See below for a description of this parameter.
//!
//! This function configures the events on which the position count can be
//! initialized.  The \e initMode parameter provides the mode as either
//! \b EQEP_INIT_DO_NOTHING (no action configured) or one of the following
//! strobe events, index events, or a logical OR of both a strobe event and an
//! index event.
//!
//! - \b EQEP_INIT_RISING_STROBE or \b EQEP_INIT_EDGE_DIR_STROBE specify
//!   which strobe event will initialize the position counter.
//! - \b EQEP_INIT_RISING_INDEX or \b EQEP_INIT_FALLING_INDEX specify
//!   which index event will initialize the position counter.
//!
//! Use EQEP_setSWPositionInit() to cause a software initialization and
//! EQEP_setInitialPosition() to set the value that gets loaded into the
//! position counter upon initialization.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setPositionInitMode(uint32_t base, uint16_t initMode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the init mode in the QEP Control register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &
                                    ~(0x300U | 0xC00U)) |
                                   initMode;
}

//*****************************************************************************
//
//! Sets the software initialization of the encoder position counter.
//!
//! \param base is the base address of the eQEP module.
//! \param initialize is a flag to specify if software initialization of the
//! position counter is enabled.
//!
//! This function does a software initialization of the position counter when
//! the \e initialize parameter is \b true. When \b false, the QEPCTL[SWI] bit
//! is cleared and no action is taken.
//!
//! The init value to be loaded into the position counter can be set with
//! EQEP_setInitialPosition().  Additional initialization causes can be
//! configured with EQEP_setPositionInitMode().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setSWPositionInit(uint32_t base, _Bool initialize)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set or clear the software initialization bit.
    //
    if(initialize)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) |= 0x80U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &= ~0x80U;
    }
}

//*****************************************************************************
//
//! Sets the init value for the encoder position counter.
//!
//! \param base is the base address of the eQEP module.
//! \param position is the value to be written to the position counter upon.
//! initialization.
//!
//! This function sets the init value for position of the encoder. See
//! EQEP_setPositionInitMode() to set the initialization cause or
//! EQEP_setSWPositionInit() to cause a software initialization.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setInitialPosition(uint32_t base, uint32_t position)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write position to position counter init register
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) = position;
}

//*****************************************************************************
//
//! Configures the quadrature modes in which the position count can be latched.
//!
//! \param base is the base address of the eQEP module.
//! \param latchMode is the configuration for latching of the position count
//! and several other registers.  See below for a description of this
//! parameter.
//!
//! This function configures the events on which the position count and several
//! other registers can be latched.  The \e latchMode parameter provides the
//! mode as the logical OR of several values.
//!
//! - \b EQEP_LATCH_CNT_READ_BY_CPU or \b EQEP_LATCH_UNIT_TIME_OUT specify
//!   the event that latches the position counter.  This latch register can be
//!   read using EQEP_getPositionLatch(). The capture timer and capture
//!   period are also latched based on this setting, and can be read using
//!   EQEP_getCaptureTimerLatch() and EQEP_getCapturePeriodLatch().
//! - \b EQEP_LATCH_RISING_STROBE or \b EQEP_LATCH_EDGE_DIR_STROBE
//!   specify which strobe event will latch the position counter into the
//!   strobe position latch register.  This register can be read with
//!    EQEP_getStrobePositionLatch().
//! - \b EQEP_LATCH_RISING_INDEX, \b EQEP_LATCH_FALLING_INDEX, or
//!   \b EQEP_LATCH_SW_INDEX_MARKER specify which index event will latch the
//!   position counter into the index position latch register.  This register
//!   can be read with EQEP_getIndexPositionLatch().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setLatchMode(uint32_t base, uint32_t latchMode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the latch mode in the QEP Control register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) &
                                    ~(0x4U | 0x30U |
                                      0x40U)) | latchMode;
}

//*****************************************************************************
//
//! Gets the encoder position that was latched on an index event.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the index position latch register. The
//! position counter is latched into this register on either a rising index
//! edge, a falling index edge, or a software index marker. This is configured
//! using EQEP_setLatchMode().
//!
//! \return The position count latched on an index event.
//
//*****************************************************************************
static inline uint32_t
EQEP_getIndexPositionLatch(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current position counter.
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x8U)))));
}

//*****************************************************************************
//
//! Gets the encoder position that was latched on a strobe event.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the strobe position latch register. The
//! position counter can be configured to be latched into this register on
//! rising strobe edges only or on rising strobe edges while moving clockwise
//! and falling strobe edges while moving counter-clockwise. This is configured
//! using EQEP_setLatchMode().
//!
//! \return The position count latched on a strobe event.
//
//*****************************************************************************
static inline uint32_t
EQEP_getStrobePositionLatch(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current position counter.
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))));
}

//*****************************************************************************
//
//! Gets the encoder position that was latched on a unit time-out event.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the position latch register. The
//! position counter is latched into this register either on a unit time-out
//! event.
//!
//! \return The position count latch register value.
//
//*****************************************************************************
static inline uint32_t
EQEP_getPositionLatch(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current position counter.
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0xCU)))));
}

//*****************************************************************************
//
//! Gets the encoder capture timer latch.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the capture timer latch register.  The
//! capture timer value is latched into this register either on a unit time-out
//! event or upon the CPU reading the eQEP position counter. This is configured
//! using EQEP_setLatchMode().
//!
//! \return The edge-capture timer latch value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCaptureTimerLatch(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current position counter.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x1FU)))));
}

//*****************************************************************************
//
//! Gets the encoder capture period latch.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the capture period latch register.  The
//! capture period value is latched into this register either on a unit
//! time-out event or upon the CPU reading the eQEP position counter. This is
//! configured using EQEP_setLatchMode().
//!
//! \return The edge-capture period latch value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCapturePeriodLatch(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current position counter.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))));
}

//*****************************************************************************
//
//! Set the quadrature mode adapter (QMA) module mode
//!
//! \param base is the base address of the eQEP module.
//! \param qmaMode is the mode in which the QMA module will operate.
//!
//! This function sets the quadrature mode adapter module mode. The possible
//! modes are passed to the function through the \e qmaMode parameter which
//! can take the values EQEP_QMA_MODE_BYPASS, EQEP_QMA_MODE_1, or
//! EQEP_QMA_MODE_2.
//!
//! To use the QMA module, you must first put the eQEP module into
//! direction-count mode (\b EQEP_CONFIG_CLOCK_DIR) using EQEP_setConfig().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setQMAModuleMode(uint32_t base, EQEP_QMAMode qmaMode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the QMA module mode into the appropriate register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) & ~0x7U) |
        (uint16_t)qmaMode;
}

//*****************************************************************************
//
//! Set the strobe input source of the eQEP module.
//!
//! \param base is the base address of the eQEP module.
//! \param strobeSrc is the source of the strobe signal.
//!
//! This function sets the source of the eQEP module's strobe signal. The
//! possible values of the \e strobeSrc parameter are
//! - \b EQEP_STROBE_FROM_GPIO - The strobe is used as-is after passing through
//!   the polarity select logic.
//! - \b EQEP_STROBE_OR_ADCSOCA - The strobe is OR'd with the ADCSOCA signal
//!   after passing through the polarity select logic.
//! - \b EQEP_STROBE_OR_ADCSOCB - The strobe is OR'd with the ADCSOCB signal
//!   after passing through the polarity select logic.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setStrobeSource(uint32_t base, EQEP_StrobeSource strobeSrc)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the strobe source selection into the appropriate register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x32U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x32U)))) & ~0x3U) |
        (uint16_t)strobeSrc;
}

//*****************************************************************************
//
//! Enables the index direction enhancement mode of the eQEP module
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables the enhancement mode for direction change
//! during Index event
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableDirectionChangeDuringIndex(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    //Sets the index direction enhancement bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Disables the index direction enhancement mode of the eQEP module
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables the enhancement mode for direction change
//! during Index event
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableDirectionChangeDuringIndex(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    //Clears the index direction enhancement bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) &= ~(0x1U);
}

//*****************************************************************************
//
//! Selects the source for eQEPA/B/I signals
//!
//! \param base is the base address of the enhanced quadrature encoder pulse
//! (eQEP) module
//! \param sourceConfig is the structure that contains source configuration
//!
//! This function configures the sources for QEPA,QEPB and Index of eQEP module
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_selectSource(uint32_t base, EQEP_SourceSelect sourceConfig )
{
    //
    // Check the arguments.
    //
    ;

    //
    // Selecting sources for eQEP signals
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x36U)))) =
           ((*((volatile uint32_t *)((uintptr_t)(base + 0x36U)))) & ~(0xFU |
             0xF0U | 0xF00U)) |
           ((uint32_t)((uint32_t)(sourceConfig.sourceA) <<
                                   0U) |
            (uint32_t)((uint32_t)(sourceConfig.sourceB) <<
                                   4U) |
            (uint32_t)((uint32_t)(sourceConfig.sourceIndex) <<
                                    8U));
}

//*****************************************************************************
//
//! Set the emulation mode of the eQEP module.
//!
//! \param base is the base address of the eQEP module.
//! \param emuMode is the mode operation upon an emulation suspend.
//!
//! This function sets the eQEP module's emulation mode. This mode determines
//! how the timers are affected by an emulation suspend. Valid values for the
//! \e emuMode parameter are the following:
//!
//! - \b EQEP_EMULATIONMODE_STOPIMMEDIATELY - The position counter, watchdog
//!   counter, unit timer, and capture timer all stop immediately.
//! - \b EQEP_EMULATIONMODE_STOPATROLLOVER - The position counter, watchdog
//!   counter, unit timer all count until period rollover. The capture timer
//!   counts until the next unit period event.
//! - \b EQEP_EMULATIONMODE_RUNFREE - The position counter, watchdog counter,
//!   unit timer, and capture timer are all unaffected by an emulation suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the emulation mode to the FREE_SOFT bits.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) =
        ((*((volatile uint16_t *)((uintptr_t)(base + 0x15U)))) & ~0xC000U) |
        ((uint16_t)emuMode << 14U);
}

//*****************************************************************************
//
//! Configures eQEP module position-compare unit.
//!
//! \param base is the base address of the eQEP module.
//! \param config is the configuration for the eQEP module
//! position-compare unit.  See below for a description of this parameter.
//! \param compareValue is the value to which the position count value is
//! compared for a position-compare event.
//! \param cycles is the width of the pulse that can be generated on a
//! position-compare event.  It is in units of 4 SYSCLKOUT cycles.
//!
//! This function configures the operation of the eQEP module position-compare
//! unit.  The \e config parameter provides the configuration of the
//! position-compare unit and is the logical OR of several values:
//!
//! - \b EQEP_COMPARE_NO_SYNC_OUT, \b EQEP_COMPARE_IDX_SYNC_OUT, or
//!   \b EQEP_COMPARE_STROBE_SYNC_OUT specify if there is a sync output pulse
//!   and which pin should be used.
//! - \b EQEP_COMPARE_NO_SHADOW, \b EQEP_COMPARE_LOAD_ON_ZERO, or
//!   \b EQEP_COMPARE_LOAD_ON_MATCH specify if a shadow is enabled and when
//!   should the load should occur--QPOSCNT = 0 or QPOSCNT = QPOSCOMP.
//!
//! The \e cycles is used to select the width of the sync output pulse. The
//! width of the resulting pulse will be \e cycles * 4 * the width of a
//! SYSCLKOUT cycle. The maximum width is 4096 * 4 * SYSCLKOUT cycles.
//!
//! \note You can set the sync pulse width independently using the
//! EQEP_setComparePulseWidth() function.
//!
//! \return None.
//
//*****************************************************************************
extern void
EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue,
                      uint16_t cycles);

//*****************************************************************************
//
//! Sets the polarity of the eQEP module's input signals.
//!
//! \param base is the base address of the eQEP module.
//! \param invertQEPA is the flag to negate the QEPA input.
//! \param invertQEPB is the flag to negate the QEPA input.
//! \param invertIndex is the flag to negate the index input.
//! \param invertStrobe is the flag to negate the strobe input.
//!
//! This function configures the polarity of the inputs to the eQEP module. To
//! negate the polarity of any of the input signals, pass \b true into its
//! corresponding parameter in this function. Pass \b false to leave it as-is.
//!
//! \return None.
//
//*****************************************************************************
extern void
EQEP_setInputPolarity(uint32_t base, _Bool invertQEPA, _Bool invertQEPB,
                      _Bool invertIndex, _Bool invertStrobe);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   erad.h
//
// TITLE:  C28x ERAD driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup erad_api ERAD
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_erad.h
//
// TITLE:   Definitions for the ERAD registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the ERAD register offsets
//
//*************************************************************************************************






//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_EVENT_STAT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_HALT_STAT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_ENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_CTM_RESET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_NMI_CTL register
//
//*************************************************************************************************
                                           // enable
                                           // enable
                                           // enable
                                           // enable
                                           // enable
                                           // enable
                                           // enable
                                           // enable

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_OWNER register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_EVENT_AND_MASK register
//
//*************************************************************************************************
                                                             // Event Mask1
                                                             // Event Mask1
                                                             // Event Mask1
                                                             // Event Mask1
                                                             // Event Mask1
                                                             // Event Mask1
                                                             // Event Mask1
                                                             // Event Mask1
                                                             // Event Mask2
                                                             // Event Mask2
                                                             // Event Mask2
                                                             // Event Mask2
                                                             // Event Mask2
                                                             // Event Mask2
                                                             // Event Mask2
                                                             // Event Mask2
                                                             // Event Mask3
                                                             // Event Mask3
                                                             // Event Mask3
                                                             // Event Mask3
                                                             // Event Mask3
                                                             // Event Mask3
                                                             // Event Mask3
                                                             // Event Mask3
                                                             // Event Mask4
                                                             // Event Mask4
                                                             // Event Mask4
                                                             // Event Mask4
                                                             // Event Mask4
                                                             // Event Mask4
                                                             // Event Mask4
                                                             // Event Mask4

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_EVENT_OR_MASK register
//
//*************************************************************************************************
                                                            // Event Mask1
                                                            // Event Mask1
                                                            // Event Mask1
                                                            // Event Mask1
                                                            // Event Mask1
                                                            // Event Mask1
                                                            // Event Mask1
                                                            // Event Mask1
                                                            // Event Mask2
                                                            // Event Mask2
                                                            // Event Mask2
                                                            // Event Mask2
                                                            // Event Mask2
                                                            // Event Mask2
                                                            // Event Mask2
                                                            // Event Mask2
                                                            // Event Mask3
                                                            // Event Mask3
                                                            // Event Mask3
                                                            // Event Mask3
                                                            // Event Mask3
                                                            // Event Mask3
                                                            // Event Mask3
                                                            // Event Mask3
                                                            // Event Mask4
                                                            // Event Mask4
                                                            // Event Mask4
                                                            // Event Mask4
                                                            // Event Mask4
                                                            // Event Mask4
                                                            // Event Mask4
                                                            // Event Mask4

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_AND_EVENT_INT_MASK register
//
//*************************************************************************************************
                                                            // AND events
                                                            // AND events
                                                            // AND events
                                                            // AND events

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_OR_EVENT_INT_MASK register
//
//*************************************************************************************************
                                                           // events
                                                           // events
                                                           // events
                                                           // events


//*************************************************************************************************
//
// The following are defines for the bit fields in the HWBP_CLEAR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HWBP_CNTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HWBP_STATUS register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_CNTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_STATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_INPUT_SEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_CLEAR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_INPUT_SEL_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_INPUT_COND register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CRC_GLOBAL_CTRL register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CRC_QUALIFIER register
//
//*************************************************************************************************




//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************

//
// Macros for but positions of some register bit fields
//


//
// Macro function for getting the instance number from the base address
//

//
// Macro function to get the HWBP event number from the base address
//

//*****************************************************************************
//
//! Values that can be passed to ERAD_enableModules() or
//! ERAD_disableModules() as \e instances parameter.
//
//*****************************************************************************


//*****************************************************************************
//
//! Values that can be passed to ERAD_setCounterInputConditioning() as options
//! parameter.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to ERAD_initModule() as \e owner parameter to
//! set owner of ERAD.
//
//*****************************************************************************
typedef enum
{
    ERAD_OWNER_NOOWNER     = 0,     //!< No owner
    ERAD_OWNER_APPLICATION = 1,     //!< Application owned
    ERAD_OWNER_DEBUGGER    = 2      //!< Debugger owned
} ERAD_Owner;

//*****************************************************************************
//
//! Values that can are returned by ERAD_getBusCompStatus() and
//! ERAD_getCounterStatus() to indicate the state of the respective module.
//
//*****************************************************************************
typedef enum
{
    ERAD_STATE_IDLE      = 0,     //!< Module is idle
    ERAD_STATE_ENABLED   = 2,     //!< Module is enabled
    ERAD_STATE_COMPLETED = 3      //!< Module was enabled and an event occurred
} ERAD_Status;

//*****************************************************************************
//
//! Values that can be passed to ERAD_configBusComp() and ERAD_profile()
//! as \e config_params.bus_sel parameter to choose which CPU bus to monitor.
//
//*****************************************************************************
typedef enum
{
    ERAD_BUSCOMP_BUS_PAB            = 0,  //!< Use the Program Address Bus
    ERAD_BUSCOMP_BUS_VPC            = 1,  //!< Use the Virtual Program Counter
    ERAD_BUSCOMP_BUS_DWAB           = 2,  //!< Use the Data Write Address Bus
    ERAD_BUSCOMP_BUS_DRAB           = 3,  //!< Use the Data Read Address Bus
    ERAD_BUSCOMP_BUS_DWDB           = 4,  //!< Use the Data Write Data Bus
    ERAD_BUSCOMP_BUS_DRDB           = 5,  //!< Use the Data Read Data Bus
    ERAD_BUSCOMP_BUS_VPC_I_ALIGNED  = 6,  //!< Use VPC Instruction aligned match
    ERAD_BUSCOMP_BUS_VPC_R1_ALIGNED = 7,  //!< Use VPC R1 aligned match
    ERAD_BUSCOMP_BUS_VPC_R2_ALIGNED = 8,  //!< Use VPC R2 aligned match
    ERAD_BUSCOMP_BUS_VPC_W_ALIGNED  = 9,  //!< Use VPC Word aligned match
} ERAD_BusComp_Bus_Select;

//*****************************************************************************
//
//! Values that can be passed to ERAD_configBusComp() and ERAD_profile()
//! as \e config_params.comp_mode to indicate what kind of comparison to use
//! for the bus comparators.
//
//*****************************************************************************
typedef enum
{
    ERAD_BUSCOMP_COMPMODE_GT = 4,         //!< Check for greater than
    ERAD_BUSCOMP_COMPMODE_GE = 5,         //!< Check for greater than equal to
    ERAD_BUSCOMP_COMPMODE_LT = 6,         //!< Check for lesser than
    ERAD_BUSCOMP_COMPMODE_LE = 7,         //!< Check for lesser than equal to
    ERAD_BUSCOMP_COMPMODE_EQ = 0          //!< Check for only equality
} ERAD_BusComp_Comp_Mode;

//*****************************************************************************
//
//! Values that can be passed to ERAD_configCounterInStartStopMode()
//! and ERAD_configCounterInCountingMode() as \e config_params.event_mode to
//! indicate whether to count rising edges or the number of CPU clock cycles an
//! is active.
//
//*****************************************************************************
typedef enum
{
    ERAD_COUNTER_MODE_ACTIVE      = 0,     //!< Count number of CPU
                                           //!  Cycles event is active for
    ERAD_COUNTER_MODE_RISING_EDGE = 1      //!< Count number of Rising
                                           //!  Edges of event
} ERAD_Counter_Event_Mode;

//*****************************************************************************
//
//! Values that can be passed to ERAD_configCounterInStartStopMode()
//! and ERAD_configCounterInCountingMode() as \e config_params.event to
//! indicate what event to consider as input. Also may be passed to
//! ERAD_configCounterInStartStopMode() as \e start_event and \e stop_event
//! to indicate start and stop events for the counter.
//
//*****************************************************************************
typedef enum
{
    ERAD_EVENT_HWBP1                   = 0,
    ERAD_EVENT_HWBP2                   = 1,
    ERAD_EVENT_HWBP3                   = 2,
    ERAD_EVENT_HWBP4                   = 3,
    ERAD_EVENT_HWBP5                   = 4,
    ERAD_EVENT_HWBP6                   = 5,
    ERAD_EVENT_HWBP7                   = 6,
    ERAD_EVENT_HWBP8                   = 7,
    ERAD_EVENT_COUNTER1_EVENT          = 8,
    ERAD_EVENT_COUNTER2_EVENT          = 9,
    ERAD_EVENT_COUNTER3_EVENT          = 10,
    ERAD_EVENT_COUNTER4_EVENT          = 11,
    ERAD_EVENT_ERAD_OR_MASK0           = 12,
    ERAD_EVENT_ERAD_OR_MASK1           = 13,
    ERAD_EVENT_ERAD_OR_MASK2           = 14,
    ERAD_EVENT_ERAD_OR_MASK3           = 15,
    ERAD_EVENT_ERAD_AND_MASK0          = 16,
    ERAD_EVENT_ERAD_AND_MASK1          = 17,
    ERAD_EVENT_ERAD_AND_MASK2          = 18,
    ERAD_EVENT_ERAD_AND_MASK3          = 19,
    ERAD_EVENT_PIE_INT1                = 20,
    ERAD_EVENT_PIE_INT2                = 21,
    ERAD_EVENT_PIE_INT3                = 22,
    ERAD_EVENT_PIE_INT4                = 23,
    ERAD_EVENT_PIE_INT5                = 24,
    ERAD_EVENT_PIE_INT6                = 25,
    ERAD_EVENT_PIE_INT7                = 26,
    ERAD_EVENT_PIE_INT8                = 27,
    ERAD_EVENT_PIE_INT9                = 28,
    ERAD_EVENT_PIE_INT10               = 29,
    ERAD_EVENT_PIE_INT11               = 30,
    ERAD_EVENT_PIE_INT12               = 31,
    ERAD_EVENT_TIMER1_TINT0            = 32,
    ERAD_EVENT_TIMER1_TINT1            = 33,
    ERAD_EVENT_TIMER2_TINT2            = 34,
    ERAD_EVENT_DMACH1INT               = 35,
    ERAD_EVENT_DMACH2INT               = 36,
    ERAD_EVENT_DMACH3INT               = 37,
    ERAD_EVENT_DMACH4INT               = 38,
    ERAD_EVENT_DMACH5INT               = 39,
    ERAD_EVENT_DMACH6INT               = 40,
    ERAD_EVENT_FSI_DATA_PKT_RCVD          = 41,
    ERAD_EVENT_FSI_ERROR_PKT_RCVD         = 42,
    ERAD_EVENT_FSI_PING_PKT_RCVD          = 43,
    ERAD_EVENT_FSI_PING_FRAME_TAG_MATCH   = 44,
    ERAD_EVENT_FSI_DATA_FRAME_TAG_MATCH   = 45,
    ERAD_EVENT_FSI_ERROR_FRAME_TAG_MATCH  = 46,
    ERAD_EVENT_FSI_FRAME_DONE             = 47,
    ERAD_EVENT_ADCAEVTINT              = 48,
    ERAD_EVENT_ADCCEVTINT              = 49,
    ERAD_EVENT_MCANA_EVT0              = 50,
    ERAD_EVENT_MCANA_EVT1              = 51,
    ERAD_EVENT_MCANA_EVT2              = 52,
    ERAD_EVENT_ADCSOCA                 = 53,
    ERAD_EVENT_ADCSOCB                 = 54,
    ERAD_EVENT_CLATASKRUN1             = 55,
    ERAD_EVENT_CLATASKRUN2             = 56,
    ERAD_EVENT_CLATASKRUN3             = 57,
    ERAD_EVENT_CLATASKRUN4             = 58,
    ERAD_EVENT_CLATASKRUN5             = 59,
    ERAD_EVENT_CLATASKRUN6             = 60,
    ERAD_EVENT_CLATASKRUN7             = 61,
    ERAD_EVENT_CLATASKRUN8             = 62,
    ERAD_EVENT_EPWMXBAR_OUT1           = 63,
    ERAD_EVENT_EPWMXBAR_OUT2           = 64,
    ERAD_EVENT_EPWMXBAR_OUT3           = 65,
    ERAD_EVENT_EPWMXBAR_OUT4           = 66,
    ERAD_EVENT_EPWMXBAR_OUT5           = 67,
    ERAD_EVENT_EPWMXBAR_OUT6           = 68,
    ERAD_EVENT_EPWMXBAR_OUT7           = 69,
    ERAD_EVENT_EPWMXBAR_OUT8           = 70,
    ERAD_EVENT_INPUTXBAR0              = 71,
    ERAD_EVENT_INPUTXBAR1              = 72,
    ERAD_EVENT_INPUTXBAR2              = 73,
    ERAD_EVENT_INPUTXBAR3              = 74,
    ERAD_EVENT_INPUTXBAR4              = 75,
    ERAD_EVENT_INPUTXBAR5              = 76,
    ERAD_EVENT_INPUTXBAR6              = 77,
    ERAD_EVENT_INPUTXBAR7              = 78,
    ERAD_EVENT_INPUTXBAR8              = 79,
    ERAD_EVENT_INPUTXBAR9              = 80,
    ERAD_EVENT_INPUTXBAR10             = 81,
    ERAD_EVENT_INPUTXBAR11             = 82,
    ERAD_EVENT_INPUTXBAR12             = 83,
    ERAD_EVENT_INPUTXBAR13             = 84,
    ERAD_EVENT_INPUTXBAR14             = 85,
    ERAD_EVENT_INPUTXBAR15             = 86,
    ERAD_EVENT_CPUx_CPUSTAT            = 87,
    ERAD_EVENT_CPUx_DBGACK             = 88,
    ERAD_EVENT_CPUx_NMI                = 89,
    ERAD_EVENT_CMPSS1_CTRIPH_OR_CTRIPL = 90,
    ERAD_EVENT_CMPSS2_CTRIPH_OR_CTRIPL = 91,
    ERAD_EVENT_CMPSS3_CTRIPH_OR_CTRIPL = 92,
    ERAD_EVENT_CMPSS4_CTRIPH_OR_CTRIPL = 93,
    ERAD_EVENT_SD1FLT1_COMPH_OR_COMPL  = 98,
    ERAD_EVENT_SD1FLT2_COMPH_OR_COMPL  = 99,
    ERAD_EVENT_SD1FLT3_COMPH_OR_COMPL  = 100,
    ERAD_EVENT_SD1FLT4_COMPH_OR_COMPL  = 101,
    ERAD_EVENT_SD2FLT1_COMPH_OR_COMPL  = 102,
    ERAD_EVENT_SD2FLT2_COMPH_OR_COMPL  = 103,
    ERAD_EVENT_SD2FLT3_COMPH_OR_COMPL  = 104,
    ERAD_EVENT_SD2FLT4_COMPH_OR_COMPL  = 105,
    ERAD_EVENT_ADCAINT1                = 106,
    ERAD_EVENT_ADCAINT2                = 107,
    ERAD_EVENT_ADCAINT3                = 108,
    ERAD_EVENT_ADCAINT4                = 109,
    ERAD_EVENT_ADCBINT1                = 110,
    ERAD_EVENT_ADCBINT2                = 111,
    ERAD_EVENT_ADCBINT3                = 112,
    ERAD_EVENT_ADCBINT4                = 113,
    ERAD_EVENT_ADCCINT1                = 114,
    ERAD_EVENT_ADCCINT2                = 115,
    ERAD_EVENT_ADCCINT3                = 116,
    ERAD_EVENT_ADCCINT4                = 117,
    ERAD_EVENT_HIC_nOE                 = 122,
    ERAD_EVENT_HIC_nWE                 = 123,
    ERAD_EVENT_HIC_nRDY                = 124,
    ERAD_EVENT_ADCBEVTINT            = 125,

    ERAD_EVENT_NO_EVENT                = 128
} ERAD_Counter_Input_Event;

typedef enum
{
    ERAD_AND_MASK1 = 0,
    ERAD_AND_MASK2 = 1,
    ERAD_AND_MASK3 = 2,
    ERAD_AND_MASK4 = 3,
    ERAD_OR_MASK1  = 4,
    ERAD_OR_MASK2  = 5,
    ERAD_OR_MASK3  = 6,
    ERAD_OR_MASK4  = 7
} ERAD_Mask;

//*****************************************************************************
//
//! Values that can be passed to ERAD_setCRCQualifier() as the \e qualifier
//! paramter to specify which events to set as the qualifier for the CRC unit.
//
//*****************************************************************************
typedef enum
{
    ERAD_CRC_QUAL_NONE      = 0,  //!< Use every valid event as qualifier
                                  //!< for CRC computation
    ERAD_CRC_QUAL_HWBP1     = 1,  //!< CRC Compute Qualified by HWBP_EVENT1
    ERAD_CRC_QUAL_HWBP2     = 2,  //!< CRC Compute Qualified by HWBP_EVENT2
    ERAD_CRC_QUAL_HWBP3     = 3,  //!< CRC Compute Qualified by HWBP_EVENT3
    ERAD_CRC_QUAL_HWBP4     = 4,  //!< CRC Compute Qualified by HWBP_EVENT4
    ERAD_CRC_QUAL_HWBP5     = 5,  //!< CRC Compute Qualified by HWBP_EVENT5
    ERAD_CRC_QUAL_HWBP6     = 6,  //!< CRC Compute Qualified by HWBP_EVENT6
    ERAD_CRC_QUAL_HWBP7     = 7,  //!< CRC Compute Qualified by HWBP_EVENT7
    ERAD_CRC_QUAL_HWBP8     = 8,  //!< CRC Compute Qualified by HWBP_EVENT8
    ERAD_CRC_QUAL_HWBP_OR1  = 9,  //!< CRC Compute Qualified by HWBP_EVENT_OR1
    ERAD_CRC_QUAL_HWBP_OR2  = 10, //!< CRC Compute Qualified by HWBP_EVENT_OR1
    ERAD_CRC_QUAL_HWBP_OR3  = 11, //!< CRC Compute Qualified by HWBP_EVENT_OR1
    ERAD_CRC_QUAL_HWBP_OR4  = 12, //!< CRC Compute Qualified by HWBP_EVENT_OR1
    ERAD_CRC_QUAL_HWBP_AND1 = 13, //!< CRC Compute Qualified by HWBP_EVENT_AND2
    ERAD_CRC_QUAL_HWBP_AND2 = 14, //!< CRC Compute Qualified by HWBP_EVENT_AND2
    ERAD_CRC_QUAL_HWBP_AND3 = 15, //!< CRC Compute Qualified by HWBP_EVENT_AND2
    ERAD_CRC_QUAL_HWBP_AND4 = 16  //!< CRC Compute Qualified by HWBP_EVENT_AND2
} ERAD_CRC_Qualifiers;

//*****************************************************************************
//
//! Values that can be passed to ERAD_setCounterInputConditioning() as
//! \e input_type parameter. To specify which input to condition.
//
//*****************************************************************************
typedef enum
{
    ERAD_COUNTER_COUNT_INPUT = 0,
    ERAD_COUNTER_START_INPUT = 1,
    ERAD_COUNTER_STOP_INPUT  = 2,
    ERAD_COUNTER_RESET_INPUT = 3
} ERAD_Counter_Input_Type;

//*****************************************************************************
//
//! Structure that is passed to ERAD_configBusComp() as \e config_params
//! to configure a bus comparator.
//
//*****************************************************************************
typedef struct ERAD_BusComp_Config
{
    uint32_t               mask;        //!< Mask to be used for comparing
    uint32_t               reference;   //!< Reference value to be compared
    ERAD_BusComp_Comp_Mode comp_mode;   //!< Comparison mode
    _Bool                   enable_int;  //!< Enable Interrupt on event match
    _Bool                   enable_stop; //!< Enable CPU halt on event match
    ERAD_BusComp_Bus_Select bus_sel;    //!< Bus to be monitored
} ERAD_BusComp_Config;

//*****************************************************************************
//
//! Structure that is passed to ERAD_profile() as \e config_params to setup
//! the required modules appropriately for each use case.
//
//*****************************************************************************
typedef struct ERAD_Profile_Params
{
    uint32_t                start_address;  //!< Start address
    uint32_t                end_address;    //!< End address
    ERAD_BusComp_Bus_Select bus_sel;        //!< Bus to be monitored
    uint32_t                busComp_base1;  //!< Bus comparators to be used
    uint32_t                busComp_base2;  //!< Bus comparators to be used
    uint32_t                counter_base;   //!< Counter to be used
} ERAD_Profile_Params;

//*****************************************************************************
//
//! Structure that is passed to ERAD_configCounterInStartStopMode() and
//! ERA_configCounterInCountingMode() as \e config_params to setup a
//! counter appropriately.
//
//*****************************************************************************
typedef struct ERAD_Counter_Config
{
    ERAD_Counter_Input_Event event;        //!< Input Event to be counted
    ERAD_Counter_Event_Mode  event_mode;   //!< Active / rising edge
    uint32_t                 reference;    //!< Reference to be compared
    _Bool                     rst_on_match; //!< Enable counter reset on match
    _Bool                     enable_int;   //!< Enable Interrupt on match
    _Bool                     enable_stop;  //!< Enable CPU halt on match
} ERAD_Counter_Config;

//*****************************************************************************
//
//! Structure that is passed to ERAD_enableInterruptOnAddressHit() and
//! ERAD_countAddressHits() as \e config_params to select the bus and the
//! address to compare. \e bus_Sel can be one of the following:
//! \b ERAD_BUSCOMP_BUS_PAB   : for instruction fetch at the address
//! \b ERAD_BUSCOMP_BUS_DWAB  : for data write access to the address
//! \b ERAD_BUSCOMP_BUS_DRAB  : for data read access to the address
//
//*****************************************************************************
typedef struct ERAD_Count_Params
{
    uint32_t                address;    //!< Address to compare
    uint32_t                mask;       //!< Mask for the address compare
    ERAD_BusComp_Bus_Select bus_sel;    //!< Bus to be monitored
} ERAD_AddressHit_Params;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************


//*****************************************************************************
//
//! Gets the current owner of ERAD.
//!
//! \param None.
//!
//! This function returns the current owner of ERAD.
//!
//! \return Owner of ERAD.
//
//*****************************************************************************
static inline ERAD_Owner
ERAD_getOwnership()
{
    //
    // Read Global Owner register and return value
    //
    return((ERAD_Owner)((*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0xAU)))) &
                        0x3U) >> 0U);
}

//*****************************************************************************
//
//! Sets the current owner of ERAD.
//!
//! \param owner is the Owner of ERAD that is to be set
//!
//! This function sets the current owner of ERAD.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setOwnership(ERAD_Owner owner)
{
    //
    // Set the Global Owner as owner
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0xAU)))) =
                (owner & 0x3U) << 0U;
    __edis();
}

//*****************************************************************************
//
//! Resets the counter using the global registers.
//!
//! \param instances is the OR'd value of counter instances to be reset.
//! Following macros can be used:
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function resets the selected counters using the global registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_resetCounter(uint16_t instances)
{
    //
    // Resets the counter by writing into the global registers
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0x6U)))) |= instances >> 8U;
    __edis();
}

//*****************************************************************************
//
//! Enables counters and bus comparators.
//!
//! \param instances is the OR'd value of instances of the counters and bus
//! comparators. Following macros can be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function enables bus comparators and counters whose instances are
//! passed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableModules(uint16_t instances)
{
    //
    // Write into Global register for enabling the required modules
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0x4U)))) |= instances;
    __edis();
}

//*****************************************************************************
//
//! Disables counters and bus comparators.
//!
//! \param instances is the OR'd value of instances of the counters and bus
//! comparators. Following macros can be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function disables bus comparators and counters whose instances are
//! passed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableModules(uint16_t instances)
{
    //
    // Write into Global register for disabling the required modules
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0x4U)))) &= (~instances);
    __edis();
}

//*****************************************************************************
//
//! Initialises ERAD.
//!
//! \param owner is the owner of ERAD that is to be set.
//!
//! This function resets all the counters and disables all bus comparators and
//! counters.
//! Also sets the owner of the ERAD to the required owner.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_initModule(ERAD_Owner owner)
{
    //
    // Set the owner of ERAD as required
    //
    ERAD_setOwnership(owner);

    //
    // Disable all counters and bus comparators
    //
    ERAD_disableModules(0x00000001UL | 0x00000002UL |
                        0x00000004UL | 0x00000008UL |
                        0x00000010UL | 0x00000020UL |
                        0x00000040UL | 0x00000080UL |
                        0x00000100UL | 0x00000200UL |
                        0x00000400UL | 0x00000800UL);

    //
    // Reset all counters
    //
    ERAD_resetCounter(0x00000100UL | 0x00000200UL |
                      0x00000400UL | 0x00000800UL);
}

//*****************************************************************************
//
//! Returns the completed status of any of the modules.
//!
//! \param None.
//!
//! This function returns the completed status of the counters and bus
//! comparators as stored in the global registers. This allows us to read just
//! one register and see if any of the modules are in a completed state.
//!
//! \return Completed status of all the modules as stored in the global
//! register.
//
//*****************************************************************************
static inline uint16_t
ERAD_getHaltStatus()
{
    //
    // Read and return from the global register
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0x2U)))));
}

//*****************************************************************************
//
//! Returns the event fired status of any of the modules.
//!
//! \param None.
//!
//! This function returns the event fired status of the counters and bus
//! comparators as stored in the global registers. This allows us to read just
//! one register and see if any of the modules have fired.
//!
//! \return Event fired status of all the modules as stored in the global
//! register.
//
//*****************************************************************************
static inline uint16_t
ERAD_getEventStatus()
{
    //
    // Read and return from the global register
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0x0U)))));
}

//*****************************************************************************
//
//! Enables an NMI for the specified modules.
//!
//! \param instances is the OR'd value of the instances of the counters and
//! bus comparator units that need to have an NMI enabled. Following macros can
//! be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function enables an NMI to be generated whenever any of the specified
//! counters or bus comparator units generate and event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableNMI(uint16_t instances)
{
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0x8U)))) |= instances;
    __edis();
}

//*****************************************************************************
//
//! Disables an NMI for the specified modules.
//!
//! \param instances is the OR'd value of the instances of the counters and
//! bus comparator units that need to have an NMI disabled. Following macros can
//! be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function disables the NMI for the specified counters and bus
//! comparator units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableNMI(uint16_t instances)
{
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005E800U + 0x8U)))) &= (~instances);
    __edis();
}

//*****************************************************************************
//
//! Returns the status of a bus comparator.
//!
//! \param base is the base of the bus comparator.
//!
//! This function returns the status of the bus comparator whose base was
//! passed. It may be either \b ERAD_STATE_IDLE, \b ERAD_STATE_ENABLED or
//! \b ERAD_STATE_COMPLETED.
//!
//! \return Status of bus comparator.
//
//*****************************************************************************
static inline ERAD_Status
ERAD_getBusCompStatus(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Read and return status of bus comparator
    //
    return((ERAD_Status)(((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) &
                    0xC000U) >> 14U));
}

//*****************************************************************************
//
//! Clears the event fired status of any of the modules.
//!
//! \param base is the base of the bus comparator.
//!
//! This function clears the event fired status of the bus comparator and
//! brings the module  and brings the module back to \b ERAD_STATE_IDLE .
//!
//! \return None
//
//*****************************************************************************
static inline void
ERAD_clearBusCompEvent(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Clear the event fired bit by writing into EVENT_CLR register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Returns the status of a counter.
//!
//! \param base is the base of the counter.
//!
//! This function returns the status of the counter whose base was
//! passed. It may be either \b ERAD_STATE_IDLE, \b ERAD_STATE_ENABLED or
//! \b ERAD_STATE_COMPLETED.
//!
//! \return Status of counter.
//
//*****************************************************************************
static inline ERAD_Status
ERAD_getCounterStatus(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Read and return status of the counter
    //
    return((ERAD_Status)(((*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &
                      0xF000U) >> 12U));
}
//*****************************************************************************
//
//! Configures the bus comparators.
//!
//! \param base is the base of the bus comparator to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the bus comparator.
//!
//! This function configures the bus comparator with the given parameters.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configBusComp(uint32_t base, ERAD_BusComp_Config config_params);

//*****************************************************************************
//
//! Configures the counter in Counting mode.
//!
//! \param base is the base of the counter to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the counter.
//!
//! This function configures the counter with the given parameters. The counter
//! is setup in Counting mode, which means counting begins as soon as the
//! counter is enabled.
//! NOTE: This function does not enable the counter. The counter must be
//! enabled using the \b ERAD_enableModules method to begin counting.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configCounterInCountingMode(uint32_t base,
                                 ERAD_Counter_Config config_params);

//*****************************************************************************
//
//! Configures the counter in Start-Stop mode.
//!
//! \param base is the base of the counter to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the counter.
//! \param start_event is the event that starts the counter
//! \param stop_event is the event which stops that counter
//!
//! This function configures the counter with the given parameters. The counter
//! is setup in Start-Stop mode, which means counting will happen only between
//! two specified events. The event that will be counted can be any of the
//! \b ERAD_Counter_Input_Event and not only CPU cycles.
//! NOTE: \b ERAD_EVENT_NO_EVENT causes the counter to use the CPU cycles.
//! NOTE: This function does not enable the counter. The counter must be
//! enabled using the \b ERAD_enableModules method to begin counting.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configCounterInStartStopMode(uint32_t base,
                                    ERAD_Counter_Config config_params,
                                    ERAD_Counter_Input_Event start_event,
                                    ERAD_Counter_Input_Event stop_event);

//*****************************************************************************
//
//! Configures the counter in Start-Stop Cumulative mode.
//!
//! \param base is the base of the counter to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the counter.
//! \param start_event is the event that starts the counter
//! \param stop_event is the event which stops that counter
//!
//! This function configures the counter with the given parameters. The counter
//! is setup in Cumulative mode, which means counting will happen only between
//! two specified events and the counter will not reset on \b stop_event. The
//! event that will be counted can be any of the \b ERAD_Counter_Input_Event
//! and not only CPU cycles.
//! NOTE: \b ERAD_EVENT_NO_EVENT causes the counter to use the CPU cycles.
//! NOTE: This function does not enable the counter. The counter must be
//! enabled using the \b ERAD_enableModules method to begin counting.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configCounterInCumulativeMode(uint32_t base,
                                   ERAD_Counter_Config config_params,
                                   ERAD_Counter_Input_Event start_event,
                                   ERAD_Counter_Input_Event stop_event);

//*****************************************************************************
//
//! Configures the AND and OR masks
//!
//! \param mask is the Mask to be used.
//!
//! \param instances is the OR'd value of the instances of the  bus comparator
//!  units whose events need to be used for the mask. Following macros can be
//!  used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! \param enable_int True if interrupt needs to be enabled, False if not
//!
//! This function enables the event generated from the specified bus comparator
//! units to be used for the specified Mask. It also configures the interrupt
//! generation when the mask event occurs.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configMask(ERAD_Mask mask, uint32_t instances, _Bool enable_int);

//*****************************************************************************
//
//! Configures the reset event of the counter.
//!
//! \param base is the base of the counter to be configured.
//! \param reset_event is the event upon which the counter must be reset.
//!
//! This function sets the event upon which the counter must reset and enables
//! reset upon such an event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableCounterResetInput(uint32_t base,
                            ERAD_Counter_Input_Event reset_event)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Setup up the counter such that the reset event is set and enabled
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) |= 0x400U;
    (*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))) =
                           ((*((volatile uint32_t *)((uintptr_t)(base + 0xAU)))) &
                           ~0x7F00U) |
                           (reset_event << 8U);
    __edis();
}

//*****************************************************************************
//
//! Disables the reset event of the counter.
//!
//! \param base is the base of the counter.
//!
//! This function disables the reset event that may have been set earlier
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableCounterResetInput(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Disable the reset bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= (~0x400U);
    __edis();
}

//*****************************************************************************
//
//! Clears an event that may have fired in the counter upon match.
//!
//! \param base is the base of the counter.
//!
//! This function clears a counter event that may have fired when the counter
//! hit a match.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_clearCounterEvent(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Clear the event by writing into CTM_CLEAR register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Clears an overflow that may have occured in the counter.
//!
//! \param base is the base of the counter.
//!
//! This function clears the overflow bit that may have got set when the
//! counter may have crossed 0xFFFFFFFF.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_clearCounterOverflow(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Clear the overflow bit by writing into the CTM_CLEAR register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Gets the current count of a counter.
//!
//! \param base is the base of the counter.
//!
//! This function returns the current count of the counter which was
//! configured earlier.
//!
//! \return Returns the value of the current count of the counter.
//
//*****************************************************************************
static inline uint32_t
ERAD_getCurrentCount(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Return the current count
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))));
}

//*****************************************************************************
//
//! Sets the current count of a counter.
//!
//! \param base is the base of the counter.
//! \param value is the value to be written as the current count.
//!
//! This function sets the current count of the counter which was
//! configured earlier. This can be used to reset the counter or start at
//! a value other than 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setCurrentCount(uint32_t base, uint32_t value)
{
    //
    // Check if owner is APPLICATION or NO_OWNER
    //
    ;

    //
    // Check if the base is valid
    //
    ;

    //
    // Write the value into CTM_COUNT register
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x4U)))) = value;
    __edis();
}

//*****************************************************************************
//
//! Gets the maximum count of a counter.
//!
//! \param base is the base of the counter.
//!
//! This function returns the current maximum count of the counter which was
//! configured earlier.
//!
//! \return Returns the value of the current maximum count of the counter.
//
//*****************************************************************************
static inline uint32_t
ERAD_getMaxCount(uint32_t base)
{
    //
    // Check if the base is valid
    //
    ;

    //
    // Return the maximum value
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x6U)))));
}

//*****************************************************************************
//
//! Sets the maximum count of a counter.
//!
//! \param base is the base of the counter.
//! \param value is the value to be written as the maximum count.
//!
//! This function sets the current maximum count of the counter which was
//! configured earlier.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setMaxCount(uint32_t base, uint32_t value)
{
    //
    // Check if owner is APPLICATION or NO_OWNER
    //
    ;

    //
    // Check if the base is valid
    //
    ;

    //
    // Write the value into the CTM_MAX_COUNT register
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x6U)))) = value;
    __edis();
}

//*****************************************************************************
//
//! Sets conditioning on the inputs to the counter.
//!
//! \param base is the base value of the counter to be configured
//! \param input_type defines which input needs to be conditioned
//! \param options is the kind of conditioning that needs to applied. This will
//! be an OR'd value of \b ERAD_INVERT_ENABLE, \b ERAD_INVERT_DISABLE,
//! \b ERAD_SYNC_ENABLE or \b ERAD_SYNC_DISABLE.
//!
//! This function conditions the inputs to the counter specified. This includes
//! inverting the input and enabling a 2-stage synchronizer for any 4 of the
//! inputs: \e reset, \e stop, \e start, \e count_input.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setCounterInputConditioning(uint32_t base,
                                 ERAD_Counter_Input_Type input_type,
                                 uint16_t options)
{
    //
    // Write into the Input Conditioning register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) =
                            ((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &
                            ~(0x03u << input_type)) | (options << input_type);
    __edis();
}

//*****************************************************************************
//
//! Initialises the CRC unit.
//!
//! \param instances is the OR'd value of CRC instances. Following macros can
//!  be used:
//!  - \b ERAD_INST_CRC1
//!  - \b ERAD_INST_CRC2
//!  - \b ERAD_INST_CRC3
//!  - \b ERAD_INST_CRC4
//!  - \b ERAD_INST_CRC5
//!  - \b ERAD_INST_CRC6
//!  - \b ERAD_INST_CRC7
//!  - \b ERAD_INST_CRC8
//!
//! This function initialises the specified CRC units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_initCRC(uint16_t instances)
{
    //
    // Write into the CRC GLOBAL CTRL register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005EA00U + 0x0U)))) |= instances;
    __edis();
}

//*****************************************************************************
//
//! Enables the CRC unit.
//!
//! \param instances is the OR'd value of CRC instances. Following macros can
//!  be used:
//!  - \b ERAD_INST_CRC1
//!  - \b ERAD_INST_CRC2
//!  - \b ERAD_INST_CRC3
//!  - \b ERAD_INST_CRC4
//!  - \b ERAD_INST_CRC5
//!  - \b ERAD_INST_CRC6
//!  - \b ERAD_INST_CRC7
//!  - \b ERAD_INST_CRC8
//!
//! This function enables the specified CRC units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableCRC(uint16_t instances)
{
    //
    // Write into the CRC GLOBAL CTRL register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005EA00U + 0x0U)))) |= instances << 8;
    __edis();
}

//*****************************************************************************
//
//! Disables the CRC unit.
//!
//! \param instances is the OR'd value of CRC instances. Following macros can
//!  be used:
//!  - \b ERAD_INST_CRC1
//!  - \b ERAD_INST_CRC2
//!  - \b ERAD_INST_CRC3
//!  - \b ERAD_INST_CRC4
//!  - \b ERAD_INST_CRC5
//!  - \b ERAD_INST_CRC6
//!  - \b ERAD_INST_CRC7
//!  - \b ERAD_INST_CRC8
//!
//! This function disables the specified CRC units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableCRC(uint16_t instances)
{
    //
    // Write into the CRC GLOBAL CTRL register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(0x0005EA00U + 0x0U)))) &= ~(instances << 8);
    __edis();
}

//*****************************************************************************
//
//! Gets the current value of the CRC unit.
//!
//! \param base is the base value of CRC unit
//!
//! This function returns the current value of te specified CRC unit.
//!
//! \return Current CRC value.
//
//*****************************************************************************
static inline uint32_t
ERAD_getCurrentCRC(uint32_t base)
{
    //
    // Check if base is valid
    //
    ;

    //
    // Read from the current value register of the specified CRC unit
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))));
}

//*****************************************************************************
//
//! Sets the seed value of the CRC unit
//!
//! \param base is the base value of the CRC unit
//! \param seed is the value of seed to be set
//!
//! This function sets a seed value of the CRC unit.
//! Note: The corresponding CRC unit must be disabled before setting the seed
//! value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setSeed(uint32_t base, uint32_t seed)
{
    //
    // Check if base is valid
    //
    ;

    //
    // Check if the unit is disabled
    //
    ;

    //
    // Write into the CRC SEED register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) = seed;
    __edis();
}

//*****************************************************************************
//
//! Sets the qualifier event of the CRC unit
//!
//! \param base is the base value of the CRC unit
//! \param qualifier is the type of qualifier to be set
//!
//! This function sets a qualifier to decide which events require a CRC
//! computation.
//! Note: The corresponding CRC unit must be disabled before setting the
//! qualifier.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setCRCQualifier(uint32_t base, ERAD_CRC_Qualifiers qualifier)
{
    //
    // Check if base is valid
    //
    ;

    //
    // Check if the unit is disabled
    //
    ;

    //
    // Write into the CRC Qualifier register
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = qualifier;
    __edis();
}

//*****************************************************************************
//
//! Configures the ERAD to profile a certain piece of code
//!
//! \param config_params are the parameters that will be used to configure ERAD
//!
//! This function configures 2 bus comparators and 1 counter to profile a
//! certain piece of code. The base address of the bus comparators and the
//! counter to be used are specified in \e config_params.
//! Note: Use \b ERAD_getMaxCount to get the latest profiled value. The
//! maximum count of the counter being used must be reset to 0x0 to get the
//! correct value everytime.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_profile(ERAD_Profile_Params config_params);

//*****************************************************************************
//
//! Enables an RTOS interrupt at a specified address.
//!
//! \param config_params contrains the bus to be monitored and the address
//! \param busComp_base is the base of the bus compoarator to be used
//!
//! This function enables an RTOS interrupt to be generated when an address
//! in memory or instruction is hit.
//!
//! If the selected bus is \b ERAD_BUSCOMP_BUS_PAB, then the ERAD will be
//! configured to trigger an interrupt when there is instruction fetch happening
//! at the specified address. Similary, if \b ERAD_BUSCOMP_BUS_DWAB is selected,
//! the ERAD will be configured to trigger an interrupt when there write
//! access to the specified address, and so on.
//!
//! Use \e
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_enableInterruptOnAddressHit(ERAD_AddressHit_Params config_params,
                                 uint32_t busComp_base);

//*****************************************************************************
//
//! Configures the ERAD to count the number of times a the specified address
//! is hit
//!
//! \param config_params are the parameters that will be used to configure ERAD
//! \param busComp_base is the base of the bus compoarator to be used
//! \param counter_base is the base of the counter to be used
//!
//! This function configures 1 bus comparator and 1 counter to count how many
//! times a the specified address is hit.
//!
//! If the selected bus is \b ERAD_BUSCOMP_BUS_PAB, then the ERAD will be
//! configured to count the number of times an instruction fetch happens
//! at the specified address. Similary, if \b ERAD_BUSCOMP_BUS_DWAB is selected,
//! the ERAD will be configured to count the number of times there is a write
//! access to the specified address, and so on.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_countAddressHits(ERAD_AddressHit_Params config_params,
                      uint32_t busComp_base, uint32_t counter_base);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   flash.h
//
// TITLE:  C28x Flash driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup flash_api Flash
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_flash.h
//
// TITLE:   Definitions for the FLASH registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the FLASH register offsets
//
//*************************************************************************************************



//*************************************************************************************************
//
// The following are defines for the bit fields in the FRDCNTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FBAC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FBFALLBACK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FBPRDY register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FPAC1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FPAC2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FMSTAT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FRD_INTF_CTRL register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the ECC_ENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_STATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_POS register
//
//*************************************************************************************************
                                                 // bits
                                                 // bits

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_STATUS_CLR register
//
//*************************************************************************************************
                                                        // Value 0 Clear
                                                        // Value 1 Clear
                                                        // occurred Clear
                                                        // Value 0 Clear
                                                        // Value 1 Clear
                                                        // occurred Clear

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_CNT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_THRESHOLD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_INTFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_INTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FADDR_TEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_TEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_STATUS register
//
//*************************************************************************************************




#pragma CODE_SECTION(Flash_setBankPowerMode, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_setPumpPowerMode, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_disableCache, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_disablePrefetch, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_setWaitstates, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_enableCache, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_enablePrefetch, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_enableECC, ".TI.ramfunc");

//*****************************************************************************
//
//! Values that can be passed to Flash_setBankPowerMode() as the bank parameter
//
//*****************************************************************************
typedef enum
{
    FLASH_BANK0 = 0x0, //!< Bank 0
    FLASH_BANK1 = 0x1, //!< Bank 1
    FLASH_BANK2 = 0x2  //!< Bank 2
} Flash_BankNumber;

//*****************************************************************************
//
//! Values that can be passed to Flash_setBankPowerMode() as the powerMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    FLASH_BANK_PWR_SLEEP    = 0x0, //!< Sleep fallback mode
    FLASH_BANK_PWR_STANDBY  = 0x1, //!< Standby fallback mode
    FLASH_BANK_PWR_ACTIVE   = 0x3  //!< Active fallback mode
} Flash_BankPowerMode;

//*****************************************************************************
//
//! Values that can be passed to Flash_setPumpPowerMode() as the powerMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    FLASH_PUMP_PWR_SLEEP    = 0x0, //!< Sleep fallback mode
    FLASH_PUMP_PWR_ACTIVE   = 0x1  //!< Active fallback mode
} Flash_PumpPowerMode;

//*****************************************************************************
//
//! Type that correspond to values returned from Flash_getLowErrorStatus() and
//! Flash_getHighErrorStatus() determining the error status code.
//
//*****************************************************************************
typedef enum
{
    FLASH_NO_ERR       = 0x0, //!< No error
    FLASH_FAIL_0       = 0x1, //!< Fail on 0
    FLASH_FAIL_1       = 0x2, //!< Fail on 1
    FLASH_UNC_ERR      = 0x4  //!< Uncorrectable error
} Flash_ErrorStatus;

//*****************************************************************************
//
//! Values that can be returned from Flash_getLowErrorType() and
//! Flash_getHighErrorType() determining the error type.
//
//*****************************************************************************
typedef enum
{
    FLASH_DATA_ERR      = 0x0, //!< Data error
    FLASH_ECC_ERR       = 0x1  //!< ECC error
} Flash_ErrorType;

//*****************************************************************************
//
//! Values that can be returned from Flash_getECCTestSingleBitErrorType().
//
//*****************************************************************************
typedef enum
{
    FLASH_DATA_BITS          = 0x0, //!< Data bits
    FLASH_CHECK_BITS         = 0x1  //!< ECC bits
} Flash_SingleBitErrorIndicator;

//*****************************************************************************
//
// Values that can be passed to Flash_clearLowErrorStatus and
// Flash_clearHighErrorStatus.
//
//*****************************************************************************

//*****************************************************************************
//
// Values that can be returned from Flash_getInterruptFlag and
// Flash_getECCTestStatus.
//
//*****************************************************************************

//*****************************************************************************
//
// Delay instruction that allows for register configuration to complete.
//
//*****************************************************************************

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a flash wrapper base address for the control registers.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! This function determines if a flash wrapper control base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! \internal
//! Checks a flash wrapper base address for the ECC registers.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function determines if a flash wrapper ECC base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets the random read wait state amount.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param waitstates is the wait-state value.
//!
//! This function sets the number of wait states for a flash read access. The
//! \e waitstates parameter is a number between 0 and 15. It is \b important
//! to look at your device's datasheet for information about what the required
//! minimum flash wait-state is for your selected SYSCLK frequency.
//!
//! By default the wait state amount is configured to the maximum 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setWaitstates(uint32_t ctrlBase, uint16_t waitstates)
{
    //
    // Check the arguments.
    //
    ;

    //
    // waitstates is 4 bits wide.
    //
    ;

    __eallow();
    //
    // Write flash read wait-state amount to appropriate register.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x0U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x0U)))) &
         ~(uint32_t)0xF00U) |
         ((uint32_t)waitstates << 8U);
    __edis();
}

//*****************************************************************************
//
//! Sets the fallback power mode of a flash bank.
//!
//! \param ctrlBase is the base address of the flash wrapper registers.
//! \param bank is the flash bank that is being configured.
//! \param powerMode is the power mode to be entered.
//!
//! This function sets the fallback power mode of the flash bank specified by
//! them \e bank parameter. The power mode is specified by the \e powerMode
//! parameter with one of the following values:
//!
//! - \b FLASH_BANK_PWR_SLEEP - Sense amplifiers and sense reference disabled.
//! - \b FLASH_BANK_PWR_STANDBY - Sense amplifiers disabled but sense reference
//!   enabled.
//! - \b FLASH_BANK_PWR_ACTIVE - Sense amplifiers and sense reference enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setBankPowerMode(uint32_t ctrlBase, Flash_BankNumber bank,
                       Flash_BankPowerMode powerMode)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Write the power mode to the appropriate register.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x20U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x20U)))) &
         ~((0x3U) << ((uint32_t)bank * 2U))) |
        ((uint32_t)powerMode << ((uint32_t)bank * 2U));
    __edis();
}

//*****************************************************************************
//
//! Sets the fallback power mode of the charge pump.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param powerMode is the power mode to be entered.
//!
//! This function sets the fallback power mode flash charge pump.
//!
//! - \b FLASH_PUMP_PWR_SLEEP - All circuits disabled.
//! - \b FLASH_PUMP_PWR_ACTIVE - All pump circuits active.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setPumpPowerMode(uint32_t ctrlBase, Flash_PumpPowerMode powerMode)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Write the power mode to the appropriate register.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x24U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x24U)))) &
        ~(uint32_t)0x1U) | (uint32_t)powerMode;
    __edis();
}

//*****************************************************************************
//
//! Enables prefetch mechanism.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enablePrefetch(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set the prefetch enable bit.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x180U)))) |=
            0x1U;
    __edis();
}

//*****************************************************************************
//
//! Disables prefetch mechanism.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disablePrefetch(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Clear the prefetch enable bit.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x180U)))) &=
            ~(uint32_t)0x1U;
    __edis();
}

//*****************************************************************************
//
//! Enables data cache.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enableCache(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set the data cache enable bit.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x180U)))) |=
            0x2U;
    __edis();
}

//*****************************************************************************
//
//! Disables data cache.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disableCache(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Clear the data cache enable bit.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x180U)))) &=
            ~(uint32_t)0x2U;
    __edis();
}

//*****************************************************************************
//
//! Enables flash error correction code (ECC) protection.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enableECC(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Write the key value 0xA to ECC_ENABLE register.
    //
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x0U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x0U)))) &
         ~(uint32_t)0xFU) | 0xAU;
    __edis();
}

//*****************************************************************************
//
//! Disables flash error correction code (ECC) protection.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disableECC(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Clear ECC enable field with the one's complement of the key.
    //
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x0U)))) =
        ((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x0U)))) &
         ~(uint32_t)0xFU) | 0x5U;
    __edis();
}



//*****************************************************************************
//
//! Sets the bank active grace period.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param period is the starting count value for the BAGP down counter.
//!
//! This function sets the bank active grace period specified by the
//! \e period parameter. The \e period is a value between 0 and 255. This
//! value must be greater than 1 when the fallback mode is not Active.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setBankActiveGracePeriod(uint32_t ctrlBase, uint32_t period)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();

    //
    // Write period to the BAGP of the FBAC register.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x1EU)))) =
          ((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x1EU)))) &
             ~(uint32_t)0xFF00U) | (period << 8U);
    __edis();
}

//*****************************************************************************
//
//! Sets the pump active grace period.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param period is the starting count value for the PAGP down counter.
//!
//! This function sets the pump active grace period specified by the
//! \e period parameter. The \e period is a value between 0 and 65535.  The
//! counter is reloaded after any flash access. After the counter expires, the
//! charge pump falls back to the power mode determined by FPAC1, bit PMPPWR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setPumpActiveGracePeriod(uint32_t ctrlBase, uint16_t period)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Write period to the PAGP of the FPAC2 register.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x26U)))) =
          ((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x26U)))) &
          ~(uint32_t)0xFFFFU) |
          ((uint32_t)period << 0U);
    __edis();
}

//*****************************************************************************
//
//! Sets the pump wake up time.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param sysclkCycles is the number of SYSCLK cycles it takes for the pump
//! to wakeup.
//!
//! This function sets the wakeup time with \e sysclkCycles parameter.
//! The \e sysclkCycles is a value between 0 and 8190. When the charge pump
//! exits sleep power mode, it will take sysclkCycles to wakeup.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setPumpWakeupTime(uint32_t ctrlBase, uint16_t sysclkCycles)
{
    //
    // Check the arguments.
    //
    ;

    //
    // PSLEEP = sysclkCycles/2. PSLEEP maximum value is 4095(12 bits wide)
    //
    ;

    __eallow();

    //
    // Write sysclkCycles/2 to PSLEEP of the FPAC1 register.
    //
    (*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x24U)))) =
          ((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x24U)))) &
          ~(uint32_t)0xFFF0000U) |
          (((uint32_t)sysclkCycles / (uint32_t)2) <<
          (uint32_t)16U);
    __edis();
}

//*****************************************************************************
//
//! Reads the bank active power state.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param bank is the flash bank that is being used.
//!
//! \return Returns \b true if the Bank is in Active power state and \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
Flash_isBankReady(uint32_t ctrlBase, Flash_BankNumber bank)
{
    //
    // Check the arguments.
    //
    ;

    _Bool ready;
    uint32_t bitMask = (uint32_t)0x1U << (uint32_t)bank;
    //
    // Return the BANKXRDY bit in FBPRDY.
    //
    if(((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x22U)))) & bitMask) == bitMask)
    {
        ready = 1;
    }
    else
    {
        ready = 0;
    }
    return(ready);
}

//*****************************************************************************
//
//! Reads the pump active power state.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return Returns \b true if the Pump is in Active power state and \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
Flash_isPumpReady(uint32_t ctrlBase)
{
    //
    // Check the arguments.
    //
    ;

    _Bool ready;

    //
    // Return the PUMPRDY bit in FBPRDY.
    //
    if(((*((volatile uint32_t *)((uintptr_t)(ctrlBase + 0x22U)))) &
        (uint32_t)0x8000U) == 0x8000U)
    {
        ready = 1;
    }
    else
    {
        ready = 0;
    }
    return(ready);
}


//*****************************************************************************
//
//! Gets the single error address low.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the 32-bit address of the single bit error that
//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where a single bit
//! error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getSingleBitErrorAddressLow(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x2U)))));
}

//*****************************************************************************
//
//! Gets the single error address high.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the 32-bit address of the single bit error that
//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where a single bit
//! error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getSingleBitErrorAddressHigh(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x4U)))));
}

//*****************************************************************************
//
//! Gets the uncorrectable error address low.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the 32-bit address of the uncorrectable error that
//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where an
//! uncorrectable error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getUncorrectableErrorAddressLow(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x6U)))));
}

//*****************************************************************************
//
//! Gets the uncorrectable error address high.
//!
//! \param eccBase is the base address of the flash wrapper ECC base.
//!
//! This function returns the 32-bit address of the uncorrectable error that
//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where an
//! uncorrectable error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getUncorrectableErrorAddressHigh(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x8U)))));
}

//*****************************************************************************
//
//! Gets the error status of the Lower 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error status of the lower 64-bits of a 128-bit
//! aligned address.
//!
//! \return Returns value of the low error status bits which can be used with
//! Flash_ErrorStatus type.
//
//*****************************************************************************
static inline Flash_ErrorStatus
Flash_getLowErrorStatus(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the Low Error Status bits
    //
    return((Flash_ErrorStatus)((*((volatile uint32_t *)((uintptr_t)(eccBase + 0xAU)))) &
            (uint32_t)0x7U));
}

//*****************************************************************************
//
//! Gets the error status of the Upper 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error status of the upper 64-bits of a 128-bit
//! aligned address.
//!
//! \return Returns value of the high error status bits which can be used with
//! Flash_ErrorStatus type.
//
//*****************************************************************************
static inline Flash_ErrorStatus
Flash_getHighErrorStatus(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the High Error Status bits
    //
    return((Flash_ErrorStatus)(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0xAU)))) >>
            16U) & (uint32_t)0x7U));
}

//*****************************************************************************
//
//! Gets the error position of the lower 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error position of the lower 64-bits. If the
//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges
//! from 0-63 for FLASH_DATA_ERR.
//!
//! \return Returns the position of the lower error bit.
//
//*****************************************************************************
static inline uint32_t
Flash_getLowErrorPosition(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) &
            (uint32_t)0x3FU) >>
            0U);
}

//*****************************************************************************
//
//! Gets the error position of the upper 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error position of the upper 64-bits. If the
//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges
//! from 0-63 for FLASH_DATA_ERR.
//!
//! \return Returns the position of the upper error bit.
//
//*****************************************************************************
static inline uint32_t
Flash_getHighErrorPosition(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) &
            (uint32_t)0x3F0000U) >>
            16U);
}

//*****************************************************************************
//
//! Clears the error position bit of the lower 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error position bit of the lower 64-bits.
//!
//! \return None
//
//*****************************************************************************
static inline void
Flash_clearLowErrorPosition(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) &= ~(uint32_t)0x3FU;
    __edis();
}

//*****************************************************************************
//
//! Clears the error position of the upper 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error position bit of the upper 64-bits.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearHighErrorPosition(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) &= ~(uint32_t)0x3F0000U;
    __edis();
}

//*****************************************************************************
//
//! Gets the error type of the lower 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error type of the lower 64-bits. The error type
//! can be FLASH_ECC_ERR or FLASH_DATA_ERR.
//!
//! \return Returns the type of the lower 64-bit error.
//
//*****************************************************************************
static inline Flash_ErrorType
Flash_getLowErrorType(uint32_t eccBase)
{
    Flash_ErrorType errorType;
    //
    // Check the arguments.
    //
    ;

    //
    // Check which error type.
    // If bit is 1 then ECC error, else it is a Data error.
    //
    if(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) & 0x100U)
                                == 0x100U)
        errorType =  FLASH_ECC_ERR;
    else
        errorType =  FLASH_DATA_ERR;

    return(errorType);
}

//*****************************************************************************
//
//! Gets the error type of the upper 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error type of the upper 64-bits. The error type
//! can be FLASH_ECC_ERR or FLASH_DATA_ERR.
//!
//! \return Returns the type of the upper 64-bit error.
//
//*****************************************************************************
static inline Flash_ErrorType
Flash_getHighErrorType(uint32_t eccBase)
{
    Flash_ErrorType errorType;
    //
    // Check the arguments.
    //
    ;

    //
    // Check which error type.
    // If bit is 1 then ECC error, else it is a Data error.
    //
    if(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) & 0x1000000U)
                                == 0x1000000U)
        errorType =  FLASH_ECC_ERR;
    else
        errorType =  FLASH_DATA_ERR;

    return(errorType);
}
//*****************************************************************************
//
//! Clears the error type bit of the lower 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error type bit of the lower 64-bits.
//!
//! \return None
//
//*****************************************************************************
static inline void
Flash_clearLowErrorType(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) &= ~(uint32_t)0x100U;
    __edis();
}

//*****************************************************************************
//
//! Clears the error type of the upper 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error type bit of the upper 64-bits.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearHighErrorType(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0xCU)))) &= ~(uint32_t)0x1000000U;
    __edis();
}
//*****************************************************************************
//
//! Clears the errors status of the lower 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param errorStatus is the error status to clear. errorStatus is a uint16_t.
//! errorStatus is a bitwise OR of the following value:
//!
//! - \b FLASH_FAIL_0_CLR
//! - \b FLASH_FAIL_1_CLR
//! - \b FLASH_UNC_ERR_CLR
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearLowErrorStatus(uint32_t eccBase, uint16_t errorStatus)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0xEU)))) |= ((uint32_t)errorStatus);
    __edis();
}

//*****************************************************************************
//
//! Clears the errors status of the upper 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param errorStatus is the error status to clear. errorStatus is a uint16_t.
//! errorStatus is a bitwise OR of the following value:
//!
//! - \b FLASH_FAIL_0_CLR
//! - \b FLASH_FAIL_1_CLR
//! - \b FLASH_UNC_ERR_CLR
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearHighErrorStatus(uint32_t eccBase, uint16_t errorStatus)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0xEU)))) |= ((uint32_t)errorStatus << 16U);
    __edis();
}

//*****************************************************************************
//
//! Gets the single bit error count.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the single bit error count.
//
//*****************************************************************************
static inline uint32_t
Flash_getErrorCount(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x10U)))) &
            (uint32_t)0xFFFFU);
}

//*****************************************************************************
//
//! Sets the single bit error threshold.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param threshold is the single bit error threshold. Valid ranges are from
//! 0-65535.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setErrorThreshold(uint32_t eccBase, uint16_t threshold)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x12U)))) = ((uint32_t)threshold &
        (uint32_t)0xFFFFU);
    __edis();
}

//*****************************************************************************
//
//! Gets the error interrupt.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the type of error interrupt that occurred.  The
//! values can be used with
//! - \b FLASH_NO_ERROR
//! - \b FLASH_SINGLE_ERROR
//! - \b FLASH_UNC_ERROR
//!
//! \return Returns the interrupt flag.
//
//*****************************************************************************
static inline uint32_t
Flash_getInterruptFlag(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read which type of error occurred.
    //
    return(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x14U)))) & (uint32_t)0x3U));
}

//*****************************************************************************
//
//! Clears the single error interrupt flag.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearSingleErrorInterruptFlag(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x16U)))) |=
        0x1U;
    __edis();
}

//*****************************************************************************
//
//! Clears the uncorrectable error interrupt flag.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearUncorrectableInterruptFlag(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x16U)))) |=
        0x2U;
    __edis();
}

//*****************************************************************************
//
//! Sets the Data Low Test register for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param data is a 32-bit value that is the low double word of selected
//! 64-bit data
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setDataLowECCTest(uint32_t eccBase, uint32_t data)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x1AU)))) = data;
    __edis();
}

//*****************************************************************************
//
//! Sets the Data High Test register for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param data is a 32-bit value that is the high double word of selected
//! 64-bit data
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setDataHighECCTest(uint32_t eccBase, uint32_t data)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x18U)))) = data;
    __edis();
}

//*****************************************************************************
//
//! Sets the test address register for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param address is a 32-bit value containing an address. Bits 21-3 will be
//! used as the flash word (128-bit) address.
//!
//! This function left shifts the address 1 bit to convert it to a byte address
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setECCTestAddress(uint32_t eccBase, uint32_t address)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Left shift the address 1 bit to make it byte-addressable
    //
    uint32_t byteAddress = address << 1;

    __eallow();

    //
    // Write bits 21-3 to the register.
    //
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x1CU)))) = byteAddress;

    __edis();

}

//*****************************************************************************
//
//! Sets the ECC test bits for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param ecc is a 32-bit value. The least significant 8 bits are used as
//! the ECC Control Bits in the ECC Test.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setECCTestECCBits(uint32_t eccBase, uint16_t ecc)
{
    //
    // Check the arguments.
    //
    ;

    ;
    __eallow();

    //
    // Write the 8 ECC Control Bits.
    //
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x1EU)))) =
        ((uint32_t)ecc & (uint32_t)0xFFU);
    __edis();
}

//*****************************************************************************
//
//! Enables ECC Test mode.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enableECCTestMode(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x20U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Disables ECC Test mode.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disableECCTestMode(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x20U)))) &=
        ~(uint32_t)0x1U;
    __edis();
}

//*****************************************************************************
//
//! Selects the ECC block on bits [63:0] of bank data.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_selectLowECCBlock(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x20U)))) &=
        ~(uint32_t)0x2U;
    __edis();
}

//*****************************************************************************
//
//! Selects the ECC block on bits [127:64] of bank data.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_selectHighECCBlock(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x20U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Performs the ECC calculation on the test block.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_performECCCalculation(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(eccBase + 0x20U)))) |= 0x4U;
    __edis();
}

//*****************************************************************************
//
//! Gets the ECC Test data out high 63:32 bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the ECC TEst data out High.
//
//*****************************************************************************
static inline uint32_t
Flash_getTestDataOutHigh(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x22U)))));
}

//*****************************************************************************
//
//! Gets the ECC Test data out low 31:0 bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the ECC Test data out Low.
//
//*****************************************************************************
static inline uint32_t
Flash_getTestDataOutLow(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x24U)))));
}

//*****************************************************************************
//
//! Gets the ECC Test status.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the ECC test status. The values can be used with
//! - \b FLASH_NO_ERROR
//! - \b FLASH_SINGLE_ERROR
//! - \b FLASH_UNC_ERROR
//!
//! \return Returns the ECC test status.
//
//*****************************************************************************
static inline uint32_t
Flash_getECCTestStatus(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read which type of error occurred.
    //
    return(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x26U))))) & (uint32_t)0x3U);
}

//*****************************************************************************
//
//! Gets the ECC Test single bit error position.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the ECC Test single bit error position. If the error type
//! is check bits than the position can range from 0 to 7. If the error type
//! is data bits than the position can range from 0 to 63.
//
//*****************************************************************************
static inline uint32_t
Flash_getECCTestErrorPosition(uint32_t eccBase)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the position bits and shift it to the right.
    //
    return(((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x26U)))) &
        (uint32_t)0xFCU) >>
        2U);
}

//*****************************************************************************
//
//! Gets the single bit error type.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the single bit error type as a
//!  Flash_SingleBitErrorIndicator. FLASH_DATA_BITS and FLASH_CHECK_BITS
//! indicate where the single bit error occurred.
//
//*****************************************************************************
static inline Flash_SingleBitErrorIndicator
Flash_getECCTestSingleBitErrorType(uint32_t eccBase)
{
    uint32_t errorType;
    //
    // Check the arguments.
    //
    ;

    //
    // Read the ERR_TYPE bit to see where the single bit error was.
    //
    errorType = (((*((volatile uint32_t *)((uintptr_t)(eccBase + 0x26U)))) &
                (uint32_t)0x100U) >> 8U);
    return((Flash_SingleBitErrorIndicator)errorType);
}

//*****************************************************************************
//
//! Initializes the flash control registers.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param waitstates is the wait-state value.
//!
//! This function initializes the flash control registers. At reset bank and
//! pump are in sleep.  A flash access will power up the bank and pump
//! automatically. This function will power up Flash bank and pump and set the
//! fallback mode of flash and pump as active.
//!
//! This function also sets the number of wait-states for a flash access
//! (see Flash_setWaitstates() for more details), and enables cache, the
//! prefetch mechanism, and ECC.
//!
//! \return None.
//
//*****************************************************************************
extern void
Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates);

//*****************************************************************************
//
//! Powers down the flash.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! This function powers down the flash bank(s) and the flash pump.
//!
//! \return None.
//
//*****************************************************************************
extern void
Flash_powerDown(uint32_t ctrlBase);

//*****************************************************************************
//
//! Wakes the flash from low power mode.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! This function will power up Flash bank and pump and set the
//! fallback mode of flash and pump as active.
//!
//! \return None.
//
//*****************************************************************************
extern void
Flash_wakeFromLPM(uint32_t ctrlBase);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   fsi.h
//
// TITLE:  C28x FSI Driver API header file
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup fsi_api FSI
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_fsi.h
//
// TITLE:   Definitions for the FSI registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the FSI register offsets
//
//*************************************************************************************************
                                                   // register
                                                   // buffer

                                                   // RX_INT1
                                                   // RX_INT2
                                                   // buffer


//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_MASTER_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_CLK_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_OPER_CTRL_LO register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_OPER_CTRL_HI register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_FRAME_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_FRAME_TAG_UDATA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_BUF_PTR_LOAD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_BUF_PTR_STS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_PING_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_PING_TAG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_INT_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_DMA_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_LOCK_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_EVT_STS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_EVT_CLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_EVT_FRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_USER_CRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_ECC_DATA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_ECC_VAL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_DLYLINE_CTRL register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_MASTER_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_OPER_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_INFO register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_TAG_UDATA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_DMA_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_EVT_STS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_CRC_INFO register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_EVT_CLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_EVT_FRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_BUF_PTR_LOAD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_BUF_PTR_STS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_WD_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_PING_WD_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_PING_TAG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_INT1_CTRL register
//
//*************************************************************************************************
                                                             // Interrupt to INT1
                                                             // Interrupt to INT1
                                                             // to INT1
                                                             // to INT1
                                                             // Interrupt to INT1
                                                             // INT1
                                                             // Interrupt to INT1
                                                             // Interrupt to INT1
                                                             // INT1
                                                             // Interrupt to INT1
                                                             // Interrupt to INT1
                                                             // Interrupt to INT1
                                                             // Interrupt to INT1

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_INT2_CTRL register
//
//*************************************************************************************************
                                                             // Interrupt to INT2
                                                             // Interrupt to INT2
                                                             // to INT2
                                                             // to INT2
                                                             // INT2
                                                             // INT2
                                                             // Interrupt to INT2
                                                             // Interrupt to INT2
                                                             // INT2
                                                             // Interrupt to INT2
                                                             // Interrupt to INT2
                                                             // Interrupt to INT2
                                                             // Interrupt to INT2

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_LOCK_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_ECC_DATA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_ECC_VAL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_ECC_LOG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_TAG_CMP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_PING_TAG_CMP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_WIDTH_0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_DLYLINE_CTRL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_VIS_1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_UDATA_FILTER register
//
//*************************************************************************************************




//*****************************************************************************
//
// FSI Tx defines
//
//*****************************************************************************

//*****************************************************************************
//
// FSI Tx events defines
//
// Values that can be passed to APIs to enable/disable interrupts and
// also to set/get/clear event status on FSI Tx operation.
//
// There are 4 supported interrupts related to Tx events-
// All are available as event status as well except 4th one.
//
//*****************************************************************************


//*****************************************************************************
//
//! \brief Flag for event status not available as interrupt
//!
//! Ping frame transmission upon hardware trigger(ping watchdog or
//! external trigger) is shown as event status.
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Mask of all Tx Events, ORing all event defines
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Maximum number of external input for triggering frame-transmission
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Shifts needed to control FSI Tx interrupt generation on INT2
//
//*****************************************************************************

//*****************************************************************************
//
// FSI Rx Defines
//
//*****************************************************************************

//*****************************************************************************
//
// FSI Rx event defines
//
// Values that can be passed to APIs to enable/disable interrupts and
// also to set/get/clear event status on FSI Rx operation.
//
// There are 15 supported interrupts related to Rx events.
// All are available as event status as well.
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Mask of all Rx Events, ORing all event defines
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Maximum value in Rx delay line tap control
//
//*****************************************************************************

//*****************************************************************************
//
// Common defines for both FSI Tx and Rx
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Maximum data length(16 words) for user/software defined data frame
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Maximum value for user data field(8 bits)
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Maximum value of Buffer pointer offset(4 bits)
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Key value for writing some FSI Tx/Rx registers
//
//*****************************************************************************

//*****************************************************************************
//
// typedefs
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Data lines used for transmit/receive operation
//!
//! \details Supported number of data lines is only 2 - 1 lane or 2 lanes
//
//*****************************************************************************
typedef enum
{
    FSI_DATA_WIDTH_1_LANE = 0x0000U,
    FSI_DATA_WIDTH_2_LANE = 0x0001U
} FSI_DataWidth;

//*****************************************************************************
//
//! \brief List of TX submodules that can be reset, can be used with reset APIs
//!
//! \details Three kind of resets can be made-
//!          1) reset entire Tx Module
//!          2) reset only TX clock
//!          3) reset ping timeout counter
//
//*****************************************************************************
typedef enum
{
    FSI_TX_MASTER_CORE_RESET      = 0x0000U,
    FSI_TX_CLOCK_RESET            = 0x0001U,
    FSI_TX_PING_TIMEOUT_CNT_RESET = 0x0002U
} FSI_TxSubmoduleInReset;

//*****************************************************************************
//
//! \brief Start Mode for Tx frame transmission
//!
//! \details Three start modes(that is, how transmission will start) are
//! supported-
//!          1. SW write of START bit in \b TX_PKT_CTRL register
//!          2. Rising edge on external trigger
//!          3. Either SW write of START bit or Frame completion
//
//*****************************************************************************
typedef enum
{
 FSI_TX_START_FRAME_CTRL               = 0x0000U,
 FSI_TX_START_EXT_TRIG                 = 0x0001U,
 FSI_TX_START_FRAME_CTRL_OR_UDATA_TAG  = 0x0002U
} FSI_TxStartMode;

//*****************************************************************************
//
//! \brief Various FSI frame types
//!
//! \details Three frame types exist-
//!          - \b Ping: Used for checking line integrity, can be sent by
//!                     software or automatically by hardware.
//!          - \b Error: Used typically during error conditions or when one
//!                      side wants to signal the other side for attention.
//!          - \b Data: Two subtypes exist based on data-length-
//!                     a) \b Fixed (1/2/4/6 words)
//!                     b) \b Nwords Software programs number of data words
//!
//!  \note 4 bit code for frame types- 0x1, 0x2 and 0x8 to 0xE are reserved
//
//*****************************************************************************
typedef enum
{
    FSI_FRAME_TYPE_PING       = 0x0000U,
    FSI_FRAME_TYPE_ERROR      = 0x000FU,
    FSI_FRAME_TYPE_1WORD_DATA = 0x0004U,
    FSI_FRAME_TYPE_2WORD_DATA = 0x0005U,
    FSI_FRAME_TYPE_4WORD_DATA = 0x0006U,
    FSI_FRAME_TYPE_6WORD_DATA = 0x0007U,
    FSI_FRAME_TYPE_NWORD_DATA = 0x0003U
} FSI_FrameType;

//*****************************************************************************
//
//! \brief Possible values of a FSI frame
//!
//! \details 4 bit field inside FSI frame is available to set tag value(0-15)
//
//*****************************************************************************
typedef enum
{
    FSI_FRAME_TAG0  = 0x0000U,
    FSI_FRAME_TAG1  = 0x0001U,
    FSI_FRAME_TAG2  = 0x0002U,
    FSI_FRAME_TAG3  = 0x0003U,
    FSI_FRAME_TAG4  = 0x0004U,
    FSI_FRAME_TAG5  = 0x0005U,
    FSI_FRAME_TAG6  = 0x0006U,
    FSI_FRAME_TAG7  = 0x0007U,
    FSI_FRAME_TAG8  = 0x0008U,
    FSI_FRAME_TAG9  = 0x0009U,
    FSI_FRAME_TAG10 = 0x000AU,
    FSI_FRAME_TAG11 = 0x000BU,
    FSI_FRAME_TAG12 = 0x000CU,
    FSI_FRAME_TAG13 = 0x000DU,
    FSI_FRAME_TAG14 = 0x000EU,
    FSI_FRAME_TAG15 = 0x000FU
} FSI_FrameTag;

//*****************************************************************************
//
//! \brief Ping timeout mode
//!
//! \details Ping timeout can reset and restart only on hardware initiated PING
//!          frames (PING Watchdog timeout)
//!          OR
//!          on any software initiated frame being sent out also based on
//!          which mode is selected
//
//*****************************************************************************
typedef enum
{
    FSI_PINGTIMEOUT_ON_HWINIT_PING_FRAME   = 0x0000U,
    FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME = 0x0001U
} FSI_PingTimeoutMode;

//! \brief ECC Computation width- 16 bit or 32 bit
//!
typedef enum
{
    FSI_32BIT_ECC_COMPUTE = 0x0000U,
    FSI_16BIT_ECC_COMPUTE = 0x0001U
} FSI_ECCComputeWidth;

//*****************************************************************************
//
//! \brief Interrupt lines supported in FSI
//!
//! \details Any event on FSI Tx or Rx can be enabled to trigger interrupt on 2
//!          interrupt lines to CPU/CLA- \b INT1 and \b INT2
//
//*****************************************************************************
typedef enum
{
    FSI_INT1 = 0x0000U,
    FSI_INT2 = 0x0001U
} FSI_InterruptNum;

//*****************************************************************************
//
//! \brief List of RX modules that can be reset, can be used with reset APIs
//!
//! \details Three submodules can be reset-
//!          1) RX master core
//!          2) frame watchdog counter
//!          3) ping watchdog counter
//
//*****************************************************************************
typedef enum
{
    FSI_RX_MASTER_CORE_RESET  = 0x0000U,
    FSI_RX_FRAME_WD_CNT_RESET = 0x0001U,
    FSI_RX_PING_WD_CNT_RESET  = 0x0002U
} FSI_RxSubmoduleInReset;

//*****************************************************************************
//
//! \brief Available Rx lines for delay tap selection
//!
//! \details Delay tapping can be done on 3 lines- 1)RXCLK 2)RXD0 and 3)RXD1
//
//*****************************************************************************
typedef enum
{
    FSI_RX_DELAY_CLK = 0x0000U,
    FSI_RX_DELAY_D0  = 0x0001U,
    FSI_RX_DELAY_D1  = 0x0002U
} FSI_RxDelayTapType;

//*****************************************************************************
//
//! \brief Indexes of available EPWM SOC triggers
//!
//
//*****************************************************************************
typedef enum
{
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP4   = 0U,
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP5   = 1U,
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP7   = 2U,
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP8   = 3U,
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP9   = 4U,
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP10  = 5U,
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP11  = 6U,
    FSI_EXT_TRIGSRC_EPWM_XBARTRIP12  = 7U,
    FSI_EXT_TRIGSRC_EPWM1_SOCA       = 8U,
    FSI_EXT_TRIGSRC_EPWM1_SOCB       = 9U,
    FSI_EXT_TRIGSRC_EPWM2_SOCA       = 10U,
    FSI_EXT_TRIGSRC_EPWM2_SOCB       = 11U,
    FSI_EXT_TRIGSRC_EPWM3_SOCA       = 12U,
    FSI_EXT_TRIGSRC_EPWM3_SOCB       = 13U,
    FSI_EXT_TRIGSRC_EPWM4_SOCA       = 14U,
    FSI_EXT_TRIGSRC_EPWM4_SOCB       = 15U,
    FSI_EXT_TRIGSRC_EPWM5_SOCA       = 16U,
    FSI_EXT_TRIGSRC_EPWM5_SOCB       = 17U,
    FSI_EXT_TRIGSRC_EPWM6_SOCA       = 18U,
    FSI_EXT_TRIGSRC_EPWM6_SOCB       = 19U,
    FSI_EXT_TRIGSRC_EPWM7_SOCA       = 20U,
    FSI_EXT_TRIGSRC_EPWM7_SOCB       = 21U,
    FSI_EXT_TRIGSRC_EPWM8_SOCA       = 22U,
    FSI_EXT_TRIGSRC_EPWM8_SOCB       = 23U,
    FSI_EXT_TRIGSRC_CLB1_CLBOUT30    = 40U,
    FSI_EXT_TRIGSRC_CLB1_CLBOUT31    = 41U,
    FSI_EXT_TRIGSRC_CLB2_CLBOUT30    = 42U,
    FSI_EXT_TRIGSRC_CLB2_CLBOUT31    = 43U,
    FSI_EXT_TRIGSRC_ADC_SOCA         = 52U,
    FSI_EXT_TRIGSRC_ADC_SOCB         = 53U,
    FSI_EXT_TRIGSRC_CPU1_TIMER0INT   = 54U,
    FSI_EXT_TRIGSRC_CPU1_TIMER1INT   = 55U,
    FSI_EXT_TRIGSRC_CPU1_TIMER2INT   = 56U
} FSI_ExtFrameTriggerSrc;

//*****************************************************************************
//
// FSI Tx function prototypes/defintion
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Validates if FSI-Tx base address is correct
//!
//! \param[in] base is the base address of the FSI-Tx module
//!
//! \return returns \b true if the base address is valid and \b false otherwise
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Sends FLUSH pattern
//!
//! \details FLUSH pattern (toggle data lines followed by toggle on clocks)
//!          should be sent only when FSI Tx is not under \b SOFT_RESET and the
//!          clock to the transmit core has been turned ON.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_sendTxFlush(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= ((uint16_t)0x2U |
                                           ((0x00A5U) <<
                                           8U));
    __edis();
}

//*****************************************************************************
//
//! \brief Stops FLUSH pattern transmission
//!
//! \details Transmission of FLUSH pattern should be stopped before starting
//!          sending frames. Generally during initilization a pair of send/stop
//!          APIs for FLUSH pattern is called to clear data/clock lines.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_stopTxFlush(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = (((~0x2U) &
                                          (*((volatile uint16_t *)((uintptr_t)(base + 0x0U))))) |
                                          ((0x00A5U) <<
                                          8U));
    __edis();
}

//*****************************************************************************
//
//! \brief Selects PLL clock as source for clock dividers
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_selectTxPLLClock(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    //
    // Set PLLCLK as source for clock divider
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x100U;

    __edis();
}

//*****************************************************************************
//
//! \brief sets clock division prescalar and enables the transmit clock
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxClock(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Enable Tx clock
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables transmit clock
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxClock(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Disable Tx clock
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) &= ~0x2U;
    __edis();
}

//*****************************************************************************
//
//! \brief Sets the prescalar clock keeping the transmit clock in reset
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] preScaleValue used to generate transmit clock, it defines the
//!            division value of /2,/3,/4,etc. of \b PLLCLK. Prescale value is
//!            is to be set while keeping the clock in reset.

//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_configPrescalar(uint32_t base, uint16_t preScaleValue)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();

    //
    // Disable Tx clock
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) &= ~0x2U;

    //
    // Set prescalar value
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) &
                                       (~0x3FCU)) |
                                       (preScaleValue <<
                                       2U);
    __edis();
}

//*****************************************************************************
//
//! \brief Sets Data width for transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] dataWidth selection between 1 or 2 lane transmission
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxDataWidth(uint32_t base, FSI_DataWidth dataWidth)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) =
                                ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                                 (~0x3U)) |
                                (uint16_t)dataWidth;
    __edis();
}

//*****************************************************************************
//
//! \brief Enables SPI compatible mode
//!
//! \details FSI supports a \b compatibility mode in order to communicate with
//!          \b legacy peripherals like \b SPI. Only the 16-bit mode of SPI will
//!          be supported. All the frame structures, CRC checks and will be
//!          identical to the normal FSI frames.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxSPIMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x4U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables SPI compatible mode
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxSPIMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x4U;
    __edis();
}

//*****************************************************************************
//
//! \brief Sets start mode for any frame transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] txStartMode is one of supported 3 start modes in transmission
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxStartMode(uint32_t base, FSI_TxStartMode txStartMode)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) =
                    ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                     (~0x38U)) |
                    ((uint16_t)txStartMode << 3U);
    __edis();
}

//*****************************************************************************
//
//! \brief Setting for when Ping timeout can reset and restart
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] pingTimeoutMode can be HW or both HW/SW initiated
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxPingTimeoutMode(uint32_t base, FSI_PingTimeoutMode pingTimeoutMode)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(pingTimeoutMode == FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |=
                                    0x80U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &=
                                    ~0x80U;
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Enables the Tx TDM mode for multi-slave configuration
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxTDMMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Enable Tx TDM Mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x200U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the Tx TDM mode.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxTDMMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x200U;
    __edis();
}
//*****************************************************************************
//
//! \brief Sets a particular external input to trigger transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] extInputNum can be one of ports from 0 to 63. See also
//! FSI_ExtFrameTriggerSrc enum members for valid external triggers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxExtFrameTrigger(uint32_t base, uint16_t extInputNum)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) =
                          ((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) &
                           (~0x1F80U)) |
                          (extInputNum << 7U);
    __edis();
}

//*****************************************************************************
//
//! \brief Enables CRC value of a data frame to be forced to zero
//!
//! \details CRC value of the data frame will be forced to 0 whenever there is
//!          a transmission and buffer over-run or under-run condition happens.
//!          The idea is to force a corruption of the CRC since the data is not
//!          guaranteed to be reliable
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxCRCForceError(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) |= 0x20U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables forcing of CRC value of a data frame to zero
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxCRCForceError(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) &= ~0x20U;
    __edis();
}

//*****************************************************************************
//
//! \brief Select between 16-bit and 32-bit ECC computation
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] eccComputeWidth is ECC Computation width
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxECCComputeWidth(uint32_t base, FSI_ECCComputeWidth eccComputeWidth)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(eccComputeWidth == FSI_16BIT_ECC_COMPUTE)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) |= 0x40U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) &= ~0x40U;
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Sets frame type for transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] frameType value of frame type
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxFrameType(uint32_t base, FSI_FrameType frameType)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) &
                                         (~0xFU)) |
                                         (uint16_t)frameType;
}

//*****************************************************************************
//
//! \brief Sets the frame size if frame type is user/software defined frame
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] nWords  is number of data words in a software defined frame
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxSoftwareFrameSize(uint32_t base, uint16_t nWords)
{
    //
    // Check the arguments.
    //
    ;
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) &
                                         (~0xF0U)) |
                                         ((nWords - 1) <<
                                          4U);
}

//*****************************************************************************
//
//! \brief Starts transmitting frames
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_startTxTransmit(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) |= 0x8000U;
}

//*****************************************************************************
//
//! \brief Sets frame tag for transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] frameTag value of frame tag, 4 bit value (0 to 15)
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxFrameTag(uint32_t base, FSI_FrameTag frameTag)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) =
                            ((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) &
                             (~0xFU)) |
                            (uint16_t)frameTag;
}

//*****************************************************************************
//
//! \brief Sets user defined data for transmission
//!        It is an extra data field(8 bit) apart from regular data
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] userDefData 8 bit user defined data value
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxUserDefinedData(uint32_t base, uint16_t userDefData)
{
    //
    // Check the arguments.
    //
    ;
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) =
                            ((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) &
                             (~0xFF00U)) |
                            (userDefData << 8U);
}

//*****************************************************************************
//
//! \brief Sets the value for transmit buffer pointer at desired location
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] bufPtrOff 4 bit offset pointer in Tx buffer where transmitter
//!            will pick the data
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxBufferPtr(uint32_t base, uint16_t bufPtrOff)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) = bufPtrOff;
    __edis();
}

//*****************************************************************************
//
//! \brief Returns current buffer pointer location
//!
//! \param[in]  base is the FSI Tx module base address
//!
//! \return current buffer pointer location
//!
//! \note   there could be lag due to synchronization hence value is accurate
//!         only when no current transmission is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getTxBufferPtr(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) &
           0xFU);
}

//*****************************************************************************
//
//! \brief Returns valid number of data words present in buffer which have not
//!        been transmitted yet
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return number of data words present in buffer which have not been
//!         transmitted yet
//! \note   there could be lag due to synchronization hence value is accurate
//!         only when no current transmission is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getTxWordCount(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) &
            0x1F00U) >>
            8U);
}

//*****************************************************************************
//
//! \brief Enables ping timer logic and once set time elapses it sends signal
//!        to transmitter to send ping frame
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] refValue 32 bit reference value for ping time-out counter
//! \param[in] pingFrameTag 4 bit tag value for ping time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxPingTimer(uint32_t base, uint32_t refValue,
                FSI_FrameTag pingFrameTag)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) = (uint16_t)pingFrameTag;

    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(base + 0xCU)))) = refValue;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x2U;

    __edis();
}

//*****************************************************************************
//
//! \brief Sets the ping tag value, used by either timeout counter initiated
//!        PING frame transfer or by external ping trigger input.
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] frameTag 4 bit tag value for ping time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxPingTag(uint32_t base, FSI_FrameTag frameTag)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) = (uint16_t)frameTag;
}

//*****************************************************************************
//
//! \brief  Disables ping timer logic
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxPingTimer(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~0x2U;
    __edis();
}

//*****************************************************************************
//
//! \brief Enables external trigger to transmit a ping frame
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] extTrigSel can be one of the external inputs from 0 to 63.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxExtPingTrigger(uint32_t base, uint16_t extTrigSel)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    //
    // Select external input trigger
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &
                                        (~0x1F8U)) |
                                        (extTrigSel <<
                                        3U);
    //
    // Enable ping frame transmission through external trigger
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x4U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables external trigger logic
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxExtPingTrigger(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~0x4U;
    __edis();
}

//*****************************************************************************
//
//! \brief Gives Current value of Ping Timeout Logic Counter
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return Current value of counter is returned
//
//*****************************************************************************
static inline uint32_t
FSI_getTxCurrentPingTimeoutCounter(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0xEU)))));
}

//*****************************************************************************
//
//! \brief Enables to generate DMA event on completion of a frame transfer
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxDMAEvent(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disable to generate DMA event on completion of a frame transfer
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxDMAEvent(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! \brief Locks the control of all transmit control registers,once locked
//!        further writes will not take effect until system reset occurs
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \note System reset only can unlock registers once locked.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_lockTxCtrl(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x12U)))) = ((uint16_t)0x1U |
                                        ((0x00A5U) <<
                                        8U));
    __edis();
}

//*****************************************************************************
//
//! \brief Returns current status of all the error flags
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return the status of error flags,each bit of integer is associated with
//!         one error flag.
//!
//! Example Usage - function will set the bits corresponding to respective
//!                 error flag in return value
//!     evtStatus = FSI_getTxEventStatus(FSI_base)
//!     if bit value of evtStatus is 12(01100) means
//!     FSI_TX_EVT_OVERRUN and FSI_TX_EVT_PING_HW_TRIG flags are set
//
//*****************************************************************************
static inline uint16_t
FSI_getTxEventStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0x14U)))) & (0x000FU));
}

//*****************************************************************************
//
//! \brief Enables user to set TX error flags
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] evtFlags contains list of event and error flags that are
//!             supposed to be set.
//!
//! \details Writing a 1 to this bit position will cause the corresponding bit
//!          in \b TX_EVT_ERR_STATUS register to get set. The purpose of this
//!          register is to allow software to simulate the effect of the event
//!          and test the associated software/ISR.
//!
//! Example Usage
//!     evtFlags = FSI_TX_EVT_FRAME_DONE & FSI_TX_EVT_OVERRUN
//!     FSI_forceTxEvents(FSI_base,evtFlags)
//!     Above call sets error flag to frameDone and overRun events
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_forceTxEvents(uint32_t base, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) = (evtFlags & (0x000FU));
    __edis();
}

//*****************************************************************************
//
//! \brief Enables user to clear TX error flags
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] evtFlags contains list of event and error flags that are
//!             supposed to be cleared.
//!
//! \details Writing a 1 to this bit position will cause the corresponding bit
//!          in the TX_EVT_ERR_STATUS register to get cleared to 0
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_clearTxEvents(uint32_t base, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) = (evtFlags & (0x000FU));
    __edis();
}

//*****************************************************************************
//
//! \brief Sets the CRC value to be picked transmission if transmission is
//!        configured to use user defined SW CRC
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] userCRCValue is user defined CRC
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxUserCRC(uint32_t base, uint16_t userCRCValue)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x40U;
    __edis();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x18U)))) = userCRCValue;
}

//*****************************************************************************
//
//! \brief Sets the CRC value to be picked transmission if transmission is
//!        configured to use user defined SW CRC
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxUserCRC(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x40U;
    __edis();
}

//*****************************************************************************
//
//! \brief Sets data for ECC logic computaion
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] data data value for which ECC needs to be computed
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxECCdata(uint32_t base, uint32_t data)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x20U)))) = data;
}

//*****************************************************************************
//
//! \brief Returns ECC value evaluated for 16/32 bit data
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return ECC value for input data
//
//*****************************************************************************
static inline uint16_t
FSI_getTxECCValue(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0x22U)))) & 0x7FU);
}

//*****************************************************************************
//
//! \brief  Enables user to generate interrupt on occurrence of FSI_TxEventList
//!         events
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] intNum is the type of interrupt to be generated
//!                    interrupt1 or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//!             should be generated.
//!
//! Example Usage
//!     intFlags = FSI_TX_EVT_FRAME_DONE && FSI_TX_EVT_BUF_OVERRUN
//!                             && FSI_TX_EVT_PING_TIMEOUT
//!     FSI_enableTxInterrupt(FSI_base, FSI_INT1, intFlags)
//!     above configuration will generate signal on interrupt line 1 upon
//!     frameDone, BufOverRun and PingTimeOut event
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxInterrupt(uint32_t base, FSI_InterruptNum intNum,
                      uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(intNum == FSI_INT1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) |= (intFlags & (0x000FU));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) |= ((intFlags & (0x000FU)) <<
                                            (0x8U));
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Enables user to disable generation interrupt on occurrence of
//!        FSI_TxEventList events
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] intNum is the type of interrupt to be generated
//!                    interrupt1 or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//!            generation has to be disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxInterrupt(uint32_t base, FSI_InterruptNum intNum,
                       uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(intNum == FSI_INT1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) &= ~(intFlags & (0x000FU));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) &= ((~(intFlags & (0x000FU)) <<
                                            (0x8U)) | 0xFFU);
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Returns address of Tx data buffer
//!
//! \details Data buffer is consisting of 16 words from offset- 0x40 to 0x4e
//!
//! \param[in]  base is the FSI Tx module base address
//!
//! \return Tx data buffer address
//
//*****************************************************************************
static inline uint32_t
FSI_getTxBufferAddress(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(base + (0x40U + (0)));
}

//*****************************************************************************
//
//! \brief Resets clock or ping timeout counter or entire TX module
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] submodule the name of submodule which is supposed to be reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_resetTxModule(uint32_t base, FSI_TxSubmoduleInReset submodule);

//*****************************************************************************
//
//! \brief Clears reset on clock or ping timeout counter or entire TX module
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] submodule the name of submodule, to be brought out of reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_clearTxModuleReset(uint32_t base, FSI_TxSubmoduleInReset submodule);

//*****************************************************************************
//
//! \brief Writes data in FSI Tx buffer
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] array is the address of the array of words to be transmitted.
//! \param[in] length is the number of words in the array to be transmitted.
//! \param[in] bufOffset is the offset in Tx buffer where data will be written
//!
//! \note Data Overwrite protection is implemented in this function by ensuring
//!       not more than 16 words are written and also wrap around case is taken
//!       care when more words need to be written if last write happens at
//!       maximum offset in Tx buffer
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_writeTxBuffer(uint32_t base, const uint16_t array[], uint16_t length,
                  uint16_t bufOffset);

//*****************************************************************************

//*****************************************************************************
//
// FSI Rx function prototypes/definitions
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Checks the FSI-Rx base address
//!
//! \param base is the base address of the FSI-Rx module
//!
//! \return returns \b true if the base address is valid and \b false otherwise
//
//*****************************************************************************

//*****************************************************************************
//
//! \brief Enables internal loopback where mux will select
//!  internal pins coming from TX module instead of what comes from pins
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxInternalLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |=
                                ((uint16_t)0x2U |
                                ((0x00A5U) << 8U));
    __edis();
}

//*****************************************************************************
//
//! \brief Disables internal loopback where mux will not use internal pins
//!        coming from TX module
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxInternalLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) =
                            ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                             (~0x2U)) |
                            ((0x00A5U) << 8U);
    __edis();
}

//*****************************************************************************
//
//! \brief Receive clock is selected from the internal port coming
//!        from TX module
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxSPIPairing(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |=
                            ((uint16_t)0x4U |
                             ((0x00A5U) << 8U));
    __edis();
}

//*****************************************************************************
//
//! \brief Selects regular receive clock coming from the pins
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxSPIPairing(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                          (~0x4U)) |
                                          ((0x00A5U) <<
                                          8U);
    __edis();
}

//*****************************************************************************
//
//! \brief Selects number of data lines used for receiving
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] dataWidth selection between 1 or 2 lane receive operation
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxDataWidth(uint32_t base, FSI_DataWidth dataWidth)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                                        (~0x3U)) |
                                        (uint16_t)dataWidth;
    __edis();
}

//*****************************************************************************
//
//! \brief Enables SPI compatible mode in FSI Rx
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxSPIMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x4U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables SPI compatible mode in FSI Rx
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxSPIMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x4U;
    __edis();
}

//*****************************************************************************
//
//! \brief Sets the frame size if frame type is user/software defined frame
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] nWords  is number of data words in a software defined frame
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxSoftwareFrameSize(uint32_t base, uint16_t nWords)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                                         (~0x78U)) |
                                        ((nWords - 1) <<
                                         3U);
    __edis();
}

//*****************************************************************************
//
//! \brief Select between 16-bit and 32-bit ECC computation
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] eccComputeWidth is ECC Computation width
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxECCComputeWidth(uint32_t base, FSI_ECCComputeWidth eccComputeWidth)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(eccComputeWidth == FSI_16BIT_ECC_COMPUTE)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x80U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x80U;
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Setting for when Ping timeout can reset and restart
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] pingTimeoutMode can be HW or both HW/SW initiated
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxPingTimeoutMode(uint32_t base, FSI_PingTimeoutMode pingTimeoutMode)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(pingTimeoutMode == FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x100U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x100U;
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Gets frame type received in the last successful frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return value of Frame type received on last successful frame
//
//*****************************************************************************
static inline FSI_FrameType
FSI_getRxFrameType(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((FSI_FrameType)((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) &
            0xFU));
}

//*****************************************************************************
//
//! \brief Enables to generate DMA event on completion of a successful
//!        frame reception
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxDMAEvent(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the DMA event generation on completion of a successful
//!        frame reception
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxDMAEvent(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! \brief Returns Frame tag received for the last successful frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return frame tag value.
//
//*****************************************************************************
static inline uint16_t
FSI_getRxFrameTag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) &
            0x1EU) >>
            1U);
}

//*****************************************************************************
//
//! \brief Returns User-Data(8-bit) field for received data frame.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return user data field value.
//
//*****************************************************************************
static inline uint16_t
FSI_getRxUserDefinedData(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) &
            0xFF00U) >>
            8U);
}

//*****************************************************************************
//
//! \brief Returns current status of all the evetn/error flags
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return the status of error flags,each bit of integer is associated
//!         with one error flag.
//!
//! Example Usage - function will set the bits corresponding to respective
//!     error flag in return value
//!     evtFlags = FSI_getRxEventStatus(FSI_base)
//!     if value of evtFlags is 1036(0100000001100) means
//!     FSI_RX_EVT_FRAME_OVERRUN,FSI_RX_EVT_TYPE_ERR and
//!     FSI_RX_EVT_CRC_ERR flags are set
//
//*****************************************************************************
static inline uint16_t
FSI_getRxEventStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) & (0x7FFFU));
}


//*****************************************************************************
//
//! \brief Enables user to set RX event/error flags
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] evtFlags contains list of error flags to be set
//!
//! \return None.
//!
//! Example Usage
//!     evtFlags = FSI_RX_EVT_EOF_ERR && FSI_RX_EVT_TYPE_ERR
//!     FSI_forceRxEvents(FSI_base,evtFlags)
//!     Above call sets error flag to FSI_RX_ERR_EOF_ERR and
//!     FSI_RX_ERR_TYPE_ERR events
//
//*****************************************************************************
static inline void
FSI_forceRxEvents(uint32_t base, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xDU)))) = (evtFlags & (0x7FFFU));
    __edis();
}

//*****************************************************************************
//
//! \brief Enables user to clear RX event/error flags
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] evtFlags contains list of error flags to be cleared
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_clearRxEvents(uint32_t base, uint16_t evtFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) = (evtFlags & (0x7FFFU));
    __edis();
}

//*****************************************************************************
//
//! \brief Returns CRC value received in data frame/frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return  CRC value received in data frame
//
//*****************************************************************************
static inline uint16_t
FSI_getRxReceivedCRC(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) & 0xFFU);
}

//*****************************************************************************
//
//! \brief Computes and returns CRC value for data received
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return CRC value computed on received data
//
//*****************************************************************************
static inline uint16_t
FSI_getRxComputedCRC(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &
            0xFF00U) >> 8U);
}

//*****************************************************************************
//
//! \brief Sets the value for receive buffer pointer at desired location
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] bufPtrOff 4 bit offset pointer in Rx buffer from where received
//!             data will be read
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxBufferPtr(uint32_t base, uint16_t bufPtrOff)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0xEU)))) = bufPtrOff;
    __edis();
}

//*****************************************************************************
//
//! \brief Returns current buffer pointer location
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return current buffer pointer location
//!
//! \note   there could be lag due to synchronization, hence value is accurate
//!         only when no current reception is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getRxBufferPtr(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) &
           0xFU);
}

//*****************************************************************************
//
//! \brief Returns valid number of data words present in buffer which have
//!        not been read out yet
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return number of data words present in buffer which have not been read
//!         out yet
//!
//! \note   there could be lag due to synchronization, hence value is accurate
//!         only when no current reception is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getRxWordCount(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) &
            0x1F00U) >>
            8U);
}

//*****************************************************************************
//
//! \brief Enables the frame watchdog counter logic to count every time it
//!        start to receive a frame
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] wdRef reference value for ping watchdog time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxFrameWatchdog(uint32_t base, uint32_t wdRef)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x12U))))   = wdRef;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the frame watchdog counter logic
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxFrameWatchdog(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U)))) &= ~0x2U;
    __edis();
}

//*****************************************************************************
//
//! \brief Returns current value of frame watchdog counter
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return current value of frame watchdog counter
//
//*****************************************************************************
static inline uint32_t
FSI_getRxFrameWatchdogCounter(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x14U)))));
}

//*****************************************************************************
//
//! \brief Enables the ping watchdog counter logic and once the set time
//!        elapses it will indicate ping watchdog time-out has occurred
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] wdRef reference value for ping watchdog time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxPingWatchdog(uint32_t base, uint32_t wdRef)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x18U))))   = wdRef;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the ping watchdog counter logic
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxPingWatchdog(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x16U)))) &= ~0x2U;
    __edis();
}

//*****************************************************************************
//
//! \brief Returns current value of ping watchdog counter
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return current value(32 bit) of ping watchdog counter
//
//*****************************************************************************
static inline uint32_t
FSI_getRxPingWatchdogCounter(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x1AU)))));
}

//*****************************************************************************
//
//! \brief Returns the value of tag received for last ping frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return the tagValue received for last ping frame
//
//*****************************************************************************
static inline uint16_t
FSI_getRxPingTag(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x17U)))) & 0x1EU) >>
            1U);
}

//*****************************************************************************
//
//! \brief  Locks the control of all receive control registers,
//!         once locked further writes will not take effect until system
//!         reset occurs
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_lockRxCtrl(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU)))) = ((uint16_t)0x1U |
                                        ((0x00A5U) <<
                                        8U));
    __edis();
}

//*****************************************************************************
//
//! \brief Sets Rx ECC data on which ECC (SEC-DED) computaion logic runs
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] rxECCdata Data for ECC logic
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxECCData(uint32_t base, uint32_t rxECCdata)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint32_t *)((uintptr_t)(base + 0x20U)))) = rxECCdata;
}

//*****************************************************************************
//
//! \brief Sets received ECC value on which ECC (SEC-DED) computaion logic runs
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] rxECCvalue Received ECC value in a data frame
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxReceivedECCValue(uint32_t base, uint16_t rxECCvalue)
{
    //
    // Check the arguments.
    //
    ;

    //
    // ECC value can be passed as 8 bit value in USERDATA field in a frame
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x22U)))) = rxECCvalue;
}

//*****************************************************************************
//
//! \brief Returns ECC Corrected data
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return 32 bit ECC corrected data
//
//*****************************************************************************
static inline uint32_t
FSI_getRxECCCorrectedData(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(base + 0x24U)))));
}

//*****************************************************************************
//
//! \brief Returns ECC Log details
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return ECC Log value(8 bit)
//
//*****************************************************************************
static inline uint16_t
FSI_getRxECCLog(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0x26U)))) &
           (0x1U | 0x2U));
}

//*****************************************************************************
//
//! \brief Let user generate interrupt on occurrence of Rx events
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] intNum the type of interrupt to be generated interrupt1
//!             or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//!             should be generated. Each bit will represent one event,bits for
//!             the events on which user want to generate interrupt will be set
//!             others remain clear
//!
//! \return None.
//!
//! Example Usage
//!     evtFlags = FSI_RX_EVT_PING_WD_TIMEOUT & FSI_RX_INT_TYPE_ERR
//!     FSI_enableRxInterrupt(FSI_base,FSI_INT1,evtFlags)
//!     Above call will generate interrupt1 on events
//!     FSI_RX_INT_PING_WD_TIMEOUT and FSI_RX_INT_TYPE_ERR
//
//*****************************************************************************
static inline void
FSI_enableRxInterrupt(uint32_t base, FSI_InterruptNum intNum,
                      uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(intNum == FSI_INT1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) |= (intFlags &
                                             (0x7FFFU));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x1DU)))) |= (intFlags &
                                             (0x7FFFU));
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Let user disable interrupt generation on Rx events
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] intNum the type of interrupt to be generated interrupt1
//!             or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//!             generation has to be disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxInterrupt(uint32_t base, FSI_InterruptNum intNum,
                       uint16_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    if(intNum == FSI_INT1)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) &= ~(intFlags &
                                              (0x7FFFU));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x1DU)))) &= ~(intFlags &
                                              (0x7FFFU));
    }

    __edis();
}

//*****************************************************************************
//
//! \brief Returns address of Rx data buffer
//!
//! \details Data buffer is consisting of 16 words from offset- 0x40 to 0x4e
//!
//! \param[in]  base is the FSI Rx module base address
//!
//! \return Rx data buffer address
//
//*****************************************************************************
static inline uint32_t
FSI_getRxBufferAddress(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(base + (0x40U + (0)));
}

//*****************************************************************************
//
//! \brief Sets the Rx Frame Reference Tag Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming frame tag.
//!
//! \param[in]  base is the FSI Rx module base address
//! \param[in]  refVal is the Rx frame reference tag value to be set
//!
//! \return Rx data buffer address
//
//*****************************************************************************
static inline void
FSI_setRxFrameTagRef(uint32_t base, uint16_t refVal)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Sets the Rx frame tag reference.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &
           ~((uint16_t)0xFU)) |
           (refVal << 0U));
    __edis();
}

//*****************************************************************************
//
//! \brief Returns the Rx Frame Reference Tag Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming frame tag.
//!
//! \param[in]  base is the FSI Rx module base address
//!
//! \return Rx frame reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxFrameTagRef(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Returns the Rx frame tag reference.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &
           0xFU) >> 0U);
}

//*****************************************************************************
//
//! \brief Sets the Rx Frame Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in]  base is the FSI Rx module base address
//! \param[in]  maskVal is the Rx frame tag mask value to be set
//!
//! \return Rx frame tag mask
//
//*****************************************************************************
static inline void
FSI_setRxFrameTagMask(uint32_t base, uint16_t maskVal)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Sets the Rx frame tag mask.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &
           ~((uint16_t)0xF0U)) |
           (maskVal << 4U));
    __edis();
}

//*****************************************************************************
//
//! \brief Returns the Rx Frame Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in]  base is the FSI Rx module base address
//!
//! \return Rx frame reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxFrameTagMask(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Returns the frame tag mask.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &
          0xF0U) >> 4U);
}

//*****************************************************************************
//
//! \brief Enables the Rx Frame Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxFrameTagCompare(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Enables the frame tag compare mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) |= 0x100U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the Rx Frame Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxFrameTagCompare(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Disables the Rx frame tag compare mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &=
                                   ~(uint16_t)0x100U;
    __edis();
}

//*****************************************************************************
//
//! \brief Enables the Rx Frame Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxFrameBroadcast(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Enables Rx frame broadcast mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) |= 0x200U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the Rx Frame Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxFrameBroadcast(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Disables Rx frame broadcast mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &=
                                  ~(uint16_t)0x200U;
    __edis();
}

//
// ping frame related APIs
//
//*****************************************************************************
//
//! \brief Sets the Rx Ping Tag Reference Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming ping tag.
//!
//! \param[in]  base is the FSI Rx module base address
//! \param[in]  refVal is the Rx frame reference tag value to be set
//!
//! \return Rx data buffer address
//
//*****************************************************************************
static inline void
FSI_setRxPingTagRef(uint32_t base, uint16_t refVal)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set Rx ping tag reference value.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) &
           ~((uint16_t)0xFU)) |
           (refVal << 0U));
    __edis();
}

//*****************************************************************************
//
//! \brief Returns the Rx Ping Reference Tag Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming ping tag.
//!
//! \param[in]  base is the FSI Rx module base address
//!
//! \return Rx frame reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxPingTagRef(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Returns Rx ping tag reference.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) &
            0xFU) >> 0U);
}

//*****************************************************************************
//
//! \brief Sets the Rx Ping Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in]  base is the FSI Rx module base address
//! \param[in]  maskVal is the Rx frame tag mask value to be set
//!
//! \return Rx ping tag mask
//
//*****************************************************************************
static inline void
FSI_setRxPingTagMask(uint32_t base, uint16_t maskVal)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set Rx ping tag mask.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) &
           ~((uint16_t)0xF0U)) |
           (maskVal << 4U));
    __edis();
}

//*****************************************************************************
//
//! \brief Returns the Rx Ping Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in]  base is the FSI Rx module base address
//!
//! \return Rx ping reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxPingTagMask(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Returns ping tag mask.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) &
            0xF0U) >> 4U);
}

//*****************************************************************************
//
//! \brief Enables the Rx Ping Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxPingTagCompare(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Enables the Rx ping tag compare mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) |= 0x100U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the Rx Ping Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxPingTagCompare(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Disables Rx ping tag compare mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) &=
                                   ~(uint16_t)0x100U;
    __edis();
}

//*****************************************************************************
//
//! \brief Enables the Rx Ping Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxPingBroadcast(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Enables the Rx ping broadcast mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) |= 0x200U;
    __edis();
}

//*****************************************************************************
//
//! \brief Disables the Rx Ping Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxPingBroadcast(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Disables the Rx ping broadcast.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x29U)))) &=
                                  ~(uint16_t)0x200U;
    __edis();
}
//*****************************************************************************
//
//! \brief Resets frame watchdog,ping watchdog or entire RX module
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] submodule the name of module which is supposed to be reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_resetRxModule(uint32_t base, FSI_RxSubmoduleInReset submodule);

//*****************************************************************************
//
//! \brief Clears resets on frame watchdog,ping watchdog or entire RX module
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] submodule module which is to be brought out of reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_clearRxModuleReset(uint32_t base, FSI_RxSubmoduleInReset submodule);

//*****************************************************************************
//
//! \brief Reads data from FSI Rx buffer
//!
//! \param[in]  base is the FSI Rx module base address
//! \param[out] array is the address of the array of words to receive the data
//! \param[in]  length is the number of words in the array to be received
//! \param[in]  bufOffset is the offset in Rx buffer from where data will
//!             be read
//!
//! \note This function ensures that not more than 16 words are read and
//!       wrap around case is also taken care when more words need to be read
//!       wherein last read happens at maximum offset in Rx buffer
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_readRxBuffer(uint32_t base, uint16_t array[], uint16_t length,
                 uint16_t bufOffset);

//*****************************************************************************
//
//! \brief Adds delay for selected tap line
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] delayTapType the line for which delay needs to be added
//!            it can be either RXCLK,RXD0 or RXD1
//! \param[in] tapValue   5 bit value of the amount of delay to be added
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_configRxDelayLine(uint32_t base, FSI_RxDelayTapType delayTapType,
                      uint16_t tapValue);

//*****************************************************************************
//
//! \brief Initializes FSI Tx module
//!
//! \details Software based initialization of the FSI transmitter IP. This is
//!          typically needed only once during initialization or if the module
//!          needs to be reset due to an underrun condition that occurred during
//!          operation.
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] prescalar is the user configurable clock divider for PLL input
//!            clock
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_performTxInitialization(uint32_t base, uint16_t prescalar);

//*****************************************************************************
//
//! \brief Initializes FSI Rx module
//!
//! \details Software based initialization of the FSI receiver module.This is
//!          typically needed only once during initialization. However, if there
//!          are framing errors in the received frames, then the receive module
//!          needs to be reset so that subsequent frames/packets can be handled
//!          fresh.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_performRxInitialization(uint32_t base);

//*****************************************************************************
//
//! \brief Sends Flush pattern sequence
//!
//! \details Flush pattern sequence sent by a FSI transmit module will bring the
//!          FSI receive module out of reset so that it will then be ready to
//!          receive subsequent frames.
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] prescalar is the user configurable clock divider for PLL input
//!            clock
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_executeTxFlushSequence(uint32_t base, uint16_t prescalar);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   gpio.h
//
// TITLE:  C28x GPIO driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup gpio_api GPIO
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_gpio.h
//
// TITLE:   Definitions for the GPIO registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the GPIO register offsets
//
//*************************************************************************************************




//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACTRL register
//
//*************************************************************************************************
                                                // GPIO15
                                                // GPIO23
                                                // GPIO31

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAQSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAQSEL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAMUX1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAMUX2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPADIR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAPUD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAINV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAODR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAAMSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAGMUX1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAGMUX2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPALOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCTRL register
//
//*************************************************************************************************
                                                // GPIO39
                                                // GPIO47
                                                // GPIO55
                                                // GPIO63

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBQSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBQSEL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBMUX1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBMUX2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBDIR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBPUD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBINV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBODR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBGMUX1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBGMUX2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCTRL register
//
//*************************************************************************************************
                                                // GPIO231
                                                // GPIO239
                                                // GPIO247
                                                // GPIO255

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHQSEL1 register
//
//*************************************************************************************************
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin
                                                // Pin

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHQSEL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHMUX1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHMUX2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHINV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHAMSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHGMUX1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHGMUX2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCR register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the GPADAT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPASET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACLEAR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPATOGGLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBDAT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCLEAR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBTOGGLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHDAT register
//
//*************************************************************************************************




//###########################################################################
//
// FILE:    hw_xint.h
//
// TITLE:   Definitions for the XINT registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the XINT register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT1CR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT2CR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT3CR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT4CR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT5CR register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:   xbar.h
//
// TITLE:  C28x X-BAR driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup xbar_api XBAR
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_clbxbar.h
//
// TITLE:   Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG0MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG0MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG1MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG1MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG2MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG2MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG3MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG3MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG4MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG4MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG5MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG5MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG6MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG6MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG7MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR
                                                        // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG7MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR
                                                         // CLB-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG0MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG1MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG2MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG3MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG4MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG5MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG6MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG7MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIGOUTINV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIGLOCK register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:    hw_epwmxbar.h
//
// TITLE:   Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP4MUX0TO15CFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP4MUX16TO31CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP5MUX0TO15CFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP5MUX16TO31CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP7MUX0TO15CFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP7MUX16TO31CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP8MUX0TO15CFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP8MUX16TO31CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP9MUX0TO15CFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP9MUX16TO31CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP10MUX0TO15CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP10MUX16TO31CFG register
//
//*************************************************************************************************
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP11MUX0TO15CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP11MUX16TO31CFG register
//
//*************************************************************************************************
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP12MUX0TO15CFG register
//
//*************************************************************************************************
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR
                                                       // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP12MUX16TO31CFG register
//
//*************************************************************************************************
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR
                                                        // EPWM-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP4MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP5MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP7MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP8MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP9MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP10MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP11MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP12MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIPOUTINV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIPLOCK register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:    hw_inputxbar.h
//
// TITLE:   Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the INPUTSELECTLOCK register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:    hw_outputxbar.h
//
// TITLE:   Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT1MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT1MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT2MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT2MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT3MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT3MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT4MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT4MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT5MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT5MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT6MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT6MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT7MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT7MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT8MUX0TO15CFG register
//
//*************************************************************************************************
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR
                                                        // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT8MUX16TO31CFG register
//
//*************************************************************************************************
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR
                                                         // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT1MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT2MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT3MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT4MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT5MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT6MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT7MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT8MUXENABLE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCH register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCHCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCHFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCHENABLE register
//
//*************************************************************************************************
                                                 // OUTPUT-XBAR
                                                 // OUTPUT-XBAR
                                                 // OUTPUT-XBAR
                                                 // OUTPUT-XBAR
                                                 // OUTPUT-XBAR
                                                 // OUTPUT-XBAR
                                                 // OUTPUT-XBAR
                                                 // OUTPUT-XBAR

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTINV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLOCK register
//
//*************************************************************************************************



//###########################################################################
//
// FILE:    hw_xbar.h
//
// TITLE:   Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR4 register
//
//*************************************************************************************************




//*****************************************************************************
//
// Useful defines used within the driver functions.
// Not intended for use by application code.
//
//*****************************************************************************



//*****************************************************************************
//
// The following values define the muxes parameter for XBAR_enableEPWMMux(),
// XBAR_enableOutputMux(), XBAR_disableEPWMMux(), and
// XBAR_disableOutputMux().
//
//*****************************************************************************

//*****************************************************************************
//
//! The following values define the \e output parameter for
//! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and
//! XBAR_disableOutputMux().
//
//*****************************************************************************
typedef enum
{
    XBAR_OUTPUT1 = 0,       //!< OUTPUT1 of the Output X-BAR
    XBAR_OUTPUT2 = 2,       //!< OUTPUT2 of the Output X-BAR
    XBAR_OUTPUT3 = 4,       //!< OUTPUT3 of the Output X-BAR
    XBAR_OUTPUT4 = 6,       //!< OUTPUT4 of the Output X-BAR
    XBAR_OUTPUT5 = 8,       //!< OUTPUT5 of the Output X-BAR
    XBAR_OUTPUT6 = 10,      //!< OUTPUT6 of the Output X-BAR
    XBAR_OUTPUT7 = 12,      //!< OUTPUT7 of the Output X-BAR
    XBAR_OUTPUT8 = 14       //!< OUTPUT8 of the Output X-BAR
} XBAR_OutputNum;

//*****************************************************************************
//
//! The following values define the \e trip parameter for
//! XBAR_setEPWMMuxConfig(), XBAR_enableEPWMMux(), and XBAR_disableEPWMMux().
//
//*****************************************************************************
typedef enum
{
    XBAR_TRIP4  = 0,        //!< TRIP4 of the ePWM X-BAR
    XBAR_TRIP5  = 2,        //!< TRIP5 of the ePWM X-BAR
    XBAR_TRIP7  = 4,        //!< TRIP7 of the ePWM X-BAR
    XBAR_TRIP8  = 6,        //!< TRIP8 of the ePWM X-BAR
    XBAR_TRIP9  = 8,        //!< TRIP9 of the ePWM X-BAR
    XBAR_TRIP10 = 10,       //!< TRIP10 of the ePWM X-BAR
    XBAR_TRIP11 = 12,       //!< TRIP11 of the ePWM X-BAR
    XBAR_TRIP12 = 14        //!< TRIP12 of the ePWM X-BAR
} XBAR_TripNum;

//*****************************************************************************
//
// The following values define the trip parameter for XBAR_setCLBMuxConfig(),
// XBAR_enableCLBMux(), and XBAR_disableCLBMux().
//
//*****************************************************************************
typedef enum
{
    XBAR_AUXSIG0 = 0,
    XBAR_AUXSIG1 = 2,
    XBAR_AUXSIG2 = 4,
    XBAR_AUXSIG3 = 6,
    XBAR_AUXSIG4 = 8,
    XBAR_AUXSIG5 = 10,
    XBAR_AUXSIG6 = 12,
    XBAR_AUXSIG7 = 14
} XBAR_AuxSigNum;

//*****************************************************************************
//
//! The following values define the \e input parameter for XBAR_setInputPin().
//
//*****************************************************************************
typedef enum
{
    XBAR_INPUT1,            //!< ePWM[TZ1], ePWM[TRIP1], X-BARs, eCAPs
    XBAR_INPUT2,            //!< ePWM[TZ2], ePWM[TRIP2], X-BARs, eCAPs
    XBAR_INPUT3,            //!< ePWM[TZ3], ePWM[TRIP3], X-BARs, eCAPs
    XBAR_INPUT4,            //!< ADC wrappers, X-BARs, XINT1, eCAPs
    XBAR_INPUT5,            //!< EXTSYNCIN1, X-BARs, XINT2, eCAPs
    XBAR_INPUT6,            //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3, eCAPs
    XBAR_INPUT7,            //!< X-BARs, eCAPs
    XBAR_INPUT8,            //!< X-BARs, eCAPs
    XBAR_INPUT9,            //!< X-BARs, eCAPs
    XBAR_INPUT10,           //!< X-BARs, eCAPs
    XBAR_INPUT11,           //!< X-BARs, eCAPs
    XBAR_INPUT12,           //!< X-BARs, eCAPs
    XBAR_INPUT13,           //!< XINT4, X-BARs, eCAPs
    XBAR_INPUT14,           //!< XINT5, X-BARs, eCAPs
    XBAR_INPUT15,           //!< eCAPs
    XBAR_INPUT16            //!< eCAPs
} XBAR_InputNum;

//*****************************************************************************
//
//! The following values define the \e muxConfig parameter for
//! XBAR_setOutputMuxConfig().
//
//*****************************************************************************
typedef enum
{
    //
    //OUTPUTXBAR
    //
    XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH        = 0x0000,
    XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L   = 0x0001,
    XBAR_OUT_MUX00_ADCAEVT1                = 0x0002,
    XBAR_OUT_MUX00_ECAP1_OUT               = 0x0003,
    XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL        = 0x0200,
    XBAR_OUT_MUX01_INPUTXBAR1              = 0x0201,
    XBAR_OUT_MUX01_CLB1_OUT4               = 0x0202,
    XBAR_OUT_MUX01_ADCCEVT1                = 0x0203,
    XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH        = 0x0400,
    XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L   = 0x0401,
    XBAR_OUT_MUX02_ADCAEVT2                = 0x0402,
    XBAR_OUT_MUX02_ECAP2_OUT               = 0x0403,
    XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL        = 0x0600,
    XBAR_OUT_MUX03_INPUTXBAR2              = 0x0601,
    XBAR_OUT_MUX03_CLB1_OUT5               = 0x0602,
    XBAR_OUT_MUX03_ADCCEVT2                = 0x0603,
    XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH        = 0x0800,
    XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L   = 0x0801,
    XBAR_OUT_MUX04_ADCAEVT3                = 0x0802,
    XBAR_OUT_MUX04_ECAP3_OUT               = 0x0803,
    XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL        = 0x0A00,
    XBAR_OUT_MUX05_INPUTXBAR3              = 0x0A01,
    XBAR_OUT_MUX05_CLB2_OUT4               = 0x0A02,
    XBAR_OUT_MUX05_ADCCEVT3                = 0x0A03,
    XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH        = 0x0C00,
    XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L   = 0x0C01,
    XBAR_OUT_MUX06_ADCAEVT4                = 0x0C02,
    XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL        = 0x0E00,
    XBAR_OUT_MUX07_INPUTXBAR4              = 0x0E01,
    XBAR_OUT_MUX07_CLB2_OUT5               = 0x0E02,
    XBAR_OUT_MUX07_ADCCEVT4                = 0x0E03,
    XBAR_OUT_MUX08_ADCBEVT1                = 0x1002,
    XBAR_OUT_MUX09_INPUTXBAR5              = 0x1201,
    XBAR_OUT_MUX09_CLB3_OUT4               = 0x1202,
    XBAR_OUT_MUX10_ADCBEVT2                = 0x1402,
    XBAR_OUT_MUX11_INPUTXBAR6              = 0x1601,
    XBAR_OUT_MUX11_CLB3_OUT5               = 0x1602,
    XBAR_OUT_MUX12_ADCBEVT3                = 0x1802,
    XBAR_OUT_MUX14_EXTSYNCOUT              = 0x1C03,
    XBAR_OUT_MUX14_ADCBEVT4                = 0x1C02,
    XBAR_OUT_MUX13_ADCSOCA                 = 0x1A01,
    XBAR_OUT_MUX13_CLB4_OUT4               = 0x1A02,
    XBAR_OUT_MUX15_ADCSOCB                 = 0x1E01,
    XBAR_OUT_MUX15_CLB4_OUT5               = 0x1E02,
    XBAR_OUT_MUX16_SD1FLT1_COMPH           = 0x2000,
    XBAR_OUT_MUX16_SD1FLT1_COMPH_OR_COMPL  = 0x2001,
    XBAR_OUT_MUX17_SD1FLT1_COMPL           = 0x2200,
    XBAR_OUT_MUX17_CLAHALT                 = 0x2203,
    XBAR_OUT_MUX18_SD1FLT2_COMPH           = 0x2400,
    XBAR_OUT_MUX18_SD1FLT2_COMPH_OR_COMPL  = 0x2401,
    XBAR_OUT_MUX19_SD1FLT2_COMPL           = 0x2600,
    XBAR_OUT_MUX20_SD1FLT3_COMPH           = 0x2800,
    XBAR_OUT_MUX20_SD1FLT3_COMPH_OR_COMPL  = 0x2801,
    XBAR_OUT_MUX21_SD1FLT3_COMPL           = 0x2A00,
    XBAR_OUT_MUX21_FSIA_RX_TRIG2           = 0x2A03,
    XBAR_OUT_MUX22_SD1FLT4_COMPH           = 0x2C00,
    XBAR_OUT_MUX22_SD1FLT4_COMPH_OR_COMPL  = 0x2C01,
    XBAR_OUT_MUX23_SD1FLT4_COMPL           = 0x2E00,
    XBAR_OUT_MUX24_SD2FLT1_COMPH           = 0x3000,
    XBAR_OUT_MUX24_SD2FLT1_COMPH_OR_COMPL  = 0x3001,
    XBAR_OUT_MUX25_SD2FLT1_COMPL           = 0x3200,
    XBAR_OUT_MUX26_SD2FLT2_COMPH           = 0x3400,
    XBAR_OUT_MUX26_SD2FLT2_COMPH_OR_COMPL  = 0x3401,
    XBAR_OUT_MUX27_SD2FLT2_COMPL           = 0x3600,
    XBAR_OUT_MUX28_SD2FLT3_COMPH           = 0x3800,
    XBAR_OUT_MUX28_SD2FLT3_COMPH_OR_COMPL  = 0x3801,
    XBAR_OUT_MUX29_SD2FLT3_COMPL           = 0x3A00,
    XBAR_OUT_MUX30_SD2FLT4_COMPH           = 0x3C00,
    XBAR_OUT_MUX30_SD2FLT4_COMPH_OR_COMPL  = 0x3C01,
    XBAR_OUT_MUX31_SD2FLT4_COMPL           = 0x3E00,
    XBAR_OUT_MUX19_ERRSTS                  = 0x2603,
    XBAR_OUT_MUX30_EPG1_OUT0               = 0x3C03,
    XBAR_OUT_MUX31_ERRSTS                  = 0x3E02,
    XBAR_OUT_MUX31_EPG1_OUT1               = 0x3E03,

    //
    //CLBOUTPUTXBAR
    //
    XBAR_OUT_MUX00_CLB1_OUT0               = 0x0000,
    XBAR_OUT_MUX00_XTRIP_OUT1              = 0x0003,
    XBAR_OUT_MUX01_CLB1_OUT1               = 0x0200,
    XBAR_OUT_MUX01_XTRIP_OUT2              = 0x0203,
    XBAR_OUT_MUX02_CLB1_OUT2               = 0x0400,
    XBAR_OUT_MUX03_CLB1_OUT3               = 0x0600,
    XBAR_OUT_MUX04_CLB1_OUT4               = 0x0800,
    XBAR_OUT_MUX05_CLB1_OUT5               = 0x0A00,
    XBAR_OUT_MUX06_CLB1_OUT6               = 0x0C00,
    XBAR_OUT_MUX07_CLB1_OUT7               = 0x0E00,
    XBAR_OUT_MUX08_CLB2_OUT0               = 0x1000,
    XBAR_OUT_MUX08_XTRIP_OUT3              = 0x1003,
    XBAR_OUT_MUX09_CLB2_OUT1               = 0x1200,
    XBAR_OUT_MUX09_XTRIP_OUT4              = 0x1203,
    XBAR_OUT_MUX10_CLB2_OUT2              = 0x1400,
    XBAR_OUT_MUX11_CLB2_OUT3              = 0x1600,
    XBAR_OUT_MUX12_CLB2_OUT4              = 0x1800,
    XBAR_OUT_MUX13_CLB2_OUT5              = 0x1A00,
    XBAR_OUT_MUX14_CLB2_OUT6              = 0x1C00,
    XBAR_OUT_MUX15_CLB2_OUT7              = 0x1E00,
    XBAR_OUT_MUX16_CLB3_OUT0              = 0x2000,
    XBAR_OUT_MUX16_XTRIP_OUT5             = 0x2003,
    XBAR_OUT_MUX17_CLB3_OUT1              = 0x2200,
    XBAR_OUT_MUX17_XTRIP_OUT6             = 0x2203,
    XBAR_OUT_MUX18_CLB3_OUT2              = 0x2400,
    XBAR_OUT_MUX19_CLB3_OUT3              = 0x2600,
    XBAR_OUT_MUX20_CLB3_OUT4              = 0x2800,
    XBAR_OUT_MUX21_CLB3_OUT5              = 0x2A00,
    XBAR_OUT_MUX22_CLB3_OUT6              = 0x2C00,
    XBAR_OUT_MUX23_CLB3_OUT7              = 0x2E00,
    XBAR_OUT_MUX24_CLB4_OUT0              = 0x3000,
    XBAR_OUT_MUX24_XTRIP_OUT7             = 0x3003,
    XBAR_OUT_MUX25_CLB4_OUT1              = 0x3200,
    XBAR_OUT_MUX25_XTRIP_OUT8             = 0x3203,
    XBAR_OUT_MUX26_CLB4_OUT2              = 0x3400,
    XBAR_OUT_MUX27_CLB4_OUT3              = 0x3600,
    XBAR_OUT_MUX28_CLB4_OUT4              = 0x3800,
    XBAR_OUT_MUX29_CLB4_OUT5              = 0x3A00,
    XBAR_OUT_MUX30_CLB4_OUT6              = 0x3C00,
    XBAR_OUT_MUX30_EPG1_OUT2              = 0x3C03,
    XBAR_OUT_MUX31_CLB4_OUT7              = 0x3E00,
    XBAR_OUT_MUX31_EPG1_OUT3              = 0x3E03
} XBAR_OutputMuxConfig;

//*****************************************************************************
//
//! The following values define the \e muxConfig parameter for
//! XBAR_setEPWMMuxConfig().
//
//*****************************************************************************
typedef enum
{
    XBAR_EPWM_MUX00_CMPSS1_CTRIPH          = 0x0000,
    XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L     = 0x0001,
    XBAR_EPWM_MUX00_ADCAEVT1               = 0x0002,
    XBAR_EPWM_MUX00_ECAP1_OUT              = 0x0003,
    XBAR_EPWM_MUX01_CMPSS1_CTRIPL          = 0x0200,
    XBAR_EPWM_MUX01_INPUTXBAR1             = 0x0201,
    XBAR_EPWM_MUX01_CLB1_OUT4              = 0x0202,
    XBAR_EPWM_MUX01_ADCCEVT1               = 0x0203,
    XBAR_EPWM_MUX02_CMPSS2_CTRIPH          = 0x0400,
    XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L     = 0x0401,
    XBAR_EPWM_MUX02_ADCAEVT2               = 0x0402,
    XBAR_EPWM_MUX02_ECAP2_OUT              = 0x0403,
    XBAR_EPWM_MUX03_CMPSS2_CTRIPL          = 0x0600,
    XBAR_EPWM_MUX03_INPUTXBAR2             = 0x0601,
    XBAR_EPWM_MUX03_CLB1_OUT5              = 0x0602,
    XBAR_EPWM_MUX03_ADCCEVT2               = 0x0603,
    XBAR_EPWM_MUX04_CMPSS3_CTRIPH          = 0x0800,
    XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L     = 0x0801,
    XBAR_EPWM_MUX04_ADCAEVT3               = 0x0802,
    XBAR_EPWM_MUX04_ECAP3_OUT              = 0x0803,
    XBAR_EPWM_MUX05_CMPSS3_CTRIPL          = 0x0A00,
    XBAR_EPWM_MUX05_INPUTXBAR3             = 0x0A01,
    XBAR_EPWM_MUX05_CLB2_OUT4              = 0x0A02,
    XBAR_EPWM_MUX05_ADCCEVT3               = 0x0A03,
    XBAR_EPWM_MUX06_CMPSS4_CTRIPH          = 0x0C00,
    XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L     = 0x0C01,
    XBAR_EPWM_MUX06_ADCAEVT4               = 0x0C02,
    XBAR_EPWM_MUX07_CMPSS4_CTRIPL          = 0x0E00,
    XBAR_EPWM_MUX07_INPUTXBAR4             = 0x0E01,
    XBAR_EPWM_MUX07_CLB2_OUT5              = 0x0E02,
    XBAR_EPWM_MUX07_ADCCEVT4               = 0x0E03,
    XBAR_EPWM_MUX08_ADCBEVT1               = 0x1002,
    XBAR_EPWM_MUX09_INPUTXBAR5             = 0x1201,
    XBAR_EPWM_MUX09_CLB3_OUT4              = 0x1202,
    XBAR_EPWM_MUX10_ADCBEVT2               = 0x1402,
    XBAR_EPWM_MUX11_INPUTXBAR6             = 0x1601,
    XBAR_EPWM_MUX11_CLB3_OUT5              = 0x1602,
    XBAR_EPWM_MUX12_ADCBEVT3               = 0x1802,
    XBAR_EPWM_MUX13_ADCSOCA                = 0x1A01,
    XBAR_EPWM_MUX13_CLB4_OUT4              = 0x1A02,
    XBAR_EPWM_MUX14_ADCBEVT4               = 0x1C02,
    XBAR_EPWM_MUX14_EXTSYNCOUT             = 0x1C03,
    XBAR_EPWM_MUX15_ADCSOCB                = 0x1E01,
    XBAR_EPWM_MUX15_CLB4_OUT5              = 0x1E02,
    XBAR_EPWM_MUX16_SD1FLT1_COMPH          = 0x2000,
    XBAR_EPWM_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001,
    XBAR_EPWM_MUX16_SD1FLT1_COMPZ          = 0x2002,
    XBAR_EPWM_MUX16_SD1FLT1_DRINT          = 0x2003,
    XBAR_EPWM_MUX17_SD1FLT1_COMPL          = 0x2200,
    XBAR_EPWM_MUX17_INPUTXBAR7             = 0x2201,
    XBAR_EPWM_MUX17_CLAHALT                = 0x2203,
    XBAR_EPWM_MUX18_SD1FLT2_COMPH          = 0x2400,
    XBAR_EPWM_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401,
    XBAR_EPWM_MUX18_SD1FLT2_COMPZ          = 0x2402,
    XBAR_EPWM_MUX18_SD1FLT2_DRINT          = 0x2403,
    XBAR_EPWM_MUX19_SD1FLT2_COMPL          = 0x2600,
    XBAR_EPWM_MUX19_INPUTXBAR8             = 0x2601,
    XBAR_EPWM_MUX19_ERRORSTS               = 0x2603,
    XBAR_EPWM_MUX20_SD1FLT3_COMPH          = 0x2800,
    XBAR_EPWM_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801,
    XBAR_EPWM_MUX20_SD1FLT3_COMPZ          = 0x2802,
    XBAR_EPWM_MUX20_SD1FLT3_DRINT          = 0x2803,
    XBAR_EPWM_MUX21_SD1FLT3_COMPL          = 0x2A00,
    XBAR_EPWM_MUX21_INPUTXBAR9             = 0x2A01,
    XBAR_EPWM_MUX22_SD1FLT4_COMPH          = 0x2C00,
    XBAR_EPWM_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01,
    XBAR_EPWM_MUX22_SD1FLT4_COMPZ          = 0x2C02,
    XBAR_EPWM_MUX22_SD1FLT4_DRINT          = 0x2C03,
    XBAR_EPWM_MUX23_SD1FLT4_COMPL          = 0x2E00,
    XBAR_EPWM_MUX23_INPUTXBAR10            = 0x2E01,
    XBAR_EPWM_MUX24_SD2FLT1_COMPH          = 0x3000,
    XBAR_EPWM_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001,
    XBAR_EPWM_MUX24_SD2FLT1_COMPZ          = 0x3002,
    XBAR_EPWM_MUX24_SD2FLT1_DRINT          = 0x3003,
    XBAR_EPWM_MUX25_SD2FLT1_COMPL          = 0x3200,
    XBAR_EPWM_MUX25_INPUTXBAR11            = 0x3201,
    XBAR_EPWM_MUX25_MCAN_FEVT0             = 0x3202,
    XBAR_EPWM_MUX26_SD2FLT2_COMPH          = 0x3400,
    XBAR_EPWM_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401,
    XBAR_EPWM_MUX26_SD2FLT2_COMPZ          = 0x3402,
    XBAR_EPWM_MUX26_SD2FLT2_DRINT          = 0x3403,
    XBAR_EPWM_MUX27_SD2FLT2_COMPL          = 0x3600,
    XBAR_EPWM_MUX27_INPUTXBAR12            = 0x3601,
    XBAR_EPWM_MUX27_MCAN_FEVT1             = 0x3602,
    XBAR_EPWM_MUX28_SD2FLT3_COMPH          = 0x3800,
    XBAR_EPWM_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801,
    XBAR_EPWM_MUX28_SD2FLT3_COMPZ          = 0x3802,
    XBAR_EPWM_MUX28_SD2FLT3_DRINT          = 0x3803,
    XBAR_EPWM_MUX29_SD2FLT3_COMPL          = 0x3A00,
    XBAR_EPWM_MUX29_INPUTXBAR13            = 0x3A01,
    XBAR_EPWM_MUX29_MCAN_FEVT2             = 0x3A02,
    XBAR_EPWM_MUX30_SD2FLT4_COMPH          = 0x3C00,
    XBAR_EPWM_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01,
    XBAR_EPWM_MUX30_SD2FLT4_COMPZ          = 0x3C02,
    XBAR_EPWM_MUX30_SD2FLT4_DRINT          = 0x3C03,
    XBAR_EPWM_MUX31_SD2FLT4_COMPL          = 0x3E00,
    XBAR_EPWM_MUX31_ERRORSTS               = 0x3E02,
    XBAR_EPWM_MUX31_INPUTXBAR14            = 0x3E01
} XBAR_EPWMMuxConfig;

//*****************************************************************************
//
// The following values define the muxConfig parameter for
// XBAR_setCLBMuxConfig().
//
//*****************************************************************************
typedef enum
{
    XBAR_CLB_MUX00_CMPSS1_CTRIPH           = 0x0000,
    XBAR_CLB_MUX00_CMPSS1_CTRIPH_OR_L      = 0x0001,
    XBAR_CLB_MUX00_ADCAEVT1                = 0x0002,
    XBAR_CLB_MUX00_ECAP1_OUT               = 0x0003,
    XBAR_CLB_MUX01_CMPSS1_CTRIPL           = 0x0200,
    XBAR_CLB_MUX01_INPUTXBAR1              = 0x0201,
    XBAR_CLB_MUX01_CLB1_OUT4               = 0x0202,
    XBAR_CLB_MUX01_ADCCEVT1                = 0x0203,
    XBAR_CLB_MUX02_CMPSS2_CTRIPH           = 0x0400,
    XBAR_CLB_MUX02_CMPSS2_CTRIPH_OR_L      = 0x0401,
    XBAR_CLB_MUX02_ADCAEVT2                = 0x0402,
    XBAR_CLB_MUX02_ECAP2_OUT               = 0x0403,
    XBAR_CLB_MUX03_CMPSS2_CTRIPL           = 0x0600,
    XBAR_CLB_MUX03_INPUTXBAR2              = 0x0601,
    XBAR_CLB_MUX03_CLB1_OUT5               = 0x0602,
    XBAR_CLB_MUX03_ADCCEVT2                = 0x0603,
    XBAR_CLB_MUX04_CMPSS3_CTRIPH           = 0x0800,
    XBAR_CLB_MUX04_CMPSS3_CTRIPH_OR_L      = 0x0801,
    XBAR_CLB_MUX04_ADCAEVT3                = 0x0802,
    XBAR_CLB_MUX04_ECAP3_OUT               = 0x0803,
    XBAR_CLB_MUX05_CMPSS3_CTRIPL           = 0x0A00,
    XBAR_CLB_MUX05_INPUTXBAR3              = 0x0A01,
    XBAR_CLB_MUX05_CLB2_OUT4               = 0x0A02,
    XBAR_CLB_MUX05_ADCCEVT3                = 0x0A03,
    XBAR_CLB_MUX06_CMPSS4_CTRIPH           = 0x0C00,
    XBAR_CLB_MUX06_CMPSS4_CTRIPH_OR_L      = 0x0C01,
    XBAR_CLB_MUX06_ADCAEVT4                = 0x0C02,
    XBAR_CLB_MUX07_CMPSS4_CTRIPL           = 0x0E00,
    XBAR_CLB_MUX07_INPUTXBAR4              = 0x0E01,
    XBAR_CLB_MUX07_CLB2_OUT5               = 0x0E02,
    XBAR_CLB_MUX07_ADCCEVT4                = 0x0E03,
    XBAR_CLB_MUX08_ADCBEVT1                = 0x1002,
    XBAR_CLB_MUX09_INPUTXBAR5              = 0x1201,
    XBAR_CLB_MUX09_CLB3_OUT4               = 0x1202,
    XBAR_CLB_MUX10_ADCBEVT2                = 0x1402,
    XBAR_CLB_MUX11_INPUTXBAR6             = 0x1601,
    XBAR_CLB_MUX11_CLB3_OUT5              = 0x1602,
    XBAR_CLB_MUX12_ADCBEVT3               = 0x1802,
    XBAR_CLB_MUX13_ADCSOCA                = 0x1A01,
    XBAR_CLB_MUX13_CLB4_OUT4              = 0x1A02,
    XBAR_CLB_MUX14_ADCBEVT4               = 0x1C02,
    XBAR_CLB_MUX14_EXTSYNCOUT             = 0x1C03,
    XBAR_CLB_MUX15_ADCSOCB                = 0x1E01,
    XBAR_CLB_MUX15_CLB4_OUT5              = 0x1E02,
    XBAR_CLB_MUX16_SD1FLT1_COMPH          = 0x2000,
    XBAR_CLB_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001,
    XBAR_CLB_MUX16_SD1FLT1_COMPZ          = 0x2002,
    XBAR_CLB_MUX16_SD1FLT1_DRINT          = 0x2003,
    XBAR_CLB_MUX17_SD1FLT1_COMPL          = 0x2200,
    XBAR_CLB_MUX17_INPUTXBAR7             = 0x2201,
    XBAR_CLB_MUX17_CLAHALT                = 0x2203,
    XBAR_CLB_MUX18_SD1FLT2_COMPH          = 0x2400,
    XBAR_CLB_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401,
    XBAR_CLB_MUX18_SD1FLT2_COMPZ          = 0x2402,
    XBAR_CLB_MUX18_SD1FLT2_DRINT          = 0x2403,
    XBAR_CLB_MUX19_SD1FLT2_COMPL          = 0x2600,
    XBAR_CLB_MUX19_INPUTXBAR8             = 0x2601,
    XBAR_CLB_MUX19_ERRORSTS               = 0x2603,
    XBAR_CLB_MUX20_SD1FLT3_COMPH          = 0x2800,
    XBAR_CLB_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801,
    XBAR_CLB_MUX20_SD1FLT3_COMPZ          = 0x2802,
    XBAR_CLB_MUX20_SD1FLT3_DRINT          = 0x2803,
    XBAR_CLB_MUX21_SD1FLT3_COMPL          = 0x2A00,
    XBAR_CLB_MUX21_INPUTXBAR9             = 0x2A01,
    XBAR_CLB_MUX22_SD1FLT4_COMPH          = 0x2C00,
    XBAR_CLB_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01,
    XBAR_CLB_MUX22_SD1FLT4_COMPZ          = 0x2C02,
    XBAR_CLB_MUX22_SD1FLT4_DRINT          = 0x2C03,
    XBAR_CLB_MUX23_SD1FLT4_COMPL          = 0x2E00,
    XBAR_CLB_MUX23_INPUTXBAR10            = 0x2E01,
    XBAR_CLB_MUX24_SD2FLT1_COMPH          = 0x3000,
    XBAR_CLB_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001,
    XBAR_CLB_MUX24_SD2FLT1_COMPZ          = 0x3002,
    XBAR_CLB_MUX24_SD2FLT1_DRINT          = 0x3003,
    XBAR_CLB_MUX25_SD2FLT1_COMPL          = 0x3200,
    XBAR_CLB_MUX25_INPUTXBAR11            = 0x3201,
    XBAR_CLB_MUX25_MCAN_FEVT0             = 0x3202,
    XBAR_CLB_MUX26_SD2FLT2_COMPH          = 0x3400,
    XBAR_CLB_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401,
    XBAR_CLB_MUX26_SD2FLT2_COMPZ          = 0x3402,
    XBAR_CLB_MUX26_SD2FLT2_DRINT          = 0x3403,
    XBAR_CLB_MUX27_SD2FLT2_COMPL          = 0x3600,
    XBAR_CLB_MUX27_INPUTXBAR12            = 0x3601,
    XBAR_CLB_MUX27_MCAN_FEVT1             = 0x3602,
    XBAR_CLB_MUX28_SD2FLT3_COMPH          = 0x3800,
    XBAR_CLB_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801,
    XBAR_CLB_MUX28_SD2FLT3_COMPZ          = 0x3802,
    XBAR_CLB_MUX28_SD2FLT3_DRINT          = 0x3803,
    XBAR_CLB_MUX29_SD2FLT3_COMPL          = 0x3A00,
    XBAR_CLB_MUX29_INPUTXBAR13            = 0x3A01,
    XBAR_CLB_MUX29_MCAN_FEVT2             = 0x3A02,
    XBAR_CLB_MUX30_SD2FLT4_COMPH          = 0x3C00,
    XBAR_CLB_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01,
    XBAR_CLB_MUX30_SD2FLT4_COMPZ          = 0x3C02,
    XBAR_CLB_MUX30_SD2FLT4_DRINT          = 0x3C03,
    XBAR_CLB_MUX31_SD2FLT4_COMPL          = 0x3E00,
    XBAR_CLB_MUX31_ERRORSTS               = 0x3E02,
    XBAR_CLB_MUX31_INPUTXBAR14             = 0x3E01
} XBAR_CLBMuxConfig;

//*****************************************************************************
//
//! The following values define the \e inputFlag parameter for
//! XBAR_getInputFlagStatus() and XBAR_clearInputFlag().
//
//*****************************************************************************
typedef enum
{
    //
    // XBARFLG1
    //
    XBAR_INPUT_FLG_CMPSS1_CTRIPL    = 0x0000,
    XBAR_INPUT_FLG_CMPSS1_CTRIPH    = 0x0001,
    XBAR_INPUT_FLG_CMPSS2_CTRIPL    = 0x0002,
    XBAR_INPUT_FLG_CMPSS2_CTRIPH    = 0x0003,
    XBAR_INPUT_FLG_CMPSS3_CTRIPL    = 0x0004,
    XBAR_INPUT_FLG_CMPSS3_CTRIPH    = 0x0005,
    XBAR_INPUT_FLG_CMPSS4_CTRIPL    = 0x0006,
    XBAR_INPUT_FLG_CMPSS4_CTRIPH    = 0x0007,
    XBAR_INPUT_FLG_CMPSS1_CTRIPOUTL = 0x0010,
    XBAR_INPUT_FLG_CMPSS1_CTRIPOUTH = 0x0011,
    XBAR_INPUT_FLG_CMPSS2_CTRIPOUTL = 0x0012,
    XBAR_INPUT_FLG_CMPSS2_CTRIPOUTH = 0x0013,
    XBAR_INPUT_FLG_CMPSS3_CTRIPOUTL = 0x0014,
    XBAR_INPUT_FLG_CMPSS3_CTRIPOUTH = 0x0015,
    XBAR_INPUT_FLG_CMPSS4_CTRIPOUTL = 0x0016,
    XBAR_INPUT_FLG_CMPSS4_CTRIPOUTH = 0x0017,
    //
    // XBARFLG2
    //
    XBAR_INPUT_FLG_INPUT1           = 0x0100,
    XBAR_INPUT_FLG_INPUT2           = 0x0101,
    XBAR_INPUT_FLG_INPUT3           = 0x0102,
    XBAR_INPUT_FLG_INPUT4           = 0x0103,
    XBAR_INPUT_FLG_INPUT5           = 0x0104,
    XBAR_INPUT_FLG_INPUT6           = 0x0105,
    XBAR_INPUT_FLG_ADCSOCA          = 0x0106,
    XBAR_INPUT_FLG_ADCSOCB          = 0x0107,
    XBAR_INPUT_FLG_INPUT7           = 0x0108,
    XBAR_INPUT_FLG_INPUT8           = 0x0109,
    XBAR_INPUT_FLG_INPUT9           = 0x010A,
    XBAR_INPUT_FLG_INPUT10          = 0x010B,
    XBAR_INPUT_FLG_INPUT11          = 0x010C,
    XBAR_INPUT_FLG_INPUT12          = 0x010D,
    XBAR_INPUT_FLG_INPUT13          = 0x010E,
    XBAR_INPUT_FLG_INPUT14          = 0x010F,
    XBAR_INPUT_FLG_ECAP1_OUT        = 0x0110,
    XBAR_INPUT_FLG_ECAP2_OUT        = 0x0111,
    XBAR_INPUT_FLG_ECAP3_OUT        = 0x0112,
    XBAR_INPUT_FLG_EXTSYNCOUT       = 0x0116,
    XBAR_INPUT_FLG_ADCAEVT1         = 0x0117,
    XBAR_INPUT_FLG_ADCAEVT2         = 0x0118,
    XBAR_INPUT_FLG_ADCAEVT3         = 0x0119,
    XBAR_INPUT_FLG_ADCAEVT4         = 0x011A,
    XBAR_INPUT_FLG_ADCCEVT1         = 0x011F,
    //
    // XBARFLG3
    //
    XBAR_INPUT_FLG_ADCCEVT2         = 0x0200,
    XBAR_INPUT_FLG_ADCCEVT3         = 0x0201,
    XBAR_INPUT_FLG_ADCCEVT4         = 0x0202,
    XBAR_INPUT_FLG_SD1FLT1_COMPL    = 0x0207,
    XBAR_INPUT_FLG_SD1FLT1_COMPH    = 0x0208,
    XBAR_INPUT_FLG_SD1FLT2_COMPL    = 0x0209,
    XBAR_INPUT_FLG_SD1FLT2_COMPH    = 0x020A,
    XBAR_INPUT_FLG_SD1FLT3_COMPL    = 0x020B,
    XBAR_INPUT_FLG_SD1FLT3_COMPH    = 0x020C,
    XBAR_INPUT_FLG_SD1FLT4_COMPL    = 0x020D,
    XBAR_INPUT_FLG_SD1FLT4_COMPH    = 0x020E,
    XBAR_INPUT_FLG_SD2FLT1_COMPL    = 0x020F,
    XBAR_INPUT_FLG_SD2FLT1_COMPH    = 0x0210,
    XBAR_INPUT_FLG_SD2FLT2_COMPL    = 0x0211,
    XBAR_INPUT_FLG_SD2FLT2_COMPH    = 0x0212,
    XBAR_INPUT_FLG_SD2FLT3_COMPL    = 0x0213,
    XBAR_INPUT_FLG_SD2FLT3_COMPH    = 0x0214,
    XBAR_INPUT_FLG_SD2FLT4_COMPL    = 0x0215,
    XBAR_INPUT_FLG_SD2FLT4_COMPH    = 0x0216,
    XBAR_INPUT_FLG_SD1FLT1_COMPZ    = 0x0218,
    XBAR_INPUT_FLG_SD1FLT1_DRINT    = 0x0219,
    XBAR_INPUT_FLG_SD1FLT2_COMPZ    = 0x021A,
    XBAR_INPUT_FLG_SD1FLT2_DRINT    = 0x021B,
    XBAR_INPUT_FLG_SD1FLT3_COMPZ    = 0x021C,
    XBAR_INPUT_FLG_SD1FLT3_DRINT    = 0x021D,
    XBAR_INPUT_FLG_SD1FLT4_COMPZ    = 0x021E,
    XBAR_INPUT_FLG_SD1FLT4_DRINT    = 0x021F,
    //
    // XBARFLG4
    //
    XBAR_INPUT_FLG_SD2FLT1_COMPZ    = 0x0300,
    XBAR_INPUT_FLG_SD2FLT1_DRINT    = 0x0301,
    XBAR_INPUT_FLG_SD2FLT2_COMPZ    = 0x0302,
    XBAR_INPUT_FLG_SD2FLT2_DRINT    = 0x0303,
    XBAR_INPUT_FLG_SD2FLT3_COMPZ    = 0x0304,
    XBAR_INPUT_FLG_SD2FLT3_DRINT    = 0x0305,
    XBAR_INPUT_FLG_SD2FLT4_COMPZ    = 0x0306,
    XBAR_INPUT_FLG_SD2FLT4_DRINT    = 0x0307,
    XBAR_INPUT_FLG_EMAC_PPS0        = 0x0308,
    XBAR_INPUT_FLG_MCANA_FEVT0      = 0x0309,
    XBAR_INPUT_FLG_MCANA_FEVT1      = 0x030A,
    XBAR_INPUT_FLG_MCANA_FEVT2      = 0x030B,
    XBAR_INPUT_FLG_CLB1_OUT4        = 0x0310,
    XBAR_INPUT_FLG_CLB1_OUT5        = 0x0311,
    XBAR_INPUT_FLG_CLB2_OUT4        = 0x0312,
    XBAR_INPUT_FLG_CLB2_OUT5        = 0x0313,
    XBAR_INPUT_FLG_CLB3_OUT4        = 0x0314,
    XBAR_INPUT_FLG_CLB3_OUT5        = 0x0315,
    XBAR_INPUT_FLG_CLB4_OUT4        = 0x0316,
    XBAR_INPUT_FLG_CLB4_OUT5        = 0x0317,
    XBAR_INPUT_FLG_ERRORSTS_ERROR   = 0x031C,
    XBAR_INPUT_FLG_CLAHALT          = 0x031F
} XBAR_InputFlag;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a X-BAR base address.
//!
//! \param base is the base address of the X-BAR.
//!
//! This function determines if a X-BAR base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the Output X-BAR mux values to be passed to the output signal.
//!
//! \param base specifies the X-BAR Enable register base address.
//! \param output is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be enabled.
//!
//! This function enables the mux values to be passed to the X-BAR output
//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is
//! the output number between 1 and 8 inclusive.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! The \e muxes parameter is a bit field of the muxes being enabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be OR'd together to enable several
//! muxes on an output at the same time. For example, passing this function
//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_enableOutputMux(uint32_t base, XBAR_OutputNum output, uint32_t muxes)
{
    uint16_t outputNum = (uint16_t)output;
    //
    // Check the arguments.
    //
    ;

    //
    // Set the enable bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(base + 0x20U + outputNum)))) |= muxes;

    __edis();
}

//*****************************************************************************
//
//! Disables the Output X-BAR mux values from being passed to the output.
//!
//! \param base specifies the X-BAR Enable Register base address.
//! \param output is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be disabled.
//!
//! This function disables the mux values from being passed to the X-BAR output
//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is
//! the output number between 1 and 8 inclusive.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! The \e muxes parameter is a bit field of the muxes being disabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be OR'd together to disable several
//! muxes on an output at the same time. For example, passing this function
//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would disable muxes 4 and 10.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_disableOutputMux(uint32_t base, XBAR_OutputNum output, uint32_t muxes)
{
    uint16_t outputNum = (uint16_t)output;

    //
    // Check the arguments.
    //
    ;

    //
    // Clear the enable bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(base + 0x20U + outputNum)))) &= ~(muxes);

    __edis();
}

//*****************************************************************************
//
//! Enables or disables the output latch to drive the selected output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! \param enable is a flag that determines whether or not the latch is
//! selected to drive the X-BAR output.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function sets the Output X-BAR output signal latch mode. If the
//! \e enable parameter is \b true, the output specified by \e output will be
//! driven by the output latch.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_setOutputLatchMode(uint32_t base, XBAR_OutputNum output, _Bool enable)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set or clear the latch setting bit based on the enable parameter.
    //
    if(enable)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x36U)))) |=
               0x1U << ((uint16_t)output / 2U);
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x36U)))) &=
               ~(0x1U << ((uint16_t)output / 2U));
    }

    __edis();
}

//*****************************************************************************
//
//! Returns the status of the output latch
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being checked.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! \return Returns \b true if the output corresponding to \e output was
//! triggered. If not, it will return \b false.
//
//*****************************************************************************
static inline _Bool
XBAR_getOutputLatchStatus(uint32_t base, XBAR_OutputNum output)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the status of the Output X-BAR output latch.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x30U)))) &
            (0x1U << ((uint16_t)output / 2U))) != 0U);
}

//*****************************************************************************
//
//! Clears the output latch for the specified output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function clears the Output X-BAR output latch. The output to be
//! configured is specified by the \e output parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_clearOutputLatch(uint32_t base, XBAR_OutputNum output)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that clears the corresponding OUTPUTLATCH bit.
    //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x32U)))) |=
        0x1U << ((uint16_t)output / 2U);
}

//*****************************************************************************
//
//! Forces the output latch for the specified output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function forces the Output X-BAR output latch. The output to be
//! configured is specified by the \e output parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_forceOutputLatch(uint32_t base, XBAR_OutputNum output)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that forces the corresponding OUTPUTLATCH bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) =
        0x1U << ((uint16_t)output / 2U);
}

//*****************************************************************************
//
//! Configures the polarity of an Output X-BAR output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! \param invert is a flag that determines whether the output is active-high
//! or active-low.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function inverts the Output X-BAR signal if the \e invert parameter is
//! \b true. If \e invert is \b false, the signal will be passed as is. The
//! \e output parameter is a value \b XBAR_OUTPUTy where y is the output
//! number between 1 and 8 inclusive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_invertOutputSignal(uint32_t base, XBAR_OutputNum output, _Bool invert)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set or clear the polarity setting bit based on the invert parameter.
    //
    __eallow();

    if(invert)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x38U)))) |=
            0x1U << ((uint16_t)output / 2U);
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x38U)))) &=
            ~(0x1U << ((uint16_t)output / 2U));
    }

    __edis();
}

//*****************************************************************************
//
//! Enables the ePWM X-BAR mux values to be passed to an ePWM module.
//!
//! \param trip is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be enabled.
//!
//! This function enables the mux values to be passed to the X-BAR trip
//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is
//! the number of the trip signal on the ePWM.
//!
//! The \e muxes parameter is a bit field of the muxes being enabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! enable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_enableEPWMMux(XBAR_TripNum trip, uint32_t muxes)
{
    //
    // Set the enable bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)((0x00007A00U + 0x20U) + (uint16_t)trip)))) |= muxes;

    __edis();
}

//*****************************************************************************
//
//! Disables the ePWM X-BAR mux values to be passed to an ePWM module.
//!
//! \param trip is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be disabled.
//!
//! This function disables the mux values to be passed to the X-BAR trip
//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is
//! the number of the trip signal on the ePWM.
//!
//! The \e muxes parameter is a bit field of the muxes being disabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! disable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_disableEPWMMux(XBAR_TripNum trip, uint32_t muxes)
{
    //
    // Clear the enable bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)((0x00007A00U + 0x20U) + (uint16_t)trip)))) &= ~(muxes);

    __edis();
}

//*****************************************************************************
//
//! Configures the polarity of an ePWM X-BAR output.
//!
//! \param trip is the X-BAR output being configured.
//! \param invert is a flag that determines whether the output is active-high
//! or active-low.
//!
//! This function inverts the ePWM X-BAR trip signal if the \e invert
//! parameter is \b true. If \e invert is \b false, the signal will be passed
//! as is. The \e trip parameter is a value \b XBAR_TRIPy where y is
//! the number of the trip signal on the ePWM X-BAR that is being configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_invertEPWMSignal(XBAR_TripNum trip, _Bool invert)
{
    //
    // Set or clear the polarity setting bit based on the invert parameter.
    //
    __eallow();

    if(invert)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007A00U + 0x38U)))) |=
            0x1U << ((uint16_t)trip / 2U);
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007A00U + 0x38U)))) &=
            ~(0x1U << ((uint16_t)trip / 2U));
    }

    __edis();
}

//*****************************************************************************
//
//! Sets the GPIO / non-GPIO pin for an Input X-BAR input.
//!
//! \param base specifies the X-BAR base address.
//! \param input is the X-BAR input being configured.
//! \param pin is the identifying number of the pin.
//!
//! The \e base parameter can take base addresses
//! INPUTXBAR_BASE
//! or CLBINPUTXBAR_BASE.
//!
//! This function configures which GPIO is assigned to an Input X-BAR input.
//! The \e input parameter is a value in the form of a define \b XBAR_INPUTy
//! where y is a the input number for the Input X-BAR.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! For the other non - GPIO values:
//! 0xFFFD: '1' will be driven to the destination
//! 0xFFFE: '1' will be driven to the destination
//! 0xFFFF: '0' will be driven to the destination
//! NOTE: Pin value greater than the available number of GPIO pins on a
//! device (except 0xFFFF) will cause the destination to be driven '1'.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_setInputPin(uint32_t base, XBAR_InputNum input, uint16_t pin)
{
    //
    // Check the argument.
    //
    ;
    ;

    //
    // Write the requested pin to the appropriate input select register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U + (uint16_t)input)))) = pin;

    __edis();
}

//*****************************************************************************
//
//! Locks an input to the Input X-BAR.
//!
//! \param base specifies the X-BAR base address.
//! \param input is an input to the Input X-BAR.
//!
//! This function locks the specific input on the Input X-BAR.
//!
//! The \e base parameter can take base addresses
//! INPUTXBAR_BASE
//! or CLBINPUTXBAR_BASE .
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_lockInput(uint32_t base, XBAR_InputNum input)
{
    //
    // Check the arguments.
    //
    ;

    //
    // lock the input in the INPUTSELECTLOCK register.
    //
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0x1EU)))) =
        (uint32_t)1U << (uint16_t)input;
    __edis();
}

//*****************************************************************************
//
//! Locks the Output X-BAR.
//!
//! \param base specifies the X-BAR base address.
//! This function locks the Output X-BAR.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_lockOutput(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Lock the Output X-BAR with the OUTPUTLOCK register.
    // Write key 0x5A5A to the KEY bits and 1 to LOCK bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(base + 0x3EU)))) =
         ((uint32_t)0x5A5A << 16U) |
         (uint32_t)0x1U;

    __edis();
}

//*****************************************************************************
//
//! Locks the ePWM X-BAR.
//!
//! This function locks the ePWM X-BAR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_lockEPWM(void)
{
    //
    // Lock the ePWM X-BAR with the TRIPLOCK register.
    // Write key 0x5A5A to the KEY bits and 1 to LOCK bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x00007A00U + 0x3EU)))) =
        ((uint32_t)0x5A5A << 16U) |
        (uint32_t)0x1U;

    __edis();
}

//*****************************************************************************
//
//! Enables the CLB X-BAR mux values to be passed to an CLB module.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be enabled.
//!
//! This function enables the mux values to be passed to the X-BAR auxSignal
//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is
//! the number of the signal on the CLB.
//!
//! The \e muxes parameter is a bit field of the muxes being enabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! enable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_enableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes)
{
    //
    // Set the enable bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)((0x00007A40U + 0x20U) + (uint16_t)auxSignal)))) |= muxes;

    __edis();
}

//*****************************************************************************
//
//! Disables the CLB X-BAR mux values to be passed to an CLB module.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be disabled.
//!
//! This function disables the mux values to be passed to the X-BAR auxSignal
//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is
//! the number of the signal on the CLB.
//!
//! The \e muxes parameter is a bit field of the muxes being disabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! disable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_disableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes)
{
    //
    // Clear the enable bit.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)((0x00007A40U + 0x20U) + (uint16_t)auxSignal)))) &= ~(muxes);

    __edis();
}

//*****************************************************************************
//
//! Configures the polarity of an CLB X-BAR output.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param invert is a flag that determines whether the output is active-high
//! or active-low.
//!
//! This function inverts the CLB X-BAR auxSignal signal if the \e invert
//! parameter is \b true. If \e invert is \b false, the signal will be passed
//! as is. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is
//! the number of the signal on the CLB X-BAR that is being configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_invertCLBSignal(XBAR_AuxSigNum auxSignal, _Bool invert)
{
    //
    // Set or clear the polarity setting bit based on the invert parameter.
    //
    __eallow();

    if(invert)
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007A40U + 0x38U)))) |=
            0x1U << ((uint16_t)auxSignal / 2U);
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(0x00007A40U + 0x38U)))) &=
            ~(0x1U << ((uint16_t)auxSignal / 2U));
    }

    __edis();
}

//*****************************************************************************
//
//! Configures the Output X-BAR mux that determines the signals passed to an
//! output.
//!
//! \param base specifies the X-BAR Config Register base address.
//! \param output is the X-BAR output being configured.
//! \param muxConfig is mux configuration that specifies the signal.
//!
//! This function configures an Output X-BAR mux. This determines which
//! signal(s) should be passed through the X-BAR to a GPIO. The \e output
//! parameter is a value \b XBAR_OUTPUTy where y is a the output number
//! between 1 and 8 inclusive.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! The \e muxConfig parameter for OUTPUT XBAR is the mux configuration
//! value that specifies which signal will be passed from the mux. The
//! values have the format of \b XBAR_OUT_MUXnn_xx where the 'xx' is
//! the signal and nn is the mux number.
//!
//! The \e muxConfig parameter for the CLB OUTPUT XBAR have the similar
//! format as \b XBAR_OUT_MUXnn_xx where the 'xx' is the signal and nn is
//! the mux number.
//!
//! This function may be called for each mux of an output and their values will
//! be logically OR'd before being passed to the output signal. This means that
//! this function may be called, for example, with the argument
//! \b XBAR_OUT_MUX00_ECAP1_OUT and then with the argument
//! \b XBAR_OUT_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01
//! being logically OR'd if both are enabled. Calling the function twice for
//! the same mux on the output will result in the configuration in the second
//! call overwriting the first.
//!
//! \return None.
//
//*****************************************************************************
extern void
XBAR_setOutputMuxConfig(uint32_t base, XBAR_OutputNum output,
                        XBAR_OutputMuxConfig muxConfig);

//*****************************************************************************
//
//! Configures the ePWM X-BAR mux that determines the signals passed to an
//! ePWM module.
//!
//! \param trip is the X-BAR output being configured.
//! \param muxConfig is mux configuration that specifies the signal.
//!
//! This function configures an ePWM X-BAR mux. This determines which signal(s)
//! should be passed through the X-BAR to an ePWM module. The \e trip
//! parameter is a value \b XBAR_TRIPy where y is a the number of the trip
//! signal on the ePWM.
//!
//! The \e muxConfig parameter is the mux configuration value that specifies
//! which signal will be passed from the mux. The values have the format of
//! \b XBAR_EPWM_MUXnn_xx where the 'xx' is the signal and nn is the mux
//! number (0 through 31). The possible values are found in <tt>xbar.h</tt>
//!
//! This function may be called for each mux of an output and their values will
//! be logically OR'd before being passed to the trip signal. This means that
//! this function may be called, for example, with the argument
//! \b XBAR_EPWM_MUX00_ECAP1_OUT and then with the argument
//! \b XBAR_EPWM_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX03
//! being logically OR'd if both are enabled. Calling the function twice for
//! the same mux on the output will result in the configuration in the second
//! call overwriting the first.
//!
//! \return None.
//
//*****************************************************************************
extern void
XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig);

//*****************************************************************************
//
//! Returns the status of the input latch.
//!
//! \param inputFlag is the X-BAR input latch being checked. Values are in the
//! format of /b XBAR_INPUT_FLG_XXXX where "XXXX" is name of the signal.
//!
//! \return Returns \b true if the X-BAR input corresponding to the
//! \e inputFlag has been triggered. If not, it will return \b false.
//
//*****************************************************************************
extern _Bool
XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag);

//*****************************************************************************
//
//! Clears the input latch for the specified input latch.
//!
//! \param inputFlag is the X-BAR input latch being cleared.
//!
//! This function clears the Input X-BAR input latch. The input latch to be
//! cleared is specified by the \e inputFlag parameter.
//!
//! \return None.
//
//*****************************************************************************
extern void
XBAR_clearInputFlag(XBAR_InputFlag inputFlag);

//*****************************************************************************
//
//! Configures the CLB X-BAR mux that determines the signals passed to a
//! CLB module.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param muxConfig is mux configuration that specifies the signal.
//!
//! This function configures an CLB X-BAR mux. This determines which signal(s)
//! should be passed through the X-BAR to an CLB module. The \e auxSignal
//! parameter is a value \b XBAR_AUXSIGy where y is a the number of the
//! signal on the CLB.
//!
//! The \e muxConfig parameter is the mux configuration value that specifies
//! which signal will be passed from the mux. The values have the format of
//! \b XBAR_CLB_MUXnn_xx where the 'xx' is the signal and nn is the mux
//! number (0 through 31). The possible values are found in <tt>xbar.h</tt>
//!
//! This function may be called for each mux of an output and their values will
//! be logically OR'd before being passed to the signal. This means that
//! this function may be called, for example, with the argument
//! \b XBAR_CLB_MUX00_ECAP1_OUT and then with the argument
//! \b XBAR_CLB_MUX03_INPUTXBAR2, resulting in the values of MUX00 and MUX03
//! being logically OR'd if both are enabled. Calling the function twice for
//! the same mux on the output will result in the configuration in the second
//! call overwriting the first.
//!
//! \return None.
//
//*****************************************************************************
extern void XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal,
                                 XBAR_CLBMuxConfig muxConfig);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************


//*****************************************************************************
//
// Useful defines used within the driver functions to access gpio registers.
// Not intended for use by application code.
//
// Divide by 2 is for C28x which has word access
//
//*****************************************************************************





//*****************************************************************************
//
// Values that can be passed to GPIO_setPadConfig() as the pinType parameter
// and returned by GPIO_getPadConfig().
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to GPIO_setDirectionMode() as the \e pinIO
//! parameter and returned from GPIO_getDirectionMode().
//
//*****************************************************************************
typedef enum
{
    GPIO_DIR_MODE_IN,                   //!< Pin is a GPIO input
    GPIO_DIR_MODE_OUT                   //!< Pin is a GPIO output
} GPIO_Direction;

//*****************************************************************************
//
//! Values that can be passed to GPIO_setInterruptType() as the \e intType
//! parameter and returned from GPIO_getInterruptType().
//
//*****************************************************************************
typedef enum
{
    GPIO_INT_TYPE_FALLING_EDGE = 0x00,   //!< Interrupt on falling edge
    GPIO_INT_TYPE_RISING_EDGE  = 0x04,   //!< Interrupt on rising edge
    GPIO_INT_TYPE_BOTH_EDGES   = 0x0C    //!< Interrupt on both edges
} GPIO_IntType;

//*****************************************************************************
//
//! Values that can be passed to GPIO_setQualificationMode() as the
//! \e qualification parameter and returned by GPIO_getQualificationMode().
//
//*****************************************************************************
typedef enum
{
    GPIO_QUAL_SYNC,                     //!< Synchronization to SYSCLKOUT
    GPIO_QUAL_3SAMPLE,                  //!< Qualified with 3 samples
    GPIO_QUAL_6SAMPLE,                  //!< Qualified with 6 samples
    GPIO_QUAL_ASYNC                     //!< No synchronization
} GPIO_QualificationMode;

//*****************************************************************************
//
//! Values that can be passed to GPIO_setAnalogMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    GPIO_ANALOG_DISABLED,       //!< Pin is in digital mode
    GPIO_ANALOG_ENABLED         //!< Pin is in analog mode
} GPIO_AnalogMode;

//*****************************************************************************
//
//! Values that can be passed to GPIO_setMasterCore() as the \e core parameter.
//
//*****************************************************************************
typedef enum
{
    GPIO_CORE_CPU1,             //!< CPU1 selected as master core
    GPIO_CORE_CPU1_CLA1         //!< CPU1's CLA1 selected as master core
} GPIO_CoreSelect;

//*****************************************************************************
//
//! Values that can be passed to GPIO_readPortData(), GPIO_setPortPins(),
//! GPIO_clearPortPins(), and GPIO_togglePortPins() as the \e port parameter.
//
//*****************************************************************************
typedef enum
{
    GPIO_PORT_A = 0,                    //!< GPIO port A
    GPIO_PORT_B = 1,                    //!< GPIO port B
    GPIO_PORT_H = 7                     //!< GPIO port H
} GPIO_Port;

//*****************************************************************************
//
//! Values that can be passed to GPIO_setInterruptPin(),
//! GPIO_setInterruptType(), GPIO_getInterruptType(), GPIO_enableInterrupt(),
//! GPIO_disableInterrupt(), as the \e extIntNum parameter.
//
//*****************************************************************************
typedef enum
{
    GPIO_INT_XINT1,                     //!< External Interrupt 1
    GPIO_INT_XINT2,                     //!< External Interrupt 2
    GPIO_INT_XINT3,                     //!< External Interrupt 3
    GPIO_INT_XINT4,                     //!< External Interrupt 4
    GPIO_INT_XINT5                      //!< External Interrupt 5
} GPIO_ExternalIntNum;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks that a pin number is valid for a device.
//!
//! Note that this function reflects the highest possible GPIO number of a
//! device on its biggest package. Check the datasheet to see what the actual
//! range of valid pin numbers is for a specific package.
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets the interrupt type for the specified pin.
//!
//! \param extIntNum specifies the external interrupt.
//! \param intType specifies the type of interrupt trigger mechanism.
//!
//! This function sets up the various interrupt trigger mechanisms for the
//! specified pin on the selected GPIO port.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! One of the following flags can be used to define the \e intType
//! parameter:
//!
//! - \b GPIO_INT_TYPE_FALLING_EDGE sets detection to edge and trigger to
//!   falling
//! - \b GPIO_INT_TYPE_RISING_EDGE sets detection to edge and trigger to rising
//! - \b GPIO_INT_TYPE_BOTH_EDGES sets detection to both edges
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_setInterruptType(GPIO_ExternalIntNum extIntNum, GPIO_IntType intType)
{
    //
    // Write the selected polarity to the appropriate register.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007070U + (uint16_t)extIntNum)))) =
        ((*((volatile uint16_t *)((uintptr_t)(0x00007070U + (uint16_t)extIntNum)))) & ~0xCU) |
        (uint16_t)intType;
}

//*****************************************************************************
//
//! Gets the interrupt type for a pin.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! This function gets the interrupt type for a interrupt. The interrupt can be
//! configured as a falling-edge, rising-edge, or both-edges detected
//! interrupt.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! \return Returns one of the flags described for GPIO_setInterruptType().
//
//*****************************************************************************
static inline GPIO_IntType
GPIO_getInterruptType(GPIO_ExternalIntNum extIntNum)
{
    //
    // Read the selected polarity from the appropriate register.
    //
    return((GPIO_IntType)((*((volatile uint16_t *)((uintptr_t)(0x00007070U + (uint16_t)extIntNum)))) &
                          0xCU));
}

//*****************************************************************************
//
//! Enables the specified external interrupt.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! This function enables the indicated external interrupt sources.  Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_enableInterrupt(GPIO_ExternalIntNum extIntNum)
{
    //
    // Set the enable bit for the specified interrupt.
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007070U + (uint16_t)extIntNum)))) |= 0x1U;
}

//*****************************************************************************
//
//! Disables the specified external interrupt.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! This function disables the indicated external interrupt sources.  Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_disableInterrupt(GPIO_ExternalIntNum extIntNum)
{
    //
    // Clear the enable bit for the specified interrupt
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00007070U + (uint16_t)extIntNum)))) &= ~0x1U;
}

//*****************************************************************************
//
//! Gets the value of the external interrupt counter.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//!
//! \b Note: The counter is clocked at the SYSCLKOUT rate.
//!
//! \return Returns external interrupt counter value.
//
//*****************************************************************************
static inline uint16_t
GPIO_getInterruptCounter(GPIO_ExternalIntNum extIntNum)
{
    ;

    //
    // Read the counter value from the appropriate register.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(0x00007070U + 0x8U + (uint16_t)extIntNum))))));
}

//*****************************************************************************
//
//! Reads the value present on the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! The value at the specified pin are read, as specified by \e pin. The value
//! is returned for both input and output pins.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return Returns the value in the data register for the specified pin.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPin(uint32_t pin)
{
    volatile uint32_t *gpioDataReg;

    //
    // Check the arguments.
    //
    ;

    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((pin / 32U) * ((0x8U - 0x0U) / 2U));

    return((gpioDataReg[(0x0U / 2U)] >> (pin % 32U)) & (uint32_t)0x1U);
}

//*****************************************************************************
//
//! Reads the data register value for specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! The value available at the data register for the specified pin is read, as
//! specified by \e pin. The value is returned for both input and output pins.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \sa GPIO_readPin()
//!
//! \return Returns the value in the data register for the specified pin.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPinDataRegister(uint32_t pin)
{
    volatile uint32_t *gpioDataReg;

    //
    // Check the arguments.
    //
    ;

    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F80U) +
                  ((pin / 32U) * ((0x2U - 0x0U) / 2U));

    return((gpioDataReg[(0x0U / 2U)] >> (pin % 32U)) & (uint32_t)0x1U);
}

//*****************************************************************************
//
//! Writes a value to the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param outVal is the value to write to the pin.
//!
//! Writes the corresponding bit values to the output pin specified by
//! \e pin.  Writing to a pin configured as an input pin has no effect.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_writePin(uint32_t pin, uint32_t outVal)
{
    volatile uint32_t *gpioDataReg;
    uint32_t pinMask;

    //
    // Check the arguments.
    //
    ;

    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((pin / 32U) * ((0x8U - 0x0U) / 2U));

    pinMask = (uint32_t)1U << (pin % 32U);

    if(outVal == 0U)
    {
        gpioDataReg[(0x4U / 2U)] = pinMask;
    }
    else
    {
        gpioDataReg[(0x2U / 2U)] = pinMask;
    }
}

//*****************************************************************************
//
//! Toggles the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! Writes the corresponding bit values to the output pin specified by
//! \e pin.  Writing to a pin configured as an input pin has no effect.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_togglePin(uint32_t pin)
{
    volatile uint32_t *gpioDataReg;

    //
    // Check the arguments.
    //
    ;

    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((pin / 32U) * ((0x8U - 0x0U) / 2U));

    gpioDataReg[(0x6U / 2U)] = (uint32_t)1U << (pin % 32U);
}

//*****************************************************************************
//
//! Reads the data on the specified port.
//!
//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X
//! where X is the port letter.
//!
//! \return Returns the value available on pin for the specified port. Each
//! bit of the the return value represents a pin on the port, where bit 0
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPortData(GPIO_Port port)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and return DATA.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((uint32_t)port * ((0x8U - 0x0U) / 2U));

    return(gpioDataReg[(0x0U / 2U)]);
}

//*****************************************************************************
//
//! Reads the data written in GPIO Data Register.
//!
//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X
//! where X is the port letter.
//!
//! Reads the data written in GPIO Data Register for the specified port. In
//! previous devices, read of GPIO data registers resulted in read of
//! corespoinding pins. The function \b GPIO_readPortData() returns the value
//! on pin.
//!
//! \sa GPIO_readPortData()
//!
//! \return Returns the value in the data register for the specified port. Each
//! bit of the the return value represents a pin on the port, where bit 0
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPortDataRegister(GPIO_Port port)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and return DATA.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F80U) +
                  ((uint32_t)port * ((0x2U - 0x0U) / 2U));

    return(gpioDataReg[(0x0U / 2U)]);
}

//*****************************************************************************
//
//! Writes a value to the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param outVal is the value to write to the port.
//!
//! This function writes the value \e outVal to the port specified by the
//! \e port parameter which takes a value in the form of \b GPIO_PORT_X where X
//! is the port letter. For example, use \b GPIO_PORT_A to affect port A
//! (GPIOs 0-31).
//!
//! The \e outVal is a bit-packed value, where each bit represents a bit on a
//! GPIO port. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO port
//! pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_writePortData(GPIO_Port port, uint32_t outVal)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and write to DATA.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((uint32_t)port * ((0x8U - 0x0U) / 2U));

    gpioDataReg[(0x0U / 2U)] = outVal;
}

//*****************************************************************************
//
//! Sets all of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function sets all of the pins specified by the \e pinMask parameter on
//! the port specified by the \e port parameter which takes a value in the
//! form of \b GPIO_PORT_X where X is the port letter. For example, use
//! \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be set. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO
//! port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_setPortPins(GPIO_Port port, uint32_t pinMask)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and write to SET.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((uint32_t)port * ((0x8U - 0x0U) / 2U));

    gpioDataReg[(0x2U / 2U)] = pinMask;
}

//*****************************************************************************
//
//! Clears all of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function clears all of the pins specified by the \e pinMask parameter
//! on the port specified by the \e port parameter which takes a value in the
//! form of \b GPIO_PORT_X where X is the port letter. For example, use
//! \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is \b set
//! identifies the pin to be cleared. Bit 0 represents GPIO port pin 0, bit 1
//! represents GPIO port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_clearPortPins(GPIO_Port port, uint32_t pinMask)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and write to CLEAR.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((uint32_t)port * ((0x8U - 0x0U) / 2U));

    gpioDataReg[(0x4U / 2U)] = pinMask;
}

//*****************************************************************************
//
//! Toggles all of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function toggles all of the pins specified by the \e pinMask parameter
//! on the port specified by the \e port parameter which takes a value in the
//! form of \b GPIO_PORT_X where X is the port letter. For example, use
//! \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be toggled. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_togglePortPins(GPIO_Port port, uint32_t pinMask)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and write to TOGGLE.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
                  ((uint32_t)port * ((0x8U - 0x0U) / 2U));

    gpioDataReg[(0x6U / 2U)] = pinMask;
}

//*****************************************************************************
//
//! Locks the configuration of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function locks the configuration registers of the pins specified by
//! the \e pinMask parameter on the port specified by the \e port parameter
//! which takes a value in the form of \b GPIO_PORT_X where X is the port
//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on.
//!
//! Note that this function is for locking the configuration of a pin such as
//! the pin muxing, direction, open drain mode, and other settings. It does not
//! affect the ability to change the value of the pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_lockPortConfig(GPIO_Port port, uint32_t pinMask)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and write to the lock.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007C00U) +
                  ((uint32_t)port * ((0x40U - 0x0U) / 2U));

    __eallow();
    gpioDataReg[(0x3CU / 2U)] |= pinMask;
    __edis();
}

//*****************************************************************************
//
//! Unlocks the configuration of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function unlocks the configuration registers of the pins specified by
//! the \e pinMask parameter on the port specified by the \e port parameter
//! which takes a value in the form of \b GPIO_PORT_X where X is the port
//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be unlocked. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_unlockPortConfig(GPIO_Port port, uint32_t pinMask)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and write to the lock.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007C00U) +
                  ((uint32_t)port * ((0x40U - 0x0U) / 2U));

    __eallow();
    gpioDataReg[(0x3CU / 2U)] &= ~pinMask;
    __edis();
}

//*****************************************************************************
//
//! Commits the lock configuration of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function commits the lock configuration registers of the pins
//! specified by the \e pinMask parameter on the port specified by the \e port
//! parameter which takes a value in the form of \b GPIO_PORT_X where X is the
//! port letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on.
//!
//! Note that once this function is called, GPIO_lockPortConfig() and
//! GPIO_unlockPortConfig() will no longer have any effect on the specified
//! pins.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_commitPortConfig(GPIO_Port port, uint32_t pinMask)
{
    volatile uint32_t *gpioDataReg;

    //
    // Get the starting address of the port's registers and write to the lock.
    //
    gpioDataReg = (uint32_t *)((uintptr_t)0x00007C00U) +
                  ((uint32_t)port * ((0x40U - 0x0U) / 2U));

    __eallow();
    gpioDataReg[(0x3EU / 2U)] |= pinMask;
    __edis();
}

//*****************************************************************************
//
//! Sets the direction and mode of the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param pinIO is the pin direction mode.
//!
//! This function configures the specified pin on the selected GPIO port as
//! either input or output.
//!
//! The parameter \e pinIO is an enumerated data type that can be one of the
//! following values:
//!
//! - \b GPIO_DIR_MODE_IN
//! - \b GPIO_DIR_MODE_OUT
//!
//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as an input
//! and \b GPIO_DIR_MODE_OUT specifies that the pin is programmed as an output.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO);

//*****************************************************************************
//
//! Gets the direction mode of a pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! This function gets the direction mode for a specified pin.  The pin can be
//! configured as either an input or output The type of direction is returned
//! as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIO_setDirectionMode().
//
//*****************************************************************************
extern GPIO_Direction
GPIO_getDirectionMode(uint32_t pin);

//*****************************************************************************
//
//! Sets the pin for the specified external interrupt.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param extIntNum specifies the external interrupt.
//!
//! This function sets which pin triggers the selected external interrupt.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \sa XBAR_setInputPin()
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum);

//*****************************************************************************
//
//! Sets the pad configuration for the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param pinType specifies the pin type.
//!
//! This function sets the pin type for the specified pin. The parameter
//! \e pinType can be the following values:
//!
//! - \b GPIO_PIN_TYPE_STD specifies a push-pull output or a floating input
//! - \b GPIO_PIN_TYPE_PULLUP specifies the pull-up is enabled for an input
//! - \b GPIO_PIN_TYPE_OD specifies an open-drain output pin
//! - \b GPIO_PIN_TYPE_INVERT specifies inverted polarity on an input
//!
//! \b GPIO_PIN_TYPE_INVERT may be OR-ed with \b GPIO_PIN_TYPE_STD or
//! \b GPIO_PIN_TYPE_PULLUP.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setPadConfig(uint32_t pin, uint32_t pinType);

//*****************************************************************************
//
//! Gets the pad configuration for a pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! This function returns the pin type for the specified pin.  The value
//! returned corresponds to the values used in GPIO_setPadConfig().
//!
//! \return Returns a bit field of the values \b GPIO_PIN_TYPE_STD,
//! \b GPIO_PIN_TYPE_PULLUP, \b GPIO_PIN_TYPE_OD, and \b GPIO_PIN_TYPE_INVERT.
//
//*****************************************************************************
extern uint32_t
GPIO_getPadConfig(uint32_t pin);

//*****************************************************************************
//
//! Sets the qualification mode for the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param qualification specifies the qualification mode of the pin.
//!
//! This function sets the qualification mode for the specified pin. The
//! parameter \e qualification can be one of the following values:
//! - \b GPIO_QUAL_SYNC
//! - \b GPIO_QUAL_3SAMPLE
//! - \b GPIO_QUAL_6SAMPLE
//! - \b GPIO_QUAL_ASYNC
//!
//! To set the qualification sampling period, use
//! GPIO_setQualificationPeriod().
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification);

//*****************************************************************************
//
//! Gets the qualification type for the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! \return Returns the qualification mode in the form of one of the values
//! \b GPIO_QUAL_SYNC, \b GPIO_QUAL_3SAMPLE, \b GPIO_QUAL_6SAMPLE, or
//! \b GPIO_QUAL_ASYNC.
//
//*****************************************************************************
extern GPIO_QualificationMode
GPIO_getQualificationMode(uint32_t pin);

//*****************************************************************************
//
//! Sets the qualification period for a set of pins
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param divider specifies the output drive strength.
//!
//! This function sets the qualification period for a set of \b 8 \b pins,
//! specified by the \e pin parameter. For instance, passing in 3 as the value
//! of \e pin will set the qualification period for GPIO0 through GPIO7, and a
//! value of 98 will set the qualification period for GPIO96 through GPIO103.
//! This is because the register field that configures the divider is shared.
//!
//! To think of this in terms of an equation, configuring \e pin as \b n will
//! configure GPIO (n & ~(7)) through GPIO ((n & ~(7)) + 7).
//!
//! \e divider is the value by which the frequency of SYSCLKOUT is divided. It
//! can be 1 or an even value between 2 and 510 inclusive.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider);

//*****************************************************************************
//
//! Selects the master core of a specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param core is the core that is master of the specified pin.
//!
//! This function configures which core owns the specified pin's data registers
//! (DATA, SET, CLEAR, and TOGGLE). The \e core parameter is an enumerated data
//! type that specifies the core, such as \b GPIO_CORE_CPU1_CLA1 to make CPU1's
//! CLA1 master of the pin.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setMasterCore(uint32_t pin, GPIO_CoreSelect core);

//*****************************************************************************
//
//! Sets the analog mode of the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param mode is the selected analog mode.
//!
//! This function configures the specified pin for either analog or digital
//! mode. Not all GPIO pins have the ability to be switched to analog mode,
//! so refer to the technical reference manual for details. This setting should
//! be thought of as another level of muxing.
//!
//! The parameter \e mode is an enumerated data type that can be one of the
//! following values:
//!
//! - \b GPIO_ANALOG_DISABLED - Pin is in digital mode
//! - \b GPIO_ANALOG_ENABLED - Pin is in analog mode
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode);

//*****************************************************************************
//
//! Configures the alternate function of a GPIO pin.
//!
//! \param pinConfig is the pin configuration value, specified as only one
//! of the \b GPIO_#_???? values.
//!
//! This function configures the pin mux that selects the peripheral function
//! associated with a particular GPIO pin.  Only one peripheral function at a
//! time can be associated with a GPIO pin, and each peripheral function should
//! only be associated with a single GPIO pin at a time (despite the fact that
//! many of them can be associated with more than one GPIO pin).
//!
//! The available mappings are supplied in <tt>pin_map.h</tt>.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setPinConfig(uint32_t pinConfig);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   hic.h
//
// TITLE:  C28x Host Interface Controller (HIC) driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup hic_api HIC
//! \brief This module is used for Host Interface Controller(HIC) configuration
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE:    hw_hic.h
//
// TITLE:   Definitions for the HIC registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the HIC register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the HICREV register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICGCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICMODECR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICPINPOLCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICBASESEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICHOSTCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICERRADDR register
//
//*************************************************************************************************
                                                   // error for Device
                                                   // error for Host

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR5 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR6 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR7 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HICCOMMIT register
//
//*************************************************************************************************




//
//Generic defines
//

//
//Number of Regions of Base addresses supported in HIC module
//

//
//Number of Device to Host and Host to Device Buffer Registers of the module
//


//
//Used in HIC_enableHostInterface() API
//

//
//Used in HIC_enableLock() and HIC_disableLock() APIs
//

//
//Flag for Unlocking in LOCK register
//

//*****************************************************************************
//
//! Values that can be passed to HIC_setConfig() as \e flags or
//! used with HIC_getConfig() API return value parsing
//
//*****************************************************************************
//
//Enumerations for HICMODECR Register
//

//
//For Read/Write Pin
//

//
//For Byte Enable BEn Pins
//

//
//For Ready nRDY Pin
//

//
//For Host to Device Buffer Device Write Enable
//

//
//For Device to Host Buffer Host Write Enable
//

//
//For Enabling Host Access to Device Region
//

//
//For Enabling Host Write to EALLOWCTL Register
//

//*****************************************************************************
//
//! Values that can be passed to HIC_setPinPolarity() API as \e flags or
//! used with HIC_getPinPolarity() API return value parsing
//
//*****************************************************************************
//
//For Pin Polarity Configuration
//Chip Select Pin (CS)
//

//
// Byte Enable Pin
//

//
// Output Enable OE Pin
//

//
// Write Enable (WE) Pin Polarity
//

//
// Ready Pin( RDY) Polarity
//

//*****************************************************************************
//
//! Values that can be passed to HIC_configureHostAccessMode() API as \e config
//! or used with HIC_getHostAccessMode() API return value parsing
//
//*****************************************************************************
//
//Host Control Register
//
//
//Access size of MMR registers
//
//
//Page selection via Pin/BASESEL Register
//

//*****************************************************************************
//
//! Values that can be passed to HIC_enableD2HInterrupt() API or
//! or used with HIC_disableD2HInterrupt() API to enable/disable interrupt
//! or with HIC_clearD2HInterrupt() API to clear interrupt
//
//*****************************************************************************
//
//SOC Internal Event Trigger (EVTTRIG)
//Refer Device TRM for details of the event(s)
//

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Returns the Revision of HIC Controller interface.
//!
//! This function returns the hardware revision of the Host Interface
//! controller module
//!
//! \return The Hardware Version number
//!         returns the content of HICREV register. Please refer to device TRM
//!         for field wise details.
//
//*****************************************************************************
static inline uint32_t
HIC_getRevision(void)
{
    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x0U)))));
}

//*****************************************************************************
//
//! Enables the Host Access to the Device region and to the Mailbox
//!
//! \return none
//!
//! \n The Host interface Controller module provides two mechanisms of access
//! 1. Using Device Memory access, the host can access the memory directly
//!    read/write/poll for registers
//! 2. Using the Mailbox mechanism which can be used when the Host can write
//!     the parameters to the mailbox Host-to-Device buffer region and then
//!     trigger an interrupt to the Device. The HIC module with the
//!     other application running on device side can then be used
//!    to signal to the host, using the Device-to-Host buffer region
//! in response.
//!  This API enables the access to the Device region and Mailbox.
//!  This should be used as the first API in sequence of configuring
//! the HIC module.
//
//*****************************************************************************
static inline void
HIC_enableHostInterface(void)
{
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x2U)))) = 0x0AU;
    __edis();
}

//*****************************************************************************
//
//! Enables the Lock for the HIC module registers protected by Writes
//!
//! \n This API enables the lock, which protects the writes to registers
//! protected by Lock. Calling this API prevents writes to the write protected
//! registers.
//!
//! \return none
//
//*****************************************************************************
static inline void
HIC_enableLock(void)
{
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x4U)))) = (0x1U |
                                 ((uint32_t)0x5A5AU <<
                                  16U));
    __edis();
}

//*****************************************************************************
//
//! Disables the Lock for the HIC module registers protected by Writes
//!
//! \n This API disables the lock(unlocks), which enables the writes
//!  to registers protected by Lock.
//! Calling this API enables writes to the write protected
//! registers.
//! This API must be called one time before calling any of these APIs
//! - HIC_setConfig()
//! - HIC_setPinPolarity()
//! - HIC_selectBaseAddress()
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_disableLock(void)
{

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x4U)))) = (0x0U |
                                 ((uint32_t)0x5A5AU <<
                                  16U));
    __edis();
}

//*****************************************************************************
//
//! Sets the Host Interface Controller Configurations
//! \n This API configures the HICMODECR register for the selected configuration
//! HIC_disableLock() API should have been called prior to this API.
//!
//! \param flags specifies the ORed values of any of following flags.
//!
//! Any one of following values for Data Width
//! - \b HIC_MODE_DW_8BIT    -for 8bit Data
//! - \b HIC_MODE_DW_16BIT   -for 16bit Data
//! - \b HIC_MODE_DW_32BIT   -for 32bit Data
//!
//! Any one of following values for Read Write Pin
//! - \b HIC_MODE_RW_PIN_SEPARATE   - for Separate Read and Write Pin
//! - \b HIC_MODE_RW_PIN_SINGLE     - for Same Read and Write Pin
//!
//! Any one of following values for Byte Enable Pin configuration
//! - \b HIC_MODE_BEN_PRESENT   - for using Byte Enable Pin
//! - \b HIC_MODE_BEN_ABSENT    - for not using Byte Enable Pin
//!
//! Any one of following values for Ready Pin
//! - \b HIC_MODE_RDY_PRESENT   - for using Ready Pin for extended wait
//! - \b HIC_MODE_RDY_ABSENT    - for not using Extended Wait pin
//!
//! Other configurations:
//! - \b HIC_MODE_H2DBUF_DEVWREN    - for enabling Device access to
//! host to Device Buffers. If this is not enabled the device cannot write to
//! Host to Device buffers
//! - \b HIC_MODE_D2HBUF_HOST_WR_ENABLE - for enabling host access to
//! device to host buffers. If this is not enabled the host cannot write to
//! device to host buffers.
//! - \b HIC_MODE_DEVICE_HOST_ACCESS_ENABLE - for enabling access to the device
//! region. Only if this is enabled the regions selected by
//! Base select registers using the HIC_selectBaseAddress() API
//! shall be accessible.
//! Without this only the HIC registers and Mailbox registers will be
//! accessible for the host.
//! - \b HIC_MODE_HOST_WREALLOW_ENABLE - for enabling host access to write to
//! EALLOW bitfield using HIC_configureHostAccessMode() API. Without enabling
//! this HIC_configureHostAccessMode(HIC_HOSTCR_EALLOW_EN)
//!  will not work.

//
//! \return None
//
//*****************************************************************************
static inline void
HIC_setConfig(uint32_t flags)
{
    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x6U)))) = flags;
    __edis();
}

//*****************************************************************************
//
//! Returns the Host Interface Controller Configurations
//!
//! \return
//! 32-bit integer specifies the ORed values of following flags
//! Any one of following values for Data Width
//! - \b HIC_MODE_DW_8BIT    -for 8bit Data
//! - \b HIC_MODE_DW_16BIT   -for 16bit Data
//! - \b HIC_MODE_DW_32BIT   -for 32bit Data
//!
//! Following values for Other Configurations
//! - \b HIC_MODE_RW_PIN_SEPARATE/ HIC_MODE_RW_PIN_SINGLE  - for Read/Write Pin
//! - \b HIC_MODE_BEN_PRESENT/HIC_MODE_BEN_ABSENT  - for Byte Enable Pin Usage
//! - \b HIC_MODE_RDY_PRESENT/HIC_MODE_RDY_ABSENT  - for using Ready Pin for
//!  extended wait
//! - \b HIC_MODE_H2DBUF_DEVWREN- Device access to Host to Device Buffer Enabled
//! - \b HIC_MODE_D2HBUF_HOST_WR_ENABLE - Host access to Device to Host Buffer
//! enabled
//! - \b HIC_MODE_DEVICE_HOST_ACCESS_ENABLE - for enabling access to the device
//! - \b HIC_MODE_HOST_WREALLOW_ENABLE - for host access to write to EALLOW
//!
//! This API returns the current configuration of HIC module.
//! It can be used along with macros defined in hw_hic.h as below.
//! For querying the Data width use like in below examples
//! \n HIC_getConfig() & HIC_MODECR_DW_MODE_M == HIC_MODE_DW_8BIT for Data width
//! \n HIC_getConfig() & HIC_MODECR_RW_MODE == HIC_MODE_RW_PIN_SINGLE for RW Pin
//! \n HIC_getConfig() & HIC_MODECR_BEN_PRESENT == HIC_MODE_BEN_PRESENT
//! for BE Pin
//
//*****************************************************************************
static inline uint32_t
HIC_getConfig(void)
{

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x6U)))));
}

//*****************************************************************************
//
//! Sets the Host Interface Controller Pin Polarity.
//! This API configures the HICPINPOLCR register for the selected configuration.
//! HIC_disableLock() API should have been called prior to this API.
//!
//! \param flags specifies the ORed values of any of following flags
//!
//! Any one of following values for Chip Select Pin
//! - \b HIC_PIN_POLARITY_CS_HIGH   - for Active High Chip Select Pin
//! - \b HIC_PIN_POLARITY_CS_LOW    - for Active Low Chip Select Pin
//!
//! Any one of following values for Byte Enable Pin configuration
//! - \b HIC_PIN_POLARITY_BEN_HIGH   - for Active High Byte Enable
//! - \b HIC_PIN_POLARITY_BEN_LOW    - for Active Low Byte Enable
//!
//! Any one of following values for Output Enable Pin
//! - \b HIC_PIN_POLARITY_OE_HIGH   - for Active High Output Enable
//! - \b HIC_PIN_POLARITY_OE_LOW    - for Active Low Output Enable
//!
//! Any one of following values for Write Enable Pin
//! - \b HIC_PIN_POLARITY_WE_HIGH   - for Active High Write Enable
//! - \b HIC_PIN_POLARITY_WE_LOW    - for Active Low Write Enable
//!
//! Any one of following values for Ready Pin
//! - \b HIC_PIN_POLARITY_RDY_HIGH   - for Active High Write Enable
//! - \b HIC_PIN_POLARITY_RDY_LOW    - for Active Low Write Enable
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_setPinPolarity(uint16_t flags)
{

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x8U)))) = flags;
    __edis();
}

//*****************************************************************************
//
//! Returns the Host Interface Controller Pin Polarity Configurations
//!
//! This API returns the HICPINPOLCR register for the selected configuration
//!
//! \return
//! 32-bit integer specifies the ORed values of any of following flags
//! Following values for corresponding Pin Configuration
//! - \b HIC_PIN_POLARITY_CS_HIGH/ HIC_PIN_POLARITY_CS_HIGH  - for CS Pin
//! - \b HIC_PIN_POLARITY_BEN_HIGH/HIC_PIN_POLARITY_BEN_HIGH- for
//!    Byte Enable pin
//! - \b HIC_PIN_POLARITY_OE_HIGH/HIC_PIN_POLARITY_OE_LOW  - for OE Pin
//! - \b HIC_PIN_POLARITY_WE_HIGH/HIC_PIN_POLARITY_WE_LOW- for WE Pin
//! - \b HIC_PIN_POLARITY_RDY_HIGH/HIC_PIN_POLARITY_RDY_LOW - for RDY Pin
//!
//! This API returns the Pin Polarity.This can be used with the macros defined
//! in hw_hic.h as shown below
//! HIC_getPinPolarity & HIC_PINPOLCR_BEN_POL == HIC_PIN_POLARITY_BEN_HIGH for
//!   checking the status of Byte Enable Pin Polarity
//
//*****************************************************************************
static inline uint32_t
HIC_getPinPolarity(void)
{

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x8U)))));
}

//*****************************************************************************
//
//! Selects the Base Address for the device memory access
//!
//! \param selectIndex specifies the index of Base address in the Base Address
//!        regions can vary from 0 to HIC_NUM_BASE_ADDRESS-1
//!
//! The Device memory region will be accessible by the region selected in this
//! API. Also look at HIC_configureHostAccessMode(HIC_HOSTCR_PAGESEL)
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_selectBaseAddress(uint16_t selectIndex)
{
    //
    //Check the arguments.
    //
    ;

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0xAU)))) = selectIndex;
}

//*****************************************************************************
//
//! Returns the Selected Base address index for the device memory access
//!
//! The Device memory region will be accessible by the region selected in this
//! API. Also look at HIC_configureHostAccessMode(HIC_HOSTCR_PAGESEL)
//!
//! \return selected index of Base address in the Base Address
//!         regions. can vary from 0 to HIC_NUM_BASE_ADDRESS-1
//
//*****************************************************************************
static inline uint16_t
HIC_getSelectedBaseAddressIndex(void)
{
    return((*((volatile uint16_t *)((uintptr_t)(0x00006500U + 0xAU)))));
}

//*****************************************************************************
//
//! Configures the Host Access modes to the device region
//!
//! \param config logical OR of the following values
//! - \b HIC_HOSTCR_EALLOW_EN for enabling module writes to EALLOW Protected
//!      registers
//! - either of
//! <b>HIC_HOST_CONTROL_ACCSIZE_16BIT/HIC_HOST_CONTROL_ACCSIZE_32BIT </b>
//!    to select 16 bit or 32 bit device side master port accesses
//! - either of
//! <b> HIC_HOST_CONTROL_PAGESEL_REG/HIC_HOST_CONTROL_PAGESEL_PIN </b>
//!    to select Page/Region selection based on PAGESEL register
//!    programmed using HIC_selectBaseAddress()API or the PAGESEL Pin
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_configureHostAccessMode(uint16_t config)
{

    //
    //Needs a key to be written for the write to go through
    //
    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0xCU)))) = (config |
                                    0xA5U <<
                                    8U);
}

//*****************************************************************************
//
//! Provides the Host Access modes configured currently
//!
//! \return Host Access mode value as configured
//!         HIC_configureHostAccessMode()
//!  API which is a logical OR of
//! - \b HIC_HOSTCR_EALLOW_EN for enabling module writes to EALLOW Protected
//!      registers
//! - either of
//! <b> HIC_HOST_CONTROL_ACCSIZE_16BIT/HIC_HOST_CONTROL_ACCSIZE_32BIT </b>
//!    for selected 16 bit or 32 bit device side master port accesses
//! - either of
//! <b> HIC_HOST_CONTROL_PAGESEL_REG/HIC_HOST_CONTROL_PAGESEL_PIN </b>
//!    for selected Page/Region selection based on PAGESEL register
//!     programmed using HIC_selectBaseAddress()API or the PAGESEL Pin
//!
//! This API can be used with few Macros defined in hw_hic.h as below
//! (HIC_getAccessMode() & HIC_HOSTCR_ACCSIZE) == HIC_HOST_CONTROL_ACCSIZE_32BIT
//! for Access size checking. Similarly it can be used for other bit fields.
//
//*****************************************************************************
static inline uint32_t
HIC_getHostAccessMode(void)
{

    //
    //Returns the lower 16 bits that contains the configuration
    //
    return((*((volatile uint16_t *)((uintptr_t)(0x00006500U + 0xCU)))));
}

//*****************************************************************************
//
//! Returns the Host and Device side Status when an Error happened on interface
//!
//! \return returns the logical OR of the following
//! - 8 bit Host to Device Error Address when Host to Device Error happens
//! - 3 bit Base select value when Host to Device Error happens
//! - 8 bit Device to Host Error Address when Device to Host Error happens
//! - 3 bit Base select value when Device to Host Error Happens.
//! \n Please refer to TRM HICERRADDR register for more details on this.
//
//*****************************************************************************
static inline uint32_t
HIC_getErrorAddress(void)
{
    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0xEU)))));
}

//*****************************************************************************
//
//! Returns the token written by the token written onto the Host to Device Token
//!
//! \return the 32 bit Token value written into the register
//!
//! This API can be used while using the Mailbox mechanism.
//
//*****************************************************************************
static inline uint32_t
HIC_getH2DToken(void)
{

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x10U)))));
}

//*****************************************************************************
//
//! Writes the Token to the Host from Device
//!
//! \param token is the 32 bit token value to be written. It could be used
//! to denote the number of bytes written on to the Device-to-Host buffer
//!
//! \return None
//!
//! This API can be used while using the Mailbox mechanism.
//! Writing to this register could be used to trigger an interrupt
//! to the Host using the Device to Host
//! interrupt line(D2HINT) of the module.
//! It can be used to interrupt the external host.
//
//*****************************************************************************
static inline void
HIC_setD2HToken(uint32_t token)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x12U)))) = token;
}

//*****************************************************************************
//
//! Returns the token written by the token written onto the Device to Host Token
//!
//! \return the 32 bit Token value written into the register
//!
//! This API can be used while using the Mailbox mechanism.
//
//*****************************************************************************
static inline uint32_t
HIC_getD2HToken(void)
{
    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x12U)))));
}

//*****************************************************************************
//
//! Configures the Base Address of the region
//!
//! \param index specifies the index of the Device Region to be configured
//!        can be from 0 to HIC_NUM_BASE_ADDRESS-1
//!
//! \param baseAddress the 32 bit base address of the device region
//!        being configured
//!
//! The device memory which HIC module can access can be divided into multiple
//! 256 byte regions.
//! For Example: GSRAM in Region 0,
//!              ADC registers in Region 1
//!              FSI registers in Region 2,etc
//! This API helps to configure the base address for each region
//! The HIC address Pin can then be used to offset into the specific region
//! by the host
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_setBaseAddress(uint16_t index,
                uint32_t baseAddress)
{
    //
    //Check the arguments.
    //
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x14U + (index * 2))))) = baseAddress;
    __edis();
}

//*****************************************************************************
//
//! Returns the Base Address configured for the region
//!
//! \param index specifies the index of the Device Region to be configured
//!        can be from 0 to HIC_NUM_BASE_ADDRESS-1
//!
//! Returns the configured base address for the Region index provided
//!
//! \return 32 bit base address configured for the region
//
//*****************************************************************************
static inline uint32_t
HIC_getBaseAddress(uint16_t index)
{
    //
    //Check the arguments.
    //
    ;

    return(0x00006500U + 0x14U + (index * 2));
}

//*****************************************************************************
//
//! Enables the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_H2DINTEN_H2D_INTEN - Data Ready interrupt Enable
//! - \b HIC_H2DINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_H2DINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_H2DINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//!
//! Enables the specified interrupts. This will result in a HIC interrupt
//! generated to the C28x core.
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_enableH2DInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x28U)))) |= flags;
}

//*****************************************************************************
//
//! Disables the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_H2DINTEN_H2D_INTEN - Data Ready interrupt Enable
//! - \b HIC_H2DINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_H2DINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_H2DINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//!
//! Disables the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_disableH2DInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x28U)))) &= ~flags;
}

//*****************************************************************************
//
//! Gives the status of Host to Device interrupts
//!
//! \return 32bit flag with the logical ORed values below
//! - \b HIC_H2DINTFLG_H2D_FLG - Data Ready interrupt Status
//! - \b HIC_H2DINTFLG_BUSERR_FLG - Bus error Interrupt Status
//! - \b HIC_H2DINTFLG_ILLWR_FLG - Illegal Write Interrupt Status
//! - \b HIC_H2DINTFLG_ILLRD_FLG - Illegal Read Interrupt Status.
//!
//! \n The Flag if Set indicates that the corresponding Interrupt is active
//! (has occured)
//
//*****************************************************************************
static inline uint32_t
HIC_getH2DInterruptStatus(void)
{

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x2AU)))));
}

//*****************************************************************************
//
//! Clears the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be cleared
//! - \b HIC_H2DINTCLR_H2D_CLR - Data Ready interrupt Clear
//! - \b HIC_H2DINTCLR_BUSERR_CLR - Bus error Interrupt Clear
//! - \b HIC_H2DINTCLR_ILLWR_CLR - Illegal Write Interrupt Clear
//! - \b HIC_H2DINTCLR_ILLRD_CLR - Illegal Read Interrupt Clear
//!
//! Clears the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_clearH2DInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x2CU)))) = flags;
}

//*****************************************************************************
//
//! Forces the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be Forced
//! - \b HIC_H2DINTFRC_H2D_INTFRC - Data Ready interrupt Force
//! - \b HIC_H2DINTFRC_BUSERR_INTFRC - Bus error Interrupt Force
//! - \b HIC_H2DINTFRC_ILLWR_INTFRC - Illegal Write Interrupt Force
//! - \b HIC_H2DINTFRC_ILLRD_INTFRC - Illegal Read Interrupt Force
//!
//! Forces the interrupt flags specified. Can be used for Debug purpose.
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_forceH2DInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x2EU)))) = flags;
}

//*****************************************************************************
//
//! Enables the Interrupts from Device to Host
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_D2HINTEN_D2H_INTEN - Data Ready interrupt Enable
//! - \b HIC_D2HINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_D2HINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_D2HINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//! - \b HIC_D2HINTEN_ACCVIO_INTEN - Access Violation Interrupt Enable
//! - \b Event Trigger interrupt flags - The higher 16 bits when Set will enable
//!  corresponding D2H interrupts. Refer TRM for details.
//!
//! Enables the specified interrupts. This will result in a HIC interrupt
//! generated to the Host(D2HINT).
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_enableD2HInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x30U)))) |= flags;
}

//*****************************************************************************
//
//! Disables the Interrupts from Device to Host
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_D2HINTEN_D2H_INTEN - Data Ready interrupt Enable
//! - \b HIC_D2HINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_D2HINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_D2HINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//! - \b HIC_D2HINTEN_ACCVIO_INTEN - Access Violation Interrupt Enable
//! - <b> Event Trigger interrupt flags </b> - The higher 16 bits when set will
//! disable corresponding D2H interrupts. Refer TRM for details.
//!
//! Disables the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_disableD2HInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x30U)))) &= ~flags;
}

//*****************************************************************************
//
//! Gives the status of Device to Host interrupts
//!
//! \return 32bit flag with the logical ORed values below
//! - \b HIC_D2HINTFLG_D2H_FLG - Data Ready interrupt Status
//! - \b HIC_D2HINTFLG_BUSERR_FLG - Bus error Interrupt Status
//! - \b HIC_D2HINTFLG_ILLWR_FLG - Illegal Write Interrupt Status
//! - \b HIC_D2HINTFLG_ILLRD_FLG - Illegal Read Interrupt Status
//! - \b HIC_D2HINTFLG_ACCVIO_FLG - Access Violation Interrupt Status
//! - <b> Event Trigger Interrupt Flags </b>- The higher 16 bits give
//! the status of event Trigger Interrupt flags.
//! Refer TRM for the sources of these interrupts.
//!
//!  The Flag if Set indicates that the corresponding Interrupt is active
//! (has occurred)
//
//*****************************************************************************
static inline uint32_t
HIC_getD2HInterruptStatus(void)
{

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x32U)))));
}

//*****************************************************************************
//
//! Clears the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be cleared
//! - \b HIC_D2HINTCLR_D2H_CLR - Data Ready interrupt Clear
//! - \b HIC_D2HINTCLR_BUSERR_CLR - Bus error Interrupt Clear
//! - \b HIC_D2HINTCLR_ILLWR_CLR - Illegal Write Interrupt Clear
//! - \b HIC_D2HINTCLR_ILLRD_CLR - Illegal Read Interrupt Clear
//! - \b HIC_D2HINTCLR_ACCVIO_CLR - Access Violation Interrupt Clear
//! - <b> Event Trigger Interrupt Clear Flags </b> - The higher 16 bits
//! indicates event trigger flags to be cleared.
//! Refer TRM for the sources of these interrupts.
//!
//! Clears the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_clearD2HInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x34U)))) = flags;
}

//*****************************************************************************
//
//! Forces the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be Forced
//! - \b HIC_D2HINTFRC_D2H_INTFRC - Data Ready interrupt Force
//! - \b HIC_D2HINTFRC_BUSERR_INTFRC - Bus error Interrupt Force
//! - \b HIC_D2HINTFRC_ILLWR_INTFRC - Illegal Write Interrupt Force
//! - \b HIC_D2HINTFRC_ILLRD_INTFRC - Illegal Read Interrupt Force
//! - \b HIC_D2HINTFRC_ACCVIO_INTFRC - Access violation Interrupt Force
//! - <b> Event Trigger Interrupt Force Flags </b> - The higher 16 bits
//! indicates event trigger flags to be cleared.
//! Refer TRM for the sources of these interrupts.
//!
//! Forces the interrupt flags specified. Can be used for Debug purposes.
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_forceD2HInterrupt(uint32_t flags)
{

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x36U)))) = flags;
}

//*****************************************************************************
//
//! Returns the Address when Access violation happened
//!
//! \return returns the 32 bit address when the Access violation happened
//!
//! While the HIC module internal access port accesses a memory, if there is
//! an access violation, the module updates the address in this register.
//
//*****************************************************************************
static inline uint32_t
HIC_getAccessViolationAddress(void)
{

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x38U)))));
}

//*****************************************************************************
//
//! Returns the Host to Device Buffer for the offset specified
//!
//! \param offset specifies the offset of the H2D buffer
//!         can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return returns the 32 bit content of the Host to Device buffer.
//!
//! The Host to Device buffer can be used to implement a communication
//! scheme on which the Host writes the data to sent to the Control peripherals.
//! The MCU can pick it up and stream it over control peripherals.
//! The Device to Host Buffer can be used to write the response back.
//! The External host need not continuously wait for the data/response.
//
//*****************************************************************************
static inline uint32_t
HIC_readH2DBuffer(uint16_t offset)
{
    //
    //Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x40U + (offset * 2))))));
}

//*****************************************************************************
//
//! Writes to the Host to Device buffer
//!
//! \param offset specifies the offset of the H2D buffer
//!         can vary from 0 to HIC_NUM_BUFFER_REGS-1
//! \param data the 32bit data to be written onto the buffer
//!
//! \return none
//!
//! This API should be used only when the Device write to Host buffer
//! is enabled, using HIC_setConfig(HIC_MODECR_H2DBUF_DEVWREN) API.
//
//*****************************************************************************
static inline void
HIC_writeH2DBuffer(uint16_t offset, uint32_t data)
{
    //
    //Check the arguments.
    //
    ;

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x40U + (offset * 2))))) = data;
}

//*****************************************************************************
//
//! Clears the Host to Device buffer (by making it Zero)
//!
//! \param offset specifies the offset of the H2D buffer
//!         can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return none
//!
//! This API should be used only when the Device write to Host buffer
//! is enabled, using HIC_setConfig(HIC_MODECR_H2DBUF_DEVWREN) API.
//! This API can be used to clear the content of H2D Buffer
//
//*****************************************************************************
static inline void
HIC_clearH2DBuffer(uint16_t offset)
{
    //
    //Check the arguments.
    //
    ;

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x40U + (offset * 2))))) = 0;
}

//*****************************************************************************
//
//! Returns the Device to Host Buffer for the offset specified
//!
//! \param offset specifies the offset of the D2H buffer
//!         can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return returns the 32 bit content of the Device to Host buffer
//!
//! The Device to Host Buffer can be used to write the response back to host
//! The External host need not continuously wait for the data/response.
//
//*****************************************************************************
static inline uint32_t
HIC_readD2HBuffer(uint16_t offset)
{
    //
    //Check the arguments.
    //
    ;

    return((*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x60U + (offset * 2))))));
}

//*****************************************************************************
//
//! Writes to the Device to Host buffer
//!
//! \param offset specifies the offset of the D2H buffer
//!         can vary from 0 to HIC_NUM_BUFFER_REGS-1
//! \param data the 32bit data to be written onto the buffer
//!
//! \return none
//
//*****************************************************************************
static inline void
HIC_writeD2HBuffer(uint16_t offset, uint32_t data)
{
    //
    //Check the arguments.
    //
    ;

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x60U + (offset * 2))))) = data;
}

//*****************************************************************************
//
//! Clears the Device to Host buffer (by making it Zero)
//!
//! \param offset specifies the offset of the D2H buffer
//!         can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return none
//!
//! This API can be used to clear the content of D2H Buffer
//
//*****************************************************************************
static inline void
HIC_clearD2HBuffer(uint16_t offset)
{
    //
    //Check the arguments.
    //
    ;

    (*((volatile uint32_t *)((uintptr_t)(0x00006500U + 0x60U + (offset * 2))))) = 0U;
}

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:  hrcap.h
//
// TITLE: C28x HRCAP Driver.
//
//#############################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup hrcap_api HRCAP
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_hrcap.h
//
// TITLE:   Definitions for the HRCAP registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the HRCAP register offsets
//
//*************************************************************************************************



//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL2 register
//
//*************************************************************************************************
                                              // flags.

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECEINT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAPSYNCINSEL register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRINTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRFRC register
//
//*************************************************************************************************




//*****************************************************************************
//
// Values that can be passed to HRCAP_enableCalibrationInterrupt(),
// HRCAP_disableCalibrationInterrupt() as the intFlags parameter and
// HRCAP_clearCalibrationFlags() and HRCAP_forceCalibrationFlags() as the flags
// parameter and returned by HRCAP_getCalibrationFlags().
//
//*****************************************************************************
//! Global calibration interrupt flag
//!
//! Calibration done flag
//!
//! Calibration period overflow flag
//!

//*****************************************************************************
//
//! Values that can be passed to HRCAP_getCalibrationClockPeriod() as the
//! \e clockSource parameter.
//
//*****************************************************************************
typedef enum
{
    HRCAP_CALIBRATION_CLOCK_SYSCLK = 0x0, //!< Use SYSCLK for period match.
    HRCAP_CALIBRATION_CLOCK_HRCLK  = 0x4  //!< Use HRCLK for period match.
}HRCAP_CalibrationClockSource;

//*****************************************************************************
//
//! Values that can be passed to HRCAP_setCalibrationMode(),
//! as the \e continuousMode parameter.
//
//*****************************************************************************
typedef enum
{
    //! Continuous calibration disabled.
    HRCAP_CONTINUOUS_CALIBRATION_DISABLED = 0x00,
    //! Continuous calibration enabled.
    HRCAP_CONTINUOUS_CALIBRATION_ENABLED =  0x20
}HRCAP_ContinuousCalibrationMode;

//*****************************************************************************
//
//! \internal
//! Checks HRCAP base address.
//!
//! \param base specifies the HRCAP module base address.
//!
//! This function determines if an HRCAP module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! enables HRCAP.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function enables High Resolution Capture module.
//!
//! \note High resolution clock must be enabled before High Resolution Module
//!       is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_enableHighResolution(uint32_t base)
{
    ;

    __eallow();

    //
    // Set HRE bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Disables HRCAP.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function disable High Resolution Capture module.
//!
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_disableHighResolution(uint32_t base)
{
    ;

    __eallow();

    //
    // Set HRE bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! Enables high resolution clock.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function enables High Resolution clock.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_enableHighResolutionClock(uint32_t base)
{
    ;

    __eallow();
    //
    // Set HRCLKE bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x2U;
    __edis();
}

//*****************************************************************************
//
//! Disables High resolution clock.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function disables High Resolution clock.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_disbleHighResolutionClock(uint32_t base)
{
    ;

    __eallow();

    //
    // Clear HRCLKE bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x2U;
    __edis();
}

//*****************************************************************************
//
//! Starts calibration.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function starts calibration.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_startCalibration(uint32_t base)
{
    ;

    __eallow();

    //
    // Set CALIBSTART bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x8U;
    __edis();
}

//*****************************************************************************
//
//! Sets the calibration mode.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function sets the the calibration mode by turning on continuous
//! calibration.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_setCalibrationMode(uint32_t base)
{
    ;

    __eallow();

    //
    // Write to CALIBSTS and CALIBCONT bits.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x20U;
    __edis();
}

//*****************************************************************************
//
//! Enables calibration interrupt.
//!
//! \param base is the base address of the HRCAP module.
//! \param intFlags is the calibration interrupt flags to be enabled.
//!
//! This function enables HRCAP calibration interrupt flags.
//! Valid values for intFlags are:
//!     - HRCAP_CALIBRATION_DONE   - Calibration done interrupt.
//!     - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow
//!                                                check interrupt.
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_enableCalibrationInterrupt(uint32_t base, uint16_t intFlags)
{
    ;
    ;

    __eallow();

    //
    // Set CALIBDONE or CALPRDCHKSTS.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= intFlags;
    __edis();
}

//*****************************************************************************
//
//! Disables calibration interrupt source.
//!
//! \param base is the base address of the HRCAP module.
//! \param intFlags is the calibration interrupt flags to be disabled.
//!
//! This function disables HRCAP calibration interrupt flags.
//! Valid values for intFlags are:
//!     - HRCAP_CALIBRATION_DONE   - Calibration done interrupt.
//!     - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period check
//!                                                   interrupt.
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_disableCalibrationInterrupt(uint32_t base, uint16_t intFlags)
{
    ;
    ;

    __eallow();

    //
    // Clear CALIBDONE or CALPRDCHKSTS.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~intFlags;
    __edis();
}

//*****************************************************************************
//
//! Returns the calibration interrupt source.
//!
//! \param base is the base address of the HRCAP module.
//!
//! This function returns the HRCAP calibration interrupt source.
//!
//! \return Returns the HRCAP interrupt that has occurred. The following are
//!         valid return values.
//!          - HRCAP_GLOBAL_CALIBRATION_INTERRUPT - Global calibration
//!                                                 interrupt.
//!          - HRCAP_CALIBRATION_DONE   - Calibration done interrupt.
//!          - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow
//!                                                interrupt.
//!
//! \note - User can check if a combination of the interrupts have occurred
//!         by ORing the above return values.
//
//*****************************************************************************
static inline uint16_t
HRCAP_getCalibrationFlags(uint32_t base)
{
    ;

    //
    // Return contents of HRFLG register.
    //
    return((uint16_t)((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) & 0x7U));
}

//*****************************************************************************
//
//! Clears calibration flags.
//!
//! \param base is the base address of the HRCAP module.
//! \param flags is the calibration flags to be cleared.
//!
//! This function clears HRCAP calibration flags.
//! The following are valid values for flags.
//!     - HRCAP_GLOBAL_CALIBRATION_INTERRUPT - Global calibration interrupt.
//!     - HRCAP_CALIBRATION_DONE   - Calibration done flag.
//!     - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_clearCalibrationFlags(uint32_t base, uint16_t flags)
{
    ;
    ;

    //
    // Write to HRCLR register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) |= flags;
}

//*****************************************************************************
//
//! Return the Calibration status
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function returns the calibration status.
//!
//! \return This functions returns true if the calibration is in process,false
//!         if there is no active calibration.
//
//*****************************************************************************
static inline _Bool
HRCAP_isCalibrationBusy(uint32_t base)
{
    ;

    //
    // Read CALIBSTS bit.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & 0x10U) ==
             0x10U);
}

//*****************************************************************************
//
//! Force a software based calibration
//!
//! \param base is the base address of the HRCAP instance used.
//! \param flag is the calibration flag source.
//!
//! This function forces a software based calibration done flag.
//! The following are valid values for flag.
//!     - HRCAP_CALIBRATION_DONE - Calibration done flag.
//!     - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_forceCalibrationFlags(uint32_t base, uint16_t flag)
{
    ;
    ;

    __eallow();

    //
    // Write to CALIBDONE or CALPRDCHKSTS bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= flag;
    __edis();
}

//*****************************************************************************
//
//! Sets the calibration period count
//!
//! \param base is the base address of the HRCAP instance used.
//! \param sysclkHz is the rate of the SYSCLK in Hz.
//!
//! This function sets the calibration period count value to achieve a period
//! of 1.6 milliseconds given the SYSCLK frequency in Hz (the \e sysclkHz
//! parameter).
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_setCalibrationPeriod(uint32_t base, uint32_t sysclkHz)
{
    ;

    __eallow();
    (*((volatile uint32_t *)((uintptr_t)(base + 0xCU)))) = (sysclkHz * 16U) / 10000U;
    __edis();
}

//*****************************************************************************
//
//! Returns the calibration clock period
//!
//! \param base is the base address of the HRCAP instance used.
//! \param clockSource is the calibration clock source
//! (\b HRCAP_CALIBRATION_CLOCK_SYSCLK or \b HRCAP_CALIBRATION_CLOCK_HRCLK).
//!
//! This function returns the period match value of the calibration clock. The
//! return value has a valid count when a period match occurs.
//!
//! \return This function returns the captured value of the clock counter
//!         specified by clockSource.
//
//*****************************************************************************
static inline uint32_t
HRCAP_getCalibrationClockPeriod(uint32_t base,
                                HRCAP_CalibrationClockSource clockSource)
{
    ;

    //
    // Return HRCAP_O_HRSYSCLKCAP or HRCAP_O_HRCLKCAP.
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x10U + (uint32_t)clockSource)))));
}

//*****************************************************************************
//
//! Calculates the scale factor
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function reads the SYSCLK and HRCLK calibration periods and then
//! uses them to calculate the scale factor.
//!
//! \return This function returns the calculated scale factor.
//
//*****************************************************************************
static inline float32_t
HRCAP_getScaleFactor(uint32_t base)
{
    ;

    //
    // Calculate and return the scale factor.
    //
    return((float32_t)HRCAP_getCalibrationClockPeriod(base,
                                            HRCAP_CALIBRATION_CLOCK_SYSCLK) /
           (float32_t)HRCAP_getCalibrationClockPeriod(base,
                                            HRCAP_CALIBRATION_CLOCK_HRCLK));
}

//*****************************************************************************
//
//! Returns event time stamp in nanoseconds
//!
//! \param timeStamp is a raw time stamp count returned by
//! ECAP_getEventTimeStamp().
//! \param scaleFactor is the calculated scale factor returned by
//! HRCAP_getScaleFactor().
//!
//! This function converts a raw CAP time stamp (the \e timeStamp parameter) to
//! nanoseconds using the provided scale factor (the \e scaleFactor parameter).
//!
//! \return Returns the converted time stamp in nanoseconds.
//
//*****************************************************************************
static inline float32_t
HRCAP_convertEventTimeStampNanoseconds(uint32_t timeStamp,
                                       float32_t scaleFactor)
{
    //
    // Convert the raw count value to nanoseconds using the given scale factor.
    //
    return((float32_t)timeStamp * scaleFactor * ((float32_t)25.0 /
                                                 (float32_t)384.0));
}


//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//#############################################################################
//
// FILE:   hrpwm.h
//
// TITLE:   C28x HRPWM Driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup hrpwm_api HRPWM
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_hrpwm.h
//
// TITLE:   Definitions for the HRPWM registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the HRPWM register offsets
//
//*************************************************************************************************
                                           // Output A
                                           // Output B
                                           // Mirror Register
                                           // Mirror Register
                                           // Resolution Register


//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMSYNCINSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBSTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMSYNCOUTEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQTSRCSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the PCCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the VCAPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the VCNTCFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCNFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRPWR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRMSTEP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCNFG2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the HRPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TRREM register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCFG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMXLINK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLA2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLB2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQSFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCSFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBREDHR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBRED register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBFEDHR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DBFED register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TBPHS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPA register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPB register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZDCSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCA register
//
//*************************************************************************************************
                                             // UP
                                             // DOWN
                                             // UP
                                             // DOWN

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCB register
//
//*************************************************************************************************
                                             // UP
                                             // DOWN
                                             // UP
                                             // DOWN

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZEINT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCBCFLG register
//
//*************************************************************************************************
                                         // 2
                                         // 2

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZOSTFLG register
//
//*************************************************************************************************
                                         // 1
                                         // 1

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCBCCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZOSTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the TZFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETPS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETFRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETINTPS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETSOCPS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCNTINITCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCNTINIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCACTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCFCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCAPCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BLANKPULSEMIXSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCAHTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCALTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBHTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBLTRIPSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMLOCK register
//
//*************************************************************************************************



//#############################################################################
//
// FILE:   hrpwm.h
//
// TITLE:   C28x HRPWM Driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//*****************************************************************************
//
//! Values that can be passed to HRPWM_setMEPEdgeSelect(),
//! HRPWM_setMEPControlMode(), HRPWM_setCounterCompareShadowLoadEvent()
//! as the \e channel parameter.
//
//*****************************************************************************
typedef enum
{
    HRPWM_CHANNEL_A = 0, //!< HRPWM A
    HRPWM_CHANNEL_B = 8  //!< HRPWM B
} HRPWM_Channel;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_setMEPEdgeSelect() as the \e mepEdgeMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! HRPWM is disabled
    HRPWM_MEP_CTRL_DISABLE = 0,
    //! MEP controls rising edge
    HRPWM_MEP_CTRL_RISING_EDGE = 1,
    //! MEP controls falling edge
    HRPWM_MEP_CTRL_FALLING_EDGE = 2,
    //! MEP controls both rising and falling edge
    HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3
} HRPWM_MEPEdgeMode;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_setHRMEPCtrlMode() as the \e
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! CMPAHR/CMPBHR or TBPRDHR controls MEP edge
    HRPWM_MEP_DUTY_PERIOD_CTRL = 0,
    //! TBPHSHR controls MEP edge
    HRPWM_MEP_PHASE_CTRL = 1
} HRPWM_MEPCtrlMode;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_setCounterCompareShadowLoadEvent(),
//! HRPWM_setRisingEdgeDelayLoadMode() and HRPWM_setFallingEdgeDelayLoadMode
//! as the \e loadEvent parameter.
//
//*****************************************************************************
typedef enum
{
    //! load when counter equals zero
    HRPWM_LOAD_ON_CNTR_ZERO = 0,
    //! load when counter equals period
    HRPWM_LOAD_ON_CNTR_PERIOD = 1,
    //! load when counter equals zero or period
    HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2
} HRPWM_LoadMode;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_setChannelBOutputPath() as the \e
//! outputOnB parameter.
//
//*****************************************************************************
typedef enum
{
    HRPWM_OUTPUT_ON_B_NORMAL = 0, //!< ePWMxB output is normal.
    HRPWM_OUTPUT_ON_B_INV_A  = 1  //!< ePWMxB output is inverted
                                  //!< version of ePWMxA signal
} HRPWM_ChannelBOutput;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_setSyncPulseSource() as the \e
//! syncPulseSource parameter.
//
//*****************************************************************************
typedef enum
{
    //! Counter equals Period
    HRPWM_PWMSYNC_SOURCE_PERIOD = 0,
    //! Counter equals zero
    HRPWM_PWMSYNC_SOURCE_ZERO = 1,
    //! Counter equals COMPC when counting up
    HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4,
    //! Counter equals COMPC when counting down
    HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5,
    //! Counter equals COMPD when counting up
    HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6,
    //! Counter equals COMPD when counting down
    HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7
} HRPWM_SyncPulseSource;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_setCounterCompareValue() as the \e
//! compModule parameter.
//
//*****************************************************************************
typedef enum
{
    HRPWM_COUNTER_COMPARE_A = 0, //!< counter compare A
    HRPWM_COUNTER_COMPARE_B = 4  //!< counter compare B
} HRPWM_CounterCompareModule;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_setDeadbandMEPEdgeSelect() as the \e
//! mepDBEdge.
//
//*****************************************************************************
typedef enum
{
    //! HRPWM is disabled
    HRPWM_DB_MEP_CTRL_DISABLE = 0,
    //! MEP controls Rising Edge Delay
    HRPWM_DB_MEP_CTRL_RED = 1,
    //! MEP controls Falling Edge Delay
    HRPWM_DB_MEP_CTRL_FED = 2,
    //! MEP controls both Falling and Rising edge delay
    HRPWM_DB_MEP_CTRL_RED_FED = 3
} HRPWM_MEPDeadBandEdgeMode;

//*****************************************************************************
//
//! Values that can be passed to HRPWM_lockRegisters() as the \e registerGroup
//! parameter.
//
//*****************************************************************************
typedef enum
{
    HRPWM_REGISTER_GROUP_HRPWM = 0x1,           //!< HRPWM register group
    HRPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2,     //!< Global load register group
    HRPWM_REGISTER_GROUP_TRIP_ZONE = 0x4,       //!< Trip zone register group
    HRPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group
    HRPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group
} HRPWM_LockRegisterGroup;

//*****************************************************************************
//
// Functions APIs shared with ePWM module
//
//*****************************************************************************

//
// Time Base Sub Module related APIs
//

//
// Action Qualifier module related APIs
//

//
// Dead Band Module related APIs
//

//
// Chopper module related APIs
//

//
// Trip Zone module related APIs
//

//
// HRPWM_getTripZoneInterruptStatus API define is obsolete please use
// HRPWM_getTripZoneFlagStatus going forward.
//

//
// HRPWM_getCycleByCycleTripZoneInterruptStatus API define is obsolete
// please use HRPWM_getCycleByCycleTripZoneFlagStatus going forward.
//

//
// HRPWM_getOneShotTripZoneInterruptStatus is obsolete please use
// HRPWM_getOneShotTripZoneFlagStatus going forward.
//

//
// HRPWM_clearTripZoneInterruptFlag is obsolete please use
// HRPWM_clearTripZoneFlag going forward.
//

//
// HRPWM_clearCycleByCycleTripZoneInterruptFlag is obsolete please use
// HRPWM_clearCycleByCycleTripZoneFlag going forward.
//

//
// HRPWM_clearOneShotTripZoneInterruptFlag is obsolete please use
// HRPWM_clearOneShotTripZoneFlag going forward.
//

//
// Event Trigger related APIs
//

//
// ADC SOC configuration related APIs
//

//
// Digital Compare Module related APIs
//

//
// Valley switching related APIs
//

//
// Global Load feature related APIs
//

//*****************************************************************************
//
// Prototypes for the API.
//
//*****************************************************************************

//*****************************************************************************
//
//! \internal
//! Checks HRPWM base address.
//!
//! \param base specifies the HRPWM module base address.
//!
//! This function determines if an HRPWM module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the consolidated phase shift value in high resolution mode.
//!
//! \param base is the base address of the EPWM module.
//! \param phaseCount is the consolidated phase shift count value.
//!
//! This function sets the consolidated phase shift value, that is, both TBPHS
//! and TBPHSHR values are configured together.
//!
//! Call EPWM_enablePhaseShiftLoad & HRPWM_enableHRPhaseShiftLoad() functions
//! to enable loading of the phaseCount in high resolution mode.
//!
//! \b Note: phaseCount is a 24-bit value.
//! \b Note: For configuring TBPHS = 0x3C, TBPHSHR = 0x2;
//!          phaseCount = 0x3C02
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Write to TBPHS:TBPHSHR bits
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x60U)))) = phaseCount << 8U;
}

//*****************************************************************************
//
//! Sets only the high resolution phase shift value.
//!
//! \param base is the base address of the EPWM module.
//! \param hrPhaseCount is the high resolution phase shift count value.
//!
//! This function sets only the high resolution phase shift(TBPHSHR) value.
//! Call the HRPWM_enableHRPhaseShiftLoad() function to enable loading of
//! the hrPhaseCount.
//!
//! \b Note: hrPhaseCount is an 8-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResPhaseShiftOnly(uint32_t base, uint16_t hrPhaseCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Write to TBPHSHR bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x60U)))) = hrPhaseCount << 8U;
}

//*****************************************************************************
//
//! Sets the consolidated period of time base counter used in HR mode.
//!
//! \param base is the base address of the EPWM module.
//! \param periodCount is the consolidated period count value.
//!
//! This function sets the consolidated period of time base counter value
//! (TBPRD:TBPRDHR) required in high resolution mode.
//!
//! User should map the desired period or frequency of the waveform into
//! the correct periodCount.
//!
//! \b Note: periodCount is a 24 bit value.
//! \b Note: For configuring TBPRD = 0x3C, TBPRDHR = 0xA;
//!          periodCount = 0x3C0A
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setTimeBasePeriod(uint32_t base, uint32_t periodCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Write to TBPRD:TBPRDHR bits
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x62U)))) = periodCount << 8U;
}

//*****************************************************************************
//
//! Sets only the high resolution time base counter.
//!
//! \param base is the base address of the EPWM module.
//! \param hrPeriodCount is the high resolution period count value.
//!
//! This function sets only the high resolution time base counter(TBPRDHR)
//! value.
//!
//! User should map the desired period or frequency of the waveform into
//! the correct hrPeriodCount.
//!
//! \b Note: hrPeriodCount is an 8-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResTimeBasePeriodOnly(uint32_t base, uint16_t hrPeriodCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Write to TBPRDHR bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x62U)))) = hrPeriodCount << 8U;
}

//*****************************************************************************
//
//! Gets the consolidated time base period count used in HR mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function gets the consolidated time base period(TBPRD:TBPRDHR) value
//! used in high resolution mode.
//!
//! \return The consolidated time base period count value.
//
//*****************************************************************************
static inline uint32_t
HRPWM_getTimeBasePeriod(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Read from TBPRD:TBPRDHR bit
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x62U)))) >> 8U);
}

//*****************************************************************************
//
//! Gets the only the high resolution time base period count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function gets only the high resolution time base period(TBPRDHR) value.
//!
//! \return The high resolution time base period count value.
//
//*****************************************************************************
static inline uint16_t
HRPWM_getHiResTimeBasePeriodOnly(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Read from TBPRDHR bit
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x62U)))) >> 8U);
}

//*****************************************************************************
//
//! Sets the high resolution edge controlled by MEP (Micro Edge Positioner).
//!
//! \param base is the base address of the EPWM module.
//! \param channel is high resolution period module.
//! \param mepEdgeMode edge of the PWM that is controlled by MEP (Micro Edge
//!        Positioner).
//!
//! This function sets the edge of the PWM that is controlled by MEP (Micro
//! Edge Positioner). Valid values for the parameters are:
//!  - channel
//!      - HRPWM_CHANNEL_A  - HRPWM A
//!      - HRPWM_CHANNEL_B  - HRPWM B
//!  - mepEdgeMode
//!      - HRPWM_MEP_CTRL_DISABLE                 - HRPWM is disabled
//!      - HRPWM_MEP_CTRL_RISING_EDGE             - MEP (Micro Edge Positioner)
//!                                                 controls rising edge.
//!      - HRPWM_MEP_CTRL_FALLING_EDGE            - MEP (Micro Edge Positioner)
//!                                                 controls falling edge.
//!      - HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE - MEP (Micro Edge Positioner)
//!                                                 controls both edges.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel,
                       HRPWM_MEPEdgeMode mepEdgeMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the edge mode
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) =
             (((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) & ~(0x3U << (uint16_t)channel )) |
              ((uint16_t)mepEdgeMode << (uint16_t)channel));
    __edis();
}

//*****************************************************************************
//
//! Sets the MEP (Micro Edge Positioner) control mode.
//!
//! \param base is the base address of the EPWM module.
//! \param channel is high resolution period module.
//! \param mepCtrlMode is the MEP (Micro Edge Positioner) control mode.
//!
//! This function sets the mode (register type) the MEP (Micro Edge Positioner)
//! will control. Valid values for the parameters are:
//!  - channel
//!      - HRPWM_CHANNEL_A  - HRPWM A
//!      - HRPWM_CHANNEL_B  - HRPWM B
//!  - mepCtrlMode
//!      - HRPWM_MEP_DUTY_PERIOD_CTRL      - MEP (Micro Edge Positioner) is
//!                                          controlled by value of CMPAHR/
//!                                          CMPBHR(depending on the value of
//!                                          channel) or TBPRDHR.
//!      - HRPWM_MEP_PHASE_CTRL            - MEP (Micro Edge Positioner) is
//!                                          controlled by TBPHSHR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel,
                        HRPWM_MEPCtrlMode mepCtrlMode)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the MEP control
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) =
       (((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) & ~(0x1U << ((uint16_t)channel + 2U))) |
         ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U)));
    __edis();
}

//*****************************************************************************
//
//! Sets the high resolution comparator load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param channel is high resolution period module.
//! \param loadEvent is the MEP (Micro Edge Positioner) control mode.
//!
//! This function sets the shadow load mode of the high resolution comparator.
//! The function sets the COMPA or COMPB register depending on the channel
//! variable.
//! Valid values for the parameters are:
//!  - channel
//!      - HRPWM_CHANNEL_A  - HRPWM A
//!      - HRPWM_CHANNEL_B  - HRPWM B
//!  - loadEvent
//!      - HRPWM_LOAD_ON_CNTR_ZERO         - load when counter equals zero
//!      - HRPWM_LOAD_ON_CNTR_PERIOD       - load when counter equals period
//!      - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD  - load when counter equals zero or
//!                                          period
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel,
                                       HRPWM_LoadMode loadEvent)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the CMPAHR or CMPBHR load mode
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) =
       (((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) & ~(0x3U << ((uint16_t)channel + 3U))) |
         ((uint16_t)loadEvent << ((uint16_t)channel + 3U)));
    __edis();
}

//*****************************************************************************
//
//! Sets the high resolution output swap mode.
//!
//! \param base is the base address of the EPWM module.
//! \param enableOutputSwap is the output swap flag.
//!
//! This function sets the HRPWM output swap mode. If enableOutputSwap is true,
//! ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA
//! output. If it is false ePWMxA and ePWMxB outputs are unchanged.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setOutputSwapMode(uint32_t base, _Bool enableOutputSwap)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set output swap mode
    //
    __eallow();
    if(enableOutputSwap)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) |= 0x80U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) &= ~0x80U;
    }
    __edis();
}

//*****************************************************************************
//
//! Sets the high resolution output on ePWMxB
//!
//! \param base is the base address of the EPWM module.
//! \param outputOnB is the output signal on ePWMxB.
//!
//! This function sets the HRPWM output signal on ePWMxB. If outputOnB is
//! HRPWM_OUTPUT_ON_B_INV_A, ePWMxB output is an inverted version of
//! ePWMxA. If outputOnB is HRPWM_OUTPUT_ON_B_NORMAL, ePWMxB output is
//! ePWMxB.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the output on ePWM B
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) =
            (((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) & ~(0x20U)) |
             ((uint16_t)outputOnB << 5U));
    __edis();
}

//*****************************************************************************
//
//! Enables MEP (Micro Edge Positioner) automatic scale mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the MEP (Micro Edge Positioner) to automatically
//! scale HRMSTEP.
//!
//! The SFO library will calculate required MEP steps per coarse steps and
//! feed it to HRMSTEP register. The MEP calibration module will use the value
//! in HRMSTEP to determine appropriate number of MEP steps represented by
//! fractional duty cycle.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_enableAutoConversion(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Enable MEP automatic scale
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) |= 0x40U;
    __edis();
}

//*****************************************************************************
//
//! Disables MEP automatic scale mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the MEP (Micro Edge Positioner) from automatically
//! scaling HRMSTEP.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_disableAutoConversion(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Disable MEP automatic scale
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) &= ~0x40U;
    __edis();
}

//*****************************************************************************
//
//! Enable high resolution period feature.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the high resolution period feature.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_enablePeriodControl(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set HRPE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) |= 0x1U;
    __edis();
}

//*****************************************************************************
//
//! Disable high resolution period feature.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the high resolution period feature.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_disablePeriodControl(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear HRPE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) &= ~0x1U;
    __edis();
}

//*****************************************************************************
//
//! Enable high resolution phase load
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables loading of high resolution phase shift value which is
//! set by the function HRPWM_setPhaseShift().
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_enablePhaseShiftLoad(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set TBPHSHRLOADE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) |= 0x4U;
    __edis();
}

//*****************************************************************************
//
//! Disable high resolution phase load
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables loading of high resolution phase shift value.
//!
//! \return
//
//*****************************************************************************
static inline void
HRPWM_disablePhaseShiftLoad(uint32_t base)
{
    //
    // Check the arguments
    //
    ;

    //
    // Clear TBPHSHRLOADE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) &= ~0x4U;
    __edis();
}

//*****************************************************************************
//
//! Set high resolution PWMSYNC source.
//!
//! \param base is the base address of the EPWM module.
//! \param syncPulseSource is the PWMSYNC source.
//!
//! This function sets the high resolution PWMSYNC pulse source.
//! Valid values for syncPulseSource are:
//!  - HRPWM_PWMSYNC_SOURCE_PERIOD      - Counter equals Period.
//!  - HRPWM_PWMSYNC_SOURCE_ZERO        - Counter equals zero.
//!  - HRPWM_PWMSYNC_SOURCE_COMPC_UP    - Counter equals COMPC when
//!                                       counting up.
//!  - HRPWM_PWMSYNC_SOURCE_COMPC_DOWN  - Counter equals COMPC when
//!                                       counting down.
//!  - HRPWM_PWMSYNC_SOURCE_COMPD_UP    - Counter equals COMPD when
//!                                       counting up.
//!  - HRPWM_PWMSYNC_SOURCE_COMPD_DOWN  - Counter equals COMPD when
//!                                       counting down.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the PWMSYNC source
    //
    __eallow();

    //
    // Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD
    // or HRPWM_PWMSYNC_SOURCE_ZERO
    //
    if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) &
          ~(0x70U | 0x2U)) |
           ((uint16_t)syncPulseSource << 1U));
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) =
          (((*((volatile uint16_t *)((uintptr_t)(base + 0x2DU)))) & ~0x70U) |
           ((uint16_t)syncPulseSource << 4U));
    }
    __edis();
}

//*****************************************************************************
//
//! Sets the Translator Remainder value.
//!
//! \param base is the base address of the EPWM module.
//! \param trremVal is the translator remainder value.
//!
//! This function sets the Translator Remainder value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set Translator Remainder value
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2EU)))) = (trremVal & 0x7FFU);
    __edis();
}

//*****************************************************************************
//
//! Sets the consolidated counter compare values in HR mode.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module.
//! \param compCount is the consolidated counter compare count value.
//!
//! This function sets the consolidated counter compare(CMPx:CMPxHR) value
//! required in high resolution mode for counter compare registers.
//! Valid values for compModule are:
//!  - HRPWM_COUNTER_COMPARE_A - counter compare A.
//!  - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \b Note: compCount is a 24 bit value.
//! \b Note: For configuring CMPA = 0xB4, CMPAHR = 0x64; value of
//!          compCount = 0xB464
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setCounterCompareValue(uint32_t base,
                             HRPWM_CounterCompareModule compModule,
                             uint32_t compCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Write to counter compare registers
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Write to CMPA:CMPAHR
        //
        (*((volatile uint32_t *)((uintptr_t)(base + 0x6AU)))) = compCount << 8U;
    }
    else
    {
        //
        // Write to CMPB:CMPBHR
        //
        (*((volatile uint32_t *)((uintptr_t)(base + 0x6CU)))) = compCount << 8U;
    }
}

//*****************************************************************************
//
//! Sets only the high resolution counter compare value.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module.
//! \param hrCompCount is the high resolution counter compare count value.
//!
//! This function sets the high resolution counter compare value(CMPxHR) for
//! counter compare registers.
//! Valid values for compModule are:
//!  - HRPWM_COUNTER_COMPARE_A - counter compare A.
//!  - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \b Note: hrCompCount is an 8-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResCounterCompareValueOnly(uint32_t base,
                                      HRPWM_CounterCompareModule compModule,
                                      uint16_t hrCompCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Write to the high resolution counter compare registers
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Write to CMPAHR
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x6AU)))) = hrCompCount << 8U;
    }
    else
    {
        //
        // Write to CMPBHR
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x6CU)))) = hrCompCount << 8U;
    }
}

//*****************************************************************************
//
//! Gets the consolidated counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module value.
//!
//! This function gets the consolidated counter compare(CMPx:CMPxHR) value
//! used in high resolution for the counter compare module specified.
//! Valid values for compModule are:
//!  - HRPWM_COUNTER_COMPARE_A - counter compare A.
//!  - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//!
//! \return None.
//
//*****************************************************************************
static inline uint32_t
HRPWM_getCounterCompareValue(uint32_t base,
                             HRPWM_CounterCompareModule compModule)
{
    uint32_t compCount;

    //
    // Check the arguments
    //
    ;

    //
    // Get counter compare value for selected module
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Read from CMPAHR
        //
        compCount = (*((volatile uint32_t *)((uintptr_t)(base + 0x6AU)))) >> 8U;
    }
    else
    {
        //
        // Read from CMPBHR
        //
        compCount = (*((volatile uint32_t *)((uintptr_t)(base + 0x6CU)))) >> 8U;
    }
    return(compCount);
}

//*****************************************************************************
//
//! Gets only the high resolution counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module value.
//!
//! This function gets only the high resolution counter compare(CMPxHR) value
//! for the counter compare module specified.
//! Valid values for compModule are:
//!  - HRPWM_COUNTER_COMPARE_A - counter compare A.
//!  - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \return None.
//
//*****************************************************************************
static inline uint16_t
HRPWM_getHiResCounterCompareValueOnly(uint32_t base,
                                      HRPWM_CounterCompareModule compModule)
{
    uint16_t hrCompCount;

    //
    // Check the arguments
    //
    ;

    //
    // Get counter compare value for selected module
    //
    if(compModule == HRPWM_COUNTER_COMPARE_A)
    {
        //
        // Read from CMPAHR
        //
        hrCompCount = (*((volatile uint16_t *)((uintptr_t)(base + 0x6AU)))) >> 8U;
    }
    else
    {
        //
        // Read from CMPBHR
        //
        hrCompCount = (*((volatile uint16_t *)((uintptr_t)(base + 0x6CU)))) >> 8U;
    }
    return(hrCompCount);
}

//*****************************************************************************
//
//! Sets the consolidated RED count in high resolution mode.
//!
//! \param base is the base address of the EPWM module.
//! \param redCount is the high resolution RED count.
//!
//! This function sets the consolidated RED (Rising Edge Delay) count
//! (DBRED:DBREDHR) value used in high resolution mode. The value of
//! redCount should be less than 0x200000.
//!
//! \b Note: redCount is a 21 bit value.
//! \b Note: For configuring DBRED = 0x4, DBREDHR = 0x1; value of
//!          redCount = ((0x4 << 7) | 0x1) = 0x201
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setRisingEdgeDelay(uint32_t base, uint32_t redCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the consolidated RED (Rising Edge Delay) count
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x50U)))) = redCount << 9U;
}

//*****************************************************************************
//
//! Sets the high resolution RED count only.
//!
//! \param base is the base address of the EPWM module.
//! \param hrRedCount is the high resolution RED count.
//!
//! This function sets only the high resolution RED (Rising Edge Delay)
//! count(DBREDHR) value.
//! The value of hrRedCount should be less than 128.
//!
//! \b Note: hrRedCount is a 7-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResRisingEdgeDelayOnly(uint32_t base, uint16_t hrRedCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the High Resolution RED (Rising Edge Delay) count only
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x50U)))) = hrRedCount << 9U;
}

//*****************************************************************************
//
//! Sets the consolidated FED value in high resolution mode.
//!
//! \param base is the base address of the EPWM module.
//! \param fedCount is the high resolution FED count.
//!
//! This function sets the consolidated FED (Falling Edge Delay) count
//! (DBFED: DBFEDHR) value used in high resolution mode. The value of fedCount
//! should be less than 0x200000.
//!
//! \b Note: fedCount is a 21 bit value.
//! \b Note: For configuring DBFED = 0x4, DBFEDHR = 0x1; value of
//!          fedCount = ((0x4 << 7) | 0x1) = 0x201
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setFallingEdgeDelay(uint32_t base, uint32_t fedCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the High Resolution FED (Falling Edge Delay) count
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x52U)))) = fedCount << 9U;
}

//*****************************************************************************
//
//! Sets high resolution FED count only.
//!
//! \param base is the base address of the EPWM module.
//! \param hrFedCount is the high resolution FED count.
//!
//! This function sets only the high resolution FED (Falling Edge Delay) count
//! (DBFEDHR)value. The value of hrFedCount should be less than 128.
//!
//! \b Note: hrFedCount is a 7-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set the high resolution FED (Falling Edge Delay) count
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x52U)))) = hrFedCount << 9U;
}

//*****************************************************************************
//
//! Set high resolution MEP (Micro Edge Positioner) step.
//!
//! \param base is the base address of the EPWM module.
//! \param mepCount is the high resolution MEP (Micro Edge Positioner) step
//!        count.
//!
//! This function sets the high resolution MEP (Micro Edge Positioner) step
//! count. The maximum value for the MEP count step is 255.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
{
    //
    // Check the arguments
    //
    ;
    ;

    //
    // Set HRPWM MEP count
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x26U)))) =
             (((*((volatile uint16_t *)((uintptr_t)(base + 0x26U)))) & ~0xFFU) |
               mepCount);
    __edis();
}

//*****************************************************************************
//
//! Set high resolution Dead Band MEP (Micro Edge Positioner) control.
//!
//! \param base is the base address of the EPWM module.
//! \param mepDBEdge is the high resolution MEP (Micro Edge Positioner) control
//!        edge.
//!
//! This function sets the high resolution Dead Band edge that the MEP (Micro
//! Edge Positioner) controls Valid values for mepDBEdge are:
//!   - HRPWM_DB_MEP_CTRL_DISABLE  - HRPWM is disabled
//!   - HRPWM_DB_MEP_CTRL_RED      - MEP (Micro Edge Positioner) controls
//!                                  Rising Edge Delay
//!   - HRPWM_DB_MEP_CTRL_FED      - MEP (Micro Edge Positioner) controls
//!                                  Falling Edge Delay
//!   - HRPWM_DB_MEP_CTRL_RED_FED  - MEP (Micro Edge Positioner) controls both
//!                                  Falling and Rising edge delays
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setDeadbandMEPEdgeSelect(uint32_t base,
                               HRPWM_MEPDeadBandEdgeMode mepDBEdge)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the HRPWM DB edge mode
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x27U)))) =
       (((*((volatile uint16_t *)((uintptr_t)(base + 0x27U)))) & ~0x3U) |
         ((uint16_t)mepDBEdge));
    __edis();
}

//*****************************************************************************
//
//! Set the high resolution Dead Band RED load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadEvent is the shadow to active load event.
//!
//! This function sets the high resolution Rising Edge Delay(RED)Dead Band
//! count load mode.
//! Valid values for loadEvent are:
//!   - HRPWM_LOAD_ON_CNTR_ZERO        - load when counter equals zero.
//!   - HRPWM_LOAD_ON_CNTR_PERIOD      - load when counter equals period
//!   - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero
//!                                             or period.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setRisingEdgeDelayLoadMode(uint32_t base,
                                 HRPWM_LoadMode loadEvent)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the HRPWM RED load mode
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x27U)))) =
      (((*((volatile uint16_t *)((uintptr_t)(base + 0x27U)))) & ~0xCU) |
       ((uint16_t)loadEvent << 2U));
    __edis();
}

//*****************************************************************************
//
//! Set the high resolution Dead Band FED load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadEvent is the shadow to active load event.
//!
//! This function sets the high resolution Falling Edge Delay(FED) Dead Band
//! count load mode.
//! Valid values for loadEvent are:
//!   - HRPWM_LOAD_ON_CNTR_ZERO        - load when counter equals zero.
//!   - HRPWM_LOAD_ON_CNTR_PERIOD      - load when counter equals period
//!   - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero
//!                                             or period.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
{
    //
    // Check the arguments
    //
    ;

    //
    // Set the HRPWM FED load mode
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x27U)))) =
       (((*((volatile uint16_t *)((uintptr_t)(base + 0x27U)))) & ~0x30U) |
        ((uint16_t)loadEvent << 4U));
    __edis();
}

//*****************************************************************************
//
//! Lock EALLOW protected register groups
//!
//! \param base is the base address of the EPWM module.
//! \param registerGroup is the EALLOW register groups.
//!
//! This functions locks the EALLOW protected register groups specified by
//! the registerGroup variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_lockRegisters(uint32_t base, HRPWM_LockRegisterGroup registerGroup)
{
    //
    // Check the arguments
    //
    ;

    //
    // Write the Key to EPWMLOCK register
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0xFAU)))) =
                           ((uint32_t)0xA5A50000U | ((uint32_t)registerGroup));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   i2c.h
//
// TITLE:  C28x I2C driver.
//
//###########################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup i2c_api I2C
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_i2c.h
//
// TITLE:   Definitions for the I2C registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the I2C register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the I2COAR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CIER register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CSTR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CDRR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CSAR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CDXR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CMDR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CISRC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CEMDR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CPSC register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CFFTX register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CFFRX register
//
//*************************************************************************************************




//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************

//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************


//*****************************************************************************
//
// I2C interrupts for use with the intFlags parameter of I2C_enableInterrupt(),
// I2C_disableInterrupt(), and I2C_clearInterruptStatus() and to be returned by
// I2C_getInterruptStatus().
//
//*****************************************************************************

//
// Helpful define to mask out the bits in the I2CSTR register that aren't
// associated with interrupts.
//

//*****************************************************************************
//
// Flags for use as the stsFlags parameter of I2C_clearStatus() and to be
// returned by I2C_getStatus().
//
//*****************************************************************************

//*****************************************************************************
//
//! I2C interrupts to be returned by I2C_getInterruptSource().
//
//*****************************************************************************
typedef enum
{
    I2C_INTSRC_NONE,                //!< No interrupt pending
    I2C_INTSRC_ARB_LOST,            //!< Arbitration-lost interrupt
    I2C_INTSRC_NO_ACK,              //!< NACK interrupt
    I2C_INTSRC_REG_ACCESS_RDY,      //!< Register-access-ready interrupt
    I2C_INTSRC_RX_DATA_RDY,         //!< Receive-data-ready interrupt
    I2C_INTSRC_TX_DATA_RDY,         //!< Transmit-data-ready interrupt
    I2C_INTSRC_STOP_CONDITION,      //!< Stop condition detected
    I2C_INTSRC_ADDR_SLAVE           //!< Addressed as slave interrupt
} I2C_InterruptSource;

//*****************************************************************************
//
//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e txLevel
//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e txLevel
//! parameter, and returned by I2C_getTxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
    I2C_FIFO_TXEMPTY    = 0x0000U,      //!< Transmit FIFO empty
    I2C_FIFO_TX0        = 0x0000U,      //!< Transmit FIFO empty
    I2C_FIFO_TX1        = 0x0001U,      //!< Transmit FIFO 1/16 full
    I2C_FIFO_TX2        = 0x0002U,      //!< Transmit FIFO 2/16 full
    I2C_FIFO_TX3        = 0x0003U,      //!< Transmit FIFO 3/16 full
    I2C_FIFO_TX4        = 0x0004U,      //!< Transmit FIFO 4/16 full
    I2C_FIFO_TX5        = 0x0005U,      //!< Transmit FIFO 5/16 full
    I2C_FIFO_TX6        = 0x0006U,      //!< Transmit FIFO 6/16 full
    I2C_FIFO_TX7        = 0x0007U,      //!< Transmit FIFO 7/16 full
    I2C_FIFO_TX8        = 0x0008U,      //!< Transmit FIFO 8/16 full
    I2C_FIFO_TX9        = 0x0009U,      //!< Transmit FIFO 9/16 full
    I2C_FIFO_TX10       = 0x000AU,      //!< Transmit FIFO 10/16 full
    I2C_FIFO_TX11       = 0x000BU,      //!< Transmit FIFO 11/16 full
    I2C_FIFO_TX12       = 0x000CU,      //!< Transmit FIFO 12/16 full
    I2C_FIFO_TX13       = 0x000DU,      //!< Transmit FIFO 13/16 full
    I2C_FIFO_TX14       = 0x000EU,      //!< Transmit FIFO 14/16 full
    I2C_FIFO_TX15       = 0x000FU,      //!< Transmit FIFO 15/16 full
    I2C_FIFO_TX16       = 0x0010U,      //!< Transmit FIFO full
    I2C_FIFO_TXFULL     = 0x0010U       //!< Transmit FIFO full
} I2C_TxFIFOLevel;

//*****************************************************************************
//
//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e rxLevel
//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e rxLevel
//! parameter, and returned by I2C_getRxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
    I2C_FIFO_RXEMPTY    = 0x0000U,      //!< Receive FIFO empty
    I2C_FIFO_RX0        = 0x0000U,      //!< Receive FIFO empty
    I2C_FIFO_RX1        = 0x0001U,      //!< Receive FIFO 1/16 full
    I2C_FIFO_RX2        = 0x0002U,      //!< Receive FIFO 2/16 full
    I2C_FIFO_RX3        = 0x0003U,      //!< Receive FIFO 3/16 full
    I2C_FIFO_RX4        = 0x0004U,      //!< Receive FIFO 4/16 full
    I2C_FIFO_RX5        = 0x0005U,      //!< Receive FIFO 5/16 full
    I2C_FIFO_RX6        = 0x0006U,      //!< Receive FIFO 6/16 full
    I2C_FIFO_RX7        = 0x0007U,      //!< Receive FIFO 7/16 full
    I2C_FIFO_RX8        = 0x0008U,      //!< Receive FIFO 8/16 full
    I2C_FIFO_RX9        = 0x0009U,      //!< Receive FIFO 9/16 full
    I2C_FIFO_RX10       = 0x000AU,      //!< Receive FIFO 10/16 full
    I2C_FIFO_RX11       = 0x000BU,      //!< Receive FIFO 11/16 full
    I2C_FIFO_RX12       = 0x000CU,      //!< Receive FIFO 12/16 full
    I2C_FIFO_RX13       = 0x000DU,      //!< Receive FIFO 13/16 full
    I2C_FIFO_RX14       = 0x000EU,      //!< Receive FIFO 14/16 full
    I2C_FIFO_RX15       = 0x000FU,      //!< Receive FIFO 15/16 full
    I2C_FIFO_RX16       = 0x0010U,      //!< Receive FIFO full
    I2C_FIFO_RXFULL     = 0x0010U       //!< Receive FIFO full
} I2C_RxFIFOLevel;

//*****************************************************************************
//
//! Values that can be passed to I2C_setBitCount() as the \e size parameter.
//
//*****************************************************************************
typedef enum
{
    I2C_BITCOUNT_1  = 1U,   //!< 1 bit per data byte
    I2C_BITCOUNT_2  = 2U,   //!< 2 bits per data byte
    I2C_BITCOUNT_3  = 3U,   //!< 3 bits per data byte
    I2C_BITCOUNT_4  = 4U,   //!< 4 bits per data byte
    I2C_BITCOUNT_5  = 5U,   //!< 5 bits per data byte
    I2C_BITCOUNT_6  = 6U,   //!< 6 bits per data byte
    I2C_BITCOUNT_7  = 7U,   //!< 7 bits per data byte
    I2C_BITCOUNT_8  = 0U    //!< 8 bits per data byte
} I2C_BitCount;

//*****************************************************************************
//
//! Values that can be passed to I2C_setAddressMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    I2C_ADDR_MODE_7BITS        = 0x0000U,   //!< 7-bit address
    I2C_ADDR_MODE_10BITS       = 0x0100U    //!< 10-bit address
} I2C_AddressMode;

//*****************************************************************************
//
//! Values that can be passed to I2C_setExtendedMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    I2C_EADDR_MODE_BC  = 1U,   //!<  Backward compatibility
    I2C_EADDR_MODE_FWD = 2U    //!<  Forward compatibility
} I2C_ExtendedMode;

//*****************************************************************************
//
//! Values that can be passed to I2C_setEmulationMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! If SCL is low, keep it low. If high, stop when it goes low again.
    I2C_EMULATION_STOP_SCL_LOW = 0x0000U,
    //! Continue I2C operation regardless
    I2C_EMULATION_FREE_RUN     = 0x4000U
} I2C_EmulationMode;

//*****************************************************************************
//
//! Values that can be passed to I2C_initMaster() as the \e dutyCycle
//! parameter.
//
//*****************************************************************************
typedef enum
{
    I2C_DUTYCYCLE_33,       //!< Clock duty cycle is 33%
    I2C_DUTYCYCLE_50        //!< Clock duty cycle is 55%
} I2C_DutyCycle;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an I2C base address.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function determines if a I2C module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enables the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function enables operation of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_enableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) |= 0x20U;
}

//*****************************************************************************
//
//! Disables the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function disables operation of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_disableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) &= ~(0x20U);
}

//*****************************************************************************
//
//! Enables the transmit and receive FIFOs.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This functions enables the transmit and receive FIFOs in the I2C.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_enableFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) |= 0x4000U | 0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x21U)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Disables the transmit and receive FIFOs.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This functions disables the transmit and receive FIFOs in the I2C.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_disableFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) &= ~(0x4000U | 0x2000U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x21U)))) &= ~0x2000U;
}

//*****************************************************************************
//
//! Sets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the I2C instance used.
//! \param txLevel is the transmit FIFO interrupt level, specified as
//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, . . . or
//! \b I2C_FIFO_TX16.
//! \param rxLevel is the receive FIFO interrupt level, specified as
//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, . . . or
//! \b I2C_FIFO_RX16.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated.  The transmit FIFO interrupt flag will be set when the FIFO
//! reaches a value less than or equal to \e txLevel.  The receive FIFO
//! flag will be set when the FIFO reaches a value greater than or equal to
//! \e rxLevel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel txLevel,
                          I2C_RxFIFOLevel rxLevel)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the FIFO interrupt levels.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) &
                                 (~0x1FU)) | (uint16_t)txLevel;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x21U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x21U)))) &
                                 (~0x1FU)) | (uint16_t)rxLevel;
}

//*****************************************************************************
//
//! Gets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the I2C instance used.
//! \param txLevel is a pointer to storage for the transmit FIFO level,
//! returned as one of \b I2C_FIFO_TX0, \b I2C_FIFO_TX1,
//! \b I2C_FIFO_TX2, . . . or \b I2C_FIFO_TX16.
//! \param rxLevel is a pointer to storage for the receive FIFO level,
//! returned as one of \b I2C_FIFO_RX0, \b I2C_FIFO_RX1,
//! \b I2C_FIFO_RX2, . . . or \b I2C_FIFO_RX16.
//!
//! This function gets the FIFO level at which transmit and receive interrupts
//! are generated.  The transmit FIFO interrupt flag will be set when the FIFO
//! reaches a value less than or equal to \e txLevel.  The receive FIFO
//! flag will be set when the FIFO reaches a value greater than or equal to
//! \e rxLevel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_getFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel *txLevel,
                          I2C_RxFIFOLevel *rxLevel)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Extract the transmit and receive FIFO levels.
    //
    *txLevel = (I2C_TxFIFOLevel)((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) &
                                 0x1FU);
    *rxLevel = (I2C_RxFIFOLevel)((*((volatile uint16_t *)((uintptr_t)(base + 0x21U)))) &
                                 0x1FU);
}

//*****************************************************************************
//
//! Get the transmit FIFO status
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function gets the current number of words in the transmit FIFO.
//!
//! \return Returns the current number of words in the transmit FIFO specified
//! as one of the following:
//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, \b I2C_FIFO_TX3,
//! ..., or \b I2C_FIFO_TX16
//
//*****************************************************************************
static inline I2C_TxFIFOLevel
I2C_getTxFIFOStatus(uint32_t base)
{
    uint16_t level;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the current FIFO status
    //
    level = (((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) & 0x1F00U) >>
              8U);

    return((I2C_TxFIFOLevel)level);
}

//*****************************************************************************
//
//! Get the receive FIFO status
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function gets the current number of words in the receive FIFO.
//!
//! \return Returns the current number of words in the receive FIFO specified
//! as one of the following:
//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, \b I2C_FIFO_RX3,
//! ..., or \b I2C_FIFO_RX16
//
//*****************************************************************************
static inline I2C_RxFIFOLevel
I2C_getRxFIFOStatus(uint32_t base)
{
    uint16_t level;

    //
    // Check the arguments.
    //
    ;

    //
    // Get the current FIFO status
    //
    level = (((*((volatile uint16_t *)((uintptr_t)(base + 0x21U)))) & 0x1F00U) >>
              8U);

    return((I2C_RxFIFOLevel)level);
}

//*****************************************************************************
//
//! Reads I2C Module clock prescaler value.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function reads the I2C prescaler value which configures the I2C module
//! clock by dividing down the SYSCLK. I2C_MODULE_CLK = SYSCLK / (I2CPSC + )
//!
//! \return Returns the I2C prescaler(I2CPSC) cast as an uint16_t.
//
//*****************************************************************************
static inline uint16_t
I2C_getPreScaler(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the contents of the Prescaler register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))));
}

//*****************************************************************************
//
//! Sets the address that the I2C Master places on the bus.
//!
//! \param base is the base address of the I2C instance used.
//! \param slaveAddr 7-bit or 10-bit slave address
//!
//! This function configures the address that the I2C Master places on the bus
//! when initiating a transaction.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setSlaveAddress(uint32_t base, uint16_t slaveAddr)
{
    //
    // Check the arguments.
    //
    ;
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) = slaveAddr;
}

//*****************************************************************************
//
//! Sets the slave address for this I2C module.
//!
//! \param base is the base address of the I2C Slave module.
//! \param slaveAddr is the 7-bit or 10-bit slave address
//!
//! This function writes the specified slave address.
//!
//! The parameter \e slaveAddr is the value that is compared against the
//! slave address sent by an I2C master.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setOwnSlaveAddress(uint32_t base, uint16_t slaveAddr)
{
    //
    // Check the arguments.
    //
    ;
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = slaveAddr;
}

//*****************************************************************************
//
//! Indicates whether or not the I2C bus is busy.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns an indication of whether or not the I2C bus is busy.
//! This function can be used in a multi-master environment to determine if the
//! bus is free for another data transfer.
//!
//! \return Returns \b true if the I2C bus is busy; otherwise, returns
//! \b false.
//
//*****************************************************************************
static inline _Bool
I2C_isBusBusy(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) & 0x1000U) == 0x1000U);
}

//*****************************************************************************
//
//! Gets the current I2C module status.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns the status for the I2C module.
//!
//! \return The current module status, enumerated as a bit field of
//! - \b I2C_STS_ARB_LOST - Arbitration-lost
//! - \b I2C_STS_NO_ACK - No-acknowledgment (NACK)
//! - \b I2C_STS_REG_ACCESS_RDY - Register-access-ready (ARDY)
//! - \b I2C_STS_RX_DATA_RDY - Receive-data-ready
//! - \b I2C_STS_TX_DATA_RDY - Transmit-data-ready
//! - \b I2C_STS_STOP_CONDITION - Stop condition detected
//! - \b I2C_STS_BYTE_SENT - Byte transmit complete
//! - \b I2C_STS_ADDR_ZERO - Address of all zeros detected
//! - \b I2C_STS_ADDR_SLAVE - Addressed as slave
//! - \b I2C_STS_TX_EMPTY - Transmit shift register empty
//! - \b I2C_STS_RX_FULL - Receive shift register full
//! - \b I2C_STS_BUS_BUSY - Bus busy, wait for STOP or reset
//! - \b I2C_STS_NACK_SENT - NACK was sent
//! - \b I2C_STS_SLAVE_DIR- Addressed as slave transmitter
//
//*****************************************************************************
static inline uint16_t
I2C_getStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return contents of the status register
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))));
}

//*****************************************************************************
//
//! Clears I2C status flags.
//!
//! \param base is the base address of the I2C instance used.
//! \param stsFlags is a bit mask of the status flags to be cleared.
//!
//! This function clears the specified I2C status flags. The \e stsFlags
//! parameter is the logical OR of the following values:
//! - \b I2C_STS_ARB_LOST
//! - \b I2C_STS_NO_ACK,
//! - \b I2C_STS_REG_ACCESS_RDY
//! - \b I2C_STS_RX_DATA_RDY
//! - \b I2C_STS_STOP_CONDITION
//! - \b I2C_STS_BYTE_SENT
//! - \b I2C_STS_NACK_SENT
//! - \b I2C_STS_SLAVE_DIR
//!
//! \note Note that some of the status flags returned by I2C_getStatus() cannot
//! be cleared by this function. Some may only be cleared by hardware or a
//! reset of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_clearStatus(uint32_t base, uint16_t stsFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write to the status registers to clear them.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) = stsFlags;
}

//*****************************************************************************
//
//! Controls the state of the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//! \param config is the command to be issued to the I2C  module.
//!
//! This function is used to control the state of the master and slave send and
//! receive operations. The \e config is a logical OR of the following options.
//!
//! One of the following four options:
//! - \b I2C_MASTER_SEND_MODE - Master-transmitter mode
//! - \b I2C_MASTER_RECEIVE_MODE - Master-receiver mode
//! - \b I2C_SLAVE_SEND_MODE - Slave-transmitter mode
//! - \b I2C_SLAVE_RECEIVE_MODE - Slave-receiver mode
//!
//! Any of the following:
//! - \b I2C_REPEAT_MODE - Sends data until stop bit is set, ignores data count
//! - \b I2C_START_BYTE_MODE - Use start byte mode
//! - \b I2C_FREE_DATA_FORMAT - Use free data format, transfers have no address
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setConfig(uint32_t base, uint16_t config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the selected options to the mode register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) &
                                ~(0x400U | 0x200U | 0x80U |
                                  0x10U | 0x8U)) | config;
}

//*****************************************************************************
//
//! Sets the data byte bit count the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//! \param size is the number of bits per data byte.
//!
//! The \e size parameter is a value I2C_BITCOUNT_x where x is the number of
//! bits per data byte.  The default and maximum size is 8 bits.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setBitCount(uint32_t base, I2C_BitCount size)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the selected options to the mode register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) & ~0x7U) |
                               (uint16_t)size;
}

//*****************************************************************************
//
//! Issues an I2C START condition.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function causes the I2C module to generate a start condition. This
//! function is only valid when the I2C module specified by the \b base
//! parameter is a master.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_sendStartCondition(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the START condition bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Issues an I2C STOP condition.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function causes the I2C module to generate a stop condition. This
//! function is only valid when the I2C module specified by the \b base
//! parameter is a master.
//!
//! To check on the status of the STOP condition, I2C_getStopConditionStatus()
//! can be used.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_sendStopCondition(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the STOP condition bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) |= 0x800U;
}

//*****************************************************************************
//
//! Issues a no-acknowledge (NACK) bit.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function causes the I2C module to generate a NACK bit. This is only
//! applicable when the I2C module is acting as a receiver.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_sendNACK(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the NACK mode bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) |= 0x8000U;
}

//*****************************************************************************
//
//! Receives a byte that has been sent to the I2C.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function reads a byte of data from the I2C Data Receive Register.
//!
//! \return Returns the byte received from by the I2C cast as an uint16_t.
//
//*****************************************************************************
static inline uint16_t
I2C_getData(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the contents of the receive register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))));
}

//*****************************************************************************
//
//! Transmits a byte from the I2C.
//!
//! \param base is the base address of the I2C instance used.
//! \param data is the data to be transmitted from the I2C Master.
//!
//! This function places the supplied data into I2C Data Transmit Register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_putData(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Place the data into the transmit register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) = data;
}

//*****************************************************************************
//
//! Get stop condition status.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function reads and returns the stop condition bit status.
//!
//! \return Returns \b true if the STP bit has been set by the device to
//! generate a stop condition when the internal data counter of the I2C module
//! has reached 0. Returns \b false when the STP bit is zero. This bit is
//! automatically cleared after the stop condition has been generated.
//
//*****************************************************************************
static inline _Bool
I2C_getStopConditionStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Check the stop condition bit and return appropriately.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) & 0x800U) != 0U);
}

//*****************************************************************************
//
//! Set number of bytes to be to transfer or receive when repeat mode is off.
//!
//! \param base is the base address of the I2C instance used.
//! \param count is the value to be put in the I2C data count register.
//!
//! This function sets the number of bytes to transfer or receive when repeat
//! mode is off.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setDataCount(uint32_t base, uint16_t count)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the count value to the appropriate register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) = count;
}

//*****************************************************************************
//
//! Sets the addressing mode to either 7-bit or 10-bit.
//!
//! \param base is the base address of the I2C instance used.
//! \param mode is the address mode, 7-bit or 10-bit.
//!
//! This function configures the I2C module for either a 7-bit address
//! (default) or a 10-bit address. The \e mode parameter configures the address
//! length to 10 bits when its value is \b I2C_ADDR_MODE_10BITS and 7 bits when
//! \b I2C_ADDR_MODE_7BITS.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setAddressMode(uint32_t base, I2C_AddressMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the appropriate value to the address expansion bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) & ~0x100U) |
                               (uint16_t)mode;
}

//*****************************************************************************
//
//! Sets I2C emulation mode.
//!
//! \param base is the base address of the I2C instance used.
//! \param mode is the emulation mode.
//!
//! This function sets the behavior of the I2C operation when an emulation
//! suspend occurs. The \e mode parameter can be one of the following:
//!
//! - \b I2C_EMULATION_STOP_SCL_LOW - If SCL is low when the breakpoint occurs,
//!   the I2C module stops immediately. If SCL is high, the I2C module waits
//!   until SCL becomes low and then stops.
//! - \b I2C_EMULATION_FREE_RUN - I2C operation continues regardless of a
//!   the suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setEmulationMode(uint32_t base, I2C_EmulationMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the desired emulation mode to the register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) & ~0x4000U) |
                               (uint16_t)mode;
}

//*****************************************************************************
//
//! Enables I2C loopback mode.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function enables loopback mode. This mode is only valid during master
//! mode and is helpful during device testing as it causes data transmitted out
//! of the data transmit register to be received in data receive register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_enableLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that enables loopback mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) |= 0x40U;
}

//*****************************************************************************
//
//! Disables I2C loopback mode.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function disables loopback mode. Loopback mode is disabled by default
//! after reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_disableLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the bit that enables loopback mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) &= ~0x40U;
}

//*****************************************************************************
//
//! Returns the current I2C interrupt source.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns the event that generated an I2C basic (non-FIFO)
//! interrupt. The possible sources are the following:
//! - \b I2C_INTSRC_NONE
//! - \b I2C_INTSRC_ARB_LOST
//! - \b I2C_INTSRC_NO_ACK
//! - \b I2C_INTSRC_REG_ACCESS_RDY
//! - \b I2C_INTSRC_RX_DATA_RDY
//! - \b I2C_INTSRC_TX_DATA_RDY
//! - \b I2C_INTSRC_STOP_CONDITION
//! - \b I2C_INTSRC_ADDR_SLAVE
//!
//! Calling this function will result in hardware automatically clearing the
//! current interrupt code and if ready, loading the next pending enabled
//! interrupt. It will also clear the corresponding interrupt flag if the
//! source is \b I2C_INTSRC_ARB_LOST, \b I2C_INTSRC_NO_ACK, or
//! \b I2C_INTSRC_STOP_CONDITION.
//!
//! \note Note that this function differs from I2C_getInterruptStatus() in that
//! it returns a single interrupt source. I2C_getInterruptSource() will return
//! the status of all interrupt flags possible, including the flags that aren't
//! necessarily enabled to generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline I2C_InterruptSource
I2C_getInterruptSource(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the interrupt source value
    //
    return((I2C_InterruptSource)((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &
                                 0x7U));
}

//*****************************************************************************
//
//! Sets the compatibility mode to support I2C Extended Mode.
//!
//! \param base is the base address of the I2C instance used.
//! \param mode is the compatibility modes.
//!
//! This function configures the I2C module for either a Forward or Backward
//! compatibilty. The \e mode parameter configures the compatibility
//! to Forward when its value is \b I2C_EADDR_MODE_FWD and Backward when
//! \b I2C_EADDR_MODE_BC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setExtendedMode(uint32_t base, I2C_ExtendedMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the appropriate value to the compatibility mode register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) =
   ((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) & ~(0x1U | 0x2U)) |
   (uint16_t)mode;
}

//*****************************************************************************
//
//! Initializes the I2C Master.
//!
//! \param base is the base address of the I2C instance used.
//! \param sysclkHz is the rate of the clock supplied to the I2C module
//! (SYSCLK) in Hz.
//! \param bitRate is the rate of the master clock signal, SCL.
//! \param dutyCycle is duty cycle of the SCL signal.
//!
//! This function initializes operation of the I2C Master by configuring the
//! bus speed for the master. Note that the I2C module \b must be put into
//! reset before calling this function. You can do this with the function
//! I2C_disableModule().
//!
//! A programmable prescaler in the I2C module divides down the input clock
//! (rate specified by \e sysclkHz) to produce the module clock (calculated to
//! be around 10 MHz in this function). That clock is then divided down further
//! to configure the SCL signal to run at the rate specified by \e bitRate. The
//! \e dutyCycle parameter determines the percentage of time high and time low
//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and
//! \b I2C_DUTYCYCLE_50 for 50%.
//!
//! The peripheral clock is the system clock.  This value is returned by
//! SysCtl_getClock(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtl_getClock()).
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_initMaster(uint32_t base, uint32_t sysclkHz, uint32_t bitRate,
               I2C_DutyCycle dutyCycle);

//*****************************************************************************
//
//! Enables I2C interrupt sources.
//!
//! \param base is the base address of the I2C instance used.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated I2C Master interrupt sources.  Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//!
//! - \b I2C_INT_ARB_LOST - Arbitration-lost interrupt
//! - \b I2C_INT_NO_ACK - No-acknowledgment (NACK) interrupt
//! - \b I2C_INT_REG_ACCESS_RDY - Register-access-ready interrupt
//! - \b I2C_INT_RX_DATA_RDY - Receive-data-ready interrupt
//! - \b I2C_INT_TX_DATA_RDY - Transmit-data-ready interrupt
//! - \b I2C_INT_STOP_CONDITION - Stop condition detected
//! - \b I2C_INT_ADDR_SLAVE - Addressed as slave interrupt
//! - \b I2C_INT_RXFF - RX FIFO level interrupt
//! - \b I2C_INT_TXFF - TX FIFO level interrupt
//!
//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO
//! interrupt vector. All others are associated with the I2C basic interrupt.
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_enableInterrupt(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Disables I2C interrupt sources.
//!
//! \param base is the base address of the I2C instance used.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated I2C Slave interrupt sources.  Only
//! the sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to I2C_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_disableInterrupt(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Gets the current I2C interrupt status.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns the interrupt status for the I2C module.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! - \b I2C_INT_ARB_LOST
//! - \b I2C_INT_NO_ACK
//! - \b I2C_INT_REG_ACCESS_RDY
//! - \b I2C_INT_RX_DATA_RDY
//! - \b I2C_INT_TX_DATA_RDY
//! - \b I2C_INT_STOP_CONDITION
//! - \b I2C_INT_ADDR_SLAVE
//! - \b I2C_INT_RXFF
//! - \b I2C_INT_TXFF
//!
//! \note This function will only return the status flags associated with
//! interrupts. However, a flag may be set even if its corresponding interrupt
//! is disabled.
//
//*****************************************************************************
extern uint32_t
I2C_getInterruptStatus(uint32_t base);

//*****************************************************************************
//
//! Clears I2C interrupt sources.
//!
//! \param base is the base address of the I2C instance used.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified I2C interrupt sources are cleared, so that they no longer
//! assert.  This function must be called in the interrupt handler to keep the
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to I2C_enableInterrupt().
//!
//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO
//! interrupt vector. All others are associated with the I2C basic interrupt.
//!
//! \note Also note that some of the status flags returned by
//! I2C_getInterruptStatus() cannot be cleared by this function. Some may only
//! be cleared by hardware or a reset of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Configures I2C Module Clock Frequency
//!
//! \param base is the base address of the I2C instance used.
//! \param sysclkHz is the rate of the clock supplied to the I2C module
//! (SYSCLK) in Hz.
//!
//! This function configures I2C module clock frequency by initializing 
//! prescale register based on SYSCLK frequency.
//! Note that the I2C module \b must be put into
//! reset before calling this function. You can do this with the function
//! I2C_disableModule().
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   lin.h
//
// TITLE:  C28x LIN driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************


//*****************************************************************************
//
//! \addtogroup lin_api LIN
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_lin.h
//
// TITLE:   Definitions for the LIN registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the LIN register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIGCR0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIGCR1 register
//
//*************************************************************************************************
                                                // mode.

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIGCR2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCISETINT register
//
//*************************************************************************************************
                                                     // mode)
                                                     // (LIN only)
                                                     // Interrupt (LIN only)
                                                     // (LIN only)

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICLEARINT register
//
//*************************************************************************************************
                                                      // compatible mode
                                                      // Interrupt (LIN only)
                                                      // Interrupt (LIN only)
                                                      // only)
                                                      // Interrupt (LIN only)
                                                      // only)

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCISETINTLVL register
//
//*************************************************************************************************
                                                          // compatible mode)
                                                          // Interrupt Level (LIN only)
                                                          // Interrupt Level
                                                          // only)
                                                          // (LIN only)
                                                          // Interrupt Level
                                                          // (LIN only)
                                                          // (LIN only)
                                                          // only)

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICLEARINTLVL register
//
//*************************************************************************************************
                                                            // (SCI compatible mode)
                                                            // only)
                                                            // Interrupt Level (LIN only)
                                                            // (LIN only)
                                                            // Level (LIN only)
                                                            // (LIN only)
                                                            // Level (LIN only)
                                                            // only)

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIINTVECT0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIINTVECT1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFORMAT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the BRSR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIED register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCITD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIPIO0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIPIO2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LINCOMP register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LINRD0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LINRD1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LINMASK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LINID register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LINTD0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LINTD1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MBRSR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the IODFTCTRL register
//
//*************************************************************************************************
                                                      // compatibility mode)
                                                      // mode)
                                                      // mode)
                                                      // mode)

//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_GLB_INT_EN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_GLB_INT_FLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_GLB_INT_CLR register
//
//*************************************************************************************************




//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************
//
// The IO DFT Enable Key
//

//
// LIN Wakeup Signal Key
//

//
// LIN Parity ID Masks
//

//*****************************************************************************
//
// Definitions for the intFlags parameter of LIN_enableInterrupt(),
// LIN_disableInterrupt(), LIN_clearInterruptStatus(),
// LIN_setInterruptLevel0() and LIN_setInterruptLevel1().
//
//*****************************************************************************

//*****************************************************************************
//
// Definitions for the return value of LIN_getInterruptStatus().
//
//*****************************************************************************
                                                  //!< signal
                                                  //!< signals
                                                  //!< Method Select
                                                  //!< Error

//*****************************************************************************
//
// Definitions for the return value of LIN_getInterruptLine0Offset() and
// LIN_getInterruptLine1Offset().
//
//*****************************************************************************

//*****************************************************************************
//
// Definitions for the LIN errors parameter of LIN_enableModuleErrors() and
// LIN_disableModuleErrors().
//
//*****************************************************************************

//*****************************************************************************
//
// Definitions for the SCI errors parameter of LIN_enableSCIModuleErrors() and
// LIN_disableSCIModuleErrors().
//
//*****************************************************************************

//*****************************************************************************
//
// Definitions for the intFlags parameter of LIN_enableSCIInterrupt(),
// LIN_disableSCIInterrupt(), LIN_clearSCIInterruptStatus(),
// LIN_setSCIInterruptLevel0() and LIN_setSCIInterruptLevel1().
//
//*****************************************************************************


//*****************************************************************************
//
//! The following are defines for the \e type parameter of the
//! LIN_enableExtLoopback() function.
//
//*****************************************************************************
typedef enum
{
    LIN_LOOPBACK_DIGITAL = 0U,    //!< Digital Loopback Mode
    LIN_LOOPBACK_ANALOG  = 2U     //!< Analog Loopback Mode
} LIN_LoopbackType;

//*****************************************************************************
//
//! The following are defines for the \e path parameter of the
//! LIN_enableExtLoopback() function.
//
//*****************************************************************************
typedef enum
{
    LIN_ANALOG_LOOP_NONE = 0U,    //!< Default path for digital loopback mode
    LIN_ANALOG_LOOP_TX   = 0U,    //!< Analog loopback through transmit pin
    LIN_ANALOG_LOOP_RX   = 1U     //!< Analog loopback through receive pin
} LIN_AnalogLoopback;

//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the
//! LIN_setCommMode() function.
//
//*****************************************************************************
typedef enum
{
    //! Use the length indicated in the LENGTH field of the SCIFORMAT register
    LIN_COMM_LIN_USELENGTHVAL = 0x0000U,

    //! Use ID4 and ID5 to convey the length
    LIN_COMM_LIN_ID4ID5LENCTL = 0x0001U
} LIN_CommMode;

//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the
//! LIN_setSCICommMode() function.
//
//*****************************************************************************
typedef enum
{
    //! Idle-line mode is used
    LIN_COMM_SCI_IDLELINE     = 0x0000U,

    //! Address bit mode is used
    LIN_COMM_SCI_ADDRBIT      = 0x0001U
} LIN_SCICommMode;

//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the LIN_setLINMode()
//! function.
//
//*****************************************************************************
typedef enum
{
    LIN_MODE_LIN_SLAVE        = 0x0000U,    //!< The node is in slave mode
    LIN_MODE_LIN_MASTER       = 0x0020U     //!< The node is in master mode
} LIN_LINMode;

//*****************************************************************************
//
//! The following are defines for the \e line parameter of the
//! LIN_enableGlobalInterrupt(), LIN_disableGlobalInterrupt(),
//! LIN_clearGlobalInterruptStatus(), and LIN_getGlobalInterruptStatus()
//! functions.
//
//*****************************************************************************
typedef enum
{
    LIN_INTERRUPT_LINE0       = 0x0U,    //!< Interrupt line 0
    LIN_INTERRUPT_LINE1       = 0x1U     //!< Interrupt line 1
} LIN_InterruptLine;

//*****************************************************************************
//
//! The following are defines for the \e type parameter of the
//! LIN_setMessageFiltering() function.
//
//*****************************************************************************
typedef enum
{
    LIN_MSG_FILTER_IDBYTE  = 0x0U,    //!< LIN Message ID Byte Filtering
    LIN_MSG_FILTER_IDSLAVE = 0x1U     //!< Slave Task ID Byte Filtering
} LIN_MessageFilter;

//*****************************************************************************
//
//! The following are defines for the \e type parameter of the
//! LIN_setChecksumType() function.
//
//*****************************************************************************
typedef enum
{
    LIN_CHECKSUM_CLASSIC  = 0x0U,    //!< Checksum Classic
    LIN_CHECKSUM_ENHANCED = 0x1U     //!< Checksum Enhanced
} LIN_ChecksumType;

//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the
//! LIN_setDebugSuspendMode() function.
//
//*****************************************************************************
typedef enum
{
    LIN_DEBUG_FROZEN   = 0x0U,    //!< Freeze module during debug
    LIN_DEBUG_COMPLETE = 0x1U     //!< Complete Tx/Rx before Freezing
} LIN_DebugMode;

//*****************************************************************************
//
//! The following are defines for the \e mask parameter of the
//! LIN_setPinSampleMask() function.
//
//*****************************************************************************
typedef enum
{
    //! No Pin Mask
    LIN_PINMASK_NONE         = 0x0U,

    //! Invert Tx Pin value at T-bit center
    LIN_PINMASK_CENTER       = 0x1U,

    //! Invert Tx Pin value at T-bit center + SCLK
    LIN_PINMASK_CENTER_SCLK  = 0x2U,

    //! Invert Tx Pin value at T-bit center + 2 SCLK
    LIN_PINMASK_CENTER_2SCLK = 0x3U
} LIN_PinSampleMask;

//*****************************************************************************
//
//! The following are defines for the \e parity parameter of the
//! LIN_enableSCIParity() function.
//
//*****************************************************************************
typedef enum
{
    LIN_SCI_PAR_ODD   = 0x0U,  //!< Odd parity
    LIN_SCI_PAR_EVEN  = 0x1U   //!< Even parity
} LIN_SCIParityType;

//*****************************************************************************
//
//! The following are defines for the \e number parameter of the
//! LIN_setSCIStopBits() function.
//
//*****************************************************************************
typedef enum
{
    LIN_SCI_STOP_ONE   = 0x0U,  //!< Use One Stop bit
    LIN_SCI_STOP_TWO   = 0x1U   //!< Use Two Stop bits
} LIN_SCIStopBits;

//*****************************************************************************
//
//! The following are defines for the \e pin parameter of the
//! LIN_getPinStatus() function.
//
//*****************************************************************************
typedef enum
{
    LIN_PINTYPE_TX = 0x4U,    //!< Transmit Pin
    LIN_PINTYPE_RX = 0x2U     //!< Receive Pin
} LIN_PinType;

//*****************************************************************************
//
// Prototypes for the LIN mode APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//!
//! Checks a LIN base address.
//!
//! \param base is the base address of the LIN controller.
//!
//! This function determines if a LIN controller base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets the LIN mode
//!
//! \param base is the LIN module base address
//! \param mode is the desired mode (slave or master)
//!
//! In LIN mode only, this function sets the mode of the LIN mode to either
//! slave or master. The \e mode parameter should be passed a value of
//! \b LIN_MODE_LIN_SLAVE or \b LIN_MODE_LIN_MASTER to configure the mode of
//! the LIN module specified by \e base.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setLINMode(uint32_t base, LIN_LINMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the LIN mode to the appropriate register.
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                                   ~0x20U) | (uint16_t)mode;

    __edis();
}

//*****************************************************************************
//
//! Set Maximum Baud Rate Prescaler
//!
//! \param base is the LIN module base address
//! \param clock is the device system clock (Hz)
//!
//! In LIN mode only, this function is used to set the maximum baud rate
//! prescaler used during synchronization phase of a slave module if the
//! ADAPT bit is set. The maximum baud rate prescaler is used by the wakeup
//! and idle timer counters for a constant 4 second expiration time relative
//! to a 20kHz rate.
//!
//! \note Use LIN_enableAutomaticBaudrate() to set the ADAPT bit and enable
//! automatic bit rate mod detection.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setMaximumBaudRate(uint32_t base, uint32_t clock)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Calculate maximum baud rate prescaler
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x7CU)))) = (uint16_t)(clock / 20000U);
}

//*****************************************************************************
//
//! Set Message filtering Type
//!
//! \param base is the LIN module base address
//! \param type is the mask filtering comparison type
//!
//! In LIN mode only, this function sets the message filtering type. The \e
//! type parameter can be one of the following values:
//! - \b LIN_MSG_FILTER_IDBYTE   - Filtering uses LIN message ID Byte
//! - \b LIN_MSG_FILTER_IDSLAVE  - Filtering uses the Slave Task ID Byte
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setMessageFiltering(uint32_t base, LIN_MessageFilter type)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Sets the message filtering type
    //
    if(type == LIN_MSG_FILTER_IDBYTE)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x1000U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x1000U;
    }
}

//*****************************************************************************
//
//! Enable Parity mode.
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the parity check.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableParity(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the parity mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x4U;
}

//*****************************************************************************
//
//! Disable Parity mode.
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function disables the parity check.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableParity(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the parity mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x4U);
}

//*****************************************************************************
//
//! Generate Parity Identifier
//! \param identifier is the LIN header ID byte
//!
//! In LIN mode only, this function generates the identifier parity bits and
//! appends them to the identifier.
//!
//! \note An ID must be generated with parity before header generation in
//! LIN master mode when parity is enabled using the function
//! LIN_enableParity().
//!
//! \return Returns the identifier appended with parity bits.
//
//*****************************************************************************
static inline uint16_t
LIN_generateParityID(uint16_t identifier)
{

    uint16_t p0, p1, parityIdentifier;

    //
    // Calculate parity bits and generate updated identifier
    //
    p0 = ((identifier & (0x1U)) ^ ((identifier & (0x2U)) >> 1U) ^
          ((identifier & (0x4U)) >> 2U) ^ ((identifier & (0x10U)) >> 4U));
    p1 = !(((identifier & (0x2U)) >> 1U) ^ ((identifier & (0x8U)) >> 3U) ^
           ((identifier & (0x10U)) >> 4U) ^ ((identifier & (0x20U)) >> 5U));
    parityIdentifier = identifier | ((p0 << 6U) | (p1 << 7U));

    return(parityIdentifier);
}

//*****************************************************************************
//
//! Set ID Byte
//!
//! \param base is the LIN module base address
//! \param identifier is the LIN header ID byte
//!
//! In LIN mode only, this function sets the message ID byte. In master mode,
//! writing to this ID initiates a header transmission. In slave task, this
//! ID is used for message filtering when HGENCTRL is 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setIDByte(uint32_t base, uint16_t identifier)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x70U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x70U)))) & ~(0xFFU)) |
                               (identifier & 0xFFU);
}

//*****************************************************************************
//
//! Set ID-SlaveTask
//!
//! \param base is the LIN module base address
//! \param identifier is the Received ID comparison ID
//!
//! In LIN mode only, this function sets the identifier to which the received
//! ID of an incoming Header will be compared in order to decide whether a RX
//! response, a TX response, or no action is required.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setIDSlaveTask(uint32_t base, uint16_t identifier)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x70U)))) = (((*((volatile uint16_t *)((uintptr_t)(base + 0x70U)))) &
                               ~(0xFF00U)) |
                              ((identifier & 0xFFU) <<
                               8U));
}

//*****************************************************************************
//
//! Send LIN wakeup signal
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function sends the LIN wakeup signal to terminate
//! the sleep mode of any LIN node connected to the bus.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_sendWakeupSignal(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set key in Byte 0 (MSB) of transmit buffer 0 register
    //
    __byte((int16_t *)(base + 0x74U + 0x3U),0) = (uint16_t)(0xF0U);

    //
    // Transmit TDO for wakeup
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) |= 0x100U;
}

//*****************************************************************************
//
//! Enter LIN Sleep Mode.
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function puts the LIN module into a low-power, sleep
//! mode. This can also be called to forcefully enter sleep when there is no
//! activity on the bus.
//!
//! \note If this function is called while the receiver is actively receiving
//! data and the wakeup interrupt is disabled, then the module will delay
//! sleep mode from being entered until completion of reception.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enterSleep(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Send Checksum Byte
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the transmitter with extended
//! frames to send a checkbyte.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_sendChecksum(uint32_t base)
{
    __byte_peripheral_32((uint32_t *)(base + 0x8U)) |= 0x10000U;
}

//*****************************************************************************
//
//! Trigger Checksum Compare
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the receiver for extended frames
//! to trigger a checksum compare.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_triggerChecksumCompare(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __byte_peripheral_32((uint32_t *)(base + 0x8U)) |= 0x20000U;
}

//*****************************************************************************
//
//! Check Tx buffer ready flag
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function checks to see if the Tx ready flag is set
//! indicating that the Tx buffer(s) is/are ready to get another character.
//!
//! \return Returns \b true if the TX ready flag is set, else returns \b false
//
//*****************************************************************************
static inline _Bool
LIN_isTxReady(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read Tx Buffer flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x100U) ==
           0x100U);
}

//*****************************************************************************
//
//! Set LIN Frame Length
//!
//! \param base is the LIN module base address
//! \param length is the number of bytes.
//!
//! In LIN mode only, this function sets the number of bytes in the response
//! field.
//!
//! The \e length parameter must be in a range between 1 and 8.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setFrameLength(uint32_t base, uint16_t length)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear and set frame length value
    //
    __byte_peripheral_32((uint32_t *)(base + 0x28U)) &= ~(0x70000U);
    __byte_peripheral_32((uint32_t *)(base + 0x28U)) |= ((((uint32_t)length - (uint32_t)1U) <<
                                         16U));
}

//*****************************************************************************
//
//! Set LIN communication mode
//!
//! \param base is the LIN module base address
//! \param mode is the selected communication mode
//!
//! In LIN mode only, this function is used to choose how the length of data is
//! conveyed. This choice relates to the version of LIN being used. The \e mode
//! parameter can have one of two values:
//! - \b LIN_COMM_LIN_USELENGTHVAL will use the length set with the
//!   LIN_setFrameLength() function.
//! - \b LIN_COMM_LIN_ID4ID5LENCTL will use ID4 and ID5 for length control.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setCommMode(uint32_t base, LIN_CommMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write communication mode selection to the appropriate bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                                    ~0x1U) | (uint16_t)mode;
}

//*****************************************************************************
//
//! Sets the transmit ID mask
//!
//! \param base is the LIN module base address
//! \param mask is the mask value to be set
//!
//! In LIN mode only, this function sets the mask used for filtering an
//! incoming ID message to determine if the TX ID flag should be set.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setTxMask(uint32_t base, uint16_t mask)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear previous mask value and set new mask
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6CU)))) &= ~(0xFFU);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6CU)))) |= (mask & 0xFFU);
}

//*****************************************************************************
//
//! Sets the receive ID mask
//!
//! \param base is the LIN module base address
//! \param mask is the mask value to be set
//!
//! In LIN mode only, this function sets the mask used for filtering an
//! incoming ID message to determine if the ID RX flag should be set.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setRxMask(uint32_t base, uint16_t mask)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear previous mask value and set new mask
    //
    __byte_peripheral_32((uint32_t *)(base + 0x6CU)) &= ~(0xFF0000U);
    __byte_peripheral_32((uint32_t *)(base + 0x6CU)) |= ((uint32_t)mask << 16U) &
                                   0xFF0000U;
}

//*****************************************************************************
//
//! Gets the transmit ID mask
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function gets the mask used for filtering an
//! incoming ID message to determine if the TX ID flag should be set.
//!
//! \return Returns the Transmit ID Mask.
//
//*****************************************************************************
static inline uint16_t
LIN_getTxMask(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((*((volatile uint16_t *)((uintptr_t)(base + 0x6CU)))) & 0xFFU);
}

//*****************************************************************************
//
//! Gets the receive ID mask
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function gets the mask used for filtering an
//! incoming ID message to determine if the ID RX flag should be set.
//!
//! \return Returns the Receive ID Mask.
//
//*****************************************************************************
static inline uint16_t
LIN_getRxMask(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((uint16_t)((__byte_peripheral_32((uint32_t *)(base + 0x6CU)) & 0xFF0000U) >>
                      16U));
}

//*****************************************************************************
//
//! Check if Rx data is ready
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, checks to see if the Rx ready bit is set indicating that
//! a valid message frame has been received.
//!
//! \return Returns \b true if the Rx ready flag is set, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isRxReady(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Ready Rx ready flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x200U) ==
           0x200U);
}

//*****************************************************************************
//
//! Get last received identifier
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function gets the last received identifier.
//!
//! \return Returns the Received Identifier.
//
//*****************************************************************************
static inline uint16_t
LIN_getRxIdentifier(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    return((uint16_t)((__byte_peripheral_32((uint32_t *)(base + 0x70U)) & 0xFF0000U) >>
                      16U));
}

//*****************************************************************************
//
//!  Checks for Tx ID Match Received
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function checks if an ID is received with a TX match
//! and no ID-parity error.
//!
//! \return Returns \b true if a valid ID is matched, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isTxMatch(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read Tx ID flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x2000U) ==
           0x2000U);
}

//*****************************************************************************
//
//! Checks for Rx ID Match Received
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function checks if an ID is received with a RX match
//! and no ID-parity error.
//!
//! \return Returns \b true if a valid ID is matched, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isRxMatch(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read Rx ID flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x4000U) ==
           0x4000U);
}

//*****************************************************************************
//
//! Enable interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! In LIN mode only, this function enables the interrupts for the specified
//! interrupt sources.
//!
//!  The \e intFlags parameter can be set to the following value to set
//!  all the flag bits:
//!  - \b LIN_INT_ALL     - All Interrupts
//!
//!  To set individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//!  - \b LIN_INT_WAKEUP  - Wakeup
//!  - \b LIN_INT_TO      - Time out
//!  - \b LIN_INT_TOAWUS  - Time out after wakeup signal
//!  - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//!  - \b LIN_INT_TX      - Transmit buffer ready
//!  - \b LIN_INT_RX      - Receive buffer ready
//!  - \b LIN_INT_ID      - Received matching identifier
//!  - \b LIN_INT_PE      - Parity error
//!  - \b LIN_INT_OE      - Overrun error
//!  - \b LIN_INT_FE      - Framing error
//!  - \b LIN_INT_NRE     - No response error
//!  - \b LIN_INT_ISFE    - Inconsistent sync field error
//!  - \b LIN_INT_CE      - Checksum error
//!  - \b LIN_INT_PBE     - Physical bus error
//!  - \b LIN_INT_BE      - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    __byte_peripheral_32((uint32_t *)(base + 0xCU)) |= intFlags;
}

//*****************************************************************************
//
//! Disable interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! In LIN mode only, this function disables the interrupts for the specified
//! interrupt sources.
//!
//!  The \e intFlags parameter can be set to the following value to disable
//!  all the flag bits:
//!  - \b LIN_INT_ALL     - All Interrupts
//!
//!  To disable individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//!  - \b LIN_INT_WAKEUP  - Wakeup
//!  - \b LIN_INT_TO      - Time out
//!  - \b LIN_INT_TOAWUS  - Time out after wakeup signal
//!  - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//!  - \b LIN_INT_TX      - Transmit buffer ready
//!  - \b LIN_INT_RX      - Receive buffer ready
//!  - \b LIN_INT_ID      - Received matching identifier
//!  - \b LIN_INT_PE      - Parity error
//!  - \b LIN_INT_OE      - Overrun error
//!  - \b LIN_INT_FE      - Framing error
//!  - \b LIN_INT_NRE     - No response error
//!  - \b LIN_INT_ISFE    - Inconsistent sync field error
//!  - \b LIN_INT_CE      - Checksum error
//!  - \b LIN_INT_PBE     - Physical bus error
//!  - \b LIN_INT_BE      - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    __byte_peripheral_32((uint32_t *)(base + 0x10U)) = intFlags;
}

//*****************************************************************************
//
//! Clear interrupt status
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be cleared.
//!
//! In LIN mode only, this function clears the specified status flags.
//!
//!  The \e intFlags parameter can be set to the following value to clear
//!  all the flag bits:
//!  - \b LIN_INT_ALL     - All Interrupts
//!
//!  To clear individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//!  - \b LIN_INT_WAKEUP  - Wakeup
//!  - \b LIN_INT_TO      - Time out
//!  - \b LIN_INT_TOAWUS  - Time out after wakeup signal
//!  - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//!  - \b LIN_INT_TX      - Transmit buffer ready
//!  - \b LIN_INT_RX      - Receive buffer ready
//!  - \b LIN_INT_ID      - Received matching identifier
//!  - \b LIN_INT_PE      - Parity error
//!  - \b LIN_INT_OE      - Overrun error
//!  - \b LIN_INT_FE      - Framing error
//!  - \b LIN_INT_NRE     - No response error
//!  - \b LIN_INT_ISFE    - Inconsistent sync field error
//!  - \b LIN_INT_CE      - Checksum error
//!  - \b LIN_INT_PBE     - Physical bus error
//!  - \b LIN_INT_BE      - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_clearInterruptStatus(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the status flags
    //
    __byte_peripheral_32((uint32_t *)(base + 0x1CU)) = intFlags;
}

//*****************************************************************************
//
//! Set interrupt level to 0
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In LIN mode only, this function sets the specified interrupt sources to
//! level 0.
//!
//!  The \e intFlags parameter can be set to the following value to set
//!  all the flag bits:
//!  - \b LIN_INT_ALL     - All Interrupts
//!
//!  To set individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//!  - \b LIN_INT_WAKEUP  - Wakeup
//!  - \b LIN_INT_TO      - Time out
//!  - \b LIN_INT_TOAWUS  - Time out after wakeup signal
//!  - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//!  - \b LIN_INT_TX      - Transmit buffer ready
//!  - \b LIN_INT_RX      - Receive buffer ready
//!  - \b LIN_INT_ID      - Received matching identifier
//!  - \b LIN_INT_PE      - Parity error
//!  - \b LIN_INT_OE      - Overrun error
//!  - \b LIN_INT_FE      - Framing error
//!  - \b LIN_INT_NRE     - No response error
//!  - \b LIN_INT_ISFE    - Inconsistent sync field error
//!  - \b LIN_INT_CE      - Checksum error
//!  - \b LIN_INT_PBE     - Physical bus error
//!  - \b LIN_INT_BE      - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setInterruptLevel0(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear interrupt levels to 0
    //
    __byte_peripheral_32((uint32_t *)(base + 0x18U)) = intFlags;
}

//*****************************************************************************
//
//! Set interrupt level to 1
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In LIN mode only, this function sets the specified interrupt sources to
//! level 1.
//!
//!  The \e intFlags parameter can be set to the following value to set
//!  all the flag bits:
//!  - \b LIN_INT_ALL     - All Interrupts
//!
//!  To set individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//!  - \b LIN_INT_WAKEUP  - Wakeup
//!  - \b LIN_INT_TO      - Time out
//!  - \b LIN_INT_TOAWUS  - Time out after wakeup signal
//!  - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//!  - \b LIN_INT_TX      - Transmit buffer ready
//!  - \b LIN_INT_RX      - Receive buffer ready
//!  - \b LIN_INT_ID      - Received matching identifier
//!  - \b LIN_INT_PE      - Parity error
//!  - \b LIN_INT_OE      - Overrun error
//!  - \b LIN_INT_FE      - Framing error
//!  - \b LIN_INT_NRE     - No response error
//!  - \b LIN_INT_ISFE    - Inconsistent sync field error
//!  - \b LIN_INT_CE      - Checksum error
//!  - \b LIN_INT_PBE     - Physical bus error
//!  - \b LIN_INT_BE      - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setInterruptLevel1(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set interrupt levels to 1
    //
    __byte_peripheral_32((uint32_t *)(base + 0x14U)) |= intFlags;
}

//*****************************************************************************
//
//! Enable Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be enabled
//!
//! In LIN mode only, this function enables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_ALL_ERRORS can be used to enable all of them:
//! - \b LIN_BIT_ERROR      - Simulates a bit error
//! - \b LIN_BUS_ERROR      - Simulates a physical bus error
//! - \b LIN_CHECKSUM_ERROR - Simulates a checksum error
//! - \b LIN_ISF_ERROR      - Simulates an inconsistent synch field error
//!
//! \note To disable these errors, use the LIN_disableModuleErrors() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableModuleErrors(uint32_t base, uint32_t errors)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    //
    // Enable write access
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) |= ((0xAU) <<
                                       8U);

    //
    // Enable specified error bits
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= errors;

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~((0xAU) <<
                                        8U);

    __edis();
}

//*****************************************************************************
//
//! Disable Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be disabled
//!
//! In LIN mode only, this function disables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_ALL_ERRORS can be used to disable all of them:
//! - \b LIN_BIT_ERROR      - Simulates a bit error
//! - \b LIN_BUS_ERROR      - Simulates a physical bus error
//! - \b LIN_CHECKSUM_ERROR - Simulates a checksum error
//! - \b LIN_ISF_ERROR      - Simulates an inconsistent synch field error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableModuleErrors(uint32_t base, uint32_t errors)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    //
    // Enable write access
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) |= ((0xAU) <<
                                       8U);

    //
    // Disable specified error bits
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(errors);

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~((0xAU) <<
                                        8U);

    __edis();
}

//*****************************************************************************
//
//! Enable Automatic Baudrate Adjustment
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the automatic baudrate adjustment
//! mode during the detection of the Synch Field.
//!
//! \note The baudrate selection register will be updated automatically by a
//! slave node if this mode is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableAutomaticBaudrate(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x200U;

    __edis();
}

//*****************************************************************************
//
//! Disable Automatic Baudrate Adjustment
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function disables the automatic baudrate adjustment
//! mode during the detection of the Synch Field. This results in a fixed
//! baud rate.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableAutomaticBaudrate(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x200U;

    __edis();
}

//*****************************************************************************
//
//! Stops LIN Extended Frame Communication
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function stops the extended frame communication.
//! Once stopped, the bit is automatically cleared.
//!
//! \note This function can only be called during extended frame communication.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_stopExtendedFrame(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set stop bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Set Checksum Type
//!
//! \param base is the LIN module base address
//! \param type is the checksum type
//!
//! In LIN mode only, this function sets the checksum type. The \e type
//! parameter can be one of the following two values:
//! - \b LIN_CHECKSUM_CLASSIC  - Checksum Classic
//! - \b LIN_CHECKSUM_ENHANCED - Checksum Enhanced
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setChecksumType(uint32_t base, LIN_ChecksumType type)
{
    //
    // Check the arguments.
    //
    ;

    if(type == LIN_CHECKSUM_ENHANCED)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x800U;
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x800U);
    }
}

//*****************************************************************************
//
//! Set Sync Break Extend and Delimiter
//!
//! \param base is the LIN module base address
//! \param syncBreak is the sync break extend value
//! \param delimiter is the sync delimiter value
//!
//! In LIN mode only, this function sets the 3-bit sync break extend value
//! and the 2-bit sync delimiter compare value.
//!
//! The \e break parameter can be a value between 0 to 7. Details:
//! - \b 0 - Sync Break has no additional T-bit
//! - \b 1 - Sync Break has 1 additional T-bit
//! - \b ...
//! - \b 7 - Sync Break has 7 additional T-bits
//!
//! The \e delimiter parameter can be a value between 1 to 4. Details:
//! - \b 1 - Delimiter has 1 T-bit
//! - \b 2 - Delimiter has 2 T-bits
//! - \b 3 - Delimiter has 3 T-bits
//! - \b 4 - Delimiter has 4 T-bits
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSyncFields(uint32_t base, uint16_t syncBreak, uint16_t delimiter)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Clear sync values and set new values
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x60U)))) &= ~((uint16_t)0x7U |
                                   (uint16_t)0x300U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x60U)))) |= (syncBreak | ((delimiter - 1U) <<
                                               8U));
}

//*****************************************************************************
//
// Prototypes for the SCI mode APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enable SCI Mode
//!
//! \param base is the LIN module base address
//!
//! This function enables the LIN peripheral to function as a SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable SCI communications mode
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x40U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x20U |
                                    0x2U;

    __edis();
}

//*****************************************************************************
//
//! Disable SCI Mode
//!
//! \param base is the LIN module base address
//!
//! This function disables the SCI mode of the LIN peripheral.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable SCI communications mode
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x20U |
                                      0x2U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x40U;

    __edis();
}

//*****************************************************************************
//
//! Set SCI communication mode
//!
//! \param base is the LIN module base address
//! \param mode is the selected communication mode
//!
//! In SCI mode only, this function is used to select between idle-line mode
//! and address-bit mode. The \e mode parameter can have one of the following
//! values:
//! - \b LIN_COMM_SCI_IDLELINE - Idle-line mode.
//! - \b LIN_COMM_SCI_ADDRBIT  - Address-bit mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCICommMode(uint32_t base, LIN_SCICommMode mode)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Write communication mode selection to the appropriate bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &
                                    ~0x1U) | (uint16_t)mode;
}

//*****************************************************************************
//
//! Enable SCI Parity mode.
//!
//! \param base is the LIN module base address
//! \param parity is the SCI parity type
//!
//! In SCI mode only, this function enables the parity check and sets the
//! parity type. The \e parity parameter can one of the following values:
//! - \b LIN_SCI_PAR_ODD  - Sets Odd parity
//! - \b LIN_SCI_PAR_EVEN - Sets Even parity
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIParity(uint32_t base, LIN_SCIParityType parity)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Enable the parity mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x4U;

    //
    // Set the parity type
    //
    if(parity == LIN_SCI_PAR_ODD)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x8U);
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x8U;
    }
}

//*****************************************************************************
//
//! Disable SCI Parity mode.
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function disables the parity check.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIParity(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Disable the parity mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x4U);
}

//*****************************************************************************
//
//! Set the number of stop bits for SCI
//!
//! \param base is the LIN module base address
//! \param number is the number of stop bits
//!
//! In SCI mode only, this function sets the number of stop bits transmitted.
//! The \e number parameter can be one of the following values:
//! - \b LIN_SCI_STOP_ONE - Set one stop bit
//! - \b LIN_SCI_STOP_TWO - Set two stop bits
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIStopBits(uint32_t base, LIN_SCIStopBits number)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set the number of stop bits
    //
    if(number == LIN_SCI_STOP_ONE)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x10U);
    }
    else
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x10U;
    }
}

//*****************************************************************************
//
//! Enable SCI Sleep mode.
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function enables the receive sleep mode
//! functionality.
//!
//! \note The receiver still operates when the sleep mode is enabled, however,
//! RXRDY is updated and SCIRD is loaded with new data only when an address
//! frame is detected.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCISleepMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set sleep mode bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x100U;
}

//*****************************************************************************
//
//! Disable SCI Sleep mode.
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function disables the receive sleep mode
//! functionality.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCISleepMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear sleep mode bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x100U);
}

//*****************************************************************************
//
//! Enter SCI Local Low-Power Mode
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function enters the SCI local low-power mode.
//!
//! \note If this function is called while the receiver is actively receiving
//! data and the wakeup interrupt is disabled, then the module will delay
//! sleep mode from being entered until completion of reception.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enterSCILowPower(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set low power bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) |= 0x1U;
}

//*****************************************************************************
//
//! Exit SCI Local Low-Power Mode
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function exits the SCI local low-power mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_exitSCILowPower(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear low power bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) &= ~0x1U;
}

//*****************************************************************************
//
//! Set SCI character length
//!
//! \param base is the LIN module base address
//! \param numBits is the number of bits per character.
//!
//! In SCI mode only, this function sets the number of bits per character.
//!
//! The \e numBits parameter must be in a range between 1 and 8.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCICharLength(uint32_t base, uint16_t numBits)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Set the number of bits per character
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x28U)))) &
                                      ~0x7U) |
                                     (uint16_t)(numBits - 1U);
}

//*****************************************************************************
//
//! Set SCI Frame Length
//!
//! \param base is the LIN module base address
//! \param length is the number of characters
//!
//! In SCI mode only, this function sets the number of characters in the
//! response field.
//!
//! The \e length parameter must be in a range between 1 and 8.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIFrameLength(uint32_t base, uint16_t length)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Set number of characters
    //
    __byte_peripheral_32((uint32_t *)(base + 0x28U)) = (__byte_peripheral_32((uint32_t *)(base + 0x28U)) &
                                        ~(0x70000U)) |
                                        (((uint32_t)length - (uint32_t)1U) <<
                                         16U);
}

//*****************************************************************************
//
//! Check if new SCI data is ready to be read
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks to see if the Rx ready bit is set
//! indicating that a new data has been received.
//!
//! \return Returns \b true if the Rx ready flag is set, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isSCIDataAvailable(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read Rx Ready flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x200U) ==
           0x200U);
}

//*****************************************************************************
//
//! Check if Space is available in SCI Transmit Buffer
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks to see if the Tx ready flag is set
//! indicating that the Tx buffer(s) is/are ready to get another character.
//!
//! \return Returns \b true if the TX ready flag is set, else returns \b false
//
//*****************************************************************************
static inline _Bool
LIN_isSCISpaceAvailable(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read Tx buffer flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x100U) ==
           0x100U);
}

//*****************************************************************************
//
//! Reads a SCI character without Blocking
//!
//! \param base is the LIN module base address
//! \param emulation sets whether the data is being read by an emulator or not
//!
//! In SCI mode only, this function gets the byte of data received. The
//! \e emulation parameter can have one of the following values:
//! - \b true - Emulator is being used, the RXRDY flag won't be cleared
//! - \b false - Emulator isn't being used, the RXRDY flag will be cleared
//!              automatically on read
//!
//! \note
//! -# If the SCI receives data that is fewer than 8 bits in length, the
//! data is left-justified and padded with trailing zeros.
//! -# To determine if new data is available to read, use the function
//! LIN_isSCIDataAvailable().
//!
//! \return Returns the received data.
//
//*****************************************************************************
static inline uint16_t
LIN_readSCICharNonBlocking(uint32_t base, _Bool emulation)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read specific data register
    //
    return(emulation ? ((*((volatile uint16_t *)((uintptr_t)(base + 0x30U)))) & 0xFFU) :
            ((*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) & 0xFFU));
}

//*****************************************************************************
//
//! Reads a SCI character with Blocking
//!
//! \param base is the LIN module base address
//! \param emulation sets whether the data is being read by an emulator or not
//!
//! In SCI mode only, this function gets the byte of data received. If new data
//! isn't available, this function will wait until new data arrives. The
//! \e emulation parameter can have one of the following values:
//! - \b true - Emulator is being used, the RXRDY flag won't be cleared
//! - \b false - Emulator isn't being used, the RXRDY flag will be cleared
//!              automatically on read
//!
//! \note If the SCI receives data that is fewer than 8 bits in length, the
//! data is left-justified and padded with trailing zeros.
//!
//! \return Returns the received data.
//
//*****************************************************************************
static inline uint16_t
LIN_readSCICharBlocking(uint32_t base, _Bool emulation)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Wait until a character is available in buffer.
    //
    while(!LIN_isSCIDataAvailable(base))
    {
    }

    //
    // Read specific data register
    //
    return(emulation ? ((*((volatile uint16_t *)((uintptr_t)(base + 0x30U)))) & 0xFFU) :
            ((*((volatile uint16_t *)((uintptr_t)(base + 0x34U)))) & 0xFFU));
}

//*****************************************************************************
//
//! Sends a SCI character without blocking
//!
//! \param base is the LIN module base address
//! \param data is the byte of data to be transmitted
//!
//! In SCI mode only, this function sets the byte of data to be transmitted
//! without blocking.
//!
//! \note The transmit ready flag gets set when this buffer is ready to be
//! loaded with another byte of data. Use LIN_isSCISpaceAvailable() to
//! determine if space is available to write another character.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_writeSCICharNonBlocking(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Set the Tx Data
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x38U)))) = (data & 0xFFU);
}

//*****************************************************************************
//
//! Sends a SCI character with blocking
//!
//! \param base is the LIN module base address
//! \param data is the byte of data to be transmitted
//!
//! In SCI mode only, this function sets the byte of data to be transmitted
//! with blocking functionality. If the buffer isn't ready to get new data
//! written to, this function will wait until space is available.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_writeSCICharBlocking(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Wait until space is available in the transmit buffer.
    //
    while(!LIN_isSCISpaceAvailable(base))
    {
    }

    //
    // Set the Tx Data
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x38U)))) = (data & 0xFFU);
}

//*****************************************************************************
//
//! Enable SCI Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be enabled
//!
//! In SCI mode only, this function enables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_SCI_ALL_ERRORS can be used to enable all of
//! them:
//! - \b LIN_SCI_FRAME_ERROR   - Simulates a frame error
//! - \b LIN_SCI_PARITY_ERROR  - Simulates a parity error
//! - \b LIN_SCI_BREAK_ERROR   - Simulates a break detect error
//!
//! \note To disable these errors, use the LIN_disableSCIModuleErrors()
//! function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIModuleErrors(uint32_t base, uint32_t errors)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    //
    // Enable write access
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) |= ((0xAU) <<
                                       8U);

    //
    // Enable specified error bits
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= errors;

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~((0xAU) <<
                                        8U);

    __edis();
}

//*****************************************************************************
//
//! Disable SCI Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be disabled
//!
//! In SCI mode only, this function disables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_SCI_ALL_ERRORS can be used to enable all of
//! them:
//! - \b LIN_SCI_FRAME_ERROR   - Simulates a frame error
//! - \b LIN_SCI_PARITY_ERROR  - Simulates a parity error
//! - \b LIN_SCI_BREAK_ERROR   - Simulates a break detect error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIModuleErrors(uint32_t base, uint32_t errors)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    //
    // Enable write access
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) |= ((0xAU) <<
                                       8U);

    //
    // Disable specified error bits
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(errors);

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~((0xAU) <<
                                        8U);

    __edis();
}

//*****************************************************************************
//
//! Enable SCI interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! In SCI mode only, this function enables the interrupts for the specified
//! interrupt sources.
//!
//!  The \e intFlags parameter can be set to the following value to set
//!  all the flag bits:
//!  - \b LIN_SCI_INT_ALL     - All Interrupts
//!
//!  To set individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//! - \b LIN_SCI_INT_BREAK    - Break Detect
//! - \b LIN_SCI_INT_WAKEUP   - Wakeup
//! - \b LIN_SCI_INT_TX       - Transmit Buffer
//! - \b LIN_SCI_INT_RX       - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA   - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA   - DMA Receive
//! - \b LIN_SCI_INT_PARITY   - Parity Error
//! - \b LIN_SCI_INT_OVERRUN  - Overrun Error
//! - \b LIN_SCI_INT_FRAME    - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set specified interrupts
    //
    __byte_peripheral_32((uint32_t *)(base + 0xCU)) |= intFlags;
}

//*****************************************************************************
//
//! Disable SCI interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! In SCI mode only, this function disables the interrupts for the specified
//! interrupt sources.
//!
//!  The \e intFlags parameter can be set to the following value to disable
//!  all the flag bits:
//!  - \b LIN_SCI_INT_ALL     - All Interrupts
//!
//!  To disable individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//! - \b LIN_SCI_INT_BREAK    - Break Detect
//! - \b LIN_SCI_INT_WAKEUP   - Wakeup
//! - \b LIN_SCI_INT_TX       - Transmit Buffer
//! - \b LIN_SCI_INT_RX       - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA   - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA   - DMA Receive
//! - \b LIN_SCI_INT_PARITY   - Parity Error
//! - \b LIN_SCI_INT_OVERRUN  - Overrun Error
//! - \b LIN_SCI_INT_FRAME    - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIInterrupt(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set specified interrupts to be cleared
    //
    __byte_peripheral_32((uint32_t *)(base + 0x10U)) |= intFlags;
}

//*****************************************************************************
//
//! Clear SCI interrupt status
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be cleared.
//!
//! In SCI mode only, this function clears the specified status flags.
//!
//!  The \e intFlags parameter can be set to the following value to clear
//!  all the flag bits:
//!  - \b LIN_SCI_INT_ALL     - All Interrupts
//!
//!  To clear individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//! - \b LIN_SCI_INT_BREAK    - Break Detect
//! - \b LIN_SCI_INT_WAKEUP   - Wakeup
//! - \b LIN_SCI_INT_TX       - Transmit Buffer
//! - \b LIN_SCI_INT_RX       - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA   - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA   - DMA Receive
//! - \b LIN_SCI_INT_PARITY   - Parity Error
//! - \b LIN_SCI_INT_OVERRUN  - Overrun Error
//! - \b LIN_SCI_INT_FRAME    - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_clearSCIInterruptStatus(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear the status flags
    //
    __byte_peripheral_32((uint32_t *)(base + 0x1CU)) |= intFlags;
}

//*****************************************************************************
//
//! Set SCI interrupt level to 0
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In SCI mode only, this function sets the specified interrupt sources to
//! level 0.
//!
//!  The \e intFlags parameter can be set to the following value to set
//!  all the flag bits:
//!  - \b LIN_SCI_INT_ALL     - All Interrupts
//!
//!  To set individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//! - \b LIN_SCI_INT_BREAK    - Break Detect
//! - \b LIN_SCI_INT_WAKEUP   - Wakeup
//! - \b LIN_SCI_INT_TX       - Transmit Buffer
//! - \b LIN_SCI_INT_RX       - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA   - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA   - DMA Receive
//! - \b LIN_SCI_INT_PARITY   - Parity Error
//! - \b LIN_SCI_INT_OVERRUN  - Overrun Error
//! - \b LIN_SCI_INT_FRAME    - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIInterruptLevel0(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Clear interrupt levels to 0
    //
    __byte_peripheral_32((uint32_t *)(base + 0x18U)) |= intFlags;
}

//*****************************************************************************
//
//! Set SCI interrupt level to 1
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In SCI mode only, this function sets the specified interrupt sources to
//! level 1.
//!
//!  The \e intFlags parameter can be set to the following value to set
//!  all the flag bits:
//!  - \b LIN_SCI_INT_ALL     - All Interrupts
//!
//!  To set individual flags, the \e intFlags parameter can be the logical
//!  OR of any of the following:
//! - \b LIN_SCI_INT_BREAK    - Break Detect
//! - \b LIN_SCI_INT_WAKEUP   - Wakeup
//! - \b LIN_SCI_INT_TX       - Transmit Buffer
//! - \b LIN_SCI_INT_RX       - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA   - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA   - DMA Receive
//! - \b LIN_SCI_INT_PARITY   - Parity Error
//! - \b LIN_SCI_INT_OVERRUN  - Overrun Error
//! - \b LIN_SCI_INT_FRAME    - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIInterruptLevel1(uint32_t base, uint32_t intFlags)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Set interrupt levels to 1
    //
    __byte_peripheral_32((uint32_t *)(base + 0x14U)) |= intFlags;
}

//*****************************************************************************
//
//! Check if SCI Receiver is Idle
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks if the receiver is in an idle state.
//!
//! \return Returns \b true if the state is idle, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isSCIReceiverIdle(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read Rx Idle flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x4U) == 0U);
}

//*****************************************************************************
//
//! Gets the SCI Transmit Frame Type
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function gets the transmit frame type which can be
//! either data or an address.
//!
//! \return Returns \b true if the frame will be an address, and returns
//! \b false if the frame will be data.
//
//*****************************************************************************
static inline _Bool
LIN_getSCITxFrameType(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read Tx Wake flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x400U) ==
           0x400U);
}

//*****************************************************************************
//
//! Gets the SCI Receiver Frame Type
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function gets the receiver frame type which can be
//! either an address or not an address.
//!
//! \return Returns \b true if the frame is an address, and returns
//! \b false if the frame isn't an address.
//
//*****************************************************************************
static inline _Bool
LIN_getSCIRxFrameType(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read Rx Wake flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x1000U) ==
           0x1000U);
}

//*****************************************************************************
//
//! Check if SCI Detected a Break Condition
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks if the module detected a break
//! condition on the Rx pin.
//!
//! \return Returns \b true if break detected, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isSCIBreakDetected(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Read Break condition flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x1U) ==
           0x1U);
}

//*****************************************************************************
//
// Prototypes for the LIN and SCI mode APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the LIN module.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function sets the RESET bit of the SCIGCR0
//! register. Registers in this module are not writable until this has been
//! done. Additionally, the transmit and receive pin control functionality is
//! enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Set reset bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x1U;

    //
    // Enable TX and RX pin control functionality
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x3CU)))) |= (0x2U | 0x4U);

    __edis();
}

//*****************************************************************************
//
//! Disable the LIN module.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function clears the RESET bit of the SCIGCR0
//! register. Registers in this module are not writable when this bit is
//! cleared. Additionally, the transmit and receive pin control functionality
//! is disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Disable TX and RX pin control functionality
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x3CU)))) &= ~(0x2U | 0x4U);

    //
    // Clear reset bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x1U;

    __edis();
}

//*****************************************************************************
//
//! Set Baud Rate Prescaler
//!
//! \param base is the LIN module base address
//! \param prescaler is the 24-bit integer prescaler
//! \param divider is the 4-bit fractional divider
//!
//! In LIN and SCI mode, this function is used to set the baudrate based on
//! the \e prescaler and \e divider values.
//!
//! P = Prescaler  \n
//! M = Fractional Divider \n
//! Bitrate = (SYSCLOCK) / ((P + 1 + M/16) * 16) \n
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setBaudRatePrescaler(uint32_t base, uint32_t prescaler,
                         uint32_t divider)
{
    //
    // Check the arguments.
    //
    ;
    ;
    ;

    //
    // Set baud rate prescaler and divider
    //
    __byte_peripheral_32((uint32_t *)(base + 0x2CU)) = (prescaler | (divider << 24U));
}

//*****************************************************************************
//
//! Enable Transmit Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the transfer of data from
//! SCITD or TDy to the transmit shift register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableDataTransmitter(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable transmit bit
    //
    __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x2000000U;
}

//*****************************************************************************
//
//! Disable Transmit Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the transfer of data from
//! SCITD or TDy to the transmit shift register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableDataTransmitter(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable transmit bit
    //
    __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x2000000U);
}

//*****************************************************************************
//
//! Enable Receive Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the receiver to transfer data
//! from the shift buffer register to the receive buffer or multi-buffer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableDataReceiver(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable receive bit
    //
    __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x1000000U;
}

//*****************************************************************************
//
//! Disable Receive Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the receiver to transfer data
//! from the shift buffer register to the receive buffer or multi-buffer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableDataReceiver(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable receive bit
    //
    __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x1000000U);
}

//*****************************************************************************
//
//! Perform software reset.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function will reset the LIN state machine and
//! clear all pending flags. It is required to call this function after a
//! wakeup signal has been sent.
//!
//! To enter the reset state separately, use LIN_enterSoftwareReset(). To come
//! out of reset, use LIN_exitSoftwareReset().
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_performSoftwareReset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x80U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x80U;
}

//*****************************************************************************
//
//! Put LIN into its reset state.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function will reset the LIN state machine and
//! clear all pending flags. It is required to call this function after a
//! wakeup signal has been sent. When in this state, changes to the
//! configuration of this module may be made.
//!
//! To take LIN out of the reset state and back into the ready state, use
//! LIN_exitSoftwareReset().
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enterSoftwareReset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~(0x80U);
}

//*****************************************************************************
//
//! Put LIN into its ready state.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function will put LIN into its ready state.
//! Transmission and reception can be done in this state. While in the ready
//! state, configuration of the module should not be changed.
//!
//! To put the module into its reset state, use LIN_enterSoftwareReset().
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_exitSoftwareReset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x80U;
}

//*****************************************************************************
//
//! Check if Bus is Busy
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function checks if the receiver bus is busy
//! receiving a frame.
//!
//! \return Returns \b true if the bus is busy, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isBusBusy(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read Bus busy flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x8U) ==
           0x8U);
}

//*****************************************************************************
//
//! Check if the Transmit Buffer is Empty
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function checks if the transmit buffer is empty
//! or not.
//!
//! \return Returns \b true if the Tx buffer is empty, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isTxBufferEmpty(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read Tx Empty Flag and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1CU)))) & 0x800U) ==
           0x800U);
}

//*****************************************************************************
//
//! Enable External Loopback mode for self test
//!
//! \param base is the LIN module base address
//! \param loopbackType is the loopback type (analog or digital)
//! \param path sets the transmit or receive pin to be included in the
//! communication path (Analog loopback mode only)
//!
//! In LIN and SCI mode, this function enables the external Loopback mode for
//! self test. The \e loopbackType parameter can be one of the following
//! values:
//! - \b LIN_LOOPBACK_DIGITAL - Digital Loopback
//! - \b LIN_LOOPBACK_ANALOG  - Analog Loopback
//!
//! The \e path parameter is only applicable in analog loopback mode and can
//! be one of the following values:
//! - \b LIN_ANALOG_LOOP_NONE - Default option for digital loopback mode
//! - \b LIN_ANALOG_LOOP_TX   - Enables analog loopback through the Tx pin
//! - \b LIN_ANALOG_LOOP_RX   - Enables analog loopback through the Rx pin
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableExtLoopback(uint32_t base, LIN_LoopbackType loopbackType,
                      LIN_AnalogLoopback path)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    //
    // Enable Loopback either in Analog or Digital Mode
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) |= (((0xAU) <<
                                        8U) |
                                       (uint16_t)loopbackType |
                                       (uint16_t)path);

    __edis();
}

//*****************************************************************************
//
//! Disable External Loopback mode for self test
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the external Loopback mode.
//!
//! \note This function also resets the analog loopback communication path to
//! the default transmit pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableExtLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    //Disable Loopback Mode
    //
    __eallow();

    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U |
                                        0x2U |
                                        0x1U);

    __edis();
}

//*****************************************************************************
//
//! Enable Internal Loopback mode for self test
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the internal Loopback mode for
//! self test.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableIntLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the internal loopback
    //
    __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x10000U;
}

//*****************************************************************************
//
//! Disable Internal Loopback mode for self test
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the internal Loopback mode for
//! self test.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableIntLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the internal loopback
    //
    __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x10000U);
}

//*****************************************************************************
//
//! Get Interrupt Flags Status
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function returns the interrupt status register.
//!
//! The following flags can be used to mask the value returned:
//! - \b LIN_FLAG_BREAK   - Break Detect Flag (SCI mode only)
//! - \b LIN_FLAG_WAKEUP  - Wake-up Flag
//! - \b LIN_FLAG_IDLE    - Receiver in Idle State (SCI mode only)
//! - \b LIN_FLAG_BUSY    - Busy Flag
//! - \b LIN_FLAG_TO      - Bus Idle Timeout Flag (LIN mode only)
//! - \b LIN_FLAG_TOAWUS  - Timeout after Wakeup Signal (LIN mode only)
//! - \b LIN_FLAG_TOA3WUS - Timeout after 3 Wakeup Signals (LIN mode only)
//! - \b LIN_FLAG_TXRDY   - Transmitter Buffer Ready Flag
//! - \b LIN_FLAG_RXRDY   - Receiver Buffer Ready Flag
//! - \b LIN_FLAG_TXWAKE  - Transmitter Wakeup Method Select (SCI mode only)
//! - \b LIN_FLAG_TXEMPTY - Transmitter Empty Flag
//! - \b LIN_FLAG_RXWAKE  - Receiver Wakeup Detect Flag
//! - \b LIN_FLAG_TXID    - Identifier on Transmit Flag (LIN mode only)
//! - \b LIN_FLAG_RXID    - Identifier on Receive Flag (LIN mode only)
//! - \b LIN_FLAG_PE      - Parity Error Flag
//! - \b LIN_FLAG_OE      - Overrun Error Flag
//! - \b LIN_FLAG_FE      - Framing Error Flag
//! - \b LIN_FLAG_NRE     - No-Response Error Flag (LIN mode only)
//! - \b LIN_FLAG_ISFE    - Inconsistent Synch Field Error Flag (LIN mode only)
//! - \b LIN_FLAG_CE      - Checksum Error Flag (LIN mode only)
//! - \b LIN_FLAG_PBE     - Physical Bus Error Flag (LIN mode only)
//! - \b LIN_FLAG_BE      - Bit Error Flag (LIN mode only)
//!
//! \return Returns the status flag register.
//
//*****************************************************************************
static inline uint32_t
LIN_getInterruptStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read and return the flag register
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0x1CU)));
}

//*****************************************************************************
//
//! Get the Interrupt Level
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function gets the interrupt level status for
//! all interrupt sources.
//!
//! \return Returns the value of the interrupt level register.
//
//*****************************************************************************
static inline uint32_t
LIN_getInterruptLevel(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Gets the interrupt levels for all sources
    //
    return(__byte_peripheral_32((uint32_t *)(base + 0x14U)));
}

//*****************************************************************************
//
//! Gets the Interrupt Vector Offset for Line 0
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function gets the offset for interrupt line 0.
//! A read to the specified line register updates its value to the next highest
//! priority pending interrupt in the flag register and clears the flag
//! corresponding to the offset that was read.
//!
//! \note The flags for the receive and the transmit interrupts cannot be
//! cleared by reading the corresponding offset vector in this function.
//!
//! The following are values that can be returned:
//! - \b LIN_VECT_NONE    - No Interrupt
//! - \b LIN_VECT_WAKEUP  - Wakeup
//! - \b LIN_VECT_ISFE    - Inconsistent-sync-field Error
//! - \b LIN_VECT_PE      - Parity Error
//! - \b LIN_VECT_ID      - ID Interrupt
//! - \b LIN_VECT_PBE     - Physical Bus Error
//! - \b LIN_VECT_FE      - Frame Error
//! - \b LIN_VECT_BREAK   - Break detect
//! - \b LIN_VECT_CE      - Checksum Error
//! - \b LIN_VECT_OE      - Overrun Error
//! - \b LIN_VECT_BE      - Bit Error
//! - \b LIN_VECT_RX      - Receive Interrupt
//! - \b LIN_VECT_TX      - Transmit Interrupt
//! - \b LIN_VECT_NRE     - No-response Error
//! - \b LIN_VECT_TOAWUS  - Timeout after wakeup signal
//! - \b LIN_VECT_TOA3WUS - Timeout after 3 wakeup signals
//! - \b LIN_VECT_TO      - Timeout (Bus Idle)
//!
//! \return Returns the interrupt vector offset for interrupt line 0.
//
//*****************************************************************************
static inline uint16_t
LIN_getInterruptLine0Offset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get interrupt vector line offset
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x20U)))) & 0x1FU);
}

//*****************************************************************************
//
//! Gets the Interrupt Vector Offset for Line 1
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function gets the offset for interrupt line 1.
//! A read to the specified line register updates its value to the next highest
//! priority pending interrupt in the flag register and clears the flag
//! corresponding to the offset that was read.
//!
//! \note The flags for the receive and the transmit interrupts cannot be
//! cleared by reading the corresponding offset vector in this function.
//!
//! The following are values that can be returned:
//! - \b LIN_VECT_NONE    - No Interrupt
//! - \b LIN_VECT_WAKEUP  - Wakeup
//! - \b LIN_VECT_ISFE    - Inconsistent-sync-field Error
//! - \b LIN_VECT_PE      - Parity Error
//! - \b LIN_VECT_ID      - ID Interrupt
//! - \b LIN_VECT_PBE     - Physical Bus Error
//! - \b LIN_VECT_FE      - Frame Error
//! - \b LIN_VECT_BREAK   - Break detect
//! - \b LIN_VECT_CE      - Checksum Error
//! - \b LIN_VECT_OE      - Overrun Error
//! - \b LIN_VECT_BE      - Bit Error
//! - \b LIN_VECT_RX      - Receive Interrupt
//! - \b LIN_VECT_TX      - Transmit Interrupt
//! - \b LIN_VECT_NRE     - No-response Error
//! - \b LIN_VECT_TOAWUS  - Timeout after wakeup signal
//! - \b LIN_VECT_TOA3WUS - Timeout after 3 wakeup signals
//! - \b LIN_VECT_TO      - Timeout (Bus Idle)
//!
//! \return Returns the interrupt vector offset for interrupt line 1.
//
//*****************************************************************************
static inline uint16_t
LIN_getInterruptLine1Offset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get interrupt vector line offset
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x24U)))) & 0x1FU);
}

//*****************************************************************************
//
//! Enable Multi-buffer Mode
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the multi-buffer mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableMultibufferMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x400U;
}

//*****************************************************************************
//
//! Disable Multi-buffer Mode
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the multi-buffer mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableMultibufferMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x400U;
}

//*****************************************************************************
//
//! Set Transmit Pin Delay
//!
//! \param base is the LIN module base address
//! \param delay is number of clock delays for the Tx pin (0 to 7)
//!
//! In LIN and SCI mode, this function sets the delay by which the value on
//! the transmit pin is delayed so that the value on the receive pin is
//! asynchronous.
//!
//! \note This is not applicable to the Start bit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setTransmitDelay(uint32_t base, uint16_t delay)
{
    //
    // Check the arguments.
    //
    ;
    ;

    __eallow();

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    //
    // Enable write access
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) |= ((0xAU) <<
                                       8U);

    //
    // Clear delay value
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(0x70000U);

    //
    // Set the delay value
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= ((uint32_t)delay <<
                                        16U);

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    __edis();
}

//*****************************************************************************
//
//! Set Pin Sample Mask
//!
//! \param base is the LIN module base address
//! \param mask is the pin sample mask to be set
//!
//! In LIN and SCI mode, this function sets sample number at which the transmit
//! pin value that is being transmitted will be inverted to verify the
//! receive pin samples correctly with the majority detection circuitry.
//! The \e mask parameter can be one of the following values:
//! - \b LIN_PINMASK_NONE         - No mask
//! - \b LIN_PINMASK_CENTER       - Invert Tx Pin value at T-bit center
//! - \b LIN_PINMASK_CENTER_SCLK  - Invert Tx Pin value at T-bit center + SCLK
//! - \b LIN_PINMASK_CENTER_2SCLK - Invert Tx Pin value at T-bit center +
//!                                 2 SCLK
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setPinSampleMask(uint32_t base, LIN_PinSampleMask mask)
{
    //
    // Check the arguments.
    //
    ;

    __eallow();

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    //
    // Enable write access
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) |= ((0xAU) <<
                                       8U);

    //
    // Clear pin mask
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(0x180000U);

    //
    // Set new pin mask value
    //
    __byte_peripheral_32((uint32_t *)(base + 0x90U)) |= ((uint32_t)mask <<
                                         19U);

    //
    // Clear the IO DFT Enable Key
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x90U)))) &= ~(0xF00U);

    __edis();
}

//*****************************************************************************
//
//! Set the Debug Suspended Mode
//!
//! \param base is the LIN module base address
//! \param mode is the debug mode
//!
//! In LIN and SCI mode, this function sets how the module operates when the
//! program is suspended and being debugged with an emulator. The \e mode
//! parameter can be one of the following values:
//! - \b LIN_DEBUG_FROZEN - The module state machine is frozen; transmissions
//! and LIN counters are halted until debug mode is exited.
//! - \b LIN_DEBUG_COMPLETE - The module continues to operate until the
//! current transmit and receive functions are complete.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setDebugSuspendMode(uint32_t base, LIN_DebugMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the debug suspend mode type
    //
    if(mode == LIN_DEBUG_FROZEN)
    {
        __byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x20000U);
    }
    else
    {
        __byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x20000U;
    }
}

//*****************************************************************************
//
//! Enables a LIN global interrupt.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function globally enables an interrupt
//! corresponding to a specified interrupt line. The \e line parameter can be
//! one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0      - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1      - Interrupt Vector Line 1
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableGlobalInterrupt(uint32_t base, LIN_InterruptLine line)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0xE0U)))) |= 0x1U <<
                                      (uint16_t)line;
}

//*****************************************************************************
//
//! Disables a LIN global interrupt.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function globally disables an interrupt
//! corresponding to a specified interrupt line. The \e line parameter can be
//! one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0      - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1      - Interrupt Vector Line 1
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableGlobalInterrupt(uint32_t base, LIN_InterruptLine line)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0xE0U)))) &= ~(0x1U <<
                                         (uint16_t)line);
}

//*****************************************************************************
//
//! Clears a LIN global interrupt flag.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function clears the global interrupt flag that
//! corresponds to a specified interrupt line. The \e line parameter can be
//! one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0      - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1      - Interrupt Vector Line 1
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_clearGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0xE8U)))) = 0x1U <<
                                        (uint16_t)line;
}

//*****************************************************************************
//
//! Returns a LIN global interrupt flag status.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function returns the status of a global interrupt
//! flag that corresponds to a specified interrupt line. The \e line parameter
//! can be one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0      - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1      - Interrupt Vector Line 1
//!
//! \return Returns \b true if the interrupt flag is set. Return \b false if
//!  not.
//
//*****************************************************************************
static inline _Bool
LIN_getGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read the flag register and return true if the specified flag is set.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xE4U)))) &
            (0x1U << (uint16_t)line)) ==
           (0x1U << (uint16_t)line));
}

//*****************************************************************************
//
//! Get the Status of LIN TX/RX Pin status.
//!
//! \param base is the LIN module base address
//! \param pin is the type of pin that is being read.
//!
//! In LIN and SCI mode, this function indicates the current status of LINTX
//! and LINRX pins. the \e pin parameter can be either LIN_PINTYPE_TX or
//! LIN_PINTYPE_RX.
//!
//! \return Returns \b true if the pin is high else \b false if low.
//
//*****************************************************************************
static inline _Bool
LIN_getPinStatus(uint32_t base, LIN_PinType pin)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Read RX/Tx pin value and return status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x44U)))) & pin) == pin);
}

//*****************************************************************************
//
//! Initializes the LIN Driver
//!
//! \param base is the LIN module base address
//!
//! This function initializes the LIN module.
//!
//! \return None.
//
//*****************************************************************************
extern void
LIN_initModule(uint32_t base);

//*****************************************************************************
//
//! Send Data
//!
//! \param base is the LIN module base address
//! \param data is the pointer to data to send
//!
//! In LIN mode only, this function sends a block of data pointed to by 'data'.
//! The number of data to transmit must be set with LIN_setFrameLength()
//! before.
//!
//! \return None.
//
//*****************************************************************************
extern void
LIN_sendData(uint32_t base, uint16_t *data);

//*****************************************************************************
//
//! Read received data
//!
//! \param base is the LIN module base address
//! \param data is the pointer to the data buffer
//!
//! In LIN mode only, this function reads a block of bytes and place it into
//! the data buffer pointed to by 'data'.
//!
//! \return None.
//
//*****************************************************************************
extern void
LIN_getData(uint32_t base, uint16_t * const data);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************


//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

/*
 *   Copyright (c) Texas Instruments Incorporated 2016
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 *  \file     mcan.h
 *
 *  \brief    This file contains the prototypes of the APIs present in the
 *            device abstraction layer file of MCAN.
 *            This also contains some related macros.
 */


/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

/*
* hw_mcanss.h
*
* Register-level header file for MCANSS2P0
*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/



/****************************************************************************************************
* Register Definitions
****************************************************************************************************/
// Sub-module base addresses






/****************************************************************************************************
* Field Definition Macros
****************************************************************************************************/


































































































































































































































































































































































































































































































































































































/* User defined ranges */











//! \addtogroup mcan_api MCAN
//! @{

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/**
 * \brief  Macro defines mask for all the interrupts status for MCAN.
 */

/**
 * \brief  Maximum payload supported by CAn-FD protocol in bytes.
 */

/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */

/**
 *  \brief    Enum to select the MCAN interrupt lines
 */
typedef enum
{
    MCAN_INTR_LINE_NUM_0 = 0U,
    /**< MCAN interrupt line 0 */
    MCAN_INTR_LINE_NUM_1 = 1U
                           /**< MCAN interrupt line 1 */
}MCAN_IntrLineNum;

/**
 *  \brief    Enum to represent the MCAN Identifier Type
 */
typedef enum
{
    MCAN_ID_TYPE_11_BIT = 0U,
    /**< 11bit MCAN Identifier */
    MCAN_ID_TYPE_29_BIT = 1U
                          /**< 29bit MCAN Identifier */
}MCAN_IdType;

/**
 *  \brief    Enum to represent the MCAN mode of operation
 */
typedef enum
{
    MCAN_OPERATION_MODE_NORMAL = 0U,
    /**< MCAN normal mode */
    MCAN_OPERATION_MODE_SW_INIT = 1U
                                  /**< MCAN SW initialization mode */
}MCAN_OperationMode;

/**
 *  \brief    Enum to represent the MCAN Message RAM type.
 */
typedef enum
{
    MCAN_MEM_TYPE_BUF = 0U,
    /**< MCAN Msg RAM buffers */
    MCAN_MEM_TYPE_FIFO = 1U
                         /**< MCAN Msg RAM FIFO/Queue */
}MCAN_MemType;

/**
 *  \brief    Enum to represent the MCAN Rx FIFO number
 */
typedef enum
{
    MCAN_RX_FIFO_NUM_0 = 0U,
    /**< MCAN Rx FIFO 0 */
    MCAN_RX_FIFO_NUM_1 = 1U
                         /**< MCAN Rx FIFO 1 */
}MCAN_RxFIFONum;

/**
 *  \brief    Enum to represent the MCAN pin type
 */
typedef enum
{
    MCAN_PIN_TYPE_RX = 0U,
    /**< MCAN Rx Pin */
    MCAN_PIN_TYPE_TX = 1U
                       /**< MCAN Tx Pin */
}MCAN_PinType;

/**
 *  \brief    Enum to represent FIFO/Buffer element Size
 */
typedef enum
{
    MCAN_ELEM_SIZE_8BYTES = 0U,
    /**< 8 byte data field */
    MCAN_ELEM_SIZE_12BYTES = 1U,
    /**< 12 byte data field */
    MCAN_ELEM_SIZE_16BYTES = 2U,
    /**< 16 byte data field */
    MCAN_ELEM_SIZE_20BYTES = 3U,
    /**< 20 byte data field */
    MCAN_ELEM_SIZE_24BYTES = 4U,
    /**< 24 byte data field */
    MCAN_ELEM_SIZE_32BYTES = 5U,
    /**< 32 byte data field */
    MCAN_ELEM_SIZE_48BYTES = 6U,
    /**< 48 byte data field */
    MCAN_ELEM_SIZE_64BYTES = 7U
                             /**< 64 byte data field */
}MCAN_ElemSize;

/**
 *  \brief    Enum to represent the MCAN time-out counter configuration
 */
typedef enum
{
    MCAN_TIMEOUT_SELECT_CONT = 0U,
    /**< Continuous operation Mode */
    MCAN_TIMEOUT_SELECT_TX_EVENT_FIFO = 1U,
    /**< Timeout controlled by Tx Event FIFO */
    MCAN_TIMEOUT_SELECT_RX_FIFO0 = 2U,
    /**< Timeout controlled by Rx FIFO 0 */
    MCAN_TIMEOUT_SELECT_RX_FIFO1 = 3U
                                   /**< Timeout controlled by Rx FIFO 1 */
}MCAN_TimeOutSelect;

/**
 * \brief  Enum for MCAN interrupts.
 */
typedef enum
{
    MCAN_INTR_SRC_RX_FIFO0_NEW_MSG = (0x00000001U),
    /**< Rx FIFO 0 New Message interrupt */
    MCAN_INTR_SRC_RX_FIFO0_WATERMARK = (0x00000002U),
    /**< Rx FIFO 0 Watermark Reached interrupt */
    MCAN_INTR_SRC_RX_FIFO0_FULL = (0x00000004U),
    /**< Rx FIFO 0 Full interrupt */
    MCAN_INTR_SRC_RX_FIFO0_MSG_LOST = (0x00000008U),
    /**< Rx FIFO 0 Message Lost interrupt */
    MCAN_INTR_SRC_RX_FIFO1_NEW_MSG = (0x00000010U),
    /**< Rx FIFO 1 New Message interrupt */
    MCAN_INTR_SRC_RX_FIFO1_WATERMARK = (0x00000020U),
    /**< Rx FIFO 1 Watermark Reached interrupt */
    MCAN_INTR_SRC_RX_FIFO1_FULL = (0x00000040U),
    /**< Rx FIFO 1 Full interrupt */
    MCAN_INTR_SRC_RX_FIFO1_MSG_LOST = (0x00000080U),
    /**< Rx FIFO 1 Message Lost interrupt */
    MCAN_INTR_SRC_HIGH_PRIO_MSG = (0x00000100U),
    /**< High Priority Message interrupt */
    MCAN_INTR_SRC_TRANS_COMPLETE = (0x00000200U),
    /**< Transmission Completed interrupt */
    MCAN_INTR_SRC_TRANS_CANCEL_FINISH = (0x00000400U),
    /**< Transmission Cancellation Finished interrupt */
    MCAN_INTR_SRC_TX_FIFO_EMPTY = (0x00000800U),
    /**< Tx FIFO Empty interrupt */
    MCAN_INTR_SRC_TX_EVT_FIFO_NEW_ENTRY = (0x00001000U),
    /**< Tx Event FIFO New Entry interrupt */
    MCAN_INTR_SRC_TX_EVT_FIFO_WATERMARK = (0x00002000U),
    /**< Tx Event FIFO Watermark Reached interrupt */
    MCAN_INTR_SRC_TX_EVT_FIFO_FULL = (0x00004000U),
    /**< Tx Event FIFO Full interrupt */
    MCAN_INTR_SRC_TX_EVT_FIFO_ELEM_LOST = (0x00008000U),
    /**< Tx Event FIFO Element Lost interrupt */
    MCAN_INTR_SRC_TIMESTAMP_WRAPAROUND = (0x00010000U),
    /**< Timestamp Wraparound interrupt */
    MCAN_INTR_SRC_MSG_RAM_ACCESS_FAILURE = (0x00020000U),
    /**< Message RAM Access Failure interrupt */
    MCAN_INTR_SRC_TIMEOUT = (0x00040000U),
    /**< Timeout Occurred interrupt */
    MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG = (0x00080000U),
    /**< Message stored to Dedicated Rx Buffer interrupt */
    MCAN_INTR_SRC_BIT_ERR_CORRECTED = (0x00100000U),
    /**< Bit Error Corrected interrupt */
    MCAN_INTR_SRC_BIT_ERR_UNCORRECTED = (0x00200000U),
    /**< Bit Error Uncorrected interrupt */
    MCAN_INTR_SRC_ERR_LOG_OVRFLW = (0x00400000U),
    /**< Error Logging Overflow interrupt */
    MCAN_INTR_SRC_ERR_PASSIVE = (0x00800000U),
    /**< Error Passive interrupt */
    MCAN_INTR_SRC_WARNING_STATUS = (0x01000000U),
    /**< Warning Status interrupt */
    MCAN_INTR_SRC_BUS_OFF_STATUS = (0x02000000U),
    /**< Bus_Off Status interrupt */
    MCAN_INTR_SRC_WATCHDOG = (0x04000000U),
    /**< Watchdog Interrupt interrupt */
    MCAN_INTR_SRC_PROTOCOL_ERR_ARB = (0x08000000U),
    /**< Protocol Error in Arbitration Phase interrupt */
    MCAN_INTR_SRC_PROTOCOL_ERR_DATA = (0x10000000U),
    /**< Protocol Error in Data Phase interrupt */
    MCAN_INTR_SRC_RES_ADDR_ACCESS = (0x20000000U)
                                    /**< Access to Reserved Address interrupt */
}MCAN_IntrSrc;

/**
 *  \brief    Enum to represent the ECC Error Types
 */
typedef enum
{
    MCAN_ECC_ERR_TYPE_SEC = 0U,
    /**< ECC Single Error Correction */
    MCAN_ECC_ERR_TYPE_DED = 1U
                            /**< ECC Single Error Detection */
}MCAN_ECCErrType;

/**
 *  \brief    Enum to select the MCAN Loopback mode
 */
typedef enum
{
    MCAN_LPBK_MODE_INTERNAL = 0U,
    /**< Internal Loop Back Mode
     *   This mode can be used for hot self-test and this mode will not
     *   affect bus state.
     */
    MCAN_LPBK_MODE_EXTERNAL = 1U
                              /**< External Loop Back Mode
                               *   In this mode, MCAN the M_CAN treats its own
                               **transmitted messages as
                               *   received messages and stores them (if they
                               **pass acceptance filtering)
                               *   into an Rx Buffer or an Rx FIFO.
                               *   This mode will affect bus state
                               */
}MCAN_LpbkMode;

/**
 *  \brief    Enum to represent MCAN's communication state
 */
typedef enum
{
    MCAN_COM_STATE_SYNCHRONIZING = 0U,
    /**< MCAN is synchronizing on CAN communication */
    MCAN_COM_STATE_IDLE = 1U,
    /**< MCAN is neither receiver nor transmitter */
    MCAN_COM_STATE_RECEIVER = 2U,
    /**< MCAN is operating as receiver */
    MCAN_COM_STATE_TRANSMITTER = 3U
                                 /**< MCAN is operating as transmitter */
}MCAN_ComState;

/**
 *  \brief    Enum to represent MCAN's Error Code
 */
typedef enum
{
    MCAN_ERR_CODE_NO_ERROR = 0U,
    /**< No error occurred since LEC has been reset by
     *   successful reception or transmission.
     */
    MCAN_ERR_CODE_STUFF_ERROR = 1U,
    /**< More than 5 equal bits in a sequence have occurred in a part of
     *   a received message where this is not allowed.
     */
    MCAN_ERR_CODE_FORM_ERROR = 2U,
    /**< A fixed format part of a received frame has the wrong format. */
    MCAN_ERR_CODE_ACK_ERROR = 3U,
    /**< The message transmitted by the M_CAN was not acknowledged
     *   by another node.
     */
    MCAN_ERR_CODE_BIT1_ERROR = 4U,
    /**< During the transmission of a message (with the exception of
     *   the arbitration field), the device wanted to send a
     *   recessive level (bit of logical value ‘1’),
     *  but the monitored bus value was dominant.
     */
    MCAN_ERR_CODE_BIT0_ERROR = 5U,
    /**< During the transmission of a message (or acknowledge bit,
     *   or active error flag, or overload flag), the device wanted to send
     *   a dominant level (data or identifier bit logical value ‘0’),
     *   but the monitored bus value was recessive. During Bus_Off recovery
     *   this status is set each time a sequence of 11 recessive bits has been
     *   monitored. This enables the CPU to monitor the proceeding of
     *   the Bus_Off recovery sequence (indicating the bus is not stuck at
     *   dominant or continuously disturbed).
     */
    MCAN_ERR_CODE_CRC_ERROR = 6U,
    /**< The CRC check sum of a received message was incorrect.
     *   The CRC of an incoming message does not match with the
     *   CRC calculated from the received data.
     */
    MCAN_ERR_CODE_NO_CHANGE = 7U
                              /**< Any read access to the Protocol Status
                               * Register re-initializes
                               *   the LEC to ‘7’. When the LEC shows the value
                               ****‘7’,
                               *   no CAN bus event was detected since the last
                               ****CPU read access to
                               *   the Protocol Status Register.
                               */
}MCAN_ErrCode;

/**
 * \brief  Structure for bit timing calculation.
 *         Bit timing related to data phase will be valid only in case where
 *         MCAN is put in CAN-FD mode and will be '0' otherwise.
 */
typedef struct
{
    uint32_t nomRatePrescalar;
    /**< Nominal Baud Rate Pre-scaler
     *   Range:[0x0-0x1FF]
     */
    uint32_t nomTimeSeg1;
    /**< Nominal Time segment before sample point
     *   Range:[0x0-0xFF]
     */
    uint32_t nomTimeSeg2;
    /**< Nominal Time segment after sample point
     *   Range:[0x0-0x7F]
     */
    uint32_t nomSynchJumpWidth;
    /**< Nominal (Re)Synchronization Jump Width
     *   Range:[0x0-0x7F]
     */
    uint32_t dataRatePrescalar;
    /**< Data Baud Rate Pre-scaler
     *   Range:[0x0-0x1F]
     */
    uint32_t dataTimeSeg1;
    /**< Data Time segment before sample point
     *   Range:[0x0-0x1F]
     */
    uint32_t dataTimeSeg2;
    /**< Data Time segment after sample point
     *   Range:[0x0-0xF]
     */
    uint32_t dataSynchJumpWidth;
    /**< Data (Re)Synchronization Jump Width
     *   Range:[0x0-0xF]
     */
}MCAN_BitTimingParams;

/**
 * \brief  Structure for MCAN Transmitter Delay Compensation parameters.
 */
typedef struct
{
    uint32_t tdcf;
    /**< Transmitter Delay Compensation Filter Window Length
     *   Range:[0x0-0x7F]
     */
    uint32_t tdco;
    /**< Transmitter Delay Compensation Offset
     *   Range:[0x0-0x7F]
     */
}MCAN_TDCConfig;

/**
 * \brief  Structure for MCAN Global Filter Configuration parameters.
 */
typedef struct
{
    uint32_t rrfe;
    /**< Reject Remote Frames Extended
     *   0 = Filter remote frames with 29-bit extended IDs
     *   1 = Reject all remote frames with 29-bit extended IDs
     */
    uint32_t rrfs;
    /**< Reject Remote Frames Standard
     *   0 = Filter remote frames with 11-bit standard IDs
     *   1 = Reject all remote frames with 11-bit standard IDs
     */
    uint32_t anfe;
    /**< Accept Non-matching Frames Extended
     *   0 = Accept in Rx FIFO 0
     *   1 = Accept in Rx FIFO 1
     *   others = Reject
     */
    uint32_t anfs;
    /**< Accept Non-matching Frames Standard
     *   0 = Accept in Rx FIFO 0
     *   1 = Accept in Rx FIFO 1
     *   others = Reject
     */
}MCAN_GlobalFiltConfig;

/**
 * \brief  Structure for MCAN initialization parameters.
 */
typedef struct
{
    uint32_t       fdMode;
    /**< FD Operation Enable
     *   0 = FD operation disabled
     *   1 = FD operation enabled
     */
    uint32_t       brsEnable;
    /**< Bit Rate Switch Enable
     *   This is valid only when opMode = 1.
     *   0 = Bit rate switching for transmissions disabled
     *   1 = Bit rate switching for transmissions enabled
     */
    uint32_t       txpEnable;
    /**< Transmit Pause
     *   0 = Transmit pause disabled
     *   1 = Transmit pause enabled
     */
    uint32_t       efbi;
    /**< FEdge Filtering during Bus Integration
     *   0 = Edge filtering disabled
     *   1 = Two consecutive dominant tq required to detect an edge for
     *       hard synchronization
     */
    uint32_t       pxhddisable;
    /**< Protocol Exception Handling Disable
     *   0 = Protocol exception handling enabled
     *   1 = Protocol exception handling disabled
     */
    uint32_t       darEnable;
    /**< Disable Automatic Retransmission
     *   0 = Automatic retransmission of messages not transmitted successfully
     *       enabled
     *   1 = Automatic retransmission disabled
     */
    uint32_t       wkupReqEnable;
    /**< Wakeup Request Enable
     *   0 = Wakeup request is disabled
     *   1 = Wakeup request is enabled
     */
    uint32_t       autoWkupEnable;
    /**< Auto-Wakeup Enable
     *   0 = Auto-Wakeup is disabled
     *   1 = Auto-Wakeup is enabled
     */
    uint32_t       emulationEnable;
    /**< Emulation/Debug Suspend Enable
     *   0 = Emulation/Debug Suspend is disabled
     *   1 = Emulation/Debug Suspend is enabled
     */
    uint32_t       wdcPreload;
    /**< Start value of the Message RAM Watchdog Counter
     *   Range:[0x0-0xFF]
     */
    MCAN_TDCConfig tdcConfig;
    /**< Transmitter Delay Compensation parameters.
     *   Refer struct #MCAN_TDCConfig.
     */
    uint32_t       tdcEnable;
    /**< Transmitter Delay Compensation Enable
     *   0 = Transmitter Delay Compensation is disabled
     *   1 = Transmitter Delay Compensation is enabled
     */
}MCAN_InitParams;

/**
 * \brief  Structure for MCAN configuration parameters.
 */
typedef struct
{
    uint32_t              monEnable;
    /**< Bus Monitoring Mode
     *   0 = Bus Monitoring Mode is disabled
     *   1 = Bus Monitoring Mode is enabled
     */
    uint32_t              asmEnable;
    /**< Restricted Operation Mode
     *   0 = Normal CAN operation
     *   1 = Restricted Operation Mode active
     *   This mode should not be combined with test modes.
     */
    uint32_t              tsPrescalar;
    /**< Timestamp Counter Prescaler.
     *   Range:[0x0-0xF]
     */
    uint32_t              tsSelect;
    /**< Timestamp source selection.
     *   00= Timestamp counter value always 0x0000
     *   01= Timestamp counter value incremented according to tsPrescalar
     *   10= External timestamp counter value used
     *   11= Same as “00”
     */
    uint32_t              timeoutSelect;
    /**< Time-out counter source select.
     *   Refer enum #MCAN_TimeOutSelect.
     */
    uint32_t              timeoutPreload;
    /**< Start value of the Timeout Counter (down-counter).
     *   The Timeout Counter is decremented in multiples of CAN bit times [1-16]
     *   depending on the configuration of the tsPrescalar.
     *   Range:[0x0-0xFFFF]
     */
    uint32_t              timeoutCntEnable;
    /**< Time-out Counter Enable
     *   0 = Time-out Counter is disabled
     *   1 = Time-out Counter is enabled
     */
    MCAN_GlobalFiltConfig filterConfig;
    /**< Global Filter Configuration parameters.
     *    Refer struct #MCAN_GlobalFiltConfig.
     */
}MCAN_ConfigParams;

/**
 * \brief  Structure for MCAN error logging counters status.
 */
typedef struct
{
    uint32_t transErrLogCnt;
    /**< Transmit Error Counter */
    uint32_t recErrCnt;
    /**< Receive Error Counter */
    uint32_t rpStatus;
    /**< Receive Error Passive
     *   0 = The Receive Error Counter is below the error passive level(128)
     *   1 = The Receive Error Counter has reached the error passive level(128)
     */
    uint32_t canErrLogCnt;
    /**< CAN Error Logging */
}MCAN_ErrCntStatus;

/**
 * \brief  Structure for MCAN protocol status.
 */
typedef struct
{
    uint32_t lastErrCode;
    /**< Last Error Code
     *   Refer enum #MCAN_ErrCode
     */
    uint32_t act;
    /**< Activity - Monitors the module’s CAN communication state.
     *   refer enum #MCAN_ComState
     */
    uint32_t errPassive;
    /**< Error Passive
     *   0 = The M_CAN is in the Error_Active state
     *   1 = The M_CAN is in the Error_Passive state
     */
    uint32_t warningStatus;
    /**< Warning Status
     *   0 = Both error counters are below the Error_Warning limit of 96
     *   1 = At least one of error counter has reached the Error_Warning
     *       limit of 96
     */
    uint32_t busOffStatus;
    /**< Bus_Off Status
     *   0 = The M_CAN is not Bus_Off
     *   1 = The M_CAN is in Bus_Off state
     */
    uint32_t dlec;
    /**< Data Phase Last Error Code
     *   Refer enum #MCAN_ErrCode
     */
    uint32_t resi;
    /**< ESI flag of last received CAN FD Message
     *   0 = Last received CAN FD message did not have its ESI flag set
     *   1 = Last received CAN FD message had its ESI flag set
     */
    uint32_t rbrs;
    /**< BRS flag of last received CAN FD Message
     *   0 = Last received CAN FD message did not have its BRS flag set
     *   1 = TLast received CAN FD message had its BRS flag set
     */
    uint32_t rfdf;
    /**< Received a CAN FD Message
     *   0 = Since this bit was reset by the CPU, no CAN FD message has been
     *       received
     *   1 = Message in CAN FD format with FDF flag set has been received
     */
    uint32_t pxe;
    /**< Protocol Exception Event
     *   0 = No protocol exception event occurred since last read access
     *   1 = Protocol exception event occurred
     */
    uint32_t tdcv;
    /**< Transmitter Delay Compensation Value */
}MCAN_ProtocolStatus;

/**
 * \brief  Structure for MCAN Message RAM Configuration Parameters.
 *         Message RAM can contain following sections:
 *         Standard ID filters, Extended ID filters, TX FIFO(or TX Q),
 *         TX Buffers, TX EventFIFO, RX FIFO0, RX FIFO1, RX Buffer.
 *         Note: If particular section in the RAM is not used then it's size
 *         should be initialized to '0'
 *         (Number of buffers in case of Tx/Rx buffer).
 */
typedef struct
{
    uint32_t flssa;
    /**< Standard ID Filter List Start Address */
    uint32_t lss;
    /**< List Size: Standard ID
     *   0 = No standard Message ID filter
     *   1-127 = Number of standard Message ID filter elements
     *   others = Values greater than 128 are interpreted as 128
     */
    uint32_t flesa;
    /**< Extended ID Filter List Start Address */
    uint32_t lse;
    /**< List Size: Extended ID
     *   0 = No standard Message ID filter
     *   1-64 = Number of standard Message ID filter elements
     *   others = Values greater than 64 are interpreted as 64
     */
    uint32_t txStartAddr;
    /**< Tx Buffers Start Address */
    uint32_t txBufNum;
    /**< Number of Dedicated Transmit Buffers
     *   0 = No Dedicated Tx Buffers
     *   1-32 = Number of Dedicated Tx Buffers
     *   others = Values greater than 32 are interpreted as 32
     */
    uint32_t txFIFOSize;
    /**< Transmit FIFO/Queue Size
     *   0 = No Tx FIFO/Queue
     *   1-32 = Number of Tx Buffers used for Tx FIFO/Queue
     *   others = Values greater than 32 are interpreted as 32
     */
    uint32_t txBufMode;
    /**< Tx FIFO/Queue Mode
     *   0 = Tx FIFO operation
     *   1 = Tx Queue operation
     */
    uint32_t txBufElemSize;
    /**< Tx Buffer Element Size */
    uint32_t txEventFIFOStartAddr;
    /**< Tx Event FIFO Start Address */
    uint32_t txEventFIFOSize;
    /**< Event FIFO Size
     *   0 = Tx Event FIFO disabled
     *   1-32 = Number of Tx Event FIFO elements
     *   others = Values greater than 32 are interpreted as 32
     */
    uint32_t txEventFIFOWaterMark;
    /**< Tx Event FIFO Watermark
     *   0 = Watermark interrupt disabled
     *   1-32 = Level for Tx Event FIFO watermark interrupt
     *   others = Watermark interrupt disabled
     */
    uint32_t rxFIFO0startAddr;
    /**< Rx FIFO0 Start Address */
    uint32_t rxFIFO0size;
    /**< Rx FIFO0 Size
     *   0 = No Rx FIFO
     *   1-64 = Number of Rx FIFO elements
     *   others = Values greater than 64 are interpreted as 64
     */
    uint32_t rxFIFO0waterMark;
    /**< Rx FIFO0 Watermark
     *   0 = Watermark interrupt disabled
     *   1-63 = Level for Rx FIFO 0 watermark interrupt
     *   others = Watermark interrupt disabled
     */
    uint32_t rxFIFO0OpMode;
    /**< Rx FIFO0 Operation Mode
     *   0 = FIFO blocking mode
     *   1 = FIFO overwrite mode
     */
    uint32_t rxFIFO1startAddr;
    /**< Rx FIFO1 Start Address */
    uint32_t rxFIFO1size;
    /**< Rx FIFO1 Size
     *   0 = No Rx FIFO
     *   1-64 = Number of Rx FIFO elements
     *   others = Values greater than 64 are interpreted as 64
     */
    uint32_t rxFIFO1waterMark;
    /**< Rx FIFO1 Watermark
     *   0 = Watermark interrupt disabled
     *   1-63 = Level for Rx FIFO 1 watermark interrupt
     *   others = Watermark interrupt disabled
     */
    uint32_t rxFIFO1OpMode;
    /**< Rx FIFO1 Operation Mode
     *   0 = FIFO blocking mode
     *   1 = FIFO overwrite mode
     */
    uint32_t rxBufStartAddr;
    /**< Rx Buffer Start Address */
    uint32_t rxBufElemSize;
    /**< Rx Buffer Element Size */
    uint32_t rxFIFO0ElemSize;
    /**< Rx FIFO0 Element Size */
    uint32_t rxFIFO1ElemSize;
    /**< Rx FIFO1 Element Size */
}MCAN_MsgRAMConfigParams;

/**
 * \brief  Structure for MCAN High Priority Message.
 */
typedef struct
{
    uint32_t bufIdx;
    /**< Buffer Index
     *   Only valid when MSI[1] = ‘1’.
     */
    uint32_t msi;
    /**< Message Storage Indicator
     *   MSI[1:0]
     *       00  = No FIFO selected
     *       01  = FIFO message lost
     *       10  = Message stored in FIFO 0
     *       11  = Message stored in FIFO 1
     */
    uint32_t filterIdx;
    /**< Filter Index */
    uint32_t filterList;
    /**< Indicates the filter list of the matching filter element
     *   0 = Standard Filter List
     *   1 = Extended Filter List
     */
}MCAN_HighPriorityMsgInfo;

/**
 * \brief  Structure for MCAN new data flag for Rx buffer.
 */
typedef struct
{
    uint32_t statusLow;
    /**< New data flag for Rx buffer no. 0 to 31 */
    uint32_t statusHigh;
    /**< New data flag for Rx buffer no. 32 to 63 */
}MCAN_RxNewDataStatus;

/**
 * \brief  Structure for MCAN Rx FIFO Status.
 */
typedef struct
{
    uint32_t num;
    /**< Rx FIFO number
     *   Refer enum #MCAN_RxFIFONum
     */
    uint32_t fillLvl;
    /**< Rx FIFO Fill Level */
    uint32_t getIdx;
    /**< Rx FIFO Get Index */
    uint32_t putIdx;
    /**< Rx FIFO Put Index */
    uint32_t fifoFull;
    /**< Rx FIFO Full
     *   0 = Rx FIFO not full
     *   1 = Rx FIFO full
     */
    uint32_t msgLost;
    /**< Rx FIFO Message Lost */
}MCAN_RxFIFOStatus;

/**
 * \brief  Structure for MCAN Tx FIFO Status.
 */
typedef struct
{
    uint32_t freeLvl;
    /**< Tx FIFO Free Level */
    uint32_t getIdx;
    /**< Tx FIFO Get Index
     *   Read as zero when Tx Queue operation is configured.
     */
    uint32_t putIdx;
    /**< Tx FIFO/Queue Put Index */
    uint32_t fifoFull;
    /**< Tx FIFO/Queue Full
     *   0 = Tx FIFO/Queue not full
     *   1 = Tx FIFO/Queue full
     */
}MCAN_TxFIFOStatus;

/**
 * \brief  Structure for MCAN Tx Event FIFO Status.
 */
typedef struct
{
    uint32_t fillLvl;
    /**< Event FIFO Fill Level */
    uint32_t getIdx;
    /**< Event FIFO Gut Index */
    uint32_t putIdx;
    /**< Event FIFO Put Index */
    uint32_t fifoFull;
    /**< Event FIFO Full
     *   0 = Tx Event FIFO not full
     *   1 = Tx Event FIFO full
     */
    uint32_t eleLost;
    /**< Tx Event FIFO Element Lost
     *   0 = No Tx Event FIFO element lost
     *   1 = Tx Event FIFO element lost, also set after write attempt to
     *       Tx Event FIFO of size zero.
     */
}MCAN_TxEventFIFOStatus;

/**
 * \brief  Structure for ECC Error forcing.
 */
typedef struct
{
    uint32_t errType;
    /**< Error type to be forced
     *   Refer enum  #MCAN_ECCErrType.
     */
    uint32_t rowNum;
    /**< Row address where error needs to be applied. */
    uint32_t bit1;
    /**< Column/Data bit that needs to be flipped when
     *   force_sec or force_ded is set
     */
    uint32_t bit2;
    /**< Data bit that needs to be flipped when force_ded is set */
    uint32_t errOnce;
    /**< Force Error once
     *   1: The error will inject an error to the specified row only once
     */
    uint32_t errForce;
    /**< Force error on the next RAM read */
}MCAN_ECCErrForceParams;

/**
 * \brief  Structure for ECC Error Status.
 */
typedef struct
{
    uint32_t secErr;
    /**< Single Bit Error Status
     *   0 = No Single Bit Error pending
     *   1 = Single Bit Error pending
     */
    uint32_t dedErr;
    /**< Double Bit Error Status
     *   0 = No Double Bit Error pending
     *   1 = Double Bit Error pending
     */
    uint32_t row;
    /**< Indicates the row/address where the single or double bit
     *   error occurred.
     */
    uint32_t bit1;
    /**< Indicates the bit position in the ram data that is in error
     */
}MCAN_ECCErrStatus;

/**
 * \brief  Structure for accessing Revision ID and Core Release Info.
 *         of MCAN module.
 */
typedef struct
{
    uint32_t scheme;
    /**< Scheme */
    uint32_t bu;
    /**< Business Unit: 10 = Processors */
    uint32_t modId;
    /**< Module ID */
    uint32_t rtlRev;
    /**< RTL revision */
    uint32_t major;
    /**< Major revision */
    uint32_t custom;
    /**< Custom revision */
    uint32_t minor;
    /**< Minor revision */
    uint32_t day;
    /**< Time Stamp Day. Two digits, BCD-coded. */
    uint32_t mon;
    /**< Time Stamp Month. Two digits, BCD-coded. */
    uint32_t year;
    /**< Time Stamp Year. Single digit, BCD-coded. */
    uint32_t subStep;
    /**< Sub-step of Core Release Single digit, BCD-coded. */
    uint32_t step;
    /**< Step of Core Release.Two digits, BCD-coded Single digit, BCD-coded. */
    uint32_t rel;
    /**< Core Release. Single digit, BCD-coded. */
}MCAN_RevisionId;

/**
 * \brief  Structure for accessing Revision ID of ECC AGGR.
 */
typedef struct
{
    uint32_t scheme;
    /**< Scheme */
    uint32_t bu;
    /**< Business Unit: 10 = Processors */
    uint32_t modId;
    /**< Module ID */
    uint32_t rtlRev;
    /**< RTL revision */
    uint32_t major;
    /**< Major revision */
    uint32_t custom;
    /**< Custom revision */
    uint32_t minor;
    /**< Minor revision */
}MCAN_ECCAggrRevisionId;

/**
 * \brief  Structure for MCAN ECC configuration parameters.
 */
typedef struct
{
    uint32_t enable;
    /**< Enable/disable ECC
     *   0 = Disable ECC
     *   1 = Enable ECC
     */
    uint32_t enableChk;
    /**< Enable/disable ECC Check
     *   0 = Disable ECC Check
     *   1 = Enable ECC Check
     */
    uint32_t enableRdModWr;
    /**< Enable/disable Read Modify Write operation
     *   0 = Disable Read Modify Write operation
     *   1 = Enable Read Modify Write operation
     */
}MCAN_ECCConfigParams;

/**
 * \brief  Structure for accessing Revision ID of ECC wrapper.
 */
typedef struct
{
    uint32_t scheme;
    /**< Scheme */
    uint32_t bu;
    /**< Business Unit: 10 = Processors */
    uint32_t modId;
    /**< Module ID */
    uint32_t rtlRev;
    /**< RTL revision */
    uint32_t major;
    /**< Major revision */
    uint32_t custom;
    /**< Custom revision */
    uint32_t minor;
    /**< Minor revision */
}MCAN_ECCWrapRevisionId;

/**
 * \brief  Structure for MCAN Tx Buffer element.
 */
typedef struct
{
    uint32_t id;
    /**< Identifier */
    uint32_t rtr;
    /**< Remote Transmission Request
     *   0 = Transmit data frame
     *   1 = Transmit remote frame
     */
    uint32_t xtd;
    /**< Extended Identifier
     *   0 = 11-bit standard identifier
     *   1 = 29-bit extended identifier
     */
    uint32_t esi;
    /**< Error State Indicator
     *   0 = ESI bit in CAN FD format depends only on error passive flag
     *   1 = ESI bit in CAN FD format transmitted recessive
     */
    uint32_t dlc;
    /**< Data Length Code
     *   0-8  = CAN + CAN FD: transmit frame has 0-8 data bytes
     *   9-15 = CAN: transmit frame has 8 data bytes
     *   9-15 = CAN FD: transmit frame has 12/16/20/24/32/48/64 data bytes
     */
    uint32_t brs;
    /**< Bit Rat Switching
     *   0 = CAN FD frames transmitted without bit rate switching
     *   1 = CAN FD frames transmitted with bit rate switching
     */
    uint32_t fdf;
    /**< FD Format
     *   0 = Frame transmitted in Classic CAN format
     *   1 = Frame transmitted in CAN FD format
     */
    uint32_t efc;
    /**< Event FIFO Control
     *   0 = Don’t store Tx events
     *   1 = Store Tx events
     */
    uint32_t mm;
    /**< Message Marker */
    uint16_t  data[(64U)];
    /**< Data bytes.
     *   Only first dlc number of bytes are valid.
     */
}MCAN_TxBufElement;

/**
 * \brief  Structure for MCAN Rx Buffer element.
 */
typedef struct
{
    uint32_t id;
    /**< Identifier */
    uint32_t rtr;
    /**< Remote Transmission Request
     *   0 = Received frame is a data frame
     *   1 = Received frame is a remote frame
     */
    uint32_t xtd;
    /**< Extended Identifier
     *   0 = 11-bit standard identifier
     *   1 = 29-bit extended identifier
     */
    uint32_t esi;
    /**< Error State Indicator
     *   0 = Transmitting node is error active
     *   1 = Transmitting node is error passive
     */
    uint32_t rxts;
    /**< Rx Timestamp */
    uint32_t dlc;
    /**< Data Length Code
     *   0-8  = CAN + CAN FD: received frame has 0-8 data bytes
     *   9-15 = CAN: received frame has 8 data bytes
     *   9-15 = CAN FD: received frame has 12/16/20/24/32/48/64 data bytes
     */
    uint32_t brs;
    /**< Bit Rat Switching
     *   0 = Frame received without bit rate switching
     *   1 = Frame received with bit rate switching
     */
    uint32_t fdf;
    /**< FD Format
     *   0 = Standard frame format
     *   1 = CAN FD frame format (new DLC-coding and CRC)
     */
    uint32_t fidx;
    /**< Filter Index */
    uint32_t anmf;
    /**< Accepted Non-matching Frame
     *   0 = Received frame matching filter index FIDX
     *   1 = Received frame did not match any Rx filter element
     */
    uint16_t  data[(64U)];
    /**< Data bytes.
     *   Only first dlc number of bytes are valid.
     */
}MCAN_RxBufElement;

/**
 * \brief  Structure for MCAN Tx Event FIFO element.
 */
typedef struct
{
    uint32_t id;
    /**< Identifier */
    uint32_t rtr;
    /**< Remote Transmission Request
     *   0 = Data frame transmitted
     *   1 = Remote frame transmitted
     */
    uint32_t xtd;
    /**< Extended Identifier
     *   0 = 11-bit standard identifier
     *   1 = 29-bit extended identifier
     */
    uint32_t esi;
    /**< Error State Indicator
     *   0 = Transmitting node is error active
     *   1 = Transmitting node is error passive
     */
    uint32_t txts;
    /**< Tx Timestamp */
    uint32_t dlc;
    /**< Data Length Code
     *   0-8  = CAN + CAN FD: frame with 0-8 data bytes transmitted
     *   9-15 = CAN: frame with 8 data bytes transmitted
     *   9-15 = CAN FD: frame with 12/16/20/24/32/48/64 data bytes transmitted
     */
    uint32_t brs;
    /**< Bit Rat Switching
     *   0 = Frame transmitted without bit rate switching
     *   1 = Frame transmitted with bit rate switching
     */
    uint32_t fdf;
    /**< FD Format
     *   0 = Standard frame format
     *   1 = CAN FD frame format (new DLC-coding and CRC)
     */
    uint32_t et;
    /**< Event Type
     *   00 = Reserved
     *   01 = Tx event
     *   10 = Transmission in spite of cancellation
     *        (always set for transmissions in DAR mode)
     *   11 = Reserved
     */
    uint32_t mm;
    /**< Message Marker */
}MCAN_TxEventFIFOElement;

/**
 * \brief  Structure for MCAN Standard Message ID Filter Element.
 */
typedef struct
{
    uint32_t sfid2;
    /**< Standard Filter ID 2 */
    uint32_t sfid1;
    /**< Standard Filter ID 1 */
    uint32_t sfec;
    /**< Standard Filter Element Configuration
     *   000 = Disable filter element
     *   001 = Store in Rx FIFO 0 if filter matches
     *   010 = Store in Rx FIFO 1 if filter matches
     *   011 = Reject ID if filter matches
     *   100 = Set priority if filter matches
     *   101 = Set priority and store in FIFO 0 if filter matches
     *   110 = Set priority and store in FIFO 1 if filter matches
     *   111 = Store into Rx Buffer or as debug message,
     *         configuration of SFT[1:0] ignored.
     *   If SFEC = “100”, “101”, or “110” a match sets high priority
     *   message event is generated.
     */
    uint32_t sft;
    /**< Standard Filter Type
     *   00 = Range filter from SFID1 to SFID2 (SFID2 ≥ SFID1)
     *   01 = Dual ID filter for SFID1 or SFID2
     *   10 = Classic filter: SFID1 = filter, SFID2 = mask
     *   11 = Filter element disabled
     */
}MCAN_StdMsgIDFilterElement;

/**
 * \brief  Structure for MCAN Extended Message ID Filter Element.
 */
typedef struct
{
    uint32_t efid1;
    /**< Extended Filter ID 1 */
    uint32_t efec;
    /**< Extended Filter Element Configuration
     *   000 = Disable filter element
     *   001 = Store in Rx FIFO 0 if filter matches
     *   010 = Store in Rx FIFO 1 if filter matches
     *   011 = Reject ID if filter matches
     *   100 = Set priority if filter matches
     *   101 = Set priority and store in FIFO 0 if filter matches
     *   110 = Set priority and store in FIFO 1 if filter matches
     *   111 = Store into Rx Buffer or as debug message,
     *         configuration of SFT[1:0] ignored.
     *   If EFEC = “100”, “101”, or “110” a match sets high priority
     *   message event is generated.
     */
    uint32_t efid2;
    /**< Extended Filter ID 2 */
    uint32_t eft;
    /**< Extended Filter Type
     *   00 = Range filter from EFID1 to EFID2 (EFID2 ≥ EFID1)
     *   01 = Dual ID filter for EFID1 or EFID2
     *   10 = Classic filter: EFID1 = filter, EFID2 = mask
     *   11 = Range filter from EFID1 to EFID2 (EFID2 ≥ EFID1),
     *        XIDAM mask not applied
     */
}MCAN_ExtMsgIDFilterElement;

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */


/**
 * \brief   This function checks if the MCAN module is in Reset.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \retval  state           Returns TRUE if reset is in progress.
 *                          Else returns FALSE.
 */
uint32_t MCAN_isInReset(uint32_t baseAddr);

/**
 * \brief   This API will return flexible data rate operation status
 *          MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  state           Returns TRUE if flexible data rate operation
 *                          is enabled. Else returns FALSE.
 */
uint32_t MCAN_isFDOpEnable(uint32_t baseAddr);

/**
 * \brief   This function checks if the memory initialization is done for
 *          MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \retval  state           Returns TRUE if memory initialization is done.
 *                          Else returns FALSE.
 */
uint32_t MCAN_isMemInitDone(uint32_t baseAddr);

/**
 * \brief   This API will set MCAN module mode of operation.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   mode            Mode of operation.
 *                          Refer enum #MCAN_OperationMode.
 *
 * \return  None.
 */
void MCAN_setOpMode(uint32_t baseAddr, uint32_t mode);

/**
 * \brief   This API will return MCAN module mode of operation.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  mode            Mode of operation.
 *                          Refer enum #MCAN_OperationMode.
 */
uint32_t MCAN_getOpMode(uint32_t baseAddr);

/**
 * \brief   This API will initialize MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   initParams      Initialization parameters.
 *                          Refer struct #MCAN_InitParams.
 *
 * \return  status          Initialization status.
 */
int32_t MCAN_init(uint32_t baseAddr, const MCAN_InitParams *initParams);

/**
 * \brief   This API will configure MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   configParams    configuration parameters.
 *                          Refer struct #MCAN_ConfigParams.
 *
 * \return  status          Configuration status.
 */
int32_t MCAN_config(uint32_t baseAddr, const MCAN_ConfigParams *configParams);

/**
 * \brief   This API will enable/disable ECC on the Message RAM.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   configParams    MCAN ECC Configuration Parameters.
 *                          Refer #struct MCAN_ECCConfigParams.
 *
 * \return  None.
 */
void MCAN_eccConfig(uint32_t                    baseAddr,
                    const MCAN_ECCConfigParams *configParams);

/**
 * \brief   This API will configure a bit timings for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   configParams    Configuration parameters for MCAN bit timing.
 *                          Refer struct #MCAN_BitTimingParams.
 *
 * \return  status          Bit Timings configuration status.
 */
int32_t MCAN_setBitTime(uint32_t                    baseAddr,
                        const MCAN_BitTimingParams *configParams);

/**
 * \brief   This API will configure Different sections of Message RAM.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   msgRAMConfigParams
 *                          Message RAM Configuration parameters.
 *                          Refer struct #MCAN_MsgRAMConfigParams.
 *
 * \return  status          Configuration Status.
 */
int32_t MCAN_msgRAMConfig(uint32_t                       baseAddr,
                          const MCAN_MsgRAMConfigParams *msgRAMConfigParams);

/**
 * \brief   This API will configure Extended ID AND Mask.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   idMask          Configuration parameters for MCAN Extended Id mask.
 *                          This value is 29 bit wide.
 *
 * \return  status          Extended ID AND Mask configuration status.
 */
int32_t MCAN_setExtIDAndMask(uint32_t baseAddr, uint32_t idMask);

/**
 * \brief   This API is used to write Tx message to message RAM.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   memType         Part of message ram to which given message to write.
 *                          Refer enum #MCAN_MemType.
 * \param   bufNum          Buffer  number where message to write.
 *                          This parameter will ignored if memType is FIFO/Q.
 * \param   elem            Message Object.
 *                          Refer struct #MCAN_TxBufElement.
 *
 * \return  None.
 */
void MCAN_writeMsgRam(uint32_t                 baseAddr,
                      uint32_t                 memType,
                      uint32_t                 bufNum,
                      const MCAN_TxBufElement *elem);

/**
 * \brief   This API will set Tx Buffer Add Request.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   bufNum          Tx Buffer number for which request is to be added.
 *
 * \return  status          Configuration Status.
 */
int32_t MCAN_txBufAddReq(uint32_t baseAddr, uint32_t bufNum);

/**
 * \brief   This API will return New Data Message Status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   newDataStatus   Rx Buffer new data status.
 *                          Refer struct #MCAN_RxNewDataStatus.
 *
 * \return  None.
 */
void  MCAN_getNewDataStatus(uint32_t              baseAddr,
                            MCAN_RxNewDataStatus *newDataStatus);

/**
 * \brief   This API clear New Data Message Status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   newDataStatus
 *                          Rx Buffer new data status.
 *                          Refer struct #MCAN_RxNewDataStatus.
 *
 * \return  None.
 */
void  MCAN_clearNewDataStatus(uint32_t                    baseAddr,
                              const MCAN_RxNewDataStatus *newDataStatus);

/**
 * \brief   This API is used to read received message form message RAM.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   memType         Part of message ram to which given message to write.
 *                          Refer enum #MCAN_MemType.
 * \param   bufNum          Buffer  number from where message is to read.
 *                          This parameter will ignored if memType is FIFO/Q.
 *  \param  fifoNum         FIFOs number from where message is to read.
 *                          Refer enum #MCAN_RxFIFONum.
 *                          This parameter will ignored if memType is buffer.
 * \param   elem            Message Object.
 *                          Refer struct #MCAN_RxBufElement.
 *
 * \return  None.
 */
void MCAN_readMsgRam(uint32_t           baseAddr,
                     uint32_t           memType,
                     uint32_t           bufNum,
                     uint32_t           fifoNum,
                     MCAN_RxBufElement *elem);

/**
 * \brief   This API is used to read message form Tx Event FIFO.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   txEventElem     Tx Event FIFO Message Object.
 *                          Refer struct #MCAN_TxEventFIFOElement.
 *
 * \return  None.
 */
void MCAN_readTxEventFIFO(uint32_t           baseAddr,
                          MCAN_TxEventFIFOElement *txEventElem);

/**
 * \brief   This API is used to add Standard Message ID Filter Element.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   filtNum         Filter number.
 * \param   elem            Filter Object.
 *                          Refer struct #MCAN_StdMsgIDFilterElement.
 *
 * \return  None.
 */
void MCAN_addStdMsgIDFilter(uint32_t                          baseAddr,
                            uint32_t                          filtNum,
                            const MCAN_StdMsgIDFilterElement *elem);

/**
 * \brief   This API is used to add Extended Message ID Filter Element.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   filtNum         Filter  number.
 * \param   elem            Filter Object.
 *                          Refer struct #MCAN_ExtMsgIDFilterElement.
 *
 * \return  None.
 */
void MCAN_addExtMsgIDFilter(uint32_t                          baseAddr,
                            uint32_t                          filtNum,
                            const MCAN_ExtMsgIDFilterElement *elem);

/**
 * \brief   This API will enable/disable Loop Back Test Mode for
 *          MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   lpbkMode        Loopback mode for MCAN.
 *                          Refer #enum MCAN_LpbkMode.
 * \param   enable          Loop Back Mode is enabled if it is TRUE.
 *                          Loop Back Mode is disabled  if it is FALSE.
 *
 * \return  None.
 * \note    This API can be called only when MCAN is in Software
 *          Initialization mode of operation.
 */
void MCAN_lpbkModeEnable(uint32_t baseAddr,
                         uint32_t lpbkMode,
                         uint32_t enable);

/**
 * \brief   This API will return error counter status for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   errCounter      Error Counter Status.
 *                          Refer struct #MCAN_ErrCntStatus.
 *
 * \return  None.
 */
void  MCAN_getErrCounters(uint32_t           baseAddr,
                          MCAN_ErrCntStatus *errCounter);

/**
 * \brief   This API will return protocol status for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   protStatus      Protocol Status.
 *                          Refer struct #MCAN_ProtocolStatus.
 *
 * \return  None.
 */
void  MCAN_getProtocolStatus(uint32_t             baseAddr,
                             MCAN_ProtocolStatus *protStatus);

/**
 * \brief   This API is used to enable/disable interrupts.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   intrMask        Interrupts to enable.
 *                          Refer enum #MCAN_IntrSrc.
 * \param   enable          Interrupt is enabled if it is TRUE.
 *                          Interrupt is disabled  if it is FALSE.
 *
 * \return  None.
 */
void MCAN_enableIntr(uint32_t baseAddr, uint32_t intrMask, uint32_t enable);

/**
 * \brief   This API is used to select interrupt line.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   intrMask        Interrupt Number for which interrupt
 *                          line is to be selected. Refer enum #MCAN_IntrSrc.
 * \param   lineNum         Interrupt Line to select.
 *                          Refer enum #MCAN_IntrLineNum,
 *
 * \return  None.
 */
void MCAN_selectIntrLine(uint32_t baseAddr,
                         uint32_t intrMask,
                         uint32_t lineNum);

/**
 * \brief   This API is used to get interrupt line selected for each interrupt.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Interrupt Line Select Status.
 */
uint32_t MCAN_getIntrLineSelectStatus(uint32_t baseAddr);

/**
 * \brief   This API is used to enable/disable selected interrupt line.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   lineNum         Interrupt Line to select.
 *                          Refer enum #MCAN_IntrLineNum,
 * \param   enable          Interrupt Line is enabled if it is 1.
 *                          Interrupt Line is disabled  if it is 0.
 *
 * \return  None.
 */
void MCAN_enableIntrLine(uint32_t baseAddr,
                         uint32_t lineNum,
                         uint32_t enable);

/**
 * \brief   This API will return interrupt status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Interrupt Status.
 */
uint32_t MCAN_getIntrStatus(uint32_t baseAddr);

/**
 * \brief   This API is used to clear the interrupt status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   intrMask        Interrupts to clear status.
 *
 * \return  None.
 */
void MCAN_clearIntrStatus(uint32_t baseAddr, uint32_t intrMask);

/**
 * \brief   This API will return High Priority Message Status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   hpm             High Priority Message Status.
 *                          Refer struct #MCAN_HighPriorityMsgInfo.
 *
 * \return  None.
 */
void  MCAN_getHighPriorityMsgStatus(uint32_t                  baseAddr,
                                    MCAN_HighPriorityMsgInfo *hpm);

/**
 * \brief   This API will Rx FIFO status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   fifoStatus      Rx FIFO Status.
 *                          Refer struct #MCAN_RxFIFOStatus.
 *
 * \return  None.
 */
void MCAN_getRxFIFOStatus(uint32_t           baseAddr,
                          MCAN_RxFIFOStatus *fifoStatus);

/**
 * \brief   This API will write Rx FIFO Acknowledgement.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *                          Refer enum #MCAN_RxFIFONum.
 * \param   fifoNum         FIFO Number.
 * \param   idx             Rx FIFO Acknowledge Index
 *
 * \return  status          Acknowledgement Status.
 */
int32_t MCAN_writeRxFIFOAck(uint32_t baseAddr,
                            uint32_t fifoNum,
                            uint32_t idx);

/**
 * \brief   This API will Tx FIFO status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   fifoStatus      Tx FIFO Status.
 *                          Refer struct #MCAN_TxFIFOStatus.
 *
 * \return  None.
 */
void MCAN_getTxFIFOQueStatus(uint32_t           baseAddr,
                             MCAN_TxFIFOStatus *fifoStatus);

/**
 * \brief   This API will return Tx Buffer Request Pending status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Tx Buffer Request Pending status.
 */
uint32_t MCAN_getTxBufReqPend(uint32_t baseAddr);

/**
 * \brief   This API will set Tx Buffer Cancellation Request.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   buffNum         Tx Buffer number for which request is to be added.
 *
 * \return  status          Configuration Status.
 */
int32_t MCAN_txBufCancellationReq(uint32_t baseAddr, uint32_t buffNum);

/**
 * \brief   This API will return Tx Buffer Transmission Occurred status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Tx Buffer Transmission Occurred status.
 */
uint32_t MCAN_getTxBufTransmissionStatus(uint32_t baseAddr);

/**
 * \brief   This API will return Transmit Buffer Cancellation Finished status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Transmit Buffer Cancellation Finished status.
 */
uint32_t MCAN_txBufCancellationStatus(uint32_t baseAddr);

/**
 * \brief   This API is used to enable/disable Tx Buffer Transmission Interrupt.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   bufNum          Buffer number for which interrupt is to enable.
 * \param   enable          Interrupt is enabled if it is TRUE.
 *                          Interrupt is disabled  if it is FALSE.
 *
 * \return  status          Configuration status.
 */
int32_t MCAN_txBufTransIntrEnable(uint32_t baseAddr,
                                  uint32_t bufNum,
                                  uint32_t enable);

/**
 * \brief   This API is used to enable/disable Tx Buffer Cancellation Finished
 *          Interrupt.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   bufNum         Buffer number for which interrupt is to enable.
 * \param   enable          Interrupt is enabled if it is TRUE.
 *                          Interrupt is disabled  if it is FALSE.
 *
 * \return  status          Configuration status.
 */
int32_t MCAN_getTxBufCancellationIntrEnable(uint32_t baseAddr,
                                            uint32_t bufNum,
                                            uint32_t enable);

/**
 * \brief   This API add clock stop request for MCAN module to put it in
 *          power down mode.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   enable          Add CLock Stop Request.
 *                          Adds Clock Clock stop Request is TRUE otherwise
 *                          removes it.
 *
 * \return  None.
 */
void MCAN_addClockStopRequest(uint32_t baseAddr, uint32_t enable);

/**
 * \brief   This API will Tx Event FIFO status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   fifoStatus      Tx Event FIFO Status.
 *                          Refer struct #MCAN_TxEventFIFOStatus.
 *
 * \return  None.
 */
void MCAN_getTxEventFIFOStatus(uint32_t                baseAddr,
                               MCAN_TxEventFIFOStatus *fifoStatus);

/**
 * \brief   This API will write Event FIFO Acknowledge Index.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   idx             Event FIFO Acknowledge Index
 *
 * \return  status          Acknowledgement Status.
 */
int32_t MCAN_writeTxEventFIFOAck(uint32_t baseAddr, uint32_t idx);

/**
 * \brief   This API will Force Error on ECC.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   eccErr          Force Error on ECC configuration.
 *                          Refer struct #MCAN_ECCErrForceParams.
 *
 * \return  status          configuration status.
 */
void MCAN_eccForceError(uint32_t                      baseAddr,
                        const MCAN_ECCErrForceParams *eccErr);

/**
 * \brief   This API will return ECC Error status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   eccErr          ECC error status.
 *                          Refer struct #MCAN_ECCErrStatus.
 *
 * \return  None.
 */
void MCAN_eccGetErrorStatus(uint32_t           baseAddr,
                            MCAN_ECCErrStatus *eccErr);

/**
 * \brief   This API is used to clear the ECC Error status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   errType         Error type to clear status.
 *                          Refer enum #MCAN_ECCErrType.
 *
 * \return  None.
 */
void MCAN_eccClearErrorStatus(uint32_t baseAddr, uint32_t errType);

/**
 * \brief   This API is used to write End of Interrupt for ECC interrupt.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   errType         Interrupt to enable.
 *                          Refer enum #MCAN_ECCErrType.
 *
 * \return  None.
 */
void MCAN_eccWriteEOI(uint32_t baseAddr, uint32_t errType);

/**
 * \brief   This API is used to enable ECC interrupt.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   errType         Interrupt to enable.
 *                          Refer enum #MCAN_ECCErrType.
 * \param   enable          ECC Interrupt is enabled if it is TRUE.
 *                          ECC Interrupt is disabled  if it is FALSE.
 *
 * \return  None.
 */
void MCAN_eccEnableIntr(uint32_t baseAddr, uint32_t errType, uint32_t enable);

/**
 * \brief   This API is used to get ECC interrupt status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   errType         Interrupt status to read.
 *                          Refer enum #MCAN_ECCErrType.
 *
 * \return  None.
 */
uint32_t MCAN_eccGetIntrStatus(uint32_t baseAddr, uint32_t errType);

/**
 * \brief   This API is used to clear ECC interrupt status.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   errType         Interrupt status to clear.
 *                          Refer enum #MCAN_ECCErrType.
 *
 * \return  None.
 */
void MCAN_eccClearIntrStatus(uint32_t baseAddr, uint32_t errType);

/**
 * \brief   This API will configure external timestamp counter for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   prescalar       Timestamp Counter Prescaler. Range:[0x0-0xFFFFFF]
 *
 * \return  None.
 *
 * \note    Actual value programmed prescalar values is (prescalar - 1).
 */
void MCAN_extTSCounterConfig(uint32_t baseAddr,
                             uint32_t prescalar);

/**
 * \brief   This API will enable/disable fast external time stamp counter for
 *          MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   enable          External TS is enabled if it is 1.
 *                          External TS is disabled  if it is 0.
 *
 * \return  None.
 */
void MCAN_extTSCounterEnable(uint32_t baseAddr, uint32_t enable);

/**
 * \brief   This API will enable/disable External TimeStamp Counter
 *          Overflow Interrupt for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   enable          External TimeStamp Counter Overflow Interrupt is
 *                          enabled if it is TRUE.
 *                          External TimeStamp Counter Overflow Interrupt is
 *                          disabled  if it is FALSE.
 *
 * \return  None.
 */
void MCAN_extTSEnableIntr(uint32_t baseAddr, uint32_t enable);

/**
 * \brief   This API is used to write End of Interrupt for External TimeStamp
 *          Counter Overflow Interrupt.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  None.
 */
void MCAN_extTSWriteEOI(uint32_t baseAddr);

/**
 * \brief   This API returns Number of unserviced rollover/overflow
 *          interrupts for external TimeStamp counter.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Returns Number of unserviced rollover/overflow
 *                          interrupts for external TimeStamp counter.
 *                          Maximum number of unserviced interrupts is 0xF.
 */
uint32_t MCAN_extTSGetUnservicedIntrCount(uint32_t baseAddr);

/* ========================================================================== */
/*                          Advance Functions                                 */
/* ========================================================================== */

/**
 * \brief   This API is used get the MCAN revision ID.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   revId           Contains Revision ID of MCAN module.
 *                          Refer struct #MCAN_RevisionId.
 *
 * \return  None.
 */
void MCAN_getRevisionId(uint32_t baseAddr, MCAN_RevisionId *revId);

/**
 * \brief   This API get clock stop acknowledgement for MCAN module.
 *          It return whether MCAN is power down mode or not.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Return Clock Stop Acknowledgement status.
 *                          Return '1' if M_CAN is set in power down mode else
 *                          returns '0'.
 */
uint32_t MCAN_getClockStopAck(uint32_t baseAddr);

/**
 * \brief   This API will set External TimeStamp Counter Overflow Interrupt
 *          Raw status for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  None.
 */
void MCAN_extTSSetRawStatus(uint32_t baseAddr);

/**
 * \brief   This API will clear External TimeStamp Counter Overflow Interrupt
 *          raw status for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  None.
 */
void MCAN_extTSClearRawStatus(uint32_t baseAddr);

/**
 * \brief   This API will return Rx pin state of MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  state           MCAN Rx Pin State.
 *                          0= The CAN bus is dominant
 *                          1= The CAN bus is recessive
 */
uint32_t MCAN_getRxPinState(uint32_t baseAddr);

/**
 * \brief   This API will set Tx pin state of MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   state           MCAN Tx Pin State.
 *                          00= Reset value
 *                          01= Sample Point can be monitored at tx pin
 *                          10= The CAN bus is dominant
 *                          11= The CAN bus is recessive
 *                          other= It will treated as 11.
 *
 * \return  None.
 */
void MCAN_setTxPinState(uint32_t baseAddr, uint32_t state);

/**
 * \brief   This API will return Tx pin state of MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  state           MCAN Tx Pin State.
 *                          00= Reset value
 *                          01= Sample Point can be monitored at tx pin
 *                          10= The CAN bus is dominant
 *                          11= The CAN bus is recessive
 */
uint32_t MCAN_getTxPinState(uint32_t baseAddr);

/**
 * \brief   This API will return current timestamp counter value.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  val             Current Timestamp counter value.
 */
uint32_t MCAN_getTSCounterVal(uint32_t baseAddr);

/**
 * \brief   This API will return clock stop acknowledgement
 *          for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  ack             Clock Stop Acknowledge
 *                          0= No clock stop acknowledged
 *                          1= M_CAN may be set in power down
 */
uint32_t MCAN_getClkStopAck(uint32_t baseAddr);

/**
 * \brief   This API will get the configured bit timings for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   configParams    Configuration parameters for MCAN bit timing.
 *                          Refer struct #MCAN_BitTimingParams.
 *
 * \return  None.
 */
void MCAN_getBitTime(uint32_t              baseAddr,
                     MCAN_BitTimingParams *configParams);

/**
 * \brief   This API will reset timestamp counter value.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  None.
 */
void MCAN_resetTSCounter(uint32_t baseAddr);

/**
 * \brief   This API will return current time-out counter value.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  val             Current Time-out counter value.
 */
uint32_t MCAN_getTOCounterVal(uint32_t baseAddr);

/**
 * \brief   This API is used get the ECC AGGR revision ID.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   revId           Contains Revision ID of ECC AGGR.
 *                          Refer struct #MCAN_ECCAggrRevisionId.
 *
 * \return  None.
 */
void MCAN_eccAggrGetRevisionId(uint32_t                baseAddr,
                               MCAN_ECCAggrRevisionId *revId);

/**
 * \brief   This API is used get the ECC Wrapper revision ID.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 * \param   revId           Contains Revision ID of ECC Wrapper
 *                          Refer struct #MCAN_ECCWrapRevisionId.
 *
 * \return  None.
 */
void MCAN_eccWrapGetRevisionId(uint32_t                baseAddr,
                               MCAN_ECCWrapRevisionId *revId);

/**
 * \brief   This API returns External TimeStamp Counter Overflow Interrupt
 *          enable status for MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  status          Returns TRUE if External TimeStamp Counter Overflow
 *                          Interrupt is enabled.
 *                          Else returns FALSE.
 */
uint32_t MCAN_extTSIsIntrEnable(uint32_t baseAddr);

/**
 * \brief   This function return endianness value of MCAN module.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \retval  val             Endianness value. (0x87654321)
 */
uint32_t MCAN_getEndianVal(uint32_t baseAddr);

/**
 * \brief   This API will get the configured Extended ID AND Mask.
 *
 * \param   baseAddr        Base Address of the MCAN Registers.
 *
 * \return  idMask          Extended ID AND Mask.
 */
uint32_t MCAN_getExtIDANDMassk(uint32_t baseAddr);

// Close the Doxygen group.
//! @}


//###########################################################################
//
// FILE:   memcfg.h
//
// TITLE:  C28x RAM config driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup memcfg_api MemCfg
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_memcfg.h
//
// TITLE:   Definitions for the MEMCFG registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the MEMCFG register offsets
//
//*************************************************************************************************

                                                            // Register
                                                            // Register
                                                            // Clear Register
                                                            // Interrupt Enable Register
                                                            // Address
                                                            // Violation Address
                                                            // Violation Address
                                                            // Violation Address
                                                            // Violation Address
                                                            // Violation Address
                                                            // Violation Address
                                                            // Address
                                                            // Register
                                                            // Register
                                                            // Register
                                                            // Enable Register
                                                            // Address
                                                            // Address
                                                            // Address
                                                            // Access Violation Address
                                                            // Address
                                                            // Violation Address




//*************************************************************************************************
//
// The following are defines for the bit fields in the DxLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DxCOMMIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DxACCPROT0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DxTEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DxINIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DxINITDONE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the DxRAMTEST_LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxCOMMIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxMSEL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxCLAPGM register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxACCPROT0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxACCPROT1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxTEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxINIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxINITDONE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxRAMTEST_LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxCOMMIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxACCPROT0 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxTEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxINIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxINITDONE register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxRAMTEST_LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxLOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxCOMMIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxTEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxINIT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxINITDONE register
//
//*************************************************************************************************
                                                         // MSG RAM
                                                         // MSG RAM
                                                         // MSG RAM
                                                         // MSG RAM

//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxRAMTEST_LOCK register
//
//*************************************************************************************************
                                                          // Configuration
                                                          // Configuration
                                                          // Configuration
                                                          // Configuration

//*************************************************************************************************
//
// The following are defines for the bit fields in the ROM_LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ROM_TEST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the ROM_FORCE_ERROR register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVINTEN register
//
//*************************************************************************************************
                                               // Enable
                                               // Enable
                                               // Enable
                                               // Enable
                                               // Enable
                                               // Enable
                                               // Enable
                                               // Enable
                                               // Enable
                                               // Enable

//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVINTEN register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRTHRES register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTSET register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTEN register
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the CPU_RAM_TEST_ERROR_STS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the CPU_RAM_TEST_ERROR_STS_CLR register
//
//*************************************************************************************************




//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************
//
// Masks to decode memory section defines.
//

//
// Used for access violation functions.
//

//
// Key for writing to memory test config lock registers
//

//*****************************************************************************
//
// Values that can be passed to MemCfg_lockConfig(), MemCfg_unlockConfig(),
// MemCfg_commitConfig(), MemCfg_setProtection(), MemCfg_initSections(),
// MemCfg_setCLAMemType(), MemCfg_setLSRAMMasterSel(), MemCfg_getInitStatus()
// as the memSection(s) or ramSection(s) parameter.
//
//*****************************************************************************
//
// DxRAM - Dedicated RAM config
//

//
// LSxRAM - Local shared RAM config
//

//
// GSxRAM - Global shared RAM config
//

//
// MSGxRAM - Message RAM config
//

//
// ROM memory sections
//

//
// All sections
//

//*****************************************************************************
//
// Values that can be passed to MemCfg_setProtection() as the protectMode
// parameter.
//
//*****************************************************************************




//*****************************************************************************
//
// Values that can be passed to MemCfg_enableViolationInterrupt()
// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(),
// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as
// the intFlags parameter. They also make up the return value of
// MemCfg_getViolationInterruptStatus().
//
//*****************************************************************************


//*****************************************************************************
//
// Values that can be passed to MemCfg_forceCorrErrorStatus(),
// MemCfg_clearCorrErrorStatus(), and MemCfg_getCorrErrorAddress() as the
// stsFlag(s) parameter and returned by MemCfg_getCorrErrorStatus().
//
// Note that MEMCFG_CERR_CPUREAD is the only value below that has a
// corresponding interrupt and may be used with the error functions that take
// an intFlag(s) parameter.
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to MemCfg_forceUncorrErrorStatus(),
// MemCfg_clearUncorrErrorStatus(), and MemCfg_getUncorrErrorAddress() as the
// stsFlag(s) parameter and returned by MemCfg_getUncorrErrorStatus().
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to MemCfg_clearDiagErrorStatus() as stsFlags
// parameter and returned by MemCfg_getDiagErrorStatus().
//
//*****************************************************************************


//*****************************************************************************
//
//! Values that can be passed to MemCfg_setCLAMemType() as the \e claMemType
//! parameter.
//
//*****************************************************************************
typedef enum
{
    MEMCFG_CLA_MEM_DATA,                //!< Section is CLA data memory
    MEMCFG_CLA_MEM_PROGRAM              //!< Section is CLA program memory
} MemCfg_CLAMemoryType;

//*****************************************************************************
//
//! Values that can be passed to MemCfg_setLSRAMMasterSel() as the \e masterSel
//! parameter.
//
//*****************************************************************************
typedef enum
{
    MEMCFG_LSRAMMASTER_CPU_ONLY,        //!< CPU is the master of the section
    MEMCFG_LSRAMMASTER_CPU_CLA1         //!< CPU and CLA1 share this section
} MemCfg_LSRAMMasterSel;

//*****************************************************************************
//
//! Values that can be passed to MemCfg_setTestMode() as the \e testMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Functional mode
    MEMCFG_TEST_FUNCTIONAL   = 0,
    //! Writes allowed to data only
    MEMCFG_TEST_WRITE_DATA   = 1,
    //! Writes allowed to ECC only (for DxRAM/MxRAM)
    MEMCFG_TEST_WRITE_ECC    = 2,
    //! Writes allowed to parity only (for LSxRAM, GSxRAM, and MSGxRAM)
    MEMCFG_TEST_WRITE_PARITY = 2,
    //! Diagnostic mode, similar to functional mode but NMI is not generated.
    MEMCFG_TEST_FUNC_DIAG    = 3
} MemCfg_TestMode;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets the CLA memory type of the specified RAM section.
//!
//! \param ramSections is the logical OR of the sections to be configured.
//! \param claMemType indicates data memory or program memory.
//!
//! This function sets the CLA memory type configuration of the RAM section. If
//! the \e claMemType parameter is \b MEMCFG_CLA_MEM_DATA, the RAM section will
//! be configured as CLA data memory. If \b MEMCFG_CLA_MEM_PROGRAM, the RAM
//! section will be configured as CLA program memory.
//!
//! The \e ramSections parameter is an OR of the following indicators:
//! \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx.
//!
//! \note This API only applies to LSx RAM and has no effect if the CLA isn't
//! master of the memory section.
//!
//! \sa MemCfg_setLSRAMMasterSel()
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_setCLAMemType(uint32_t ramSections, MemCfg_CLAMemoryType claMemType)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the CLA memory configuration to the appropriate register. Either
    // set or clear the bit that determines the function of the RAM section as
    // it relates to the CLA.
    //
    __eallow();

    if(claMemType == MEMCFG_CLA_MEM_PROGRAM)
    {
        //
        // Program memory
        //
        (*((volatile uint32_t *)((uintptr_t)(0x0005F400U + 0x26U)))) |= ramSections;
    }
    else
    {
        //
        // Data memory
        //
        (*((volatile uint32_t *)((uintptr_t)(0x0005F400U + 0x26U)))) &= ~ramSections;
    }

    __edis();
}

//*****************************************************************************
//
//! Enables individual RAM access violation interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//! Can be a logical OR any of the following values:
//!  - \b MEMCFG_NMVIOL_CPUREAD   - Non-master CPU read access
//!  - \b MEMCFG_NMVIOL_CPUWRITE  - Non-master CPU write access
//!  - \b MEMCFG_NMVIOL_CPUFETCH  - Non-master CPU fetch access
//!  - \b MEMCFG_NMVIOL_DMAWRITE  - Non-master DMA write access
//!  - \b MEMCFG_NMVIOL_CLA1READ  - Non-master CLA1 read access
//!  - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access
//!  - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access
//!  - \b MEMCFG_NMVIOL_DMAREAD   - Non Master DMA read access
//!  - \b MEMCFG_NMVIOL_HICREAD   - Non-master HIC read access
//!  - \b MEMCFG_NMVIOL_HICWRITE  - Non-master HIC write access
//!  - \b MEMCFG_MVIOL_CPUFETCH   - Master CPU fetch access
//!  - \b MEMCFG_MVIOL_CPUWRITE   - Master CPU write access
//!  - \b MEMCFG_MVIOL_DMAWRITE   - Master DMA write access
//!  - \b MEMCFG_MVIOL_HICWRITE   - Master HIC write access
//! This function enables the indicated RAM access violation interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_enableViolationInterrupt(uint32_t intFlags)
{
    //
    // Enable the specified interrupts.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x6U)))) |=
        intFlags & 0x0000FFFFU;

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x26U)))) |=
        (intFlags & 0x000F0000U) >> 16U;

    __edis();
}

//*****************************************************************************
//
//! Disables individual RAM access violation interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be disabled.
//! Can be a logical OR any of the following values:
//!  - \b MEMCFG_NMVIOL_CPUREAD   - Non-master CPU read access
//!  - \b MEMCFG_NMVIOL_CPUWRITE  - Non-master CPU write access
//!  - \b MEMCFG_NMVIOL_CPUFETCH  - Non-master CPU fetch access
//!  - \b MEMCFG_NMVIOL_DMAWRITE  - Non-master DMA write access
//!  - \b MEMCFG_NMVIOL_CLA1READ  - Non-master CLA1 read access
//!  - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access
//!  - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access
//!  - \b MEMCFG_NMVIOL_DMAREAD   - Non Master DMA read access
//!  - \b MEMCFG_NMVIOL_HICREAD   - Non-master HIC read access
//!  - \b MEMCFG_NMVIOL_HICWRITE  - Non-master HIC write access
//!  - \b MEMCFG_MVIOL_CPUFETCH   - Master CPU fetch access
//!  - \b MEMCFG_MVIOL_CPUWRITE   - Master CPU write access
//!  - \b MEMCFG_MVIOL_DMAWRITE   - Master DMA write access
//!  - \b MEMCFG_MVIOL_HICWRITE   - Master HIC write access
//!
//! This function disables the indicated RAM access violation interrupt
//! sources. Only the sources that are enabled can be reflected to the
//! processor interrupt; disabled sources have no effect on the processor.
//!
//! \note Note that only non-master violations may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_disableViolationInterrupt(uint32_t intFlags)
{
    //
    // Disable the specified interrupts.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x6U)))) &=
        ~(intFlags & 0x0000FFFFU);

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x26U)))) &=
        ~((intFlags & 0x000F0000U) >> 16U);

    __edis();
}

//*****************************************************************************
//
//! Gets the current RAM access violation status.
//!
//! This function returns the RAM access violation status. This function will
//! return flags for both master and non-master access violations although only
//! the non-master flags have the ability to cause the generation of an
//! interrupt.
//!
//! \return Returns the current violation status, enumerated as a bit field of
//! the values:
//!  - \b MEMCFG_NMVIOL_CPUREAD   - Non-master CPU read access
//!  - \b MEMCFG_NMVIOL_CPUWRITE  - Non-master CPU write access
//!  - \b MEMCFG_NMVIOL_CPUFETCH  - Non-master CPU fetch access
//!  - \b MEMCFG_NMVIOL_DMAWRITE  - Non-master DMA write access
//!  - \b MEMCFG_NMVIOL_CLA1READ  - Non-master CLA1 read access
//!  - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access
//!  - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access
//!  - \b MEMCFG_NMVIOL_DMAREAD   - Non Master DMA read access
//!  - \b MEMCFG_NMVIOL_HICREAD   - Non-master HIC read access
//!  - \b MEMCFG_NMVIOL_HICWRITE  - Non-master HIC write access
//!  - \b MEMCFG_MVIOL_CPUFETCH   - Master CPU fetch access
//!  - \b MEMCFG_MVIOL_CPUWRITE   - Master CPU write access
//!  - \b MEMCFG_MVIOL_DMAWRITE   - Master DMA write access
//!  - \b MEMCFG_MVIOL_HICWRITE   - Master HIC write access
//*****************************************************************************
static inline uint32_t
MemCfg_getViolationInterruptStatus(void)
{
    uint32_t status;

    //
    // Read and return RAM access status flags.
    //
    status = ((*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x0U))))) |
             ((*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x20U)))) <<
              16U);

    return(status);
}

//*****************************************************************************
//
//! Sets the RAM access violation status.
//!
//! \param intFlags is a bit mask of the access violation flags to be set.
//! Can be a logical OR any of the following values:
//!  - \b MEMCFG_NMVIOL_CPUREAD   - Non-master CPU read access
//!  - \b MEMCFG_NMVIOL_CPUWRITE  - Non-master CPU write access
//!  - \b MEMCFG_NMVIOL_CPUFETCH  - Non-master CPU fetch access
//!  - \b MEMCFG_NMVIOL_DMAWRITE  - Non-master DMA write access
//!  - \b MEMCFG_NMVIOL_CLA1READ  - Non-master CLA1 read access
//!  - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access
//!  - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access
//!  - \b MEMCFG_NMVIOL_DMAREAD   - Non Master DMA read access
//!  - \b MEMCFG_NMVIOL_HICREAD   - Non-master HIC read access
//!  - \b MEMCFG_NMVIOL_HICWRITE  - Non-master HIC write access
//!  - \b MEMCFG_MVIOL_CPUFETCH   - Master CPU fetch access
//!  - \b MEMCFG_MVIOL_CPUWRITE   - Master CPU write access
//!  - \b MEMCFG_MVIOL_DMAWRITE   - Master DMA write access
//!  - \b MEMCFG_MVIOL_HICWRITE   - Master HIC write access
//!
//! This function sets the RAM access violation status. This function will
//! set flags for both master and non-master access violations, and an
//! interrupt will be generated if it is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceViolationInterrupt(uint32_t intFlags)
{
    //
    // Shift and mask the flags appropriately and write them to the
    // corresponding SET register.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x2U)))) =
        intFlags & 0x0000FFFFU;

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x22U)))) =
        (intFlags & 0x000F0000U) >> 16U;

    __edis();
}

//*****************************************************************************
//
//! Clears RAM access violation flags.
//!
//! \param intFlags is a bit mask of the access violation flags to be cleared.
//! Can be a logical OR any of the following values:
//!  - \b MEMCFG_NMVIOL_CPUREAD   - Non-master CPU read access
//!  - \b MEMCFG_NMVIOL_CPUWRITE  - Non-master CPU write access
//!  - \b MEMCFG_NMVIOL_CPUFETCH  - Non-master CPU fetch access
//!  - \b MEMCFG_NMVIOL_DMAWRITE  - Non-master DMA write access
//!  - \b MEMCFG_NMVIOL_CLA1READ  - Non-master CLA1 read access
//!  - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access
//!  - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access
//!  - \b MEMCFG_NMVIOL_DMAREAD   - Non Master DMA read access
//!  - \b MEMCFG_NMVIOL_HICREAD   - Non-master HIC read access
//!  - \b MEMCFG_NMVIOL_HICWRITE  - Non-master HIC write access
//!  - \b MEMCFG_MVIOL_CPUFETCH   - Master CPU fetch access
//!  - \b MEMCFG_MVIOL_CPUWRITE   - Master CPU write access
//!  - \b MEMCFG_MVIOL_DMAWRITE   - Master DMA write access
//!  - \b MEMCFG_MVIOL_HICWRITE   - Master HIC write access
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearViolationInterruptStatus(uint32_t intFlags)
{
    //
    // Clear the requested access violation flags.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x4U)))) |=
        intFlags & 0x0000FFFFU;

    (*((volatile uint32_t *)((uintptr_t)(0x0005F500U + 0x24U)))) |=
        (intFlags & 0x000F0000U) >> 16U;

    __edis();
}

//*****************************************************************************
//
//! Sets the correctable error threshold value.
//!
//! \param threshold is the correctable error threshold.
//!
//! This value sets the error-count threshold at which a correctable error
//! interrupt is generated. That is when the error count register reaches the
//! value specified by the \e threshold parameter, an interrupt is
//! generated if it is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_setCorrErrorThreshold(uint32_t threshold)
{
    //
    // Write the threshold value to the appropriate register.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x30U)))) = threshold;

    __edis();
}

//*****************************************************************************
//
//! Gets the correctable error count.
//!
//! \return Returns the number of correctable error have occurred.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getCorrErrorCount(void)
{
    //
    // Read and return the number of errors that have occurred.
    //
    return((*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x2EU)))));
}

//*****************************************************************************
//
//! Enables individual RAM correctable error interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be enabled. Can
//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function enables the indicated RAM correctable error interrupt
//! sources. Only the sources that are enabled can be reflected to the
//! processor interrupt; disabled sources have no effect on the processor.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_enableCorrErrorInterrupt(uint32_t intFlags)
{
    //
    // Enable the specified interrupts.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x38U)))) |= intFlags;

    __edis();
}

//*****************************************************************************
//
//! Disables individual RAM correctable error interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be disabled. Can
//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function disables the indicated RAM correctable error interrupt
//! sources. Only the sources that are enabled can be reflected to the
//! processor interrupt; disabled sources have no effect on the processor.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_disableCorrErrorInterrupt(uint32_t intFlags)
{
    //
    // Disable the specified interrupts.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x38U)))) &= ~(intFlags);

    __edis();
}

//*****************************************************************************
//
//! Gets the current RAM correctable error interrupt status.
//!
//! \return Returns the current error interrupt status. Will return a value of
//! \b MEMCFG_CERR_CPUREAD if an interrupt has been generated. If not, the
//! function will return 0.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getCorrErrorInterruptStatus(void)
{
    //
    // Read and return correctable error interrupt flags.
    //
    return((*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x32U)))));
}

//*****************************************************************************
//
//! Sets the RAM correctable error interrupt status.
//!
//! \param intFlags is a bit mask of the interrupt sources to be set. Can take
//! the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function sets the correctable error interrupt flag.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceCorrErrorInterrupt(uint32_t intFlags)
{
    //
    // Write the flags to the appropriate SET register.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x36U)))) = intFlags;

    __edis();
}

//*****************************************************************************
//
//! Clears the RAM correctable error interrupt status.
//!
//! \param intFlags is a bit mask of the interrupt sources to be cleared. Can
//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function clears the correctable error interrupt flag.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearCorrErrorInterruptStatus(uint32_t intFlags)
{
    //
    // Clear the requested flags.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x34U)))) |= intFlags;

    __edis();
}

//*****************************************************************************
//
//! Gets the current correctable RAM error status.
//!
//! \return Returns the current error status, enumerated as a bit field of
//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ
//
//*****************************************************************************
static inline uint32_t
MemCfg_getCorrErrorStatus(void)
{
    //
    // Read and return RAM error status flags.
    //
    return((*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x20U)))));
}

//*****************************************************************************
//
//! Gets the current uncorrectable RAM error status.
//!
//! \return Returns the current error status, enumerated as a bit field of
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ
//! or \b MEMCFG_UCERR_HICREAD.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getUncorrErrorStatus(void)
{
    //
    // Read and return RAM error status flags.
    //
    return((*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x0U)))));
}

//*****************************************************************************
//
//! Sets the specified correctable RAM error status flag.
//!
//! \param stsFlags is a bit mask of the error sources. This parameter can be
//! any of the following values:
//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ
//!
//! This function sets the specified correctable RAM error status flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceCorrErrorStatus(uint32_t stsFlags)
{
    //
    // Write the flags to the appropriate SET register.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x22U)))) = stsFlags;

    __edis();
}

//*****************************************************************************
//
//! Sets the specified uncorrectable RAM error status flag.
//!
//! \param stsFlags is a bit mask of the error sources. This parameter can be
//! any of the following values:
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ
//! or \b MEMCFG_UCERR_HICREAD.
//!
//! This function sets the specified uncorrectable RAM error status flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceUncorrErrorStatus(uint32_t stsFlags)
{
    //
    // Write the flags to the appropriate SET register.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x2U)))) = stsFlags;

    __edis();
}

//*****************************************************************************
//
//! Clears correctable RAM error flags.
//!
//! \param stsFlags is a bit mask of the status flags to be cleared.
//! This parameter can be any of the following :
//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ
//!
//! This function clears the specified correctable RAM error flags.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearCorrErrorStatus(uint32_t stsFlags)
{
    //
    // Clear the requested flags.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x24U)))) |= stsFlags;

    __edis();
}

//*****************************************************************************
//
//! Clears uncorrectable RAM error flags.
//!
//! \param stsFlags is a bit mask of the status flags to be cleared.
//! This parameter can be any of the following :
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ
//! or \b MEMCFG_UCERR_HICREAD.
//!
//! This function clears the specified uncorrectable RAM error flags.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearUncorrErrorStatus(uint32_t stsFlags)
{
    //
    // Clear the requested flags.
    //
    __eallow();

    (*((volatile uint32_t *)((uintptr_t)(0x0005F540U + 0x4U)))) |= stsFlags;

    __edis();
}

//*****************************************************************************
//
//! Gets the diagnostics corr/uncorr memory error status in test mode.
//!
//! \return Returns the diagnostics error status in test mode. It can return
//! following values: \b MEMCFG_DIAGERR_UNCORR, and/or \b MEMCFG_DIAGERR_CORR.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getDiagErrorStatus(void)
{
    //
    // Returns diag error status.
    //
    return((*((volatile uint32_t *)((uintptr_t)(0x0005F590U + 0x0U)))));
}

//*****************************************************************************
//
//! Clears the diagnostics corr/uncorr memory error status.
//!
//! \param stsFlags is a bit mask of the status flags to be cleared.
//!
//! This function clears the specified diagnostics corr/uncorr RAM/ROM memory
//! error flags in test mode. The param \e stsFlags can be any of the following
//! values: \b MEMCFG_DIAGERR_UNCORR, and/or \b MEMCFG_DIAGERR_CORR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearDiagErrorStatus(uint32_t stsFlags)
{
    //
    // Clear diag error status.
    //
    (*((volatile uint32_t *)((uintptr_t)(0x0005F590U + 0x2U)))) |= stsFlags;
}

//*****************************************************************************
//
//! Gets address location of diagnostics corr/uncorr memory read/write error.
//!
//! \return Return address location of diagnostics corr/uncorr memory error
//! error in test mode.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getDiagErrorAddress(void)
{
    //
    // Return diag error address.
    //
    return((*((volatile uint32_t *)((uintptr_t)(0x0005F590U + 0x4U)))));
}
//*****************************************************************************
//
//! Locks the writes to the configuration of specified memory sections.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function locks writes to the access protection and master select
//! configuration of a memory section.That means calling MemCfg_setProtection()
//! or MemCfg_setLSRAMMasterSel() for a locked memory section will have no
//! effect until MemCfg_unlockConfig() is called.
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0 and \b MEMCFG_SECT_M1 or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCLA1TOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//!   \b MEMCFG_SECT_MSGX_ALL to configure all message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_lockConfig(uint32_t memSections);

//*****************************************************************************
//
//! Unlocks the writes to the configuration of a memory section.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function unlocks writes to the access protection and master select
//! configuration of a memory section that has been locked using
//! MemCfg_lockConfig().
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0 and \b MEMCFG_SECT_M1 or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCLA1TOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//!   \b MEMCFG_SECT_MSGX_ALL to configure all message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_unlockConfig(uint32_t memSections);

//*****************************************************************************
//
//! Permanently locks writes to the configuration of a memory section.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function permanently locks writes to the access protection and master
//! select configuration of a memory section. That means calling
//! MemCfg_setProtection() or MemCfg_setLSRAMMasterSel() for a locked memory
//! section will have no effect. To lock the configuration in a nonpermanent
//! way, use MemCfg_lockConfig().
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0 and \b MEMCFG_SECT_M1 or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCLA1TOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//!   \b MEMCFG_SECT_MSGX_ALL to configure all message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_commitConfig(uint32_t memSections);

//*****************************************************************************
//
//! Sets the access protection mode of a single memory section.
//!
//! \param memSection is the memory section to be configured.
//! \param protectMode is the logical OR of the settings to be applied.
//!
//! This function sets the access protection mode of a specified memory section.
//! The mode is passed into the \e protectMode parameter as the logical OR of
//! the following values:
//! - \b MEMCFG_PROT_ALLOWCPUFETCH or \b MEMCFG_PROT_BLOCKCPUFETCH - CPU fetch
//! - \b MEMCFG_PROT_ALLOWCPUWRITE or \b MEMCFG_PROT_BLOCKCPUWRITE - CPU write
//! - \b MEMCFG_PROT_ALLOWDMAWRITE or \b MEMCFG_PROT_BLOCKDMAWRITE - DMA write
//! - \b MEMCFG_PROT_ALLOWHICWRITE or \b MEMCFG_PROT_BLOCKHICWRITE - HIC write
//!
//! The \e memSection parameter is one of the following indicators:
//! - \b MEMCFG_SECT_M0 or \b MEMCFG_SECT_M1
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx
//!
//! This function will have no effect if the associated registers have been
//! locked by MemCfg_lockConfig() or MemCfg_commitConfig() or if the memory
//! is configured as CLA program memory.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_setProtection(uint32_t memSection, uint32_t protectMode);

//*****************************************************************************
//
//! Sets the master of the specified LSxRAM section.
//!
//! \param ramSection is the LSxRAM section to be configured.
//! \param masterSel is the sharing selection.
//!
//! This function sets the master select configuration of the LSxRAM section.If
//! the \e masterSel parameter is \b MEMCFG_LSRAMMASTER_CPU_ONLY, the LSxRAM
//! section passed into the \e ramSection parameter will be dedicated to the
//! CPU. If \b MEMCFG_LSRAMMASTER_CPU_CLA1, the memory section will be shared
//! between the CPU and the CLA.
//!
//! The \e ramSection parameter should be a value from \b MEMCFG_SECT_LS0
//! through \b MEMCFG_SECT_LSx.
//!
//! This function will have no effect if the associated registers have been
//! locked by MemCfg_lockConfig() or MemCfg_commitConfig().
//!
//! \note This API only applies to LSxRAM.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_setLSRAMMasterSel(uint32_t ramSection, MemCfg_LSRAMMasterSel masterSel);

//*****************************************************************************
//
//! Locks the writes to the test mode configuration of specified memory
//! sections.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function locks writes to the test mode configuration of a RAM section.
//! That means calling MemCfg_setTestMode() for a locked RAM section will have
//! no effect until MemCfg_unlockTestConfig() is called.
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or use \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or use
//!   \b MEMCFG_SECT_LSX_ALL to configure all possible LSRAM sections.
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or use
//!   \b MEMCFG_SECT_GSX_ALL to configure all possible GSRAM sections.
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//!   \b MEMCFG_SECT_MSGX_ALL to configure all possible message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_lockTestConfig(uint32_t memSections);

//*****************************************************************************
//
//! Unlocks the writes to the test mode configuration of specified memory
//! sections.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function unlocks writes to the test mode configuration of a RAM
//! section that has been locked using MemCfg_lockTestConfig().
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or use \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or use
//!   \b MEMCFG_SECT_LSX_ALL to configure all possible LSRAM sections.
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or use
//!   \b MEMCFG_SECT_GSX_ALL to configure all possible GSRAM sections.
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//!   \b MEMCFG_SECT_MSGX_ALL to configure all possible message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_unlockTestConfig(uint32_t memSections);

//*****************************************************************************
//
//! Sets the test mode of the specified memory section.
//!
//! \param memSection is the memory section to be configured.
//! \param testMode is the test mode selected.
//!
//! This function sets the test mode configuration of the RAM section. The
//! \e testMode parameter can take one of the following values:
//! - \b MEMCFG_TEST_FUNCTIONAL
//! - \b MEMCFG_TEST_WRITE_DATA
//! - \b MEMCFG_TEST_WRITE_ECC
//! - \b MEMCFG_TEST_WRITE_PARITY
//! - \b MEMCFG_TEST_FUNC_DIAG
//!
//! The \e memSection parameter is one of the following indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode);

//*****************************************************************************
//
//! Starts the initialization the specified RAM sections.
//!
//! \param ramSections is the logical OR of the sections to be initialized.
//!
//! This function starts the initialization of the specified RAM sections. Use
//! MemCfg_getInitStatus() to check if the initialization is done.
//!
//! The \e ramSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or
//!   \b MEMCFG_SECT_MSGX_ALL
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_initSections(uint32_t ramSections);

//*****************************************************************************
//
//! Get the status of initialized RAM sections.
//!
//! \param ramSections is the logical OR of the sections to be checked.
//!
//! This function gets the initialization status of the RAM sections specified
//! by the \e ramSections parameter.
//!
//! The \e ramSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//!   \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or
//!   \b MEMCFG_SECT_MSGX_ALL
//! - \b OR use \b MEMCFG_SECT_ALL to get status of all possible sections.
//!
//! \note Use MemCfg_initSections() to start the initialization.
//!
//! \return Returns \b true if all the sections specified by \e ramSections
//! have been initialized and \b false if not.
//
//*****************************************************************************
extern _Bool
MemCfg_getInitStatus(uint32_t ramSections);

//*****************************************************************************
//
//! Get the violation address associated with a intFlag.
//!
//! \param intFlag is the type of access violation as indicated by ONE of
//! these values:
//!  - \b MEMCFG_NMVIOL_CPUREAD   - Non-master CPU read access
//!  - \b MEMCFG_NMVIOL_CPUWRITE  - Non-master CPU write access
//!  - \b MEMCFG_NMVIOL_CPUFETCH  - Non-master CPU fetch access
//!  - \b MEMCFG_NMVIOL_DMAWRITE  - Non-master DMA write access
//!  - \b MEMCFG_NMVIOL_CLA1READ  - Non-master CLA1 read access
//!  - \b MEMCFG_NMVIOL_CLA1WRITE - Non-master CLA1 write access
//!  - \b MEMCFG_NMVIOL_CLA1FETCH - Non-master CLA1 fetch access
//!  - \b MEMCFG_NMVIOL_DMAREAD   - Non Master DMA read access
//!  - \b MEMCFG_NMVIOL_HICREAD   - Non-master HIC read access
//!  - \b MEMCFG_NMVIOL_HICWRITE  - Non-master HIC write access
//!  - \b MEMCFG_MVIOL_CPUFETCH   - Master CPU fetch access
//!  - \b MEMCFG_MVIOL_CPUWRITE   - Master CPU write access
//!  - \b MEMCFG_MVIOL_DMAWRITE   - Master DMA write access
//!  - \b MEMCFG_MVIOL_HICWRITE   - Master HIC write access
//!
//! \return Returns the violation address associated with the \e intFlag.
//
//*****************************************************************************
extern uint32_t
MemCfg_getViolationAddress(uint32_t intFlag);

//*****************************************************************************
//
//! Get the correctable error address associated with a stsFlag.
//!
//! \param stsFlag is the type of error to which the returned address will
//! correspond. It can take following values: \b MEMCFG_CERR_CPUREAD,
//! \b MEMCFG_CERR_CLA1READ, \b MEMCFG_CERR_DMAREAD.
//!
//! \return Returns the error address associated with the stsFlag.
//
//*****************************************************************************
extern uint32_t
MemCfg_getCorrErrorAddress(uint32_t stsFlag);

//*****************************************************************************
//
//! Get the uncorrectable error address associated with a stsFlag.
//!
//! \param stsFlag is the type of error to which the returned address will
//! correspond. It may be passed one of these values:
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, or
//! \b MEMCFG_UCERR_CLA1READ values
//!
//! \return Returns the error address associated with the stsFlag.
//
//*****************************************************************************
extern uint32_t
MemCfg_getUncorrErrorAddress(uint32_t stsFlag);

//*****************************************************************************
//
//! Forces parity error in the selected memory.
//!
//! \param memSections is the logical OR of the sections to be tested.
//!
//! This function forces the parity error in the memories specified
//! by the \e memSections parameter.
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_ROMBOOT, \b MEMCFG_SECT_ROMSECURE ,
//!   \b MEMCFG_SECT_ROMCLADATA, \b MEMCFG_SECT_ROM_ALL.
//! - \b OR use \b MEMCFG_SECT_ALL to force parity error in all possible
//!      memory sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_forceMemError(uint32_t memSections);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   pin_map.h
//
// TITLE:  Definitions of pin mux info for gpio.c.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
// 0x00000003 = MUX register value
// 0x0000000C = GMUX register value
// 0x0000FF00 = Shift amount within mux registers
// 0xFFFF0000 = Offset of MUX register
//*****************************************************************************























































































//###########################################################################
//
// FILE:   sci.h
//
// TITLE:  C28x SCI driver.
//
//###########################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup sci_api SCI
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_sci.h
//
// TITLE:   Definitions for the SCI registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the SCI register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIHBAUD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCILBAUD register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXST register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXEMU register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXBUF register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCITXBUF register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFTX register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFRX register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFCT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIPRI register
//
//*************************************************************************************************




//*****************************************************************************
//
// Values that can be passed to SCI_enableInterrupt, SCI_disableInterrupt, and
// SCI_clearInterruptStatus as the intFlags parameter, and returned from
// SCI_getInterruptStatus.
//
//*****************************************************************************

//*****************************************************************************
//
// Values that can be passed to SCI_setConfig as the config parameter
// and returned by SCI_getConfig in the config parameter.
// Additionally, the SCI_CONFIG_PAR_* enum subset can be passed to
// SCI_setParityMode as the parity parameter, and are returned by
// SCI_getParityMode.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be used with SCI_setParityMode() and SCI_getParityMode() to
//! describe the parity of the SCI communication.
//
//*****************************************************************************
typedef enum
{
    SCI_CONFIG_PAR_NONE = 0x0000U,  //!< No parity
    SCI_CONFIG_PAR_EVEN = 0x0060U,  //!< Even parity
    SCI_CONFIG_PAR_ODD  = 0x0020U   //!< Odd parity
} SCI_ParityType;

//*****************************************************************************
//
//! Values that can be passed to SCI_setFIFOInterruptLevel() as the txLevel
//! parameter and returned by SCI_getFIFOInteruptLevel() and
//! SCI_getTxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
    SCI_FIFO_TX0  = 0x0000U, //!< Transmit interrupt empty
    SCI_FIFO_TX1  = 0x0001U, //!< Transmit interrupt 1/16 full
    SCI_FIFO_TX2  = 0x0002U, //!< Transmit interrupt 2/16 full
    SCI_FIFO_TX3  = 0x0003U, //!< Transmit interrupt 3/16 full
    SCI_FIFO_TX4  = 0x0004U, //!< Transmit interrupt 4/16 full
    SCI_FIFO_TX5  = 0x0005U, //!< Transmit interrupt 5/16 full
    SCI_FIFO_TX6  = 0x0006U, //!< Transmit interrupt 6/16 full
    SCI_FIFO_TX7  = 0x0007U, //!< Transmit interrupt 7/16 full
    SCI_FIFO_TX8  = 0x0008U, //!< Transmit interrupt 8/16 full
    SCI_FIFO_TX9  = 0x0009U, //!< Transmit interrupt 9/16 full
    SCI_FIFO_TX10 = 0x000AU, //!< Transmit interrupt 10/16 full
    SCI_FIFO_TX11 = 0x000BU, //!< Transmit interrupt 11/16 full
    SCI_FIFO_TX12 = 0x000CU, //!< Transmit interrupt 12/16 full
    SCI_FIFO_TX13 = 0x000DU, //!< Transmit interrupt 13/16 full
    SCI_FIFO_TX14 = 0x000EU, //!< Transmit interrupt 14/16 full
    SCI_FIFO_TX15 = 0x000FU, //!< Transmit interrupt 15/16 full
    SCI_FIFO_TX16 = 0x0010U  //!< Transmit interrupt full
} SCI_TxFIFOLevel;

//*****************************************************************************
//
//! Values that can be passed to SCI_setFIFOInterruptLevel() as the rxLevel
//! parameter and returned by SCI_getFIFOInterruptLevel() and
//! SCI_getRxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
    SCI_FIFO_RX0  = 0x0000U, //!< Receive interrupt empty
    SCI_FIFO_RX1  = 0x0001U, //!< Receive interrupt 1/16 full
    SCI_FIFO_RX2  = 0x0002U, //!< Receive interrupt 2/16 full
    SCI_FIFO_RX3  = 0x0003U, //!< Receive interrupt 3/16 full
    SCI_FIFO_RX4  = 0x0004U, //!< Receive interrupt 4/16 full
    SCI_FIFO_RX5  = 0x0005U, //!< Receive interrupt 5/16 full
    SCI_FIFO_RX6  = 0x0006U, //!< Receive interrupt 6/16 full
    SCI_FIFO_RX7  = 0x0007U, //!< Receive interrupt 7/16 full
    SCI_FIFO_RX8  = 0x0008U, //!< Receive interrupt 8/16 full
    SCI_FIFO_RX9  = 0x0009U, //!< Receive interrupt 9/16 full
    SCI_FIFO_RX10 = 0x000AU, //!< Receive interrupt 10/16 full
    SCI_FIFO_RX11 = 0x000BU, //!< Receive interrupt 11/16 full
    SCI_FIFO_RX12 = 0x000CU, //!< Receive interrupt 12/16 full
    SCI_FIFO_RX13 = 0x000DU, //!< Receive interrupt 13/16 full
    SCI_FIFO_RX14 = 0x000EU, //!< Receive interrupt 14/16 full
    SCI_FIFO_RX15 = 0x000FU, //!< Receive interrupt 15/16 full
    SCI_FIFO_RX16 = 0x0010U  //!< Receive interrupt full
} SCI_RxFIFOLevel;

//*****************************************************************************
//
// Values returned from SCI_getRxStatus().  These correspond to the different
// bits and flags of the SCIRXST register.
//
//*****************************************************************************

//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a SCI base address.
//!
//! \param base is the base address of the SCI port.
//!
//! This function determines if a SCI port base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Sets the type of parity.
//!
//! \param base is the base address of the SCI port.
//! \param parity specifies the type of parity to use.
//!
//! Sets the type of parity to use for transmitting and expect when receiving.
//! The \e parity parameter must be one of the following:
//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setParityMode(uint32_t base, SCI_ParityType parity)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the parity mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = (((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &
                                 ~(0x0060U)) | (uint16_t)parity);
}

//*****************************************************************************
//
//! Gets the type of parity currently being used.
//!
//! \param base is the base address of the SCI port.
//!
//! This function gets the type of parity used for transmitting data and
//! expected when receiving data.
//!
//! \return Returns the current parity settings, specified as one of the
//! following:
//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD.
//
//*****************************************************************************
static inline SCI_ParityType
SCI_getParityMode(uint32_t base)
{
    uint16_t parity;

    //
    // Check the arguments.
    //
    ;

    //
    // Return the current parity setting.
    //
    parity = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & (0x0060U));

    return((SCI_ParityType)parity);
}

//*****************************************************************************
//
//! Sets the multiprocessor protocol to address-bit mode.
//!
//! \param base is the base address of the SCI port.
//!
//! This function sets the multi-processor protocol to address-bit mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setAddrMultiProcessorMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the address-bit mode protocol
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x8U;
}

//*****************************************************************************
//
//! Sets the multiprocessor protocol to idle-line mode.
//!
//! \param base is the base address of the SCI port.
//!
//! This function sets the multi-processor protocol to idle-line protocol.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setIdleMultiProcessorMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the address-bit mode protocol
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x8U;
}

//*****************************************************************************
//
//! Locks Autobaud.
//!
//! \param base is the base address of the SCI port.
//!
//! This function performs an autobaud lock for the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_lockAutobaud(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Prime the baud register
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) = 0x0U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))) = 0x1U;

    //
    // Prepare for autobaud detection.
    // Set the CDC bit to enable autobaud detection and clear the ABD bit.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) |= 0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) |= 0x4000U;

    //
    // Wait until we correctly read an 'A' or 'a' and lock
    //
    while(((*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) & 0x8000U) != 0x8000U)
    {
    }

    //
    // After autobaud lock, clear the ABD and CDC bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) |= 0x4000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) &= ~0x2000U;
}

//*****************************************************************************
//
//! Sets the FIFO interrupt level at which interrupts are generated.
//!
//! \param base is the base address of the SCI port.
//! \param txLevel is the transmit FIFO interrupt level, specified as one of
//! the following:
//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, . . . or
//! \b SCI_FIFO_TX15.
//! \param rxLevel is the receive FIFO interrupt level, specified as one of
//! the following
//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX15.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel,
                          SCI_RxFIFOLevel rxLevel)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the FIFO interrupt levels.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &
                                 (~0x1FU)) | (uint16_t)txLevel;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &
                                 (~0x1FU)) | (uint16_t)rxLevel;
}

//*****************************************************************************
//
//! Gets the FIFO interrupt level at which interrupts are generated.
//!
//! \param base is the base address of the SCI port.
//! \param txLevel is a pointer to storage for the transmit FIFO interrupt
//! level, returned as one of the following:
//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, ... or \b SCI_FIFO_TX15.
//! \param rxLevel is a pointer to storage for the receive FIFO interrupt
//! level, returned as one of the following:
//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX15.
//!
//! This function gets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_getFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel *txLevel,
                          SCI_RxFIFOLevel *rxLevel)
{

    //
    // Check the arguments.
    //
    ;

    //
    // Extract the transmit and receive FIFO levels.
    //
    *txLevel = (SCI_TxFIFOLevel)((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &
                                 0x1FU);
    *rxLevel = (SCI_RxFIFOLevel)((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &
                                 0x1FU);
}

//*****************************************************************************
//
//! Gets the current configuration of a SCI.
//!
//! \param base is the base address of the SCI port.
//! \param lspclkHz is the rate of the clock supplied to the SCI module.  This
//! is the LSPCLK.
//! \param baud is a pointer to storage for the baud rate.
//! \param config is a pointer to storage for the data format.
//!
//! The baud rate and data format for the SCI is determined, given an
//! explicitly provided peripheral clock (hence the ExpClk suffix).  The
//! returned baud rate is the actual baud rate; it may not be the exact baud
//! rate requested or an ``official'' baud rate.  The data format returned in
//! \e config is enumerated the same as the \e config parameter of
//! SCI_setConfig().
//!
//! The peripheral clock is the low speed peripheral clock.  This will be
//! the value returned by SysCtl_getLowSeedClock(), or it can be explicitly
//! hard coded if it is constant and known (to save the code/execution overhead
//! of a call to SysCtl_getLowSpeedClock()).
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_getConfig(uint32_t base, uint32_t lspclkHz, uint32_t *baud,
              uint32_t *config)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Compute the baud rate.
    //
    *baud = lspclkHz /
            ((1U + (uint32_t)((uint32_t)((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) << 8U) |
               (*((volatile uint16_t *)((uintptr_t)(base + 0x3U)))))) * 8U);

    //
    // Get the parity, data length, and number of stop bits.
    //
    *config = (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & (0x0060U |
                                          0x0080U |
                                          0x0007U);
}

//*****************************************************************************
//
//! Enables transmitting and receiving.
//!
//! \param base is the base address of the SCI port.
//!
//! Enables SCI by taking SCI out of the software reset. Sets the TXENA, and
//! RXENA bits which enables transmit and receive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable RX, TX, and the SCI.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= (0x2U | 0x1U |
                                  0x20U);
}

//*****************************************************************************
//
//! Disables transmitting and receiving.
//!
//! \param base is the base address of the SCI port.
//!
//! Clears the SCIEN, TXE, and RXE bits. The user should ensure that all the
//! data has been sent before disable the module during transmission.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~(0x4000U);

    //
    // Disable the SCI.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &= ~(0x2U | 0x1U);
}

//*****************************************************************************
//
//! Enables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions enables the transmit and receive FIFOs in the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x8000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x4000U | 0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Disables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions disables the transmit and receive FIFOs in the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~0x4000U;
}

//*****************************************************************************
//
//! Determines if the FIFO enhancement is enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns a flag indicating whether or not the FIFO enhancement
//! is enabled.
//!
//! \return Returns \b true if the FIFO enhancement is enabled or \b false
//! if the FIFO enhancement is disabled.
//
//*****************************************************************************
static inline _Bool
SCI_isFIFOEnabled(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return true if the FIFO is enabled and false if it is disabled.
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) & 0x4000U) ==
            0x4000U) ? 1 : 0);
}

//*****************************************************************************
//
//! Resets the receive FIFO.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions resets the receive FIFO of the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_resetRxFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Reset the specified FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &= ~0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Resets the transmit FIFO.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions resets the transmit FIFO of the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_resetTxFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Reset the specified FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Resets the SCI Transmit and Receive Channels
//!
//! \param base is the base address of the SCI port.
//!
//! This functions resets transmit and receive channels in the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_resetChannels(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Reset the Tx and Rx Channels
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~0x8000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x8000U;
}

//*****************************************************************************
//
//! Determines if there are any characters in the receive buffer when the
//! FIFO enhancement is not enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns a flag indicating whether or not there is data
//! available in the receive buffer.
//!
//! \return Returns \b true if there is data in the receive buffer or \b false
//! if there is no data in the receive buffer.
//
//*****************************************************************************
static inline _Bool
SCI_isDataAvailableNonFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the availability of characters with FIFO disabled.
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))) & 0x40U) ==
            0x40U) ? 1 : 0);
}

//*****************************************************************************
//
//! Determines if there is any space in the transmit buffer when the FIFO
//! enhancement is not enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns a flag indicating whether or not there is space
//! available in the transmit buffer when not using the FIFO enhancement.
//!
//! \return Returns \b true if there is space available in the transmit buffer
//! or \b false if there is no space available in the transmit buffer.
//
//*****************************************************************************
static inline _Bool
SCI_isSpaceAvailableNonFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the availability of space.
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & 0x80U) ==
            0x80U) ? 1 : 0);
}

//*****************************************************************************
//
//! Get the transmit FIFO status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions gets the current number of words in the transmit FIFO.
//!
//! \return Returns the current number of words in the transmit FIFO specified
//! as one of the following:
//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, \b SCI_FIFO_TX3
//! \b SCI_FIFO_TX4, ..., or \b SCI_FIFO_TX16
//
//*****************************************************************************
static inline SCI_TxFIFOLevel
SCI_getTxFIFOStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the current FIFO status
    //
    return((SCI_TxFIFOLevel)(((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) & 0x1F00U) >>
                             8U));
}

//*****************************************************************************
//
//! Get the receive FIFO status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions gets the current number of words in the receive FIFO.
//!
//! \return Returns the current number of words in the receive FIFO specified
//! as one of the following:
//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, \b SCI_FIFO_RX3
//! \b SCI_FIFO_RX4, ..., or \b SCI_FIFO_RX16
//
//*****************************************************************************
static inline SCI_RxFIFOLevel
SCI_getRxFIFOStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the current FIFO status
    //
    return((SCI_RxFIFOLevel)(((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) & 0x1F00U) >>
                             8U));
}

//*****************************************************************************
//
//! Determines whether the SCI transmitter is busy or not.
//!
//! \param base is the base address of the SCI port.
//!
//! Allows the caller to determine whether all transmitted bytes have cleared
//! the transmitter hardware when the FIFO is not enabled.  When the FIFO is
//! enabled, this function allows the caller to determine whether there is any
//! data in the FIFO.
//!
//! Without the FIFO enabled, if \b false is returned, the transmit buffer and
//! shift registers are empty and the transmitter is not busy. With the FIFO
//! enabled, if \b false is returned, the FIFO is empty.  This does not
//! necessarily mean that the transmitter is not busy.  The empty FIFO does not
//! reflect the status of the transmitter shift register. The FIFO may be empty
//! while the transmitter is still transmitting data.
//!
//! \return Returns \b true if the SCI is transmitting or \b false if
//! transmissions are complete.
//
//*****************************************************************************
static inline _Bool
SCI_isTransmitterBusy(uint32_t base)
{
    //
    // Check the argument.
    //
    ;

    //
    // Check if FIFO enhancement is enabled.
    //
    if(SCI_isFIFOEnabled(base))
    {
        //
        // With FIFO enhancement, determine if the SCI is busy.
        //
        return((((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) & 0x1F00U) !=
                 0) ? 1 : 0);
    }
    else
    {
        //
        // Without FIFO enhancement, determine if the SCI is busy.
        // Check if the transmit buffer and shift register empty.
        //
        return((((*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) & 0x40U) ==
                0x40U) ? 0 : 1);
    }
}

//*****************************************************************************
//
//! Waits to send a character from the specified port when the FIFO enhancement
//! is enabled.
//!
//! \param base is the base address of the SCI port.
//! \param data is the character to be transmitted.
//!
//! Sends the character \e data to the transmit buffer for the specified port.
//! If there is no space available in the transmit FIFO, this function waits
//! until there is space available before returning. \e data is a uint16_t but
//! only 8 bits are written to the SCI port.  SCI only transmits 8 bit
//! characters.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until space is available in the transmit FIFO.
    //
    while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16)
    {
    }

    //
    // Send a char.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = data;
}

//*****************************************************************************
//
//! Waits to send a character from the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param data is the character to be transmitted.
//!
//! Sends the character \e data to the transmit buffer for the specified port.
//! If there is no space available in the transmit buffer, or the transmit
//! FIFO if it is enabled, this function waits until there is space available
//! before returning. \e data is a uint16_t but only 8 bits are written to the
//! SCI port.  SCI only transmits 8 bit characters.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_writeCharBlockingNonFIFO(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until space is available in the transmit buffer.
    //
    while(!SCI_isSpaceAvailableNonFIFO(base))
    {
    }

    //
    // Send a char.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = data;
}

//*****************************************************************************
//
//! Sends a character to the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param data is the character to be transmitted.
//!
//! Writes the character \e data to the transmit buffer for the specified port.
//! This function does not block and only writes to the transmit buffer.
//! The user should use SCI_isSpaceAvailableNonFIFO() or SCI_getTxFIFOStatus()
//! to determine if the transmit buffer or FIFO have space available.
//! \e data is a uint16_t but only 8 bits are written to the SCI port.  SCI
//! only transmits 8 bit characters.
//!
//! This function replaces the original SCICharNonBlockingPut() API and
//! performs the same actions.  A macro is provided in <tt>sci.h</tt> to map
//! the original API to this API.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_writeCharNonBlocking(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Send a char.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x9U)))) = data;
}

//*****************************************************************************
//
//! Gets current receiver status flags.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns the current receiver status flags.  The returned
//! error flags are equivalent to the error bits returned via the previous
//! reading or receiving of a character with the exception that the overrun
//! error is set immediately the overrun occurs rather than when a character
//! is next read.
//!
//! \return Returns a bitwise OR combination of the receiver status flags,
//! \b SCI_RXSTATUS_WAKE, \b SCI_RXSTATUS_PARITY, \b SCI_RXSTATUS_OVERRUN,
//! \b SCI_RXSTATUS_FRAMING, \b SCI_RXSTATUS_BREAK, \b SCI_RXSTATUS_READY,
//! and \b SCI_RXSTATUS_ERROR.
//
//*****************************************************************************
static inline uint16_t
SCI_getRxStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current value of the receive status register.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x5U)))));
}

//*****************************************************************************
//
//! Waits for a character from the specified port when the FIFO enhancement
//! is enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! Gets a character from the receive FIFO for the specified port.  If there
//! are no characters available, this function waits until a character is
//! received before returning. Returns immediately in case of Error.
//!
//! \return Returns the character read from the specified port as \e uint16_t
//!         or 0x0 in case of Error. The application must use
//!         SCI_getRxStatus() API to check if some error occurred before
//!         consuming the data
//
//*****************************************************************************
static inline uint16_t
SCI_readCharBlockingFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until a character is available in the receive FIFO.
    //
    while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0)
    {
        //
        //If there is any error return
        //
        if((SCI_getRxStatus(base) & 0x0080U) != 0U)
        {
            return(0U);
        }
    }

    //
    // Return the character from the receive buffer.
    //
    return((uint16_t)((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) & 0xFFU));
}

//*****************************************************************************
//
//! Waits for a character from the specified port when the FIFO enhancement
//! is not enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! Gets a character from the receive buffer for the specified port.  If there
//! is no characters available, this function waits until a character is
//! received before returning.
//!
//! \return Returns the character read from the specified port as \e uint16_t.
//
//*****************************************************************************
static inline uint16_t
SCI_readCharBlockingNonFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until a character is available in the receive FIFO.
    //
    while(!SCI_isDataAvailableNonFIFO(base))
    {
    }

    //
    // Return the character from the receive buffer.
    //
    return((uint16_t)((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) & 0xFFU));
}

//*****************************************************************************
//
//! Receives a character from the specified port.
//!
//! \param base is the base address of the SCI port.
//!
//! Gets a character from the receive buffer for the specified port. This
//! function does not block and only reads the receive buffer.  The user should
//! use SCI_isDataAvailableNonFIFO() or SCI_getRxFIFOStatus() to determine if
//! the receive buffer or FIFO have data available.
//!
//! This function replaces the original SCICharNonBlockingGet() API and
//! performs the same actions.  A macro is provided in <tt>sci.h</tt> to map
//! the original API to this API.
//!
//! \return Returns \e uin16_t which is read from the receive buffer.
//
//*****************************************************************************
static inline uint16_t
SCI_readCharNonBlocking(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the character from the receive buffer.
    //
    return((uint16_t)((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) & 0xFFU));
}

//*****************************************************************************
//
//! Performs a software reset of the SCI and Clears all reported receiver
//! status flags.
//!
//! \param base is the base address of the SCI port.
//!
//! This function performs a software reset of the SCI port.  It affects the
//! operating flags of the SCI, but it neither affects the configuration bits
//! nor restores the reset values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_performSoftwareReset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // To clear all errors a sw reset of the module is required
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &= ~0x20U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x20U;
}

//*****************************************************************************
//
//! Enables Loop Back Test Mode
//!
//! \param base is the base address of the SCI port.
//!
//! Enables the loop back test mode where the Tx pin is internally connected
//! to the Rx pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the loop back mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x10U;
}

//*****************************************************************************
//
//! Disables Loop Back Test Mode
//!
//! \param base is the base address of the SCI port.
//!
//! Disables the loop back test mode where the Tx pin is no longer internally
//! connected to the Rx pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the loop back mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x10U;
}

//*****************************************************************************
//
//! Get the receive FIFO Overflow flag status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions gets the receive FIFO overflow flag status.
//!
//! \return Returns \b true if overflow has occurred, else returned \b false if
//! an overflow hasn't occurred.
//
//*****************************************************************************
static inline _Bool
SCI_getOverflowStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return the current FIFO overflow status
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) & 0x8000U) == 0x8000U);
}

//*****************************************************************************
//
//! Clear the receive FIFO Overflow flag status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions clears the receive FIFO overflow flag status.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_clearOverflowStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the current FIFO overflow status
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) |= 0x4000U;
}

//*****************************************************************************
//
//! Sets the configuration of a SCI.
//!
//! \param base is the base address of the SCI port.
//! \param lspclkHz is the rate of the clock supplied to the SCI module.  This
//! is the LSPCLK.
//! \param baud is the desired baud rate.
//! \param config is the data format for the port (number of data bits,
//! number of stop bits, and parity).
//!
//! This function configures the SCI for operation in the specified data
//! format.  The baud rate is provided in the \e baud parameter and the data
//! format in the \e config parameter.
//!
//! The \e config parameter is the bitwise OR of three values: the number of
//! data bits, the number of stop bits, and the parity.  \b SCI_CONFIG_WLEN_8,
//! \b SCI_CONFIG_WLEN_7, \b SCI_CONFIG_WLEN_6, \b SCI_CONFIG_WLEN_5,
//! \b SCI_CONFIG_WLEN_4, \b SCI_CONFIG_WLEN_3, \b SCI_CONFIG_WLEN_2, and
//! \b SCI_CONFIG_WLEN_1. Select from eight to one data bits per byte
//! (respectively).
//! \b SCI_CONFIG_STOP_ONE and \b SCI_CONFIG_STOP_TWO select one or two stop
//! bits (respectively).  \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN,
//! \b SCI_CONFIG_PAR_ODD, select the parity mode (no parity bit, even parity
//! bit, odd parity bit respectively).
//!
//! The peripheral clock is the low speed peripheral clock.  This will be
//! the value returned by SysCtl_getLowSpeedClock(), or it can be explicitly
//! hard coded if it is constant and known (to save the code/execution overhead
//! of a call to SysCtl_getLowSpeedClock()).
//!
//! A baud rate divider (BRR) is used in this function to calculate the
//! baud rate. The value of BRR is calculated in float and type casted as int
//! to be fed in the \b SCIHBAUD and  \b SCILBAUD registers. This conversion
//! brings an error in the calculated baud rate and the requested. Error will
//! be significant when operating at higher baud rates. The error is due to
//! lower BRR integer value granularity at higher baud rates.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud,
              uint32_t config);

//*****************************************************************************
//
//! Waits to send an array of characters from the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param array is the address of the array of characters to be transmitted.
//!   It is pointer to the array of characters to be transmitted.
//! \param length is the length of the array, or number of characters in the
//!   array to be transmitted.
//!
//! Sends the number of characters specified by \e length, starting at the
//! address \e array, out of the transmit buffer for the specified port.
//! If there is no space available in the transmit buffer, or the transmit
//! FIFO if it is enabled, this function waits until there is space available
//! and \e length number of characters are transmitted before returning.
//! \e array is a pointer to uint16_ts but only the least significant 8 bits
//! are written to the SCI port.  SCI only transmits 8 bit characters.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_writeCharArray(uint32_t base, const uint16_t * const array,
                   uint16_t length);

//*****************************************************************************
//
//! Waits to receive an array of characters from the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param array is the address of the array of characters to be received.
//!   It is a pointer to the array of characters to be received.
//! \param length is the length of the array, or number of characters in the
//!   array to be received.
//!
//! Receives an array of characters from the receive buffer for the specified
//! port, and stores them as an array of characters starting at address
//! \e array.  This function waits until the \e length number of characters are
//! received before returning.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length);

//*****************************************************************************
//
//! Enables individual SCI interrupt sources.
//!
//! \param base is the base address of the SCI port.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SCI interrupt sources.  Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The \e intFlags parameter is the bitwise OR of any of the following:
//!
//! - \b SCI_INT_RXERR      - RXERR Interrupt
//! - \b SCI_INT_RXRDY_BRKDT - RXRDY/BRKDT Interrupt
//! - \b SCI_INT_TXRDY      - TXRDY Interrupt
//! - \b SCI_INT_TXFF       - TX FIFO Level Interrupt
//! - \b SCI_INT_RXFF       - RX FIFO Level Interrupt
//! - \b SCI_INT_FE         - Frame Error
//! - \b SCI_INT_OE         - Overrun Error
//! - \b SCI_INT_PE         - Parity Error
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_enableInterrupt(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Disables individual SCI interrupt sources.
//!
//! \param base is the base address of the SCI port.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SCI interrupt sources.  Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to SCI_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_disableInterrupt(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param base is the base address of the SCI port.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in SCI_enableInterrupt().
//
//*****************************************************************************
extern uint32_t
SCI_getInterruptStatus(uint32_t base);

//*****************************************************************************
//
//! Clears SCI interrupt sources.
//!
//! \param base is the base address of the SCI port.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SCI interrupt sources are cleared, so that they no longer
//! assert.  This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to SCI_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Sets SCI Baud rate.
//!
//! \param base is the base address of the SCI port.
//! \param lspclkHz is the rate of the clock supplied to the SCI module.  This
//! is the LSPCLK.
//! \param baud is the desired baud rate.
//!
//! This function configures the SCI for operation in the specified baud rate
//! The baud rate is provided in the \e baud parameter.
//!
//! The peripheral clock is the low speed peripheral clock.  This will be
//! the value returned by SysCtl_getLowSpeedClock()
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud);

//*****************************************************************************
//
//! Sets the SCI TXWAKE flag
//!
//! \param base is the base address of the SCI port.
//!
//! This function sets the TXWAKE flag bit to indicate that the next frame
//! is an address frame.
//! TXWAKE bit controls selection of data-transmit feature based on
//! which mode is selected from idle-line and address-bit.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_setWakeFlag(uint32_t base);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   sdfm.h
//
// TITLE:   C28x SDFM Driver
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************


//*****************************************************************************
//
//! \addtogroup sdfm_api SDFM
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_sdfm.h
//
// TITLE:   Definitions for the SDFM registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the SDFM register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the SDIFLG register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDIFLGCLR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDMFILEN register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSTATUS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPH1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA1 register
//
//*************************************************************************************************
                                                // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO1 register
//
//*************************************************************************************************
                                                   // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPH2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPHZ register
//
//*************************************************************************************************
                                            // output

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPL2 register
//
//*************************************************************************************************
                                            // output.

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPH1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA2 register
//
//*************************************************************************************************
                                                // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO2 register
//
//*************************************************************************************************
                                                   // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPH2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPHZ register
//
//*************************************************************************************************
                                            // output

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPL2 register
//
//*************************************************************************************************
                                            // output.

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPH1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA3 register
//
//*************************************************************************************************
                                                // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO3 register
//
//*************************************************************************************************
                                                   // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPH2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPHZ register
//
//*************************************************************************************************
                                            // output

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC3 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPL2 register
//
//*************************************************************************************************
                                            // output.

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPH1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPL1 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA4 register
//
//*************************************************************************************************
                                                // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO4 register
//
//*************************************************************************************************
                                                   // mode

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPH2 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPHZ register
//
//*************************************************************************************************
                                            // output

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC4 register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPL2 register
//
//*************************************************************************************************
                                            // output.

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT2FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT2FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT1FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT1FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT2FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT2FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT1FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT1FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT2FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT2FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT1FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT1FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3LOCK register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4CTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT2FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT2FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT1FLTCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT1FLTCLKCTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4LOCK register
//
//*************************************************************************************************




//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//! Macro to get the low threshold
//!

//! Macro to get the high threshold
//!

//! Macro to get the high threshold 1 & 2 to be passed as lowThreshold
//! parameter to SDFM_setCompFilterLowThreshold().
//!

//! Macro to get the high threshold 1 & 2 to be passed as highThreshold
//! parameter to SDFM_setCompFilterHighThreshold().
//!

//! Macro to convert comparator over sampling ratio to acceptable bit location
//!
//! Macro to convert the data shift bit values to acceptable bit location
//!

//! Macro to combine high threshold and low threshold values
//!

//! Macro to set the FIFO level to acceptable bit location
//!

//! Macro to set and enable the zero cross threshold value.
//!

//! Macros to enable or disable filter.
//!

//*****************************************************************************
//
// Defines for SDFM register offsets. Added for internal use. Not to be used by
// application.
//
//*****************************************************************************
//!< SD filter offset

//!< Event Digital filter offset

//!< Offset between high threshold 1 & 2 registers

//!< Offset between low threshold 1 & 2 registers

//*****************************************************************************
//
// Define to mask out the bits in the SDCOMPHFILCTL register that aren't
// associated with comparator event filter configurations. Added for internal
// use, not to be used in application code.
//
//*****************************************************************************

//*****************************************************************************
//
// Define to mask out the bits in the SDCOMPLOCK register that aren't
// associated with lock configuration.  Added for internal use, not to be used
// in application code.
//
//*****************************************************************************

//*****************************************************************************
//
// Values that can be passed to SDFM_enableSynchronizer() or
// SDFM_disableSynchronizer() as syncConfig parameter.
//
//*****************************************************************************
//! Define for Clock synchronizer Configuration
//! Define for Data Synchronizer Configuration

//*****************************************************************************
//
//! Values that can be returned from SDFM_getThresholdStatus()
//
//*****************************************************************************
typedef enum
{
    SDFM_OUTPUT_WITHIN_THRESHOLD = 0,   //!< SDFM output is within threshold
    SDFM_OUTPUT_ABOVE_THRESHOLD  = 1,   //!< SDFM output is above threshold
    SDFM_OUTPUT_BELOW_THRESHOLD  = 2    //!< SDFM output is below threshold
} SDFM_OutputThresholdStatus;

//*****************************************************************************
//
//! Values that can be passed to all functions as the \e filterNumber
//! parameter.
//
//*****************************************************************************
typedef enum
{
    SDFM_FILTER_1 = 0, //!< Digital filter 1
    SDFM_FILTER_2 = 1, //!< Digital filter 2
    SDFM_FILTER_3 = 2, //!< Digital filter 3
    SDFM_FILTER_4 = 3  //!< Digital filter 4
} SDFM_FilterNumber;

//*****************************************************************************
//
//! Values that can be passed to SDFM_setFilterType(),
//! SDFM_setComparatorFilterType() as the \e filterType parameter.
//
//*****************************************************************************
typedef enum
{
    //! Digital filter with SincFast structure.
    SDFM_FILTER_SINC_FAST = 0x00,
    //! Digital filter with Sinc1 structure
    SDFM_FILTER_SINC_1    = 0x10,
    //! Digital filter with Sinc3 structure.
    SDFM_FILTER_SINC_2    = 0x20,
    //! Digital filter with Sinc4 structure.
    SDFM_FILTER_SINC_3    = 0x30
} SDFM_FilterType;

//*****************************************************************************
//
//! Values that can be passed to SDFM_setupModulatorClock(),as the
//! \e clockMode parameter.
//
//*****************************************************************************
typedef enum
{
   //! Modulator clock is identical to the data rate
   SDFM_MODULATOR_CLK_EQUAL_DATA_RATE  = 0,
} SDFM_ModulatorClockMode;

//*****************************************************************************
//
//! Values that can be passed to SDFM_setOutputDataFormat(),as the
//! \e dataFormat parameter.
//
//*****************************************************************************
typedef enum
{
   //! Filter output is in 16 bits 2's complement format.
   SDFM_DATA_FORMAT_16_BIT = 0,
   //! Filter output is in 32 bits 2's complement format.
   SDFM_DATA_FORMAT_32_BIT = 1
} SDFM_OutputDataFormat;

//*****************************************************************************
//
//! Values that can be passed to SDFM_setDataReadyInterruptSource(),as the
//! \e dataReadySource parameter.
//
//*****************************************************************************
typedef enum
{
   //! Data ready interrupt source is direct (non -FIFO).
   SDFM_DATA_READY_SOURCE_DIRECT = 0,
   //! Data ready interrupt source is FIFO.
   SDFM_DATA_READY_SOURCE_FIFO = 1
} SDFM_DataReadyInterruptSource;

//*****************************************************************************
//
//! Values that can be passed to SDFM_setPWMSyncSource(),as the
//! \e syncSource parameter.
//
//*****************************************************************************
typedef enum
{
   SDFM_SYNC_PWM1_SOCA = 0,    //!< SDFM sync source is PWM1 SOCA
   SDFM_SYNC_PWM1_SOCB = 1,    //!< SDFM sync source is PWM1 SOCB
   SDFM_SYNC_PWM2_SOCA = 4,    //!< SDFM sync source is PWM2 SOCA
   SDFM_SYNC_PWM2_SOCB = 5,    //!< SDFM sync source is PWM2 SOCB
   SDFM_SYNC_PWM3_SOCA = 8,    //!< SDFM sync source is PWM3 SOCA
   SDFM_SYNC_PWM3_SOCB = 9,    //!< SDFM sync source is PWM3 SOCB
   SDFM_SYNC_PWM4_SOCA = 12,   //!< SDFM sync source is PWM4 SOCA
   SDFM_SYNC_PWM4_SOCB = 13,   //!< SDFM sync source is PWM4 SOCB
   SDFM_SYNC_PWM5_SOCA = 16,   //!< SDFM sync source is PWM5 SOCA
   SDFM_SYNC_PWM5_SOCB = 17,   //!< SDFM sync source is PWM5 SOCB
   SDFM_SYNC_PWM6_SOCA = 20,   //!< SDFM sync source is PWM6 SOCA
   SDFM_SYNC_PWM6_SOCB = 21,   //!< SDFM sync source is PWM6 SOCB
   SDFM_SYNC_PWM7_SOCA = 24,   //!< SDFM sync source is PWM7 SOCA
   SDFM_SYNC_PWM7_SOCB = 25,   //!< SDFM sync source is PWM7 SOCB
   SDFM_SYNC_PWM8_SOCA = 28,   //!< SDFM sync source is PWM8 SOCA
   SDFM_SYNC_PWM8_SOCB = 29    //!< SDFM sync source is PWM8 SOCB
} SDFM_PWMSyncSource;

//*****************************************************************************
//
//! Values that can be passed to SDFM_setFIFOClearOnSyncMode(),as the
//! \e fifoClearSyncMode parameter.
//
//*****************************************************************************
typedef enum
{
   //! SDFM FIFO buffer is not cleared on Sync signal
   SDFM_FIFO_NOT_CLEARED_ON_SYNC = 0,
   //! SDFM FIFO buffer is cleared on Sync signal
   SDFM_FIFO_CLEARED_ON_SYNC     = 1
} SDFM_FIFOClearSyncMode;

//*****************************************************************************
//
//! Values that can be passed to SDFM_setWaitForSyncClearMode(),as the
//! \e syncClearMode parameter.
//
//*****************************************************************************
typedef enum
{
   //! Wait for sync cleared using software.
   SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC = 0,
   //! Wait for sync cleared automatically
   SDFM_AUTO_CLEAR_WAIT_FOR_SYNC   = 1
} SDFM_WaitForSyncClearMode;

//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventSource() as the
//! \e compEventNum parameter.
//
//*****************************************************************************
typedef enum
{
    SDFM_COMP_EVENT_1 = 11U, //!< Selects CEVT1
    SDFM_COMP_EVENT_2 = 14U  //!< Selects CEVT2
} SDFM_CompEventNumber;

//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventSource() as the
//! \e compEventSource parameter.
//
//*****************************************************************************
typedef enum
{
    SDFM_COMP_EVENT_SRC_COMPH1    = 0, //!< COMPH1 event is the source
    SDFM_COMP_EVENT_SRC_COMPH1_L1 = 1, //!< Either of COMPH1 or COMPL1 event
                                       //!< can be the source
    SDFM_COMP_EVENT_SRC_COMPH2    = 2, //!< COMPH2 event is the source
    SDFM_COMP_EVENT_SRC_COMPH2_L2 = 3, //!< Either of COMPH2 or COMPL2 event
                                       //!< can be the source
    SDFM_COMP_EVENT_SRC_COMPL1    = 0, //!< COMPL1 event is the source
    SDFM_COMP_EVENT_SRC_COMPL2    = 2  //!< COMPL2 event is the source
} SDFM_CompEventSource;

//*****************************************************************************
//
//! Values that can be passed to SDFM_selectClockSource() as the \e clkSource
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Source is respective channel clock
    SDFM_CLK_SOURCE_CHANNEL_CLK = 0x0,
    //! Source is SD1 channel clock is the source
    SDFM_CLK_SOURCE_SD1_CLK = 0x8U
} SDFM_ClockSource;

//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventHighSource() as the
//! \e source parameter.
//
//*****************************************************************************
typedef enum
{
    //! Comparator event high source is unfiltered event
    SDFM_COMPHOUT_SOURCE_COMPHIN = 0x0,
    //! Comparator event high source is filtered event
    SDFM_COMPHOUT_SOURCE_FILTER  = 0x8
} SDFM_CompEventHighSource;

//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventLowSource() as the
//! \e source parameter.
//
//*****************************************************************************
typedef enum
{
    //! Comparator event low source is unfiltered event
    SDFM_COMPLOUT_SOURCE_COMPLIN = 0x000,
    //! Comparator event low source is filtered event
    SDFM_COMPLOUT_SOURCE_FILTER  = 0x800
} SDFM_CompEventLowSource;

//*****************************************************************************
//
//! Values that can be passed to SDFM_configCompEventLowFilter() &
//! SDFM_configCompEventHighFilter() as the \e filterNumber.
//
//*****************************************************************************
typedef struct
{
    uint16_t sampleWindow; //!< Sample window size
    uint16_t threshold;    //!< Majority voting threshold
    uint16_t clkPrescale;  //!< Sample clock pre-scale
} SDFM_CompEventFilterConfig;

//*****************************************************************************
//
// Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt
// as intFlags parameter
//
//*****************************************************************************
//! Interrupt is generated if Modulator fails.
//!
//! Interrupt on Comparator low-level threshold.
//!
//! Interrupt on Comparator high-level threshold.
//!
//! Interrupt on Acknowledge flag
//!
//! Interrupt on FIFO level
//!
//! Interrupt on FIFO overflow
//!

//*****************************************************************************
//
// Values that can be passed to SDFM_clearInterruptFlag flags parameter
//
//*****************************************************************************
//! Master interrupt flag
//!
//! Filter 1 high -level threshold flag
//!
//! Filter 1 low -level threshold flag
//!
//! Filter 2 high -level threshold flag
//!
//! Filter 2 low -level threshold flag
//!
//! Filter 3 high -level threshold flag
//!
//! Filter 3 low -level threshold flag
//!
//! Filter 4 high -level threshold flag
//!
//! Filter 4 low -level threshold flag
//!
//! Filter 1 modulator failed flag
//!
//! Filter 2 modulator failed flag
//!
//! Filter 3 modulator failed flag
//!
//! Filter 4 modulator failed flag
//!
//! Filter 1 new data flag
//!
//! Filter 2 new data flag
//!
//! Filter 3 new data flag
//!
//! Filter 4 new data flag
//!
//! Filter 1 FIFO overflow flag
//!
//! Filter 2 FIFO overflow flag
//!
//! Filter 3 FIFO overflow flag
//!
//! Filter 4 FIFO overflow flag
//!
//! Filter 1 FIFO overflow flag
//!
//! Filter 2 FIFO overflow flag
//!
//! Filter 3 FIFO overflow flag
//!
//! Filter 4 FIFO overflow flag
//!

//*****************************************************************************
//
//! \internal
//! Checks SDFM base address.
//!
//! \param base specifies the SDFM module base address.
//!
//! This function determines if SDFM module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enable external reset
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables data filter to be reset by an external source (PWM
//! compare output).
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Set the SDSYNCEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U + ((uint32_t)filterNumber * 16U))))) |=
        0x1000U;
    __edis();
}

//*****************************************************************************
//
//! Disable external reset
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables data filter from being reset by an external source
//! (PWM compare output).
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_disableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Clear the SDSYNCEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U + ((uint32_t)filterNumber * 16U))))) &=
        ~0x1000U;
    __edis();
}

//*****************************************************************************
//
//! Enable filter
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables the filter specified by the \e filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Set the FEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U + ((uint32_t)filterNumber * 16U))))) |=
        0x100U;
    __edis();
}

//*****************************************************************************
//
//! Disable filter
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables the filter specified by the \e filterNumber
//! variable.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_disableFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Clear the FEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x11U + ((uint32_t)filterNumber * 16U))))) &=
        ~0x100U;
    __edis();
}

//*****************************************************************************
//
//! Enable FIFO buffer
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables the filter FIFO buffer specified by the
//! \e filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableFIFOBuffer(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Set the FFEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1DU + ((uint32_t)filterNumber * 16U))))) |=
        0x2000U;
    __edis();
}

//*****************************************************************************
//
//! Disable FIFO buffer
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables the filter FIFO buffer specified by the
//! \e filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableFIFOBuffer(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Clear the FFEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1DU + ((uint32_t)filterNumber * 16U))))) &=
        ~0x2000U;
    __edis();
}

//*****************************************************************************
//
//! Return the Zero Cross Trip status
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Zero Cross Trip status for the filter
//! specified by filterNumber variable.
//!
//! \return \b true if Comparator filter output >= High-level threshold (Z)
//!         \b false if Comparator filter output < High-level threshold (Z)
//
//*****************************************************************************
static inline _Bool
SDFM_getZeroCrossTripStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))) >> (uint16_t)filterNumber) &
            0x1U) == 1U);
}

//*****************************************************************************
//
//! Clear the Zero Cross Trip status
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//!  This function clears the Zero Cross Trip status for the filter
//!  specified by filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_clearZeroCrossTripStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Set SDCTL MIE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= (1U << filterNumber);
    __edis();
}

//*****************************************************************************
//
//! Enable Comparator.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//!  This function enables the Comparator for the selected filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableComparator(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Set CEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U + ((uint32_t)filterNumber * 16U))))) |=
        0x2000U;
    __edis();
}

//*****************************************************************************
//
//! Disable Comparator.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//!  This function disables the Comparator for the selected filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableComparator(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Clear CEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U + ((uint32_t)filterNumber * 16U))))) &=
        ~0x2000U;
    __edis();
}

//*****************************************************************************
//
//! Selects Comparator Event Source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number
//! \param compEventNum is the event number
//! \param compEventSource is the event source
//!
//!  This function selects the comparator event source. Valid values for
//! \e compEventNum are:
//! - SDFM_COMP_EVENT_1 - Selects comparator event 1
//! - SDFM_COMP_EVENT_2 - Selects comparator event 2
//! Valid values for \e SDFM_COMP_EVENT_1 are:
//! - SDFM_COMP_EVENT_SRC_COMPH1 - COMPH1 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH1_L1 - Either of COMPH1 or COMPL1 event can be
//!                                   the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH2 - COMPH2 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH2_L2 - Either of COMPH2 or COMPL2 event can be
//!                                   the source for selected event
//!
//! Valid values for \e SDFM_COMP_EVENT_2 are:
//! - SDFM_COMP_EVENT_SRC_COMPL1 - COMPL1 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH1_L1 - Either of COMPH1 or COMPL1 event can be
//!                                   the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPL2 - COMPL2 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH2_L2 - Either of COMPH2 or COMPL2 event can be
//!                                   the source for selected event
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectCompEventSource(uint32_t base, SDFM_FilterNumber filterNumber,
                           SDFM_CompEventNumber compEventNum,
                           SDFM_CompEventSource compEventSource)
{
    uint32_t address;
    ;
    address = base + 0x15U + ((uint32_t)filterNumber *
                                         (0x20U - 0x10U));

    //
    // Select source for selected comparator event
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~((uint16_t)0x2U << compEventNum)) |
                      ((uint16_t)compEventSource << compEventNum) ;
    __edis();
}

//*****************************************************************************
//
//! Set filter type.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param filterType is the filter type or structure.
//!
//! This function sets the filter type or structure to be used as specified by
//! filterType for the selected filter number as specified by filterNumber.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setFilterType(uint32_t base, SDFM_FilterNumber filterNumber,
                   SDFM_FilterType filterType)
{
    uint32_t address;

    ;

    address = base + 0x11U + ((uint32_t)filterNumber * 16U);

    //
    // Write to SST bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0xC00U)) |
                      ((uint16_t)filterType << 6U);
    __edis();
}

//*****************************************************************************
//
//! Set data filter over sampling ratio.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param overSamplingRatio is the data filter over sampling ratio.
//!
//! This function sets the filter oversampling ratio for the filter specified
//! by the filterNumber variable.Valid values for the variable
//! overSamplingRatio are 0 to 255 inclusive. The actual oversampling ratio
//! will be this value plus one.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber,
                                uint16_t overSamplingRatio)
{
    uint32_t address;

    ;
    ;

    address = base + 0x11U + ((uint32_t)filterNumber * 16U);

    //
    // Write to DOSR bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0xFFU)) |
                      overSamplingRatio;
    __edis();
}

//*****************************************************************************
//
//! Set modulator clock mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param clockMode is the modulator clock mode.
//!
//! This function sets the modulator clock mode specified by clockMode
//! for the filter specified by filterNumber.
//!
//! \note This function also enables the data and clock synchronizers for
//! the specified filter.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setupModulatorClock(uint32_t base, SDFM_FilterNumber filterNumber,
                         SDFM_ModulatorClockMode clockMode)
{
    uint32_t address;

    ;

    address = base + 0x10U + ((uint32_t)filterNumber * 16U);

    //
    // Write to MOD bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0x3U)) |
                      (uint16_t)clockMode;

    //
    // Enable data and clock synchronizer
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U + ((uint32_t)filterNumber * (0x20U - 0x10U)))))) |=
           (0x10U | 0x40U);
    __edis();
}

//*****************************************************************************
//
//! Set the output data format
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param dataFormat is the output data format.
//!
//! This function sets the output data format for the filter specified by
//! filterNumber.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setOutputDataFormat(uint32_t base, SDFM_FilterNumber filterNumber,
                         SDFM_OutputDataFormat dataFormat)
{
    uint32_t address;

    ;

    address = base + 0x12U + ((uint32_t)filterNumber * 16U);

    //
    // Write to DR bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0x400U)) |
                      ((uint16_t)dataFormat << 10U);
    __edis();
}

//*****************************************************************************
//
//! Set data shift value.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param shiftValue is the data shift value.
//!
//! This function sets the shift value for the 16 bit 2's complement data
//! format. The valid maximum value for shiftValue is 31.
//!
//! \b Note: Use this function with 16 bit 2's complement data format only.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setDataShiftValue(uint32_t base, SDFM_FilterNumber filterNumber,
                       uint16_t shiftValue)
{
    uint32_t address;

    ;
    ;

    address = base + 0x12U + ((uint32_t)filterNumber * 16U);

    //
    // Write to SH bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0xF800U)) |
                      (shiftValue << 11U);
    __edis();
}


//*****************************************************************************
//
//! Set Filter output high-level threshold.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param highThreshold is the high-level threshold 1 & 2.
//!
//! This function sets the unsigned high-level threshold value for the
//! Comparator filter output. If the output value of the filter exceeds
//! highThreshold and interrupt generation is enabled, an interrupt will be
//! issued. The param \b highThreshold takes both high threshold 1 & 2 values.
//! The upper 16-bits represent the high threshold 2 value while lower 16-bits
//! represent the threshold 1 values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setCompFilterHighThreshold(uint32_t base, SDFM_FilterNumber filterNumber,
                                uint32_t highThreshold)
{
    uint32_t address;

    ;
    ;
    ;

    address = base + 0x13U +
              ((uint32_t)filterNumber * (0x20U - 0x10U));

    //
    // Write to HLT bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0x7FFFU) |
                      (uint16_t)highThreshold;
    (*((volatile uint16_t *)((uintptr_t)(address + (0x1BU - 0x13U))))) =
                                  ((*((volatile uint16_t *)((uintptr_t)(address + (0x1BU - 0x13U))))) &
                                   ~0x7FFFU) |
                                  (uint16_t)(highThreshold >> 16U);
    __edis();
}

//*****************************************************************************
//
//! Set Filter output low-level threshold.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number
//! \param lowThreshold is the low-level threshold
//!
//! This function sets the unsigned low-level threshold value 1 or 2 for the
//! Comparator filter output. If the output value of the filter gets below
//! lowThreshold and interrupt generation is enabled, an interrupt will be
//! issued. The param \b lowThreshold takes both low threshold 1 & 2 values.
//! The upper 16-bits represent the low threshold 2 value while lower 16-bits
//! represent the threshold 1 values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setCompFilterLowThreshold(uint32_t base, SDFM_FilterNumber filterNumber,
                               uint32_t lowThreshold)
{
    uint32_t address;

    ;
    ;
    ;

    address = base + 0x14U +
              ((uint32_t)filterNumber * (0x20U - 0x10U));

    //
    // Write to LLT bit.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0x7FFFU) |
                      (uint16_t)lowThreshold;
    (*((volatile uint16_t *)((uintptr_t)(address + (0x1FU - 0x14U))))) =
                                   ((*((volatile uint16_t *)((uintptr_t)(address + (0x1FU - 0x14U))))) &
                                    ~0x7FFFU) |
                                   (uint16_t)(lowThreshold >> 16U);
    __edis();
}
//*****************************************************************************
//
//! Set Filter output zero-cross threshold.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param zeroCrossThreshold is the zero-cross threshold.
//!
//! This function sets the unsigned zero-cross threshold value for the
//! Comparator filter output.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setCompFilterZeroCrossThreshold(uint32_t base,
                                     SDFM_FilterNumber filterNumber,
                                     uint16_t zeroCrossThreshold)
{
    uint32_t address;

    ;
    ;

    address = base + 0x1CU + ((uint32_t)filterNumber * 16U);

    //
    // Write to ZCT bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0x7FFFU) |
                      zeroCrossThreshold;

    __edis();
}

//*****************************************************************************
//
//! Enable zero-cross Edge detect mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables Zero Cross Edge detection.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableZeroCrossEdgeDetect(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Set ZCEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U + ((uint32_t)filterNumber * 16U))))) |=
        0x400U;
    __edis();
}

//*****************************************************************************
//
//! Disable zero-cross Edge detect mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables Zero Cross Edge detection.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableZeroCrossEdgeDetect(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Clear ZCEN bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x15U + ((uint32_t)filterNumber * 16U))))) &=
        ~0x400U;
    __edis();
}

//*****************************************************************************
//
//! Enable SDFM interrupts.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param intFlags is the interrupt source.
//!
//! This function enables the low threshold , high threshold or modulator
//! failure interrupt as determined by intFlags for the filter specified
//! by filterNumber.
//! Valid values for intFlags are:
//!  SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT,
//!  SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT, SDFM_FIFO_INTERRUPT,
//!  SDFM_FIFO_OVERFLOW_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber,
                     uint16_t intFlags)
{
    uint16_t offset;

    ;

    offset = (uint16_t)filterNumber * 16U;

    __eallow();

    //
    // Low, high threshold, Modulator failure
    //
    if((intFlags & (0x200U |
                    0x40U |
                    0x20U)) != 0U)
    {
        //
        // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x15U + offset)))) |=
                (intFlags & (0x200U |
                             0x40U |
                             0x20U));
    }

    //
    // Data filter acknowledge interrupt
    //
    if((intFlags & 0x1U) != 0U)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x11U + offset)))) |= 0x200U;
    }

    //
    // FIFO , FIFO overflow interrupt
    //
    if((intFlags & (0x1000U | 0x8000U)) != 0U)
    {
        //
        // Set OVFIEN or FFIEN bits of SDFM_O_SDFIFOCTLx
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x1DU + offset)))) |=
                (intFlags & (0x1000U |
                             0x8000U));
    }
    __edis();
}

//*****************************************************************************
//
//! Disable SDFM interrupts.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param intFlags is the interrupt source.
//!
//! This function disables the low threshold , high threshold or modulator
//! failure interrupt as determined by intFlags for the filter
//! specified by filterNumber.
//! Valid values for intFlags are:
//!  SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT,
//!  SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT, SDFM_FIFO_INTERRUPT,
//!  SDFM_FIFO_OVERFLOW_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber,
                      uint16_t intFlags)
{
    uint16_t offset;

    ;

    offset = (uint16_t)filterNumber * 16U;

    __eallow();

    //
    // Low, high threshold, modulator failure interrupts
    //
    if((intFlags & (0x200U |
                    0x40U |
                    0x20U)) != 0U)
    {
        //
        // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx
        //
        (*((volatile uint16_t *)((uintptr_t)(base + 0x15U + offset)))) &=
            ~(intFlags & (0x200U |
                          0x40U |
                          0x20U));
    }

    //
    // Data filter acknowledge interrupt
    //
    if((intFlags & 0x1U) != 0U)
    {
        (*((volatile uint16_t *)((uintptr_t)(base + 0x11U + offset)))) &= ~0x200U;
    }

    //
    // FIFO , FIFO overflow interrupt
    //
    if((intFlags & (0x1000U | 0x8000U)) != 0U)
    {
         //
         // Set OVFIEN or FFIEN bits of SDFM_O_SDFIFOCTLx
         //
         (*((volatile uint16_t *)((uintptr_t)(base + 0x1DU + offset)))) &=
            ~(intFlags & (0x1000U | 0x8000U));
    }
    __edis();
}

//*****************************************************************************
//
//! Set the comparator filter type.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param filterType is the comparator filter type or structure.
//!
//! This function sets the Comparator filter type or structure to be used as
//! specified by filterType for the selected filter number as specified by
//! filterNumber.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setComparatorFilterType(uint32_t base, SDFM_FilterNumber filterNumber,
                             SDFM_FilterType filterType)
{
    uint32_t address;

    ;

    address = base + 0x15U + ((uint32_t)filterNumber * 16U);

    //
    // Write to CS1_CS0 bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0x180U)) |
                      ((uint16_t)filterType << 3U);
    __edis();
}

//*****************************************************************************
//
//! Set Comparator filter over sampling ratio.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param overSamplingRatio is the comparator filter over sampling ration.
//!
//! This function sets the comparator filter oversampling ratio for the filter
//! specified by the filterNumber.Valid values for the variable
//! overSamplingRatio are 0 to 31 inclusive.
//! The actual oversampling ratio will be this value plus one.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setCompFilterOverSamplingRatio(uint32_t base,
                                    SDFM_FilterNumber filterNumber,
                                    uint16_t overSamplingRatio)
{
    uint32_t address;

    ;
    ;

    address = base + 0x15U + ((uint32_t)filterNumber * 16U);

    //
    // Write to COSR bits
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0x1FU)) |
                      overSamplingRatio;
    __edis();
}

//*****************************************************************************
//
//! Get the filter data output.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the latest data filter output. Depending on the
//! filter data output format selected, the valid value will be the lower 16
//! bits or the whole 32 bits of the returned value.
//!
//! \return Returns the latest data filter output.
//*****************************************************************************
static inline uint32_t
SDFM_getFilterData(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDDATA bits
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x16U + ((uint32_t)filterNumber * 16U))))));
}

//*****************************************************************************
//
//! Get the Comparator threshold status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Comparator output threshold status for the given
//! filterNumber.
//!
//! \return Returns the following status flags.
//! - \b SDFM_OUTPUT_WITHIN_THRESHOLD if the output is within the
//!                                   specified threshold.
//! - \b SDFM_OUTPUT_ABOVE_THRESHOLD  if the output is above the high
//!                                   threshold
//! - \b SDFM_OUTPUT_BELOW_THRESHOLD  if the output is below the low
//!                                   threshold.
//!
//*****************************************************************************
static inline SDFM_OutputThresholdStatus
SDFM_getThresholdStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDIFLG high/low threshold bits
    //
    return((SDFM_OutputThresholdStatus)(((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) >>
                                        (2U * (uint16_t)filterNumber)) & 0x3U));
}

//*****************************************************************************
//
//! Get the Modulator status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Modulator status.
//!
//! \return Returns true if the Modulator is operating normally
//!         Returns false if the Modulator has failed
//!
//*****************************************************************************
static inline _Bool
SDFM_getModulatorStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDIFLG MF1, MF2, MF3 OR MF4 bits
    //
    return((((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) >> ((uint16_t)filterNumber + 8U)) &
            0x1U) != 0x1U);
}

//*****************************************************************************
//
//! Check if new Filter data is available.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns new filter data status.
//!
//! \return Returns \b true if new filter data is available
//!         Returns \b false if no new filter data is available
//!
//*****************************************************************************
static inline _Bool
SDFM_getNewFilterDataStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDIFLG AF1, AF2, AF3 OR AF4 bits
    //
    return((((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) >> ((uint16_t)filterNumber + 12U)) &
            0x1U) == 0x1U);
}

//*****************************************************************************
//
//! Check if FIFO buffer is overflowed.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the status of the FIFO buffer overflow for the given
//! filter value.
//!
//! \return Returns \b true if FIFO buffer is overflowed
//!         Returns \b false if FIFO buffer is not overflowed
//!
//*****************************************************************************
static inline _Bool
SDFM_getFIFOOverflowStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDIFLG SDFFOVF1, SDFFOVF2, SDFFOVF3 OR SDFFOVF4 bits
    //
    return((((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) >> ((uint16_t)filterNumber + 16U)) &
            0x1U) == 0x1U);
}

//*****************************************************************************
//
//! Check FIFO buffer interrupt status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the status of the FIFO buffer interrupt for the given
//! filter.
//!
//! \return Returns \b true if FIFO buffer interrupt has occurred.
//!         Returns \b false if FIFO buffer interrupt has not occurred.
//!
//*****************************************************************************
static inline _Bool
SDFM_getFIFOISRStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDIFLG SDFFINT1, SDFFINT2, SDFFINT3 OR SDFFINT4 bits
    //
    return((((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) >> ((uint16_t)filterNumber + 20U)) &
            0x1U) == 0x1U);
}

//*****************************************************************************
//
//! Get pending interrupt.
//!
//! \param base is the base address of the SDFM module
//!
//! This function returns any pending interrupt status.
//!
//! \return Returns \b true if there is a pending interrupt.
//!         Returns \b false if no interrupt is pending.
//!
//*****************************************************************************
static inline _Bool
SDFM_getIsrStatus(uint32_t base)
{
    ;

    //
    // Read SDIFLG MIF
    //
    return(((*((volatile uint32_t *)((uintptr_t)(base + 0x0U)))) >> 31U) == 0x1U);
}

//*****************************************************************************
//
//! Clear pending flags.
//!
//! \param base is the base address of the SDFM module
//! \param flag is the SDFM status
//!
//! This function clears the specified pending interrupt flag.
//! Valid values are
//! SDFM_MASTER_INTERRUPT_FLAG,SDFM_FILTER_1_NEW_DATA_FLAG,
//! SDFM_FILTER_2_NEW_DATA_FLAG,SDFM_FILTER_3_NEW_DATA_FLAG,
//! SDFM_FILTER_4_NEW_DATA_FLAG,SDFM_FILTER_1_MOD_FAILED_FLAG,
//! SDFM_FILTER_2_MOD_FAILED_FLAG,SDFM_FILTER_3_MOD_FAILED_FLAG,
//! SDFM_FILTER_4_MOD_FAILED_FLAG,SDFM_FILTER_1_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_1_LOW_THRESHOLD_FLAG,SDFM_FILTER_2_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_2_LOW_THRESHOLD_FLAG,SDFM_FILTER_3_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_3_LOW_THRESHOLD_FLAG,SDFM_FILTER_4_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_4_LOW_THRESHOLD_FLAG,SDFM_FILTER_1_FIFO_OVERFLOW_FLAG,
//! SDFM_FILTER_2_FIFO_OVERFLOW_FLAG,SDFM_FILTER_3_FIFO_OVERFLOW_FLAG
//! SDFM_FILTER_4_FIFO_OVERFLOW_FLAG,SDFM_FILTER_1_FIFO_INTERRUPT_FLAG,
//! SDFM_FILTER_2_FIFO_INTERRUPT_FLAG,SDFM_FILTER_3_FIFO_INTERRUPT_FLAG
//! SDFM_FILTER_4_FIFO_INTERRUPT_FLAG or any combination of the above flags.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_clearInterruptFlag(uint32_t base, uint32_t flag)
{
    ;
    ;

    //
    // Write to  SDIFLGCLR register
    //
    (*((volatile uint32_t *)((uintptr_t)(base + 0x2U)))) |= flag;
}

//*****************************************************************************
//
//! Enable master interrupt.
//!
//! \param base is the base address of the SDFM module
//!
//! This function enables the master SDFM interrupt.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_enableMasterInterrupt(uint32_t base)
{
    ;

    //
    // Set SDCTL MIE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) |= 0x2000U;
    __edis();
}

//*****************************************************************************
//
//! Disable master interrupt.
//!
//! \param base is the base address of the SDFM module
//!
//! This function disables the master SDFM interrupt.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_disableMasterInterrupt(uint32_t base)
{
    ;

    //
    // Clear SDCTL MIE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x4U)))) &= ~0x2000U;
    __edis();
}

//*****************************************************************************
//
//! Enable master filter.
//!
//! \param base is the base address of the SDFM module
//!
//! This function enables master filter.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_enableMasterFilter(uint32_t base)
{
    ;

    //
    // Set SDMFILEN MFE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) |= 0x800U;
    __edis();
}

//*****************************************************************************
//
//! Disable master filter.
//!
//! \param base is the base address of the SDFM module
//!
//! This function disables master filter.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_disableMasterFilter(uint32_t base)
{
    ;

    //
    // Clear SDMFILEN MFE bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))) &= ~0x800U;
    __edis();
}

//*****************************************************************************
//
//! Return the FIFO data count
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the FIFO data count.
//!
//! \return Returns the number of data words available in FIFO buffer.
//
//*****************************************************************************
static inline uint16_t
SDFM_getFIFODataCount(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDFFST
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0x1DU + ((uint32_t)filterNumber * 16U))))) & 0x7C0U) >>
         6U);
}

//*****************************************************************************
//
//! Return the Comparator sinc filter data
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Comparator sinc filter data output.
//!
//! \return Returns the Comparator sinc filter data output.
//!
//
//*****************************************************************************
static inline uint16_t
SDFM_getComparatorSincData(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDCDATA
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x1AU + ((uint32_t)filterNumber * 16U))))));
}

//*****************************************************************************
//
//! Return the FIFO data
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the latest FIFO data.
//!
//! \return Returns the latest FIFO data.
//!
//! \note Discard the upper 16 bits if the output data format is 16bits.
//
//*****************************************************************************
static inline uint32_t
SDFM_getFIFOData(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read SDDATFIFO
    //
    return((*((volatile uint32_t *)((uintptr_t)(base + 0x18U + ((uint32_t)filterNumber * 16U))))));
}

//*****************************************************************************
//
//! Set the FIFO interrupt level.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param fifoLevel is the FIFO interrupt level.
//!
//! This function sets the FIFO interrupt level. Interrupt is generated when
//! the FIFO buffer word count gets to or exceeds the value of \e fifoLevel.
//! Maximum value for \e fifoLevel is 16.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setFIFOInterruptLevel(uint32_t base, SDFM_FilterNumber filterNumber,
                           uint16_t fifoLevel)
{
    uint32_t address;

    ;
    ;

    address = base + 0x1DU + ((uint32_t)filterNumber * 16U);

    //
    // Write to SDFFIL bit
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) =
        (((*((volatile uint16_t *)((uintptr_t)(address)))) & (~0x1FU)) | fifoLevel);
    __edis();
}

//*****************************************************************************
//
//! Set data ready interrupt source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param dataReadySource is the data ready interrupt source.
//!
//! This function sets the data ready interrupt source.
//! Valid values for \e dataReadySource:
//!   - SDFM_DATA_READY_SOURCE_DIRECT - Direct data ready
//!   - SDFM_DATA_READY_SOURCE_FIFO  - FIFO data ready.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setDataReadyInterruptSource(uint32_t base, SDFM_FilterNumber filterNumber,
                                 SDFM_DataReadyInterruptSource dataReadySource)
{
    uint32_t address;

    ;

    address = base + 0x1DU + ((uint32_t)filterNumber * 16U);

    //
    // Write to DRINTSEL
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0x4000U) |
                      ((uint16_t)dataReadySource << 14U);
    __edis();
}

//*****************************************************************************
//
//! Get the wait-for-sync event status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Wait-for-Sync event status.
//!
//! \return Returns true if sync event has occurred.
//!         Returns false if sync event has not occurred.
//
//*****************************************************************************
static inline _Bool
SDFM_getWaitForSyncStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Read WTSYNFLG bit
    //
    return((((*((volatile uint16_t *)((uintptr_t)(base + 0x1EU + ((uint32_t)filterNumber * 16U))))) &
            0x80U) >> 7U) == 0x1U);
}

//*****************************************************************************
//
//! Clear the Wait-for-sync event status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function clears the Wait-for-sync event status.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_clearWaitForSyncFlag(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    __eallow();

    //
    // Clear WTSYNCLR bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU + ((uint32_t)filterNumber * 16U))))) |=
           0x100U;
    __edis();
}

//*****************************************************************************
//
//! Enable wait for sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables the wait for sync mode. Data to FIFO will be written
//! only after PWM sync event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableWaitForSync(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    __eallow();

    //
    // Set WTSYNCEN bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU + ((uint32_t)filterNumber * 16U))))) |=
        0x40U;
    __edis();
}

//*****************************************************************************
//
//! Disable wait for sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables the wait for sync mode. Data to FIFO will be written
//! every Data ready event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableWaitForSync(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    __eallow();

    //
    // Clear WTSYNCEN bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1EU + ((uint32_t)filterNumber * 16U))))) &=
        ~0x40U;
    __edis();
}

//*****************************************************************************
//
//! Set the PWM sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncSource is the PWM sync source.
//!
//! This function sets the PWM sync source for the specific SDFM filter. Valid
//! values for syncSource are SDFM_SYNC_PWMx_CMPy. Where x ranges from 1 to 8
//! Representing PWM1 to PWM8 respectively and y ranges from A to D
//! representing PWM comparators A to D.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setPWMSyncSource(uint32_t base, SDFM_FilterNumber filterNumber,
                      SDFM_PWMSyncSource syncSource)
{
    uint32_t address;

    ;

    address = base + 0x1EU + ((uint32_t)filterNumber * 16U);

    __eallow();

    //
    // Write to SYNCSEL bits
    //
    (*((volatile uint16_t *)((uintptr_t)(address)))) =
        ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0x3FU) | (uint16_t)syncSource;
    __edis();
	
	//
	//Enable SDSYNC reset to data filter
	//
	SDFM_enableExternalReset(base, filterNumber);
}

//*****************************************************************************
//
//! Set FIFO clear on sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param fifoClearSyncMode is the FIFO clear on sync mode.
//!
//! This function sets the FIFO clear mode for the specified filter when a sync
//! happens depending on the value of fifoClearSyncMode.
//! Valid values for fifoClearSyncMode are:
//!  - SDFM_FIFO_NOT_CLEARED_ON_SYNC - FIFO is not cleared on sync.
//!  - SDFM_FIFO_CLEARED_ON_SYNC - FIFO is cleared on sync.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setFIFOClearOnSyncMode(uint32_t base, SDFM_FilterNumber filterNumber,
                            SDFM_FIFOClearSyncMode fifoClearSyncMode)
{
    uint32_t address;

    ;

    address = base + 0x1EU + ((uint32_t)filterNumber * 16U);

    __eallow();

    //
    // Write to FFSYNCCLREN bit
    //
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0x200U) |
                      ((uint16_t)fifoClearSyncMode << 9U);
    __edis();
}

//*****************************************************************************
//
//! Set Wait-for-sync clear mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncClearMode is the wait-for-sync clear mode.
//!
//! This function sets the Wait-For-sync clear mode depending on the value of
//! syncClearMode.
//! Valid values for syncClearMode are:
//!   - SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC - Wait-for-sync flag is cleared by
//!                                       invoking SDFM_clearWaitForSyncFlag().
//!   - SDFM_AUTO_CLEAR_WAIT_FOR_SYNC   - Wait-for-sync flag is cleared
//!                                       automatically on FIFO interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setWaitForSyncClearMode(uint32_t base, SDFM_FilterNumber filterNumber,
                             SDFM_WaitForSyncClearMode syncClearMode)
{
    uint32_t address;

    ;

    address = base + 0x1EU + ((uint32_t)filterNumber * 16U);

    __eallow();

    //
    // Write to WTSCLREN  bit
    //
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0x400U) |
                      ((uint16_t)syncClearMode << 10U);
    __edis();
}

//*****************************************************************************
//
//! Selects clock source for SDFM channels.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param clkSource is the clock source
//!
//! This function selects the clock for SDFM module filter channels.
//! Valid values for clkSource are:
//!   - SDFM_CLK_SOURCE_CHANNEL_CLK - Respective channel's clk is the source
//!   - SDFM_CLK_SOURCE_SD1_CLK     - Filter 1 clock is the source
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectClockSource(uint32_t base, SDFM_FilterNumber filterNumber,
                       SDFM_ClockSource clkSource)
{
    uint32_t address;

    ;
    address = base + 0x10U +
              ((uint32_t)filterNumber * (0x20U - 0x10U));

    //
    // Select SDFM clock source.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~(0x8U)) |
                      (uint16_t)clkSource;
    __edis();
}

//*****************************************************************************
//
//! Enables Input Synchronizer.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncConfig defines which synchronizer to be enabled
//!
//! This function enables either data or clock or both synchronizer.
//! Valid values for syncConfig can be the logical OR of any of the values:
//!   - SDFM_CLOCK_SYNCHRONIZER - Enable SDFM input clock synchronizer
//!   - SDFM_DATA_SYNCHRONIZER  - Enable SDFM input data synchronizer
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableSynchronizer(uint32_t base, SDFM_FilterNumber filterNumber,
                        uint16_t syncConfig)
{
    ;

    //
    // Select SDFM clock source.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U + ((uint32_t)filterNumber * (0x20U - 0x10U)))))) |= syncConfig;
    __edis();
}

//*****************************************************************************
//
//! Disables Input Synchronizer.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncConfig defines which synchronizer to be disabled
//!
//! This function disables either data or clock or both synchronizer.
//! Valid values for syncConfig can be the logical OR of any of the values:
//!   - SDFM_CLOCK_SYNCHRONIZER - Disable SDFM input clock synchronizer
//!   - SDFM_DATA_SYNCHRONIZER  - Disable SDFM input data synchronizer
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableSynchronizer(uint32_t base, SDFM_FilterNumber filterNumber,
                         uint16_t syncConfig)
{
    ;

    //
    // Select SDFM clock source.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x10U + ((uint32_t)filterNumber * (0x20U - 0x10U)))))) &= ~syncConfig;
    __edis();
}

//*****************************************************************************
//
//! Selects comparator event high source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param source is the comparator event high source
//!
//! This function selects the source for comparator event high.
//! Valid values for source are:
//!   - SDFM_COMPHOUT_SOURCE_COMPHIN - Original COMPHIN/CEVT1 signal is source
//!   - SDFM_COMPHOUT_SOURCE_FILTER  - Filtered COMPHIN/CEVT1 signal is source
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectCompEventHighSource(uint32_t base, SDFM_FilterNumber filterNumber,
                               SDFM_CompEventHighSource source)
{
    uint32_t address;
    ;
    address = base + 0x60U +
              ((uint32_t)filterNumber * (0x68U - 0x60U));

    //
    // Set COMPHOUT source.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0xCU) |
                      (uint16_t)source;
    __edis();
}

//*****************************************************************************
//
//! Selects comparator event low source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param source is the comparator event low source
//!
//! This function selects the source for comparator event low.
//! Valid values for source are:
//!   - SDFM_COMPLOUT_SOURCE_COMPLIN - Original COMPLIN/CEVT2 signal is source
//!   - SDFM_COMPHOUT_SOURCE_FILTER  - Filtered COMPLIN/CEVT2 signal is source
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectCompEventLowSource(uint32_t base, SDFM_FilterNumber filterNumber,
                              SDFM_CompEventLowSource source)
{
    uint32_t address;
    ;
    address = base + 0x60U +
              ((uint32_t)filterNumber * (0x68U - 0x60U));

    //
    // Set COMPLOUT source.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(address)))) = ((*((volatile uint16_t *)((uintptr_t)(address)))) & ~0xC00U) |
                      (uint16_t)source;
    __edis();
}

//*****************************************************************************
//
//! Initializes Comparator Event Low Filter.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function initializes Comparator Event Low Filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_initCompEventLowFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Initialize comparator event low filter.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x61U + ((uint32_t)filterNumber * (0x68U - 0x60U)))))) |=
                                      (uint16_t)0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Initializes Comparator Event High Filter.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function initializes Comparator Event High Filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_initCompEventHighFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
    ;

    //
    // Initialize comparator event high filter.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x63U + ((uint32_t)filterNumber * (0x68U - 0x60U)))))) |=
                                      (uint16_t)0x8000U;
    __edis();
}

//*****************************************************************************
//
//! Lock Comparator Event Filter Configurations
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param lockConfig defines the configurations to be locked
//!
//! This function locks the comparator event filter configurations. Valid
//! values of the lockConfig can be logical OR of any of the following values:
//! - SDFM_SDCOMPLOCK_SDCOMPCTL - Locks write access to SDCOMPCTL register
//! - SDFM_SDCOMPLOCK_COMP - Locks write access to SDCOMPxFILCTL &
//!                          SDCOMPxFILCLKCTL register
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_lockCompEventFilterConfig(uint32_t base, SDFM_FilterNumber filterNumber,
                               uint16_t lockConfig)
{
    ;

    //
    // Lock comparator event filter related configurations.
    //
    __eallow();
    (*((volatile uint16_t *)((uintptr_t)(base + 0x67U + ((uint32_t)filterNumber * (0x68U - 0x60U)))))) |= lockConfig;
    __edis();
}

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Configures SDFM comparator for filter config & threshold values
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio.
//! \param config2 is high-level and low-level threshold 1 values.
//! \param config3 is the zero-cross threshold value.
//!
//! This function configures the comparator filter for filter config and
//! threshold values based on provided inputs.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//!   - config1.[3:0]  filter number
//!   - config1.[7:4]  filter type
//!   - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location.
//! For example the value
//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16))
//! will select Filter 1, SINC 2 type with an oversampling ratio of 16.
//!
//! The config2 parameter is the logical OR of the filter high and low
//! threshold 1 values.
//! The bit definitions for config2 are as follow:
//!   - config2.[15:0]  low threshold 1
//!   - config2.[31:16] high threshold 1
//! The upper 16 bits define the high threshold 1 and the lower 16 bits define
//! the low threshold 1. SDFM_THRESHOLD(H,L) can be used to combine the high
//! and low thresholds.
//! The config3 parameter is the logical OR of the zero cross threshold
//! enable flag and the zero-cross threshold value.
//! The bit definitions for config3 are as follow:
//!   - config3.[15] - Enable or disable zero cross threshold. Valid values
//!                    are 1 or 0 to enable or disable the zero cross threshold
//!                    respectively.
//!   -config3.[14:0] - Zero Cross Threshold value.
//! The SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) macro can be used to specify the
//! zero-cross threshold value and OR the 1 to enable it.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configComparator(uint32_t base, uint16_t config1,
                      uint32_t config2, uint16_t config3);

//*****************************************************************************
//
//! Configure SDFM enhanced comparator for filter config & threshold values
//!
//! \param base is the base address of the SDFM module
//! \param filterConfig is the filter number, filter type & over sampling ratio.
//! \param highLowThreshold1 is high-level and low-level threshold 1 values.
//! \param highLowThreshold2 is high-level and low-level threshold 2 values.
//! \param zeroCrossThreshold is the zero-cross threshold value.
//!
//! This function configures the comparator filter for filter config and
//! threshold values based on input parameters.
//!
//! The filterConfig parameter is the logical OR of the filter number, filter
//! type and oversampling ratio.
//! The bit definitions for filterConfig are as follow:
//!   - filterConfig.[3:0]  filter number
//!   - filterConfig.[7:4]  filter type
//!   - filterConfig.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location.
//! For example the value
//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16))
//! will select Filter 1, SINC 2 type with an oversampling ratio of 16.
//!
//! The highLowThreshold1 parameter is the logical OR of the filter high & low
//! threshold 1 values.
//! The bit definitions for highLowThreshold1 are as follow:
//!   - highLowThreshold1.[15:0]  low threshold 1
//!   - highLowThreshold1.[31:16] high threshold 1
//! The upper 16 bits define the high threshold and the lower 16 bits define
//! the low threshold. SDFM_THRESHOLD(H,L) can be used to combine the high and
//! low thresholds.
//!
//! The highLowThreshold2 parameter is the logical OR of the filter high & low
//! threshold 2 values.
//! The bit definitions for highLowThreshold2 are as follow:
//!   - highLowThreshold2.[15:0]  low threshold 2
//!   - highLowThreshold2.[31:16] high threshold 2
//! The upper 16 bits define the high threshold and the lower 16 bits define
//! the low threshold. SDFM_THRESHOLD(H,L) can be used to combine the high &
//! low thresholds.
//!
//! The zeroCrossThreshold parameter is the logical OR of the zero cross
//! threshold enable flag and the zero-cross threshold value. The bit
//! definitions for zeroCrossThreshold are as follows:
//!   - zeroCrossThreshold.[15] - Enable or disable zero cross threshold. Valid
//!     values are 1 or 0 to enable or disable the zero cross threshold
//!     respectively.
//!   - zeroCrossThreshold.[14:0] - Zero Cross Threshold value.
//! The SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) macro can be used as parameter
//! zeroCrossThreshold to enable & specify the zero-cross threshold value.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configEnhancedComparator(uint32_t base, uint16_t filterConfig,
                              uint32_t highLowThreshold1,
                              uint32_t highLowThreshold2,
                              uint16_t zeroCrossThreshold);

//*****************************************************************************
//
//! Configure SDFM data filter
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio
//!                configuration.
//! \param config2 is filter switch, data representation and data shift values
//!                configuration.
//!
//! This function configures the data filter based on configurations
//! config1 and config2.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//!   - config1.[3:0]  Filter number
//!   - config1.[7:4]  Filter type
//!   - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio , which ranges [1,256] inclusive , in the appropriate bit location
//! for config1. For example the value
//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64))
//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64.
//!
//! The config2 parameter is the logical OR of data representation, filter
//! switch, and data shift values
//! The bit definitions for config2 are as follow:
//!   - config2.[0]  Data representation
//!   - config2.[1]  Filter switch
//!   - config2.[15:2]  Shift values
//! Valid values for data representation are given in SDFM_OutputDataFormat
//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the
//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value
//! of the data shift value,which ranges [0,31] inclusive, in the appropriate
//! bit location for config2.
//! The shift value is valid only in SDFM_DATA_FORMAT_16_BIT data
//! representation format.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2);

//*****************************************************************************
//
//! Configure SDFM comparator Zero Cross threshold
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio.
//! \param config2 is the zero cross threshold value.
//!
//! This function configures the comparator filter zero cross threshold values
//! based on configurations config1 and config2.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//!   - config1.[3:0]  filter number
//!   - config1.[7:4]  filter type
//!   - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location.
//! For example the value
//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16))
//! will select Filter 1 , SINC 2 type with an oversampling ratio of 16.
//!
//! The config2 parameter is the value of the zero cross threshold. The maximum
//! acceptable value is 32767.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configZeroCrossComparator(uint32_t base, uint16_t config1,
                               uint16_t config2);

//*****************************************************************************
//
//! Configure SDFM data filter FIFO
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio
//!                configuration.
//! \param config2 is filter switch, data representation and data shift values
//!                and FIFO level configuration.
//!
//! This function enables and configures the data filter FIFO based on
//! configurations config1 and config2.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//!   - config1.[3:0]  filter number
//!   - config1.[7:4]  filter type
//!   - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio , which ranges [1,256] inclusive , in the appropriate bit location
//! for config1. For example the value
//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64))
//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64.
//!
//! The config2 parameter is the logical OR of data representation, filter
//! switch, data shift value, and FIFO level
//! The bit definitions for config2 are as follow:
//!   - config2.[0]  Data representation
//!   - config2.[1]  filter switch.
//!   - config2.[6:2]  shift values.
//!   - config2.[15:7] FIFO level
//! Valid values for data representation are given in SDFM_OutputDataFormat
//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the
//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value
//! of the data shift value,which ranges [0,31] inclusive, in the appropriate
//! bit location for config2.
//! The value of FIFO level ranges [1,16] inclusive. The macro
//! SDFM_SET_FIFO_LEVEL(X) can be used to set the value of the FIFO level.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configDataFilterFIFO(uint32_t base, uint16_t config1, uint16_t config2);

//*****************************************************************************
//
//! Configure Comparator Event Low Filter
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param config is the comparator event low source
//!
//! This function configures the sample window, threshold and clock prescale
//! configurations for the comparator event low filter.
//!
//! \return None.
//
//*****************************************************************************
extern void
SDFM_configCompEventLowFilter(uint32_t base, SDFM_FilterNumber filterNumber,
                              const SDFM_CompEventFilterConfig *config);

//*****************************************************************************
//
//! Configure Comparator Event High Filter
//!
//! \param base is the base address of the SDFM module.
//! \param filterNumber is the filter number.
//! \param config is the comparator event high source
//!
//! This function configures the sample window, threshold and clock prescale
//! configurations for the comparator event high filter.
//!
//! \return None.
//
//*****************************************************************************
extern void
SDFM_configCompEventHighFilter(uint32_t base, SDFM_FilterNumber filterNumber,
                               const SDFM_CompEventFilterConfig *config);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE:   spi.h
//
// TITLE:  C28x SPI driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup spi_api SPI
//! \brief This module is used for SPI configurations.
//! @{
//
//*****************************************************************************

//###########################################################################
//
// FILE:    hw_spi.h
//
// TITLE:   Definitions for the SPI registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*************************************************************************************************
//
// The following are defines for the SPI register offsets
//
//*************************************************************************************************


//*************************************************************************************************
//
// The following are defines for the bit fields in the SPICCR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPICTL register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPISTS register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIBRR register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFTX register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFRX register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFCT register
//
//*************************************************************************************************

//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIPRI register
//
//*************************************************************************************************




//*****************************************************************************
//
// Values that can be passed to SPI_enableInterrupt(), SPI_disableInterrupt(),
// and SPI_clearInterruptStatus() as the intFlags parameter, and returned by
// SPI_getInterruptStatus().
//
//*****************************************************************************


//*****************************************************************************
//
//! This macro definition is used to transmit a byte of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//!
//! This macro definition is to transmit a byte of data.
//! This macro uses SPI_pollingNonFIFOTransaction function
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro definition is used to transmit a 16-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//!
//! This macro definition is to transmit a 16-bit word of data.
//! This macro uses SPI_pollingNonFIFOTransaction function
//! SPI character length is hardcoded to 16 (16bit word) of character length
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro definition can be used to transmit 'N' bytes of data
//!
//! \param base specifies the SPI module base address.
//! \param txBuffer is the transmit buffer to be transmitted over SPI
//! \param numOfWords is the number of bytes to be transmitted
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This macro definition can be used to transmit 'N' bytes of data.
//! This macro definition uses SPI_pollingFIFOTransaction function.
//!
//! SPI character length is hardcoded to 8 (8bits) of character length
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro definition can be used to transmit 'N' 16-bit words of data
//!
//! \param base specifies the SPI module base address.
//! \param txBuffer is the transmit buffer to be transmitted over SPI
//! \param numOfWords is the number of 16-bit word to be transmitted
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function can be used to transmit 'N' 16-bit words of data.
//! This function uses SPI_pollingFIFOTransaction function.
//! SPI character length is hardcoded to 16 (16-bit word)
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro definition can be used to transmit 'N' with configurable
//! SPI character length
//!
//! \param base specifies the SPI module base address
//! \param charLength specifies the SPI character length
//! \param txBuffer is the transmit buffer to be transmitted over SPI
//! \param numOfWords is the number of 16-bit word to be transmitted
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This macro definition can be used to transmit 'N' with configurable
//! SPI character length.
//!
//! This macro uses SPIpolling_FIFO_Transaction function.
//! SPI character length is configurable using charLength variable.
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro definition is used to receive a byte of data
//!
//! \param base specifies the SPI module base address.
//! \param dummyData is the data which is transmitted to initiate
//!        SPI transaction to receive SPI data
//!
//! This macro definition is to receive a byte of data.
//! This macro uses SPI_pollingNonFIFOTransaction function
//! SPI character length is hardcoded to 8 (1byte = 8bits) of character length
//!
//! \return the received byte.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro is used to receive 'N' bytes of data
//!
//! \param base specifies the SPI module base address.
//! \param rxBuffer specifies receive buffer which will store the received bytes
//! \param numOfWords specifies the number of bytes to be received
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function is used to receive 'N' bytes of data
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro is used to receive 'N' 16-bits words of data
//!
//! \param base specifies the SPI module base address.
//! \param rxBuffer specifies receive buffer which will store the received bytes
//! \param numOfWords specifies the number of 16-bit words to be received
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function is used to receive 'N' 16-bit words of data
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 16bits
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! This macro is used to receive 'N' words with specified character length
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the SPI character length of SPI transaction
//! \param rxBuffer specifies receive buffer which will store the received bytes
//! \param numOfWords specifies the number of words with specified character
//!        length
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function is used to receive 'N' words with specified character length
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is configurable using charLength variable
//!
//! \return None.
//
//*****************************************************************************

//*****************************************************************************
//
//! Values that can be passed to SPI_setConfig() as the \e protocol parameter.
//
//*****************************************************************************
typedef enum
{
    //! Mode 0. Polarity 0, phase 0. Rising edge without delay.
    SPI_PROT_POL0PHA0   = 0x0000U,
    //! Mode 1. Polarity 0, phase 1. Rising edge with delay.
    SPI_PROT_POL0PHA1   = 0x0002U,
    //! Mode 2. Polarity 1, phase 0. Falling edge without delay.
    SPI_PROT_POL1PHA0   = 0x0001U,
    //! Mode 3. Polarity 1, phase 1. Falling edge with delay.
    SPI_PROT_POL1PHA1   = 0x0003U
} SPI_TransferProtocol;

//*****************************************************************************
//
//! Values that can be passed to SPI_setConfig() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
    SPI_MODE_SLAVE     = 0x0002U,   //!< SPI slave
    SPI_MODE_MASTER    = 0x0006U,   //!< SPI master
    SPI_MODE_SLAVE_OD  = 0x0000U,   //!< SPI slave w/ output (TALK) disabled
    SPI_MODE_MASTER_OD = 0x0004U    //!< SPI master w/ output (TALK) disabled
} SPI_Mode;

//*****************************************************************************
//
//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e txLevel
//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e txLevel
//! parameter, and returned by SPI_getTxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
    SPI_FIFO_TXEMPTY    = 0x0000U,      //!< Transmit FIFO empty
    SPI_FIFO_TX0        = 0x0000U,      //!< Transmit FIFO empty
    SPI_FIFO_TX1        = 0x0001U,      //!< Transmit FIFO 1/16 full
    SPI_FIFO_TX2        = 0x0002U,      //!< Transmit FIFO 2/16 full
    SPI_FIFO_TX3        = 0x0003U,      //!< Transmit FIFO 3/16 full
    SPI_FIFO_TX4        = 0x0004U,      //!< Transmit FIFO 4/16 full
    SPI_FIFO_TX5        = 0x0005U,      //!< Transmit FIFO 5/16 full
    SPI_FIFO_TX6        = 0x0006U,      //!< Transmit FIFO 6/16 full
    SPI_FIFO_TX7        = 0x0007U,      //!< Transmit FIFO 7/16 full
    SPI_FIFO_TX8        = 0x0008U,      //!< Transmit FIFO 8/16 full
    SPI_FIFO_TX9        = 0x0009U,      //!< Transmit FIFO 9/16 full
    SPI_FIFO_TX10       = 0x000AU,      //!< Transmit FIFO 10/16 full
    SPI_FIFO_TX11       = 0x000BU,      //!< Transmit FIFO 11/16 full
    SPI_FIFO_TX12       = 0x000CU,      //!< Transmit FIFO 12/16 full
    SPI_FIFO_TX13       = 0x000DU,      //!< Transmit FIFO 13/16 full
    SPI_FIFO_TX14       = 0x000EU,      //!< Transmit FIFO 14/16 full
    SPI_FIFO_TX15       = 0x000FU,      //!< Transmit FIFO 15/16 full
    SPI_FIFO_TX16       = 0x0010U,      //!< Transmit FIFO full
    SPI_FIFO_TXFULL     = 0x0010U       //!< Transmit FIFO full
} SPI_TxFIFOLevel;

//*****************************************************************************
//
//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e rxLevel
//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e rxLevel
//! parameter, and returned by SPI_getRxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
    SPI_FIFO_RXEMPTY    = 0x0000U,      //!< Receive FIFO empty
    SPI_FIFO_RX0        = 0x0000U,      //!< Receive FIFO empty
    SPI_FIFO_RX1        = 0x0001U,      //!< Receive FIFO 1/16 full
    SPI_FIFO_RX2        = 0x0002U,      //!< Receive FIFO 2/16 full
    SPI_FIFO_RX3        = 0x0003U,      //!< Receive FIFO 3/16 full
    SPI_FIFO_RX4        = 0x0004U,      //!< Receive FIFO 4/16 full
    SPI_FIFO_RX5        = 0x0005U,      //!< Receive FIFO 5/16 full
    SPI_FIFO_RX6        = 0x0006U,      //!< Receive FIFO 6/16 full
    SPI_FIFO_RX7        = 0x0007U,      //!< Receive FIFO 7/16 full
    SPI_FIFO_RX8        = 0x0008U,      //!< Receive FIFO 8/16 full
    SPI_FIFO_RX9        = 0x0009U,      //!< Receive FIFO 9/16 full
    SPI_FIFO_RX10       = 0x000AU,      //!< Receive FIFO 10/16 full
    SPI_FIFO_RX11       = 0x000BU,      //!< Receive FIFO 11/16 full
    SPI_FIFO_RX12       = 0x000CU,      //!< Receive FIFO 12/16 full
    SPI_FIFO_RX13       = 0x000DU,      //!< Receive FIFO 13/16 full
    SPI_FIFO_RX14       = 0x000EU,      //!< Receive FIFO 14/16 full
    SPI_FIFO_RX15       = 0x000FU,      //!< Receive FIFO 15/16 full
    SPI_FIFO_RX16       = 0x0010U,      //!< Receive FIFO full
    SPI_FIFO_RXFULL     = 0x0010U,      //!< Receive FIFO full
    SPI_FIFO_RXDEFAULT  = 0x001FU       //!< To prevent interrupt at reset
} SPI_RxFIFOLevel;

//*****************************************************************************
//
//! Values that can be passed to SPI_setEmulationMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
    //! Transmission stops after midway in the bit stream
    SPI_EMULATION_STOP_MIDWAY         = 0x0000U,
    //! Continue SPI operation regardless
    SPI_EMULATION_FREE_RUN            = 0x0010U,
    //! Transmission will stop after a started transmission completes
    SPI_EMULATION_STOP_AFTER_TRANSMIT = 0x0020U
} SPI_EmulationMode;

//*****************************************************************************
//
//! Values that can be passed to SPI_setSTESignalPolarity() as the \e polarity
//! parameter.
//
//*****************************************************************************
typedef enum
{
    SPI_STE_ACTIVE_LOW  = 0x0000U,        //!< SPISTE is active low (normal)
    SPI_STE_ACTIVE_HIGH = 0x2U  //!< SPISTE is active high (inverted)
} SPI_STEPolarity;

//*****************************************************************************
//
//! Values that can be passed to SPI_receive16Bits(), SPI_receive24Bits(),
//! SPI_receive32Bits()
//
//*****************************************************************************
typedef enum
{
    SPI_DATA_LITTLE_ENDIAN   = 0U, //!< LITTLE ENDIAN
    SPI_DATA_BIG_ENDIAN   = 1U,    //!< BIG ENDIAN
} SPI_endianess;

//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an SPI base address.
//!
//! \param base specifies the SPI module base address.
//!
//! This function determines if a SPI module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************

//*****************************************************************************
//
//! Enables the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//!
//! This function enables operation of the serial peripheral interface.  The
//! serial peripheral interface must be configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x80U;
}

//*****************************************************************************
//
//! Disables the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//!
//! This function disables operation of the serial peripheral interface. Call
//! this function before doing any configuration.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableModule(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~(0x80U);
}

//*****************************************************************************
//
//! Sets the character length of SPI transaction
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the character length of SPI transaction
//!
//! This function configures the character length of SPI transaction.
//! SPI character length can be from anywhere between 1-bit word to 16 bit word
//! of character length
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setcharLength(uint32_t base, uint16_t charLength)
{
    ;
    SPI_disableModule(base);
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) & ~0xFU) |
                               (charLength - 1U);
    SPI_enableModule(base);
}


//*****************************************************************************
//
//! Enables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SPI port.
//!
//! This functions enables the transmit and receive FIFOs in the SPI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Enable the FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x4000U | 0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Disables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SPI port.
//!
//! This functions disables the transmit and receive FIFOs in the SPI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Disable the FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~(0x4000U | 0x2000U);
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &= ~0x2000U;
}

//*****************************************************************************
//
//! Resets the transmit FIFO.
//!
//! \param base is the base address of the SPI port.
//!
//! This function resets the transmit FIFO, setting the FIFO pointer back to
//! zero.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_resetTxFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Reset the TX FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Resets the receive FIFO.
//!
//! \param base is the base address of the SPI port.
//!
//! This function resets the receive FIFO, setting the FIFO pointer back to
//! zero.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_resetRxFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Reset the RX FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &= ~0x2000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) |= 0x2000U;
}

//*****************************************************************************
//
//! Sets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the SPI port.
//! \param txLevel is the transmit FIFO interrupt level, specified as
//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, . . . or
//! \b SPI_FIFO_TX16.
//! \param rxLevel is the receive FIFO interrupt level, specified as
//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, . . . or
//! \b SPI_FIFO_RX16.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel txLevel,
                          SPI_RxFIFOLevel rxLevel)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the FIFO interrupt levels.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &
                                 (~0x1FU)) | (uint16_t)txLevel;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &
                                 (~0x1FU)) | (uint16_t)rxLevel;
}

//*****************************************************************************
//
//! Gets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the SPI port.
//! \param txLevel is a pointer to storage for the transmit FIFO level,
//! returned as one of \b SPI_FIFO_TX0, \b SPI_FIFO_TX1,
//! \b SPI_FIFO_TX2, . . . or \b SPI_FIFO_TX16.
//! \param rxLevel is a pointer to storage for the receive FIFO level,
//! returned as one of \b SPI_FIFO_RX0, \b SPI_FIFO_RX1,
//! \b SPI_FIFO_RX2, . . . or \b SPI_FIFO_RX16.
//!
//! This function gets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_getFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel *txLevel,
                          SPI_RxFIFOLevel *rxLevel)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Extract the transmit and receive FIFO levels.
    //
    *txLevel = (SPI_TxFIFOLevel)((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &
                                 0x1FU);
    *rxLevel = (SPI_RxFIFOLevel)((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) &
                                 0x1FU);
}

//*****************************************************************************
//
//! Get the transmit FIFO status
//!
//! \param base is the base address of the SPI port.
//!
//! This function gets the current number of words in the transmit FIFO.
//!
//! \return Returns the current number of words in the transmit FIFO specified
//! as one of the following:
//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, \b SPI_FIFO_TX3,
//! ..., or \b SPI_FIFO_TX16
//
//*****************************************************************************
static inline SPI_TxFIFOLevel
SPI_getTxFIFOStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the current FIFO status
    //
    return((SPI_TxFIFOLevel)(((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) & 0x1F00U) >>
                             8U));
}

//*****************************************************************************
//
//! Get the receive FIFO status
//!
//! \param base is the base address of the SPI port.
//!
//! This function gets the current number of words in the receive FIFO.
//!
//! \return Returns the current number of words in the receive FIFO specified
//! as one of the following:
//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, \b SPI_FIFO_RX3,
//! ..., or \b SPI_FIFO_RX16
//
//*****************************************************************************
static inline SPI_RxFIFOLevel
SPI_getRxFIFOStatus(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Get the current FIFO status
    //
    return((SPI_RxFIFOLevel)(((*((volatile uint16_t *)((uintptr_t)(base + 0xBU)))) & 0x1F00U) >>
                             8U));
}

//*****************************************************************************
//
//! Determines whether the SPI transmitter is busy or not.
//!
//! \param base is the base address of the SPI port.
//!
//! This function allows the caller to determine whether all transmitted bytes
//! have cleared the transmitter hardware.  If \b false is returned, then the
//! transmit FIFO is empty and all bits of the last transmitted word have left
//! the hardware shift register. This function is only valid when operating in
//! FIFO mode.
//!
//! \return Returns \b true if the SPI is transmitting or \b false if all
//! transmissions are complete.
//
//*****************************************************************************
static inline _Bool
SPI_isBusy(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Determine if the SPI is busy.
    //
    return(((*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) & 0x1F00U) != 0U);
}

//*****************************************************************************
//
//! Puts a data element into the SPI transmit buffer.
//!
//! \param base specifies the SPI module base address.
//! \param data is the left-justified data to be transmitted over SPI.
//!
//! This function places the supplied data into the transmit buffer of the
//! specified SPI module.
//!
//! \note The data being sent must be left-justified in \e data. The lower
//! 16 - N bits will be discarded where N is the data width selected in
//! SPI_setConfig(). For example, if configured for a 6-bit data width, the
//! lower 10 bits of data will be discarded.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_writeDataNonBlocking(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write data to the transmit buffer.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) = data;
}

//*****************************************************************************
//
//! Gets a data element from the SPI receive buffer.
//!
//! \param base specifies the SPI module base address.
//!
//! This function gets received data from the receive buffer of the specified
//! SPI module and returns it.
//!
//! \note Only the lower N bits of the value written to \e data contain valid
//! data, where N is the data width as configured by SPI_setConfig(). For
//! example, if the interface is configured for 8-bit data width, only the
//! lower 8 bits of the value written to \e data contain valid data.
//!
//! \return Returns the word of data read from the SPI receive buffer.
//
//*****************************************************************************
static inline uint16_t
SPI_readDataNonBlocking(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Check for data to read.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))));
}

//*****************************************************************************
//
//! Waits for space in the FIFO and then puts data into the transmit buffer.
//!
//! \param base specifies the SPI module base address.
//! \param data is the left-justified data to be transmitted over SPI.
//!
//! This function places the supplied data into the transmit buffer of the
//! specified SPI module once space is available in the transmit FIFO. This
//! function should only be used when the FIFO is enabled.
//!
//! \note The data being sent must be left-justified in \e data. The lower
//! 16 - N bits will be discarded where N is the data width selected in
//! SPI_setConfig(). For example, if configured for a 6-bit data width, the
//! lower 10 bits of data will be discarded.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until space is available in the receive FIFO.
    //
    while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL)
    {
    }

    //
    // Write data to the transmit buffer.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) = data;
}

//*****************************************************************************
//
//! Waits for data in the FIFO and then reads it from the receive buffer.
//!
//! \param base specifies the SPI module base address.
//!
//! This function waits until there is data in the receive FIFO and then reads
//! received data from the receive buffer.  This function should only be used
//! when FIFO mode is enabled.
//!
//! \note Only the lower N bits of the value written to \e data contain valid
//! data, where N is the data width as configured by SPI_setConfig(). For
//! example, if the interface is configured for 8-bit data width, only the
//! lower 8 bits of the value written to \e data contain valid data.
//!
//! \return Returns the word of data read from the SPI receive buffer.
//
//*****************************************************************************
static inline uint16_t
SPI_readDataBlockingFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until data is available in the receive FIFO.
    //
    while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY)
    {
    }

    //
    // Check for data to read.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))));
}

//*****************************************************************************
//
//! Waits for the transmit buffer to empty and then writes data to it.
//!
//! \param base specifies the SPI module base address.
//! \param data is the left-justified data to be transmitted over SPI.
//!
//! This function places the supplied data into the transmit buffer of the
//! specified SPI module once it is empty. This function should not be used
//! when FIFO mode is enabled.
//!
//! \note The data being sent must be left-justified in \e data. The lower
//! 16 - N bits will be discarded where N is the data width selected in
//! SPI_setConfig(). For example, if configured for a 6-bit data width, the
//! lower 10 bits of data will be discarded.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_writeDataBlockingNonFIFO(uint32_t base, uint16_t data)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until the transmit buffer is not full.
    //
    while(((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) & 0x20U) != 0U)
    {
    }

    //
    // Write data to the transmit buffer.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x8U)))) = data;
}

//*****************************************************************************
//
//! Waits for data to be received and then reads it from the buffer.
//!
//! \param base specifies the SPI module base address.
//!
//! This function waits for data to be received and then reads it from the
//! receive buffer of the specified SPI module. This function should not be
//! used when FIFO mode is enabled.
//!
//! \note Only the lower N bits of the value written to \e data contain valid
//! data, where N is the data width as configured by SPI_setConfig(). For
//! example, if the interface is configured for 8-bit data width, only the
//! lower 8 bits of the value written to \e data contain valid data.
//!
//! \return Returns the word of data read from the SPI receive buffer.
//
//*****************************************************************************
static inline uint16_t
SPI_readDataBlockingNonFIFO(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Wait until data has been received.
    //
    while(((*((volatile uint16_t *)((uintptr_t)(base + 0x2U)))) & 0x40U) == 0U)
    {
    }

    //
    // Check for data to read.
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x7U)))));
}

//*****************************************************************************
//
//! Enables SPI 3-wire mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function enables 3-wire mode. When in master mode, this allows SPISIMO
//! to become SPIMOMI and SPISOMI to become free for non-SPI use. When in slave
//! mode, SPISOMI because the SPISISO pin and SPISIMO is free for non-SPI use.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableTriWire(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the tri-wire bit to enable 3-wire mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) |= 0x1U;
}

//*****************************************************************************
//
//! Disables SPI 3-wire mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function disables 3-wire mode. SPI will operate in normal 4-wire mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableTriWire(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the tri-wire bit to disable 3-wire mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) &= ~0x1U;
}

//*****************************************************************************
//
//! Enables SPI loopback mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function enables loopback mode. This mode is only valid during master
//! mode and is helpful during device testing as it internally connects SIMO
//! and SOMI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that enables loopback mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x10U;
}

//*****************************************************************************
//
//! Disables SPI loopback mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function disables loopback mode. Loopback mode is disabled by default
//! after reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableLoopback(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the bit that enables loopback mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x10U;
}

//*****************************************************************************
//
//! Set the slave select (SPISTE) signal polarity.
//!
//! \param base is the base address of the SPI port.
//! \param polarity is the SPISTE signal polarity.
//!
//! This function sets the polarity of the slave select (SPISTE) signal. The
//! two modes to choose from for the \e polarity parameter are
//! \b SPI_STE_ACTIVE_LOW for active-low polarity (typical) and
//! \b SPI_STE_ACTIVE_HIGH for active-high polarity (considered inverted).
//!
//! \note This has no effect on the STE signal when in master mode. It is only
//! applicable to slave mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setSTESignalPolarity(uint32_t base, SPI_STEPolarity polarity)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the polarity of the SPISTE signal to the register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) & ~0x2U) |
                               (uint16_t)polarity;
}

//*****************************************************************************
//
//! Enables SPI high speed mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function enables high speed mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableHighSpeedMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the bit that enables high speed mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) |= 0x20U;
}

//*****************************************************************************
//
//! Disables SPI high speed mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function disables high speed mode. High speed mode is disabled by
//! default after reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableHighSpeedMode(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Clear the bit that enables high speed mode.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x0U)))) &= ~0x20U;
}

//*****************************************************************************
//
//! Sets SPI emulation mode.
//!
//! \param base is the base address of the SPI port.
//! \param mode is the emulation mode.
//!
//! This function sets the behavior of the SPI operation when an emulation
//! suspend occurs. The \e mode parameter can be one of the following:
//!
//! - \b SPI_EMULATION_STOP_MIDWAY - Transmission stops midway through the bit
//!   stream. The rest of the bits will be transmitting after the suspend is
//!   deasserted.
//! - \b SPI_EMULATION_STOP_AFTER_TRANSMIT - If the suspend occurs before the
//!   first SPICLK pulse, the transmission will not start. If it occurs later,
//!   the transmission will be completed.
//! - \b SPI_EMULATION_FREE_RUN - SPI operation continues regardless of a
//!   the suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setEmulationMode(uint32_t base, SPI_EmulationMode mode)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write the desired emulation mode to the register.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) = ((*((volatile uint16_t *)((uintptr_t)(base + 0xFU)))) &
                                ~(0x10U | 0x20U)) |
                               (uint16_t)mode;
}

//*****************************************************************************
//
//! Configures the FIFO Transmit Delay
//!
//! \param base is the base address of the SPI port.
//! \param delay Tx FIFO delay to be configured in cycles (0..0xFF)
//!
//! This function sets the delay between every transfer from FIFO
//! transmit buffer to transmit shift register. The delay is defined in
//! number SPI serial clock cycles.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_setTxFifoTransmitDelay(uint32_t base, uint16_t delay)
{
    //
    // Check the arguments.
    //
    ;
    ;

    //
    // Configure the FIFO Transmit Delay Bits
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xCU)))) = delay;
}

//*****************************************************************************
//
//! Returns the Emulation Buffer Received Data
//!
//! \param base is the base address of the SPI port.
//!
//! This function returns the Emulation Buffer Received Data
//!
//! \return Rx emulation buffer data
//
//*****************************************************************************
static inline uint16_t
SPI_readRxEmulationBuffer(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Return Emulation Buffer Received Data
    //
    return((*((volatile uint16_t *)((uintptr_t)(base + 0x6U)))));
}

//*****************************************************************************
//
//! Enable Trasnmit
//!
//! \param base is the base address of the SPI port.
//!
//! This function sets the TALK bit enabling the data trasnmission.
//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as
//! SPI_MODE_SLAVE or SPI_MODE_MASTER.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_enableTalk(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the TALK bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) |= 0x2U;
}

//*****************************************************************************
//
//! Disable Trasnmit
//!
//! \param base is the base address of the SPI port.
//!
//! This function clears the TALK bit disabling the data trasnmission. The
//! output pin will be put in high-impedance state.
//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as
//! SPI_MODE_SLAVE or SPI_MODE_MASTER.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_disableTalk(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Set the TALK bit
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0x1U)))) &= ~0x2U;
}

//*****************************************************************************
//
//! Reset SPI transmit and receive channels
//!
//! \param base is the base address of the SPI port.
//!
//! This function resets the SPI transmit and receive channels.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_reset(uint32_t base)
{
    //
    // Check the arguments.
    //
    ;

    //
    // Write to SPRST bit the TX FIFO.
    //
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) &= ~0x8000U;
    (*((volatile uint16_t *)((uintptr_t)(base + 0xAU)))) |= 0x8000U;
}

//*****************************************************************************
//
//! Configures the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//! \param lspclkHz is the rate of the clock supplied to the SPI module
//! (LSPCLK) in Hz.
//! \param protocol specifies the data transfer protocol.
//! \param mode specifies the mode of operation.
//! \param bitRate specifies the clock rate in Hz.
//! \param dataWidth specifies number of bits transferred per frame.
//!
//! This function configures the serial peripheral interface.  It sets the SPI
//! protocol, mode of operation, bit rate, and data width.
//!
//! The \e protocol parameter defines the data frame format.  The \e protocol
//! parameter can be one of the following values: \b SPI_PROT_POL0PHA0,
//! \b SPI_PROT_POL0PHA1, \b SPI_PROT_POL1PHA0, or
//! \b SPI_PROT_POL1PHA1. These frame formats encode the following polarity
//! and phase configurations:
//!
//! <pre>
//! Polarity Phase       Mode
//!   0       0   SPI_PROT_POL0PHA0
//!   0       1   SPI_PROT_POL0PHA1
//!   1       0   SPI_PROT_POL1PHA0
//!   1       1   SPI_PROT_POL1PHA1
//! </pre>
//!
//! The \e mode parameter defines the operating mode of the SPI module.  The
//! SPI module can operate as a master or slave; the SPI can also be be
//! configured to disable output on its serial output line.  The \e mode
//! parameter can be one of the following values: \b SPI_MODE_MASTER,
//! \b SPI_MODE_SLAVE, \b SPI_MODE_MASTER_OD or \b SPI_MODE_SLAVE_OD ("OD"
//! indicates "output disabled").
//!
//! The \e bitRate parameter defines the bit rate for the SPI.  This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - \e bitRate can be no greater than lspclkHz divided by 4.
//! - \e lspclkHz / \e bitRate cannot be greater than 128.
//!
//! The \e dataWidth parameter defines the width of the data transfers and
//! can be a value between 1 and 16, inclusive.
//!
//! The peripheral clock is the low speed peripheral clock.  This value is
//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtl_getLowSpeedClock()).
//!
//! \note SPI operation should be disabled via SPI_disableModule() before any
//! changes to its configuration.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol,
              SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth);

//*****************************************************************************
//
//! Configures the baud rate of the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//! \param lspclkHz is the rate of the clock supplied to the SPI module
//! (LSPCLK) in Hz.
//! \param bitRate specifies the clock rate in Hz.
//!
//! This function configures the SPI baud rate. The \e bitRate parameter
//! defines the bit rate for the SPI.  This bit rate must satisfy the following
//! clock ratio criteria:
//!
//! - \e bitRate can be no greater than \e lspclkHz divided by 4.
//! - \e lspclkHz / \e bitRate cannot be greater than 128.
//!
//! The peripheral clock is the low speed peripheral clock.  This value is
//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtl_getLowSpeedClock()).
//!
//! \note SPI_setConfig() also sets the baud rate. Use SPI_setBaudRate()
//! if you wish to configure it separately from protocol and mode.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate);

//*****************************************************************************
//
//! Enables individual SPI interrupt sources.
//!
//! \param base specifies the SPI module base address.
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated SPI interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.  The \e intFlags parameter can be
//! any of the following values:
//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt
//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty
//! - \b SPI_INT_RXFF (also enables \b SPI_INT_RXFF_OVERFLOW) - RX FIFO level
//!   interrupt (and RX FIFO overflow)
//! - \b SPI_INT_TXFF - TX FIFO level interrupt
//!
//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY,
//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with
//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_enableInterrupt(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Disables individual SPI interrupt sources.
//!
//! \param base specifies the SPI module base address.
//! \param intFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated SPI interrupt sources.  The
//! \e intFlags parameter can be any of the following values:
//! - \b SPI_INT_RX_OVERRUN
//! - \b SPI_INT_RX_DATA_TX_EMPTY
//! - \b SPI_INT_RXFF (also disables \b SPI_INT_RXFF_OVERFLOW)
//! - \b SPI_INT_TXFF
//!
//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY,
//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with
//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_disableInterrupt(uint32_t base, uint32_t intFlags);

//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param base specifies the SPI module base address.
//!
//! This function returns the interrupt status for the SPI module.
//!
//! \return The current interrupt status, enumerated as a bit field of the
//! following values:
//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt
//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty
//! - \b SPI_INT_RXFF - RX FIFO level interrupt
//! - \b SPI_INT_RXFF_OVERFLOW - RX FIFO overflow
//! - \b SPI_INT_TXFF - TX FIFO level interrupt
//
//*****************************************************************************
extern uint32_t
SPI_getInterruptStatus(uint32_t base);

//*****************************************************************************
//
//! Clears SPI interrupt sources.
//!
//! \param base specifies the SPI module base address.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears the specified SPI interrupt sources so that they no
//! longer assert.  This function must be called in the interrupt handler to
//! keep the interrupts from being triggered again immediately upon exit.  The
//! \e intFlags parameter can consist of a bit field of the following values:
//! - \b SPI_INT_RX_OVERRUN
//! - \b SPI_INT_RX_DATA_TX_EMPTY
//! - \b SPI_INT_RXFF
//! - \b SPI_INT_RXFF_OVERFLOW
//! - \b SPI_INT_TXFF
//!
//! \note \b SPI_INT_RX_DATA_TX_EMPTY is cleared by a read of the receive
//! receive buffer, so it usually doesn't need to be cleared using this
//! function.
//!
//! \note Also note that \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY,
//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with
//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags);


//*****************************************************************************
//
//! This function can be used to transmit a 24-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function can be used to transmit a 24-bit word of data.
//! 24-bit word data is divided into three bytes of data.
//!
//! This function uses SPI_pollingFIFOTransaction function.
//! SPI character length is hardcoded to 8 (8bits) of character length
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay);

//*****************************************************************************
//
//! This function can be used to transmit a 32-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function can be used to transmit a 32-bit word of data.
//! 32-bit word data is divided into four bytes of data.
//!
//! This function uses SPI_pollingFIFOTransaction function.
//! SPI character length is hardcoded to 8 (8bits) of character length
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay);



//*****************************************************************************
//
//! This function is used to receive a 16-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param endianness specifies the endianess of received data
//! \param dummyData is the data which is transmitted to initiate
//!        SPI transaction to receive SPI data
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function is used to receive a 16-bit word of data.
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return the received 16-bit word.
//
//*****************************************************************************
extern uint16_t
SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
                  uint16_t txDelay);

//*****************************************************************************
//
//! This function is used to receive a 24-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param endianness specifies the endianess of received data
//! \param dummyData is the data which is transmitted to initiate
//!        SPI transaction to receive SPI data
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function is used to receive a 24-bit word of data.
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return the received 24-bit word.
//
//*****************************************************************************
extern uint32_t
SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
                  uint16_t txDelay);

//*****************************************************************************
//
//! This function is used to receive a 32-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param endianness specifies the endianess of received data
//! \param dummyData is the data which is transmitted to initiate
//!        SPI transaction to receive SPI data
//! \param txDelay specifies the number of serial clock cycles delay time after
//!        completion of perious word
//!
//! This function is used to receive a 32-bit word of data.
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return the received 32-bit word.
//
//*****************************************************************************
extern uint32_t
SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
                  uint16_t txDelay);



//*****************************************************************************
//
//! This function is used to initiate SPI transaction of specified character
//! length
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the SPI character length of SPI transaction
//! \param data specified the data to be transmitted
//!
//! This function is used to initiate SPI transaction of specified character.
//! SPI character length is configurable using charLength variable
//!
//! \return .
//
//*****************************************************************************
extern uint16_t
SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength,
                              uint16_t data);

//*****************************************************************************
//
//! This function is used to initiate SPI transaction of specified character
//! length and 'N' words of transaction
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the SPI character length of SPI transaction
//! \param pTxBuffer specifies the pointer to transmit buffer
//! \param pRxBuffer specifies the pointer to receive buffer
//! \param numOfWords specified the number of data to be transmitted / received
//!
//! SPI character length is configurable using charLength variable
//!
//! \return none
//
//*****************************************************************************
extern void
SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength,
                           uint16_t *pTxBuffer, uint16_t *pRxBuffer,
                           uint16_t numOfWords, uint16_t txDelay);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************

//###########################################################################
//
// FILE:   version.h
//
// TITLE:  API to return the version number of the driverlib.lib in use.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################


//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup version_api Version
//! @{
//
//*****************************************************************************

//! Version number to be returned by Version_getLibVersion()
//!

//*****************************************************************************
//
//! Returns the driverlib version number
//!
//! This function can be used to check the version number of the driverlib.lib
//! that is in use. The version number will take the format x.xx.xx.xx, so for
//! example, if the function returns 2100200, the driverlib version being used
//! is 2.10.02.00.
//!
//! \return Returns an integer value indicating the driverlib version.
//
//*****************************************************************************
extern uint32_t
Version_getLibVersion(void);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************


//#############################################################################
//
// FILE:   device.h
//
// TITLE:  Device setup for examples.
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################


//
// Included Files
//

//*****************************************************************************
//
// Defines for pin numbers
//
//*****************************************************************************
//
// ControlCARD
//

//
// LEDs
//

//
// CANA
//

//
// SCI for USB-to-UART adapter on FTDI chip
//

//
// MCAN
//

//
// LINA
//

//
// I2C
//

//I2CB GPIO pins


//
// FSI
//


//*****************************************************************************
//
// Defines related to clock configuration
//
//*****************************************************************************

//
// To use INTOSC as the clock source, comment the #define USE_PLL_SRC_XTAL,
// and uncomment the #define USE_PLL_SRC_INTOSC
//
//#define USE_PLL_SRC_INTOSC

//
// 20MHz XTAL on controlCARD. For use with SysCtl_getClock().
// 10MHz INTOSC on the device.
//

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 20MHz (XTAL_OSC) * 48 (IMULT) / (2 (REFDIV) * 4 (ODIV) * 1(SYSDIV))
//

//
// 120MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//


//
// 30MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
// low speed peripheral clock divider of 4. Update the code below if a
// different LSPCLK divider is used!
//

//*****************************************************************************
//
// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
// will convert the desired delay in microseconds to the count value expected
// by the function. \b x is the number of microseconds to delay.
//
//*****************************************************************************

//
//  Defines for setting FSI clock speeds
//

//*****************************************************************************
//
// Defines, Globals, and Header Includes related to Flash Support
//
//*****************************************************************************
/*****************************************************************************/
/* stddef.h                                                                  */
/*                                                                           */
/* Copyright (c) 1993 Texas Instruments Incorporated                         */
/* http://www.ti.com/                                                        */
/*                                                                           */
/*  Redistribution and  use in source  and binary forms, with  or without    */
/*  modification,  are permitted provided  that the  following conditions    */
/*  are met:                                                                 */
/*                                                                           */
/*     Redistributions  of source  code must  retain the  above copyright    */
/*     notice, this list of conditions and the following disclaimer.         */
/*                                                                           */
/*     Redistributions in binary form  must reproduce the above copyright    */
/*     notice, this  list of conditions  and the following  disclaimer in    */
/*     the  documentation  and/or   other  materials  provided  with  the    */
/*     distribution.                                                         */
/*                                                                           */
/*     Neither the  name of Texas Instruments Incorporated  nor the names    */
/*     of its  contributors may  be used to  endorse or  promote products    */
/*     derived  from   this  software  without   specific  prior  written    */
/*     permission.                                                           */
/*                                                                           */
/*  THIS SOFTWARE  IS PROVIDED BY THE COPYRIGHT  HOLDERS AND CONTRIBUTORS    */
/*  "AS IS"  AND ANY  EXPRESS OR IMPLIED  WARRANTIES, INCLUDING,  BUT NOT    */
/*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR    */
/*  A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT    */
/*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,    */
/*  SPECIAL,  EXEMPLARY,  OR CONSEQUENTIAL  DAMAGES  (INCLUDING, BUT  NOT    */
/*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,    */
/*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY    */
/*  THEORY OF  LIABILITY, WHETHER IN CONTRACT, STRICT  LIABILITY, OR TORT    */
/*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE    */
/*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.     */
/*                                                                           */
/*****************************************************************************/



_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */
_Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */
_Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */



typedef long ptrdiff_t;


typedef unsigned long size_t;


typedef unsigned long wchar_t;


/*----------------------------------------------------------------------------*/
/* C++11 and C11 required max_align_t to be defined. The libc++ cstddef       */
/* header expects the macro __DEFINED_max_align_t to be defined if it is to   */
/* use the definintion of max_align_t from stddef.h. Only define it if        */
/* compiling for C11 or we're in non strict ansi mode.                        */
/*----------------------------------------------------------------------------*/
typedef long double max_align_t;

_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.10\")") /* need types as macro arguments */


_Pragma("diag_pop")


_Pragma("diag_pop")


extern uint16_t RamfuncsLoadStart;
extern uint16_t RamfuncsLoadEnd;
extern uint16_t RamfuncsLoadSize;
extern uint16_t RamfuncsRunStart;
extern uint16_t RamfuncsRunEnd;
extern uint16_t RamfuncsRunSize;


//*****************************************************************************
//
// Function Prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup device_api
//! @{
//
//*****************************************************************************

//*****************************************************************************
//
//! @brief Function to initialize the device. Primarily initializes system
//!  control to aknown state by disabling the watchdog, setting up the
//!  SYSCLKOUT frequency, and enabling the clocks to the peripherals.
//!
//! \param None.
//! \return None.
//
//*****************************************************************************
extern void Device_init(void);

//*****************************************************************************
//!
//!
//! @brief Function to turn on all peripherals, enabling reads and writes to the
//! peripherals' registers.
//!
//! Note that to reduce power, unused peripherals should be disabled.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_enableAllPeripherals(void);
//*****************************************************************************
//!
//!
//! @brief Function to disable pin locks on GPIOs.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_initGPIO(void);

//*****************************************************************************
//!
//! @brief Error handling function to be called when an ASSERT is violated
//!
//! @param *filename File name in which the error has occurred
//! @param line Line number within the file
//! @return None
//
//*****************************************************************************
extern void __error__(char *filename, uint32_t line);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//#############################################################################
//
// FILE:   psfbpcmc_settings.h
//
// TITLE:  psfbpcmc_settings.h
//
//#############################################################################
// $TI Release: $
// $Release Date: $
// Copyright (C) {2020} Texas Instruments Incorporated - http://www.ti.com/
// * ALL RIGHTS RESERVED*
//#############################################################################



//*****************************************************************************
//defines
//*****************************************************************************

/* Device Related Defines */

/* Project Options*/
//=============================================================================
// Incremental Build options for System check-out
//=============================================================================
// BUILD 1 	 Open Loop Check
// BUILD 2   Closed Voltage Loop Check

// 1 means control runs on C28x , otherwise it will run on CLA

//Select SR Mode

/* Power Stage Related Values*/




/* Control Loop Design */


//=============================================================================
// User code settings file
//=============================================================================
//#############################################################################
//
// FILE:   psfbpcmc_user_settings.h
//
// TITLE:  psfbpcmc User Settings
//
//#############################################################################
// $TI Release: TIDM_02000 v1.01.01.00 $
// $Release Date: Wed Oct  5 02:42:51 CDT 2022 $
// $Copyright:
// Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
//
// ALL RIGHTS RESERVED
// $
//#############################################################################
//
// Define initial slope
//

//
// 2^16
//

//
// TASK configuration
//


//
// Interrupt related parameters
//

//
// Initial period
//
//#define PSFB_FB_PWM_PERIOD_TICKS (PSFB_PWMSYSCLOCK_FREQ_HZ) / ((float)100*1000*2)
//#define PSFB_FB_PWM_PERIOD_TICKS (PSFB_PWMSYSCLOCK_FREQ_HZ) / ((float)46*1000*2)

//
// Voltage loop control coefficients
//

//
// DB-deadband (us)
//


//
// Board configurations
//
// 230106
// #define PSFB_LED_CCARD1_IO       32
// #define PSFB_LED_CCARD1_IO_CONF  GPIO_32_GPIO32
// #define PSFB_LED_CCARD2_IO       34
// #define PSFB_LED_CCARD2_IO_CONF  GPIO_34_GPIO34

// 230106
//#define PSFB_DEBUG_IO            5
//#define PSFB_DEBUG_IO_CONF       GPIO_5_GPIO5

// 230106 Add GPIO

// EPWM3_A - GPIO Settings
// INPUTXBAR Configurations
// Interrupt Settings for INT_myECAP0


// 230130

// 230130 Cold redundancy PMBus message definition

//230130 12Vmain output port On/Off control

//230130 PWR_OK output port On/Off control




// STB_Protect_MCU_Detection port 

// StandBy Auto-recovery timer relative variables
/*05Nov2014 added to auto-recovery DCmain by STB_prot. consider Only STB protection.*/

//nPS_ON input port Enabled/Disabled check

// AC state



// STB Variable SWITCH

// PSON

// OCP, OCW




// CR
 
/* Threhold to change frome CR STB to CR Active at low line(115V) */

/* Threhold to change frome CR Active to CR STB at low line(115V) */

/* Threhold to change frome CR STB to CR Active at high line(230V) */

/* Threhold to change frome CR Active to CR STB at high line(230V) */

// --PFC OTP Level--

// --SR OTP Level--

// --Ambient OTP Level--

// --PFC OTW Level--

// --SR OTW Level--

// -- Ambient OTW Level--

//Secondary Thermistor

// OTP sensor timer for input noise


// STB voltage

// 12Vmain 



//************************* Cold redundancy Constants ******************************************
// Cold redundancy event definition



// Cold redundancy PMBus message definition
// CRPS 1.20 4.Cold Redundancy

// Pin state definition

//20Mar2013.add CR_Test Issue. before CR mode setting is complete, CR_Bus# is high.

/* CR_CONFIG PIN CONTROL */
/*DCDC active_inactive 0- enable DCDC*/

//============================================================================
// SMBAlert_Setting ()
// CRPS Rev1.24.  1.12	SMBAlert#
// Control a SMBAlert Signal output during changing a mode.
// INPUT   : SMBAlert_Mode, Delay_SMBAlert_ms
// OUTPUT  : nSMB_Alert
//============================================================================
// SMBAlert_Setting module has the below 5 state 
//24Jan2014. SMBAlert Glitch of Supermicro issue.1+1 Redundant state. first 1 AC cycle and 3~4 sec then normal AC input.
//Glitch of SMBAlert at fast AC Recycling test.
//nSMB_Alert output port On/Off control
// SMBAlert control for OPP
//07Oct2014. nSMBAlert_SmaRT input Enable/Disabled.

// LED output port On/Off control

// Ignore_LS High/Low Control for LTC6102 // SH 2 180417


// Operating sequence

// LOAD_20PCNT_OVER output port On/Off control 28July2015.

// LOAD_60PCNT_OVER output port On/Off control

// FAN Duty control definition
// Fan duty controlled by over temperature
// NTC sensor, temperature sensor's voltage is decreased when temperature is increased.
// 190218 not used#define I_HIGH_THRESHOLD_UNDER_0RPM		702  //03July2013 Not used.   2012.01.19 SET LEVEL(2.248V) ORG 564(1.8V) // 3.5[A]

//LED control



// 19Oct2015. Low line  To prohibit PFC OTP @ low line.

//
// ADC configuration
//

//
// XBAR MUX initialization
//

//
// CMPSS initialization
//


// ADC MODULE A

// LVBUS, 12Vmain_BOR
//#define PSFB_LVBUS_ADC_PIN               ADC_CH_ADCIN0



// IHV-FB 

// 12VLS sensing

// TSR sensing

// 12VRS_P sensing


// ADC MODULE B
// Output current sensing Heavy

// Output current sensing Light

// 12VSB_BOR sensing

// ISTB sensing

// A0 sensing

// Output current sensing Fast

// ADC MODULE C

// LS sensing

// Ambient temp. sensing

// 12VRS_N sensing

// 12VSB_AOR sensing

// PSON sensing



// CMPSS 


//
// PWM pin, ADC, SDFM, Relay Selection related variables
//










// 230224 not used #define PSFB_DEBUG_PWM_BASE                      EPWM6_BASE

//#define PSFB_SR_DEADBAND_RED_INITIAL     28                // SR Deadtime initiall
//#define PSFB_SR_DEADBAND_FED_INITIAL     28



//
// SFRA freq
//

//
// SFRA Options
//

//
// SFRA related
//



//
// if the following #define is set to 1 SFRA GUI indicates status on an LED
// otherwise LED code is ignored
//

//
// Add any system specific setting below
//

//
//SFRA step Multiply = 10^(1/No of steps per decade(40))
//

// 230128 UART
// UART Data transfer's Order 




typedef struct
{
//    unsigned char PrimaryMCU_Status;
//    struct
//    {
        unsigned char cmd					;
        unsigned char Tx_count				;
        unsigned char PWOK_deassert_low		;
        unsigned char PWOK_deassert_high	;
        unsigned char CS_Status				;
        unsigned char Crc_Low				;
        unsigned char Crc_High				;

//    };
} UART_TX_HEADER;

typedef union {
    unsigned int word;

    struct {
        unsigned int b0 : 1;
        unsigned int b1 : 1;
        unsigned int b2 : 1;
        unsigned int b3 : 1;
        unsigned int b4 : 1;
        unsigned int b5 : 1;
        unsigned int b6 : 1;
        unsigned int b7 : 1;
        unsigned int b8 : 1;
        unsigned int b9 : 1;
        unsigned int b10 : 1;
        unsigned int b11 : 1;
        unsigned int b12 : 1;
        unsigned int b13 : 1;
        unsigned int b14 : 1;
        unsigned int b15 : 1;
    } bits;

    struct {
        unsigned char LSB;
        unsigned char MSB;
    } bytes;
} wdata;

typedef union {

    unsigned char byte;

    struct {
        unsigned char b0 : 1;
        unsigned char b1 : 1;
        unsigned char b2 : 1;
        unsigned char b3 : 1;
        unsigned char b4 : 1;
        unsigned char b5 : 1;
        unsigned char b6 : 1;
        unsigned char b7 : 1;
    } bits;

} bbdata;

typedef struct {
    bbdata uni_STATUS_IOUT;
    bbdata uni_STATUS_INPUT;
    bbdata uni_STATUS_TEMPERATURE;
    wdata uni_STATUS_WORD;
    bbdata uni_STATUS_CML;  //2012.05.29 ins. refer to 1.6kw.

    bbdata uni_STATUS_VOUT_MASK;
    bbdata uni_STATUS_IOUT_MASK;
    bbdata uni_STATUS_INPUT_MASK;
    bbdata uni_STATUS_TEMPERATURE_MASK;
} structPAGE;

typedef union
{
    unsigned char Bytes[4];
    unsigned long DWord;
} BYTES_TO_WORD;


// Blackbox
//170926 ksm add read previous blackbox data



/* Position that  Black Box data is stored  */







//DataLogging States
enum
{
	DATALOGGING_INIT,
	DATALOGGING_READ,
	DATALOGGING_WRITE,
	DATALOGGING_VERIFY,
	DATALOGGING_VERIFY_RESULT,
	DATALOGGING_IDLE
};

typedef struct {
    unsigned int   Addr;
    unsigned int   Length;
} _DATA_LOGGING_QUOUE_LIST;

typedef struct {
    unsigned char  Enable;
    unsigned char  FIFOIndex_In;
    unsigned char  FIFOIndex_Out;
    _DATA_LOGGING_QUOUE_LIST  Lists[20];
} _DATA_LOGGING_WRITE_QUOUE;

/*memory space to store black box data*/
typedef struct {
    unsigned char LO  : 4;
    unsigned char HI  : 4;
} nibble_struct;

typedef union {
    unsigned char byte;
    nibble_struct nibble;
} fault_cnt_union;

// Hot sied status

//SMBus Address
// Check A0 and A1 ports
//      A0/A1              :    0/0      0/1      1/0       1/1
// PS PSMI Device     :    B0h      B2h      B4h       B6h




// Declare No_page









// Declare PAGE[0] BMC Variables 






// Declare PAGE[1]  ME Variables 





// Declare PAGE[0] SMBAlert Mask




// Declare PAGE[1] SMBAlert Mask










//--- Cmd IOUT
                                                        // Intel, 0xF000 -> 0xE000
                                                        // I12V scaling factor = -2 = 2*exp(X), two's complement = 1111000000000000b = 0xF00

//--- Cmd VCAP = Vpfc
//--- Cmd VOUT(12VOUT and 5VOUT)



//--- Cmd FAN1 SPEED


// Fault Flags

//PS_ON_HOTSIDE output  port On/Off control

//#define PMBUS_CMD_IOUT_OC_FAULT_LIMIT_DATA 0x0064  // 220519 change 0x00EB -> 100A

// Define voltage status

// Command code : 0xF0, RW Word



// 2011.10.08  16:12:03 WON INSERT FW_UPLOADING_COMMAND

// PFC burst mode condition, 211218 burst




//Accuracy_78M6610


typedef struct {
    unsigned int b0  : 1;   /*This construct specifies the length in bits for each field */
    unsigned int b1  : 1;
    unsigned int b2  : 1;
    unsigned int b3  : 1;
    unsigned int b4  : 1;
    unsigned int b5  : 1;
    unsigned int b6  : 1;
    unsigned int b7  : 1;
    unsigned int b8  : 1;
    unsigned int b9  : 1;
    unsigned int b10 : 1;
    unsigned int b11 : 1;
    unsigned int b12 : 1;
    unsigned int b13 : 1;
    unsigned int b14 : 1;
    unsigned int b15 : 1;
} flagdata;


//
// check sfra_gui_scicomms_driverlib.c file
// for defines used by SCI CommsSFRA GUI
//










// *****************
// FW Updating in Bootloader mode
// *****************

extern unsigned char PMBus_FWUpload_Mode;






//*********************************************************************
//********************* BOOTLOADER ************************************
//*********************************************************************




// lfuSwitch set to this when Enabled








typedef union{
    enum
    {
        upLoadStatus_Idle = 0x00,
        upLoadStatus_start = 0x02,
        upLoadStatus_failed = 0x04,
    }enum_State;
    int32_t pad;
}FW_UPLOAD_State_EnumType;

extern volatile FW_UPLOAD_State_EnumType FwUpLoad_Status;


typedef union{
    enum
    {
        NOERROR = 0,
        TIMEOUT = 1,
        FRAMERR = 2,
        PRTYERR = 3,
        RXERR = 4,

        sciError5 = 5,
        sciError6 = 6,
        sciError7 = 7,
        sciError8 = 8,
    }enum_sciState;
    int32_t pad;
}SCI_State_EnumType;

extern volatile SCI_State_EnumType SCI_State;

//
// typedefs
//
typedef union
{
    unsigned char All[34];
    struct
    {
        unsigned char Crc_Low;
        unsigned char Crc_High;
        unsigned char Image_Infomation[8];
        unsigned char Model_Name[12];
        unsigned char empty;
        unsigned char FW_Major;
        unsigned char FW_Minor_Primary;
        unsigned char FW_Minor_Secondary;
        unsigned char HW_Revison_First;
        unsigned char HW_Revison_Second;
        unsigned char Block_Size_Low;
        unsigned char Block_Size_High;
        unsigned char Write_Time_Low;
        unsigned char Write_Time_High;
        unsigned char Encrption_Flag;
        unsigned char Select_Update_Mcu;
    }byte;
} BL_IMAGE_HEADER;

extern BL_IMAGE_HEADER xBL_Image_Header;


typedef union
{
    unsigned char All[96];
    struct
    {
        unsigned char Receive_Block_Size;
        unsigned char Current_Block_Cnt_L;
        unsigned char Current_Block_Cnt_H;
        unsigned char Update_Data[92];
        unsigned char Crc8;
    }byte;
} BL_UPDATE_DATA_INFO;

extern BL_UPDATE_DATA_INFO xBL_Update_Data_Info;


//typedef union
//{
//    unsigned char All[7];
//    struct
//    {
//        unsigned char Cmd2nd;
//        unsigned char Data_Size;
//        unsigned char PWOK_PFC_V_DET_Avg;  // PWOK_Deassert_Level_PFC_V_DET_Value_Avg;
//        unsigned char PWOK_VAC_V_DET_rms;
//
//        unsigned char b0 : 1;
//        unsigned char b1 : 1;
//        unsigned char b2 : 1;
//        unsigned char b3 : 1;
//        unsigned char b4 : 1;
//        unsigned char PSON_HOTSIDE : 1;
//        unsigned char Load20p : 1;
//        unsigned char Load60p : 1;
//
//        unsigned char Crc_Low;
//        unsigned char Crc_High;
//
//    }bytes;
//} UART_RX_HEADER;
//
//extern UART_RX_HEADER xUart_Rx_Header;
//
//
//typedef union {
//    unsigned char PrimaryMCU_Status2;
//    struct {
//        unsigned char Cmd1st                : 4;
//        unsigned char FW_Upload_Mode        : 1;   // checking Relay operation
//        unsigned char PFC_UV_indicator_flag : 1;   // checking Relay operation
//        unsigned char AC_UV_Fault           : 1;   // checking Relay operation
//        unsigned char DCDC                  : 1;   // checking PFC operation
//    } bits;
//}UART_Status_2;
//
//extern UART_Status_2 UART_Status2;
//
//
//typedef union {
//    unsigned char PrimaryMCU_Status1;//_UART_PrimaryMCU_Status;
//    struct {
//        unsigned char bUART_PriMCU_PFC_Turnon_Flag   : 1;   // checking PFC operation
//        unsigned char bUART_PriMCU_Relay_Turnon_Flag : 1;   // checking Relay operation
//        unsigned char bUART_PriMCU_ACInout_Loss      : 1;   // checking AC Loss
//        unsigned char bUART_PriMCU_ACInput_OC        : 1;
//        unsigned char bUART_PriMCU_ACInput_UVW       : 1;
//        unsigned char bUART_PriMCU_PFC_OVP           : 1;
//        unsigned char bUART_PriMCU_DCInputEnabled    : 1;   // checking DC Input
//        unsigned char bUART_PriMCU_ACInput_OVP       : 1;
//        //unsigned char bUART_PriMCU_ACInput_OVP         : 1;  // Comment for AC_FAIL >> by skim 2022.06.15
//        unsigned char bUART_PriMCU_AC_Fail : 1; // Add for AC_FAIL >> by skim 2022.06.15
//    } bits;
//}UART_Status_1;
//
//extern UART_Status_1 UART_Status1;
//
//
//typedef struct
//{
////    unsigned char PrimaryMCU_Status;
////    struct
////    {
//        unsigned char Status2;//UART_Status_2 Status2;
//        unsigned char Data_High;
//        unsigned char Data_Low;
//        unsigned char Status1;//UART_Status_1 Status1;
//        unsigned char FW_Upload;
//        unsigned char FW_Version;
//        unsigned char Crc_Low;
//        unsigned char Crc_High;
//
////    };
//} UART_TX_HEADER;
//
//extern UART_TX_HEADER xUart_Tx_Header;


typedef struct
{
    //set
    uint32_t Timer_1ms;
    uint32_t Timer_100us;
    //get
    uint32_t tick_sec;
    uint32_t tick_ms;
    uint32_t tick_us;

    uint32_t tick_main_ms;

} TASK_TIMER_Count;
extern TASK_TIMER_Count TickCount;














//*********************************************************************
//  debug
//*********************************************************************

typedef struct
{
    uint16_t debug0;
    uint16_t debug1;
    uint16_t debug2;
    unsigned char debugBuff0[10];
    unsigned char debugBuff1[10];
    unsigned char debugBuff2[10];
    unsigned char debugBuff3[10];
//    unsigned char debugBuff4[10];
//    unsigned char debugBuff5[200];
    uint16_t u16Index_sector;

} DBUG_POINT_HEADER;
extern DBUG_POINT_HEADER xDebug_Point;


typedef struct
{
//    uint16_t scibRx_Array[200];
//    uint16_t scibRx_Buffer[5][200];
    uint16_t scibRX_Size;
    uint16_t scibRX_Size_Num;

    uint32_t rxComplete;
    uint32_t rxIndex;
    uint16_t rxData;
    uint16_t rxSize;
    uint16_t rxTimerOver;
    uint16_t rxError;
    uint16_t rxReturn;

} rxBlockinfor;
extern rxBlockinfor sciInfor;





//
// Analog pin mux select define for AIO245 (so that ADC input can be used as a
// digital Input)
//

//
// Timer definitions based on System Clock
// 150 MHz devices
//


//230329


// 230215 not used #define PSFB_HVBUS_FB    		ADC_readResult(PSFB_HVBUS_ADCRESULTREGBASE, PSFB_HVBUS_ADC_SOC_NO)
// 230215 not used #define PSFB_IHV_FILT_FB 		ADC_readResult(PSFB_IHV_FILT_ADCRESULTREGBASE, PSFB_IHV_FILT_ADC_SOC_NO)

// 230215 sensing




//
// 1.0/4096
//


//
// the function prototypes
//
void PSFB_HAL_setupDevice(void);
void PSFB_HAL_setupFBPWMs(uint32_t base1, uint32_t base2,
                          uint16_t pwm_period_ticks,
                          uint16_t pwm_dbred_ticks, uint16_t pwm_dbfed_ticks);
void PSFB_HAL_setupSRPWMs(uint32_t base1, uint16_t pwm_period_ticks,
                 uint16_t pwm_db_red_init, uint16_t pwm_db_fed_init);
void PSFB_HAL_setupAdcOvrSamplPWM(uint32_t base1, uint16_t pwm_period_ticks);
void PSFB_HAL_setupFANPWM(uint32_t base1, uint16_t pwm_period_ticks); // 230106
void PSFB_HAL_initCmpssPCMC(void);
void PSFB_HAL_setupADCSOCTrigger(uint32_t base);
void PSFB_HAL_setupADC(void);
void PSFB_HAL_setupGPIOs(void);

// 230106
void Setup_SCI(void);
void Setup_I2C(void);
void Setup_FAN(void);
void Setup_DAC(void);

void PSFB_HAL_setupPWMs(void);
void PSFB_HAL_setupBoardProtection(uint32_t base1, uint32_t base2,
                                   uint32_t base3);
void PSFB_HAL_setupLEDGPIO(void);
void PSFB_HAL_setupdebugGPIO(void);
void PSFB_HAL_disablePWMCLKCounting(void);
void PSFB_HAL_enablePWMCLKCounting(void);
void PSFB_HAL_setPinsAsPWM();
void PSFB_HAL_setupCLA(void);

// 230106
void Setup_STANDBYGPIO(void);
void Setup_EEPROMWPGPIO(void);
void Setup_LSGPIO(void);
void Setup_PSONGPIO(void);
void Setup_ProtectionGPIO(void);
void Setup_Address_DSSIGPIO(void);
void Setup_PWOKGPIO(void);
void Setup_SMBAlert(void);
void Setup_CR(void);
void Setup_FRU(void);

//
// Function Prototypes
// CLA C Tasks defined in Cla1Tasks_C.cla
//
__attribute__((interrupt))  void Cla1Task1();
__attribute__((interrupt))  void Cla1Task2();
__attribute__((interrupt))  void Cla1Task3();
__attribute__((interrupt))  void Cla1Task4();
__attribute__((interrupt))  void Cla1Task5();
__attribute__((interrupt))  void Cla1Task6();
__attribute__((interrupt))  void Cla1Task7();
__attribute__((interrupt))  void Cla1BackgroundTask();

extern uint16_t Cla1ProgLoadStart;
extern uint16_t Cla1ProgLoadEnd;
extern uint16_t Cla1ProgLoadSize;
extern uint16_t Cla1ProgRunStart;
extern uint16_t Cla1ProgRunEnd;
extern uint16_t Cla1ProgRunSize;

//
// ISR related
//

    #pragma INTERRUPT (ISR1, HPI)
//    #pragma CODE_SECTION(ISR1,"isrcodefuncs");
    #pragma CODE_SECTION(ISR1,"ramfuncs");
    interrupt void ISR1(void);
    static inline void PSFB_HAL_clearInterrupt(uint16_t pie_group_no);
    static inline void PSFB_HAL_setupInterrupt(void);

//
// End #if PSFB_CONTROL_RUNNING_ON == C28x_CORE
//

static inline void PSFB_HAL_clearPWMInterruptFlag(uint32_t base)
{
    EPWM_clearEventTriggerInterruptFlag(base);
}

static inline void PSFB_HAL_enablePWMInterruptGeneration(uint32_t base)
{
    //
    // INT on ZRO event
    //
    EPWM_setInterruptSource(base, 1U);
    EPWM_setInterruptEventCount(base, 1);
    EPWM_enableInterrupt(base);
    EPWM_clearEventTriggerInterruptFlag(base);
}

static inline void PSFB_HAL_toggleLED(void)
{
    uint16_t ledCnt1 = 0;

    if(ledCnt1 == 0)
    {
        GPIO_togglePin(30);
        ledCnt1 = 10;
    }
    else
    {
        ledCnt1--;
    }
}


static inline void PSFB_HAL_clearInterrupt(uint16_t pie_group_no)
{
    Interrupt_clearACKGroup(pie_group_no);
}

static inline void PSFB_HAL_setupInterrupt(void)
{
    Interrupt_register(0x00300301U, &ISR1);
    PSFB_HAL_enablePWMInterruptGeneration(0x00004000U);
    PSFB_HAL_clearInterrupt(0x4U);
    Interrupt_enable(0x00300301U);

    // Interrupts that are used in this example are re-mapped to ISR functions
    // found within this file.
    //
//    Interrupt_register(INT_SPIB_TX, &spibTxFIFOISR);
//    Interrupt_register(INT_SPIB_RX, &spibRxFIFOISR);
//
//    // Enable interrupts required for this example
//    //
//    Interrupt_enable(INT_SPIB_RX);
//    Interrupt_disable(INT_SPIB_TX);
//
//
//    Interrupt_register(INT_SCIA_RX, &sciaRxISR);
//    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);
//    Interrupt_enable(INT_SCIA_RX);
//
//    Interrupt_register(INT_SCIA_TX, &sciaTxISR);
//    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);
//    Interrupt_enable(INT_SCIA_TX);




    __eallow();

    //
    // Enable Global interrupt INTM
    //
    __asm(" clrc INTM");

    //
    // Enable Global realtime interrupt DBGM
    //
    __asm(" clrc DBGM");
    __edis();
}

//
// End #ifndef __TMS320C28XX_CLA__
//


//
// End #ifndef PSFBPCMC_BOARD_H
//

//
// Global variables
//
extern int16_t PSFB_sr_enable;
extern int16_t PSFB_SR_mode_check;
extern int16_t SR_count;  //0331

//
// This routine sets up the basic device configuration such as initializing PLL
// copying code from FLASH to RAM
//
void PSFB_HAL_setupDevice(void)
{

    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Disable pin locks and enable internal pull-ups.
    //
    Device_initGPIO();

    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    //
    // TASK A FREQUENCY (400Hz), 2.5ms -> 250us
    //
    CPUTimer_setPeriod(0x00000C00U, ((20000000U * 48) / (2 * 4 * 1)) / ((uint16_t) 2500));

    //
    // TASK B FREQUENCY (10Hz), 100ms -> 1ms
    //
    CPUTimer_setPeriod(0x00000C08U , ((20000000U * 48) / (2 * 4 * 1)) / ((uint16_t) 1000));

    //
    // TASK C FREQUENCY (10kHz), 100us
    //
    CPUTimer_setPeriod(0x00000C10U , ((20000000U * 48) / (2 * 4 * 1)) / ((uint16_t) 10000));

    //
    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
    //
    CPUTimer_setPreScaler(0x00000C00U , 0);

    //
    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
    //
    CPUTimer_setPreScaler(0x00000C08U , 0);

    //
    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
    //
    CPUTimer_setPreScaler(0x00000C10U , 0);

    //
    // Make sure timer is stopped
    //
    CPUTimer_stopTimer(0x00000C00U);
    CPUTimer_stopTimer(0x00000C08U);
    CPUTimer_stopTimer(0x00000C10U);
    CPUTimer_setEmulationMode(0x00000C00U,
                              CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
    CPUTimer_setEmulationMode(0x00000C08U,
                              CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
    CPUTimer_setEmulationMode(0x00000C10U,
                              CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);

    //
    // Reload all counter register with period value
    //
    CPUTimer_reloadTimerCounter(0x00000C00U);
    CPUTimer_reloadTimerCounter(0x00000C08U);
    CPUTimer_reloadTimerCounter(0x00000C10U);

    CPUTimer_resumeTimer(0x00000C00U);
    CPUTimer_resumeTimer(0x00000C08U);
    CPUTimer_resumeTimer(0x00000C10U);

}

void PSFB_HAL_setupADC(void)
{
    //
    // ADC configurations and power up the ADC for both ADC A
    //
    __eallow();

    ADC_setVREF(0x00007400U, ADC_REFERENCE_EXTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(0x00007480U, ADC_REFERENCE_EXTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(0x00007500U, ADC_REFERENCE_EXTERNAL, ADC_REFERENCE_3_3V);

    //
    // configurations for ADC-A
    //
    ADC_setPrescaler(0x00007400U, ADC_CLK_DIV_2_0);
    ADC_setPrescaler(0x00007480U, ADC_CLK_DIV_2_0);
    ADC_setPrescaler(0x00007500U, ADC_CLK_DIV_2_0);

    //
    // power up the ADC
    //
    ADC_enableConverter(0x00007400U);
    ADC_enableConverter(0x00007480U);
    ADC_enableConverter(0x00007500U);

    //
    // delay for > 1ms to allow ADC time to power up
    //
    SysCtl_delay(((((long double)(((uint16_t)1000))) / (1000000.0L / (long double)((20000000U * 48) / (2 * 4 * 1)))) - 9.0L) / 5.0L);

    __edis();

    //
    // Start Configuration ADC Channels
    //
    // ADC CONVERSION CHANNELS CONFIGURATION
    // setup ADC conversions for current and voltage signals
    //
    
    // ADC MODULE A
    
    // LVBUS, 12V_Bor
    ADC_setupSOC(0x00007400U, ADC_SOC_NUMBER0,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN14, 10);
	// 230329
    ADC_setupSOC(0x00007400U, ADC_SOC_NUMBER1,
             ADC_TRIGGER_EPWM1_SOCA,
             ADC_CH_ADCIN14, 10);
	
    ADC_setupSOC(0x00007400U, ADC_SOC_NUMBER2,
	         ADC_TRIGGER_EPWM1_SOCA,
	         ADC_CH_ADCIN14, 10);
	
	//  IHV-FB, primary current
    ADC_setupSOC(0x00007400U, ADC_SOC_NUMBER3,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN2, 10);
	// 12VLS
    ADC_setupSOC(0x00007400U, ADC_SOC_NUMBER4,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN5, 10);
	// TSR
    ADC_setupSOC(0x00007400U, ADC_SOC_NUMBER5,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN8, 10);
	// 12VRS+
    ADC_setupSOC(0x00007400U, ADC_SOC_NUMBER6,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN9, 10);


    // ADC MODULE B

	// IOUT Heavy
    ADC_setupSOC(0x00007480U, ADC_SOC_NUMBER0,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN2, 10);
	// IOUT Light
    ADC_setupSOC(0x00007480U, ADC_SOC_NUMBER1,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN3, 10);
	// 12VSB_Bor
    ADC_setupSOC(0x00007480U, ADC_SOC_NUMBER2,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN11, 10);
	// Istb
    ADC_setupSOC(0x00007480U, ADC_SOC_NUMBER3,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN8, 10);
	// A0
	ADC_setupSOC(0x00007480U, ADC_SOC_NUMBER4,
				 ADC_TRIGGER_EPWM1_SOCA,
				 ADC_CH_ADCIN5, 10);

	// IOUT Heavy Fast
    ADC_setupSOC(0x00007480U, ADC_SOC_NUMBER5,
                 ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN9, 10);
	

	// ADC MODULE C

	// LS_ERROR
	ADC_setupSOC(0x00007500U, ADC_SOC_NUMBER0,
				 ADC_TRIGGER_EPWM1_SOCA,
				 ADC_CH_ADCIN2, 10);
	// Tamb
	ADC_setupSOC(0x00007500U, ADC_SOC_NUMBER1,
				 ADC_TRIGGER_EPWM1_SOCA,
				 ADC_CH_ADCIN5, 10);
	// 12VRS-
	ADC_setupSOC(0x00007500U, ADC_SOC_NUMBER2,
				 ADC_TRIGGER_EPWM1_SOCA,
				 ADC_CH_ADCIN8, 10);
	// 12VSB_Aor
	ADC_setupSOC(0x00007500U, ADC_SOC_NUMBER3,
				 ADC_TRIGGER_EPWM1_SOCA,
				 ADC_CH_ADCIN1, 10);
	// PSON
	ADC_setupSOC(0x00007500U, ADC_SOC_NUMBER4,
				 ADC_TRIGGER_EPWM1_SOCA,
				 ADC_CH_ADCIN3, 10);
}

void PSFB_HAL_setupADCSOCTrigger(uint32_t base)
{
    //
    // Select SOC from counter at ctr =0
    //
    EPWM_setADCTriggerSource(base, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);
	// test EPWM_setADCTriggerSource(base, EPWM_SOC_A, EPWM_SOC_TBCTR_PERIOD);

    //
    // Generate pulse on 1st even
    //
    EPWM_setADCTriggerEventPrescale(base, EPWM_SOC_A, ((uint16_t)1));

    //
    // Enable SOC on A group
    //
    EPWM_enableADCTrigger(base, EPWM_SOC_A);
}
// 230106
__interrupt void scibTxISR(void);
__interrupt void scibRxISR(void);

void Setup_SCI(void)
{
	//
	// GPIO57 is the SCI Rx pin.
	//
	GPIO_setMasterCore(57, GPIO_CORE_CPU1);
	GPIO_setPinConfig(0x00481206U);
	GPIO_setDirectionMode(57, GPIO_DIR_MODE_IN);
	GPIO_setPadConfig(57, 0x0000U);
	GPIO_setQualificationMode(57, GPIO_QUAL_ASYNC);

	//
	// GPIO56 is the SCI Tx pin.
	//
	GPIO_setMasterCore(56, GPIO_CORE_CPU1);
	GPIO_setPinConfig(0x00481006U);
	GPIO_setDirectionMode(56, GPIO_DIR_MODE_OUT);
	GPIO_setPadConfig(56, 0x0000U);
	GPIO_setQualificationMode(56, GPIO_QUAL_ASYNC);

	//
	// Map the ISR to the wake interrupt.
	//
	Interrupt_register(0x00630904U, scibTxISR);
	Interrupt_register(0x00620903U, scibRxISR);

	//
	// Initialize SCIA and its FIFO.
	//
	SCI_performSoftwareReset(0x00007210U);

	//
	// Configure SCIA for echoback.
	//
	SCI_setConfig(0x00007210U, (((20000000U * 48) / (2 * 4 * 1)) / 4), 115200, (0x0007U |
											 0x0000U |
											 SCI_CONFIG_PAR_EVEN)); // SCI_CONFIG_PAR_ODD));
	SCI_resetChannels(0x00007210U);
	SCI_clearInterruptStatus(0x00007210U, 0x04U | 0x02U);
	SCI_enableModule(0x00007210U);
	SCI_performSoftwareReset(0x00007210U);

	//
	// Enable the TXRDY and RXRDY interrupts.
	//
	SCI_enableInterrupt(0x00007210U, 0x04U | 0x02U);

	//
	// Send starting message.
	//
	//msg = "\r\n\n\nHello World!\0";
	//SCI_writeCharArray(SCIA_BASE, (uint16_t*)msg, 17);
	//msg = "\r\nYou will enter a character, and the DSP will echo it back!\n\0";
	//SCI_writeCharArray(SCIA_BASE, (uint16_t*)msg, 62);

	//
	// Clear the SCI interrupts before enabling them.
	//
	SCI_clearInterruptStatus(0x00007210U, 0x04U | 0x02U);

	//
	// Enable the interrupts in the PIE: Group 9 interrupts 1 & 2.
	//
	Interrupt_enable(0x00620903U);
	Interrupt_enable(0x00630904U);
	Interrupt_clearACKGroup(0x100U);
/*        // DSSI
        // GPIO17 is the SCI Rx pin.
        GPIO_setMasterCore(SCIRXDA_A1_GPIO, GPIO_CORE_CPU1);
        GPIO_setPinConfig(SCIRXDA_A1_GPIO_CONF);
        GPIO_setDirectionMode(SCIRXDA_A1_GPIO, GPIO_DIR_MODE_IN);
        GPIO_setPadConfig(SCIRXDA_A1_GPIO, GPIO_PIN_TYPE_STD);
        GPIO_setQualificationMode(SCIRXDA_A1_GPIO, GPIO_QUAL_ASYNC);

        // GPIO16 is the SCI Tx pin.
        GPIO_setMasterCore(SCITXDA_GPIO, GPIO_CORE_CPU1);
        GPIO_setPinConfig(SCITXDA_GPIO_CONF);
        GPIO_setDirectionMode(SCITXDA_GPIO, GPIO_DIR_MODE_OUT);
        GPIO_setPadConfig(SCITXDA_GPIO, GPIO_PIN_TYPE_STD);
        GPIO_setQualificationMode(SCITXDA_GPIO, GPIO_QUAL_ASYNC);

        // Map the ISR to the wake interrupt.
        Interrupt_register(INT_SCIA_TX, &sciaTxISR);
        Interrupt_register(INT_SCIA_RX, &sciaRxISR);

        // Initialize SCIA and its FIFO.
        SCI_performSoftwareReset(SCIA_BASE);

        // Configure SCIA for echoback.
        SCI_setConfig(SCIA_BASE, DEVICE_LSPCLK_FREQ, 115200, (SCI_CONFIG_WLEN_8 |
                                                SCI_CONFIG_STOP_ONE |
                                                SCI_CONFIG_PAR_EVEN));	// SCI_CONFIG_PAR_ODD));

        SCI_resetChannels(SCIA_BASE);
        SCI_clearInterruptStatus(SCIA_BASE, SCI_INT_TXFF | SCI_INT_RXFF);
        SCI_enableFIFO(SCIA_BASE);
        SCI_enableModule(SCIA_BASE);
        SCI_performSoftwareReset(SCIA_BASE);

        // Set the transmit FIFO level to 0 and the receive FIFO level to 2.
        // Enable the TXFF and RXFF interrupts.
        SCI_setFIFOInterruptLevel(SCIA_BASE, SCI_FIFO_TX0, SCI_FIFO_RX1);
        SCI_enableInterrupt(SCIA_BASE, SCI_INT_TXFF | SCI_INT_RXFF);

        // Clear the SCI interrupts before enabling them.
        SCI_clearInterruptStatus(SCIA_BASE, SCI_INT_TXFF | SCI_INT_RXFF);

        // Enable the interrupts in the PIE: Group 9 interrupts 1 & 2.
        Interrupt_enable(INT_SCIA_RX);
        Interrupt_enable(INT_SCIA_TX);
        Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);*/
}

// 230106
void Setup_I2C(void)
{
        // Blackbox
        // Initialize GPIOs for use as SDA A and SCL A respectively
        // GPIO26 is the SDA pin.
        GPIO_setPinConfig(0x00081400U);
        GPIO_setPadConfig(26, 0x0001U);
        GPIO_setQualificationMode(26, GPIO_QUAL_ASYNC);
        // GPIO27 is the SCL pin.
        GPIO_setPinConfig(0x00081600U);
        GPIO_setPadConfig(27, 0x0001U);
        GPIO_setQualificationMode(27, GPIO_QUAL_ASYNC);

        // PMBus
        // Initialize GPIOs for use as SDA A and SCL A respectively

        // GPIO14 is the SDA pin.
        GPIO_setPinConfig(0x00061C00U);
        GPIO_setPadConfig(14, 0x0001U);
        GPIO_setQualificationMode(14, GPIO_QUAL_ASYNC);
        // GPIO15 is the SCL pin.
        GPIO_setPinConfig(0x00061E00U);
        GPIO_setPadConfig(15, 0x0001U);
        GPIO_setQualificationMode(15, GPIO_QUAL_ASYNC);
}

// 230106
__interrupt void INT_myECAP0_ISR(void);
void Setup_FAN(void)
{
	// EPWM3 -> myEPWM3 Pinmux
	GPIO_setPinConfig(0x00060801U);
	GPIO_setPadConfig(4, 0x0000U);
	GPIO_setQualificationMode(4, GPIO_QUAL_SYNC);

	// GPIO_setPinConfig(GPIO_5_EPWM3_B);
	// GPIO_setPadConfig(myEPWM3_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	// GPIO_setQualificationMode(myEPWM3_EPWMB_GPIO, GPIO_QUAL_SYNC);

	// Stop all PWM mode clock
    PSFB_HAL_disablePWMCLKCounting();
	
	// EPWM Configurations
    EPWM_setClockPrescaler(0x00004200U, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(0x00004200U, 2400);	
    EPWM_setTimeBaseCounter(0x00004200U, 0);	
    EPWM_setTimeBaseCounterMode(0x00004200U, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_disablePhaseShiftLoad(0x00004200U);	
    EPWM_setPhaseShift(0x00004200U, 0);	
    EPWM_setSyncInPulseSource(0x00004200U, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3);	
    EPWM_setCounterCompareValue(0x00004200U, EPWM_COUNTER_COMPARE_A, 0);	// 1200 50% duty	
    EPWM_setCounterCompareShadowLoadMode(0x00004200U, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    //EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    //EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(0x00004200U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(0x00004200U, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    //EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    //EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);		

	// capture
	// GPIO16 -> myGPIO0 Pinmux
	GPIO_setPinConfig(0x00061000U);
		
	// INPUTXBAR Configurations
	XBAR_setInputPin(0x00007900U, XBAR_INPUT12, 8);

	// myECAP0_init
	// Disable ,clear all capture flags and interrupts
	ECAP_disableInterrupt(0x00005200U,
		(0x2U  |
		0x4U  |
		0x8U  |
		0x10U  |
		0x20U |
		0x40U   |
		0x80U));
	ECAP_clearInterrupt(0x00005200U,
		(0x2U  |
		0x4U  |
		0x8U  |
		0x10U  |
		0x20U |
		0x40U   |
		0x80U));
	// Disables time stamp capture.
	ECAP_disableTimeStampCapture(0x00005200U);
	// Stops Time stamp counter.
	ECAP_stopCounter(0x00005200U);
	// Sets eCAP in Capture mode.
	ECAP_enableCaptureMode(0x00005200U);
	// Sets the capture mode.
	//ECAP_setCaptureMode(myECAP0_BASE,ECAP_CONTINUOUS_CAPTURE_MODE,ECAP_EVENT_4);
	ECAP_setCaptureMode(0x00005200U,ECAP_ONE_SHOT_CAPTURE_MODE,ECAP_EVENT_4);
	// Sets the Capture event prescaler.
	ECAP_setEventPrescaler(0x00005200U, 0U);
	// Sets the Capture event polarity.
	ECAP_setEventPolarity(0x00005200U,ECAP_EVENT_1,ECAP_EVNT_RISING_EDGE);
	ECAP_setEventPolarity(0x00005200U,ECAP_EVENT_2,ECAP_EVNT_RISING_EDGE);
	ECAP_setEventPolarity(0x00005200U,ECAP_EVENT_3,ECAP_EVNT_RISING_EDGE);
	ECAP_setEventPolarity(0x00005200U,ECAP_EVENT_4,ECAP_EVNT_RISING_EDGE);
	// Configure counter reset on events
	ECAP_disableCounterResetOnEvent(0x00005200U,ECAP_EVENT_1);
	ECAP_disableCounterResetOnEvent(0x00005200U,ECAP_EVENT_2);
	ECAP_disableCounterResetOnEvent(0x00005200U,ECAP_EVENT_3);
	ECAP_enableCounterResetOnEvent(0x00005200U,ECAP_EVENT_4);	
	// Select eCAP input.
	ECAP_selectECAPInput(0x00005200U,ECAP_INPUT_INPUTXBAR12);
	// Sets a phase shift value count.
	ECAP_setPhaseShiftCount(0x00005200U,0U);
	// Enable counter loading with phase shift value.
	ECAP_enableLoadCounter(0x00005200U);
	// Configures Sync out signal mode.
	// ECAP_setSyncOutMode(myECAP0_BASE,ECAP_SYNC_OUT_SYNCI);
	ECAP_setSyncOutMode(0x00005200U,ECAP_SYNC_OUT_DISABLED);
	// Configures emulation mode.
	ECAP_setEmulationMode(0x00005200U,ECAP_EMULATION_FREE_RUN);
	// Set up the source for sync-in pulse..
	ECAP_setSyncInPulseSource(0x00005200U,ECAP_SYNC_IN_PULSE_SRC_DISABLE);
	// Starts Time stamp counter for myECAP0.
	ECAP_startCounter(0x00005200U);
	// Enables time stamp capture for myECAP0.
	ECAP_enableTimeStampCapture(0x00005200U);
	// Re-arms the eCAP module for myECAP0.
	ECAP_reArm(0x00005200U);
	// Enables interrupt source for myECAP0.
	ECAP_enableInterrupt(0x00005200U,0x10U);	

	//myGPIO0_init
	GPIO_setPadConfig(8, 0x0000U);
	GPIO_setQualificationMode(8, GPIO_QUAL_6SAMPLE);
	GPIO_setDirectionMode(8, GPIO_DIR_MODE_IN);
	GPIO_setMasterCore(8, GPIO_CORE_CPU1);

	// Interrupt Setings for INT_myECAP0
	Interrupt_register(0x00380401U, &INT_myECAP0_ISR);
	Interrupt_enable(0x00380401U);
}

// 230106 
void Setup_DAC(void)
{
    //
        // Set VDAC as the DAC reference voltage.
        // Edit here to use ADC VREF as the reference voltage.
    //
        DAC_setReferenceVoltage(0x00005C00U, DAC_REF_ADC_VREFHI);

        //
        // Enable the DAC output
        //
        DAC_enableOutput(0x00005C00U);

        //
        // Set the DAC shadow output to 0
        //
        DAC_setShadowValue(0x00005C00U, 0);
        SysCtl_delay(((((long double)(10)) / (1000000.0L / (long double)((20000000U * 48) / (2 * 4 * 1)))) - 9.0L) / 5.0L);

        //
        // Set VDAC as the DAC reference voltage.
        // Edit here to use ADC VREF as the reference voltage.
        //
        DAC_setReferenceVoltage(0x00005C10U, DAC_REF_ADC_VREFHI);

        //
        // Enable the DAC output
        //
        DAC_enableOutput(0x00005C10U);

    //
        // Set the DAC shadow output to 0
    //
        DAC_setShadowValue(0x00005C10U, 0);

        SysCtl_delay(((((long double)(10)) / (1000000.0L / (long double)((20000000U * 48) / (2 * 4 * 1)))) - 9.0L) / 5.0L);
}

void PSFB_HAL_setupGPIOs(void)
{
    // configure LED GPIO
    PSFB_HAL_setupLEDGPIO();

    // configure Debug GPIO, GPIO_TP1, GPIO_TP2
    PSFB_HAL_setupdebugGPIO();

    // 230106 STB_prot_MCU#, STB_ON#, Stb_VAR#
    Setup_STANDBYGPIO();

    // 230106 EEPROM WP
    Setup_EEPROMWPGPIO();

    // 230106 Load share, Ignore_LS
    Setup_LSGPIO();

    // 230106 PSON, PSON_GPIO
    Setup_PSONGPIO();

    // 230106 AC_FAIL, SCP, OCP, OVP
    Setup_ProtectionGPIO();

    // 230106
    Setup_Address_DSSIGPIO();

    // 230106 PW_OK_IN_FET, PWOK_1ST
    Setup_PWOKGPIO();

    // 230106 SMBAlert#_1ST, SMBAlert#_FET, SMBAlert#_2nd
    Setup_SMBAlert();

    // 230106 CR_BUS, CR_Low_Load, CR_config#, CR_Fault
    Setup_CR();

    // 230106 FRU_A1-3
    Setup_FRU();
}

void PSFB_HAL_setupPWMs(void)
{
    //
    // Stop all PWM mode clock
    //
    PSFB_HAL_disablePWMCLKCounting();

    PSFB_HAL_setupFBPWMs(0x00004000U, 0x00004100U,
                         ((120*1000000)) / (((float32_t)55*1000)*2),
                         (int)((float32_t)(float32_t) 0.13 * (float32_t)(120*1000000) * (float32_t)0.000001), (int)((float32_t)(float32_t) 0.13 * (float32_t)(120*1000000) * (float32_t)0.000001));

    //
    // PWM configuration for synchronous rectification
    //
    if(PSFB_sr_enable == 1)
     {
        //
        // SR FET PWM configuration
        //


        PSFB_HAL_setupSRPWMs(0x00004300U, ((120*1000000)) / (((float32_t)55*1000)*2),
                             (int)((float32_t)(float32_t) 0.13 * (float32_t)(120*1000000) * (float32_t)0.000001),
                             (int)((float32_t)(float32_t) 0.13 * (float32_t)(120*1000000) * (float32_t)0.000001));
     }

    //
    // ADC Over-sampling PWM Configuration
    //
    PSFB_HAL_setupAdcOvrSamplPWM(0x00004400U,
                                 ((120*1000000)) / (((float32_t)55*1000)*2));

}

void PSFB_HAL_setupBoardProtection(uint32_t base1, uint32_t base2,
                                   uint32_t base3)
{
    //
    // Disable all the muxes first
    //
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00);

    //
    // Setup PWM TRIP 4 as the destination for CMPSS1L output (OCP)
    // Trip4 will be active if CMPSSL is active
    //
    XBAR_setEPWMMuxConfig(XBAR_TRIP4, XBAR_EPWM_MUX01_CMPSS1_CTRIPL);
    XBAR_enableEPWMMux(XBAR_TRIP4, 0x00000002U);

    EPWM_selectDigitalCompareTripInput(base1, EPWM_DC_TRIP_TRIPIN4,
                                       EPWM_DC_TYPE_DCBH);
    EPWM_selectDigitalCompareTripInput(base2, EPWM_DC_TRIP_TRIPIN4,
                                       EPWM_DC_TYPE_DCBH);
    EPWM_selectDigitalCompareTripInput(base3, EPWM_DC_TRIP_TRIPIN4,
                                       EPWM_DC_TYPE_DCBH);

    EPWM_setTripZoneDigitalCompareEventCondition(base1, EPWM_TZ_DC_OUTPUT_B1,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneDigitalCompareEventCondition(base2, EPWM_TZ_DC_OUTPUT_B1,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);
    EPWM_setTripZoneDigitalCompareEventCondition(base3, EPWM_TZ_DC_OUTPUT_B1,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);

    EPWM_setDigitalCompareEventSource(base1, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
    EPWM_setDigitalCompareEventSource(base2, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
    EPWM_setDigitalCompareEventSource(base3, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

    //
    // Enable the following trips. Add Emu stop.
    //
    EPWM_enableTripZoneSignals(base1, 0x8000U);
    EPWM_enableTripZoneSignals(base2, 0x8000U);
    EPWM_enableTripZoneSignals(base3, 0x8000U);

    //
    // What do we want the OST/CBC events to do?
    // TZA events can force EPWMxA
    // TZB events can force EPWMxB
    //
    EPWM_setTripZoneAction(base1, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base1, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base3, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
    EPWM_setTripZoneAction(base3, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);

    //
    // Clear any spurious trip
    //
    EPWM_clearTripZoneFlag(base1, (0x4U |
            0x10U | 0x20U));
    EPWM_clearTripZoneFlag(base2, (0x4U |
            0x10U | 0x20U));
    EPWM_clearTripZoneFlag(base3, (0x4U |
            0x10U | 0x20U));
}

//
// initCmpssPCMC - Function to configure the high comparator of CMPSS3
//
void PSFB_HAL_initCmpssPCMC(void)
{
    //
    // Enable CMPSS and configure the negative input signal to come from
    // the DAC
    //
    CMPSS_enableModule(0x00005C80U);                 // CMPSS1 enable
    CMPSS_configHighComparator(0x00005C80U,          // High comparator (PCMC)
                               0x0000U);                  // DAC Value : internal DAC

    //
    // Use DACL for OCP and configure the negative input signal to come from
    // the DAC
    //
    CMPSS_configLowComparator(0x00005C80U,           // CMPSS Low comparator (OCP)
                              0x0000U);                   // DAC Value : internal DAC

    //
    // On 28004x, there is an additional MUX on the CMPSS,
    // configured in the analogsysctrl
    // Select positive input of CMPSSH to come from A2/B6/PGA1_OF (IHV_FB)
    // Select positive input of CMPSSL to come from A2/B6/PGA1_OF (IHV_FB)
    //
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1,       // HP :High positive, LP : Low positive
                           0);     // asys output?
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1,
                           0);

    //
    // Use VDDA as the reference for the DAC and set DAC value to
    //
    CMPSS_configDAC(0x00005C80U, 0x0000U |       // DAC Value -> Cmpss negative input
                    0x0080U | 0x0001U);

    __eallow();

    //
    // Set PWMSYNC as coming from ADC_OVERSAMPLE_PWM_BASE
    //
    (*((volatile uint16_t *)((uintptr_t)(0x00005C80U + 0x4U)))) =
            ((*((volatile uint16_t *)((uintptr_t)(0x00005C80U + 0x4U)))) &
             ~(0x1EU)) | (8);// 230227 8=>ePWM5, 4: ePWM3

    __edis();

    CMPSS_setRampDecValue(0x00005C80U, 20);

    //
    // DAC Initialization
    //
    CMPSS_setMaxRampValue(0x00005C80U, 512);
    CMPSS_setDACValueLow(0x00005C80U, 3584);              // Low Cmpss : IHV_FB OCP intial Setting. 3584/4096

    CMPSS_configFilterLow(0x00005C80U, 2,
                          10, 7);              // Digital filter 10 sample >= 7

    CMPSS_configFilterHigh(0x00005C80U, 0,
                          4, 4);              // Digital filter 10 sample >= 7

    //
    // Initialize digital filter
    //
    CMPSS_initFilterHigh(0x00005C80U);
    CMPSS_initFilterLow(0x00005C80U);

    //
    // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
    // the asynchronous comparator output.
    //
//    CMPSS_configOutputsHigh(PSFB_PCMC_OCP_CMPSS_BASE,
//                            CMPSS_TRIP_ASYNC_COMP | CMPSS_TRIPOUT_ASYNC_COMP);
    CMPSS_configOutputsHigh(0x00005C80U,
                           0x0008U | 0x0020U);
    CMPSS_configOutputsLow(0x00005C80U,
                           0x0008U | 0x0020U);

    //
    // Clear the latched comparator events
    //
    CMPSS_clearFilterLatchHigh(0x00005C80U);
    CMPSS_clearFilterLatchLow(0x00005C80U);
}

void PSFB_HAL_setupLEDGPIO(void)
{
        // 230103
        // GPIO30, 31 is the LED2, LED1 pin.
    GPIO_setDirectionMode(31, GPIO_DIR_MODE_OUT);
    GPIO_setDirectionMode(30, GPIO_DIR_MODE_OUT);
    GPIO_setQualificationMode(31, GPIO_QUAL_SYNC);
    GPIO_setQualificationMode(30, GPIO_QUAL_SYNC);
    GPIO_setPinConfig(0x00081C00U);
    GPIO_setPinConfig(0x00081E00U);
	GPIO_writePin(31, 0);
	GPIO_writePin(30, 0);
}

void PSFB_HAL_setupdebugGPIO(void)
{
        // GPIO_setDirectionMode(PSFB_DEBUG_IO, GPIO_DIR_MODE_OUT);
        // GPIO_setQualificationMode(PSFB_DEBUG_IO, GPIO_QUAL_SYNC);
        // GPIO_setPinConfig(PSFB_DEBUG_IO_CONF);
        // GPIO_writePin(PSFB_DEBUG_IO, 0);
        // 220103
        // GPIO51 is the GPIO_TP1 pin.
    GPIO_setDirectionMode(51, GPIO_DIR_MODE_OUT);
    GPIO_setQualificationMode(51, GPIO_QUAL_SYNC);
    GPIO_setPinConfig(0x00480600U);
    GPIO_writePin(51, 1);

        // GPIO52 is the GPIO_TP2 pin.
    GPIO_setDirectionMode(52, GPIO_DIR_MODE_OUT);
    GPIO_setQualificationMode(52, GPIO_QUAL_SYNC);
    GPIO_setPinConfig(0x00480800U);
    GPIO_writePin(52, 0);
}

// 230106 STB_prot_MCU#, STB_ON#, STB_VAR#
void Setup_STANDBYGPIO(void)
{
        // GPIO48 is the STB_prot_MCU pin.
        GPIO_setDirectionMode(48, GPIO_DIR_MODE_IN);
        // GPIO_setPadConfig(STB_prot_MCU, GPIO_PIN_TYPE_PULLUP)
        GPIO_setPinConfig(0x00480000U);

        // GPIO49 is the STB_ON pin.
        GPIO_setDirectionMode(49, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(49, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00480200U);
        GPIO_writePin(49, 1);

        // GPIO50 is the STB_VAR pin.
        GPIO_setDirectionMode(50, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(50, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00480400U);
        GPIO_writePin(50, 1);
}

// 230106 EEPROM WP
void Setup_EEPROMWPGPIO(void)
{
        // GPIO53 is the Write protect pin.
        GPIO_setDirectionMode(53, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(53, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00480A00U);
        GPIO_writePin(53, 0);
}

// 230106 Ignore_LS
void Setup_LSGPIO(void)
{
        // GPIO55 is the Ignore LS pin.
        GPIO_setDirectionMode(55, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(55, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00480E00U);
        GPIO_writePin(55, 0);
}

// 230106 PSON_GPIO
void Setup_PSONGPIO(void)
{
        // GPIO60 is the PSON_GPIO pin.
        GPIO_setDirectionMode(60, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(60, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00481800U);
        GPIO_writePin(60, 0);
}

// 230106 AC_FAIL, SCP, Fast OCP, OVP
void Setup_ProtectionGPIO(void)
{
        // GPIO13 is the AC Fail pin.
        GPIO_setDirectionMode(13, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(13, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00061A00U);
        GPIO_writePin(13, 0);

        // GPIO12 is the SCP pin.
        GPIO_setDirectionMode(12, GPIO_DIR_MODE_IN);
        GPIO_setPinConfig(0x00061800U);

        // GPIO11 is the Fast OCP pin.
        GPIO_setDirectionMode(11, GPIO_DIR_MODE_IN);
        GPIO_setPinConfig(0x00061600U);

        // GPIO3 is the OVP pin.
        GPIO_setDirectionMode(3, GPIO_DIR_MODE_IN);
        GPIO_setPinConfig(0x00060600U);        
}

// 230106 DSSI, Address
void Setup_Address_DSSIGPIO(void)
{
        // GPIO17 is the SCI Rx or A1 pin.
        GPIO_setPinConfig(0x00080200U);
        GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN);
        // GPIO_setPadConfig(DEVICE_GPIO_PIN_SCIRXDA_A1, GPIO_PIN_TYPE_STD);
        // GPIO_setQualificationMode(DEVICE_GPIO_PIN_SCIRXDA_A1, GPIO_QUAL_ASYNC);

        // GPIO16 is the SCI Tx pin.
        GPIO_setPinConfig(0x00080000U);
        GPIO_setDirectionMode(16, GPIO_DIR_MODE_OUT);
        GPIO_setPadConfig(16, 0x0000U);
        GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC);

        // GPIO20 is the A0 pin.
        GPIO_setPinConfig(0x00080800U);
        GPIO_setDirectionMode(20, GPIO_DIR_MODE_IN);
}

// 230106 
void Setup_PWOKGPIO(void)
{
        // GPIO24 is the PW_OK_IN_FET pin.
        GPIO_setDirectionMode(24, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(24, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00081000U);
        GPIO_writePin(24, 0);

        // GPIO25 is the PWOK_1st pin.
        GPIO_setPinConfig(0x00081200U);
        GPIO_setDirectionMode(25, GPIO_DIR_MODE_IN);
}

void Setup_SMBAlert(void)
{
        // GPIO40 is the SMBAlert#_1ST pin.
        GPIO_setPinConfig(40);
        GPIO_setDirectionMode(40, GPIO_DIR_MODE_IN);

        // GPIO23 is the SMBAlert#_FET pin.
        GPIO_setDirectionMode(23, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(23, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00080E00U);
        GPIO_writePin(23, 0);

        // GPIO41 is the SMBAlert#_2nd pin.
        GPIO_setPinConfig(41);
        GPIO_setDirectionMode(41, GPIO_DIR_MODE_IN);
}

void Setup_CR(void)
{
        // GPIO5 is the CR_BUS pin.
        GPIO_setPinConfig(5);
        GPIO_setDirectionMode(5, GPIO_DIR_MODE_IN);

        // GPIO9 is the CR_Low_Load pin.
        GPIO_setDirectionMode(9, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(9, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00061200U);
        GPIO_writePin(9, 0);

        // GPIO61 is the CR_Config pin.
        GPIO_setDirectionMode(61, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(61, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00481A00U);
        GPIO_writePin(61, 0);

        // GPIO29 is the CR_Fault pin.
        GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(29, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00081A00U);
        GPIO_writePin(29, 0);
}

void Setup_FRU(void)
{
        // GPIO59 is the FRU_A1 pin.
        GPIO_setDirectionMode(59, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(59, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00481600U);
        GPIO_writePin(59, 0);

        // GPIO10 is the FRU_A0 pin.
        GPIO_setDirectionMode(10, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(10, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00061400U);
        GPIO_writePin(10, 0);

        // GPIO34 is the FRU_A2 pin.
        GPIO_setDirectionMode(34, GPIO_DIR_MODE_OUT);
        GPIO_setQualificationMode(34, GPIO_QUAL_SYNC);
        GPIO_setPinConfig(0x00460400U);
        GPIO_writePin(34, 0);
}


void PSFB_HAL_setupAdcOvrSamplPWM(uint32_t base1, uint16_t pwm_period_ticks)
{
    __eallow();

    EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base1, pwm_period_ticks - 1);
    EPWM_setTimeBaseCounter(base1, 2);
    EPWM_setPhaseShift(base1, 2);
    EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP);
    EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    EPWM_enablePhaseShiftLoad(base1);

    HRPWM_setSyncPulseSource(base1, HRPWM_PWMSYNC_SOURCE_COMPC_UP);
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_C,
                                 pwm_period_ticks - 5);

    __edis();
}

void PSFB_HAL_setupFBPWMs(uint32_t base1, uint32_t base2,
        uint16_t pwm_period_ticks, uint16_t pwm_db_ticks_ls,
        uint16_t pwm_db_ticks_hs)
{
    __eallow();

    //
    // PWM clock on F28004x is divided by 2
    // ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=1
    //

    //
    // Base 1
    // Time Base SubModule Registers
    //
    EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base1, pwm_period_ticks);
    EPWM_setTimeBaseCounter(base1, 0);
    EPWM_setPhaseShift(base1, 0);
    EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //
    // Counter Compare Submodule Registers
    //
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_A, 0);
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_B, 0);
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_C,
                                (pwm_period_ticks - 20));
    EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);
    EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_B,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //
    // to start don't configure the PWM to do anything
    //
    (*((volatile uint16_t *)((uintptr_t)(base1 + 0x40U)))) = 0;

    //
    // CTR = ZERO , set to 1
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //
    // CTR = PRD , set to 0
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

    EPWM_setDeadBandCounterClock(base1, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);
    EPWM_setRisingEdgeDelayCount(base1, pwm_db_ticks_hs);
    EPWM_setFallingEdgeDelayCount(base1, pwm_db_ticks_ls);
    EPWM_setDeadBandDelayMode(base1, EPWM_DB_RED, 1);
    EPWM_setDeadBandDelayMode(base1, EPWM_DB_FED, 1);
    EPWM_setRisingEdgeDeadBandDelayInput(base1, 0U);
    EPWM_setFallingEdgeDeadBandDelayInput(base1, 0U);
    EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_RED,
                                  EPWM_DB_POLARITY_ACTIVE_HIGH);

    //
    // xB is inverted
    //
    EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_FED,
                                  EPWM_DB_POLARITY_ACTIVE_LOW);

    //
    // Configure PWM base1 as master
    //
    EPWM_disablePhaseShiftLoad(base1);
    EPWM_enableSyncOutPulseSource(base1, 0x2U);
    //EPWM_setSyncOutPulseMode(base1, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);


    //
    // Base 2
    //
    EPWM_setPeriodLoadMode(base2, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base2, (pwm_period_ticks - 1));
    EPWM_setTimeBaseCounter(base2, 2);
    EPWM_setPhaseShift(base2, 2);
    EPWM_setTimeBaseCounterMode(base2, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_setClockPrescaler(base2, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //
    // Counter Compare Submodule Registers
    //
    EPWM_setCounterCompareValue(base2, EPWM_COUNTER_COMPARE_A, 0);
    EPWM_setCounterCompareValue(base2, EPWM_COUNTER_COMPARE_B, 0);
    EPWM_setCounterCompareShadowLoadMode(base2, EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);
    EPWM_setCounterCompareShadowLoadMode(base2, EPWM_COUNTER_COMPARE_B,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);

    //
    // to start don't configure the PWM to do anything
    //
    (*((volatile uint16_t *)((uintptr_t)(base2 + 0x40U)))) = 0;

    //
    // BasexA output
    //
    // CTR = PRD , set to 1
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

    //
    // CTR = ZERO , set to 0
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //
    // CTR = T1U , set to 1
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);

    //
    // CTR = T1D , set to 0
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);                    // ??

    //
    // CTR = PRD , set to 1
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

    //
    // CTR = ZERO , set to 0
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //
    // CTR = T1U , set to 1
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);

    //
    // CTR = T1D , set to 0
    //
    EPWM_setActionQualifierAction(base2, EPWM_AQ_OUTPUT_B ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);

    //
    // Set DCEVTFILT as the trigger source for Channel A
    //
    EPWM_setActionQualifierT1TriggerSource(base2,
                                           EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);

    //
    // Digital Compare and Comparator-X-Bar Configuration
    // Disable all the muxes first
    //
    XBAR_enableEPWMMux(XBAR_TRIP5, 0x00);

    //
    // Setup PWM TRIP 5 as the destination for CMPSS1H output (PCMC)
    // Trip5 will be active if CMPSSH is active
    //
    XBAR_setEPWMMuxConfig(XBAR_TRIP5, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP5, 0x00000001U);

    //
    // DCAH = TRIP5 = Comparator 1H output
    //
    EPWM_selectDigitalCompareTripInput(base2, EPWM_DC_TRIP_TRIPIN5,
                                        EPWM_DC_TYPE_DCAH);

    //
    // DCAH = high
    //
    EPWM_setTripZoneDigitalCompareEventCondition(base2, EPWM_TZ_DC_OUTPUT_A2,
                                                  EPWM_TZ_EVENT_DCXH_HIGH);

    //
    // Set the source for digital compare filter as DCAEVT2
    //
    EPWM_setDigitalCompareEventSource(base2, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2,
                                       EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    //
    // Allow ASYNC DCAEVT2 for trip zone actions
    //
    EPWM_setDigitalCompareEventSyncMode(base2, EPWM_DC_MODULE_A,
                                        EPWM_DC_EVENT_2,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    //
    // Select DCAEVT2 cycle by cycle trip
    //
    EPWM_enableTripZoneSignals(base2, 0x40U);

    //
    // Event Filtering Configuration (inside digital compare)
    // Enable DC filter blanking window
    //
    EPWM_enableDigitalCompareBlankingWindow(base2);

    //
    // Set the signal source that will be filtered.
    //
    EPWM_setDigitalCompareFilterInput(base2, EPWM_DC_WINDOW_SOURCE_DCAEVT2);

    //
    // Set the Digital Compare filter blanking pulse.
    //
    EPWM_setDigitalCompareBlankingEvent(base2,
                                     EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);

    //
    // Set the blanking window offset in TBCLK counts
    //
    EPWM_setDigitalCompareWindowOffset(base2, pwm_period_ticks - 5);

    //
    // Set the blanking window length in TBCLK counts
    //
    EPWM_setDigitalCompareWindowLength(base2, 10);

    //
    // Trip-zone event actions
    // What do we want the CBC events to do?
    // TZAx events can force EPWMxA
    // TZBx events can force EPWMxB
    //
    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZA_D,
                              EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZA_U,
                              EPWM_TZ_ADV_ACTION_DISABLE);
    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZB_U,
                              EPWM_TZ_ADV_ACTION_LOW);
    EPWM_setTripZoneAdvAction(base2, EPWM_TZ_ADV_ACTION_EVENT_TZB_D,
                              EPWM_TZ_ADV_ACTION_DISABLE);
    EPWM_setTripZoneAction(base2, EPWM_TZ_ACTION_EVENT_TZA,
                           EPWM_TZ_ACTION_DISABLE);
    EPWM_setTripZoneAction(base2, EPWM_TZ_ACTION_EVENT_TZB,
                           EPWM_TZ_ACTION_DISABLE);

    //
    // Select CBC clear event
    //
    EPWM_selectCycleByCycleTripZoneClearEvent(base2,
                           EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

    //
    // Clear any spurious trip
    //
    EPWM_clearTripZoneFlag(base1, (0x4U |
            0x10U | 0x8000U));
    EPWM_clearTripZoneFlag(base2, (0x4U |
            0x10U | 0x8000U));

    EPWM_setDeadBandCounterClock(base2, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);
    EPWM_setRisingEdgeDelayCount(base2, pwm_db_ticks_hs);
    EPWM_setFallingEdgeDelayCount(base2, pwm_db_ticks_ls);
    EPWM_setDeadBandDelayMode(base2, EPWM_DB_RED, 1);
    EPWM_setDeadBandDelayMode(base2, EPWM_DB_FED, 1);
    EPWM_setRisingEdgeDeadBandDelayInput(base2, 0U);
    EPWM_setFallingEdgeDeadBandDelayInput(base2, 1U);
    EPWM_setDeadBandDelayPolarity(base2, EPWM_DB_RED,
                                  EPWM_DB_POLARITY_ACTIVE_HIGH);

    //
    // xB is inverted
    //
    EPWM_setDeadBandDelayPolarity(base2, EPWM_DB_FED,
                                  EPWM_DB_POLARITY_ACTIVE_LOW);

    //
    // Configure PWM base2 as slave
    //

    EPWM_setSyncInPulseSource(base2, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);        // Change
    EPWM_enablePhaseShiftLoad(base2);
//    EPWM_setSyncOutPulseMode(base2, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);
    EPWM_enableSyncOutPulseSource(base2, 0x2U);        // Change
    EPWM_setPhaseShift(base2, 2);
    EPWM_setCountModeAfterSync(base2, EPWM_COUNT_MODE_UP_AFTER_SYNC);


    __edis();
}

void PSFB_HAL_setupSRPWMs(uint32_t base1,  uint16_t pwm_period_ticks,
                 uint16_t pwm_db_red_init, uint16_t pwm_db_fed_init)
{
    __eallow();

    //
    // PWM clock on F28004x is divided by 2
    // ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=1
    // Deadband needs to be 0.5us => 10ns*50=500ns
    //
    // Base 1
    //
    EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base1, pwm_period_ticks);
    EPWM_setTimeBaseCounter(base1, 0);
//    EPWM_setPhaseShift(base1, 0);    //230208
    EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP_DOWN);
    EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    //
    // Counter Compare Submodule Registers
    //


    //
    // Configure PWM base1 as slave
    //
    EPWM_setSyncInPulseSource(base1, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);
    EPWM_enablePhaseShiftLoad(base1);
    //EPWM_setSyncOutPulseMode(base1, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);
    EPWM_enableSyncOutPulseSource(base1, 0x2U);

//    EPWM_setPhaseShift(base1, pwm_period_ticks - PSFB_SR_SHIFT);//400ns shift 230208
    EPWM_setPhaseShift(base1, 10);//400ns shift 230208

    EPWM_setCountModeAfterSync(base1, EPWM_COUNT_MODE_DOWN_AFTER_SYNC);//230208

//    EPWM_setPhaseShift(base1, 2);
//    EPWM_setCountModeAfterSync(base1, EPWM_COUNT_MODE_UP_AFTER_SYNC);

//    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_A, pwm_period_ticks-PSFB_SR_SHIFT);//230208
//    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_B, PSFB_SR_SHIFT);//230208

    EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);
    EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_B,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);

    EPWM_setActionQualifierShadowLoadMode(base1, EPWM_ACTION_QUALIFIER_A,
                                          EPWM_AQ_LOAD_ON_CNTR_ZERO);
    EPWM_setActionQualifierShadowLoadMode(base1, EPWM_ACTION_QUALIFIER_B,
                                          EPWM_AQ_LOAD_ON_CNTR_ZERO);

    //
    // to start don't configure the PWM to do anything
    //
    (*((volatile uint16_t *)((uintptr_t)(base1 + 0x40U)))) = 0;

    //
    // BasexA output
    // CTR = PRD , set to 1
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

    //
    // CTR = ZERO , set to 0
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //
    // CTR = T1U , set to 1
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);

    //
    // BasexB output - Following 4 not needed if xB generated using DB
    // CTR = PRD , set to 1
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_B ,
            EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

    //
    // CTR = ZERO , set to 0
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_B ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    //
    // CTR = T1D , set to 0
    //
    EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_B ,
            EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN);

    //
    // Set DCEVTFILT as the trigger source for Channel A
    //
    EPWM_setActionQualifierT1TriggerSource(base1,
                                           EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT);

    //
    // Digital Compare Configuration
    // DCAH = TRIP5 = Comparator 1 output (high side)
    //
    EPWM_selectDigitalCompareTripInput(base1, EPWM_DC_TRIP_TRIPIN5,
                                       EPWM_DC_TYPE_DCAH);

    //
    // DCAH = high
    //
    EPWM_setTripZoneDigitalCompareEventCondition(base1, EPWM_TZ_DC_OUTPUT_A2,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);

    //
    // Set the source for digital compare filter as DCAEVT2
    //
    EPWM_setDigitalCompareEventSource(base1, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    //
    // Allow ASYNC DCAEVT2 for trip zone actions
    //
    EPWM_setDigitalCompareEventSyncMode(base1, EPWM_DC_MODULE_A,
                                        EPWM_DC_EVENT_2,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    //
    // Event Filtering Configuration (inside digital compare)
    // Enable DC filter blanking window
    //
    EPWM_enableDigitalCompareBlankingWindow(base1);

    //
    // Set the signal source that will be filtered.
    //
    EPWM_setDigitalCompareFilterInput(base1, EPWM_DC_WINDOW_SOURCE_DCAEVT2);

    //
    // Set the Digital Compare filter blanking pulse.
    //
    EPWM_setDigitalCompareBlankingEvent(base1,
                                        EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD);

    //
    // Set the blanking window offset in TBCLK counts
    //
    EPWM_setDigitalCompareWindowOffset(base1, pwm_period_ticks - 5);

    //
    // Set the blanking window length in TBCLK counts - initial value
    //
    EPWM_setDigitalCompareWindowLength(base1, 10);

    EPWM_setDeadBandControlShadowLoadMode(base1, EPWM_DB_LOAD_ON_CNTR_ZERO);

    EPWM_setDeadBandCounterClock(base1, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);
    EPWM_setRisingEdgeDelayCount(base1, pwm_db_fed_init);
    EPWM_setFallingEdgeDelayCount(base1, pwm_db_red_init);
    EPWM_setDeadBandDelayMode(base1, EPWM_DB_RED, 1);
    EPWM_setDeadBandDelayMode(base1, EPWM_DB_FED, 1);
    EPWM_setRisingEdgeDeadBandDelayInput(base1, 0U);
    EPWM_setFallingEdgeDeadBandDelayInput(base1, 1U);
    EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_RED,
                                  EPWM_DB_POLARITY_ACTIVE_HIGH);

    //
    // xB is inverted
    //
    EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_FED,
                                  EPWM_DB_POLARITY_ACTIVE_LOW);


    EPWM_setDeadBandOutputSwapMode(base1, EPWM_DB_OUTPUT_A, 1);
    EPWM_setDeadBandOutputSwapMode(base1, EPWM_DB_OUTPUT_B, 1);//220130   A<->B Swap

//    EPWM_setDeadBandOutputSwapMode(base1, EPWM_DB_OUTPUT_A, false);
//    EPWM_setDeadBandOutputSwapMode(base1, EPWM_DB_OUTPUT_B, false);



    __edis();
}

void PSFB_HAL_setPinsAsPWM()
{
    GPIO_setDirectionMode(0, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(0, 0x0000U);
    GPIO_setPinConfig(0x00060001U);

    GPIO_setDirectionMode(1, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(1, 0x0000U);
    GPIO_setPinConfig(0x00060201U);

    GPIO_setDirectionMode(0, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(0, 0x0000U);
    GPIO_setPinConfig(0x00060001U);

    GPIO_setDirectionMode(1, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(1, 0x0000U);
    GPIO_setPinConfig(0x00060201U);

    GPIO_setDirectionMode(2, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(2, 0x0000U);
    GPIO_setPinConfig(0x00060401U);

    GPIO_setDirectionMode(3, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(3, 0x0000U);
    GPIO_setPinConfig(0x00060601U);

    GPIO_setDirectionMode(6, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(6, 0x0000U);
    GPIO_setPinConfig(0x00060C01U);

    GPIO_setDirectionMode(7, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(7, 0x0000U);
    GPIO_setPinConfig(0x00060E01U);

}

void PSFB_HAL_disablePWMCLKCounting(void)
{
    __eallow();
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    __edis();
}

void PSFB_HAL_enablePWMCLKCounting(void)
{
    __eallow();
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    __edis();
}

void PSFB_HAL_setupCLA(void)
{
    //
    // setup CLA to register an interrupt
    //

}
