let SysCtl_PeripheralPCLOCKCR = [
	{ name: "SYSCTL_PERIPH_CLK_CLA1", displayName: "CLA1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_DMA", displayName: "DMA clock" },
	{ name: "SYSCTL_PERIPH_CLK_TIMER0", displayName: "CPUTIMER0 clock" },
	{ name: "SYSCTL_PERIPH_CLK_TIMER1", displayName: "CPUTIMER1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_TIMER2", displayName: "CPUTIMER2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CPUBGCRC", displayName: "CPUBGCRC clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLA1BGCRC", displayName: "CLA1BGCRC clock" },
	{ name: "SYSCTL_PERIPH_CLK_HRCAL", displayName: "HRCAL clock" },
	{ name: "SYSCTL_PERIPH_CLK_TBCLKSYNC", displayName: "TBCLKSYNC clock" },
	{ name: "SYSCTL_PERIPH_CLK_GTBCLKSYNC", displayName: "GTBCLKSYNC clock" },
	{ name: "SYSCTL_PERIPH_CLK_ERAD", displayName: "ERAD clock" },
	{ name: "SYSCTL_PERIPH_CLK_EMIF1", displayName: "EMIF1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EMIF2", displayName: "EMIF2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM1", displayName: "EPWM1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM2", displayName: "EPWM2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM3", displayName: "EPWM3 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM4", displayName: "EPWM4 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM5", displayName: "EPWM5 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM6", displayName: "EPWM6 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM7", displayName: "EPWM7 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM8", displayName: "EPWM8 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM9", displayName: "EPWM9 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM10", displayName: "EPWM10 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM11", displayName: "EPWM11 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM12", displayName: "EPWM12 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM13", displayName: "EPWM13 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM14", displayName: "EPWM14 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM15", displayName: "EPWM15 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EPWM16", displayName: "EPWM16 clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAP1", displayName: "ECAP1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAP2", displayName: "ECAP2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAP3", displayName: "ECAP3 clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAP4", displayName: "ECAP4 clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAP5", displayName: "ECAP5 clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAP6", displayName: "ECAP6 clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAP7", displayName: "ECAP7 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EQEP1", displayName: "EQEP1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EQEP2", displayName: "EQEP2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_EQEP3", displayName: "EQEP3 clock" },
	{ name: "SYSCTL_PERIPH_CLK_SD1", displayName: "SD1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_SD2", displayName: "SD2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_SCIA", displayName: "SCI_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_SCIB", displayName: "SCI_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_SCIC", displayName: "SCI_C clock" },
	{ name: "SYSCTL_PERIPH_CLK_SCID", displayName: "SCI_D clock" },
	{ name: "SYSCTL_PERIPH_CLK_SPIA", displayName: "SPI_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_SPIB", displayName: "SPI_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_SPIC", displayName: "SPI_C clock" },
	{ name: "SYSCTL_PERIPH_CLK_SPID", displayName: "SPI_D clock" },
	{ name: "SYSCTL_PERIPH_CLK_I2CA", displayName: "I2C_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_I2CB", displayName: "I2C_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_CANA", displayName: "CAN_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_CANB", displayName: "CAN_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_MCBSPA", displayName: "MCBSP_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_MCBSPB", displayName: "MCBSP_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_USBA", displayName: "USB_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_ADCA", displayName: "ADC_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_ADCB", displayName: "ADC_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_ADCC", displayName: "ADC_C clock" },
	{ name: "SYSCTL_PERIPH_CLK_ADCD", displayName: "ADC_D clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS1", displayName: "CMPSS1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS2", displayName: "CMPSS2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS3", displayName: "CMPSS3 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS4", displayName: "CMPSS4 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS5", displayName: "CMPSS5 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS6", displayName: "CMPSS6 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS7", displayName: "CMPSS7 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CMPSS8", displayName: "CMPSS8 clock" },
	{ name: "SYSCTL_PERIPH_CLK_DACA", displayName: "DAC_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_DACB", displayName: "DAC_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_DACC", displayName: "DAC_C clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB1", displayName: "CLB1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB2", displayName: "CLB2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB3", displayName: "CLB3 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB4", displayName: "CLB4 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB5", displayName: "CLB5 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB6", displayName: "CLB6 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB7", displayName: "CLB7 clock" },
	{ name: "SYSCTL_PERIPH_CLK_CLB8", displayName: "CLB8 clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSITXA", displayName: "FSITX_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSITXB", displayName: "FSITX_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXA", displayName: "FSIRX_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXB", displayName: "FSIRX_B clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXC", displayName: "FSIRX_C clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXD", displayName: "FSIRX_D clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXE", displayName: "FSIRX_E clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXF", displayName: "FSIRX_F clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXG", displayName: "FSIRX_G clock" },
	{ name: "SYSCTL_PERIPH_CLK_FSIRXH", displayName: "FSIRX_H clock" },
	{ name: "SYSCTL_PERIPH_CLK_PMBUSA", displayName: "PMBUS_A clock" },
	{ name: "SYSCTL_PERIPH_CLK_DCC0", displayName: "DCC0 clock" },
	{ name: "SYSCTL_PERIPH_CLK_DCC1", displayName: "DCC1 clock" },
	{ name: "SYSCTL_PERIPH_CLK_DCC2", displayName: "DCC2 clock" },
	{ name: "SYSCTL_PERIPH_CLK_PBIST", displayName: "PBISTCLK clock" },
	{ name: "SYSCTL_PERIPH_CLK_ECAT", displayName: "ETHERCAT clock" },
]
let SysCtl_PeripheralSOFTPRES = [
	{ name: "SYSCTL_PERIPH_RES_CPU1CLA1", displayName: "Reset CPU1_CLA1 clock" },
	{ name: "SYSCTL_PERIPH_RES_CPU2CLA1", displayName: "Reset CPU2_CLA1 clock" },
	{ name: "SYSCTL_PERIPH_RES_CPU1CPUBGCRC", displayName: "Reset CPU1_CPUBGCRC clock" },
	{ name: "SYSCTL_PERIPH_RES_CPU1CLA1BGCRC", displayName: "Reset CPU1_CLA1BGCRC clock" },
	{ name: "SYSCTL_PERIPH_RES_CPU2CPUBGCRC", displayName: "Reset CPU2_CPUBGCRC clock" },
	{ name: "SYSCTL_PERIPH_RES_CPU2CLA1BGCRC", displayName: "Reset CPU2_CLA1BGCRC clock" },
	{ name: "SYSCTL_PERIPH_RES_CPU1ERAD", displayName: "Reset CPU1_ERAD clock" },
	{ name: "SYSCTL_PERIPH_RES_CPU2ERAD", displayName: "Reset CPU2_ERAD clock" },
	{ name: "SYSCTL_PERIPH_RES_EMIF1", displayName: "Reset EMIF1 clock" },
	{ name: "SYSCTL_PERIPH_RES_EMIF2", displayName: "Reset EMIF2 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM1", displayName: "Reset EPWM1 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM2", displayName: "Reset EPWM2 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM3", displayName: "Reset EPWM3 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM4", displayName: "Reset EPWM4 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM5", displayName: "Reset EPWM5 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM6", displayName: "Reset EPWM6 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM7", displayName: "Reset EPWM7 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM8", displayName: "Reset EPWM8 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM9", displayName: "Reset EPWM9 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM10", displayName: "Reset EPWM10 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM11", displayName: "Reset EPWM11 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM12", displayName: "Reset EPWM12 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM13", displayName: "Reset EPWM13 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM14", displayName: "Reset EPWM14 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM15", displayName: "Reset EPWM15 clock" },
	{ name: "SYSCTL_PERIPH_RES_EPWM16", displayName: "Reset EPWM16 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAP1", displayName: "Reset ECAP1 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAP2", displayName: "Reset ECAP2 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAP3", displayName: "Reset ECAP3 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAP4", displayName: "Reset ECAP4 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAP5", displayName: "Reset ECAP5 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAP6", displayName: "Reset ECAP6 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAP7", displayName: "Reset ECAP7 clock" },
	{ name: "SYSCTL_PERIPH_RES_EQEP1", displayName: "Reset EQEP1 clock" },
	{ name: "SYSCTL_PERIPH_RES_EQEP2", displayName: "Reset EQEP2 clock" },
	{ name: "SYSCTL_PERIPH_RES_EQEP3", displayName: "Reset EQEP3 clock" },
	{ name: "SYSCTL_PERIPH_RES_SD1", displayName: "Reset SD1 clock" },
	{ name: "SYSCTL_PERIPH_RES_SD2", displayName: "Reset SD2 clock" },
	{ name: "SYSCTL_PERIPH_RES_SCIA", displayName: "Reset SCI_A clock" },
	{ name: "SYSCTL_PERIPH_RES_SCIB", displayName: "Reset SCI_B clock" },
	{ name: "SYSCTL_PERIPH_RES_SCIC", displayName: "Reset SCI_C clock" },
	{ name: "SYSCTL_PERIPH_RES_SCID", displayName: "Reset SCI_D clock" },
	{ name: "SYSCTL_PERIPH_RES_SPIA", displayName: "Reset SPI_A clock" },
	{ name: "SYSCTL_PERIPH_RES_SPIB", displayName: "Reset SPI_B clock" },
	{ name: "SYSCTL_PERIPH_RES_SPIC", displayName: "Reset SPI_C clock" },
	{ name: "SYSCTL_PERIPH_RES_SPID", displayName: "Reset SPI_D clock" },
	{ name: "SYSCTL_PERIPH_RES_I2CA", displayName: "Reset I2C_A clock" },
	{ name: "SYSCTL_PERIPH_RES_I2CB", displayName: "Reset I2C_B clock" },
	{ name: "SYSCTL_PERIPH_RES_CANA", displayName: "Reset CAN_A clock" },
	{ name: "SYSCTL_PERIPH_RES_CANB", displayName: "Reset CAN_B clock" },
	{ name: "SYSCTL_PERIPH_RES_MCBSPA", displayName: "Reset MCBSP_A clock" },
	{ name: "SYSCTL_PERIPH_RES_MCBSPB", displayName: "Reset MCBSP_B clock" },
	{ name: "SYSCTL_PERIPH_RES_USBA", displayName: "Reset USB_A clock" },
	{ name: "SYSCTL_PERIPH_RES_ADCA", displayName: "Reset ADC_A clock" },
	{ name: "SYSCTL_PERIPH_RES_ADCB", displayName: "Reset ADC_B clock" },
	{ name: "SYSCTL_PERIPH_RES_ADCC", displayName: "Reset ADC_C clock" },
	{ name: "SYSCTL_PERIPH_RES_ADCD", displayName: "Reset ADC_D clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS1", displayName: "Reset CMPSS1 clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS2", displayName: "Reset CMPSS2 clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS3", displayName: "Reset CMPSS3 clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS4", displayName: "Reset CMPSS4 clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS5", displayName: "Reset CMPSS5 clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS6", displayName: "Reset CMPSS6 clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS7", displayName: "Reset CMPSS7 clock" },
	{ name: "SYSCTL_PERIPH_RES_CMPSS8", displayName: "Reset CMPSS8 clock" },
	{ name: "SYSCTL_PERIPH_RES_DACA", displayName: "Reset DAC_A clock" },
	{ name: "SYSCTL_PERIPH_RES_DACB", displayName: "Reset DAC_B clock" },
	{ name: "SYSCTL_PERIPH_RES_DACC", displayName: "Reset DAC_C clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB1", displayName: "Reset CLB1 clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB2", displayName: "Reset CLB2 clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB3", displayName: "Reset CLB3 clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB4", displayName: "Reset CLB4 clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB5", displayName: "Reset CLB5 clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB6", displayName: "Reset CLB6 clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB7", displayName: "Reset CLB7 clock" },
	{ name: "SYSCTL_PERIPH_RES_CLB8", displayName: "Reset CLB8 clock" },
	{ name: "SYSCTL_PERIPH_RES_FSITXA", displayName: "Reset FSITX_A clock" },
	{ name: "SYSCTL_PERIPH_RES_FSITXB", displayName: "Reset FSITX_B clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXA", displayName: "Reset FSIRX_A clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXB", displayName: "Reset FSIRX_B clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXC", displayName: "Reset FSIRX_C clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXD", displayName: "Reset FSIRX_D clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXE", displayName: "Reset FSIRX_E clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXF", displayName: "Reset FSIRX_F clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXG", displayName: "Reset FSIRX_G clock" },
	{ name: "SYSCTL_PERIPH_RES_FSIRXH", displayName: "Reset FSIRX_H clock" },
	{ name: "SYSCTL_PERIPH_RES_PMBUSA", displayName: "Reset PMBUS_A clock" },
	{ name: "SYSCTL_PERIPH_RES_DCC0", displayName: "Reset DCC0 clock" },
	{ name: "SYSCTL_PERIPH_RES_DCC1", displayName: "Reset DCC1 clock" },
	{ name: "SYSCTL_PERIPH_RES_DCC2", displayName: "Reset DCC2 clock" },
	{ name: "SYSCTL_PERIPH_RES_ECAT", displayName: "Reset ETHERCAT clock" },
]
let SysCtl_CPUSelPeripheral = [
	{ name: "SYSCTL_CPUSEL0_EPWM", displayName: "CPUSEL0 EPWM" },
	{ name: "SYSCTL_CPUSEL1_ECAP", displayName: "CPUSEL1 ECAP" },
	{ name: "SYSCTL_CPUSEL2_EQEP", displayName: "CPUSEL2 EQEP" },
	{ name: "SYSCTL_CPUSEL4_SD", displayName: "CPUSEL4 SD" },
	{ name: "SYSCTL_CPUSEL5_SCI", displayName: "CPUSEL5 SCI" },
	{ name: "SYSCTL_CPUSEL6_SPI", displayName: "CPUSEL6 SPI" },
	{ name: "SYSCTL_CPUSEL7_I2C", displayName: "CPUSEL7 I2C" },
	{ name: "SYSCTL_CPUSEL8_CAN", displayName: "CPUSEL8 CAN" },
	{ name: "SYSCTL_CPUSEL9_MCBSP", displayName: "CPUSEL9 MCBSP" },
	{ name: "SYSCTL_CPUSEL11_ADC", displayName: "CPUSEL11 ADC" },
	{ name: "SYSCTL_CPUSEL12_CMPSS", displayName: "CPUSEL12 CMPSS" },
	{ name: "SYSCTL_CPUSEL14_DAC", displayName: "CPUSEL14 DAC" },
	{ name: "SYSCTL_CPUSEL15_CLB", displayName: "CPUSEL15 CLB" },
	{ name: "SYSCTL_CPUSEL16_FSI", displayName: "CPUSEL16 FSI" },
	{ name: "SYSCTL_CPUSEL18_PMBUS", displayName: "CPUSEL18 PMBUS" },
	{ name: "SYSCTL_CPUSEL25_HRCAL", displayName: "CPUSEL25 HRCAL" },
]
let SysCtl_CPUSel = [
	{ name: "SYSCTL_CPUSEL_CPU1", displayName: "CPUSEL CPU1" },
	{ name: "SYSCTL_CPUSEL_CPU2", displayName: "CPUSEL CPU2" },
]
let SysCtl_WDPredivider = [
	{ name: "SYSCTL_WD_PREDIV_2", displayName: "PREDIVCLK = INTOSC1 / 2" },
	{ name: "SYSCTL_WD_PREDIV_4", displayName: "PREDIVCLK = INTOSC1 / 4" },
	{ name: "SYSCTL_WD_PREDIV_8", displayName: "PREDIVCLK = INTOSC1 / 8" },
	{ name: "SYSCTL_WD_PREDIV_16", displayName: "PREDIVCLK = INTOSC1 / 16" },
	{ name: "SYSCTL_WD_PREDIV_32", displayName: "PREDIVCLK = INTOSC1 / 32" },
	{ name: "SYSCTL_WD_PREDIV_64", displayName: "PREDIVCLK = INTOSC1 / 64" },
	{ name: "SYSCTL_WD_PREDIV_128", displayName: "PREDIVCLK = INTOSC1 / 128" },
	{ name: "SYSCTL_WD_PREDIV_256", displayName: "PREDIVCLK = INTOSC1 / 256" },
	{ name: "SYSCTL_WD_PREDIV_512", displayName: "PREDIVCLK = INTOSC1 / 512" },
	{ name: "SYSCTL_WD_PREDIV_1024", displayName: "PREDIVCLK = INTOSC1 / 1024" },
	{ name: "SYSCTL_WD_PREDIV_2048", displayName: "PREDIVCLK = INTOSC1 / 2048" },
	{ name: "SYSCTL_WD_PREDIV_4096", displayName: "PREDIVCLK = INTOSC1 / 4096" },
]
let SysCtl_WDPrescaler = [
	{ name: "SYSCTL_WD_PRESCALE_1", displayName: "WDCLK = PREDIVCLK / 1" },
	{ name: "SYSCTL_WD_PRESCALE_2", displayName: "WDCLK = PREDIVCLK / 2" },
	{ name: "SYSCTL_WD_PRESCALE_4", displayName: "WDCLK = PREDIVCLK / 4" },
	{ name: "SYSCTL_WD_PRESCALE_8", displayName: "WDCLK = PREDIVCLK / 8" },
	{ name: "SYSCTL_WD_PRESCALE_16", displayName: "WDCLK = PREDIVCLK / 16" },
	{ name: "SYSCTL_WD_PRESCALE_32", displayName: "WDCLK = PREDIVCLK / 32" },
	{ name: "SYSCTL_WD_PRESCALE_64", displayName: "WDCLK = PREDIVCLK / 64" },
]
let SysCtl_WDMode = [
	{ name: "SYSCTL_WD_MODE_RESET", displayName: "WD MODE RESET" },
	{ name: "SYSCTL_WD_MODE_INTERRUPT", displayName: "WD MODE INTERRUPT" },
]
let SysCtl_LSPCLKPrescaler = [
	{ name: "SYSCTL_LSPCLK_PRESCALE_1", displayName: "LSPCLK = SYSCLK / 1" },
	{ name: "SYSCTL_LSPCLK_PRESCALE_2", displayName: "LSPCLK = SYSCLK / 2" },
	{ name: "SYSCTL_LSPCLK_PRESCALE_4", displayName: "LSPCLK = SYSCLK / 4 (default)" },
	{ name: "SYSCTL_LSPCLK_PRESCALE_6", displayName: "LSPCLK = SYSCLK / 6" },
	{ name: "SYSCTL_LSPCLK_PRESCALE_8", displayName: "LSPCLK = SYSCLK / 8" },
	{ name: "SYSCTL_LSPCLK_PRESCALE_10", displayName: "LSPCLK = SYSCLK / 10" },
	{ name: "SYSCTL_LSPCLK_PRESCALE_12", displayName: "LSPCLK = SYSCLK / 12" },
	{ name: "SYSCTL_LSPCLK_PRESCALE_14", displayName: "LSPCLK = SYSCLK / 14" },
]
let SysCtl_EPWMCLKDivider = [
	{ name: "SYSCTL_EPWMCLK_DIV_1", displayName: "EPWMCLK = PLLSYSCLK / 1" },
	{ name: "SYSCTL_EPWMCLK_DIV_2", displayName: "EPWMCLK = PLLSYSCLK / 2" },
]
let SysCtl_EMIF1CLKDivider = [
	{ name: "SYSCTL_EMIF1CLK_DIV_1", displayName: "EMIF1CLK = PLLSYSCLK / 1" },
	{ name: "SYSCTL_EMIF1CLK_DIV_2", displayName: "EMIF1CLK = PLLSYSCLK / 2" },
]
let SysCtl_EMIF2CLKDivider = [
	{ name: "SYSCTL_EMIF2CLK_DIV_1", displayName: "EMIF2CLK = PLLSYSCLK / 1" },
	{ name: "SYSCTL_EMIF2CLK_DIV_2", displayName: "EMIF2CLK = PLLSYSCLK / 2" },
]
let SysCtl_AccessPeripheral = [
	{ name: "SYSCTL_ACCESS_ADCA", displayName: "ADCA access" },
	{ name: "SYSCTL_ACCESS_ADCB", displayName: "ADCB access" },
	{ name: "SYSCTL_ACCESS_ADCC", displayName: "ADCC access" },
	{ name: "SYSCTL_ACCESS_ADCD", displayName: "ADCD access" },
	{ name: "SYSCTL_ACCESS_CMPSS1", displayName: "CMPSS1 access" },
	{ name: "SYSCTL_ACCESS_CMPSS2", displayName: "CMPSS2 access" },
	{ name: "SYSCTL_ACCESS_CMPSS3", displayName: "CMPSS3 access" },
	{ name: "SYSCTL_ACCESS_CMPSS4", displayName: "CMPSS4 access" },
	{ name: "SYSCTL_ACCESS_CMPSS5", displayName: "CMPSS5 access" },
	{ name: "SYSCTL_ACCESS_CMPSS6", displayName: "CMPSS6 access" },
	{ name: "SYSCTL_ACCESS_CMPSS7", displayName: "CMPSS7 access" },
	{ name: "SYSCTL_ACCESS_CMPSS8", displayName: "CMPSS8 access" },
	{ name: "SYSCTL_ACCESS_DACA", displayName: "DACA access" },
	{ name: "SYSCTL_ACCESS_DACB", displayName: "DACB access" },
	{ name: "SYSCTL_ACCESS_DACC", displayName: "DACC access" },
	{ name: "SYSCTL_ACCESS_EPWM1", displayName: "EPWM1 access" },
	{ name: "SYSCTL_ACCESS_EPWM2", displayName: "EPWM2 access" },
	{ name: "SYSCTL_ACCESS_EPWM3", displayName: "EPWM3 access" },
	{ name: "SYSCTL_ACCESS_EPWM4", displayName: "EPWM4 access" },
	{ name: "SYSCTL_ACCESS_EPWM5", displayName: "EPWM5 access" },
	{ name: "SYSCTL_ACCESS_EPWM6", displayName: "EPWM6 access" },
	{ name: "SYSCTL_ACCESS_EPWM7", displayName: "EPWM7 access" },
	{ name: "SYSCTL_ACCESS_EPWM8", displayName: "EPWM8 access" },
	{ name: "SYSCTL_ACCESS_EPWM9", displayName: "EPWM9 access" },
	{ name: "SYSCTL_ACCESS_EPWM10", displayName: "EPWM10 access" },
	{ name: "SYSCTL_ACCESS_EPWM11", displayName: "EPWM11 access" },
	{ name: "SYSCTL_ACCESS_EPWM12", displayName: "EPWM12 access" },
	{ name: "SYSCTL_ACCESS_EPWM13", displayName: "EPWM13 access" },
	{ name: "SYSCTL_ACCESS_EPWM14", displayName: "EPWM14 access" },
	{ name: "SYSCTL_ACCESS_EPWM15", displayName: "EPWM15 access" },
	{ name: "SYSCTL_ACCESS_EPWM16", displayName: "EPWM16 access" },
	{ name: "SYSCTL_ACCESS_EQEP1", displayName: "EQEP1 access" },
	{ name: "SYSCTL_ACCESS_EQEP2", displayName: "EQEP2 access" },
	{ name: "SYSCTL_ACCESS_EQEP3", displayName: "EQEP3 access" },
	{ name: "SYSCTL_ACCESS_ECAP1", displayName: "ECAP1 access" },
	{ name: "SYSCTL_ACCESS_ECAP2", displayName: "ECAP2 access" },
	{ name: "SYSCTL_ACCESS_ECAP3", displayName: "ECAP3 access" },
	{ name: "SYSCTL_ACCESS_ECAP4", displayName: "ECAP4 access" },
	{ name: "SYSCTL_ACCESS_ECAP5", displayName: "ECAP5 access" },
	{ name: "SYSCTL_ACCESS_ECAP6", displayName: "ECAP6 access" },
	{ name: "SYSCTL_ACCESS_ECAP7", displayName: "ECAP7 access" },
	{ name: "SYSCTL_ACCESS_SDFM1", displayName: "SDFM1 access" },
	{ name: "SYSCTL_ACCESS_SDFM2", displayName: "SDFM2 access" },
	{ name: "SYSCTL_ACCESS_CLB1", displayName: "CLB1 access" },
	{ name: "SYSCTL_ACCESS_CLB2", displayName: "CLB2 access" },
	{ name: "SYSCTL_ACCESS_CLB3", displayName: "CLB3 access" },
	{ name: "SYSCTL_ACCESS_CLB4", displayName: "CLB4 access" },
	{ name: "SYSCTL_ACCESS_CLB5", displayName: "CLB5 access" },
	{ name: "SYSCTL_ACCESS_CLB6", displayName: "CLB6 access" },
	{ name: "SYSCTL_ACCESS_CLB7", displayName: "CLB7 access" },
	{ name: "SYSCTL_ACCESS_CLB8", displayName: "CLB8 access" },
	{ name: "SYSCTL_ACCESS_SPIA", displayName: "SPIA access" },
	{ name: "SYSCTL_ACCESS_SPIB", displayName: "SPIB access" },
	{ name: "SYSCTL_ACCESS_SPIC", displayName: "SPIC access" },
	{ name: "SYSCTL_ACCESS_SPID", displayName: "SPID access" },
	{ name: "SYSCTL_ACCESS_PMBUSA", displayName: "PMBUS_A access" },
	{ name: "SYSCTL_ACCESS_CANA", displayName: "CAN_A access" },
	{ name: "SYSCTL_ACCESS_CANB", displayName: "CAN_B access" },
	{ name: "SYSCTL_ACCESS_MCBSPA", displayName: "MCBSPA access" },
	{ name: "SYSCTL_ACCESS_MCBSPB", displayName: "MCBSPB access" },
	{ name: "SYSCTL_ACCESS_USBA", displayName: "USBA access" },
	{ name: "SYSCTL_ACCESS_HRPWM", displayName: "HRPWM access" },
	{ name: "SYSCTL_ACCESS_ECAT", displayName: "ETHERCAT access" },
	{ name: "SYSCTL_ACCESS_FSIATX", displayName: "FSIATX access" },
	{ name: "SYSCTL_ACCESS_FSIARX", displayName: "FSIARX access" },
	{ name: "SYSCTL_ACCESS_FSIBTX", displayName: "FSIBTX access" },
	{ name: "SYSCTL_ACCESS_FSIBRX", displayName: "FSIBRX access" },
	{ name: "SYSCTL_ACCESS_FSICRX", displayName: "FSICRX access" },
	{ name: "SYSCTL_ACCESS_FSIDRX", displayName: "FSIDRX access" },
	{ name: "SYSCTL_ACCESS_FSIERX", displayName: "FSIERX access" },
	{ name: "SYSCTL_ACCESS_FSIFRX", displayName: "FSIFRX access" },
	{ name: "SYSCTL_ACCESS_FSIGRX", displayName: "FSIGRX access" },
	{ name: "SYSCTL_ACCESS_FSIHRX", displayName: "FSIHRX access" },
]
let SysCtl_AccessMaster = [
	{ name: "SYSCTL_ACCESS_CPUX", displayName: "CPU access to the peripheral" },
	{ name: "SYSCTL_ACCESS_CLA1", displayName: "CLA1 access to the peripheral" },
	{ name: "SYSCTL_ACCESS_DMA1", displayName: "DMA access to the peripheral" },
]
let SysCtl_AccessPermission = [
	{ name: "SYSCTL_ACCESS_FULL", displayName: "ACCESS FULL" },
	{ name: "SYSCTL_ACCESS_PROTECTED", displayName: "ACCESS PROTECTED" },
	{ name: "SYSCTL_ACCESS_NONE", displayName: "ACCESS NONE" },
]
let SysCtl_ClockOut = [
	{ name: "SYSCTL_CLOCKOUT_PLLSYS", displayName: "PLL System Clock post SYSCLKDIV" },
	{ name: "SYSCTL_CLOCKOUT_PLLRAW", displayName: "PLL Raw Clock" },
	{ name: "SYSCTL_CLOCKOUT_SYSCLK", displayName: "CPU System Clock" },
	{ name: "SYSCTL_CLOCKOUT_SYSCLK2", displayName: "CPU 2 System Clock" },
	{ name: "SYSCTL_CLOCKOUT_AUXPLLCLK", displayName: "Aux PLL Clock" },
	{ name: "SYSCTL_CLOCKOUT_INTOSC1", displayName: "Internal Oscillator 1" },
	{ name: "SYSCTL_CLOCKOUT_INTOSC2", displayName: "Internal Oscillator 2" },
	{ name: "SYSCTL_CLOCKOUT_XTALOSC", displayName: "External Oscillator" },
	{ name: "SYSCTL_CLOCKOUT_CMCLK", displayName: "CMCLK" },
	{ name: "SYSCTL_CLOCKOUT_PUMPOSC", displayName: "PUMPOSC" },
	{ name: "SYSCTL_SYSPLLCLK_AUX", displayName: "Test Clk of the System APLL" },
	{ name: "SYSCTL_AUXPLLCLK_AUX", displayName: "Test Clk of the Auxillary APLL" },
	{ name: "SYSCTL_SYSPLLCLKOUT", displayName: "PLL System Clock pre SYSCLKDIV" },
	{ name: "SYSCTL_AUXPLLCLKOUT", displayName: "PLL System Clock pre AUXCLKDIV" },
]
let SysCtl_ExternalOscMode = [
	{ name: "SYSCTL_XTALMODE_CRYSTAL", displayName: "XTAL Oscillator Crystal Mode" },
	{ name: "SYSCTL_XTALMODE_SINGLE", displayName: "XTAL Oscillator Single-Ended Mode" },
]
let SysCtl_SyncOutputSource = [
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT", displayName: "EPWM1SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM2SYNCOUT", displayName: "EPWM2SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM3SYNCOUT", displayName: "EPWM3SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT", displayName: "EPWM4SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM5SYNCOUT", displayName: "EPWM5SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM6SYNCOUT", displayName: "EPWM6SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT", displayName: "EPWM7SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM8SYNCOUT", displayName: "EPWM8SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM9SYNCOUT", displayName: "EPWM9SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT", displayName: "EPWM10SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM11SYNCOUT", displayName: "EPWM11SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM12SYNCOUT", displayName: "EPWM12SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM13SYNCOUT", displayName: "EPWM13SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM14SYNCOUT", displayName: "EPWM14SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM15SYNCOUT", displayName: "EPWM15SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_EPWM16SYNCOUT", displayName: "EPWM16SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_ECAP1SYNCOUT", displayName: "ECAP1SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_ECAP2SYNCOUT", displayName: "ECAP2SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_ECAP3SYNCOUT", displayName: "ECAP3SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_ECAP4SYNCOUT", displayName: "ECAP4SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_ECAP5SYNCOUT", displayName: "ECAP5SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_ECAP6SYNCOUT", displayName: "ECAP6SYNCOUT --> EXTSYNCOUT" },
	{ name: "SYSCTL_SYNC_OUT_SRC_ECAP7SYNCOUT", displayName: "ECAP7SYNCOUT --> EXTSYNCOUT" },
]
let SysCtl_DeviceParametric = [
	{ name: "SYSCTL_DEVICE_QUAL", displayName: "Device Qualification Status" },
	{ name: "SYSCTL_DEVICE_PINCOUNT", displayName: "Device Pin Count" },
	{ name: "SYSCTL_DEVICE_INSTASPIN", displayName: "Device InstaSPIN Feature Set" },
	{ name: "SYSCTL_DEVICE_FLASH", displayName: "Device Flash size (KB)" },
	{ name: "SYSCTL_DEVICE_PARTID", displayName: "Device Part ID Format Revision" },
	{ name: "SYSCTL_DEVICE_FAMILY", displayName: "Device Family" },
	{ name: "SYSCTL_DEVICE_PARTNO", displayName: "Device Part Number" },
	{ name: "SYSCTL_DEVICE_CLASSID", displayName: "Device Class ID" },
]
let SysCtl_CoreReset = [
	{ name: "SYSCTL_CORE_DEACTIVE", displayName: "Core reset is deactivated" },
	{ name: "SYSCTL_CORE_ACTIVE", displayName: "Core is held in reset" },
]
let SysCtl_SelADC = [
	{ name: "SYSCTL_SELECT_ADCA", displayName: "ADCA access" },
	{ name: "SYSCTL_SELECT_ADCB", displayName: "ADCB access" },
	{ name: "SYSCTL_SELECT_ADCC", displayName: "ADCC access" },
	{ name: "SYSCTL_SELECT_ADCD", displayName: "ADCD access" },
]
let SysCtl_CPUBank = [
	{ name: "SYSCTL_CPU1BANK", displayName: "CPU1BANK" },
	{ name: "SYSCTL_CPU2BANK", displayName: "CPU2BANK" },
	{ name: "SYSCTL_CMBANK", displayName: "CMBANK" },
]
let SysCtl_SharedPeripheral = [
	{ name: "SYSCTL_PALLOCATE_USBA", displayName: "Allocate USB_A to CM" },
	{ name: "SYSCTL_PALLOCATE_ETHERCAT", displayName: "Allocate ETHERCAT to CM" },
	{ name: "SYSCTL_PALLOCATE_CAN_A", displayName: "Allocate CAN_A to CM" },
	{ name: "SYSCTL_PALLOCATE_CAN_B", displayName: "Allocate CAN_B to CM" },
]
let SysCtl_SelType = [
	{ name: "SYSCTL_USBTYPE", displayName: "USBTYPE" },
	{ name: "SYSCTL_ECAPTYPE", displayName: "ECAPTYPE" },
	{ name: "SYSCTL_SDFMTYPE", displayName: "SDFMTYPE" },
	{ name: "SYSCTL_MEMMAPTYPE", displayName: "MEMMAPTYPE" },
]
let SysCtl_XClkDivider = [
	{ name: "SYSCTL_XCLKOUT_DIV_1", displayName: " XCLKOUT =  XCLKOUT / 1" },
	{ name: "SYSCTL_XCLKOUT_DIV_2", displayName: " XCLKOUT =  XCLKOUT / 2" },
	{ name: "SYSCTL_XCLKOUT_DIV_4", displayName: " XCLKOUT =  XCLKOUT / 4" },
	{ name: "SYSCTL_XCLKOUT_DIV_8", displayName: " XCLKOUT =  XCLKOUT / 8" },
]
let SysCtl_CMClkDivider = [
	{ name: "SYSCTL_CMCLKOUT_DIV_1", displayName: " CM clock =  CM clock / 1" },
	{ name: "SYSCTL_CMCLKOUT_DIV_2", displayName: " CM clock =  CM clock / 2" },
	{ name: "SYSCTL_CMCLKOUT_DIV_3", displayName: " CM clock =  CM clock / 3" },
	{ name: "SYSCTL_CMCLKOUT_DIV_4", displayName: " CM clock =  CM clock / 4" },
	{ name: "SYSCTL_CMCLKOUT_DIV_5", displayName: " CM clock =  CM clock / 5" },
	{ name: "SYSCTL_CMCLKOUT_DIV_6", displayName: " CM clock =  CM clock / 6" },
	{ name: "SYSCTL_CMCLKOUT_DIV_7", displayName: " CM clock =  CM clock / 7" },
	{ name: "SYSCTL_CMCLKOUT_DIV_8", displayName: " CM clock =  CM clock / 8" },
]
let SysCtl_EnetClkDivider = [
	{ name: "SYSCTL_ENETCLKOUT_DIV_1", displayName: " Enet clock =  Enet clock / 1" },
	{ name: "SYSCTL_ENETCLKOUT_DIV_2", displayName: " Enet clock =  Enet clock / 2" },
	{ name: "SYSCTL_ENETCLKOUT_DIV_3", displayName: " Enet clock =  Enet clock / 3" },
	{ name: "SYSCTL_ENETCLKOUT_DIV_4", displayName: " Enet clock =  Enet clock / 4" },
	{ name: "SYSCTL_ENETCLKOUT_DIV_5", displayName: " Enet clock =  Enet clock / 5" },
	{ name: "SYSCTL_ENETCLKOUT_DIV_6", displayName: " Enet clock =  Enet clock / 6" },
	{ name: "SYSCTL_ENETCLKOUT_DIV_7", displayName: " Enet clock =  Enet clock / 7" },
	{ name: "SYSCTL_ENETCLKOUT_DIV_8", displayName: " Enet clock =  Enet clock / 8" },
]
let SysCtl_ECatClkDivider = [
	{ name: "SYSCTL_ECATCLKOUT_DIV_1", displayName: " ECat clock =  ECat clock / 1" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_2", displayName: " ECat clock =  ECat clock / 2" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_3", displayName: " ECat clock =  ECat clock / 3" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_4", displayName: " ECat clock =  ECat clock / 4" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_5", displayName: " ECat clock =  ECat clock / 5" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_6", displayName: " ECat clock =  ECat clock / 6" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_7", displayName: " ECat clock =  ECat clock / 7" },
	{ name: "SYSCTL_ECATCLKOUT_DIV_8", displayName: " ECat clock =  ECat clock / 8" },
]
let SysCtl_PLLClockSource = [
	{ name: "SYSCTL_SOURCE_AUXPLL", displayName: "SOURCE AUXPLL" },
	{ name: "SYSCTL_SOURCE_SYSPLL", displayName: "SOURCE SYSPLL" },
]
let SysCtl_MCANClkDivider = [
	{ name: "SYSCTL_MCANCLK_DIV_1", displayName: " MCAN clock =  MCAN clock / 1" },
	{ name: "SYSCTL_MCANCLK_DIV_2", displayName: " MCAN clock =  MCAN clock / 2" },
	{ name: "SYSCTL_MCANCLK_DIV_3", displayName: " MCAN clock =  MCAN clock / 3" },
	{ name: "SYSCTL_MCANCLK_DIV_4", displayName: " MCAN clock =  MCAN clock / 4" },
	{ name: "SYSCTL_MCANCLK_DIV_5", displayName: " MCAN clock =  MCAN clock / 5" },
	{ name: "SYSCTL_MCANCLK_DIV_6", displayName: " MCAN clock =  MCAN clock / 6" },
	{ name: "SYSCTL_MCANCLK_DIV_7", displayName: " MCAN clock =  MCAN clock / 7" },
	{ name: "SYSCTL_MCANCLK_DIV_8", displayName: " MCAN clock =  MCAN clock / 8" },
	{ name: "SYSCTL_MCANCLK_DIV_9", displayName: " MCAN clock =  MCAN clock / 9" },
	{ name: "SYSCTL_MCANCLK_DIV_10", displayName: " MCAN clock =  MCAN clock / 10" },
	{ name: "SYSCTL_MCANCLK_DIV_11", displayName: " MCAN clock =  MCAN clock / 11" },
	{ name: "SYSCTL_MCANCLK_DIV_12", displayName: " MCAN clock =  MCAN clock / 12" },
	{ name: "SYSCTL_MCANCLK_DIV_13", displayName: " MCAN clock =  MCAN clock / 13" },
	{ name: "SYSCTL_MCANCLK_DIV_14", displayName: " MCAN clock =  MCAN clock / 14" },
	{ name: "SYSCTL_MCANCLK_DIV_15", displayName: " MCAN clock =  MCAN clock / 15" },
	{ name: "SYSCTL_MCANCLK_DIV_16", displayName: " MCAN clock =  MCAN clock / 16" },
	{ name: "SYSCTL_MCANCLK_DIV_17", displayName: " MCAN clock =  MCAN clock / 17" },
	{ name: "SYSCTL_MCANCLK_DIV_18", displayName: " MCAN clock =  MCAN clock / 18" },
	{ name: "SYSCTL_MCANCLK_DIV_19", displayName: " MCAN clock =  MCAN clock / 19" },
	{ name: "SYSCTL_MCANCLK_DIV_20", displayName: " MCAN clock =  MCAN clock / 20" },
]
let SysCtl_AuxPLLClkDivider = [
	{ name: "SYSCTL_AUXPLLCLK_DIV_1", displayName: " AUXPLL clock =  AUXPLL clock / 1" },
	{ name: "SYSCTL_AUXPLLCLK_DIV_2", displayName: " AUXPLL clock =  AUXPLL clock / 2" },
	{ name: "SYSCTL_AUXPLLCLK_DIV_4", displayName: " AUXPLL clock =  AUXPLL clock / 4" },
	{ name: "SYSCTL_AUXPLLCLK_DIV_8", displayName: " AUXPLL clock =  AUXPLL clock / 8" },
	{ name: "SYSCTL_AUXPLLCLK_DIV_3", displayName: " AUXPLL clock =  AUXPLL clock / 3" },
	{ name: "SYSCTL_AUXPLLCLK_DIV_5", displayName: " AUXPLL clock =  AUXPLL clock / 5" },
	{ name: "SYSCTL_AUXPLLCLK_DIV_6", displayName: " AUXPLL clock =  AUXPLL clock / 6" },
	{ name: "SYSCTL_AUXPLLCLK_DIV_7", displayName: " AUXPLL clock =  AUXPLL clock / 7" },
]
let SysCtl_Cputimer2ClkDivider = [
	{ name: "SYSCTL_TMR2CLKPRESCALE_1", displayName: " Cputimer2 clock =  Cputimer2 clock / 1" },
	{ name: "SYSCTL_TMR2CLKPRESCALE_2", displayName: " Cputimer2 clock =  Cputimer2 clock / 2" },
	{ name: "SYSCTL_TMR2CLKPRESCALE_4", displayName: " Cputimer2 clock =  Cputimer2 clock / 4" },
	{ name: "SYSCTL_TMR2CLKPRESCALE_8", displayName: " Cputimer2 clock =  Cputimer2 clock / 8" },
	{ name: "SYSCTL_TMR2CLKPRESCALE_16", displayName: " Cputimer2 clock =  Cputimer2 clock / 16" },
]
let SysCtl_Cputimer2ClkSource = [
	{ name: "SYSCTL_TMR2CLKSRCSEL_SYSCLK", displayName: "System Clock" },
	{ name: "SYSCTL_TMR2CLKSRCSEL_INTOSC1", displayName: "Internal Oscillator 1" },
	{ name: "SYSCTL_TMR2CLKSRCSEL_INTOSC2", displayName: "Internal Oscillator 2" },
	{ name: "SYSCTL_TMR2CLKSRCSEL_XTAL", displayName: "Crystal oscillator" },
	{ name: "SYSCTL_TMR2CLKSRCSEL_AUXPLLCLK", displayName: "Aux PLL CLock" },
]
let SysCtl_ClkRegSel = [
	{ name: "SYSCTL_REG_SEL_CLKSRCCTL1", displayName: "CLKSRCCTL1 lock" },
	{ name: "SYSCTL_REG_SEL_CLKSRCCTL2", displayName: "CLKSRCCTL2 lock" },
	{ name: "SYSCTL_REG_SEL_CLKSRCCTL3", displayName: "CLKSRCCTL3 lock" },
	{ name: "SYSCTL_REG_SEL_SYSPLLCTL1", displayName: "SYSPLLCTL1 lock" },
	{ name: "SYSCTL_REG_SEL_SYSPLLCTL2", displayName: "SYSPLLCTL2 lock" },
	{ name: "SYSCTL_REG_SEL_SYSPLLCTL3", displayName: "SYSPLLCTL3 lock" },
	{ name: "SYSCTL_REG_SEL_SYSPLLMULT", displayName: "SYSPLLMULT lock" },
	{ name: "SYSCTL_REG_SEL_AUXPLLCTL1", displayName: "AUXPLLCTL1 lock" },
	{ name: "SYSCTL_REG_SEL_AUXPLLMULT", displayName: "AUXPLLMULT lock" },
	{ name: "SYSCTL_REG_SEL_SYSCLKDIVSEL", displayName: "SYSCLKDIVSEL lock" },
	{ name: "SYSCTL_REG_SEL_AUXCLKDIVSEL", displayName: "AUXCLKDIVSEL lock" },
	{ name: "SYSCTL_REG_SEL_PERCLKDIVSEL", displayName: "PERCLKDIVSEL lock" },
	{ name: "SYSCTL_REG_SEL_CLBCLKCTL", displayName: "CLBCLKCTL lock" },
	{ name: "SYSCTL_REG_SEL_LOSPCP", displayName: "LOSPCP lock" },
	{ name: "SYSCTL_REG_SEL_XTALCR", displayName: "XTALCR lock" },
	{ name: "SYSCTL_REG_SEL_ETHERCATCLKCTL", displayName: "ETHERCATCLKCTL lock" },
	{ name: "SYSCTL_REG_SEL_CMCLKCTL", displayName: "CMCLKCTL lock" },
]
let SysCtl_CpuRegSel = [
	{ name: "SYSCTL_REG_SEL_PIEVERRADDR", displayName: "PIEVERRADDR lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR0", displayName: "PCLKCR0 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR1", displayName: "PCLKCR1 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR2", displayName: "PCLKCR2 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR3", displayName: "PCLKCR3 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR4", displayName: "PCLKCR4 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR6", displayName: "PCLKCR6 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR7", displayName: "PCLKCR7 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR8", displayName: "PCLKCR8 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR9", displayName: "PCLKCR9 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR10", displayName: "PCLKCR10 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR11", displayName: "PCLKCR11 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR13", displayName: "PCLKCR13 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR14", displayName: "PCLKCR14 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR16", displayName: "PCLKCR16 lock" },
	{ name: "SYSCTL_REG_SEL_LPMCR", displayName: "LPMCR lock" },
	{ name: "SYSCTL_REG_SEL_GPIOLPMSEL0", displayName: "GPIOLPMSEL0 lock" },
	{ name: "SYSCTL_REG_SEL_GPIOLPMSEL1", displayName: "GPIOLPMSEL1 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR17", displayName: "PCLKCR17 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR18", displayName: "PCLKCR18 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR20", displayName: "PCLKCR20 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR21", displayName: "PCLKCR21 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR22", displayName: "PCLKCR22 lock" },
	{ name: "SYSCTL_REG_SEL_PCLKCR23", displayName: "PCLKCR23 lock" },
	{ name: "SYSCTL_REG_SEL_ETHERCATCTL", displayName: "ETHERCATCTL lock" },
]
let SysCtl_CLBClkDivider = [
	{ name: "SYSCTL_CLBCLKOUT_DIV_1", displayName: " CLB clock =  CLB clock / 1" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_2", displayName: " CLB clock =  CLB clock / 2" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_3", displayName: " CLB clock =  CLB clock / 3" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_4", displayName: " CLB clock =  CLB clock / 4" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_5", displayName: " CLB clock =  CLB clock / 5" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_6", displayName: " CLB clock =  CLB clock / 6" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_7", displayName: " CLB clock =  CLB clock / 7" },
	{ name: "SYSCTL_CLBCLKOUT_DIV_8", displayName: " CLB clock =  CLB clock / 8" },
]
let SysCtl_CLBTClkDivider = [
	{ name: "SYSCTL_CLBTCLKOUT_DIV_1", displayName: " CLBTCLKOUT =  CLB clock / 1" },
	{ name: "SYSCTL_CLBTCLKOUT_DIV_2", displayName: " CLBTCLKOUT =  CLB clock / 2" },
]
let SysCtl_CLBInst = [
	{ name: "SYSCTL_CLB1", displayName: "CLB 1 instance" },
	{ name: "SYSCTL_CLB2", displayName: "CLB 2 instance" },
	{ name: "SYSCTL_CLB3", displayName: "CLB 3 instance" },
	{ name: "SYSCTL_CLB4", displayName: "CLB 4 instance" },
	{ name: "SYSCTL_CLB5", displayName: "CLB 5 instance" },
	{ name: "SYSCTL_CLB6", displayName: "CLB 6 instance" },
	{ name: "SYSCTL_CLB7", displayName: "CLB 7 instance" },
	{ name: "SYSCTL_CLB8", displayName: "CLB 8 instance" },
]
let SysCtl_CLBClkm = [
	{ name: "SYSCTL_CLBCLK_SYNC", displayName: " CLB is synchronous to SYSCLK" },
	{ name: "SYSCTL_CLBCLK_ASYNC", displayName: " CLB runs of asynchronous clock" },
]
exports = {
	SysCtl_PeripheralPCLOCKCR: SysCtl_PeripheralPCLOCKCR,
	SysCtl_PeripheralSOFTPRES: SysCtl_PeripheralSOFTPRES,
	SysCtl_CPUSelPeripheral: SysCtl_CPUSelPeripheral,
	SysCtl_CPUSel: SysCtl_CPUSel,
	SysCtl_WDPredivider: SysCtl_WDPredivider,
	SysCtl_WDPrescaler: SysCtl_WDPrescaler,
	SysCtl_WDMode: SysCtl_WDMode,
	SysCtl_LSPCLKPrescaler: SysCtl_LSPCLKPrescaler,
	SysCtl_EPWMCLKDivider: SysCtl_EPWMCLKDivider,
	SysCtl_EMIF1CLKDivider: SysCtl_EMIF1CLKDivider,
	SysCtl_EMIF2CLKDivider: SysCtl_EMIF2CLKDivider,
	SysCtl_AccessPeripheral: SysCtl_AccessPeripheral,
	SysCtl_AccessMaster: SysCtl_AccessMaster,
	SysCtl_AccessPermission: SysCtl_AccessPermission,
	SysCtl_ClockOut: SysCtl_ClockOut,
	SysCtl_ExternalOscMode: SysCtl_ExternalOscMode,
	SysCtl_SyncOutputSource: SysCtl_SyncOutputSource,
	SysCtl_DeviceParametric: SysCtl_DeviceParametric,
	SysCtl_CoreReset: SysCtl_CoreReset,
	SysCtl_SelADC: SysCtl_SelADC,
	SysCtl_CPUBank: SysCtl_CPUBank,
	SysCtl_SharedPeripheral: SysCtl_SharedPeripheral,
	SysCtl_SelType: SysCtl_SelType,
	SysCtl_XClkDivider: SysCtl_XClkDivider,
	SysCtl_CMClkDivider: SysCtl_CMClkDivider,
	SysCtl_EnetClkDivider: SysCtl_EnetClkDivider,
	SysCtl_ECatClkDivider: SysCtl_ECatClkDivider,
	SysCtl_PLLClockSource: SysCtl_PLLClockSource,
	SysCtl_MCANClkDivider: SysCtl_MCANClkDivider,
	SysCtl_AuxPLLClkDivider: SysCtl_AuxPLLClkDivider,
	SysCtl_Cputimer2ClkDivider: SysCtl_Cputimer2ClkDivider,
	SysCtl_Cputimer2ClkSource: SysCtl_Cputimer2ClkSource,
	SysCtl_ClkRegSel: SysCtl_ClkRegSel,
	SysCtl_CpuRegSel: SysCtl_CpuRegSel,
	SysCtl_CLBClkDivider: SysCtl_CLBClkDivider,
	SysCtl_CLBTClkDivider: SysCtl_CLBTClkDivider,
	SysCtl_CLBInst: SysCtl_CLBInst,
	SysCtl_CLBClkm: SysCtl_CLBClkm,
}
