let CLB_Inputs = [
	{ name: "CLB_IN0", displayName: "Input 0" },
	{ name: "CLB_IN1", displayName: "Input 1" },
	{ name: "CLB_IN2", displayName: "Input 2" },
	{ name: "CLB_IN3", displayName: "Input 3" },
	{ name: "CLB_IN4", displayName: "Input 4" },
	{ name: "CLB_IN5", displayName: "Input 5" },
	{ name: "CLB_IN6", displayName: "Input 6" },
	{ name: "CLB_IN7", displayName: "Input 7" },
]
let CLB_Outputs = [
	{ name: "CLB_OUT0", displayName: "Output 0" },
	{ name: "CLB_OUT1", displayName: "Output 1" },
	{ name: "CLB_OUT2", displayName: "Output 2" },
	{ name: "CLB_OUT3", displayName: "Output 3" },
	{ name: "CLB_OUT4", displayName: "Output 4" },
	{ name: "CLB_OUT5", displayName: "Output 5" },
	{ name: "CLB_OUT6", displayName: "Output 6" },
	{ name: "CLB_OUT7", displayName: "Output 7" },
]
let CLB_AOCs = [
	{ name: "CLB_AOC0", displayName: "AOC 0" },
	{ name: "CLB_AOC1", displayName: "AOC 1" },
	{ name: "CLB_AOC2", displayName: "AOC 2" },
	{ name: "CLB_AOC3", displayName: "AOC 3" },
	{ name: "CLB_AOC4", displayName: "AOC 4" },
	{ name: "CLB_AOC5", displayName: "AOC 5" },
	{ name: "CLB_AOC6", displayName: "AOC 6" },
	{ name: "CLB_AOC7", displayName: "AOC 7" },
]
let CLB_SWReleaseCtrl = [
	{ name: "CLB_SW_RLS_CTRL0", displayName: "SW RLS CTRL 0" },
	{ name: "CLB_SW_RLS_CTRL1", displayName: "SW RLS CTRL 1" },
	{ name: "CLB_SW_RLS_CTRL2", displayName: "SW RLS CTRL 2" },
	{ name: "CLB_SW_RLS_CTRL3", displayName: "SW RLS CTRL 3" },
	{ name: "CLB_SW_RLS_CTRL4", displayName: "SW RLS CTRL 4" },
	{ name: "CLB_SW_RLS_CTRL5", displayName: "SW RLS CTRL 5" },
	{ name: "CLB_SW_RLS_CTRL6", displayName: "SW RLS CTRL 6" },
	{ name: "CLB_SW_RLS_CTRL7", displayName: "SW RLS CTRL 7" },
]
let CLB_SWGateCtrl = [
	{ name: "CLB_SW_GATE_CTRL0", displayName: "SW GATE CTRL 0" },
	{ name: "CLB_SW_GATE_CTRL1", displayName: "SW GATE CTRL 1" },
	{ name: "CLB_SW_GATE_CTRL2", displayName: "SW GATE CTRL 2" },
	{ name: "CLB_SW_GATE_CTRL3", displayName: "SW GATE CTRL 3" },
	{ name: "CLB_SW_GATE_CTRL4", displayName: "SW GATE CTRL 4" },
	{ name: "CLB_SW_GATE_CTRL5", displayName: "SW GATE CTRL 5" },
	{ name: "CLB_SW_GATE_CTRL6", displayName: "SW GATE CTRL 6" },
	{ name: "CLB_SW_GATE_CTRL7", displayName: "SW GATE CTRL 7" },
]
let CLB_Counters = [
	{ name: "CLB_CTR0", displayName: "Counter 0" },
	{ name: "CLB_CTR1", displayName: "Counter 1" },
	{ name: "CLB_CTR2", displayName: "Counter 2" },
]
let CLB_Register = [
	{ name: "CLB_REG_HLC_R0", displayName: "HLC R0 register" },
	{ name: "CLB_REG_HLC_R1", displayName: "HLC R1 register" },
	{ name: "CLB_REG_HLC_R2", displayName: "HLC R2 register" },
	{ name: "CLB_REG_HLC_R3", displayName: "HLC R3 register" },
	{ name: "CLB_REG_CTR_C0", displayName: "Counter 0 register" },
	{ name: "CLB_REG_CTR_C1", displayName: "Counter 1 register" },
	{ name: "CLB_REG_CTR_C2", displayName: "Counter 2 register" },
]
let CLB_FilterType = [
	{ name: "CLB_FILTER_NONE", displayName: "No filtering" },
	{ name: "CLB_FILTER_RISING_EDGE", displayName: "Rising edge detect" },
	{ name: "CLB_FILTER_FALLING_EDGE", displayName: "Falling edge detect" },
	{ name: "CLB_FILTER_ANY_EDGE", displayName: "Any edge detect" },
]
let CLB_GPInputMux = [
	{ name: "CLB_GP_IN_MUX_EXTERNAL", displayName: "Use external input path" },
	{ name: "CLB_GP_IN_MUX_GP_REG", displayName: "Use CLB_GP_REG bit value as input" },
]
let CLB_LocalInputMux = [
	{ name: "CLB_LOCAL_IN_MUX_GLOBAL_IN", displayName: "Global input mux selection" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAEVT1", displayName: "EPWMx DCAEVT1" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAEVT2", displayName: "EPWMx DCAEVT2" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBEVT1", displayName: "EPWMx DCBEVT1" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBEVT2", displayName: "EPWMx DCBEVT2" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAH", displayName: "EPWMx DCAH" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAL", displayName: "EPWMx DCAL" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBH", displayName: "EPWMx DCBH" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBL", displayName: "EPWMx DCBL" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_OST", displayName: "EPWMx OST" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_CBC", displayName: "EPWMx CBC" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_ECAPIN", displayName: "ECAPx ECAPIN" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT", displayName: "ECAPx ECAP_OUT" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN", displayName: "ECAPx ECAP_OUT_EN" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT1", displayName: "ECAPx CEVT1" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT2", displayName: "ECAPx CEVT2" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT3", displayName: "ECAPx CEVT3" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT4", displayName: "ECAPx CEVT4" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPA", displayName: "EQEPx EQEPA" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPB", displayName: "EQEPx EQEPB" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPI", displayName: "EQEPx EQEPI" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPS", displayName: "EQEPx EQEPS" },
	{ name: "CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC", displayName: "CPU1.TBCLKSYNC" },
	{ name: "CLB_LOCAL_IN_MUX_LIN_TX", displayName: "LIN A/B TX" },
	{ name: "CLB_LOCAL_IN_MUX_CPU1_HALT", displayName: "CPU1.HALT" },
	{ name: "CLB_LOCAL_IN_MUX_SPISIMO_MASTER", displayName: "SPISIMO Master Output" },
	{ name: "CLB_LOCAL_IN_MUX_SPICLK", displayName: "SPI Clock" },
	{ name: "CLB_LOCAL_IN_MUX_SPISIMO_SLAVE", displayName: "SPISIMO Slave Input" },
	{ name: "CLB_LOCAL_IN_MUX_SPISTE", displayName: "SPI STE" },
	{ name: "CLB_LOCAL_IN_MUX_SCI_TX", displayName: "SCI TX" },
	{ name: "CLB_LOCAL_IN_MUX_SPISOMI_OUT", displayName: "SPISOMI(OUT)" },
	{ name: "CLB_LOCAL_IN_MUX_CLB_PSCLK", displayName: "CLB prescaled clock" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCAEVT1", displayName: "EPWM3 DCAEVT1 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCAEVT1", displayName: "EPWM4 DCAEVT1 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCAEVT2", displayName: "EPWM3 DCAEVT2 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCAEVT2", displayName: "EPWM4 DCBEVT2 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCBEVT1", displayName: "EPWM3 DCBEVT1 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCBEVT1", displayName: "EPWM4 DCBEVT1 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCBEVT2", displayName: "EPWM3 DCBEVT2 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCBEVT2", displayName: "EPWM4 DCBEVT2 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCAH", displayName: "EPWM3 DCAH (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCAH", displayName: "EPWM4 DCAH (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCAL", displayName: "EPWM3 DCAL (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCAL", displayName: "EPWM4 DCAL (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCBH", displayName: "EPWM3 DCBH (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCBH", displayName: "EPWM4 DCBH (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_DCBL", displayName: "EPWM3 DCBL (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_DCBL", displayName: "EPWM4 DCBL (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_OST", displayName: "EPWM3 OST (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_OST", displayName: "EPWM4 OST (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM3_CBC", displayName: "EPWM3 CBC (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM4_CBC", displayName: "EPWM4 CBC (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM5_DCAEVT1", displayName: "EPWM5 DCAEVT1 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM6_DCAEVT1", displayName: "EPWM6 DCAEVT1 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM5_DCAEVT2", displayName: "EPWM5 DCAEVT2 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM6_DCAEVT2", displayName: "EPWM6 DCBEVT2 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM5_DCBEVT1", displayName: "EPWM5 DCBEVT1 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM6_DCBEVT1", displayName: "EPWM6 DCBEVT1 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM5_DCBEVT2", displayName: "EPWM5 DCBEVT2 (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM6_DCBEVT2", displayName: "EPWM6 DCBEVT2 (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM5_DCAH", displayName: "EPWM5 DCAH (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM6_DCAH", displayName: "EPWM6 DCAH (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM5_DCAL", displayName: "EPWM5 DCAL (CLB1)" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM6_DCAL", displayName: "EPWM6 DCAL (CLB2)" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT1", displayName: "CLBINPUTXBAR INPUT1" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT2", displayName: "CLBINPUTXBAR INPUT2" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT3", displayName: "CLBINPUTXBAR INPUT3" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT4", displayName: "CLBINPUTXBAR INPUT4" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT5", displayName: "CLBINPUTXBAR INPUT5" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT6", displayName: "CLBINPUTXBAR INPUT6" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT7", displayName: "CLBINPUTXBAR INPUT7" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT8", displayName: "CLBINPUTXBAR INPUT8" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT9", displayName: "CLBINPUTXBAR INPUT9" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT10", displayName: "CLBINPUTXBAR INPUT10" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT11", displayName: "CLBINPUTXBAR INPUT11" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT12", displayName: "CLBINPUTXBAR INPUT12" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT13", displayName: "CLBINPUTXBAR INPUT13" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT14", displayName: "CLBINPUTXBAR INPUT14" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT15", displayName: "CLBINPUTXBAR INPUT15" },
	{ name: "CLB_LOCAL_IN_MUX_INPUT16", displayName: "CLBINPUTXBAR INPUT16" },
]
let CLB_GlobalInputMux = [
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A", displayName: "EPWM1A" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A_OE", displayName: "EPWM1A trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B", displayName: "EPWM1B" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B_OE", displayName: "EPWM1B trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO", displayName: "EPWM1 TBCTR = Zero" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD", displayName: "EPWM1 TBCTR = TBPRD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR", displayName: "EPWM1 CTRDIR" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_TBCLK", displayName: "EPWM1 TBCLK" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA", displayName: "EPWM1 TBCTR = CMPA" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB", displayName: "EPWM1 TBCTR = CMPB" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC", displayName: "EPWM1 TBCTR = CMPC" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD", displayName: "EPWM1 TBCTR = CMPD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A_AQ", displayName: "EPWM1A AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B_AQ", displayName: "EPWM1B AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A_DB", displayName: "EPWM1A DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B_DB", displayName: "EPWM1B DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A", displayName: "EPWM2A (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6A", displayName: "EPWM6A (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A_OE", displayName: "EPWM2A trip output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6A_OE", displayName: "EPWM6A trip output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B", displayName: "EPWM2B (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6B", displayName: "EPWM6B (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B_OE", displayName: "EPWM2B trip output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6B_OE", displayName: "EPWM6B trip output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO", displayName: "EPWM2 TBCTR = Zero (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_CTR_ZERO", displayName: "EPWM6 TBCTR = Zero (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD", displayName: "EPWM2 TBCTR = TBPRD (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_CTR_PRD", displayName: "EPWM6 TBCTR = TBPRD (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR", displayName: "EPWM2 CTRDIR (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_CTRDIR", displayName: "EPWM6 CTRDIR (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_TBCLK", displayName: "EPWM2 TBCLK (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_TBCLK", displayName: "EPWM6 TBCLK (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA", displayName: "EPWM2 TBCTR = CMPA (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPA", displayName: "EPWM6 TBCTR = CMPA (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB", displayName: "EPWM2 TBCTR = CMPB (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPB", displayName: "EPWM6 TBCTR = CMPB (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC", displayName: "EPWM2 TBCTR = CMPC (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPC", displayName: "EPWM6 TBCTR = CMPC (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD", displayName: "EPWM2 TBCTR = CMPD (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_CTR_CMPD", displayName: "EPWM6 TBCTR = CMPD (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A_AQ", displayName: "EPWM2A AQ submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6A_AQ", displayName: "EPWM6A AQ submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B_AQ", displayName: "EPWM2B AQ submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6B_AQ", displayName: "EPWM6B AQ submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A_DB", displayName: "EPWM2A DB submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6A_DB", displayName: "EPWM6A DB submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B_DB", displayName: "EPWM2B DB submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6B_DB", displayName: "EPWM6B DB submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A", displayName: "EPWM3A (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7A", displayName: "EPWM7A (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A_OE", displayName: "EPWM3A trip output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7A_OE", displayName: "EPWM7A trip output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B", displayName: "EPWM3B (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7B", displayName: "EPWM7B (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B_OE", displayName: "EPWM3B trip output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7B_OE", displayName: "EPWM7B trip output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO", displayName: "EPWM3 TBCTR = Zero (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_CTR_ZERO", displayName: "EPWM7 TBCTR = Zero (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD", displayName: "EPWM3 TBCTR = TBPRD (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_CTR_PRD", displayName: "EPWM7 TBCTR = TBPRD (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR", displayName: "EPWM3 CTRDIR (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_CTRDIR", displayName: "EPWM7 CTRDIR (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_TBCLK", displayName: "EPWM3 TBCLK (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_TBCLK", displayName: "EPWM7 TBCLK (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA", displayName: "EPWM3 TBCTR = CMPA (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPA", displayName: "EPWM7 TBCTR = CMPA (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB", displayName: "EPWM3 TBCTR = CMPB (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPB", displayName: "EPWM7 TBCTR = CMPB (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC", displayName: "EPWM3 TBCTR = CMPC (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPC", displayName: "EPWM7 TBCTR = CMPC (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD", displayName: "EPWM3 TBCTR = CMPD (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7_CTR_CMPD", displayName: "EPWM7 TBCTR = CMPD (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A_AQ", displayName: "EPWM3A AQ submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7A_AQ", displayName: "EPWM7A AQ submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B_AQ", displayName: "EPWM3B AQ submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7B_AQ", displayName: "EPWM7B AQ submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A_DB", displayName: "EPWM3A DB submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7A_DB", displayName: "EPWM7A DB submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B_DB", displayName: "EPWM3B DB submodule output (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM7B_DB", displayName: "EPWM7B DB submodule output (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A", displayName: "EPWM4A" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A_OE", displayName: "EPWM4A trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B", displayName: "EPWM4B" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B_OE", displayName: "EPWM4B trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO", displayName: "EPWM4 TBCTR = Zero" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD", displayName: "EPWM4 TBCTR = TBPRD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR", displayName: "EPWM4 CTRDIR" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_TBCLK", displayName: "EPWM4 TBCLK" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA", displayName: "EPWM4 TBCTR = CMPA" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB", displayName: "EPWM4 TBCTR = CMPB" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC", displayName: "EPWM4 TBCTR = CMPC" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD", displayName: "EPWM4 TBCTR = CMPD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A_AQ", displayName: "EPWM4A AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B_AQ", displayName: "EPWM4B AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A_DB", displayName: "EPWM4A DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B_DB", displayName: "EPWM4B DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG0", displayName: "CLB X-BAR AUXSIG0" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG1", displayName: "CLB X-BAR AUXSIG1" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG2", displayName: "CLB X-BAR AUXSIG2" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG3", displayName: "CLB X-BAR AUXSIG3" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG4", displayName: "CLB X-BAR AUXSIG4" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG5", displayName: "CLB X-BAR AUXSIG5" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG6", displayName: "CLB X-BAR AUXSIG6" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG7", displayName: "CLB X-BAR AUXSIG7" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT16", displayName: "CLB1 OUT16" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT17", displayName: "CLB1 OUT17" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT18", displayName: "CLB1 OUT18" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT19", displayName: "CLB1 OUT19" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT20", displayName: "CLB1 OUT20" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT21", displayName: "CLB1 OUT21" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT22", displayName: "CLB1 OUT22" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB1_OUT23", displayName: "CLB1 OUT23" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT16", displayName: "CLB2 OUT16" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT17", displayName: "CLB2 OUT17" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT18", displayName: "CLB2 OUT18" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT19", displayName: "CLB2 OUT19" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT20", displayName: "CLB2 OUT20" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT21", displayName: "CLB2 OUT21" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT22", displayName: "CLB2 OUT22" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB2_OUT23", displayName: "CLB2 OUT23" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5A", displayName: "EPWM5A" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5A_OE", displayName: "EPWM5A trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5B", displayName: "EPWM5B" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5B_OE", displayName: "EPWM5B trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CTR_ZERO", displayName: "EPWM5 TBCTR = Zero" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CTR_PRD", displayName: "EPWM5 TBCTR = TBPRD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CTRDIR", displayName: "EPWM5 CTRDIR" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_TBCLK", displayName: "EPWM5 TBCLK" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPA", displayName: "EPWM5 TBCTR = CMPA" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPB", displayName: "EPWM5 TBCTR = CMPB" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPC", displayName: "EPWM5 TBCTR = CMPC" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CTR_CMPD", displayName: "EPWM5 TBCTR = CMPD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5A_AQ", displayName: "EPWM5A AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5B_AQ", displayName: "EPWM5B AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5A_DB", displayName: "EPWM5A DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5B_DB", displayName: "EPWM5B DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT0", displayName: "CPU1 ERAD Event 0" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT1", displayName: "CPU1 ERAD Event 1" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT2", displayName: "CPU1 ERAD Event 2" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT3", displayName: "CPU1 ERAD Event 3" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT4", displayName: "CPU1 ERAD Event 4" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT5", displayName: "CPU1 ERAD Event 5" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT6", displayName: "CPU1 ERAD Event 6" },
	{ name: "CLB_GLOBAL_IN_MUX_CPU1_ERAD_EVENT7", displayName: "CPU1 ERAD Event 7" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_PING_TAG_MATCH", displayName: "FSIRXA PING TAG Match" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_DATA_TAG_MATCH", displayName: "FSIRXA DATA TAG Match" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_TAG_MATCH", displayName: "FSIRXA ERROR TAG Match" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_OUTPUT_FRAME_DONE", displayName: "FSIRXA Output Frame Done (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_ECAP3_ECAPIN", displayName: "ECAP3 ECAPIN (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_DATA_PACKET_RCVD", displayName: "FSIRXA Data Packet Received (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_ECAP3_ECAP_OUT", displayName: "ECAP3 ECAP_OUT (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_ERROR_PACKET_RCVD", displayName: "FSIRXA Error Packet Received (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_ECAP3_ECAP_OUT_EN", displayName: "ECAP3 ECAP_OUT_EN (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_PING_PACKET_RCVD", displayName: "FSIRXA PING Packet Received (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_ECAP3_CEVT1", displayName: "ECAP3 CEVT1 (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_FSIRXA_PACKET_TAG3", displayName: "FSIRXA Packet TAG3 (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_ECAP3_CEVT2", displayName: "ECAP3 CEVT2 (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_SPI1_SPICLK", displayName: "SPI1 SPICLK OUT (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_ECAP3_CEVT3", displayName: "ECAP3 CEVT3 (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER", displayName: "SPI1 SPISOMI Master IN (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_ECAP3_CEVT4", displayName: "ECAP3 CEVT4 (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_SPI1_SPISTE", displayName: "SPI1 SPISTE OUT (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_OST", displayName: "EPWM5 OST (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_SPI2_SPICLK", displayName: "SPI2 SPICLK OUT (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_CBC", displayName: "EPWM5 CBC (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER", displayName: "SPI2 SPISOMI Master IN (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_OST", displayName: "EPWM6 OST (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_SPI2_SPISTE", displayName: "SPI2 SPISTE OUT (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWm6_CBC", displayName: "EPWM6 CBC (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_DCBH", displayName: "EPWM5 DCBH (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_DCBH", displayName: "EPWM6 DCBH (CLB2)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM5_DCBL", displayName: "EPWM5 DCBL (CLB1)" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM6_DCBL", displayName: "EPWM6 DCBL (CLB2)" },
]
exports = {
	CLB_Inputs: CLB_Inputs,
	CLB_Outputs: CLB_Outputs,
	CLB_AOCs: CLB_AOCs,
	CLB_SWReleaseCtrl: CLB_SWReleaseCtrl,
	CLB_SWGateCtrl: CLB_SWGateCtrl,
	CLB_Counters: CLB_Counters,
	CLB_Register: CLB_Register,
	CLB_FilterType: CLB_FilterType,
	CLB_GPInputMux: CLB_GPInputMux,
	CLB_LocalInputMux: CLB_LocalInputMux,
	CLB_GlobalInputMux: CLB_GlobalInputMux,
}
