let CLB_Inputs = [
	{ name: "CLB_IN0", displayName: "Input 0" },
	{ name: "CLB_IN1", displayName: "Input 1" },
	{ name: "CLB_IN2", displayName: "Input 2" },
	{ name: "CLB_IN3", displayName: "Input 3" },
	{ name: "CLB_IN4", displayName: "Input 4" },
	{ name: "CLB_IN5", displayName: "Input 5" },
	{ name: "CLB_IN6", displayName: "Input 6" },
	{ name: "CLB_IN7", displayName: "Input 7" },
]
let CLB_Outputs = [
	{ name: "CLB_OUT0", displayName: "Output 0" },
	{ name: "CLB_OUT1", displayName: "Output 1" },
	{ name: "CLB_OUT2", displayName: "Output 2" },
	{ name: "CLB_OUT3", displayName: "Output 3" },
	{ name: "CLB_OUT4", displayName: "Output 4" },
	{ name: "CLB_OUT5", displayName: "Output 5" },
	{ name: "CLB_OUT6", displayName: "Output 6" },
	{ name: "CLB_OUT7", displayName: "Output 7" },
]
let CLB_Counters = [
	{ name: "CLB_CTR0", displayName: "Counter 0" },
	{ name: "CLB_CTR1", displayName: "Counter 1" },
	{ name: "CLB_CTR2", displayName: "Counter 2" },
]
let CLB_Register = [
	{ name: "CLB_REG_HLC_R0", displayName: "HLC R0 register" },
	{ name: "CLB_REG_HLC_R1", displayName: "HLC R1 register" },
	{ name: "CLB_REG_HLC_R2", displayName: "HLC R2 register" },
	{ name: "CLB_REG_HLC_R3", displayName: "HLC R3 register" },
	{ name: "CLB_REG_CTR_C0", displayName: "Counter 0 register" },
	{ name: "CLB_REG_CTR_C1", displayName: "Counter 1 register" },
	{ name: "CLB_REG_CTR_C2", displayName: "Counter 2 register" },
]
let CLB_FilterType = [
	{ name: "CLB_FILTER_NONE", displayName: "No filtering" },
	{ name: "CLB_FILTER_RISING_EDGE", displayName: "Rising edge detect" },
	{ name: "CLB_FILTER_FALLING_EDGE", displayName: "Falling edge detect" },
	{ name: "CLB_FILTER_ANY_EDGE", displayName: "Any edge detect" },
]
let CLB_GPInputMux = [
	{ name: "CLB_GP_IN_MUX_EXTERNAL", displayName: "Use external input path" },
	{ name: "CLB_GP_IN_MUX_GP_REG", displayName: "Use CLB_GP_REG bit value as input" },
]
let CLB_LocalInputMux = [
	{ name: "CLB_LOCAL_IN_MUX_GLOBAL_IN", displayName: "Global input mux selection" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAEVT1", displayName: "EPWMx DCAEVT1" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAEVT2", displayName: "EPWMx DCAEVT2" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBEVT1", displayName: "EPWMx DCBEVT1" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBEVT2", displayName: "EPWMx DCBEVT2" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAH", displayName: "EPWMx DCAH" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCAL", displayName: "EPWMx DCAL" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBH", displayName: "EPWMx DCBH" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_DCBL", displayName: "EPWMx DCBL" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_OST", displayName: "EPWMx OST" },
	{ name: "CLB_LOCAL_IN_MUX_EPWM_CBC", displayName: "EPWMx CBC" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_ECAPIN", displayName: "ECAPx ECAPIN" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT", displayName: "ECAPx ECAP_OUT" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN", displayName: "ECAPx ECAP_OUT_EN" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT1", displayName: "ECAPx CEVT1" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT2", displayName: "ECAPx CEVT2" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT3", displayName: "ECAPx CEVT3" },
	{ name: "CLB_LOCAL_IN_MUX_ECAP_CEVT4", displayName: "ECAPx CEVT4" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPA", displayName: "EQEPx EQEPA" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPB", displayName: "EQEPx EQEPB" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPI", displayName: "EQEPx EQEPI" },
	{ name: "CLB_LOCAL_IN_MUX_EQEP_EQEPS", displayName: "EQEPx EQEPS" },
	{ name: "CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC", displayName: "CPU1.TBCLKSYNC" },
	{ name: "CLB_LOCAL_IN_MUX_CPU2_TBCLKSYNC", displayName: "CPU2.TBCLKSYNC" },
	{ name: "CLB_LOCAL_IN_MUX_CPU1_HALT", displayName: "CPU1.HALT" },
	{ name: "CLB_LOCAL_IN_MUX_CPU2_HALT", displayName: "CPU2.HALT" },
]
let CLB_GlobalInputMux = [
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A", displayName: "EPWM1A" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A_OE", displayName: "EPWM1A trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B", displayName: "EPWM1B" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B_OE", displayName: "EPWM1B trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO", displayName: "EPWM1 TBCTR = Zero" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD", displayName: "EPWM1 TBCTR = TBPRD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR", displayName: "EPWM1 CTRDIR" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_TBCLK", displayName: "EPWM1 TBCLK" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA", displayName: "EPWM1 TBCTR = CMPA" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB", displayName: "EPWM1 TBCTR = CMPB" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC", displayName: "EPWM1 TBCTR = CMPC" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD", displayName: "EPWM1 TBCTR = CMPD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A_AQ", displayName: "EPWM1A AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B_AQ", displayName: "EPWM1B AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1A_DB", displayName: "EPWM1A DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM1B_DB", displayName: "EPWM1B DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A", displayName: "EPWM2A" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A_OE", displayName: "EPWM2A trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B", displayName: "EPWM2B" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B_OE", displayName: "EPWM2B trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO", displayName: "EPWM2 TBCTR = Zero" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD", displayName: "EPWM2 TBCTR = TBPRD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR", displayName: "EPWM2 CTRDIR" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_TBCLK", displayName: "EPWM2 TBCLK" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA", displayName: "EPWM2 TBCTR = CMPA" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB", displayName: "EPWM2 TBCTR = CMPB" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC", displayName: "EPWM2 TBCTR = CMPC" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD", displayName: "EPWM2 TBCTR = CMPD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A_AQ", displayName: "EPWM2A AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B_AQ", displayName: "EPWM2B AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2A_DB", displayName: "EPWM2A DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM2B_DB", displayName: "EPWM2B DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A", displayName: "EPWM3A" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A_OE", displayName: "EPWM3A trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B", displayName: "EPWM3B" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B_OE", displayName: "EPWM3B trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO", displayName: "EPWM3 TBCTR = Zero" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD", displayName: "EPWM3 TBCTR = TBPRD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR", displayName: "EPWM3 CTRDIR" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_TBCLK", displayName: "EPWM3 TBCLK" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA", displayName: "EPWM3 TBCTR = CMPA" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB", displayName: "EPWM3 TBCTR = CMPB" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC", displayName: "EPWM3 TBCTR = CMPC" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD", displayName: "EPWM3 TBCTR = CMPD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A_AQ", displayName: "EPWM3A AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B_AQ", displayName: "EPWM3B AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3A_DB", displayName: "EPWM3A DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM3B_DB", displayName: "EPWM3B DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A", displayName: "EPWM4A" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A_OE", displayName: "EPWM4A trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B", displayName: "EPWM4B" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B_OE", displayName: "EPWM4B trip output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO", displayName: "EPWM4 TBCTR = Zero" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD", displayName: "EPWM4 TBCTR = TBPRD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR", displayName: "EPWM4 CTRDIR" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_TBCLK", displayName: "EPWM4 TBCLK" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA", displayName: "EPWM4 TBCTR = CMPA" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB", displayName: "EPWM4 TBCTR = CMPB" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC", displayName: "EPWM4 TBCTR = CMPC" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD", displayName: "EPWM4 TBCTR = CMPD" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A_AQ", displayName: "EPWM4A AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B_AQ", displayName: "EPWM4B AQ submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4A_DB", displayName: "EPWM4A DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_EPWM4B_DB", displayName: "EPWM4B DB submodule output" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG0", displayName: "CLB X-BAR AUXSIG0" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG1", displayName: "CLB X-BAR AUXSIG1" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG2", displayName: "CLB X-BAR AUXSIG2" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG3", displayName: "CLB X-BAR AUXSIG3" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG4", displayName: "CLB X-BAR AUXSIG4" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG5", displayName: "CLB X-BAR AUXSIG5" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG6", displayName: "CLB X-BAR AUXSIG6" },
	{ name: "CLB_GLOBAL_IN_MUX_CLB_AUXSIG7", displayName: "CLB X-BAR AUXSIG7" },
]
exports = {
	CLB_Inputs: CLB_Inputs,
	CLB_Outputs: CLB_Outputs,
	CLB_Counters: CLB_Counters,
	CLB_Register: CLB_Register,
	CLB_FilterType: CLB_FilterType,
	CLB_GPInputMux: CLB_GPInputMux,
	CLB_LocalInputMux: CLB_LocalInputMux,
	CLB_GlobalInputMux: CLB_GlobalInputMux,
}
