/*
 * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include "board.h"

//*****************************************************************************
//
// Board Configurations
// Initializes the rest of the modules. 
// Call this function in your application if you wish to do all module 
// initialization.
// If you wish to not use some of the initializations, instead of the 
// Board_init use the individual Module_inits
//
//*****************************************************************************
void Board_init()
{
	EALLOW;

	PinMux_init();
	SYSCTL_init();
	INPUTXBAR_init();
	SYNC_init();
	ASYSCTL_init();
	ADC_init();
	CMPSS_init();
	CMPSSLITE_init();
	CPUTIMER_init();
	EPWM_init();
	EPWMXBAR_init();
	GPIO_init();
	OTHER_init();
	SPI_init();
	INTERRUPT_init();

	EDIS;
}

//*****************************************************************************
//
// PINMUX Configurations
//
//*****************************************************************************
void PinMux_init()
{
	//
	// PinMux for modules assigned to CPU1
	//
	
	//
	// ANALOG -> PFC_MOTORS_EMI Pinmux
	//
	// Analog PinMux for A0/C15/CMP1_DACL
	GPIO_setPinConfig(GPIO_231_GPIO231);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(231, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A1
	GPIO_setPinConfig(GPIO_232_GPIO232);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(232, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A10/C10, GPIO230
	GPIO_setPinConfig(GPIO_230_GPIO230);
	// AGPIO -> Analog mode selected
	GPIO_setAnalogMode(230, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A11/C0
	GPIO_setPinConfig(GPIO_237_GPIO237);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(237, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A12/C1
	GPIO_setPinConfig(GPIO_238_GPIO238);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(238, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A15/C7
	GPIO_setPinConfig(GPIO_233_GPIO233);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(233, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A2/C9, GPIO224
	GPIO_setPinConfig(GPIO_224_GPIO224);
	// AGPIO -> Analog mode selected
	GPIO_setAnalogMode(224, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A3/C5, GPIO242
	GPIO_setPinConfig(GPIO_242_GPIO242);
	// AGPIO -> Analog mode selected
	GPIO_setAnalogMode(242, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A4/C14
	GPIO_setPinConfig(GPIO_225_GPIO225);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(225, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A5/C2
	GPIO_setPinConfig(GPIO_244_GPIO244);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(244, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A6, GPIO228
	GPIO_setPinConfig(GPIO_228_GPIO228);
	// AGPIO -> Analog mode selected
	GPIO_setAnalogMode(228, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A7/C3
	GPIO_setPinConfig(GPIO_245_GPIO245);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(245, GPIO_ANALOG_ENABLED);
	// Analog PinMux for A8/C11
	GPIO_setPinConfig(GPIO_241_GPIO241);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(241, GPIO_ANALOG_ENABLED);
	// Analog PinMux for C4/A14
	GPIO_setPinConfig(GPIO_239_GPIO239);
	// AIO -> Analog mode selected
	GPIO_setAnalogMode(239, GPIO_ANALOG_ENABLED);
	// Analog PinMux for C6, GPIO226
	GPIO_setPinConfig(GPIO_226_GPIO226);
	// AGPIO -> Analog mode selected
	GPIO_setAnalogMode(226, GPIO_ANALOG_ENABLED);
	// Analog PinMux for C8/A9, GPIO227
	GPIO_setPinConfig(GPIO_227_GPIO227);
	// AGPIO -> Analog mode selected
	GPIO_setAnalogMode(227, GPIO_ANALOG_ENABLED);
	//
	// EPWM1 -> MTR1_PWM_U Pinmux
	//
	GPIO_setPinConfig(MTR1_PWM_U_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(MTR1_PWM_U_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR1_PWM_U_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(MTR1_PWM_U_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(MTR1_PWM_U_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR1_PWM_U_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM2 -> MTR2_PWM_W Pinmux
	//
	GPIO_setPinConfig(MTR2_PWM_W_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(MTR2_PWM_W_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR2_PWM_W_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(MTR2_PWM_W_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(MTR2_PWM_W_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR2_PWM_W_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM3 -> MTR1_PWM_V Pinmux
	//
	GPIO_setPinConfig(MTR1_PWM_V_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(MTR1_PWM_V_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR1_PWM_V_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(MTR1_PWM_V_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(MTR1_PWM_V_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR1_PWM_V_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM4 -> MTR2_PWM_U Pinmux
	//
	GPIO_setPinConfig(MTR2_PWM_U_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(MTR2_PWM_U_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR2_PWM_U_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(MTR2_PWM_U_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(MTR2_PWM_U_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR2_PWM_U_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM5 -> MTR1_PWM_W Pinmux
	//
	GPIO_setPinConfig(MTR1_PWM_W_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(MTR1_PWM_W_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR1_PWM_W_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(MTR1_PWM_W_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(MTR1_PWM_W_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR1_PWM_W_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM6 -> MTR2_PWM_V Pinmux
	//
	GPIO_setPinConfig(MTR2_PWM_V_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(MTR2_PWM_V_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR2_PWM_V_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(MTR2_PWM_V_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(MTR2_PWM_V_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(MTR2_PWM_V_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM7 -> PFC_PWM Pinmux
	//
	GPIO_setPinConfig(PFC_PWM_EPWMA_PIN_CONFIG);
	// AGPIO -> GPIO mode selected
	GPIO_setAnalogMode(12, GPIO_ANALOG_DISABLED);
	GPIO_setPadConfig(PFC_PWM_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(PFC_PWM_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(PFC_PWM_EPWMB_PIN_CONFIG);
	// AGPIO -> GPIO mode selected
	GPIO_setAnalogMode(13, GPIO_ANALOG_DISABLED);
	GPIO_setPadConfig(PFC_PWM_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(PFC_PWM_EPWMB_GPIO, GPIO_QUAL_SYNC);

	// GPIO22 -> MTR1_PM_nFAULT_GPIO Pinmux
	GPIO_setPinConfig(GPIO_22_GPIO22);
	// GPIO23 -> MTR2_PM_nFAULT_GPIO Pinmux
	GPIO_setPinConfig(GPIO_23_GPIO23);
	// GPIO18, X2 -> ACPOWER_RELAY_GPIO Pinmux
	GPIO_setPinConfig(GPIO_18_GPIO18);
	// A17/C17, GPIO20 -> FOURWAY_RELAY_GPIO Pinmux
	GPIO_setPinConfig(GPIO_20_GPIO20);
	// AGPIO -> GPIO mode selected
	GPIO_setAnalogMode(20, GPIO_ANALOG_DISABLED);
	// GPIO32 -> EEV_STEPPER_2H_GPIO Pinmux
	GPIO_setPinConfig(GPIO_32_GPIO32);
	// GPIO17 -> EMI_INJ_PD_GPIO Pinmux
	GPIO_setPinConfig(GPIO_17_GPIO17);
	// GPIO16 -> EMI_INJ_PU_GPIO Pinmux
	GPIO_setPinConfig(GPIO_16_GPIO16);
	// GPIO11 -> EMI_INJ_MD_GPIO Pinmux
	GPIO_setPinConfig(GPIO_11_GPIO11);
	// GPIO2 -> EEV_STEPPER_1H_GPIO Pinmux
	GPIO_setPinConfig(GPIO_2_GPIO2);
	// GPIO3 -> EEV_STEPPER_1L_GPIO Pinmux
	GPIO_setPinConfig(GPIO_3_GPIO3);
	// GPIO33 -> EMI_RESET_GPIO Pinmux
	GPIO_setPinConfig(GPIO_33_GPIO33);
	//
	// OTHER -> cJTAG Pinmux
	//
	//
	// SPIA -> DAC_SPI Pinmux
	//
	GPIO_setPinConfig(DAC_SPI_SPIPICO_PIN_CONFIG);
	GPIO_setPadConfig(DAC_SPI_SPIPICO_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DAC_SPI_SPIPICO_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(DAC_SPI_SPICLK_PIN_CONFIG);
	// AGPIO -> GPIO mode selected
	GPIO_setAnalogMode(28, GPIO_ANALOG_DISABLED);
	GPIO_setPadConfig(DAC_SPI_SPICLK_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DAC_SPI_SPICLK_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(DAC_SPI_SPIPTE_PIN_CONFIG);
	GPIO_setPadConfig(DAC_SPI_SPIPTE_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DAC_SPI_SPIPTE_GPIO, GPIO_QUAL_ASYNC);


}

//*****************************************************************************
//
// ADC Configurations
//
//*****************************************************************************
void ADC_init(){
	MTR1_EMI_init();
	PFC_MTRS_init();
}

void MTR1_EMI_init(){
	//
	// ADC Initialization: Write ADC configurations and power up the ADC
	//
	// Configures the ADC module's offset trim
	//
	ADC_setOffsetTrimAll(ADC_REFERENCE_INTERNAL,ADC_REFERENCE_3_3V);
	//
	// Configures the analog-to-digital converter module prescaler.
	//
	ADC_setPrescaler(MTR1_EMI_BASE, ADC_CLK_DIV_4_0);
	//
	// Sets the timing of the end-of-conversion pulse
	//
	ADC_setInterruptPulseMode(MTR1_EMI_BASE, ADC_PULSE_END_OF_ACQ_WIN);
	//
	// Sets the timing of early interrupt generation.
	//
	ADC_setInterruptCycleOffset(MTR1_EMI_BASE, 0U);
	//
	// Powers up the analog-to-digital converter core.
	//
	ADC_enableConverter(MTR1_EMI_BASE);
	//
	// Delay for 1ms to allow ADC time to power up
	//
	DEVICE_DELAY_US(5000);
	//
	// SOC Configuration: Setup ADC EPWM channel and trigger settings
	//
	// Disables SOC burst mode.
	//
	ADC_disableBurstMode(MTR1_EMI_BASE);
	//
	// Sets the priority mode of the SOCs.
	//
	ADC_setSOCPriority(MTR1_EMI_BASE, ADC_PRI_THRU_SOC3_HIPRI);
	//
	// Start of Conversion 0 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 0
	//	  	Trigger			: ADC_TRIGGER_EPWM3_SOCA
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(MTR1_EMI_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM3_SOCA, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(MTR1_EMI_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 1 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 1
	//	  	Trigger			: ADC_TRIGGER_EPWM3_SOCB
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(MTR1_EMI_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM3_SOCB, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(MTR1_EMI_BASE, ADC_SOC_NUMBER1, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 2 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 2
	//	  	Trigger			: ADC_TRIGGER_EPWM5_SOCA
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(MTR1_EMI_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM5_SOCA, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(MTR1_EMI_BASE, ADC_SOC_NUMBER2, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 3 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 3
	//	  	Trigger			: ADC_TRIGGER_EPWM5_SOCB
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(MTR1_EMI_BASE, ADC_SOC_NUMBER3, ADC_TRIGGER_EPWM5_SOCB, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(MTR1_EMI_BASE, ADC_SOC_NUMBER3, ADC_INT_SOC_TRIGGER_NONE);
			
	//
	// PPB Configuration: Configure high and low limits detection for ADCPPB
	//
	// Post Processing Block 1 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 1
	// 		SOC/EOC number			: 0
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(MTR1_EMI_BASE, ADC_PPB_NUMBER1, ADC_SOC_NUMBER0);
	ADC_disablePPBEvent(MTR1_EMI_BASE, ADC_PPB_NUMBER1, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(MTR1_EMI_BASE, ADC_PPB_NUMBER1, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER1, 0);
	ADC_setPPBReferenceOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER1, 0);
	ADC_disablePPBTwosComplement(MTR1_EMI_BASE, ADC_PPB_NUMBER1);
	ADC_setPPBTripLimits(MTR1_EMI_BASE, ADC_PPB_NUMBER1, 0, 0);
	ADC_disablePPBEventCBCClear(MTR1_EMI_BASE, ADC_PPB_NUMBER1);
	//
	// Post Processing Block 2 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 2
	// 		SOC/EOC number			: 1
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(MTR1_EMI_BASE, ADC_PPB_NUMBER2, ADC_SOC_NUMBER1);
	ADC_disablePPBEvent(MTR1_EMI_BASE, ADC_PPB_NUMBER2, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(MTR1_EMI_BASE, ADC_PPB_NUMBER2, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER2, 0);
	ADC_setPPBReferenceOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER2, 0);
	ADC_disablePPBTwosComplement(MTR1_EMI_BASE, ADC_PPB_NUMBER2);
	ADC_setPPBTripLimits(MTR1_EMI_BASE, ADC_PPB_NUMBER2, 0, 0);
	ADC_disablePPBEventCBCClear(MTR1_EMI_BASE, ADC_PPB_NUMBER2);
	//
	// Post Processing Block 3 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 3
	// 		SOC/EOC number			: 2
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(MTR1_EMI_BASE, ADC_PPB_NUMBER3, ADC_SOC_NUMBER2);
	ADC_disablePPBEvent(MTR1_EMI_BASE, ADC_PPB_NUMBER3, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(MTR1_EMI_BASE, ADC_PPB_NUMBER3, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER3, 0);
	ADC_setPPBReferenceOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER3, 0);
	ADC_disablePPBTwosComplement(MTR1_EMI_BASE, ADC_PPB_NUMBER3);
	ADC_setPPBTripLimits(MTR1_EMI_BASE, ADC_PPB_NUMBER3, 0, 0);
	ADC_disablePPBEventCBCClear(MTR1_EMI_BASE, ADC_PPB_NUMBER3);
	//
	// Post Processing Block 4 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 4
	// 		SOC/EOC number			: 3
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(MTR1_EMI_BASE, ADC_PPB_NUMBER4, ADC_SOC_NUMBER3);
	ADC_disablePPBEvent(MTR1_EMI_BASE, ADC_PPB_NUMBER4, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(MTR1_EMI_BASE, ADC_PPB_NUMBER4, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER4, 0);
	ADC_setPPBReferenceOffset(MTR1_EMI_BASE, ADC_PPB_NUMBER4, 0);
	ADC_disablePPBTwosComplement(MTR1_EMI_BASE, ADC_PPB_NUMBER4);
	ADC_setPPBTripLimits(MTR1_EMI_BASE, ADC_PPB_NUMBER4, 0, 0);
	ADC_disablePPBEventCBCClear(MTR1_EMI_BASE, ADC_PPB_NUMBER4);
}
void PFC_MTRS_init(){
	//
	// ADC Initialization: Write ADC configurations and power up the ADC
	//
	// Configures the ADC module's offset trim
	//
	ADC_setOffsetTrimAll(ADC_REFERENCE_INTERNAL,ADC_REFERENCE_3_3V);
	//
	// Configures the analog-to-digital converter module prescaler.
	//
	ADC_setPrescaler(PFC_MTRS_BASE, ADC_CLK_DIV_4_0);
	//
	// Sets the timing of the end-of-conversion pulse
	//
	ADC_setInterruptPulseMode(PFC_MTRS_BASE, ADC_PULSE_END_OF_CONV);
	//
	// Powers up the analog-to-digital converter core.
	//
	ADC_enableConverter(PFC_MTRS_BASE);
	//
	// Delay for 1ms to allow ADC time to power up
	//
	DEVICE_DELAY_US(5000);
	//
	// SOC Configuration: Setup ADC EPWM channel and trigger settings
	//
	// Disables SOC burst mode.
	//
	ADC_disableBurstMode(PFC_MTRS_BASE);
	//
	// Sets the priority mode of the SOCs.
	//
	ADC_setSOCPriority(PFC_MTRS_BASE, ADC_PRI_SOC0_HIPRI);
	//
	// Start of Conversion 0 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 0
	//	  	Trigger			: ADC_TRIGGER_EPWM7_SOCA
	//	  	Channel			: ADC_CH_ADCIN9
	//	 	Sample Window	: 14 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN9, 14U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 1 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 1
	//	  	Trigger			: ADC_TRIGGER_EPWM7_SOCA
	//	  	Channel			: ADC_CH_ADCIN10
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN10, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER1, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 2 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 2
	//	  	Trigger			: ADC_TRIGGER_EPWM7_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM7_SOCA, ADC_CH_ADCIN4, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER2, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 3 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 3
	//	  	Trigger			: ADC_TRIGGER_EPWM7_SOCB
	//	  	Channel			: ADC_CH_ADCIN9
	//	 	Sample Window	: 14 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER3, ADC_TRIGGER_EPWM7_SOCB, ADC_CH_ADCIN9, 14U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER3, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 4 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 4
	//	  	Trigger			: ADC_TRIGGER_EPWM7_SOCB
	//	  	Channel			: ADC_CH_ADCIN10
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER4, ADC_TRIGGER_EPWM7_SOCB, ADC_CH_ADCIN10, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER4, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 5 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 5
	//	  	Trigger			: ADC_TRIGGER_EPWM7_SOCB
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER5, ADC_TRIGGER_EPWM7_SOCB, ADC_CH_ADCIN4, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER5, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 6 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 6
	//	  	Trigger			: ADC_TRIGGER_EPWM1_SOCA
	//	  	Channel			: ADC_CH_ADCIN8
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER6, ADC_TRIGGER_EPWM1_SOCA, ADC_CH_ADCIN8, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER6, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 7 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 7
	//	  	Trigger			: ADC_TRIGGER_EPWM1_SOCA
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER7, ADC_TRIGGER_EPWM1_SOCA, ADC_CH_ADCIN1, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER7, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 8 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 8
	//	  	Trigger			: ADC_TRIGGER_EPWM1_SOCA
	//	  	Channel			: ADC_CH_ADCIN5
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER8, ADC_TRIGGER_EPWM1_SOCA, ADC_CH_ADCIN5, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER8, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 9 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 9
	//	  	Trigger			: ADC_TRIGGER_EPWM4_SOCA
	//	  	Channel			: ADC_CH_ADCIN2
	//	 	Sample Window	: 14 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER9, ADC_TRIGGER_EPWM4_SOCA, ADC_CH_ADCIN2, 14U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER9, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 10 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 10
	//	  	Trigger			: ADC_TRIGGER_EPWM4_SOCA
	//	  	Channel			: ADC_CH_ADCIN6
	//	 	Sample Window	: 14 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER10, ADC_TRIGGER_EPWM4_SOCA, ADC_CH_ADCIN6, 14U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER10, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 11 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 11
	//	  	Trigger			: ADC_TRIGGER_EPWM4_SOCA
	//	  	Channel			: ADC_CH_ADCIN3
	//	 	Sample Window	: 14 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER11, ADC_TRIGGER_EPWM4_SOCA, ADC_CH_ADCIN3, 14U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER11, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 12 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 12
	//	  	Trigger			: ADC_TRIGGER_EPWM4_SOCA
	//	  	Channel			: ADC_CH_ADCIN11
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER12, ADC_TRIGGER_EPWM4_SOCA, ADC_CH_ADCIN11, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER12, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 13 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 13
	//	  	Trigger			: ADC_TRIGGER_EPWM4_SOCA
	//	  	Channel			: ADC_CH_ADCIN14
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER13, ADC_TRIGGER_EPWM4_SOCA, ADC_CH_ADCIN14, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER13, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 14 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 14
	//	  	Trigger			: ADC_TRIGGER_EPWM4_SOCA
	//	  	Channel			: ADC_CH_ADCIN15
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(PFC_MTRS_BASE, ADC_SOC_NUMBER14, ADC_TRIGGER_EPWM4_SOCA, ADC_CH_ADCIN15, 20U);
	ADC_setInterruptSOCTrigger(PFC_MTRS_BASE, ADC_SOC_NUMBER14, ADC_INT_SOC_TRIGGER_NONE);
	//
	// ADC Interrupt 2 Configuration
	// 		Source	: ADC_SOC_NUMBER2
	// 		Interrupt Source: enabled
	//		Continuous Mode	: enabled
	//
	//
	ADC_setInterruptSource(PFC_MTRS_BASE, ADC_INT_NUMBER2, ADC_SOC_NUMBER2);
	ADC_clearInterruptStatus(PFC_MTRS_BASE, ADC_INT_NUMBER2);
	ADC_enableContinuousMode(PFC_MTRS_BASE, ADC_INT_NUMBER2);
	ADC_enableInterrupt(PFC_MTRS_BASE, ADC_INT_NUMBER2);
	//
	// ADC Interrupt 3 Configuration
	// 		Source	: ADC_SOC_NUMBER8
	// 		Interrupt Source: enabled
	//		Continuous Mode	: enabled
	//
	//
	ADC_setInterruptSource(PFC_MTRS_BASE, ADC_INT_NUMBER3, ADC_SOC_NUMBER8);
	ADC_clearInterruptStatus(PFC_MTRS_BASE, ADC_INT_NUMBER3);
	ADC_enableContinuousMode(PFC_MTRS_BASE, ADC_INT_NUMBER3);
	ADC_enableInterrupt(PFC_MTRS_BASE, ADC_INT_NUMBER3);
	//
	// ADC Interrupt 4 Configuration
	// 		Source	: ADC_SOC_NUMBER14
	// 		Interrupt Source: enabled
	//		Continuous Mode	: enabled
	//
	//
	ADC_setInterruptSource(PFC_MTRS_BASE, ADC_INT_NUMBER4, ADC_SOC_NUMBER14);
	ADC_clearInterruptStatus(PFC_MTRS_BASE, ADC_INT_NUMBER4);
	ADC_enableContinuousMode(PFC_MTRS_BASE, ADC_INT_NUMBER4);
	ADC_enableInterrupt(PFC_MTRS_BASE, ADC_INT_NUMBER4);
			
	//
	// PPB Configuration: Configure high and low limits detection for ADCPPB
	//
	// Post Processing Block 1 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 1
	// 		SOC/EOC number			: 0
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(PFC_MTRS_BASE, ADC_PPB_NUMBER1, ADC_SOC_NUMBER0);
	ADC_disablePPBEvent(PFC_MTRS_BASE, ADC_PPB_NUMBER1, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(PFC_MTRS_BASE, ADC_PPB_NUMBER1, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER1, 0);
	ADC_setPPBReferenceOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER1, 0);
	ADC_disablePPBTwosComplement(PFC_MTRS_BASE, ADC_PPB_NUMBER1);
	ADC_setPPBTripLimits(PFC_MTRS_BASE, ADC_PPB_NUMBER1, 0, 0);
	ADC_disablePPBEventCBCClear(PFC_MTRS_BASE, ADC_PPB_NUMBER1);
	//
	// Post Processing Block 2 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 2
	// 		SOC/EOC number			: 1
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(PFC_MTRS_BASE, ADC_PPB_NUMBER2, ADC_SOC_NUMBER1);
	ADC_disablePPBEvent(PFC_MTRS_BASE, ADC_PPB_NUMBER2, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(PFC_MTRS_BASE, ADC_PPB_NUMBER2, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER2, 0);
	ADC_setPPBReferenceOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER2, 0);
	ADC_disablePPBTwosComplement(PFC_MTRS_BASE, ADC_PPB_NUMBER2);
	ADC_setPPBTripLimits(PFC_MTRS_BASE, ADC_PPB_NUMBER2, 0, 0);
	ADC_disablePPBEventCBCClear(PFC_MTRS_BASE, ADC_PPB_NUMBER2);
	//
	// Post Processing Block 3 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 3
	// 		SOC/EOC number			: 3
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(PFC_MTRS_BASE, ADC_PPB_NUMBER3, ADC_SOC_NUMBER3);
	ADC_disablePPBEvent(PFC_MTRS_BASE, ADC_PPB_NUMBER3, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(PFC_MTRS_BASE, ADC_PPB_NUMBER3, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER3, 0);
	ADC_setPPBReferenceOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER3, 0);
	ADC_disablePPBTwosComplement(PFC_MTRS_BASE, ADC_PPB_NUMBER3);
	ADC_setPPBTripLimits(PFC_MTRS_BASE, ADC_PPB_NUMBER3, 0, 0);
	ADC_disablePPBEventCBCClear(PFC_MTRS_BASE, ADC_PPB_NUMBER3);
	//
	// Post Processing Block 4 Configuration
	// 		Configures a post-processing block (PPB) in the ADC.
	// 		PPB Number				: 4
	// 		SOC/EOC number			: 4
	// 		Calibration Offset		: 0
	// 		Reference Offset		: 0
	// 		Two's Complement		: Disabled
	// 		Trip High Limit			: 0
	// 		Trip Low Limit			: 0
	// 		Clear PPB Event Flags	: Disabled
	//
	ADC_setupPPB(PFC_MTRS_BASE, ADC_PPB_NUMBER4, ADC_SOC_NUMBER4);
	ADC_disablePPBEvent(PFC_MTRS_BASE, ADC_PPB_NUMBER4, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_disablePPBEventInterrupt(PFC_MTRS_BASE, ADC_PPB_NUMBER4, (ADC_EVT_TRIPHI | ADC_EVT_TRIPLO | ADC_EVT_ZERO));
	ADC_setPPBCalibrationOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER4, 0);
	ADC_setPPBReferenceOffset(PFC_MTRS_BASE, ADC_PPB_NUMBER4, 0);
	ADC_disablePPBTwosComplement(PFC_MTRS_BASE, ADC_PPB_NUMBER4);
	ADC_setPPBTripLimits(PFC_MTRS_BASE, ADC_PPB_NUMBER4, 0, 0);
	ADC_disablePPBEventCBCClear(PFC_MTRS_BASE, ADC_PPB_NUMBER4);
}

//*****************************************************************************
//
// ASYSCTL Configurations
//
//*****************************************************************************
void ASYSCTL_init(){
	//
	// asysctl initialization
	//
	// Enables the temperature sensor output to the ADC.
	//
	ASysCtl_enableTemperatureSensor();
	DEVICE_DELAY_US(500);
	//
	// Set the analog voltage reference selection to internal.
	//
	ASysCtl_setAnalogReferenceInternal( ASYSCTL_VREFHI );
	//
	// Set the internal analog voltage reference selection to 1.65V.
	//
	ASysCtl_setAnalogReference1P65( ASYSCTL_VREFHI );
}
//*****************************************************************************
//
// CMPSS Configurations
//
//*****************************************************************************
void CMPSS_init(){
	MTR2_CMPSS_UV_init();
}

void MTR2_CMPSS_UV_init(){
    //
    // Select the value for CMP1HPMXSEL.
    //
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1,0U);
    //
    // Select the value for CMP1LPMXSEL.
    //
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1,2U);
    //
    // Sets the configuration for the high comparator.
    //
    CMPSS_configHighComparator(MTR2_CMPSS_UV_BASE,(CMPSS_INSRC_DAC));
    //
    // Sets the configuration for the low comparator.
    //
    CMPSS_configLowComparator(MTR2_CMPSS_UV_BASE,(CMPSS_INSRC_DAC | CMPSS_INV_INVERTED));
    //
    // Sets the configuration for the internal comparator DACs.
    //
    CMPSS_configDAC(MTR2_CMPSS_UV_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW));
    //
    // Sets the value of the internal DAC of the high comparator.
    //
    CMPSS_setDACValueHigh(MTR2_CMPSS_UV_BASE,3096U);
    //
    // Sets the value of the internal DAC of the low comparator.
    //
    CMPSS_setDACValueLow(MTR2_CMPSS_UV_BASE,1024U);
    //
    //  Configures the digital filter of the high comparator.
    //
    CMPSS_configFilterHigh(MTR2_CMPSS_UV_BASE, 16U, 16U, 12U);
    //
    // Configures the digital filter of the low comparator.
    //
    CMPSS_configFilterLow(MTR2_CMPSS_UV_BASE, 16U, 16U, 12U);
    //
    // Initializes the digital filter of the high comparator.
    //
    CMPSS_initFilterHigh(MTR2_CMPSS_UV_BASE);
    //
    // Initializes the digital filter of the low comparator.
    //
    CMPSS_initFilterLow(MTR2_CMPSS_UV_BASE);
    //
    // Sets the output signal configuration for the high comparator.
    //
    CMPSS_configOutputsHigh(MTR2_CMPSS_UV_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the output signal configuration for the low comparator.
    //
    CMPSS_configOutputsLow(MTR2_CMPSS_UV_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the comparator hysteresis settings.
    //
    CMPSS_setHysteresis(MTR2_CMPSS_UV_BASE,0U);
    //
    // Configures the comparator subsystem's ramp generator.
    //
    CMPSS_configRamp(MTR2_CMPSS_UV_BASE,0U,0U,0U,1U,true);
    //
    // Disables reset of HIGH comparator digital filter output latch on PWMSYNC
    //
    CMPSS_disableLatchResetOnPWMSYNCHigh(MTR2_CMPSS_UV_BASE);
    //
    // Disables reset of LOW comparator digital filter output latch on PWMSYNC
    //
    CMPSS_disableLatchResetOnPWMSYNCLow(MTR2_CMPSS_UV_BASE);
    //
    // Sets the ePWM module blanking signal that holds trip in reset.
    //
    CMPSS_configBlanking(MTR2_CMPSS_UV_BASE,1U);
    //
    // Disables an ePWM blanking signal from holding trip in reset.
    //
    CMPSS_disableBlanking(MTR2_CMPSS_UV_BASE);
    //
    // Configures whether or not the digital filter latches are reset by PWMSYNC
    //
    CMPSS_configLatchOnPWMSYNC(MTR2_CMPSS_UV_BASE,false,false);
    //
    // Enables the CMPSS module.
    //
    CMPSS_enableModule(MTR2_CMPSS_UV_BASE);
    //
    // Delay for CMPSS DAC to power up.
    //
    DEVICE_DELAY_US(500);
    //
    // Causes a software reset of the high comparator digital filter output latch.
    //
    CMPSS_clearFilterLatchHigh(MTR2_CMPSS_UV_BASE);
    //
    // Causes a software reset of the low comparator digital filter output latch.
    //
    CMPSS_clearFilterLatchLow(MTR2_CMPSS_UV_BASE);
}

//*****************************************************************************
//
// CMPSS-LITE Configurations
//
//*****************************************************************************
void CMPSSLITE_init(){
	PFC_CMPSS_VIAC_init();
	MTRS_CMPSS_UW_init();
	MTR1_CMPSS_IDC_init();
}

void PFC_CMPSS_VIAC_init(){
    //
    // Select the value for CMP2HPMXSEL.
    //
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_2,2U);
    //
    // Select the value for CMP2LPMXSEL.
    //
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_2,0U);
    //
    // Sets the configuration for the high comparator.
    //
    CMPSSLITE_configHighComparator(PFC_CMPSS_VIAC_BASE,(CMPSS_INSRC_DAC));
    //
    // Sets the configuration for the low comparator.
    //
    CMPSSLITE_configLowComparator(PFC_CMPSS_VIAC_BASE,(CMPSS_INSRC_DAC | CMPSS_INV_INVERTED));
    //
    // Sets the configuration for the internal comparator DACs.
    //
    CMPSSLITE_configDAC(PFC_CMPSS_VIAC_BASE, CMPSS_DACVAL_SYSCLK);
    //
    // Sets the value of the internal DAC of the high comparator.
    //
    CMPSSLITE_setDACValueHigh(PFC_CMPSS_VIAC_BASE,3096U);
    //
    // Sets the value of the internal DAC of the low comparator.
    //
    CMPSSLITE_setDACValueLow(PFC_CMPSS_VIAC_BASE,1024U);
    //
    //  Configures the digital filter of the high comparator.
    //
    CMPSSLITE_configFilterHigh(PFC_CMPSS_VIAC_BASE, 32U, 32U, 30U);
    //
    // Configures the digital filter of the low comparator.
    //
    CMPSSLITE_configFilterLow(PFC_CMPSS_VIAC_BASE, 32U, 32U, 30U);
    //
    // Initializes the digital filter of the high comparator.
    //
    CMPSSLITE_initFilterHigh(PFC_CMPSS_VIAC_BASE);
    //
    // Initializes the digital filter of the low comparator.
    //
    CMPSSLITE_initFilterLow(PFC_CMPSS_VIAC_BASE);
    //
    // Sets the output signal configuration for the high comparator.
    //
    CMPSSLITE_configOutputsHigh(PFC_CMPSS_VIAC_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the output signal configuration for the low comparator.
    //
    CMPSSLITE_configOutputsLow(PFC_CMPSS_VIAC_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the comparator hysteresis settings.
    //
    CMPSSLITE_setHysteresis(PFC_CMPSS_VIAC_BASE,1U);
    //
    // Disables reset of HIGH comparator digital filter output latch on PWMSYNC
    //
    CMPSSLITE_disableLatchResetOnPWMSYNCHigh(PFC_CMPSS_VIAC_BASE);
    //
    // Disables reset of LOW comparator digital filter output latch on PWMSYNC
    //
    CMPSSLITE_disableLatchResetOnPWMSYNCLow(PFC_CMPSS_VIAC_BASE);
    //
    // Sets the ePWM module blanking signal that holds trip in reset.
    //
    CMPSSLITE_configBlanking(PFC_CMPSS_VIAC_BASE,7U);
    //
    // Disables an ePWM blanking signal from holding trip in reset.
    //
    CMPSSLITE_disableBlanking(PFC_CMPSS_VIAC_BASE);
    //
    // Configures whether or not the digital filter latches are reset by PWMSYNC
    //
    CMPSSLITE_configLatchOnPWMSYNC(PFC_CMPSS_VIAC_BASE,false,false);
    //
    // Enables the CMPSSLITE module.
    //
    CMPSSLITE_enableModule(PFC_CMPSS_VIAC_BASE);
    //
    // Delay for CMPSSLITE DAC to power up.
    //
    DEVICE_DELAY_US(500);
    //
    // Causes a software reset of the high comparator digital filter output latch.
    //
    CMPSSLITE_clearFilterLatchHigh(PFC_CMPSS_VIAC_BASE);
    //
    // Causes a software reset of the low comparator digital filter output latch.
    //
    CMPSSLITE_clearFilterLatchLow(PFC_CMPSS_VIAC_BASE);
}
void MTRS_CMPSS_UW_init(){
    //
    // Select the value for CMP3HPMXSEL.
    //
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_3,2U);
    //
    // Select the value for CMP3LPMXSEL.
    //
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_3,2U);
    //
    // Sets the configuration for the high comparator.
    //
    CMPSSLITE_configHighComparator(MTRS_CMPSS_UW_BASE,(CMPSS_INSRC_DAC));
    //
    // Sets the configuration for the low comparator.
    //
    CMPSSLITE_configLowComparator(MTRS_CMPSS_UW_BASE,(CMPSS_INSRC_DAC | CMPSS_INV_INVERTED));
    //
    // Sets the configuration for the internal comparator DACs.
    //
    CMPSSLITE_configDAC(MTRS_CMPSS_UW_BASE, CMPSS_DACVAL_SYSCLK);
    //
    // Sets the value of the internal DAC of the high comparator.
    //
    CMPSSLITE_setDACValueHigh(MTRS_CMPSS_UW_BASE,3096U);
    //
    // Sets the value of the internal DAC of the low comparator.
    //
    CMPSSLITE_setDACValueLow(MTRS_CMPSS_UW_BASE,1024U);
    //
    //  Configures the digital filter of the high comparator.
    //
    CMPSSLITE_configFilterHigh(MTRS_CMPSS_UW_BASE, 32U, 32U, 30U);
    //
    // Configures the digital filter of the low comparator.
    //
    CMPSSLITE_configFilterLow(MTRS_CMPSS_UW_BASE, 32U, 32U, 30U);
    //
    // Initializes the digital filter of the high comparator.
    //
    CMPSSLITE_initFilterHigh(MTRS_CMPSS_UW_BASE);
    //
    // Initializes the digital filter of the low comparator.
    //
    CMPSSLITE_initFilterLow(MTRS_CMPSS_UW_BASE);
    //
    // Sets the output signal configuration for the high comparator.
    //
    CMPSSLITE_configOutputsHigh(MTRS_CMPSS_UW_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the output signal configuration for the low comparator.
    //
    CMPSSLITE_configOutputsLow(MTRS_CMPSS_UW_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the comparator hysteresis settings.
    //
    CMPSSLITE_setHysteresis(MTRS_CMPSS_UW_BASE,1U);
    //
    // Disables reset of HIGH comparator digital filter output latch on PWMSYNC
    //
    CMPSSLITE_disableLatchResetOnPWMSYNCHigh(MTRS_CMPSS_UW_BASE);
    //
    // Disables reset of LOW comparator digital filter output latch on PWMSYNC
    //
    CMPSSLITE_disableLatchResetOnPWMSYNCLow(MTRS_CMPSS_UW_BASE);
    //
    // Sets the ePWM module blanking signal that holds trip in reset.
    //
    CMPSSLITE_configBlanking(MTRS_CMPSS_UW_BASE,1U);
    //
    // Disables an ePWM blanking signal from holding trip in reset.
    //
    CMPSSLITE_disableBlanking(MTRS_CMPSS_UW_BASE);
    //
    // Configures whether or not the digital filter latches are reset by PWMSYNC
    //
    CMPSSLITE_configLatchOnPWMSYNC(MTRS_CMPSS_UW_BASE,false,false);
    //
    // Enables the CMPSSLITE module.
    //
    CMPSSLITE_enableModule(MTRS_CMPSS_UW_BASE);
    //
    // Delay for CMPSSLITE DAC to power up.
    //
    DEVICE_DELAY_US(500);
    //
    // Causes a software reset of the high comparator digital filter output latch.
    //
    CMPSSLITE_clearFilterLatchHigh(MTRS_CMPSS_UW_BASE);
    //
    // Causes a software reset of the low comparator digital filter output latch.
    //
    CMPSSLITE_clearFilterLatchLow(MTRS_CMPSS_UW_BASE);
}
void MTR1_CMPSS_IDC_init(){
    //
    // Select the value for CMP4HPMXSEL.
    //
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_4,2U);
    //
    // Select the value for CMP4LPMXSEL.
    //
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_4,2U);
    //
    // Sets the configuration for the high comparator.
    //
    CMPSSLITE_configHighComparator(MTR1_CMPSS_IDC_BASE,(CMPSS_INSRC_DAC));
    //
    // Sets the configuration for the low comparator.
    //
    CMPSSLITE_configLowComparator(MTR1_CMPSS_IDC_BASE,(CMPSS_INSRC_DAC | CMPSS_INV_INVERTED));
    //
    // Sets the configuration for the internal comparator DACs.
    //
    CMPSSLITE_configDAC(MTR1_CMPSS_IDC_BASE, CMPSS_DACVAL_SYSCLK);
    //
    // Sets the value of the internal DAC of the high comparator.
    //
    CMPSSLITE_setDACValueHigh(MTR1_CMPSS_IDC_BASE,3096U);
    //
    // Sets the value of the internal DAC of the low comparator.
    //
    CMPSSLITE_setDACValueLow(MTR1_CMPSS_IDC_BASE,1024U);
    //
    //  Configures the digital filter of the high comparator.
    //
    CMPSSLITE_configFilterHigh(MTR1_CMPSS_IDC_BASE, 32U, 32U, 30U);
    //
    // Configures the digital filter of the low comparator.
    //
    CMPSSLITE_configFilterLow(MTR1_CMPSS_IDC_BASE, 32U, 32U, 30U);
    //
    // Initializes the digital filter of the high comparator.
    //
    CMPSSLITE_initFilterHigh(MTR1_CMPSS_IDC_BASE);
    //
    // Initializes the digital filter of the low comparator.
    //
    CMPSSLITE_initFilterLow(MTR1_CMPSS_IDC_BASE);
    //
    // Sets the output signal configuration for the high comparator.
    //
    CMPSSLITE_configOutputsHigh(MTR1_CMPSS_IDC_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the output signal configuration for the low comparator.
    //
    CMPSSLITE_configOutputsLow(MTR1_CMPSS_IDC_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER));
    //
    // Sets the comparator hysteresis settings.
    //
    CMPSSLITE_setHysteresis(MTR1_CMPSS_IDC_BASE,1U);
    //
    // Disables reset of HIGH comparator digital filter output latch on PWMSYNC
    //
    CMPSSLITE_disableLatchResetOnPWMSYNCHigh(MTR1_CMPSS_IDC_BASE);
    //
    // Disables reset of LOW comparator digital filter output latch on PWMSYNC
    //
    CMPSSLITE_disableLatchResetOnPWMSYNCLow(MTR1_CMPSS_IDC_BASE);
    //
    // Sets the ePWM module blanking signal that holds trip in reset.
    //
    CMPSSLITE_configBlanking(MTR1_CMPSS_IDC_BASE,1U);
    //
    // Disables an ePWM blanking signal from holding trip in reset.
    //
    CMPSSLITE_disableBlanking(MTR1_CMPSS_IDC_BASE);
    //
    // Configures whether or not the digital filter latches are reset by PWMSYNC
    //
    CMPSSLITE_configLatchOnPWMSYNC(MTR1_CMPSS_IDC_BASE,false,false);
    //
    // Enables the CMPSSLITE module.
    //
    CMPSSLITE_enableModule(MTR1_CMPSS_IDC_BASE);
    //
    // Delay for CMPSSLITE DAC to power up.
    //
    DEVICE_DELAY_US(500);
    //
    // Causes a software reset of the high comparator digital filter output latch.
    //
    CMPSSLITE_clearFilterLatchHigh(MTR1_CMPSS_IDC_BASE);
    //
    // Causes a software reset of the low comparator digital filter output latch.
    //
    CMPSSLITE_clearFilterLatchLow(MTR1_CMPSS_IDC_BASE);
}

//*****************************************************************************
//
// CPUTIMER Configurations
//
//*****************************************************************************
void CPUTIMER_init(){
	CPU_TIMER0_init();
	CPU_TIMER1_init();
	CPU_TIMER2_init();
}

void CPU_TIMER0_init(){
	CPUTimer_setEmulationMode(CPU_TIMER0_BASE, CPUTIMER_EMULATIONMODE_RUNFREE);
	CPUTimer_setPreScaler(CPU_TIMER0_BASE, 0U);
	CPUTimer_setPeriod(CPU_TIMER0_BASE, 100000U);
	CPUTimer_disableInterrupt(CPU_TIMER0_BASE);
	CPUTimer_stopTimer(CPU_TIMER0_BASE);

	CPUTimer_reloadTimerCounter(CPU_TIMER0_BASE);
	CPUTimer_startTimer(CPU_TIMER0_BASE);
}
void CPU_TIMER1_init(){
	CPUTimer_setEmulationMode(CPU_TIMER1_BASE, CPUTIMER_EMULATIONMODE_RUNFREE);
	CPUTimer_setPreScaler(CPU_TIMER1_BASE, 0U);
	CPUTimer_setPeriod(CPU_TIMER1_BASE, 500000U);
	CPUTimer_disableInterrupt(CPU_TIMER1_BASE);
	CPUTimer_stopTimer(CPU_TIMER1_BASE);

	CPUTimer_reloadTimerCounter(CPU_TIMER1_BASE);
	CPUTimer_startTimer(CPU_TIMER1_BASE);
}
void CPU_TIMER2_init(){
	CPUTimer_setEmulationMode(CPU_TIMER2_BASE, CPUTIMER_EMULATIONMODE_RUNFREE);
	CPUTimer_selectClockSource(CPU_TIMER2_BASE, CPUTIMER_CLOCK_SOURCE_SYS, CPUTIMER_CLOCK_PRESCALER_1);
	CPUTimer_setPreScaler(CPU_TIMER2_BASE, 0U);
	CPUTimer_setPeriod(CPU_TIMER2_BASE, 4294967295U);
	CPUTimer_disableInterrupt(CPU_TIMER2_BASE);
	CPUTimer_stopTimer(CPU_TIMER2_BASE);

	CPUTimer_reloadTimerCounter(CPU_TIMER2_BASE);
	CPUTimer_startTimer(CPU_TIMER2_BASE);
}

//*****************************************************************************
//
// EPWM Configurations
//
//*****************************************************************************
void EPWM_init(){
    EPWM_setEmulationMode(MTR1_PWM_U_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(MTR1_PWM_U_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(MTR1_PWM_U_BASE, 5000);	
    EPWM_setTimeBaseCounter(MTR1_PWM_U_BASE, 0);	
    EPWM_setTimeBaseCounterMode(MTR1_PWM_U_BASE, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(MTR1_PWM_U_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(MTR1_PWM_U_BASE);	
    EPWM_setPhaseShift(MTR1_PWM_U_BASE, 0);	
    EPWM_setSyncPulseSource(MTR1_PWM_U_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_U_BASE, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR1_PWM_U_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_U_BASE, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR1_PWM_U_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_U_BASE, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(MTR1_PWM_U_BASE, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(MTR1_PWM_U_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(MTR1_PWM_U_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(MTR1_PWM_U_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(MTR1_PWM_U_BASE, 240);	
    EPWM_setDeadBandDelayMode(MTR1_PWM_U_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(MTR1_PWM_U_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(MTR1_PWM_U_BASE, 240);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(MTR1_PWM_U_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(MTR1_PWM_U_BASE);	
    EPWM_setTripZoneAction(MTR1_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(MTR1_PWM_U_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT1);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_U_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_U_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_U_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_U_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableInterrupt(MTR1_PWM_U_BASE);	
    EPWM_setInterruptSource(MTR1_PWM_U_BASE, EPWM_INT_TBCTR_ZERO);	
    EPWM_setInterruptEventCount(MTR1_PWM_U_BASE, 1);	
    EPWM_enableADCTrigger(MTR1_PWM_U_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(MTR1_PWM_U_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(MTR1_PWM_U_BASE, EPWM_SOC_A, 1);	
    EPWM_enableADCTrigger(MTR1_PWM_U_BASE, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(MTR1_PWM_U_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_D_CMPD);	
    EPWM_setADCTriggerEventPrescale(MTR1_PWM_U_BASE, EPWM_SOC_B, 1);	
    EPWM_setEmulationMode(MTR2_PWM_W_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(MTR2_PWM_W_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(MTR2_PWM_W_BASE, 5000);	
    EPWM_setTimeBaseCounter(MTR2_PWM_W_BASE, 0);	
    EPWM_setTimeBaseCounterMode(MTR2_PWM_W_BASE, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(MTR2_PWM_W_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(MTR2_PWM_W_BASE);	
    EPWM_setPhaseShift(MTR2_PWM_W_BASE, 0);	
    EPWM_setSyncPulseSource(MTR2_PWM_W_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_W_BASE, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR2_PWM_W_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_W_BASE, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR2_PWM_W_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_W_BASE, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(MTR2_PWM_W_BASE, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(MTR2_PWM_W_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(MTR2_PWM_W_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(MTR2_PWM_W_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(MTR2_PWM_W_BASE, 240);	
    EPWM_setDeadBandDelayMode(MTR2_PWM_W_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(MTR2_PWM_W_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(MTR2_PWM_W_BASE, 240);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(MTR2_PWM_W_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(MTR2_PWM_W_BASE);	
    EPWM_setTripZoneAction(MTR2_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(MTR2_PWM_W_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT2);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_W_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_W_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_W_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_W_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableADCTrigger(MTR2_PWM_W_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(MTR2_PWM_W_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPC);	
    EPWM_setADCTriggerEventPrescale(MTR2_PWM_W_BASE, EPWM_SOC_A, 1);	
    EPWM_enableADCTrigger(MTR2_PWM_W_BASE, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(MTR2_PWM_W_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_U_CMPD);	
    EPWM_setADCTriggerEventPrescale(MTR2_PWM_W_BASE, EPWM_SOC_B, 1);	
    EPWM_setEmulationMode(MTR1_PWM_V_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(MTR1_PWM_V_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(MTR1_PWM_V_BASE, 5000);	
    EPWM_setTimeBaseCounter(MTR1_PWM_V_BASE, 0);	
    EPWM_setTimeBaseCounterMode(MTR1_PWM_V_BASE, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(MTR1_PWM_V_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(MTR1_PWM_V_BASE);	
    EPWM_setPhaseShift(MTR1_PWM_V_BASE, 0);	
    EPWM_setSyncPulseSource(MTR1_PWM_V_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_V_BASE, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR1_PWM_V_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_V_BASE, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR1_PWM_V_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_V_BASE, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(MTR1_PWM_V_BASE, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(MTR1_PWM_V_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(MTR1_PWM_V_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(MTR1_PWM_V_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(MTR1_PWM_V_BASE, 240);	
    EPWM_setDeadBandDelayMode(MTR1_PWM_V_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(MTR1_PWM_V_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(MTR1_PWM_V_BASE, 240);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(MTR1_PWM_V_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(MTR1_PWM_V_BASE);	
    EPWM_setTripZoneAction(MTR1_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(MTR1_PWM_V_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT1);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_V_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_V_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_V_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_V_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableADCTrigger(MTR1_PWM_V_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(MTR1_PWM_V_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPC);	
    EPWM_setADCTriggerEventPrescale(MTR1_PWM_V_BASE, EPWM_SOC_A, 1);	
    EPWM_enableADCTrigger(MTR1_PWM_V_BASE, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(MTR1_PWM_V_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_U_CMPD);	
    EPWM_setADCTriggerEventPrescale(MTR1_PWM_V_BASE, EPWM_SOC_B, 1);	
    EPWM_setEmulationMode(MTR2_PWM_U_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(MTR2_PWM_U_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(MTR2_PWM_U_BASE, 5000);	
    EPWM_setTimeBaseCounter(MTR2_PWM_U_BASE, 0);	
    EPWM_setTimeBaseCounterMode(MTR2_PWM_U_BASE, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(MTR2_PWM_U_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(MTR2_PWM_U_BASE);	
    EPWM_setPhaseShift(MTR2_PWM_U_BASE, 0);	
    EPWM_setSyncPulseSource(MTR2_PWM_U_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_U_BASE, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR2_PWM_U_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_U_BASE, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR2_PWM_U_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_U_BASE, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(MTR2_PWM_U_BASE, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_U_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(MTR2_PWM_U_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(MTR2_PWM_U_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(MTR2_PWM_U_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(MTR2_PWM_U_BASE, 245);	
    EPWM_setDeadBandDelayMode(MTR2_PWM_U_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(MTR2_PWM_U_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(MTR2_PWM_U_BASE, 225);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(MTR2_PWM_U_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(MTR2_PWM_U_BASE);	
    EPWM_setTripZoneAction(MTR2_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_U_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(MTR2_PWM_U_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT2);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_U_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_U_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_U_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_U_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_U_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_U_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_U_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableInterrupt(MTR2_PWM_U_BASE);	
    EPWM_setInterruptSource(MTR2_PWM_U_BASE, EPWM_INT_TBCTR_ZERO);	
    EPWM_setInterruptEventCount(MTR2_PWM_U_BASE, 3);	
    EPWM_enableADCTrigger(MTR2_PWM_U_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(MTR2_PWM_U_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(MTR2_PWM_U_BASE, EPWM_SOC_A, 3);	
    EPWM_enableADCTrigger(MTR2_PWM_U_BASE, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(MTR2_PWM_U_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_D_CMPD);	
    EPWM_setADCTriggerEventPrescale(MTR2_PWM_U_BASE, EPWM_SOC_B, 3);	
    EPWM_setEmulationMode(MTR1_PWM_W_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(MTR1_PWM_W_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(MTR1_PWM_W_BASE, 5000);	
    EPWM_setTimeBaseCounter(MTR1_PWM_W_BASE, 0);	
    EPWM_setTimeBaseCounterMode(MTR1_PWM_W_BASE, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(MTR1_PWM_W_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(MTR1_PWM_W_BASE);	
    EPWM_setPhaseShift(MTR1_PWM_W_BASE, 0);	
    EPWM_setSyncPulseSource(MTR1_PWM_W_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_W_BASE, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR1_PWM_W_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_W_BASE, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR1_PWM_W_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR1_PWM_W_BASE, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(MTR1_PWM_W_BASE, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR1_PWM_W_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(MTR1_PWM_W_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(MTR1_PWM_W_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(MTR1_PWM_W_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(MTR1_PWM_W_BASE, 240);	
    EPWM_setDeadBandDelayMode(MTR1_PWM_W_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(MTR1_PWM_W_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(MTR1_PWM_W_BASE, 240);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(MTR1_PWM_W_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(MTR1_PWM_W_BASE);	
    EPWM_setTripZoneAction(MTR1_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR1_PWM_W_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(MTR1_PWM_W_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT1);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_W_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_W_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(MTR1_PWM_W_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR1_PWM_W_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR1_PWM_W_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_W_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR1_PWM_W_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableADCTrigger(MTR1_PWM_W_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(MTR1_PWM_W_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_D_CMPC);	
    EPWM_setADCTriggerEventPrescale(MTR1_PWM_W_BASE, EPWM_SOC_A, 1);	
    EPWM_enableADCTrigger(MTR1_PWM_W_BASE, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(MTR1_PWM_W_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_D_CMPD);	
    EPWM_setADCTriggerEventPrescale(MTR1_PWM_W_BASE, EPWM_SOC_B, 1);	
    EPWM_setEmulationMode(MTR2_PWM_V_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(MTR2_PWM_V_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(MTR2_PWM_V_BASE, 5000);	
    EPWM_setTimeBaseCounter(MTR2_PWM_V_BASE, 0);	
    EPWM_setTimeBaseCounterMode(MTR2_PWM_V_BASE, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(MTR2_PWM_V_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(MTR2_PWM_V_BASE);	
    EPWM_setPhaseShift(MTR2_PWM_V_BASE, 0);	
    EPWM_setSyncPulseSource(MTR2_PWM_V_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_V_BASE, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR2_PWM_V_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_V_BASE, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(MTR2_PWM_V_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(MTR2_PWM_V_BASE, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(MTR2_PWM_V_BASE, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(MTR2_PWM_V_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(MTR2_PWM_V_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(MTR2_PWM_V_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(MTR2_PWM_V_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(MTR2_PWM_V_BASE, 240);	
    EPWM_setDeadBandDelayMode(MTR2_PWM_V_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(MTR2_PWM_V_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(MTR2_PWM_V_BASE, 240);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(MTR2_PWM_V_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(MTR2_PWM_V_BASE);	
    EPWM_setTripZoneAction(MTR2_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(MTR2_PWM_V_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(MTR2_PWM_V_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT2);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_V_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_V_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(MTR2_PWM_V_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(MTR2_PWM_V_BASE, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(MTR2_PWM_V_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_V_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(MTR2_PWM_V_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableADCTrigger(MTR2_PWM_V_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(MTR2_PWM_V_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_U_CMPC);	
    EPWM_setADCTriggerEventPrescale(MTR2_PWM_V_BASE, EPWM_SOC_A, 1);	
    EPWM_enableADCTrigger(MTR2_PWM_V_BASE, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(MTR2_PWM_V_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_U_CMPD);	
    EPWM_setADCTriggerEventPrescale(MTR2_PWM_V_BASE, EPWM_SOC_B, 1);	
    EPWM_setEmulationMode(PFC_PWM_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(PFC_PWM_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(PFC_PWM_BASE, 5000);	
    EPWM_setTimeBaseCounter(PFC_PWM_BASE, 0);	
    EPWM_setTimeBaseCounterMode(PFC_PWM_BASE, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(PFC_PWM_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(PFC_PWM_BASE);	
    EPWM_setPhaseShift(PFC_PWM_BASE, 0);	
    EPWM_setSyncPulseSource(PFC_PWM_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(PFC_PWM_BASE, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(PFC_PWM_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(PFC_PWM_BASE, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(PFC_PWM_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(PFC_PWM_BASE, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(PFC_PWM_BASE, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(PFC_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(PFC_PWM_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(PFC_PWM_BASE, 10);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(PFC_PWM_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(PFC_PWM_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(PFC_PWM_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(PFC_PWM_BASE);	
    EPWM_setTripZoneAction(PFC_PWM_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(PFC_PWM_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(PFC_PWM_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(PFC_PWM_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(PFC_PWM_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(PFC_PWM_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(PFC_PWM_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1);	
    EPWM_selectDigitalCompareTripInput(PFC_PWM_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(PFC_PWM_BASE, EPWM_DC_COMBINATIONAL_TRIPIN4, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(PFC_PWM_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(PFC_PWM_BASE, EPWM_DC_COMBINATIONAL_TRIPIN4, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(PFC_PWM_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(PFC_PWM_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(PFC_PWM_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(PFC_PWM_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(PFC_PWM_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(PFC_PWM_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(PFC_PWM_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(PFC_PWM_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(PFC_PWM_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(PFC_PWM_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setDigitalCompareEventSource(PFC_PWM_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(PFC_PWM_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableInterrupt(PFC_PWM_BASE);	
    EPWM_setInterruptSource(PFC_PWM_BASE, EPWM_INT_TBCTR_PERIOD);	
    EPWM_setInterruptEventCount(PFC_PWM_BASE, 2);	
    EPWM_enableADCTrigger(PFC_PWM_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(PFC_PWM_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_PERIOD);	
    EPWM_setADCTriggerEventPrescale(PFC_PWM_BASE, EPWM_SOC_A, 2);	
    EPWM_enableADCTrigger(PFC_PWM_BASE, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(PFC_PWM_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(PFC_PWM_BASE, EPWM_SOC_B, 2);	
}
// MTR1_PWM_U Configuration Template
void MTR1_configureEPWM(uint32_t base){
    EPWM_setEmulationMode(base, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(base, 5000);	
    EPWM_setTimeBaseCounter(base, 0);	
    EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(base, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(base);	
    EPWM_setPhaseShift(base, 0);	
    EPWM_setSyncPulseSource(base, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(base, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(base, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(base, 240);	
    EPWM_setDeadBandDelayMode(base, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(base, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(base, 240);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(base);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(base);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(base, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT1);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableInterrupt(base);	
    EPWM_setInterruptSource(base, EPWM_INT_TBCTR_ZERO);	
    EPWM_setInterruptEventCount(base, 1);	
    EPWM_enableADCTrigger(base, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(base, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(base, EPWM_SOC_A, 1);	
    EPWM_enableADCTrigger(base, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(base, EPWM_SOC_B, EPWM_SOC_TBCTR_D_CMPD);	
    EPWM_setADCTriggerEventPrescale(base, EPWM_SOC_B, 1);	
}
// MTR2_PWM_U Configuration Template
void MTR2_configureEPWM(uint32_t base){
    EPWM_setEmulationMode(base, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(base, 5000);	
    EPWM_setTimeBaseCounter(base, 0);	
    EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(base, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(base);	
    EPWM_setPhaseShift(base, 0);	
    EPWM_setSyncPulseSource(base, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(base, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(base, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(base, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(base, 245);	
    EPWM_setDeadBandDelayMode(base, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(base, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(base, 225);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(base);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(base);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(base, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT2);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableInterrupt(base);	
    EPWM_setInterruptSource(base, EPWM_INT_TBCTR_ZERO);	
    EPWM_setInterruptEventCount(base, 3);	
    EPWM_enableADCTrigger(base, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(base, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(base, EPWM_SOC_A, 3);	
    EPWM_enableADCTrigger(base, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(base, EPWM_SOC_B, EPWM_SOC_TBCTR_D_CMPD);	
    EPWM_setADCTriggerEventPrescale(base, EPWM_SOC_B, 3);	
}
// PFC_PWM Configuration Template
void PFC_configureEPWM(uint32_t base){
    EPWM_setEmulationMode(base, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(base, 5000);	
    EPWM_setTimeBaseCounter(base, 0);	
    EPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);	
    EPWM_setCountModeAfterSync(base, EPWM_COUNT_MODE_UP_AFTER_SYNC);	
    EPWM_disablePhaseShiftLoad(base);	
    EPWM_setPhaseShift(base, 0);	
    EPWM_setSyncPulseSource(base, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, 5000);	
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, 5000);	
    EPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_C, 5);	
    EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_D, 5);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(base, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(base, 10);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(base, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(base, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(base);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(base);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_LOW);	
    EPWM_setTripZoneAction(base, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_LOW);	
    EPWM_enableTripZoneSignals(base, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN4, EPWM_DC_TYPE_DCAH);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN4, EPWM_DC_TYPE_DCAL);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXL_HIGH);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBH);	
    EPWM_selectDigitalCompareTripInput(base, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL);	
    EPWM_enableDigitalCompareTripCombinationInput(base, EPWM_DC_COMBINATIONAL_TRIPIN7, EPWM_DC_TYPE_DCBL);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setTripZoneDigitalCompareEventCondition(base, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_HIGH);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_setDigitalCompareEventSource(base, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);	
    EPWM_enableInterrupt(base);	
    EPWM_setInterruptSource(base, EPWM_INT_TBCTR_PERIOD);	
    EPWM_setInterruptEventCount(base, 2);	
    EPWM_enableADCTrigger(base, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(base, EPWM_SOC_A, EPWM_SOC_TBCTR_PERIOD);	
    EPWM_setADCTriggerEventPrescale(base, EPWM_SOC_A, 2);	
    EPWM_enableADCTrigger(base, EPWM_SOC_B);	
    EPWM_setADCTriggerSource(base, EPWM_SOC_B, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(base, EPWM_SOC_B, 2);	
}

//*****************************************************************************
//
// EPWMXBAR Configurations
//
//*****************************************************************************
void EPWMXBAR_init(){
	PFC_FAULT_IAC_CMPSS_init();
	COMP_nFAULT_CMPSS_init();
	FAN_nFAULT_CMPSS_init();
}

void PFC_FAULT_IAC_CMPSS_init(){
		
	XBAR_setEPWMMuxConfig(PFC_FAULT_IAC_CMPSS, XBAR_EPWM_MUX02_CMPSS2_CTRIPH);
	XBAR_setEPWMMuxConfig(PFC_FAULT_IAC_CMPSS, XBAR_EPWM_MUX03_CMPSS2_CTRIPL);
	XBAR_enableEPWMMux(PFC_FAULT_IAC_CMPSS, XBAR_MUX02 | XBAR_MUX03);
}
void COMP_nFAULT_CMPSS_init(){
		
	XBAR_setEPWMMuxConfig(COMP_nFAULT_CMPSS, XBAR_EPWM_MUX07_CMPSS4_CTRIPL);
	XBAR_enableEPWMMux(COMP_nFAULT_CMPSS, XBAR_MUX07);
}
void FAN_nFAULT_CMPSS_init(){
		
	XBAR_setEPWMMuxConfig(FAN_nFAULT_CMPSS, XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
	XBAR_setEPWMMuxConfig(FAN_nFAULT_CMPSS, XBAR_EPWM_MUX01_CMPSS1_CTRIPL);
	XBAR_setEPWMMuxConfig(FAN_nFAULT_CMPSS, XBAR_EPWM_MUX05_CMPSS3_CTRIPL);
	XBAR_enableEPWMMux(FAN_nFAULT_CMPSS, XBAR_MUX00 | XBAR_MUX01 | XBAR_MUX05);
}

//*****************************************************************************
//
// GPIO Configurations
//
//*****************************************************************************
void GPIO_init(){
	MTR1_PM_nFAULT_GPIO_init();
	MTR2_PM_nFAULT_GPIO_init();
	ACPOWER_RELAY_GPIO_init();
	FOURWAY_RELAY_GPIO_init();
	EEV_STEPPER_2H_GPIO_init();
	EMI_INJ_PD_GPIO_init();
	EMI_INJ_PU_GPIO_init();
	EMI_INJ_MD_GPIO_init();
	EEV_STEPPER_1H_GPIO_init();
	EEV_STEPPER_1L_GPIO_init();
	EMI_RESET_GPIO_init();
}

void MTR1_PM_nFAULT_GPIO_init(){
	GPIO_setPadConfig(MTR1_PM_nFAULT_GPIO, GPIO_PIN_TYPE_STD | GPIO_PIN_TYPE_PULLUP);
	GPIO_setQualificationMode(MTR1_PM_nFAULT_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(MTR1_PM_nFAULT_GPIO, GPIO_DIR_MODE_IN);
}
void MTR2_PM_nFAULT_GPIO_init(){
	GPIO_setPadConfig(MTR2_PM_nFAULT_GPIO, GPIO_PIN_TYPE_STD | GPIO_PIN_TYPE_PULLUP);
	GPIO_setQualificationMode(MTR2_PM_nFAULT_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(MTR2_PM_nFAULT_GPIO, GPIO_DIR_MODE_IN);
}
void ACPOWER_RELAY_GPIO_init(){
	GPIO_writePin(ACPOWER_RELAY_GPIO, 0);
	GPIO_setPadConfig(ACPOWER_RELAY_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(ACPOWER_RELAY_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(ACPOWER_RELAY_GPIO, GPIO_DIR_MODE_OUT);
}
void FOURWAY_RELAY_GPIO_init(){
	GPIO_writePin(FOURWAY_RELAY_GPIO, 0);
	GPIO_setPadConfig(FOURWAY_RELAY_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(FOURWAY_RELAY_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(FOURWAY_RELAY_GPIO, GPIO_DIR_MODE_OUT);
}
void EEV_STEPPER_2H_GPIO_init(){
	GPIO_writePin(EEV_STEPPER_2H_GPIO, 0);
	GPIO_setPadConfig(EEV_STEPPER_2H_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(EEV_STEPPER_2H_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(EEV_STEPPER_2H_GPIO, GPIO_DIR_MODE_OUT);
}
void EMI_INJ_PD_GPIO_init(){
	GPIO_setPadConfig(EMI_INJ_PD_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(EMI_INJ_PD_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(EMI_INJ_PD_GPIO, GPIO_DIR_MODE_OUT);
}
void EMI_INJ_PU_GPIO_init(){
	GPIO_setPadConfig(EMI_INJ_PU_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(EMI_INJ_PU_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(EMI_INJ_PU_GPIO, GPIO_DIR_MODE_OUT);
}
void EMI_INJ_MD_GPIO_init(){
	GPIO_setPadConfig(EMI_INJ_MD_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(EMI_INJ_MD_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(EMI_INJ_MD_GPIO, GPIO_DIR_MODE_OUT);
}
void EEV_STEPPER_1H_GPIO_init(){
	GPIO_writePin(EEV_STEPPER_1H_GPIO, 0);
	GPIO_setPadConfig(EEV_STEPPER_1H_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(EEV_STEPPER_1H_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(EEV_STEPPER_1H_GPIO, GPIO_DIR_MODE_OUT);
}
void EEV_STEPPER_1L_GPIO_init(){
	GPIO_writePin(EEV_STEPPER_1L_GPIO, 0);
	GPIO_setPadConfig(EEV_STEPPER_1L_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(EEV_STEPPER_1L_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(EEV_STEPPER_1L_GPIO, GPIO_DIR_MODE_IN);
}
void EMI_RESET_GPIO_init(){
	GPIO_writePin(EMI_RESET_GPIO, 0);
	GPIO_setPadConfig(EMI_RESET_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(EMI_RESET_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(EMI_RESET_GPIO, GPIO_DIR_MODE_OUT);
}

//*****************************************************************************
//
// INPUTXBAR Configurations
//
//*****************************************************************************
void INPUTXBAR_init(){
	COMP_nFAULT_IN_init();
	FAN_nFAULT_IN_init();
}

void COMP_nFAULT_IN_init(){
	XBAR_setInputPin(INPUTXBAR_BASE, COMP_nFAULT_IN_INPUT, COMP_nFAULT_IN_SOURCE);
	XBAR_lockInput(INPUTXBAR_BASE, COMP_nFAULT_IN_INPUT);
}
void FAN_nFAULT_IN_init(){
	XBAR_setInputPin(INPUTXBAR_BASE, FAN_nFAULT_IN_INPUT, FAN_nFAULT_IN_SOURCE);
	XBAR_lockInput(INPUTXBAR_BASE, FAN_nFAULT_IN_INPUT);
}

//*****************************************************************************
//
// INTERRUPT Configurations
//
//*****************************************************************************
void INTERRUPT_init(){
	
	// Interrupt Setings for INT_PFC_MTRS_2
	Interrupt_register(INT_PFC_MTRS_2, &pfcCtrlISR);
	Interrupt_enable(INT_PFC_MTRS_2);
	
	// Interrupt Setings for INT_PFC_MTRS_3
	Interrupt_register(INT_PFC_MTRS_3, &motor1CtrlISR);
	Interrupt_enable(INT_PFC_MTRS_3);
	
	// Interrupt Setings for INT_PFC_MTRS_4
	Interrupt_register(INT_PFC_MTRS_4, &motor2CtrlISR);
	Interrupt_enable(INT_PFC_MTRS_4);
}
//*****************************************************************************
//
// OTHER Configurations
//
//*****************************************************************************
void OTHER_init(){
	//cJTAG initialization
	    
}
//*****************************************************************************
//
// SPI Configurations
//
//*****************************************************************************
void SPI_init(){
	DAC_SPI_init();
}

void DAC_SPI_init(){
	SPI_disableModule(DAC_SPI_BASE);
	SPI_setConfig(DAC_SPI_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
				  SPI_MODE_CONTROLLER, 4000000, 16);
	SPI_setPTESignalPolarity(DAC_SPI_BASE, SPI_PTE_ACTIVE_LOW);
	SPI_enableFIFO(DAC_SPI_BASE);
	SPI_setFIFOInterruptLevel(DAC_SPI_BASE, SPI_FIFO_TX4, SPI_FIFO_RX4);
	SPI_disableLoopback(DAC_SPI_BASE);
	SPI_setEmulationMode(DAC_SPI_BASE, SPI_EMULATION_FREE_RUN);
	SPI_enableModule(DAC_SPI_BASE);
}

//*****************************************************************************
//
// SYNC Scheme Configurations
//
//*****************************************************************************
void SYNC_init(){
	SysCtl_setSyncOutputConfig(SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT);
	//
	// SOCA
	//
	SysCtl_enableExtADCSOCSource(0);
	//
	// SOCB
	//
	SysCtl_enableExtADCSOCSource(0);
}
//*****************************************************************************
//
// SYSCTL Configurations
//
//*****************************************************************************
void SYSCTL_init(){
	//
    // sysctl initialization
	//
    SysCtl_setStandbyQualificationPeriod(2);
    SysCtl_configureType(SYSCTL_ECAPTYPE, 0, 0);
    SysCtl_selectErrPinPolarity(0);

    SysCtl_disableMCD();


    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL);
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DCC0);
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPG1);



}

