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//! \file   \solutions\tidm_02010_dmpfc\f280013x\drivers\include\hal.h
//! \brief  Contains public interface to various functions related
//!         to the HAL object
//!

#ifndef HAL_H
#define HAL_H

//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif

//*****************************************************************************
//
//! \defgroup HAL HAL
//! @{
//
//*****************************************************************************

// the includes
#include "userParams.h"

#include "user.h"

#if defined(SYSCONFIG_EN)
#include "board.h"
#endif  // !SYSCONFIG_EN

// platforms
#include "hal_obj.h"

#if defined(MOTOR1_DCLINKSS) || defined(MOTOR2_DCLINKSS)
#include "dclink_ss.h"
#endif  // MOTOR1_DCLINKSS || MOTOR2_DCLINKSS

// **************************************************************************
// the globals
extern __interrupt void motor1CtrlISR(void);
extern __interrupt void motor2CtrlISR(void);
extern __interrupt void pfcCtrlISR(void);

#ifdef _FLASH
extern uint32_t loadStart_ctrlfuncs;
extern uint32_t loadEnd_ctrlfuncs;
extern uint32_t loadSize_ctrlfuncs;
extern uint32_t runStart_ctrlfuncs;
extern uint32_t runEnd_ctrlfuncs;
extern uint32_t runSize_ctrlfuncs;
#endif

extern uint32_t loadStart_est_data;
extern uint32_t loadEnd_est_data;
extern uint32_t loadSize_est_data;

extern uint32_t loadStart_user_data;
extern uint32_t loadEnd_user_data;
extern uint32_t loadSize_user_data;

extern uint32_t loadStart_sys_data;
extern uint32_t loadEnd_sys_data;
extern uint32_t loadSize_sys_data;

extern uint32_t loadStart_foc_data;
extern uint32_t loadEnd_foc_data;
extern uint32_t loadSize_foc_data;

extern uint32_t loadStart_pfc_data;
extern uint32_t loadEnd_pfc_data;
extern uint32_t loadSize_pfc_data;

extern uint32_t loadStart_motor_data;
extern uint32_t loadEnd_motor_data;
extern uint32_t loadSize_motor_data;

extern uint32_t loadStart_dmaBuf_data;
extern uint32_t loadEnd_dmaBuf_data;
extern uint32_t loadSize_dmaBuf_data;

extern uint32_t loadStart_vibc_data;
extern uint32_t loadEnd_vibc_data;
extern uint32_t loadSize_vibc_data;

extern uint32_t loadStart_sfra_data;
extern uint32_t loadEnd_sfra_data;
extern uint32_t loadSize_sfra_data;

extern uint32_t loadStart_datalog_data;
extern uint32_t loadEnd_datalog_data;
extern uint32_t loadSize_datalog_data;

extern uint32_t loadStart_dbgc_data;
extern uint32_t loadEnd_dbgc_data;
extern uint32_t loadSize_dbgc_data;

// hal object
extern HAL_Handle  halHandle;      //!< the handle for the hardware abstraction layer
extern HAL_Obj     hal;            //!< the hardware abstraction layer object

extern HAL_Handle halHandle;

extern HAL_MTR_Handle halMtrHandle[2];
extern HAL_MTR_Obj    halMtr[2];

extern volatile uint16_t mtr1PIEIER;
extern volatile uint16_t mtr2PIEIER;

// **************************************************************************
// the defines
//! Trip Zones all interrupt
//!
#define MTR_TZ_FLAG                 (EPWM_TZ_FLAG_OST |                        \
                                     EPWM_TZ_FLAG_DCAEVT1)

#define PFC_TZ_FLAG                 (EPWM_TZ_FLAG_OST |                        \
                                     EPWM_TZ_FLAG_DCAEVT1)

#define HAL_TZFLAG_INTERRUPT_ALL    (EPWM_TZ_INTERRUPT_DCBEVT2 |               \
                                     EPWM_TZ_INTERRUPT_DCBEVT1 |               \
                                     EPWM_TZ_INTERRUPT_DCAEVT2 |               \
                                     EPWM_TZ_INTERRUPT_DCAEVT1 |               \
                                     EPWM_TZ_INTERRUPT_OST |                   \
                                     EPWM_TZ_INTERRUPT_CBC )

#define HAL_TZSEL_SIGNALS_ALL       (EPWM_TZ_SIGNAL_CBC1 |                     \
                                     EPWM_TZ_SIGNAL_CBC2 |                     \
                                     EPWM_TZ_SIGNAL_CBC3 |                     \
                                     EPWM_TZ_SIGNAL_CBC4 |                     \
                                     EPWM_TZ_SIGNAL_CBC5 |                     \
                                     EPWM_TZ_SIGNAL_CBC6 |                     \
                                     EPWM_TZ_SIGNAL_DCAEVT2 |                  \
                                     EPWM_TZ_SIGNAL_DCBEVT2 |                  \
                                     EPWM_TZ_SIGNAL_OSHT1 |                    \
                                     EPWM_TZ_SIGNAL_OSHT2 |                    \
                                     EPWM_TZ_SIGNAL_OSHT3 |                    \
                                     EPWM_TZ_SIGNAL_OSHT4 |                    \
                                     EPWM_TZ_SIGNAL_OSHT5 |                    \
                                     EPWM_TZ_SIGNAL_OSHT6 |                    \
                                     EPWM_TZ_SIGNAL_DCAEVT1 |                  \
                                     EPWM_TZ_SIGNAL_DCBEVT1)

//! \brief Defines the PWM frequency for PWMDAC
//!
#define HAL_PWMDAC_FREQ_KHZ         100.0f

//! \brief Defines the comparator number for current protection
//!
#define HAL_NUM_CMPSS_CURRENT       3


// Defines LINA
#define LIN_CHAR_LENGTH     8
#define LIN_FRAME_LENGTH    1


// Defines EEPROM
#if !defined(SYSCONFIG_EN)
#define EEPROM_SLAVE_ADDRESS               0x50
#endif

#define EEPROM_HIGH_ADDR                   0x00
#define EEPROM_LOW_ADDR                    0x30
#define EEPROM_NUM_BYTES                   8
#define EEPROM_MAX_BUFFER_SIZE             14      // Max is currently 14 because of
                                            // 2 address bytes and the 16-byte
                                            // FIFO

// I2C message states for I2CMsg struct
#define EEPROM_MSG_STATUS_INACTIVE         0x0000 // Message not in use, do not send
#define EEPROM_MSG_STATUS_SEND_WITHSTOP    0x0010 // Send message with stop bit
#define EEPROM_MSG_STATUS_WRITE_BUSY       0x0011 // Message sent, wait for stop
#define EEPROM_MSG_STATUS_SEND_NOSTOP      0x0020 // Send message without stop bit
#define EEPROM_MSG_STATUS_SEND_NOSTOP_BUSY 0x0021 // Message sent, wait for ARDY
#define EEPROM_MSG_STATUS_RESTART          0x0022 // Ready to become master-receiver
#define EEPROM_MSG_STATUS_READ_BUSY        0x0023 // Wait for stop before reading data

// Error messages for read and write functions
#define EEPROM_ERROR_BUS_BUSY              0x1000
#define EEPROM_ERROR_STOP_NOT_READY        0x5555
#define EEPROM_SUCCESS                     0x0000


#if defined(SYSCONFIG_EN)
//------------------------------------------------------------------------------
#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)       // TO VERIFY and TEST

#define TEST_SWITCH_GPIO        EEV_STEPPER_2H_GPIO

// PWM Shift Settings
#define PFC_EPWM_SYSN_O_TIME    2
#define MTR_EPWM_SYSN_O_TIME    2

// PFC-CMPSS
#define PFC_CMPSS_IAC_BASE      PFC_CMPSS_VIAC_BASE
#define PFC_CMPSS_VDC_BASE      PFC_CMPSS_VIAC_BASE

// PFC-ADC
#define PFC_IAC_ADC_BASE        PFC_MTRS_BASE           // ADCA-A9*/C8  -SOC0
#define PFC_VAC_ADC_BASE        PFC_MTRS_BASE           // ADCA-A10*/C10-SOC1
#define PFC_VDC_ADC_BASE        PFC_MTRS_BASE           // ADCA-A4*/C14 -SOC2

#define PFC_IAC_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A9*/C8
#define PFC_VAC_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A10*/C10
#define PFC_VDC_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A4*/C14

#define PFC_IAC1_ADC_SOC_NUM    PFC_MTRS_IAC1           // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC1_ADC_SOC_NUM    PFC_MTRS_VAC1           // ADCA-A10*/C10-SOC1-PPB2
#define PFC_VDC1_ADC_SOC_NUM    PFC_MTRS_VDC1           // ADCA-A4*/C14 -SOC2

#define PFC_IAC2_ADC_SOC_NUM    PFC_MTRS_IAC2           // ADCA-A9*/C8  -SOC3-PPB3
#define PFC_VAC2_ADC_SOC_NUM    PFC_MTRS_VAC2           // ADCA-A10*/C10-SOC4-PPB4
#define PFC_VDC2_ADC_SOC_NUM    PFC_MTRS_VDC2           // ADCA-A4*/C14 -SOC5

#define PFC_IAC_ADC_SOC_NUM     PFC_IAC1_ADC_SOC_NUM    // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC_ADC_SOC_NUM     PFC_VAC1_ADC_SOC_NUM    // ADCA-A10*/C10-SOC1-PPB2
#define PFC_VDC_ADC_SOC_NUM     PFC_VDC1_ADC_SOC_NUM    // ADCA-A4*/C14 -SOC2

#define PFC_IAC1_ADC_PPB_NUM    ADC_PPB_NUMBER1         // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC1_ADC_PPB_NUM    ADC_PPB_NUMBER2         // ADCA-A10*/C10-SOC1-PPB2

#define PFC_IAC2_ADC_PPB_NUM    ADC_PPB_NUMBER3         // ADCA-A9*/C8  -SOC0-PPB3
#define PFC_VAC2_ADC_PPB_NUM    ADC_PPB_NUMBER4         // ADCA-A10*/C10-SOC1-PPB4

#define PFC_IAC_ADC_PPB_NUM     PFC_IAC1_ADC_PPB_NUM    // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC_ADC_PPB_NUM     PFC_VAC1_ADC_PPB_NUM    // ADCA-A10*/C10-SOC1-PPB2

// PFC-interrupt
#define PFC_PWM_INT_BASE        PFC_PWM_BASE            // EPWM7

#define PFC_ADC_INT_BASE        PFC_VDC_ADC_BASE        // ADCA-A4*/C14-SOC2
#define PFC_ADC_INT_NUM         ADC_INT_NUMBER2         // ADCA_INT2-SOC2

#define PFC_PIE_INT_NUM         INT_PFC_MTRS_2          // ADCA_INT2-SOC2
#define PFC_INT_ACK_GROUP       INT_PFC_MTRS_4_INTERRUPT_ACK_GROUP   // ADCA_INT2-CPU_INT10

//------------------------------------------------------------------------------
// Motor 1 Settings
// ADC, Motor_1, dc-bus voltage
#define MTR1_VDC_ADC_BASE       PFC_MTRS_BASE           // ADCA-A4*/C14

#if defined(MOTOR1_DCLINKSS)    // Single Shunt
// ADC, Motor_1, dc_link current
#define MTR1_IDC1_ADC_BASE      MTR1_EMI_BASE           // ADCC-A12/C1*/CMP1P*-SOC0
#define MTR1_IDC2_ADC_BASE      MTR1_EMI_BASE           // ADCC-A12/C1*-SOC1
#define MTR1_IDC3_ADC_BASE      MTR1_EMI_BASE           // ADCC-A12/C1*-SOC2
#define MTR1_IDC4_ADC_BASE      MTR1_EMI_BASE           // ADCC-A12/C1*-SOC3

#define MTR1_IDC1_ADCRES_BASE   MTR1_EMI_RESULT_BASE    // ADCC-A12/C1*
#define MTR1_IDC2_ADCRES_BASE   MTR1_EMI_RESULT_BASE    // ADCC-A12/C1*
#define MTR1_IDC3_ADCRES_BASE   MTR1_EMI_RESULT_BASE    // ADCC-A12/C1*
#define MTR1_IDC4_ADCRES_BASE   MTR1_EMI_RESULT_BASE    // ADCC-A12/C1*

#define MTR1_IDC1_ADC_SOC_NUM   MTR1_EMI_IDC1           // ADCC-A12/C1*-SOC0
#define MTR1_IDC2_ADC_SOC_NUM   MTR1_EMI_IDC2           // ADCC-A12/C1*-SOC1
#define MTR1_IDC3_ADC_SOC_NUM   MTR1_EMI_IDC3           // ADCC-A12/C1*-SOC2
#define MTR1_IDC4_ADC_SOC_NUM   MTR1_EMI_IDC4           // ADCC-A12/C1*-SOC3

#define MTR1_IDC1_ADC_PPB_NUM   ADC_PPB_NUMBER1         // ADCC-A12/C1*-SOC0-PPB1
#define MTR1_IDC2_ADC_PPB_NUM   ADC_PPB_NUMBER2         // ADCC-A12/C1*-SOC1-PPB2
#define MTR1_IDC3_ADC_PPB_NUM   ADC_PPB_NUMBER3         // ADCC-A12/C1*-SOC2-PPB3
#define MTR1_IDC4_ADC_PPB_NUM   ADC_PPB_NUMBER4         // ADCC-A12/C1*-SOC3-PPB4

// CMPSS, Motor_1, dc_link current
// #define MTR1_CMPSS_IDC_BASE     CMPSS4_BASE          // defined in board.h

#else   // !MOTOR1_DCLINKSS, Three-shunt
// ADC, Motor_1, phase current
#define MTR1_IU_ADCRES_BASE     MTR1_EMI_RESULT_BASE    // ADCC-A0/C15*
#define MTR1_IV_ADCRES_BASE     MTR1_EMI_RESULT_BASE    // ADCC-A12/C1*
#define MTR1_IW_ADCRES_BASE     MTR1_EMI_RESULT_BASE    // ADCC-A7/C3*

#define MTR1_IU_ADC_SOC_NUM     MTR1_EMI_IU_M1          // ADCC-A0/C15*-SOC4
#define MTR1_IV_ADC_SOC_NUM     MTR1_EMI_IV_M1          // ADCC-A12/C1*-SOC5
#define MTR1_IW_ADC_SOC_NUM     MTR1_EMI_IW_M1          // ADCC-A7/C3* -SOC6

// CMPSS, Motor_1, Phase current
#define MTR1_CMPSS_U_BASE       MTRS_CMPSS_UW_BASE
#define MTR1_CMPSS_V_BASE       MTR1_CMPSS_VW_BASE
#define MTR1_CMPSS_W_BASE       MTR1_CMPSS_VW_BASE
#endif    // !MOTOR1_DCLINKSS, Three-shunt

#define MTR1_VU_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A8*/C11
#define MTR1_VV_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A1*
#define MTR1_VW_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A5*/C2
#define MTR1_VDC_ADCRES_BASE    PFC_MTRS_RESULT_BASE    // ADCA-A4*/C14

#define MTR1_VU_ADC_SOC_NUM     PFC_MTRS_VU_M1          // ADCA-A8*/C11-SOC6
#define MTR1_VV_ADC_SOC_NUM     PFC_MTRS_VV_M1          // ADCA-A1*    -SOC7
#define MTR1_VW_ADC_SOC_NUM     PFC_MTRS_VW_M1          // ADCA-A5*/C2 -SOC8
#define MTR1_VDC_ADC_SOC_NUM    PFC_MTRS_VDC_M1         // ADCA-A4*/C14-SOC9

// Motor_1-interrupt
#define MTR1_PWM_INT_BASE       MTR1_PWM_U_BASE         // EPWM1

#define MTR1_ADC_INT_BASE       MTR1_VDC_ADCRES_BASE    // ADCA-A5*/C2-SOC9
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER3         //* ADCA_INT3  -SOC9

#define MTR1_PIE_INT_NUM        INT_PFC_MTRS_3          // ADCA_INT3-SOC8
#define MTR1_INT_ACK_GROUP      INT_PFC_MTRS_3_INTERRUPT_ACK_GROUP   // ADCA_INT3-CPU_INT10

//------------------------------------------------------------------------------
// Motor 2 Settings
// ADC, Motor_2, dc-bus voltage
#define MTR2_VDC_ADC_BASE       PFC_MTRS_BASE           // ADCA-A4*/C14

#if defined(MOTOR2_DCLINKSS)    // Single Shunt

#else   // !MOTOR2_DCLINKSS, Three-shunt
// ADC, Motor_2, Phase Current
#define MTR2_IU_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A2*/C9
#define MTR2_IV_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A6*
#define MTR2_IW_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A3*/C5

#define MTR2_IU_ADC_SOC_NUM     PFC_MTRS_IU_M2          // ADCA-A2*/C9 -SOC10
#define MTR2_IV_ADC_SOC_NUM     PFC_MTRS_IV_M2          // ADCA-A6*    -SOC11
#define MTR2_IW_ADC_SOC_NUM     PFC_MTRS_IW_M2          // ADCA-A3*/C5 -SOC12

// CMPSS, Motor_2, Phase Current
#define MTR2_CMPSS_U_BASE       MTR2_CMPSS_UV_BASE
#define MTR2_CMPSS_V_BASE       MTR2_CMPSS_UV_BASE
#define MTR2_CMPSS_W_BASE       MTRS_CMPSS_UW_BASE
#endif    // !MOTOR2_DCLINKSS, Three-shunt

#define MTR2_VU_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A11*/C0
#define MTR2_VV_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A14*/C4
#define MTR2_VW_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A15*/C7

#define MTR2_VU_ADC_SOC_NUM     PFC_MTRS_VU_M2          // ADCA-A11*/C0-SOC13
#define MTR2_VV_ADC_SOC_NUM     PFC_MTRS_VV_M2          // ADCA-A14*/C4-SOC14
#define MTR2_VW_ADC_SOC_NUM     PFC_MTRS_VW_M2          // ADCA-A15*/C7-SOC15
#define MTR2_VDC_ADC_SOC_NUM    PFC_MTRS_VDC_M1         // ADCA-A4*/C14-SOC2

// Motor_2-interrupt
#define MTR2_PWM_INT_BASE       MTR2_PWM_U_BASE         // EPWM4

#define MTR2_ADC_INT_BASE       MTR2_VDC_ADC_BASE       // ADCA-A15*/C7 -SOC14
#define MTR2_ADC_INT_NUM        ADC_INT_NUMBER4         //* ADCA_INT4-SOC14

#define MTR2_PIE_INT_NUM        INT_PFC_MTRS_4          // ADCA_INT4-SOC14
#define MTR2_INT_ACK_GROUP      INT_PFC_MTRS_4_INTERRUPT_ACK_GROUP   // ADCA_INT4-CPU_INT10

// Interrupt Nesting
#define PFC_CPU_INT_NUM         INTERRUPT_CPU_INT10     //* ADCA_INT2-CPU_INT10
#define PFC_PIE_O_IER           PIE_O_IER10             //* ADCA_INT2-CPU_INT10
#define PFC_PIE_IER_INT         PIE_IER10_INTX2         //* ADCA_INT2-PIE_INT2

#define MTR1_PIE_O_IER          PIE_O_IER10             //* ADCC_INT2-CPU_INT10
#define MTR2_PIE_O_IER          PIE_O_IER10             //* ADCC_INT3-CPU_INT10

// DMCPFC_REV3P2 | DMCPFC_REV3P1
//------------------------------------------------------------------------------

#elif defined(HVMTRPFC_REV1P1)

// HVMTRPFC_REV1P1

//------------------------------------------------------------------------------
#elif defined(BSXL8323RH_REVB)       // TO VERIFY and TEST

#define TEST_SWITCH_GPIO        EEV_STEPPER_2H_GPIO

// PWM Shift Settings
#define PFC_EPWM_SYSN_O_TIME    2
#define MTR_EPWM_SYSN_O_TIME    2

// PFC-CMPSS
#define PFC_CMPSS_IAC_BASE      PFC_CMPSS_VIAC_BASE
#define PFC_CMPSS_VDC_BASE      PFC_CMPSS_VIAC_BASE

// PFC-ADC
#define PFC_IAC_ADC_BASE        PFC_MTRS_BASE           // ADCA-A9*/C8  -SOC0
#define PFC_VAC_ADC_BASE        PFC_MTRS_BASE           // ADCA-A10*/C10-SOC1
#define PFC_VDC_ADC_BASE        PFC_MTRS_BASE           // ADCA-A4*/C14 -SOC2

#define PFC_IAC_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A9*/C8
#define PFC_VAC_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A10*/C10
#define PFC_VDC_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A4*/C14

#define PFC_IAC1_ADC_SOC_NUM    PFC_MTRS_IAC1           // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC1_ADC_SOC_NUM    PFC_MTRS_VAC1           // ADCA-A10*/C10-SOC1-PPB2
#define PFC_VDC1_ADC_SOC_NUM    PFC_MTRS_VDC1           // ADCA-A4*/C14 -SOC2

#define PFC_IAC2_ADC_SOC_NUM    PFC_MTRS_IAC2           // ADCA-A9*/C8  -SOC3-PPB3
#define PFC_VAC2_ADC_SOC_NUM    PFC_MTRS_VAC2           // ADCA-A10*/C10-SOC4-PPB4
#define PFC_VDC2_ADC_SOC_NUM    PFC_MTRS_VDC2           // ADCA-A4*/C14 -SOC5

#define PFC_IAC_ADC_SOC_NUM     PFC_IAC1_ADC_SOC_NUM    // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC_ADC_SOC_NUM     PFC_VAC1_ADC_SOC_NUM    // ADCA-A10*/C10-SOC1-PPB2
#define PFC_VDC_ADC_SOC_NUM     PFC_VDC1_ADC_SOC_NUM    // ADCA-A4*/C14 -SOC2

#define PFC_IAC1_ADC_PPB_NUM    ADC_PPB_NUMBER1         // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC1_ADC_PPB_NUM    ADC_PPB_NUMBER2         // ADCA-A10*/C10-SOC1-PPB2

#define PFC_IAC2_ADC_PPB_NUM    ADC_PPB_NUMBER3         // ADCA-A9*/C8  -SOC0-PPB3
#define PFC_VAC2_ADC_PPB_NUM    ADC_PPB_NUMBER4         // ADCA-A10*/C10-SOC1-PPB4

#define PFC_IAC_ADC_PPB_NUM     PFC_IAC1_ADC_PPB_NUM    // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC_ADC_PPB_NUM     PFC_VAC1_ADC_PPB_NUM    // ADCA-A10*/C10-SOC1-PPB2

// PFC-interrupt
#define PFC_PWM_INT_BASE        PFC_PWM_BASE            // EPWM7

#define PFC_ADC_INT_BASE        PFC_VDC_ADC_BASE        // ADCA-A4*/C14-SOC2
#define PFC_ADC_INT_NUM         ADC_INT_NUMBER2         // ADCA_INT2-SOC2

#define PFC_PIE_INT_NUM         INT_PFC_MTRS_2          // ADCA_INT2-SOC2
#define PFC_INT_ACK_GROUP       INT_PFC_MTRS_4_INTERRUPT_ACK_GROUP   // ADCA_INT2-CPU_INT10

// Motor_1-CMPSS
#define MTR1_CMPSS_U_BASE       MTR2_CMPSS_UV_BASE
#define MTR1_CMPSS_V_BASE       MTR1_CMPSS_VW_BASE
#define MTR1_CMPSS_W_BASE       MTR1_CMPSS_VW_BASE

// Motor_1-ADC
#define MTR1_VDC_ADC_BASE       PFC_MTRS_BASE           // ADCA-A4*/C14

#define MTR1_IU_ADCRES_BASE     MTR1_EMI_RESULT_BASE    // ADCC-A0/C15*
#define MTR1_IV_ADCRES_BASE     MTR1_EMI_RESULT_BASE    // ADCC-A12/C1*
#define MTR1_IW_ADCRES_BASE     MTR1_EMI_RESULT_BASE    // ADCC-A7/C3*
#define MTR1_VU_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A8*/C11
#define MTR1_VV_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A1*
#define MTR1_VW_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A5*/C2
#define MTR1_VDC_ADCRES_BASE    PFC_MTRS_RESULT_BASE    // ADCA-A4*/C14

#define MTR1_IU_ADC_SOC_NUM     MTR1_EMI_IU_M1          // ADCC-A0/C15*-SOC4
#define MTR1_IV_ADC_SOC_NUM     MTR1_EMI_IV_M1          // ADCC-A12/C1*-SOC5
#define MTR1_IW_ADC_SOC_NUM     MTR1_EMI_IW_M1          // ADCC-A7/C3* -SOC6
#define MTR1_VU_ADC_SOC_NUM     PFC_MTRS_VU_M1          // ADCA-A8*/C11-SOC6
#define MTR1_VV_ADC_SOC_NUM     PFC_MTRS_VV_M1          // ADCA-A1*    -SOC7
#define MTR1_VW_ADC_SOC_NUM     PFC_MTRS_VW_M1          // ADCA-A5*/C2 -SOC8
#define MTR1_VDC_ADC_SOC_NUM    PFC_MTRS_VDC_M1         // ADCA-A4*/C14-SOC9

// Motor_1-interrupt
#define MTR1_PWM_INT_BASE       MTR1_PWM_U_BASE         // EPWM1

#define MTR1_ADC_INT_BASE       MTR1_VDC_ADCRES_BASE    // ADCA-A5*/C2-SOC9
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER3         //* ADCA_INT3  -SOC9

#define MTR1_PIE_INT_NUM        INT_PFC_MTRS_3          // ADCA_INT3-SOC8
#define MTR1_INT_ACK_GROUP      INT_PFC_MTRS_3_INTERRUPT_ACK_GROUP   // ADCA_INT3-CPU_INT10

// Motor_2-CMPSS
#define MTR2_CMPSS_U_BASE       MTR2_CMPSS_UV_BASE
#define MTR2_CMPSS_V_BASE       MTR2_CMPSS_UV_BASE
#define MTR2_CMPSS_W_BASE       MTRS_CMPSS_UW_BASE

// Motor_1-ADC
#define MTR2_VDC_ADC_BASE       PFC_MTRS_BASE           // ADCA-A4*/C14

#define MTR2_IU_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A2*/C9
#define MTR2_IV_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A6*
#define MTR2_IW_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A3*/C5
#define MTR2_VU_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A11*/C0
#define MTR2_VV_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A14*/C4
#define MTR2_VW_ADCRES_BASE     PFC_MTRS_RESULT_BASE    // ADCA-A15*/C7

#define MTR2_IU_ADC_SOC_NUM     PFC_MTRS_IU_M2          // ADCA-A2*/C9 -SOC10
#define MTR2_IV_ADC_SOC_NUM     PFC_MTRS_IV_M2          // ADCA-A6*    -SOC11
#define MTR2_IW_ADC_SOC_NUM     PFC_MTRS_IW_M2          // ADCA-A3*/C5 -SOC12
#define MTR2_VU_ADC_SOC_NUM     PFC_MTRS_VU_M2          // ADCA-A11*/C0-SOC13
#define MTR2_VV_ADC_SOC_NUM     PFC_MTRS_VV_M2          // ADCA-A14*/C4-SOC14
#define MTR2_VW_ADC_SOC_NUM     PFC_MTRS_VW_M2          // ADCA-A15*/C7-SOC15
#define MTR2_VDC_ADC_SOC_NUM    PFC_MTRS_VDC_M1         // ADCA-A4*/C14-SOC2

// Motor_2-interrupt
#define MTR2_PWM_INT_BASE       MTR2_PWM_U_BASE         // EPWM4

#define MTR2_ADC_INT_BASE       MTR2_VDC_ADC_BASE       // ADCA-A15*/C7 -SOC14
#define MTR2_ADC_INT_NUM        ADC_INT_NUMBER4         //* ADCA_INT4-SOC14

#define MTR2_PIE_INT_NUM        INT_PFC_MTRS_4          // ADCA_INT4-SOC14
#define MTR2_INT_ACK_GROUP      INT_PFC_MTRS_4_INTERRUPT_ACK_GROUP   // ADCA_INT4-CPU_INT10

// Interrupt Nesting
#define PFC_CPU_INT_NUM         INTERRUPT_CPU_INT10     //* ADCA_INT2-CPU_INT10
#define PFC_PIE_O_IER           PIE_O_IER10             //* ADCA_INT2-CPU_INT10
#define PFC_PIE_IER_INT         PIE_IER10_INTX2         //* ADCA_INT2-PIE_INT2

#define MTR1_PIE_O_IER          PIE_O_IER10             //* ADCC_INT2-CPU_INT10
#define MTR2_PIE_O_IER          PIE_O_IER10             //* ADCC_INT3-CPU_INT10

// BSXL8323RH_REVB

//------------------------------------------------------------------------------
//#####END_INTERNAL#####
#else   // Not select a kit
#error Not select a right board to set definintion for the hal configuration
#endif   // Not select a kit

#else   //!SYSCONFIG_EN
//******************************************************************************
#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)

#define TEST_SWITCH_GPIO        24

#if defined(DMCPFC_REV3P2)
//! \brief Power relay for inrush current
#define ACPOWER_RELAY_GPIO      18

//! \brief Power relay for Four-Way Relay
#define FOURWAY_RELAY_GPIO      39
#elif defined(DMCPFC_REV3P1)
//! \brief Power relay for inrush current
#define ACPOWER_RELAY_GPIO      39

//! \brief Power relay for Four-Way Relay
#define FOURWAY_RELAY_GPIO      18
#endif  // DMCPFC_REV3P1

//----- PFC  -------------------------------------------------------------------
#define PFC_PWM_BASE            EPWM7_BASE

#define PFC_CMPSS_IAC_BASE      CMPSSLITE2_BASE
#define PFC_CMPSS_VDC_BASE      CMPSSLITE2_BASE


#define PFC_EPWM_SYSN_O_TIME    2
#define MTR_EPWM_SYSN_O_TIME    2

// ADC Channel, Trigger, SCO and Interrupt Configure
#define PFC_ADC_TRIGGER_IAC     ADC_TRIGGER_CPU1_TINT1  // CPU_TINT1
#define PFC_ADC_TRIGGER_VIS1    ADC_TRIGGER_EPWM7_SOCA  // EPWM7_SOCA @ Zero
#define PFC_ADC_TRIGGER_VIS2    ADC_TRIGGER_EPWM7_SOCB  // EPWM7_SOCA @ Period

#define PFC_I_ADC_SAMPLE_WINDOW     15                  // 15 sample cycle
#define PFC_V_ADC_SAMPLE_WINDOW     20                  // 20 sample cycle

#define PFC_IAC_ADC_BASE        ADCA_BASE               // ADCA-A9*/C8  -SOC0
#define PFC_VAC_ADC_BASE        ADCA_BASE               // ADCA-A10*/C10-SOC1
#define PFC_VDC_ADC_BASE        ADCA_BASE               // ADCA-A4*/C14 -SOC2

#define PFC_IAC_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A9*/C8
#define PFC_VAC_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A10*/C10
#define PFC_VDC_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A4*/C14

#define PFC_IAC_ADC_CH_NUM      ADC_CH_ADCIN9           // ADCA-A9*/C8
#define PFC_VAC_ADC_CH_NUM      ADC_CH_ADCIN10          // ADCA-A10*/C10
#define PFC_VDC_ADC_CH_NUM      ADC_CH_ADCIN4           // ADCA-A4*/C14

#define PFC_IAC1_ADC_SOC_NUM    ADC_SOC_NUMBER0         // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC1_ADC_SOC_NUM    ADC_SOC_NUMBER1         // ADCA-A10*/C10-SOC1-PPB2
#define PFC_VDC1_ADC_SOC_NUM    ADC_SOC_NUMBER2         // ADCA-A4*/C14 -SOC2

#define PFC_IAC2_ADC_SOC_NUM    ADC_SOC_NUMBER3         // ADCA-A9*/C8  -SOC3-PPB3
#define PFC_VAC2_ADC_SOC_NUM    ADC_SOC_NUMBER4         // ADCA-A10*/C10-SOC4-PPB4
#define PFC_VDC2_ADC_SOC_NUM    ADC_SOC_NUMBER5         // ADCA-A4*/C14 -SOC5

#define PFC_IAC1_ADC_PPB_NUM    ADC_PPB_NUMBER1         // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC1_ADC_PPB_NUM    ADC_PPB_NUMBER2         // ADCA-A10*/C10-SOC1-PPB2

#define PFC_IAC2_ADC_PPB_NUM    ADC_PPB_NUMBER3         // ADCA-A9*/C8  -SOC0-PPB3
#define PFC_VAC2_ADC_PPB_NUM    ADC_PPB_NUMBER4         // ADCA-A10*/C10-SOC1-PPB4

#define PFC_IAC_ADC_SOC_NUM     PFC_IAC1_ADC_SOC_NUM    // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC_ADC_SOC_NUM     PFC_VAC1_ADC_SOC_NUM    // ADCA-A10*/C10-SOC1-PPB2
#define PFC_VDC_ADC_SOC_NUM     PFC_VDC1_ADC_SOC_NUM    // ADCA-A4*/C14 -SOC2

#define PFC_IAC_ADC_PPB_NUM     PFC_IAC1_ADC_PPB_NUM    // ADCA-A9*/C8  -SOC0-PPB1
#define PFC_VAC_ADC_PPB_NUM     PFC_VAC1_ADC_PPB_NUM    // ADCA-A10*/C10-SOC1-PPB2

#define PFC_IAC_ADCRES_ADDR     (PFC_IAC_ADCRES_BASE + \
                                 ADC_PPBxRESULT_OFFSET_BASE + \
                                 PFC_IAC_ADC_PPB_NUM * 2U)

#define PFC_IAC1_ADCRESLT       (PFC_IAC_ADCRES_BASE + ADC_O_RESULT0)   // ADCA-A9*/C8  -SOC0
#define PFC_VAC1_ADCRESLT       (PFC_VAC_ADCRES_BASE + ADC_O_RESULT1)   // ADCA-A10*/C10-SOC1
#define PFC_VDC1_ADCRESLT       (PFC_VDC_ADCRES_BASE + ADC_O_RESULT2)   // ADCA-A4*/C14 -SOC2

#define PFC_IAC2_ADCRESLT       (PFC_IAC_ADCRES_BASE + ADC_O_RESULT3)   // ADCA-A9*/C8  -SOC3
#define PFC_VAC2_ADCRESLT       (PFC_VAC_ADCRES_BASE + ADC_O_RESULT4)   // ADCA-A10*/C10-SOC4
#define PFC_VDC2_ADCRESLT       (PFC_VDC_ADCRES_BASE + ADC_O_RESULT5)   // ADCA-A4*/C14 -SOC5

#define PFC_IAC_ADCRESLT        PFC_IAC1_ADCRESLT                       // ADCA-A9*/C8  -SOC0
#define PFC_VAC_ADCRESLT        PFC_VAC1_ADCRESLT                       // ADCA-A10*/C10-SOC1
#define PFC_VDC_ADCRESLT        PFC_VDC1_ADCRESLT                       // ADCA-A4*/C14 -SOC2

// Interrupt
#define PFC_PWM_INT_BASE        PFC_PWM_BASE            // EPWM7

#define PFC_ADC_INT_BASE        ADCA_BASE               // ADCA-A4/C14*-SOC2
#define PFC_ADC_INT_NUM         ADC_INT_NUMBER2         // ADCA_INT2-SOC2
#define PFC_ADC_INT_SOC         ADC_SOC_NUMBER2         // ADCA_INT2-SOC2
#define PFC_PIE_INT_NUM         INT_ADCA2               // ADCA_INT2-SOC2
#define PFC_CPU_INT_NUM         INTERRUPT_CPU_INT10     // ADCA_INT2-CPU_INT10
#define PFC_INT_ACK_GROUP       INTERRUPT_ACK_GROUP10   // ADCA_INT2-CPU_INT10

#define PFC_PIE_O_IER           PIE_O_IER10             // ADCA_INT2-CPU_INT10
#define PFC_PIE_IER_INT         PIE_IER10_INTX2         // ADCA_INT2-PIE_INT2

#define PFC_DMA_ADC_INT_BASE    ADCA_BASE               // ADCA-A4*/C14-SOC2
#define PFC_DMA_ADC_INT_NUM     ADC_INT_NUMBER1         // ADCA_INT1   -SOC2
#define PFC_DMA_ADC_INT_SOC     ADC_SOC_NUMBER2         // ADCA_INT1   -SOC2
#define PFC_DMA_IAC_TRIGGER     DMA_TRIGGER_ADCA1       // ADCA-INT1

// CMPSS
#define PFC_IAC_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_2    // A9*/C8, CMPSS2-HP
#define PFC_IAC_CMPHP_MUX       2                            // A9*/C8, CMPSS2-HP

#define PFC_VDC_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_2    // A4*/C14, CMPSS2-LP
#define PFC_VDC_CMPHP_MUX       0                            // A4*/C14, CMPSS2-LP

#define PFC_CMPSS_OFFSET_VALUE  (uint16_t)(USER_PFC_IAC_OFFSET * USER_PFC_ADC_INV_SF)

#define PFC_CMPSS_DACH_VALUE    1024
#define PFC_CMPSS_DACL_VALUE    2048

// XBAR-EPWM
#define PFC_XBAR_TRIP_ADDRL     XBAR_O_TRIP4MUX0TO15CFG
#define PFC_XBAR_TRIP_ADDRH     XBAR_O_TRIP4MUX16TO31CFG

#define PFC_IAC_XBAR_EPWM_MUX   XBAR_EPWM_MUX02_CMPSS2_CTRIPH   // A9*/C8, CMPSS4-HP
#define PFC_IAC_XBAR_MUX        XBAR_MUX02                      // A9*/C8, CMPSS4-HP

#define PFC_VDC_XBAR_EPWM_MUX   XBAR_EPWM_MUX03_CMPSS2_CTRIPL   // A4*/C14, CMPSS4-LP
#define PFC_VDC_XBAR_MUX        XBAR_MUX03                      // A4*/C14, CMPSS4-LP

#define PFC_XBAR_INPUT          XBAR_INPUT3
#define PFC_TZ_SIGNAL           EPWM_TZ_SIGNAL_OSHT3
#define PFC_XBAR_TRIP           XBAR_TRIP4
#define PFC_DCTRIPIN            EPWM_DC_COMBINATIONAL_TRIPIN4


//------------------------------------------------------------------------------
//! \ Motor 1
#define MTR1_PWM_U_BASE         EPWM1_BASE
#define MTR1_PWM_V_BASE         EPWM3_BASE
#define MTR1_PWM_W_BASE         EPWM5_BASE


//! \brief Defines the gpio for enabling Power Module
#define MTR1_GATE_EN_GPIO       28                  // N/A

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR1_PM_nFAULT_GPIO     22

#define MTR1_QEP_BASE           EQEP1_BASE          // N/A

// XBAR-EPWM
#define MTR1_XBAR_INPUT         XBAR_INPUT1
#define MTR1_TZ_OSHT            EPWM_TZ_SIGNAL_OSHT1

#define MTR1_XBAR_TRIP          XBAR_TRIP7
#define MTR1_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN7

#define MTR1_XBAR_TRIP_ADDRL    XBAR_O_TRIP7MUX0TO15CFG
#define MTR1_XBAR_TRIP_ADDRH    XBAR_O_TRIP7MUX16TO31CFG

#define MTR1_CMPSS_DACH_VALUE   (2048 + 1024 + 512)
#define MTR1_CMPSS_DACL_VALUE   (2048 - 1024 - 512)

//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR1_PWM_DBFED_CNT      215           // 2.15us, (>2.0us)

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR1_PWM_DBRED_CNT      220           // 2.20us, (>2.0us)

#if defined(MOTOR1_DCLINKSS)    // Single Shunt
// Single-shunt

// ADC
// Single shunt (need to connect NU, NV and NW using jumper wires)
#define MTR1_I_ADC_SAMPLE_WINDOW    10      // 10 sample cycles for current
#define MTR1_V_ADC_SAMPLE_WINDOW    20      // 20 sample cycles for voltage

#define MTR1_ADC_TRIGGER_SOC    ADC_TRIGGER_EPWM1_SOCA  // EPWM1_SOCA for single/three-shunt

#define MTR1_IDC1_TRIGGER_SOC   ADC_TRIGGER_EPWM3_SOCA  // EPWM3_SOCA for single-shunt
#define MTR1_IDC2_TRIGGER_SOC   ADC_TRIGGER_EPWM3_SOCB  // EPWM3_SOCB for single-shunt
#define MTR1_IDC3_TRIGGER_SOC   ADC_TRIGGER_EPWM5_SOCA  // EPWM5_SOCA for single-shunt
#define MTR1_IDC4_TRIGGER_SOC   ADC_TRIGGER_EPWM5_SOCB  // EPWM5_SOCB for single-shunt

// Single shunt (need to connect NU, NV and NW using jumper wires)
#define MTR1_IDC1_ADC_BASE      ADCC_BASE               // ADCC-A12/C1*-SOC0
#define MTR1_IDC2_ADC_BASE      ADCC_BASE               // ADCC-A12/C1*-SOC1
#define MTR1_IDC3_ADC_BASE      ADCC_BASE               // ADCC-A12/C1*-SOC2
#define MTR1_IDC4_ADC_BASE      ADCC_BASE               // ADCC-A12/C1*-SOC3

#define MTR1_IDC1_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A12/C1*
#define MTR1_IDC2_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A12/C1*
#define MTR1_IDC3_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A12/C1*
#define MTR1_IDC4_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A12/C1*

#define MTR1_IDC1_ADC_CH_NUM    ADC_CH_ADCIN1           // ADCC-A12/C1*
#define MTR1_IDC2_ADC_CH_NUM    ADC_CH_ADCIN1           // ADCC-A12/C1*
#define MTR1_IDC3_ADC_CH_NUM    ADC_CH_ADCIN1           // ADCC-A12/C1*
#define MTR1_IDC4_ADC_CH_NUM    ADC_CH_ADCIN1           // ADCC-A12/C1*

#define MTR1_IDC1_ADC_SOC_NUM   ADC_SOC_NUMBER0         // ADCC-A12/C1*-SOC0
#define MTR1_IDC2_ADC_SOC_NUM   ADC_SOC_NUMBER1         // ADCC-A12/C1*-SOC1
#define MTR1_IDC3_ADC_SOC_NUM   ADC_SOC_NUMBER2         // ADCC-A12/C1*-SOC2
#define MTR1_IDC4_ADC_SOC_NUM   ADC_SOC_NUMBER3         // ADCC-A12/C1*-SOC3

// CMPSS - Single Shunt
#define MTR1_CMPSS_IDC_BASE     CMPSSLITE4_BASE

// CMPSS - Single Shunt
#define MTR1_IDC_CMPLP_SEL      ASYSCTL_CMPLPMUX_SELECT_4    // A12/C1*, CMPSS4-LP
#define MTR1_IDC_CMPLP_MUX      2                            // A12/C1*, CMPSS4-LP

// XBAR-EPWM-TRIP
#define MTR1_IDC_XBAR_EPWM_MUX  XBAR_EPWM_MUX07_CMPSS4_CTRIPL       // CMPSS4-LP
#define MTR1_IDC_XBAR_MUX       XBAR_MUX07                          // CMPSS4-LP
#else   // !MOTOR1_DCLINKSS, Three-shunt
// Three-shunt
#define MTR1_I_ADC_SAMPLE_WINDOW  15                    // 15 sample cycles
#define MTR1_V_ADC_SAMPLE_WINDOW  20                    // 20 sample cycles

// ADC
#define MTR1_ADC_TRIGGER_SOC    ADC_TRIGGER_EPWM1_SOCA  // EPWM1_SOCA for single/three-shunt

// ADC - three shunt current
#define MTR1_IU_ADC_BASE        ADCC_BASE               // ADCC-A0/C15*
#define MTR1_IV_ADC_BASE        ADCC_BASE               // ADCC-A12/C1*
#define MTR1_IW_ADC_BASE        ADCC_BASE               // ADCC-A7/C3*

#define MTR1_IU_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A0/C15*
#define MTR1_IV_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A12/C1*
#define MTR1_IW_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A7/C3*

#define MTR1_IU_ADC_CH_NUM      ADC_CH_ADCIN15          // ADCC-A0/C15*
#define MTR1_IV_ADC_CH_NUM      ADC_CH_ADCIN1           // ADCC-A12/C1*
#define MTR1_IW_ADC_CH_NUM      ADC_CH_ADCIN3           // ADCC-A7/C3*

#define MTR1_IU_ADC_SOC_NUM     ADC_SOC_NUMBER1         // ADCC-A0/C15*-SOC1
#define MTR1_IV_ADC_SOC_NUM     ADC_SOC_NUMBER2         // ADCC-A12/C1*-SOC2
#define MTR1_IW_ADC_SOC_NUM     ADC_SOC_NUMBER3         // ADCC-A7/C3* -SOC3

#define MTR1_CMPSS_U_BASE       CMPSSLITE3_BASE
#define MTR1_CMPSS_V_BASE       CMPSSLITE4_BASE
#define MTR1_CMPSS_W_BASE       CMPSSLITE4_BASE

// CMPSS - Three Shunt
#define MTR1_IU_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // A0/C15*, CMPSS3-HP
#define MTR1_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // A0/C15*, CMPSS3-LP,NA

#define MTR1_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_4    // A12/C1*, CMPSS4-HP
#define MTR1_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_4    // A12/C1*, CMPSS4-LP,NA

#define MTR1_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_4    // A7/C3*, CMPSS4-HP,NA
#define MTR1_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_4    // A7/C3*, CMPSS4-LP

#define MTR1_IU_CMPHP_MUX       2                            // A0/C15*, CMPSS3-HP
#define MTR1_IU_CMPLP_MUX       2                            // A0/C15*, CMPSS3-LP, N/A

#define MTR1_IV_CMPHP_MUX       2                            // A12/C1*, CMPSS4-HP
#define MTR1_IV_CMPLP_MUX       2                            // A12/C1*, CMPSS4-LP,NA

#define MTR1_IW_CMPHP_MUX       1                            // A7/C3*, CMPSS4-HP, N/A
#define MTR1_IW_CMPLP_MUX       1                            // A7/C3*, CMPSS4-LP

// XBAR-EPWM-TRIP
#define MTR1_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX04_CMPSS3_CTRIPH       // CMPSS3-HP
#define MTR1_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX06_CMPSS4_CTRIPH       // CMPSS4-HP
#define MTR1_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX07_CMPSS4_CTRIPL       // CMPSS4-LP

#define MTR1_IU_XBAR_MUX        XBAR_MUX04          // CMPSS3-HP
#define MTR1_IV_XBAR_MUX        XBAR_MUX06          // CMPSS4-HP
#define MTR1_IW_XBAR_MUX        XBAR_MUX07          // CMPSS4-LP

#endif    // !MOTOR1_DCLINKSS, Three-shunt

// ADC -Three phase voltage and dc-bus voltage
#define MTR1_VU_ADC_BASE        ADCA_BASE               // ADCA-A8*/C11
#define MTR1_VV_ADC_BASE        ADCA_BASE               // ADCA-A1*
#define MTR1_VW_ADC_BASE        ADCA_BASE               // ADCA-A5*/C2
#ifndef PFC_DISABLE
#define MTR1_VDC_ADC_BASE       PFC_VDC_ADC_BASE        // ADCA-A4*/C14
#else   // PFC_DISABLE
#define MTR1_VDC_ADC_BASE       ADCA_BASE               // ADCA-A4*/C14
#endif  // PFC_DISABLE

#define MTR1_VU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A8*/C11
#define MTR1_VV_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A1*
#define MTR1_VW_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A5*/C2
#ifndef PFC_DISABLE
#define MTR1_VDC_ADCRES_BASE    PFC_VDC_ADCRES_BASE     // ADCA-A4*/C14
#else   // PFC_DISABLE
#define MTR1_VDC_ADCRES_BASE    ADCARESULT_BASE         // ADCA-A4*/C14
#endif  // PFC_DISABLE

#define MTR1_VU_ADC_CH_NUM      ADC_CH_ADCIN8           // ADCA-A8*/C11
#define MTR1_VV_ADC_CH_NUM      ADC_CH_ADCIN1           // ADCA-A1*
#define MTR1_VW_ADC_CH_NUM      ADC_CH_ADCIN5           // ADCA-A5*/C2
#ifndef PFC_DISABLE
#define MTR1_VDC_ADC_CH_NUM     PFC_VDC_ADC_CH_NUM      // ADCA-A4*/C14
#else   // PFC_DISABLE
#define MTR1_VDC_ADC_CH_NUM     ADC_CH_ADCIN4           // ADCA-A4*/C14
#endif  // PFC_DISABLE

#define MTR1_VU_ADC_SOC_NUM     ADC_SOC_NUMBER6         // ADCA-A8*/C11-SOC6
#define MTR1_VV_ADC_SOC_NUM     ADC_SOC_NUMBER7         // ADCA-A1*    -SOC7
#define MTR1_VW_ADC_SOC_NUM     ADC_SOC_NUMBER8         // ADCA-A5*/C2 -SOC8
#ifndef PFC_DISABLE
#define MTR1_VDC_ADC_SOC_NUM    PFC_VDC_ADC_SOC_NUM     // ADCA-A4*/C14-SOC2
#else   // PFC_DISABLE
#define MTR1_VDC_ADC_SOC_NUM    ADC_SOC_NUMBER15        // ADCA-A4*/C14-SOC15
#endif  // PFC_DISABLE

// interrupt
#define MTR1_PWM_INT_BASE       MTR1_PWM_U_BASE         // EPWM1

#if defined(MOTOR1_FAST)    // FAST +Single/Three-shunt
#define MTR1_ADC_INT_BASE       ADCA_BASE               // ADCA-A5*/C2 -SOC8
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER3         // ADCA_INT3-SOC8
#define MTR1_ADC_INT_SOC        ADC_SOC_NUMBER8         // ADCA_INT3-SOC8

#define MTR1_PIE_INT_NUM        INT_ADCA3               // ADCA_INT3-SOC8
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT3-CPU_INT10
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT3-CPU_INT10

#define MTR1_PIE_O_IER          PIE_O_IER10             // ADCA_INT3-CPU_INT10
#define MTR1_PIE_IER_INT        PIE_IER10_INTX3         // ADCA_INT3-PIE_INT3
#elif defined(MOTOR1_DCLINKSS) && defined(MOTOR1_ESMO)     // eSMO + Single/Three-shunt
#define MTR1_PIE_INT_NUM        INT_EPWM1               // EPWM1_INT
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT3      // EPWM1_INT-CPU_INT3
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP3    // EPWM1_INT-CPU_INT3

#define MTR1_PIE_O_IER          PIE_O_IER3              // EPWM1_INT-CPU_INT3
#define MTR1_PIE_IER_INT        PIE_IER3_INTX1          // EPWM1_INT-PIE_INT1
#elif defined(MOTOR1_ESMO)  // eSMO + Three Shunt
#define MTR1_ADC_INT_BASE       ADCC_BASE               // ADCC-A7/C3*-SOC6
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER3         // ADCC_INT3-SOC6
#define MTR1_ADC_INT_SOC        ADC_SOC_NUMBER6         // ADCC_INT3-SOC6

#define MTR1_PIE_INT_NUM        INT_ADCC3               // ADCC_INT3-SOC6
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCC_INT3-CPU_INT10
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCC_INT3-CPU_INT10

#define MTR1_PIE_O_IER          PIE_O_IER10             // ADCC_INT3-CPU_INT10
#define MTR1_PIE_IER_INT        PIE_IER10_INTX3         // ADCC_INT3-PIE_INT3
#else   // !(MOTOR1_FAST | MOTOR1_ESMO)
#error Not select a right current sampling mode and estimator
#endif  // !(MOTOR1_FAST | MOTOR1_ESMO)

//------------------------------------------------------------------------------
//! \Motor 2
#define MTR2_PWM_U_BASE         EPWM4_BASE
#define MTR2_PWM_V_BASE         EPWM6_BASE
#define MTR2_PWM_W_BASE         EPWM2_BASE

//! \brief Defines the gpio for enabling Power Module
#define MTR2_GATE_EN_GPIO       28                  // N/A

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR2_PM_nFAULT_GPIO     23

#define MTR2_QEP_BASE           EQEP2_BASE          // N/A


// XBAR-EPWM_TRIP
#define MTR2_XBAR_INPUT         XBAR_INPUT2
#define MTR2_TZ_OSHT            EPWM_TZ_SIGNAL_OSHT2
#define MTR2_XBAR_TRIP          XBAR_TRIP8
#define MTR2_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN8

// XBAR-EPWM_TRIP
#define MTR2_XBAR_TRIP_ADDRL    XBAR_O_TRIP8MUX0TO15CFG
#define MTR2_XBAR_TRIP_ADDRH    XBAR_O_TRIP8MUX16TO31CFG

#define MTR2_CMPSS_DACH_VALUE   (2048 + 1024 + 512)
#define MTR2_CMPSS_DACL_VALUE   (2048 - 1024 - 512)

//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR2_PWM_DBFED_CNT      175         // 1.75us (>1.5us)

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR2_PWM_DBRED_CNT      180         // 1.80us (>1.5us)

#if defined(MOTOR2_DCLINKSS)    // Single Shunt
#define MTR2_I_ADC_SAMPLE_WINDOW    10      // 10 sample cycles for current
#define MTR2_V_ADC_SAMPLE_WINDOW    20      // 20 sample cycles for voltage

#define MTR2_ADC_TRIGGER_SOC    ADC_TRIGGER_EPWM4_SOCA  // EPWM4_SOCA

// Single shunt (need to connect NU, NV and NW using jumper wires)
#define MTR2_IDC1_TRIGGER_SOC   ADC_TRIGGER_EPWM6_SOCA  // EPWM6_SOCA for single-shunt
#define MTR2_IDC2_TRIGGER_SOC   ADC_TRIGGER_EPWM6_SOCB  // EPWM6_SOCB for single-shunt
#define MTR2_IDC3_TRIGGER_SOC   ADC_TRIGGER_EPWM2_SOCA  // EPWM2_SOCA for single-shunt
#define MTR2_IDC4_TRIGGER_SOC   ADC_TRIGGER_EPWM2_SOCB  // EPWM2_SOCB for single-shunt

#define MTR2_IDC1_ADC_BASE      ADCC_BASE               // ADCC-A3/C5* -SOC4
#define MTR2_IDC2_ADC_BASE      ADCC_BASE               // ADCC-A3/C5* -SOC5
#define MTR2_IDC3_ADC_BASE      ADCC_BASE               // ADCC-A3/C5* -SOC6
#define MTR2_IDC4_ADC_BASE      ADCC_BASE               // ADCC-A3/C5* -SOC7

#define MTR2_IDC1_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A3/C5*
#define MTR2_IDC2_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A3/C5*
#define MTR2_IDC3_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A3/C5*
#define MTR2_IDC4_ADCRES_BASE   ADCCRESULT_BASE         // ADCC-A3/C5*

#define MTR2_IDC1_ADC_CH_NUM    ADC_CH_ADCIN5           // ADCC-A3/C5*
#define MTR2_IDC2_ADC_CH_NUM    ADC_CH_ADCIN5           // ADCC-A3/C5*
#define MTR2_IDC3_ADC_CH_NUM    ADC_CH_ADCIN5           // ADCC-A3/C5*
#define MTR2_IDC4_ADC_CH_NUM    ADC_CH_ADCIN5           // ADCC-A3/C5*

#define MTR2_IDC1_ADC_SOC_NUM   ADC_SOC_NUMBER4         // ADCC-A3/C5* -SOC4
#define MTR2_IDC2_ADC_SOC_NUM   ADC_SOC_NUMBER5         // ADCC-A3/C5* -SOC5
#define MTR2_IDC3_ADC_SOC_NUM   ADC_SOC_NUMBER6         // ADCC-A3/C5* -SOC6
#define MTR2_IDC4_ADC_SOC_NUM   ADC_SOC_NUMBER7         // ADCC-A3/C5* -SOC7

// CMPSS - Single Shunt
#define MTR2_CMPSS_IDC_BASE     CMPSSLITE3_BASE              // A3/C5*, CMPSS3-LP

#define MTR2_IDC_CMPLP_SEL      ASYSCTL_CMPLPMUX_SELECT_3    // A3/C5*, CMPSS3-LP
#define MTR2_IDC_CMPLP_MUX      3                            // A3/C5*, CMPSS3-LP

// XBAR-EPWM_Single Shunt
#define MTR2_IDC_XBAR_EPWM_MUX  XBAR_EPWM_MUX05_CMPSS3_CTRIPL       // CMPSS3-LP
#define MTR2_IDC_XBAR_MUX       XBAR_MUX05                          // CMPSS3-LP
#define MTR2_IDC_XBAR_OUT_MUX   XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL     // CMPSS3-LP, N/A
#else   // !MOTOR2_DCLINKSS, Three-shunt
#define MTR2_ADC_TRIGGER_SOC        ADC_TRIGGER_EPWM4_SOCA  // EPWM4_SOCA
#define MTR2_I_ADC_SAMPLE_WINDOW    15
#define MTR2_V_ADC_SAMPLE_WINDOW    20

// ADC, Three shunt current
#define MTR2_IU_ADC_BASE        ADCA_BASE               // ADCA-A2*/C9
#define MTR2_IV_ADC_BASE        ADCA_BASE               // ADCA-A6*
#define MTR2_IW_ADC_BASE        ADCA_BASE               // ADCA-A3*/C5

#define MTR2_IU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A2*/C9
#define MTR2_IV_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A6*
#define MTR2_IW_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A3*/C5

#define MTR2_IU_ADC_CH_NUM      ADC_CH_ADCIN2           // ADCA-A2*/C9
#define MTR2_IV_ADC_CH_NUM      ADC_CH_ADCIN6           // ADCA-A6*
#define MTR2_IW_ADC_CH_NUM      ADC_CH_ADCIN3           // ADCA-A3*/C5

#define MTR2_IU_ADC_SOC_NUM     ADC_SOC_NUMBER9         // ADCA-A2*/C9 -SOC9
#define MTR2_IV_ADC_SOC_NUM     ADC_SOC_NUMBER10        // ADCA-A6*    -SOC10
#define MTR2_IW_ADC_SOC_NUM     ADC_SOC_NUMBER11        // ADCA-A3*/C5 -SOC11

// CMPSS -Three shunt current
#define MTR2_CMPSS_U_BASE       CMPSS1_BASE
#define MTR2_CMPSS_V_BASE       CMPSS1_BASE
#define MTR2_CMPSS_W_BASE       CMPSSLITE3_BASE

#define MTR2_IU_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_1    // A2*/C9 CMPSS1-HP
#define MTR2_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_1    // A2*/C9 CMPSS1-LP, N/A

#define MTR2_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_1    // A6*, CMPSS1-HP, N/A
#define MTR2_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_1    // A6*, CMPSS1-LP

#define MTR2_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // A3*/C5, CMPSS3-HP, N/A
#define MTR2_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // A3*/C5, CMPSS3-LP

#define MTR2_IU_CMPHP_MUX       0       // A2*/C9, CMPSS1-HP
#define MTR2_IU_CMPLP_MUX       0       // A2*/C9, CMPSS1-LP, N/A

#define MTR2_IV_CMPHP_MUX       2       // A6*, CMPSS1-HP, N/A
#define MTR2_IV_CMPLP_MUX       2       // A6*, CMPSS1-LP

#define MTR2_IW_CMPHP_MUX       3       // A3*/C5, CMPSS3-HP, N/A
#define MTR2_IW_CMPLP_MUX       3       // A3*/C5, CMPSS3-LP

// XBAR-EPWM_Three Shunt
#define MTR2_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX00_CMPSS1_CTRIPH  // CMPSS1-HP
#define MTR2_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX01_CMPSS1_CTRIPL  // CMPSS1-LP
#define MTR2_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX05_CMPSS3_CTRIPL  // CMPSS3-LP

#define MTR2_IU_XBAR_MUX        XBAR_MUX00                      // CMPSS1-HP
#define MTR2_IV_XBAR_MUX        XBAR_MUX01                      // CMPSS1-LP
#define MTR2_IW_XBAR_MUX        XBAR_MUX05                      // CMPSS3-LP

#endif    // !MOTOR2_DCLINKSS, Three-shunt

// ADC, Three-phase voltage and dc-bus voltage
#define MTR2_VU_ADC_BASE        ADCA_BASE               // ADCA-A11*/C0
#define MTR2_VV_ADC_BASE        ADCA_BASE               // ADCA-A14*/C4
#define MTR2_VW_ADC_BASE        ADCA_BASE               // ADCA-A15*/C7
#ifndef PFC_DISABLE
#define MTR2_VDC_ADC_BASE       PFC_VDC_ADC_BASE        // ADCA-A4*/C14
#else   // PFC_DISABLE
#define MTR2_VDC_ADC_BASE       ADCA_BASE               // ADCA-A4*/C14
#endif  // PFC_DISABLE

#define MTR2_VU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A11*/C0
#define MTR2_VV_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A14*/C4
#define MTR2_VW_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A15*/C7
#ifndef PFC_DISABLE
#define MTR2_VDC_ADCRES_BASE    PFC_VDC_ADCRES_BASE     // ADCA-A4*/C14
#else   // PFC_DISABLE
#define MTR2_VDC_ADCRES_BASE    ADCARESULT_BASE         // ADCA-A4*/C14
#endif  // PFC_DISABLE

#define MTR2_VU_ADC_CH_NUM      ADC_CH_ADCIN11          // ADCA-A11*/C0
#define MTR2_VV_ADC_CH_NUM      ADC_CH_ADCIN14          // ADCA-A14*/C4
#define MTR2_VW_ADC_CH_NUM      ADC_CH_ADCIN15          // ADCA-A15*/C7
#ifndef PFC_DISABLE
#define MTR2_VDC_ADC_CH_NUM     PFC_VDC_ADC_CH_NUM      // ADCA-A4*/C14
#else   // PFC_DISABLE
#define MTR2_VDC_ADC_CH_NUM     ADC_CH_ADCIN4           // ADCA-A4*/C14
#endif  // PFC_DISABLE

#define MTR2_VU_ADC_SOC_NUM     ADC_SOC_NUMBER12        // ADCA-A11*/C0-SOC12
#define MTR2_VV_ADC_SOC_NUM     ADC_SOC_NUMBER13        // ADCA-A14*/C4-SOC13
#define MTR2_VW_ADC_SOC_NUM     ADC_SOC_NUMBER14        // ADCA-A15*/C7-SOC14
#ifndef PFC_DISABLE
#define MTR2_VDC_ADC_SOC_NUM    PFC_VDC_ADC_SOC_NUM     // ADCA-A4*/C14-SOC2
#else   // PFC_DISABLE
#define MTR2_VDC_ADC_SOC_NUM    ADC_SOC_NUMBER15        // ADCA-A4*/C14-SOC15
#endif  // PFC_DISABLE

// Interrupt
#define MTR2_PWM_INT_BASE       MTR2_PWM_U_BASE         // EPWM4

#if defined(MOTOR2_FAST)
#define MTR2_ADC_INT_BASE       ADCA_BASE               // ADCA-A15*/C7 -SOC14
#define MTR2_ADC_INT_NUM        ADC_INT_NUMBER4         // ADCA_INT4-SOC14
#define MTR2_ADC_INT_SOC        ADC_SOC_NUMBER14        // ADCA_INT4-SOC14

#define MTR2_PIE_INT_NUM        INT_ADCA4               // ADCA_INT4-SOC14
#define MTR2_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT4-CPU_INT10
#define MTR2_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT4-CPU_INT10

#define MTR2_PIE_O_IER          PIE_O_IER10             // ADCA_INT4-CPU_INT10
#define MTR2_PIE_IER_INT        PIE_IER10_INTX4         // ADCA_INT4-PIE_INT4
#elif defined(MOTOR2_DCLINKSS) && defined(MOTOR2_ESMO)     // eSMO + Single/Three-shunt
#define MTR2_PIE_INT_NUM        INT_EPWM4               // EPWM4_INT
#define MTR2_CPU_INT_NUM        INTERRUPT_CPU_INT3      // EPWM4_INT-CPU_INT3
#define MTR2_INT_ACK_GROUP      INTERRUPT_ACK_GROUP3    // EPWM4_INT-CPU_INT3

#define MTR2_PIE_O_IER          PIE_O_IER3              // EPWM4_INT-CPU_INT3
#define MTR2_PIE_IER_INT        PIE_IER3_INTX1          // EPWM4_INT-PIE_INT1
#elif defined(MOTOR2_ESMO)   // MOTOR2_ESMO
#define MTR2_ADC_INT_BASE       ADCA_BASE               // ADCA-A3*/C5 -SOC11
#define MTR2_ADC_INT_NUM        ADC_INT_NUMBER4         // ADCA_INT4-SOC11
#define MTR2_ADC_INT_SOC        ADC_SOC_NUMBER11        // ADCA_INT4-SOC11
#define MTR2_PIE_INT_NUM        INT_ADCA4               // ADCA_INT4-SOC11
#define MTR2_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT4-CPU_INT10
#define MTR2_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT4-CPU_INT10

#define MTR2_PIE_O_IER          PIE_O_IER10             // ADCA_INT4-CPU_INT10
#define MTR2_PIE_IER_INT        PIE_IER10_INTX4         // ADCA_INT4-PIE_INT10
#else
#error Not select a right current sampling mode and estimator
#endif  // MOTOR2_FAST | MOTOR2_ESMO

//------------------------------------------------------------------------------
#define SYS1_ADC_TRIGGER_SOC    ADC_TRIGGER_EPWM1_SOCA  // EPWM1_SOCA

#define SYS1_PIPE_ADC_BASE      ADCA_BASE               // ADCA-A15*/C7
#define SYS1_EXHA_ADC_BASE      ADCC_BASE               // ADCA-C6*
#define SYS1_ENVI_ADC_BASE      ADCA_BASE               // ADCA-A18*/C18
#define SYS1_M1PT_ADC_BASE      ADCA_BASE               // ADCA-A11*/C0
#define SYS1_M2PT_ADC_BASE      ADCA_BASE               // ADCA-A14*/C4

#define SYS1_PIPE_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A15*/C7
#define SYS1_EXHA_ADCRES_BASE   ADCCRESULT_BASE         // ADCA-C6*
#define SYS1_ENVI_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A18*/C18
#define SYS1_M1PT_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A11*/C0
#define SYS1_M2PT_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A14*/C4

#define SYS1_PIPE_ADC_CH_NUM    ADC_CH_ADCIN15          // ADCA-A15*/C7
#define SYS1_EXHA_ADC_CH_NUM    ADC_CH_ADCIN6           // ADCA-C6*
#define SYS1_ENVI_ADC_CH_NUM    ADC_CH_ADCIN18          // ADCA-A18*/C18
#define SYS1_M1PT_ADC_CH_NUM    ADC_CH_ADCIN11          // ADCA-A11*/C0
#define SYS1_M2PT_ADC_CH_NUM    ADC_CH_ADCIN13          // ADCA-A14*/C4

#define SYS1_PIPE_ADC_SOC_NUM   ADC_SOC_NUMBER11        // ADCA-A15*/C7 -SOC11
#define SYS1_EXHA_ADC_SOC_NUM   ADC_SOC_NUMBER12        // ADCA-C6*     -SOC12
#define SYS1_ENVI_ADC_SOC_NUM   ADC_SOC_NUMBER13        // ADCA-A18*/C18-SOC13
#define SYS1_M1PT_ADC_SOC_NUM   ADC_SOC_NUMBER14        // ADCA-A11*/C0 -SOC14
#define SYS1_M2PT_ADC_SOC_NUM   ADC_SOC_NUMBER15        // ADCA-A14*/C4 -SOC15

#define SYS1_PIPE_ADCRESLT      (SYS1_PIPE_ADCRES_BASE + ADC_O_RESULT11)  // ADCA-A15*/C7 -SOC11
#define SYS1_EXHA_ADCRESLT      (SYS1_EXHA_ADCRES_BASE + ADC_O_RESULT12)  // ADCA-C6*     -SOC12
#define SYS1_ENVI_ADCRESLT      (SYS1_ENVI_ADCRES_BASE + ADC_O_RESULT13)  // ADCA-A18*/C18-SOC13
#define SYS1_M1PT_ADCRESLT      (SYS1_ENVI_ADCRES_BASE + ADC_O_RESULT14)  // ADCA-A11*/C0 -SOC14
#define SYS1_M2PT_ADCRESLT      (SYS1_ENVI_ADCRES_BASE + ADC_O_RESULT15)  // ADCA-A14*/C4 -SOC15

// DMCPFC_REV3P2 | DMCPFC_REV3P1

#elif defined(HVMTRPFC_REV1P1)

#define TEST_SWITCH_GPIO        5

#define ACPOWER_RELAY_GPIO      32

//! \brief Power relay for Four-Way Relay
#define FOURWAY_RELAY_GPIO      33

//------------------------------------------------------------------------------
#define EPWMDAC1_BASE           EPWM6_BASE
#define EPWMDAC2_BASE           EPWM6_BASE
#define EPWMDAC3_BASE           EPWM7_BASE
#define EPWMDAC4_BASE           EPWM7_BASE

//------------------------------------------------------------------------------
#define PFC_PWM_BASE            EPWM4_BASE
#define PFC_CMPSS_IAC_BASE      CMPSS1_BASE

#define PFC_XBAROUTPUT          XBAR_OUTPUT4        // N/A

#define PFC_XBAROUTPUT_CFGL     XBAR_O_OUTPUT4MUX0TO15CFG
#define PFC_XBAROUTPUT_CFGH     XBAR_O_OUTPUT4MUX16TO31CFG

//------------------------------------------------------------------------------
#define PFC_EPWM_SYSN_O_TIME    2
#define MTR_EPWM_SYSN_O_TIME    2

//------------------------------------------------------------------------------
//! \ PFC
// ADC
#define PFC_ADC_TRIGGER_IAC      ADC_TRIGGER_CPU1_TINT1  // CPU_TINT1
#define PFC_ADC_TRIGGER_VIS1     ADC_TRIGGER_EPWM4_SOCA  // EPWM4_SOCA, @Period
#define PFC_ADC_TRIGGER_VIS2     ADC_TRIGGER_EPWM4_SOCB  // EPWM4_SOCB, @Zero

#define PFC_IADC_SAMPLE_WINDOW  15
#define PFC_VADC_SAMPLE_WINDOW  20

#define PFC_IAC_ADC_BASE        ADCA_BASE               // ADCA-A6*
#define PFC_VAC_ADC_BASE        ADCA_BASE               // ADCA-A14*/C4
#define PFC_VDC_ADC_BASE        ADCA_BASE               // ADCA-A4*/C14
#define PFC_VAN_ADC_BASE        ADCA_BASE               // ADCA-A11*/C0

#define PFC_IAC_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A6*
#define PFC_VAC_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A14*/C4
#define PFC_VDC_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A4*/C14
#define PFC_VAN_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A11*/C0

#define PFC_IAC_ADC_CH_NUM      ADC_CH_ADCIN6           // ADCA-A6*
#define PFC_VAC_ADC_CH_NUM      ADC_CH_ADCIN14          // ADCA-A14*/C4
#define PFC_VDC_ADC_CH_NUM      ADC_CH_ADCIN4           // ADCA-A4*/C14
#define PFC_VAN_ADC_CH_NUM      ADC_CH_ADCIN11          // ADCA-A11*/C0

#define PFC_IAC1_ADC_SOC_NUM    ADC_SOC_NUMBER0         // ADCA-A6*    -SOC0-PPB1
#define PFC_VAC1_ADC_SOC_NUM    ADC_SOC_NUMBER1         // ADCA-A14*/C4-SOC1-PPB2
#define PFC_VDC1_ADC_SOC_NUM    ADC_SOC_NUMBER2         // ADCA-A4*/C14-SOC2
#define PFC_VAN1_ADC_SOC_NUM    ADC_SOC_NUMBER3         // ADCA-A11*/C0-SOC3

#define PFC_IAC2_ADC_SOC_NUM    ADC_SOC_NUMBER4         // ADCA-A6*    -SOC4-PPB3
#define PFC_VAC2_ADC_SOC_NUM    ADC_SOC_NUMBER5         // ADCA-A14*/C4-SOC5-PPB4
#define PFC_VDC2_ADC_SOC_NUM    ADC_SOC_NUMBER6         // ADCA-A4*/C14-SOC6
#define PFC_VAN2_ADC_SOC_NUM    ADC_SOC_NUMBER7         // ADCA-A11*/C0-SOC7

#define PFC_IAC1_ADC_PPB_NUM    ADC_PPB_NUMBER1         // ADCA-A6*    -SOC0-PPB1
#define PFC_VAC1_ADC_PPB_NUM    ADC_PPB_NUMBER2         // ADCA-A14*/C4-SOC1-PPB2

#define PFC_IAC2_ADC_PPB_NUM    ADC_PPB_NUMBER3         // ADCA-A6*    -SOC4-PPB3
#define PFC_VAC2_ADC_PPB_NUM    ADC_PPB_NUMBER4         // ADCA-A14*/C4-SOC5-PPB4

#define PFC_IAC_ADC_SOC_NUM     PFC_IAC1_ADC_SOC_NUM    // ADCA-A6*    -SOC0-PPB1
#define PFC_VAC_ADC_SOC_NUM     PFC_VAC1_ADC_SOC_NUM    // ADCA-A14*/C4-SOC1-PPB2
#define PFC_VDC_ADC_SOC_NUM     PFC_VDC1_ADC_SOC_NUM    // ADCA-A4*/C14-SOC2
#define PFC_VAN_ADC_SOC_NUM     PFC_VAN1_ADC_SOC_NUM    // ADCA-A11*/C0-SOC3

#define PFC_IAC_ADC_PPB_NUM     PFC_IAC1_ADC_PPB_NUM    // ADCA-A6*    -SOC0-PPB1
#define PFC_VAC_ADC_PPB_NUM     PFC_VAC1_ADC_PPB_NUM    // ADCA-A14*/C4-SOC1-PPB2

#define PFC_IAC_ADCRES_ADDR     (PFC_IAC_ADCRES_BASE + \
                                 ADC_PPBxRESULT_OFFSET_BASE + \
                                 PFC_IAC_ADC_PPB_NUM * 2U)

#define PFC_IAC1_ADCRESLT       (PFC_IAC_ADCRES_BASE + ADC_O_RESULT0)   // ADCA-A6*    -SOC0
#define PFC_VAC1_ADCRESLT       (PFC_VAC_ADCRES_BASE + ADC_O_RESULT1)   // ADCC-A14*/C4-SOC1
#define PFC_VDC1_ADCRESLT       (PFC_VDC_ADCRES_BASE + ADC_O_RESULT2)   // ADCC-A4*/C14-SOC2
#define PFC_VAN1_ADCRESLT       (PFC_VAN_ADCRES_BASE + ADC_O_RESULT3)   // ADCA-A11*/C0-SOC3

#define PFC_IAC2_ADCRESLT       (PFC_IAC_ADCRES_BASE + ADC_O_RESULT4)   // ADCA-A6*    -SOC4
#define PFC_VAC2_ADCRESLT       (PFC_VAC_ADCRES_BASE + ADC_O_RESULT5)   // ADCC-A14*/C4-SOC5
#define PFC_VDC2_ADCRESLT       (PFC_VDC_ADCRES_BASE + ADC_O_RESULT6)   // ADCC-A4*/C14-SOC6
#define PFC_VAN2_ADCRESLT       (PFC_VAN_ADCRES_BASE + ADC_O_RESULT7)   // ADCA-A11*/C0-SOC7

#define PFC_IAC_ADCRESLT        PFC_IAC1_ADCRESLT                       // ADCC-A6*    -SOC0-PPB1
#define PFC_VAC_ADCRESLT        PFC_VAC1_ADCRESLT                       // ADCC-A14*/C4-SOC1-PPB2
#define PFC_VDC_ADCRESLT        PFC_VDC1_ADCRESLT                       // ADCC-A4*/C14-SOC2
#define PFC_VAN_ADCRESLT        PFC_VAN1_ADCRESLT                       // ADCC-A11*/C0-SOC3

//------------------------------------------------------------------------------
// Interrupt
#define PFC_PWM_INT_BASE        PFC_PWM_BASE            // EPWM4

#define PFC_ADC_INT_BASE        ADCA_BASE               // ADCA-A11 -SOC3
#define PFC_ADC_INT_NUM         ADC_INT_NUMBER2         // ADCA_INT2-SOC3
#define PFC_ADC_INT_SOC         ADC_SOC_NUMBER3         // ADCA_INT2-SOC3
#define PFC_PIE_INT_NUM         INT_ADCA2               // ADCA_INT2-SOC3
#define PFC_CPU_INT_NUM         INTERRUPT_CPU_INT10     // ADCA_INT2-CPU_INT10
#define PFC_INT_ACK_GROUP       INTERRUPT_ACK_GROUP10   // ADCA_INT2-CPU_INT10

#define PFC_PIE_O_IER           PIE_O_IER10             // ADCA_INT2-CPU_INT10
#define PFC_PIE_IER_INT         PIE_IER10_INTX2         // ADCA_INT2-PIE_INT3

// Not use DMA
#define PFC_DMA_ADC_INT_BASE    ADCA_BASE               // ADCA-A6 -SOC0
#define PFC_DMA_ADC_INT_NUM     ADC_INT_NUMBER1         // ADCA_INT1-SOC0
#define PFC_DMA_ADC_INT_SOC     ADC_SOC_NUMBER0         // ADCC_INT1-SOC0, ILPFC
#define PFC_DMA_IAC_TRIGGER     DMA_TRIGGER_ADCA1       // ADCA-INT1

//------------------------------------------------------------------------------
// CMPSS
#define PFC_IAC_CMPHP_SEL        ASYSCTL_CMPHPMUX_SELECT_1    // A6*, CMPSS1-HP
#define PFC_IAC_CMPHP_MUX        2                            // A6*, CMPSS1-HP

#define PFC_CMPSS_OFFSET_VALUE  (uint16_t)(USER_PFC_IAC_OFFSET * USER_PFC_ADC_INV_SF)

#define PFC_CMPSS_DACH_VALUE     1024
#define PFC_CMPSS_DACL_VALUE     2048

//-----------------------------------------------------------------------------
// XBAR-EPWM
#define PFC_XBAR_TRIP_ADDRL     XBAR_O_TRIP4MUX0TO15CFG
#define PFC_XBAR_TRIP_ADDRH     XBAR_O_TRIP4MUX16TO31CFG

#define PFC_IAC_XBAR_EPWM_MUX   XBAR_EPWM_MUX00_CMPSS1_CTRIPH   //  A6*, CMPSS1-HP

#define PFC_IAC_XBAR_MUX        XBAR_MUX00          //  A6*, CMPSS1-HP

#define PFC_XBAR_INPUT          XBAR_INPUT3
#define PFC_TZ_SIGNAL           EPWM_TZ_SIGNAL_OSHT3
#define PFC_XBAR_TRIP           XBAR_TRIP4
#define PFC_DCTRIPIN            EPWM_DC_COMBINATIONAL_TRIPIN4


//------------------------------------------------------------------------------
//! \ Motor 1
#define MTR1_PWM_U_BASE         EPWM1_BASE
#define MTR1_PWM_V_BASE         EPWM2_BASE
#define MTR1_PWM_W_BASE         EPWM3_BASE

#define MTR1_CMPSS_IDC_BASE     CMPSS1_BASE

#define MTR1_CMPSS_U_BASE       CMPSSLITE3_BASE
#define MTR1_CMPSS_V_BASE       CMPSSLITE2_BASE
#define MTR1_CMPSS_W_BASE       CMPSSLITE3_BASE


//! \brief Defines the gpio for enabling Power Module
#define MTR1_GATE_EN_GPIO       9                   // N/A

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR1_PM_nFAULT_GPIO     39

#define MTR1_SPI_BASE           SPIA_BASE           // N/A
#define MTR1_QEP_BASE           EQEP1_BASE          // N/A

//------------------------------------------------------------------------------
// ADC
#define MTR1_ADC_TRIGGER_SOC     ADC_TRIGGER_EPWM1_SOCA  // EPWM1_SOCA


// three shunt
#define MTR1_ADC_SAMPLE_WINDOW  14

#define MTR1_IU_ADC_BASE        ADCC_BASE               // ADCC-C6*
#define MTR1_IV_ADC_BASE        ADCC_BASE               // ADCC-A12/C1*
#define MTR1_IW_ADC_BASE        ADCC_BASE               // ADCC-A3/C5*
#define MTR1_VU_ADC_BASE        ADCC_BASE               // ADCC-A8/C11*
#define MTR1_VV_ADC_BASE        ADCC_BASE               // ADCC-A10/C10*
#define MTR1_VW_ADC_BASE        ADCC_BASE               // ADCC-A15/C7*
#if defined(PFC_DISABLE)
#define MTR1_VDC_ADC_BASE       ADCC_BASE               // ADCA-A7/C3*
#else
#define MTR1_VDC_ADC_BASE       PFC_VDC_ADC_BASE        // ADCA-A4*/C14
#endif  // !PFC_DISABLE

#define MTR1_IU_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-C6*
#define MTR1_IV_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A12/C1*
#define MTR1_IW_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A3/C5*
#define MTR1_VU_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A8/C11*
#define MTR1_VV_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A10/C10*
#define MTR1_VW_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A15/C7*
#if defined(PFC_DISABLE)
#define MTR1_VDC_ADCRES_BASE    ADCCRESULT_BASE         // ADCA-A7/C3*
#else
#define MTR1_VDC_ADCRES_BASE    PFC_VDC_ADCRES_BASE     // ADCA-A4*/C14
#endif  // !PFC_DISABLE

#define MTR1_IU_ADC_CH_NUM      ADC_CH_ADCIN6           // ADCC-C6*
#define MTR1_IV_ADC_CH_NUM      ADC_CH_ADCIN1           // ADCC-A12/C1*
#define MTR1_IW_ADC_CH_NUM      ADC_CH_ADCIN5           // ADCC-A3/C5*
#define MTR1_VU_ADC_CH_NUM      ADC_CH_ADCIN11          // ADCC-A8/C11*
#define MTR1_VV_ADC_CH_NUM      ADC_CH_ADCIN10          // ADCC-A10/C10*
#define MTR1_VW_ADC_CH_NUM      ADC_CH_ADCIN7           // ADCC-A15/C7*
#if defined(PFC_DISABLE)
#define MTR1_VDC_ADC_CH_NUM     ADC_CH_ADCIN3           // ADCA-A7/C3*
#else
#define MTR1_VDC_ADC_CH_NUM     PFC_VDC_ADC_CH_NUM      // ADCA-A4*/C14
#endif  // !PFC_DISABLE

#define MTR1_IU_ADC_SOC_NUM     ADC_SOC_NUMBER0         // ADCC-C6*     -SOC0
#define MTR1_IV_ADC_SOC_NUM     ADC_SOC_NUMBER1         // ADCC-A12/C1* -SOC1
#define MTR1_IW_ADC_SOC_NUM     ADC_SOC_NUMBER2         // ADCC-A3/C5*  -SOC2
#define MTR1_VU_ADC_SOC_NUM     ADC_SOC_NUMBER3         // ADCC-A8/C11* -SOC3
#define MTR1_VV_ADC_SOC_NUM     ADC_SOC_NUMBER4         // ADCC-A10/C10*-SOC4
#define MTR1_VW_ADC_SOC_NUM     ADC_SOC_NUMBER5         // ADCC-A15/C7* -SOC5
#if defined(PFC_DISABLE)
#define MTR1_VDC_ADC_SOC_NUM    ADC_SOC_NUMBER6         // ADCA-A7/C3*  -SOC6
#else
#define MTR1_VDC_ADC_SOC_NUM    PFC_VDC_ADC_SOC_NUM     // ADCA-A4*/C14
#endif  // !PFC_DISABLE

#define MTR1_IU_ADCRESLT        (MTR1_IU_ADCRES_BASE + ADC_O_RESULT0)  // ADCC-C6*     -SOC0
#define MTR1_IV_ADCRESLT        (MTR1_IV_ADCRES_BASE + ADC_O_RESULT1)  // ADCC-A12/C1* -SOC1
#define MTR1_IW_ADCRESLT        (MTR1_IW_ADCRES_BASE + ADC_O_RESULT2)  // ADCC-A3/C5*  -SOC2
#define MTR1_VU_ADCRESLT        (MTR1_VU_ADCRES_BASE + ADC_O_RESULT3)  // ADCC-A8/C11* -SOC3
#define MTR1_VV_ADCRESLT        (MTR1_VV_ADCRES_BASE + ADC_O_RESULT4)  // ADCC-A10/C10*-SOC4
#define MTR1_VW_ADCRESLT        (MTR1_VW_ADCRES_BASE + ADC_O_RESULT5)  // ADCC-A15/C7* -SOC5
#if defined(PFC_DISABLE)
#define MTR1_VDC_ADCRESLT       (MTR1_VDC_ADCRES_BASE + ADC_O_RESULT6) // ADCA-A7/C3*  -SOC6
#else
#define MTR1_VDC_ADCRESLT       PFC_VDC_ADCRESLT                       // ADCA-A4*/C14
#endif  // !PFC_DISABLE

//------------------------------------------------------------------------------
// interrupt
#define MTR1_ADC_INT_BASE       ADCC_BASE               // ADCC-C7  -SOC5
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER2         // ADCC_INT2-SOC5
#define MTR1_ADC_INT_SOC        ADC_SOC_NUMBER5         // ADCC_INT2-SOC5
#define MTR1_PIE_INT_NUM        INT_ADCC2               // ADCC_INT2-SOC5
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCC_INT2-CPU_INT10
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCC_INT2-CPU_INT10

#define MTR1_PIE_O_IER          PIE_O_IER10             // ADCC_INT2-CPU_INT10
#define MTR1_PIE_IER_INT        PIE_IER10_INTX10        // ADCC_INT2-PIE_INT10
//------------------------------------------------------------------------------
// CMPSS
#define MTR1_IDC_CMPLP_SEL      ASYSCTL_CMPLPMUX_SELECT_1    // A2/C9*, CMPSS1-LP
#define MTR1_IDC_CMPLP_MUX      0                            // A2/C9*, CMPSS1-LP

#define MTR1_IU_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // C6*, CMPSS3-HP
#define MTR1_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // C6*, CMPSS3-LP, N/A

#define MTR1_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_2    // A12/C1*, CMPSS2-HP
#define MTR1_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_2    // A12/C1*, CMPSS2-LP

#define MTR1_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // A3/C5*, CMPSS3-HP, N/A
#define MTR1_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // A3/C5*, CMPSS3-LP

#define MTR1_IU_CMPHP_MUX       0                            // C6*, CMPSS3-HP
#define MTR1_IU_CMPLP_MUX       0                            // C6*, CMPSS3-LP, N/A

#define MTR1_IV_CMPHP_MUX       1                            // A12/C1*, CMPSS2-HP
#define MTR1_IV_CMPLP_MUX       1                            // A12/C1*, CMPSS2-LP

#define MTR1_IW_CMPHP_MUX       3                            // A3/C5*, CMPSS3-HP, N/A
#define MTR1_IW_CMPLP_MUX       3                            // A3/C5*, CMPSS3-LP

#define MTR1_CMPSS_DACH_VALUE   (2048 + 1024 + 512)
#define MTR1_CMPSS_DACL_VALUE   (2048 - 1024 - 512)

//------------------------------------------------------------------------------
// XBAR-EPWM
#define MTR1_XBAR_TRIP_ADDRL    XBAR_O_TRIP7MUX0TO15CFG
#define MTR1_XBAR_TRIP_ADDRH    XBAR_O_TRIP7MUX16TO31CFG

#define MTR1_IDC_XBAR_EPWM_MUX  XBAR_EPWM_MUX01_CMPSS1_CTRIPL  // CMPSS1_LP
#define MTR1_IDC_XBAR_MUX       XBAR_MUX01                     // CMPSS1

#define MTR1_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX04_CMPSS3_CTRIPH       // CMPSS3-HP
#define MTR1_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L  // CMPSS2-HP&LP
#define MTR1_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX05_CMPSS3_CTRIPL       // CMPSS3-LP

#define MTR1_IU_XBAR_MUX        XBAR_MUX04          // CMPSS3-HP
#define MTR1_IV_XBAR_MUX        XBAR_MUX02          // CMPSS2-HP&LP
#define MTR1_IW_XBAR_MUX        XBAR_MUX05          // CMPSS3-LP

#define MTR1_XBAR_INPUT         XBAR_INPUT1
#define MTR1_TZ_OSHT            EPWM_TZ_SIGNAL_OSHT1
#define MTR1_XBAR_TRIP          XBAR_TRIP7
#define MTR1_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN7


//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR1_PWM_DBFED_CNT      225           // 2.25us

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR1_PWM_DBRED_CNT      245           // 2.45us

//------------------------------------------------------------------------------
//! \Motor 2
#if defined(TEST_MOTOR2)
#define MTR1_PWM_U_BASE         EPWM1_BASE
#define MTR1_PWM_V_BASE         EPWM2_BASE
#define MTR1_PWM_W_BASE         EPWM3_BASE

#define MTR1_ADC_TRIGGER_SOC     ADC_TRIGGER_EPWM1_SOCA  // EPWM1_SOCA

#define MTR2_CMPSS_U_BASE       CMPSSLITE3_BASE
#define MTR2_CMPSS_V_BASE       CMPSSLITE4_BASE
#define MTR2_CMPSS_W_BASE       CMPSSLITE3_BASE
#else
#define MTR2_PWM_U_BASE         EPWM5_BASE
#define MTR2_PWM_V_BASE         EPWM5_BASE
#define MTR2_PWM_W_BASE         EPWM5_BASE

#define MTR2_ADC_TRIGGER_SOC     ADC_TRIGGER_EPWM5_SOCA  // EPWM5_SOCA

#define MTR2_CMPSS_U_BASE       CMPSSLITE4_BASE
#define MTR2_CMPSS_V_BASE       CMPSSLITE4_BASE
#define MTR2_CMPSS_W_BASE       CMPSSLITE4_BASE
#endif  // TEST_MOTOR2


//! \brief Defines the gpio for enabling Power Module
#define MTR2_GATE_EN_GPIO       24                   // N/A

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR2_PM_nFAULT_GPIO     25

#define MTR2_SPI_BASE           SPIB_BASE           // N/A
#define MTR2_QEP_BASE           EQEP1_BASE          // N/A

//------------------------------------------------------------------------------
// ADC
#define MTR2_ADC_SAMPLE_WINDOW  14

#define MTR2_IU_ADC_BASE        ADCC_BASE               // ADCC-C6*
#define MTR2_IV_ADC_BASE        ADCC_BASE               // ADCC-A9/C8*
#define MTR2_IW_ADC_BASE        ADCC_BASE               // ADCC-A5/C2*
#define MTR2_VU_ADC_BASE        ADCC_BASE               // ADCC-A8/C11*
#define MTR2_VV_ADC_BASE        ADCC_BASE               // ADCC-A10/C10*
#define MTR2_VW_ADC_BASE        ADCC_BASE               // ADCC-A15/C7*
#if defined(PFC_DISABLE)
#define MTR2_VDC_ADC_BASE       MTR1_VDC_ADC_BASE       // ADCA-A7/C3*
#else
#define MTR2_VDC_ADC_BASE       PFC_VDC_ADC_BASE        // ADCA-A4*/C14
#endif  // !PFC_DISABLE

#define MTR2_IU_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-C6*
#define MTR2_IV_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A9/C8*
#define MTR2_IW_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A5/C2*
#define MTR2_VU_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A8/C11*
#define MTR2_VV_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A10/C10*
#define MTR2_VW_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A15/C7*
#if defined(PFC_DISABLE)
#define MTR2_VDC_ADCRES_BASE    MTR1_VDC_ADCRES_BASE    // ADCA-A7/C3*
#else
#define MTR2_VDC_ADCRES_BASE    PFC_VDC_ADCRES_BASE     // ADCC-A4*/C14
#endif  // !PFC_DISABLE

#define MTR2_IU_ADC_CH_NUM      ADC_CH_ADCIN6           // ADCC-C6
#define MTR2_IV_ADC_CH_NUM      ADC_CH_ADCIN8           // ADCC-A9/C8*
#define MTR2_IW_ADC_CH_NUM      ADC_CH_ADCIN2           // ADCC-A5/C2*
#define MTR2_VU_ADC_CH_NUM      ADC_CH_ADCIN11          // ADCC-A8/C11*
#define MTR2_VV_ADC_CH_NUM      ADC_CH_ADCIN10          // ADCC-A10/C10*
#define MTR2_VW_ADC_CH_NUM      ADC_CH_ADCIN7           // ADCC-A15/C7*
#if defined(PFC_DISABLE)
#define MTR2_VDC_ADC_CH_NUM     MTR1_VDC_ADC_CH_NUM     // ADCA-A7/C3*
#else
#define MTR2_VDC_ADC_CH_NUM     PFC_VDC_ADC_CH_NUM      // ADCA-A4*/C14
#endif  // !PFC_DISABLE

#define MTR2_IU_ADC_SOC_NUM     ADC_SOC_NUMBER7         // ADCC-C6      -SOC7
#define MTR2_IV_ADC_SOC_NUM     ADC_SOC_NUMBER8         // ADCC-A9/C8*  -SOC8
#define MTR2_IW_ADC_SOC_NUM     ADC_SOC_NUMBER9         // ADCC-A5/C2*  -SOC9
#define MTR2_VU_ADC_SOC_NUM     ADC_SOC_NUMBER10        // ADCC-A8/C11* -SOC10
#define MTR2_VV_ADC_SOC_NUM     ADC_SOC_NUMBER11        // ADCC-A10/C10*-SOC11
#define MTR2_VW_ADC_SOC_NUM     ADC_SOC_NUMBER12        // ADCC-A15/C7* -SOC12
#if defined(PFC_DISABLE)
#define MTR2_VDC_ADC_SOC_NUM    MTR1_VDC_ADC_SOC_NUM    // ADCA-A7/C3*  -SOC6
#else
#define MTR2_VDC_ADC_SOC_NUM    PFC_VDC_ADC_SOC_NUM     // ADCA-A4*/C14
#endif  // !PFC_DISABLE

#define MTR2_IU_ADCRESLT        (MTR2_IU_ADCRES_BASE + ADC_O_RESULT7)   // ADCC-C6*     -SOC7
#define MTR2_IV_ADCRESLT        (MTR2_IV_ADCRES_BASE + ADC_O_RESULT8)   // ADCC-A9/C8*  -SOC8
#define MTR2_IW_ADCRESLT        (MTR2_IW_ADCRES_BASE + ADC_O_RESULT9)   // ADCC-A5/C2*  -SOC9
#define MTR2_VU_ADCRESLT        (MTR2_VU_ADCRES_BASE + ADC_O_RESULT10)  // ADCC-A8/C11* -SOC10
#define MTR2_VV_ADCRESLT        (MTR2_VV_ADCRES_BASE + ADC_O_RESULT11)  // ADCC-A10/C10*-SOC11
#define MTR2_VW_ADCRESLT        (MTR2_VW_ADCRES_BASE + ADC_O_RESULT12)  // ADCC-A15/C7* -SOC12
#if defined(PFC_DISABLE)
#define MTR2_VDC_ADCRESLT       MTR1_VDC_ADCRESLT                       // ADCA-A7/C3*  -SOC6
#else
#define MTR2_VDC_ADCRESLT       PFC_VDC_ADCRESLT                        // ADCA-A4*/C14
#endif  // !PFC_DISABLE

//------------------------------------------------------------------------------
// Interrupt
#define MTR2_ADC_INT_BASE       ADCC_BASE               // ADCC-C7  -SOC12
#define MTR2_ADC_INT_NUM        ADC_INT_NUMBER3         // ADCC_INT3-SOC12
#define MTR2_ADC_INT_SOC        ADC_SOC_NUMBER12        // ADCC_INT3-SOC12
#define MTR2_PIE_INT_NUM        INT_ADCC3               // ADCC_INT3-SOC12
#define MTR2_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCC_INT3-CPU_INT10
#define MTR2_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCC_INT3-CPU_INT10

#define MTR2_PIE_O_IER           PIE_O_IER10             // ADCC_INT3-CPU_INT10
#define MTR2_PIE_IER_INT         PIE_IER10_INTX11        // ADCC_INT3-PIE_INT11
//------------------------------------------------------------------------------
// CMPSS
#define MTR2_IU_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // C6*, CMPSS3-HP
#define MTR2_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // C6*, CMPSS3-LP, N/A

#define MTR2_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_4    // A9/C8*, CMPSS4-HP
#define MTR2_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_4    // A9/C8*, CMPSS4-LP

#define MTR2_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // A5/C2*, CMPSS3-HP, N/A
#define MTR2_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // A5/C2*, CMPSS3-LP

#define MTR2_IU_CMPHP_MUX       0       // C6*, CMPSS3-HP
#define MTR2_IU_CMPLP_MUX       0       // C6*, CMPSS3-LP

#define MTR2_IV_CMPHP_MUX       0       // A9/C8*, CMPSS4-HP
#define MTR2_IV_CMPLP_MUX       0       // A9/C8*, CMPSS4-LP

#define MTR2_IW_CMPHP_MUX       1       // A5/C2*, CMPSS3-HP
#define MTR2_IW_CMPLP_MUX       1       // A5/C2*, CMPSS3-LP

#define MTR2_CMPSS_DACH_VALUE   (2048 + 1024 + 512)
#define MTR2_CMPSS_DACL_VALUE   (2048 - 1024 - 512)

//------------------------------------------------------------------------------
// XBAR-EPWM
#define MTR2_XBAR_TRIP_ADDRL    XBAR_O_TRIP8MUX0TO15CFG
#define MTR2_XBAR_TRIP_ADDRH    XBAR_O_TRIP8MUX16TO31CFG

#define MTR2_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX04_CMPSS3_CTRIPH       // CMPSS3-HP
#define MTR2_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L  // CMPSS4-HP&LP
#define MTR2_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX05_CMPSS3_CTRIPL       // CMPSS3-LP

#define MTR2_IU_XBAR_MUX        XBAR_MUX04                  // CMPSS3-HP
#define MTR2_IV_XBAR_MUX        XBAR_MUX06                  // CMPSS4-HP&LP
#define MTR2_IW_XBAR_MUX        XBAR_MUX05                  // CMPSS3-LP

#define MTR2_XBAR_INPUT         XBAR_INPUT2
#define MTR2_TZ_OSHT            EPWM_TZ_SIGNAL_OSHT2
#define MTR2_XBAR_TRIP          XBAR_TRIP8
#define MTR2_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN8


//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR2_PWM_DBFED_CNT      225         // 2.25us

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR2_PWM_DBRED_CNT      245         // 2.45us

//---HVMTRPFC_REV1P1----

//=============================================================================
#elif defined(BSXL8323RH_REVB)

#define TEST_SWITCH_GPIO        5

//! \brief Power relay for inrush current
#define ACPOWER_RELAY_GPIO      23

//! \brief Power relay for Four-Way Relay
#define FOURWAY_RELAY_GPIO      23

//----- PFC  -------------------------------------------------------------------
#define PFC_PWM_BASE            EPWM6_BASE      // GPIO10/11

#define PFC_CMPSS_IAC_BASE      CMPSSLITE4_BASE
#define PFC_CMPSS_VDC_BASE      CMPSSLITE4_BASE
#define PFC_CMPSS_VAC_BASE      CMPSSLITE4_BASE

#define PFC_XBAROUTPUT          XBAR_OUTPUT3        // N/A

#define PFC_XBAROUTPUT_CFGL     XBAR_O_OUTPUT3MUX0TO15CFG
#define PFC_XBAROUTPUT_CFGH     XBAR_O_OUTPUT3MUX16TO31CFG

#define PFC_EPWM_SYSN_O_TIME    2
#define MTR_EPWM_SYSN_O_TIME    2

// ADC Channel, Trigger, SOC and Interrupt Configure
#define PFC_ADC_TRIGGER_IAC      ADC_TRIGGER_CPU1_TINT1  // CPU_TINT1
#define PFC_ADC_TRIGGER_VIS1     ADC_TRIGGER_EPWM6_SOCA  // EPWM6_SOCA @ Zero
#define PFC_ADC_TRIGGER_VIS2     ADC_TRIGGER_EPWM6_SOCB  // EPWM6_SOCA @ Period

#define PFC_I_ADC_SAMPLE_WINDOW     15                  // 15 sample cycle
#define PFC_V_ADC_SAMPLE_WINDOW     20                  // 20 sample cycle

#define PFC_IAC_ADC_BASE        ADCC_BASE               // ADCC-A12/C1*, N/A
#define PFC_VAC_ADC_BASE        ADCC_BASE               // ADCC-A0/C15*, N/A
#define PFC_VDC_ADC_BASE        ADCC_BASE               // ADCC-C6*

#define PFC_IAC_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A12/C1*, N/A
#define PFC_VAC_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-A0/C15*, N/A
#define PFC_VDC_ADCRES_BASE     ADCCRESULT_BASE         // ADCC-C6*

#define PFC_IAC_ADC_CH_NUM      ADC_CH_ADCIN1           // ADCC-A12/C1*, N/A
#define PFC_VAC_ADC_CH_NUM      ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A
#define PFC_VDC_ADC_CH_NUM      ADC_CH_ADCIN6           // ADCC-C6*

#define PFC_IAC1_ADC_SOC_NUM    ADC_SOC_NUMBER0         // ADCC-A12/C1*-SOC0
#define PFC_VAC1_ADC_SOC_NUM    ADC_SOC_NUMBER1         // ADCC-A0/C15*-SOC1
#define PFC_VDC1_ADC_SOC_NUM    ADC_SOC_NUMBER2         // ADCC-C6*    -SOC2

#define PFC_IAC2_ADC_SOC_NUM    ADC_SOC_NUMBER3         // ADCC-A12/C1*-SOC3
#define PFC_VAC2_ADC_SOC_NUM    ADC_SOC_NUMBER4         // ADCC-A0/C15*-SOC4
#define PFC_VDC2_ADC_SOC_NUM    ADC_SOC_NUMBER5         // ADCC-C6*    -SOC5

#define PFC_IAC1_ADC_PPB_NUM    ADC_PPB_NUMBER1         // ADCC-A12/C1* -SOC0-PPB1
#define PFC_VAC1_ADC_PPB_NUM    ADC_PPB_NUMBER2         // ADCC-A0/C15* -SOC1-PPB2

#define PFC_IAC2_ADC_PPB_NUM    ADC_PPB_NUMBER3         // ADCC-A12/C1* -SOC3-PPB3
#define PFC_VAC2_ADC_PPB_NUM    ADC_PPB_NUMBER4         // ADCC-A0/C15* -SOC4-PPB4

#define PFC_IAC_ADC_SOC_NUM     PFC_IAC1_ADC_SOC_NUM    // ADCC-A12/C1* -SOC0-PPB1
#define PFC_VAC_ADC_SOC_NUM     PFC_VAC1_ADC_SOC_NUM    // ADCC-A0/C15* -SOC1-PPB2
#define PFC_VDC_ADC_SOC_NUM     PFC_VDC1_ADC_SOC_NUM    // ADCC-C6*     -SOC2

#define PFC_IAC_ADC_PPB_NUM     PFC_IAC1_ADC_PPB_NUM    // ADCC-A12/C1* -SOC0-PPB1
#define PFC_VAC_ADC_PPB_NUM     PFC_VAC1_ADC_PPB_NUM    // ADCC-A0/C15* -SOC1-PPB2

#define PFC_IAC_ADCRES_ADDR     (PFC_IAC_ADCRES_BASE + \
                                 ADC_PPBxRESULT_OFFSET_BASE + \
                                 PFC_IAC_ADC_PPB_NUM * 2U)
// only for datalog and PWMDAC
#define PFC_IAC1_ADCRESLT       (PFC_IAC_ADCRES_BASE + ADC_O_RESULT0)   // ADCC-A12/C1*-SOC0
#define PFC_VAC1_ADCRESLT       (PFC_VAC_ADCRES_BASE + ADC_O_RESULT1)   // ADCC-A0/C15*-SOC1
#define PFC_VDC1_ADCRESLT       (PFC_VDC_ADCRES_BASE + ADC_O_RESULT2)   // ADCC-C6*    -SOC2

#define PFC_IAC2_ADCRESLT       (PFC_IAC_ADCRES_BASE + ADC_O_RESULT3)   // ADCC-A12/C1*-SOC3
#define PFC_VAC2_ADCRESLT       (PFC_VAC_ADCRES_BASE + ADC_O_RESULT4)   // ADCC-A0/C15*-SOC4
#define PFC_VDC2_ADCRESLT       (PFC_VDC_ADCRES_BASE + ADC_O_RESULT5)   // ADCC-C6*    -SOC5

#define PFC_IAC_ADCRESLT        PFC_IAC1_ADCRESLT                       // ADCC-A9*/C8  -SOC0
#define PFC_VAC_ADCRESLT        PFC_VAC1_ADCRESLT                       // ADCC-A10*/C10-SOC1
#define PFC_VDC_ADCRESLT        PFC_VDC1_ADCRESLT                       // ADCC-A4*/C14 -SOC2
//------------------------------------------------------------------------------
// Interrupt
#define PFC_PWM_INT_BASE        PFC_PWM_BASE            // EPWM6

#define PFC_ADC_INT_BASE        ADCC_BASE               // ADCC-C6  -SOC2
#define PFC_ADC_INT_NUM         ADC_INT_NUMBER2         // ADCC_INT2-SOC2
#define PFC_ADC_INT_SOC         ADC_SOC_NUMBER2         // ADCC_INT2-SOC2
#define PFC_PIE_INT_NUM         INT_ADCC2               // ADCC_INT2-SOC2
#define PFC_CPU_INT_NUM         INTERRUPT_CPU_INT10     // ADCC_INT2-CPU_INT10
#define PFC_INT_ACK_GROUP       INTERRUPT_ACK_GROUP10   // ADCC_INT2-CPU_INT10

#define PFC_PIE_O_IER           PIE_O_IER10             // ADCA_INT2-CPU_INT10
#define PFC_PIE_IER_INT         PIE_IER10_INTX2         // ADCA_INT2-PIE_INT10

#define PFC_DMA_ADC_INT_BASE    ADCC_BASE               // ADCC-C6 -SOC2
#define PFC_DMA_ADC_INT_NUM     ADC_INT_NUMBER1         // ADCC_INT1-SOC2
#define PFC_DMA_ADC_INT_SOC     ADC_SOC_NUMBER2         // ADCC_INT1-SOC2
#define PFC_DMA_IAC_TRIGGER     DMA_TRIGGER_ADCC1       // ADCC-INT1

//------------------------------------------------------------------------------
// CMPSS
#define PFC_IAC_CMPHP_SEL        ASYSCTL_CMPHPMUX_SELECT_4    // A12/C1*, CMPSS4-HP
#define PFC_IAC_CMPHP_MUX        2                            // A12/C1*, CMPSS4-HP

#define PFC_VDC_CMPHP_SEL        ASYSCTL_CMPHPMUX_SELECT_3    // C6*, CMPSS3-HP
#define PFC_VDC_CMPHP_MUX        0                            // C6*, CMPSS3-HP


#define PFC_CMPSS_OFFSET_VALUE  (uint16_t)(USER_PFC_IAC_OFFSET * USER_PFC_ADC_INV_SF)

#define PFC_CMPSS_DACH_VALUE     1024
#define PFC_CMPSS_DACL_VALUE     2048

//-----------------------------------------------------------------------------
// XBAR-EPWM
#define PFC_XBAR_TRIP_ADDRL     XBAR_O_TRIP4MUX0TO15CFG
#define PFC_XBAR_TRIP_ADDRH     XBAR_O_TRIP4MUX16TO31CFG

#define PFC_IAC_XBAR_EPWM_MUX   XBAR_EPWM_MUX06_CMPSS4_CTRIPH   // A12/C1*, CMPSS4-HP
#define PFC_IAC_XBAR_MUX        XBAR_MUX06                      // A12/C1*, CMPSS4-HP

#define PFC_VDC_XBAR_EPWM_MUX   XBAR_EPWM_MUX04_CMPSS3_CTRIPH   // A12/C1*, CMPSS3-HP
#define PFC_VDC_XBAR_MUX        XBAR_MUX04                      // A12/C1*, CMPSS3-HP

#define PFC_XBAR_INPUT          XBAR_INPUT3
#define PFC_TZ_SIGNAL           EPWM_TZ_SIGNAL_OSHT3
#define PFC_XBAR_TRIP           XBAR_TRIP4
#define PFC_DCTRIPIN            EPWM_DC_COMBINATIONAL_TRIPIN4


//------------------------------------------------------------------------------
//! \ Motor 1
#define MTR1_PWM_U_BASE         EPWM1_BASE      // GPIO0/1
#define MTR1_PWM_V_BASE         EPWM2_BASE      // GPIO2/3
#define MTR1_PWM_W_BASE         EPWM3_BASE      // GPIO4/15

#define MTR1_CMPSS_IDC_BASE     CMPSSLITE3_BASE

#define MTR1_CMPSS_U_BASE       CMPSS1_BASE
#define MTR1_CMPSS_V_BASE       CMPSSLITE3_BASE
#define MTR1_CMPSS_W_BASE       CMPSS1_BASE


//! \brief Defines the gpio for enabling Power Module
#define MTR1_GATE_EN_GPIO       29

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR1_PM_nFAULT_GPIO     34

//! \brief Defines the gpio for enabling calibration
#define MTR1_DRV_CAL_GPIO       27

//------------------------------------------------------------------------------
// ADC
#define MTR1_ADC_TRIGGER_SOC     ADC_TRIGGER_EPWM1_SOCA  // EPWM1_SOCA

// Single shunt (need to connect NU, NV and NW using jumper wires)
#define MTR1_IDC_SAMPLE_WINDOW  9                       // 10 sample cycles

#define MTR1_IDC1_TRIGGER_SOC    ADC_TRIGGER_EPWM2_SOCA  // EPWM2_SOCA for single shunt
#define MTR1_IDC2_TRIGGER_SOC    ADC_TRIGGER_EPWM2_SOCB  // EPWM2_SOCB for single shunt
#define MTR1_IDC3_TRIGGER_SOC    ADC_TRIGGER_EPWM3_SOCA  // EPWM3_SOCA for single shunt
#define MTR1_IDC4_TRIGGER_SOC    ADC_TRIGGER_EPWM3_SOCB  // EPWM3_SOCB for single shunt

#define MTR1_IDC1_ADC_BASE      ADCA_BASE               // ADCA-A14*/C4/CMP3-SOC0
#define MTR1_IDC2_ADC_BASE      ADCA_BASE               // ADCA-A14*/C4/CMP3-SOC1
#define MTR1_IDC3_ADC_BASE      ADCA_BASE               // ADCA-A14*/C4/CMP3-SOC2
#define MTR1_IDC4_ADC_BASE      ADCA_BASE               // ADCA-A14*/C4/CMP3-SOC3

#define MTR1_IDC1_ADCRES_BASE   ADCARESULT_BASE         // ADCC-A14*/C4
#define MTR1_IDC2_ADCRES_BASE   ADCARESULT_BASE         // ADCC-A14*/C4
#define MTR1_IDC3_ADCRES_BASE   ADCARESULT_BASE         // ADCC-A14*/C4
#define MTR1_IDC4_ADCRES_BASE   ADCARESULT_BASE         // ADCC-A14*/C4

#define MTR1_IDC1_ADC_CH_NUM    ADC_CH_ADCIN14          // ADCC-A14*/C4
#define MTR1_IDC2_ADC_CH_NUM    ADC_CH_ADCIN14          // ADCC-A14*/C4
#define MTR1_IDC3_ADC_CH_NUM    ADC_CH_ADCIN14          // ADCC-A14*/C4
#define MTR1_IDC4_ADC_CH_NUM    ADC_CH_ADCIN14          // ADCC-A14*/C4

#define MTR1_IDC1_ADC_SOC_NUM   ADC_SOC_NUMBER0         // ADCA-A14*/C4-SOC0
#define MTR1_IDC2_ADC_SOC_NUM   ADC_SOC_NUMBER1         // ADCA-A14*/C4-SOC1
#define MTR1_IDC3_ADC_SOC_NUM   ADC_SOC_NUMBER2         // ADCA-A14*/C4-SOC2
#define MTR1_IDC4_ADC_SOC_NUM   ADC_SOC_NUMBER3         // ADCA-A14*/C4-SOC3

#define MTR1_IDC1_ADC_PPB_NUM   ADC_PPB_NUMBER1         // ADCA-A14*/C4-SOC0
#define MTR1_IDC2_ADC_PPB_NUM   ADC_PPB_NUMBER2         // ADCA-A14*/C4-SOC1
#define MTR1_IDC3_ADC_PPB_NUM   ADC_PPB_NUMBER3         // ADCA-A14*/C4-SOC2
#define MTR1_IDC4_ADC_PPB_NUM   ADC_PPB_NUMBER4         // ADCA-A14*/C4-SOC3

#define MTR1_IDC1_ADCRESLT      (MTR1_IDC1_ADCRES_BASE + ADC_O_RESULT0) // ADCA-A14*/C4-SOC0
#define MTR1_IDC2_ADCRESLT      (MTR1_IDC2_ADCRES_BASE + ADC_O_RESULT1) // ADCA-A14*/C4-SOC1
#define MTR1_IDC3_ADCRESLT      (MTR1_IDC3_ADCRES_BASE + ADC_O_RESULT2) // ADCA-A14*/C4-SOC2
#define MTR1_IDC4_ADCRESLT      (MTR1_IDC4_ADCRES_BASE + ADC_O_RESULT3) // ADCA-A14*/C4-SOC3

#define MTR1_IDC1_ADCRES_ADDR   (MTR1_IDC1_ADCRES_BASE + \
                                 ADC_PPBxRESULT_OFFSET_BASE + \
                                 MTR1_IDC1_ADC_PPB_NUM * 2U)

// Three shunt
#define MTR1_I_ADC_SAMPLE_WINDOW    9                   // 10 sample cycles
#define MTR1_V_ADC_SAMPLE_WINDOW    20                  // 20 sample cycles

#define MTR1_IU_ADC_BASE        ADCA_BASE               // ADCA-A11*/C0
#define MTR1_IV_ADC_BASE        ADCA_BASE               // ADCA-A14*/C4
#define MTR1_IW_ADC_BASE        ADCA_BASE               // ADCA-A15*/C7
#define MTR1_VU_ADC_BASE        ADCA_BASE               // ADCA-A6*
#define MTR1_VV_ADC_BASE        ADCA_BASE               // ADCA-A3*/C5
#define MTR1_VW_ADC_BASE        ADCA_BASE               // ADCA-A2*/C9
#define MTR1_VDC_ADC_BASE       PFC_VDC_ADC_BASE        // ADCC-C6*

#define MTR1_IU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A11*/C0
#define MTR1_IV_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A14*/C4
#define MTR1_IW_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A15*/C7
#define MTR1_VU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A6*
#define MTR1_VV_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A3*/C5
#define MTR1_VW_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A2*/C9
#define MTR1_VDC_ADCRES_BASE    PFC_VDC_ADCRES_BASE     // ADCC-A1*//C6

#define MTR1_IU_ADC_CH_NUM      ADC_CH_ADCIN11          // ADCA-A11*/C0
#define MTR1_IV_ADC_CH_NUM      ADC_CH_ADCIN14          // ADCC-A14*/C4
#define MTR1_IW_ADC_CH_NUM      ADC_CH_ADCIN15          // ADCC-A15*/C7
#define MTR1_VU_ADC_CH_NUM      ADC_CH_ADCIN6           // ADCA-A6*
#define MTR1_VV_ADC_CH_NUM      ADC_CH_ADCIN3           // ADCA-A3*/C5
#define MTR1_VW_ADC_CH_NUM      ADC_CH_ADCIN2           // ADCA-A2*/C9
#define MTR1_VDC_ADC_CH_NUM     PFC_VDC_ADC_CH_NUM      // ADCC-C6*    -SOC2

#define MTR1_IU_ADC_SOC_NUM     ADC_SOC_NUMBER2         // ADCA-A11*/C0-SOC2
#define MTR1_IV_ADC_SOC_NUM     ADC_SOC_NUMBER3         // ADCA-A14*/C4-SOC3
#define MTR1_IW_ADC_SOC_NUM     ADC_SOC_NUMBER4         // ADCA-A15*/C7-SOC4
#define MTR1_VU_ADC_SOC_NUM     ADC_SOC_NUMBER5         // ADCA-A6*    -SOC5
#define MTR1_VV_ADC_SOC_NUM     ADC_SOC_NUMBER6         // ADCA-A3*/C5 -SOC6
#define MTR1_VW_ADC_SOC_NUM     ADC_SOC_NUMBER7         // ADCA-A2*/C9 -SOC7
#define MTR1_VDC_ADC_SOC_NUM    PFC_VDC_ADC_SOC_NUM     // ADCC-C6*    -SOC2

#define MTR1_IU_ADCRESLT        (MTR1_IU_ADCRES_BASE + ADC_O_RESULT2)   // ADCA-A11*/C0-SOC2
#define MTR1_IV_ADCRESLT        (MTR1_IV_ADCRES_BASE + ADC_O_RESULT3)   // ADCA-A14*/C4-SOC3
#define MTR1_IW_ADCRESLT        (MTR1_IW_ADCRES_BASE + ADC_O_RESULT4)   // ADCA-A15*/C7-SOC4
#define MTR1_VU_ADCRESLT        (MTR1_VU_ADCRES_BASE + ADC_O_RESULT5)   // ADCA-A6*    -SOC5
#define MTR1_VV_ADCRESLT        (MTR1_VV_ADCRES_BASE + ADC_O_RESULT6)   // ADCA-A3*/C5 -SOC6
#define MTR1_VW_ADCRESLT        (MTR1_VW_ADCRES_BASE + ADC_O_RESULT7)   // ADCA-A2*/C9 -SOC7
#define MTR1_VDC_ADCRESLT       PFC_VDC_ADCRESLT                        // ADCA-A1*//C6

//------------------------------------------------------------------------------
// interrupt
#define MTR1_PWM_INT_BASE       MTR1_PWM_U_BASE         // EPWM1

#if defined(MOTOR1_FAST)        // Single/Three-shunt & FAST
#define MTR1_ADC_INT_BASE       ADCA_BASE               // ADCA-A2*/C9-SOC7
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER2         // ADCA_INT2  -SOC7
#define MTR1_ADC_INT_SOC        ADC_SOC_NUMBER7         // ADCA_INT2  -SOC7

#define MTR1_PIE_INT_NUM        INT_ADCA2               // ADCA_INT2-SOC7
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT2-CPU_INT10
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT2-CPU_INT10

#define MTR1_PIE_O_IER          PIE_O_IER10             // ADCA_INT2-CPU_INT10
#define MTR1_PIE_IER_INT        PIE_IER10_INTX2         // ADCA_INT2-PIE_INT2
#elif defined(MOTOR1_DCLINKSS) && defined(MOTOR1_ESMO)  // Single shunt & eSMO
#define MTR1_ADC_INT_BASE       ADCA_BASE               // ADCA-A3  -SOC9
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER2         // ADCA_INT2-SOC9
#define MTR1_ADC_INT_SOC        ADC_SOC_NUMBER9         // ADCA_INT2-SOC9

#define MTR1_PIE_INT_NUM        INT_ADCA2               // ADCA_INT2-SOC9
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT2-CPU_INT10
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT2-CPU_INT10

#define MTR1_PIE_O_IER          PIE_O_IER10             // ADCA_INT2-CPU_INT10
#define MTR1_PIE_IER_INT        PIE_IER10_INTX2         // ADCA_INT2-PIE_INT2
#elif defined(MOTOR1_ESMO)  // Three-Shunt & eSMO
#define MTR1_ADC_INT_BASE       ADCA_BASE               // ADCA-A15 -SOC4
#define MTR1_ADC_INT_NUM        ADC_INT_NUMBER2         // ADCA_INT2-SOC4
#define MTR1_ADC_INT_SOC        ADC_SOC_NUMBER4         // ADCA_INT2-SOC4

#define MTR1_PIE_INT_NUM        INT_ADCA2               // ADCA_INT2-SOC4
#define MTR1_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT2-CPU_INT10
#define MTR1_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT2-CPU_INT10

#define MTR1_PIE_O_IER          PIE_O_IER10             // ADCA_INT2-CPU_INT10
#define MTR1_PIE_IER_INT        PIE_IER10_INTX2         // ADCA_INT2-PIE_INT2
#else  // !(MOTOR1_FAST | MOTOR1_ESMO)
#error Not select a right estimator or sampling mode
#endif  // !(MOTOR1_FAST | MOTOR1_ESMO)

//------------------------------------------------------------------------------
// CMPSS
#define MTR1_IDC_CMPLP_SEL      ASYSCTL_CMPLPMUX_SELECT_3    // CMPSS3-A14*/C4, N/A

#define MTR1_IDC_CMPLP_MUX      4                            // CMPSS2-A14*/C4, N/A

#define MTR1_IU_CMPHP_SEL       ASYSCTL_CMPLPMUX_SELECT_1    // CMPSS1-A11*/C0
#define MTR1_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_1    // CMPSS1-A11*/C0, N/A

#define MTR1_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_3    // CMPSS3-A14*/C4, N/A
#define MTR1_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_3    // CMPSS3-A14*/C4

#define MTR1_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_1    // CMPSS1-A15*/C7, N/A
#define MTR1_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_1    // CMPSS1-A15*/C7

#define MTR1_IU_CMPHP_MUX       1                            // CMPSS1-A11*/C0
#define MTR1_IU_CMPLP_MUX       1                            // CMPSS1-A11*/C0, N/A

#define MTR1_IV_CMPHP_MUX       4                            // CMPSS2-A14*/C4, N/A
#define MTR1_IV_CMPLP_MUX       4                            // CMPSS2-A14*/C4

#define MTR1_IW_CMPHP_MUX       3                            // CMPSS3-A15*/C7, N/A
#define MTR1_IW_CMPLP_MUX       3                            // CMPSS3-A15*/C7

#define MTR1_CMPSS_DACH_VALUE   (2048 + 1024 + 512)
#define MTR1_CMPSS_DACL_VALUE   (2048 - 1024 - 512)

//------------------------------------------------------------------------------
// XBAR-EPWM
#define MTR1_XBAR_TRIP_ADDRL    XBAR_O_TRIP7MUX0TO15CFG
#define MTR1_XBAR_TRIP_ADDRH    XBAR_O_TRIP7MUX16TO31CFG

#define MTR1_IDC_XBAR_EPWM_MUX  XBAR_EPWM_MUX05_CMPSS3_CTRIPL       // CMPSS3-LP
#define MTR1_IDC_XBAR_MUX       XBAR_MUX05                          // CMPSS3-LP

#define MTR1_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX00_CMPSS1_CTRIPH       // CMPSS1-HP
#define MTR1_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX05_CMPSS3_CTRIPL       // CMPSS3-LP
#define MTR1_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX01_CMPSS1_CTRIPL       // CMPSS1-LP

#define MTR1_IU_XBAR_MUX        XBAR_MUX00                          // CMPSS1-HP
#define MTR1_IV_XBAR_MUX        XBAR_MUX05                          // CMPSS3-LP
#define MTR1_IW_XBAR_MUX        XBAR_MUX01                          // CMPSS1-LP

#define MTR1_XBAR_INPUT         XBAR_INPUT1
#define MTR1_TZ_OSHT            EPWM_TZ_SIGNAL_OSHT1

#define MTR1_XBAR_TRIP          XBAR_TRIP7
#define MTR1_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN7


//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR1_PWM_DBFED_CNT      5           // 50ns

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR1_PWM_DBRED_CNT      5           // 50ns

//------------------------------------------------------------------------------
//! \Motor 2
#define MTR2_PWM_U_BASE         EPWM7_BASE      // GPIO12/13
#define MTR2_PWM_V_BASE         EPWM4_BASE      // GPIO6/7
#define MTR2_PWM_W_BASE         EPWM5_BASE      // GPIO16/17

#define MTR2_CMPSS_IDC_BASE     CMPSSLITE2_BASE

#define MTR2_CMPSS_U_BASE       CMPSSLITE2_BASE
#define MTR2_CMPSS_V_BASE       CMPSSLITE4_BASE
#define MTR2_CMPSS_W_BASE       CMPSSLITE2_BASE


//! \brief Defines the gpio for enabling Power Module
#define MTR2_GATE_EN_GPIO       24                   // N/A

//! \brief Defines the gpio for the nFAULT of Power Module
#define MTR2_PM_nFAULT_GPIO     41

//! \brief Defines the gpio for the SPI_CS of DRV device
//!
#define MTR2_DRV_SPI_CS_GPIO    32

//! \brief Defines the gpio for enabling calibration
#define MTR2_DRV_CAL_GPIO       46

#define MTR2_SPI_BASE           SPIB_BASE           // N/A
#define MTR2_QEP_BASE           EQEP1_BASE          // N/A

//------------------------------------------------------------------------------
// ADC
#define MTR2_ADC_TRIGGER_SOC     ADC_TRIGGER_EPWM7_SOCA  // EPWM7_SOCA

#define MTR2_IDC1_TRIGGER_SOC    ADC_TRIGGER_EPWM4_SOCA  // EPWM4_SOCA for single shunt
#define MTR2_IDC2_TRIGGER_SOC    ADC_TRIGGER_EPWM4_SOCB  // EPWM4_SOCB for single shunt
#define MTR2_IDC3_TRIGGER_SOC    ADC_TRIGGER_EPWM5_SOCA  // EPWM4_SOCA for single shunt
#define MTR2_IDC4_TRIGGER_SOC    ADC_TRIGGER_EPWM5_SOCB  // EPWM4_SOCB for single shunt

#define MTR2_I_ADC_SAMPLE_WINDOW    9                   // 10 sample cycles
#define MTR2_V_ADC_SAMPLE_WINDOW    20                  // 20 sample cycles

// Single shunt
#define MTR2_IDC1_ADC_BASE      ADCA_BASE               // ADCA-A9*/C8/CMP2-SOC8
#define MTR2_IDC2_ADC_BASE      ADCA_BASE               // ADCA-A9*/C8/CMP2-SOC9
#define MTR2_IDC3_ADC_BASE      ADCA_BASE               // ADCA-A9*/C8/CMP2-SOC10
#define MTR2_IDC4_ADC_BASE      ADCA_BASE               // ADCA-A9*/C8/CMP2-SOC11

#define MTR2_IDC1_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A9*/C8
#define MTR2_IDC2_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A9*/C8
#define MTR2_IDC3_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A9*/C8
#define MTR2_IDC4_ADCRES_BASE   ADCARESULT_BASE         // ADCA-A9*/C8

#define MTR2_IDC1_ADC_CH_NUM    ADC_CH_ADCIN9           // ADCA-A9*/C8
#define MTR2_IDC2_ADC_CH_NUM    ADC_CH_ADCIN9           // ADCA-A9*/C8
#define MTR2_IDC3_ADC_CH_NUM    ADC_CH_ADCIN9           // ADCA-A9*/C8
#define MTR2_IDC4_ADC_CH_NUM    ADC_CH_ADCIN9           // ADCA-A9*/C8

#define MTR2_IDC1_ADC_SOC_NUM   ADC_SOC_NUMBER8         // ADCA-A9*/C8 -SOC8
#define MTR2_IDC2_ADC_SOC_NUM   ADC_SOC_NUMBER9         // ADCA-A9*/C8 -SOC9
#define MTR2_IDC3_ADC_SOC_NUM   ADC_SOC_NUMBER10        // ADCA-A9*/C8 -SOC10
#define MTR2_IDC4_ADC_SOC_NUM   ADC_SOC_NUMBER11        // ADCA-A9*/C8 -SOC11

#define MTR2_IDC1_ADC_PPB_NUM   ADC_PPB_NUMBER1         // ADCA-A9*/C8  -SOC8
#define MTR2_IDC2_ADC_PPB_NUM   ADC_PPB_NUMBER2         // ADCA-A9*/C8  -SOC9
#define MTR2_IDC3_ADC_PPB_NUM   ADC_PPB_NUMBER3         // ADCA-A9*/C8  -SOC10
#define MTR2_IDC4_ADC_PPB_NUM   ADC_PPB_NUMBER4         // ADCA-A9*/C8  -SOC11

#define MTR2_IDC1_ADCRESLT      (MTR2_IDC1_ADCRES_BASE + ADC_O_RESULT8)  // ADCA-A9*/C8  -SOC8
#define MTR2_IDC2_ADCRESLT      (MTR2_IDC2_ADCRES_BASE + ADC_O_RESULT9)  // ADCA-A9*/C8  -SOC9
#define MTR2_IDC3_ADCRESLT      (MTR2_IDC3_ADCRES_BASE + ADC_O_RESULT10) // ADCA-A9*/C8  -SOC10
#define MTR2_IDC4_ADCRESLT      (MTR2_IDC4_ADCRES_BASE + ADC_O_RESULT11) // ADCA-A9*/C8  -SOC11

#define MTR2_IDC1_ADCRES_ADDR   (MTR2_IDC1_ADCRES_BASE + \
                                 ADC_PPBxRESULT_OFFSET_BASE + \
                                 MTR2_IDC1_ADC_PPB_NUM * 2U)

// Three shunt
#define MTR2_IU_ADC_BASE        ADCA_BASE               // ADCA-A10*/C10
#define MTR2_IV_ADC_BASE        ADCA_BASE               // ADCA-A9*/C8
#define MTR2_IW_ADC_BASE        ADCA_BASE               // ADCA-A4*/C14
#define MTR2_VU_ADC_BASE        ADCA_BASE               // ADCA-A5*/C2
#define MTR2_VV_ADC_BASE        ADCA_BASE               // ADCA-A7*/C3
#define MTR2_VW_ADC_BASE        ADCA_BASE               // ADCA-A8*/C11
#define MTR2_VDC_ADC_BASE       PFC_VDC_ADC_BASE        // ADCC-C6*    -SOC2

#define MTR2_IU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A10*/C10
#define MTR2_IV_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A9*/C8
#define MTR2_IW_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A4*/C14
#define MTR2_VU_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A5*/C2
#define MTR2_VV_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A7*/C3
#define MTR2_VW_ADCRES_BASE     ADCARESULT_BASE         // ADCA-A8*/C11
#define MTR2_VDC_ADCRES_BASE    PFC_VDC_ADCRES_BASE     // ADCC-C6*    -SOC2

#define MTR2_IU_ADC_CH_NUM      ADC_CH_ADCIN10          // ADCA-A10*/C10
#define MTR2_IV_ADC_CH_NUM      ADC_CH_ADCIN9           // ADCA-A9*/C8
#define MTR2_IW_ADC_CH_NUM      ADC_CH_ADCIN4           // ADCA-A4*/C14
#define MTR2_VU_ADC_CH_NUM      ADC_CH_ADCIN5           // ADCA-A5*/C2
#define MTR2_VV_ADC_CH_NUM      ADC_CH_ADCIN7           // ADCA-A7*/C3
#define MTR2_VW_ADC_CH_NUM      ADC_CH_ADCIN8           // ADCA-A8*/C11
#define MTR2_VDC_ADC_CH_NUM     PFC_VDC_ADC_CH_NUM      // ADCC-C6*    -SOC2

#define MTR2_IU_ADC_SOC_NUM     ADC_SOC_NUMBER10        // ADCA-A10*/C10-SOC10
#define MTR2_IV_ADC_SOC_NUM     ADC_SOC_NUMBER11        // ADCA-A9*/C8  -SOC11
#define MTR2_IW_ADC_SOC_NUM     ADC_SOC_NUMBER12        // ADCA-A4*/C14 -SOC12
#define MTR2_VU_ADC_SOC_NUM     ADC_SOC_NUMBER13        // ADCA-A5*/C2  -SOC13
#define MTR2_VV_ADC_SOC_NUM     ADC_SOC_NUMBER14        // ADCA-A7*/C3  -SOC14
#define MTR2_VW_ADC_SOC_NUM     ADC_SOC_NUMBER15        // ADCA-A8*/C11 -SOC15
#define MTR2_VDC_ADC_SOC_NUM    PFC_VDC_ADC_SOC_NUM     // ADCC-C6*      -SOC2

#define MTR2_IU_ADCRESLT        (MTR2_IU_ADCRES_BASE + ADC_O_RESULT10)  // ADCA-A10*/C10-SOC10
#define MTR2_IV_ADCRESLT        (MTR2_IV_ADCRES_BASE + ADC_O_RESULT11)  // ADCA-A9*/C8  -SOC11
#define MTR2_IW_ADCRESLT        (MTR2_IW_ADCRES_BASE + ADC_O_RESULT12)  // ADCA-A4*/C14 -SOC12
#define MTR2_VU_ADCRESLT        (MTR2_VU_ADCRES_BASE + ADC_O_RESULT13)  // ADCA-A5*/C2  -SOC13
#define MTR2_VV_ADCRESLT        (MTR2_VV_ADCRES_BASE + ADC_O_RESULT14)  // ADCA-A7*/C3  -SOC14
#define MTR2_VW_ADCRESLT        (MTR2_VW_ADCRES_BASE + ADC_O_RESULT15)  // ADCA-A8*/C11 -SOC15
#define MTR2_VDC_ADCRESLT       PFC_VDC_ADCRESLT                        // ADCA-A1*//C6

//------------------------------------------------------------------------------
// Interrupt
#define MTR2_PWM_INT_BASE       MTR2_PWM_U_BASE         // EPWM7

#if defined(MOTOR2_FAST)  // Single/Three-shunt & FAST
#define MTR2_ADC_INT_BASE       ADCA_BASE               // ADCA-A8  -SOC15
#define MTR2_ADC_INT_NUM        ADC_INT_NUMBER3         // ADCA_INT3-SOC15
#define MTR2_ADC_INT_SOC        ADC_SOC_NUMBER15        // ADCA_INT3-SOC15

#define MTR2_PIE_INT_NUM        INT_ADCA3               // ADCA_INT3-SOC15
#define MTR2_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT3-CPU_INT10
#define MTR2_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT3-CPU_INT10

#define MTR2_PIE_O_IER          PIE_O_IER10             // ADCA_INT3-CPU_INT10
#define MTR2_PIE_IER_INT        PIE_IER10_INTX3        // ADCA_INT3-PIE_INT3
#elif defined(MOTOR2_ESMO)  // Three-shunt & eSMO
#define MTR2_ADC_INT_BASE       ADCA_BASE               // ADCA-A8  -SOC11
#define MTR2_ADC_INT_NUM        ADC_INT_NUMBER3         // ADCA_INT3-SOC11
#define MTR2_ADC_INT_SOC        ADC_SOC_NUMBER11        // ADCA_INT3-SOC11

#define MTR2_PIE_INT_NUM        INT_ADCA3               // ADCA_INT3-SOC11
#define MTR2_CPU_INT_NUM        INTERRUPT_CPU_INT10     // ADCA_INT3-CPU_INT10
#define MTR2_INT_ACK_GROUP      INTERRUPT_ACK_GROUP10   // ADCA_INT3-CPU_INT10

#define MTR2_PIE_O_IER          PIE_O_IER10             // ADCA_INT3-CPU_INT10
#define MTR2_PIE_IER_INT        PIE_IER10_INTX3        // ADCA_INT3-PIE_INT3
#else  // !MOTOR2_DCLINKSS
#error Not select a right estimator or sampling mode
#endif  // !MOTOR2_DCLINKSS

//------------------------------------------------------------------------------
// CMPSS
#define MTR2_IDC_CMPLP_SEL      ASYSCTL_CMPLPMUX_SELECT_2    // A9*/C8, CMPSS2-LP

#define MTR2_IDC_CMPLP_MUX      2       // A9*/C8, CMPSS2-LP

#define MTR2_IU_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_2    // A10*/C10, CMPSS2-HP
#define MTR2_IU_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_2    // A10*/C10, CMPSS2-LP, N/A

#define MTR2_IV_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_4    // A9*/C8, CMPSS4-HP N/A
#define MTR2_IV_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_4    // A9*/C8, CMPSS4-LP

#define MTR2_IW_CMPHP_SEL       ASYSCTL_CMPHPMUX_SELECT_2    // A4*/C14, CMPSS2, N/A
#define MTR2_IW_CMPLP_SEL       ASYSCTL_CMPLPMUX_SELECT_2    // A4*/C14, CMPSS2

#define MTR2_IU_CMPHP_MUX       3       // A10*/C10, CMPSS2-HP
#define MTR2_IU_CMPLP_MUX       3       // A10*/C10, CMPSS2-LP

#define MTR2_IV_CMPHP_MUX       0       // A9*/C8, CMPSS4-HP
#define MTR2_IV_CMPLP_MUX       0       // A9*/C8, CMPSS4-LP

#define MTR2_IW_CMPHP_MUX       0       // A4*/C14, CMPSS2-HP
#define MTR2_IW_CMPLP_MUX       0       // A4*/C14, CMPSS2-LP

#define MTR2_CMPSS_DACH_VALUE   (2048 + 1024 + 512)
#define MTR2_CMPSS_DACL_VALUE   (2048 - 1024 - 512)

//------------------------------------------------------------------------------
// XBAR-EPWM
#define MTR2_XBAR_TRIP_ADDRL    XBAR_O_TRIP8MUX0TO15CFG
#define MTR2_XBAR_TRIP_ADDRH    XBAR_O_TRIP8MUX16TO31CFG

#define MTR2_IDC_XBAR_EPWM_MUX  XBAR_EPWM_MUX03_CMPSS2_CTRIPL   // CMPSS2_LP
#define MTR2_IDC_XBAR_MUX       XBAR_MUX03                      // CMPSS2_LP

#define MTR2_IU_XBAR_EPWM_MUX   XBAR_EPWM_MUX02_CMPSS2_CTRIPH   // CMPSS2_HP
#define MTR2_IV_XBAR_EPWM_MUX   XBAR_EPWM_MUX07_CMPSS4_CTRIPL   // CMPSS4_LP
#define MTR2_IW_XBAR_EPWM_MUX   XBAR_EPWM_MUX03_CMPSS2_CTRIPL   // CMPSS2_LP

#define MTR2_IU_XBAR_MUX        XBAR_MUX02                  // CMPSS2_HP
#define MTR2_IV_XBAR_MUX        XBAR_MUX07                  // CMPSS4_LP
#define MTR2_IW_XBAR_MUX        XBAR_MUX03                  // CMPSS2_LP

#define MTR2_XBAR_INPUT         XBAR_INPUT2
#define MTR2_TZ_OSHT            EPWM_TZ_SIGNAL_OSHT2

#define MTR2_XBAR_TRIP          XBAR_TRIP8
#define MTR2_DCTRIPIN           EPWM_DC_COMBINATIONAL_TRIPIN8


//! \brief Defines the PWM deadband falling edge delay count (system clocks)
#define MTR2_PWM_DBFED_CNT      5         // 2.25us

//! \brief Defines the PWM deadband rising edge delay count (system clocks)
#define MTR2_PWM_DBRED_CNT      5         // 2.45us

//------------------------------------------------------------------------------
#define SYS_ADC_TRIGGER_TEMP     ADC_TRIGGER_EPWM6_SOCB  // EPWM6_SOCB, CNT=PRD

#define SYS_TEMP_SAMPLE_WINDOW  15

#define SYS_ENVI_ADC_BASE       ADCC_BASE               // ADCC-A0/C15*, N/A
#define SYS_COMP_ADC_BASE       ADCC_BASE               // ADCC-A0/C15*, N/A
#define SYS_PIPE_ADC_BASE       ADCC_BASE               // ADCC-A0/C15*, N/A
#define SYS_EXHT_ADC_BASE       ADCC_BASE               // ADCC-A0/C15*, N/A
#define SYS_IPM1_ADC_BASE       ADCC_BASE               // ADCC-A0/C15*, N/A
#define SYS_IMP2_ADC_BASE       ADCC_BASE               // ADCC-A0/C15*, N/A
#define SYS_LOAD_ADC_BASE       ADCC_BASE               // ADCC-A0/C15*, N/A

#define SYS_ENVI_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-A0/C15*, N/A
#define SYS_COMP_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-A0/C15*, N/A
#define SYS_PIPE_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-A0/C15*, N/A
#define SYS_EXHT_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-A0/C15*, N/A
#define SYS_IMP1_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-A0/C15*, N/A
#define SYS_IMP2_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-A0/C15*, N/A
#define SYS_LOAD_ADCRES_BASE    ADCCRESULT_BASE         // ADCC-A0/C15*, N/A

#define SYS_ENVI_ADC_CH_NUM     ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A
#define SYS_COMP_ADC_CH_NUM     ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A
#define SYS_PIPE_ADC_CH_NUM     ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A
#define SYS_EXHT_ADC_CH_NUM     ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A
#define SYS_IPM1_ADC_CH_NUM     ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A
#define SYS_IMP2_ADC_CH_NUM     ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A
#define SYS_LOAD_ADC_CH_NUM     ADC_CH_ADCIN15          // ADCC-A0/C15*, N/A

#define SYS_ENVI_ADC_SOC_NUM    ADC_SOC_NUMBER8         // ADCC-A0/C15* -SOC8
#define SYS_COMP_ADC_SOC_NUM    ADC_SOC_NUMBER9         // ADCC-A0/C15* -SOC9
#define SYS_PIPE_ADC_SOC_NUM    ADC_SOC_NUMBER10        // ADCC-A0/C15* -SOC10
#define SYS_EXHT_ADC_SOC_NUM    ADC_SOC_NUMBER11        // ADCC-A0/C15* -SOC11
#define SYS_IPM1_ADC_SOC_NUM    ADC_SOC_NUMBER12        // ADCC-A0/C15* -SOC12
#define SYS_IPM2_ADC_SOC_NUM    ADC_SOC_NUMBER13        // ADCC-A0/C15* -SOC13
#define SYS_LOAD_ADC_SOC_NUM    ADC_SOC_NUMBER14        // ADCC-A0/C15* -SOC14

#define SYS_ENVI_ADCRESLT       (SYS_ENVI_ADCRES_BASE + ADC_O_RESULT8)  // ADCA-A7*/C3  -SOC8
#define SYS_COMP_ADCRESLT       (SYS_COMP_ADCRES_BASE + ADC_O_RESULT9)  // ADCA-A12*/C1 -SOC9
#define SYS_PIPE_ADCRESLT       (SYS_PIPE_ADCRES_BASE + ADC_O_RESULT10) // ADCA-A0*/C15 -SOC10
#define SYS_EXHT_ADCRESLT       (SYS_EXHT_ADCRES_BASE + ADC_O_RESULT11) // ADCA-A1*     -SOC11
#define SYS_IPM1_ADCRESLT       (SYS_IPM1_ADCRES_BASE + ADC_O_RESULT12) // ADCA-A11*/C0 -SOC12
#define SYS_IPM2_ADCRESLT       (SYS_IPM2_ADCRES_BASE + ADC_O_RESULT13) // ADCA-A8*/C11 -SOC13
#define SYS_LOAD_ADCRESLT       (SYS_LOAD_ADCRES_BASE + ADC_O_RESULT14) // ADCA-A14*/C4 -SOC14
// BSXL8323RH_REVB
//=============================================================================
//******************************************************************************
#else
#error Not select a right board to set definintion for the hal configuration
#endif
#endif  // !SYSCONFIG_EN


// **************************************************************************
// the typedefs


//! \brief Defines GPIO for the LED numbers
//!
#if defined(SYSCONFIG_EN)
#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
#define HAL_GPIO_LED1       28      //!< GPIO pin number for LaunchPad LED 4
#define HAL_GPIO_LED2       29      //!< GPIO pin number for LaunchPad LED 5
#define HAL_GPIO_LEDS       28      //!< GPIO pin number for LED for Fault
#define HAL_GPIO_ISR_M1     2       //!< GPIO pin number for PFC ISR Executing Time
#define HAL_GPIO_ISR_M2     3       //!< GPIO pin number for MTR1 ISR Executing Time
#define HAL_GPIO_ISR_PFC    32      //!< GPIO pin number for MTR2 ISR Executing Time

//! \brief Defines the function to turn LEDs off
#define HAL_turnOffLED          HAL_setGPIOHigh

//! \brief Defines the function to turn LEDs on
#define HAL_turnOnLED           HAL_setGPIOLow

//! \brief Defines the function to toggle LEDs
#define HAL_toggleLED           HAL_toggleGPIO

//! \brief Defines the function to turn on power relay
#define HAL_turnOnPowerRelay    HAL_setGPIOHigh
// DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
#define HAL_GPIO_LED1       31      //!< GPIO pin number for LaunchPad LED 4
#define HAL_GPIO_LED2       34      //!< GPIO pin number for LaunchPad LED 5
#define HAL_GPIO_LEDS       42      //!< GPIO pin number for LED for Fault
#define HAL_GPIO_ISR_M1     25      //!< GPIO pin number for PFC ISR Executing Time
#define HAL_GPIO_ISR_M2     26      //!< GPIO pin number for MTR1 ISR Executing Time
#define HAL_GPIO_ISR_PFC    27      //!< GPIO pin number for MTR2 ISR Executing Time

//! \brief Defines the function to turn LEDs off
#define HAL_turnOffLED          HAL_setGPIOHigh

//! \brief Defines the function to turn LEDs on
#define HAL_turnOnLED           HAL_setGPIOLow

//! \brief Defines the function to toggle LEDs
#define HAL_toggleLED           HAL_toggleGPIO

//! \brief Defines the function to turn on power relay
#define HAL_turnOnPowerRelay    HAL_setGPIOHigh
// HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
#define HAL_GPIO_LED1       31      //!< GPIO pin number for LaunchPad LED 4
#define HAL_GPIO_LED2       34      //!< GPIO pin number for LaunchPad LED 5
#define HAL_GPIO_LEDS       31      //!< GPIO pin number for LED for Fault
#define HAL_GPIO_ISR_M1     39      //!< GPIO pin number for PFC ISR Executing Time
#define HAL_GPIO_ISR_M2     40      //!< GPIO pin number for MTR1 ISR Executing Time
#define HAL_GPIO_ISR_PFC    35      //!< GPIO pin number for MTR2 ISR Executing Time

//! \brief Defines the function to turn LEDs off
#define HAL_turnOffLED          HAL_setGPIOHigh

//! \brief Defines the function to turn LEDs on
#define HAL_turnOnLED           HAL_setGPIOLow

//! \brief Defines the function to toggle LEDs
#define HAL_toggleLED           HAL_toggleGPIO

//! \brief Defines the function to turn on power relay
#define HAL_turnOnPowerRelay    HAL_setGPIOHigh
// BSXL8323RH_REVB
#else   // Not select a kit
#error Not select a right board to set the GPIO for the LED
#endif   // Not select a kit
#else   // !SYSCONFIG_EN
#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
#define HAL_GPIO_LED1       28      //!< GPIO pin number for LaunchPad LED 4
#define HAL_GPIO_LED2       29      //!< GPIO pin number for LaunchPad LED 5
#define HAL_GPIO_LEDS       28      //!< GPIO pin number for LED for Fault
#define HAL_GPIO_ISR_M1     2       //!< GPIO pin number for PFC ISR Executing Time
#define HAL_GPIO_ISR_M2     3       //!< GPIO pin number for MTR1 ISR Executing Time
#define HAL_GPIO_ISR_PFC    32      //!< GPIO pin number for MTR2 ISR Executing Time

//! \brief Defines the function to turn LEDs off
#define HAL_turnOffLED          HAL_setGPIOHigh

//! \brief Defines the function to turn LEDs on
#define HAL_turnOnLED           HAL_setGPIOLow

//! \brief Defines the function to toggle LEDs
#define HAL_toggleLED           HAL_toggleGPIO

//! \brief Defines the function to turn on power relay
#define HAL_turnOnPowerRelay    HAL_setGPIOHigh
// DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
#define HAL_GPIO_LED1       31      //!< GPIO pin number for LaunchPad LED 4
#define HAL_GPIO_LED2       34      //!< GPIO pin number for LaunchPad LED 5
#define HAL_GPIO_LEDS       42      //!< GPIO pin number for LED for Fault
#define HAL_GPIO_ISR_M1     25      //!< GPIO pin number for PFC ISR Executing Time
#define HAL_GPIO_ISR_M2     26      //!< GPIO pin number for MTR1 ISR Executing Time
#define HAL_GPIO_ISR_PFC    27      //!< GPIO pin number for MTR2 ISR Executing Time

//! \brief Defines the function to turn LEDs off
#define HAL_turnOffLED          HAL_setGPIOHigh

//! \brief Defines the function to turn LEDs on
#define HAL_turnOnLED           HAL_setGPIOLow

//! \brief Defines the function to toggle LEDs
#define HAL_toggleLED           HAL_toggleGPIO

//! \brief Defines the function to turn on power relay
#define HAL_turnOnPowerRelay    HAL_setGPIOHigh
// HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
#define HAL_GPIO_LED1       31      //!< GPIO pin number for LaunchPad LED 4
#define HAL_GPIO_LED2       34      //!< GPIO pin number for LaunchPad LED 5
#define HAL_GPIO_LEDS       31      //!< GPIO pin number for LED for Fault
#define HAL_GPIO_ISR_M1     39      //!< GPIO pin number for PFC ISR Executing Time
#define HAL_GPIO_ISR_M2     40      //!< GPIO pin number for MTR1 ISR Executing Time
#define HAL_GPIO_ISR_PFC    35      //!< GPIO pin number for MTR2 ISR Executing Time

//! \brief Defines the function to turn LEDs off
#define HAL_turnOffLED          HAL_setGPIOHigh

//! \brief Defines the function to turn LEDs on
#define HAL_turnOnLED           HAL_setGPIOLow

//! \brief Defines the function to toggle LEDs
#define HAL_toggleLED           HAL_toggleGPIO

//! \brief Defines the function to turn on power relay
#define HAL_turnOnPowerRelay    HAL_setGPIOHigh
// BSXL8323RH_REVB
#else   // Not select a kit
#error Not select a right board to set the GPIO for the LED
#endif   // Not select a kit
#endif   // !SYSCONFIG_EN

//! \brief Enumeration for the sensor types
//!
typedef enum
{
  HAL_SENSORTYPE_CURRENT = 0,  //!< Enumeration for current sensor
  HAL_SENSORTYPE_VOLTAGE = 1   //!< Enumeration for voltage sensor
} HAL_SensorType_e;

//! \brief Enumeration for the QEP setup
//!
typedef enum
{
  HAL_QEP_QEP1=0,  //!< Select QEP1
  HAL_QEP_QEP2=1   //!< Select QEP2
} HAL_QEPSelect_e;

//! \brief Enumeration for the CPU Timer
//!
typedef enum
{
  HAL_CPU_TIMER0 = 0,  //!< Select CPU Timer0
  HAL_CPU_TIMER1 = 1,  //!< Select CPU Timer1
  HAL_CPU_TIMER2 = 2   //!< Select CPU Timer2
} HAL_CPUTimerNum_e;


// **************************************************************************
// the function prototypes

//! \brief     Acknowledges an interrupt from the ADC so that another ADC
//!            interrupt can happen again.
//! \param[in] handle     The hardware abstraction layer (HAL) handle
static inline void HAL_ackMtr1ADCInt(void)
{
#if defined(MOTOR1_DCLINKSS) && defined(MOTOR1_ESMO)
    // clear the PWM interrupt flag
    EPWM_clearEventTriggerInterruptFlag(MTR1_PWM_INT_BASE);

    // Acknowledge interrupt from PIE group
    Interrupt_clearACKGroup(MTR1_INT_ACK_GROUP);
#else // MOTOR1_FAST or !MOTOR1_DCLINKSS
    // (!MOTOR1_DCLINKSS & MOTOR1_ESMO) or MOTOR1_FAST or (MOTOR1_FAST & MOTOR1_DCLINKSS)
    // clear the ADC interrupt flag
    ADC_clearInterruptStatus(MTR1_ADC_INT_BASE, MTR1_ADC_INT_NUM);

    // Acknowledge interrupt from PIE group
    Interrupt_clearACKGroup(MTR1_INT_ACK_GROUP);
#endif  // !MOTOR1_DCLINKSS or MOTOR1_FAST

    return;
} // end of HAL_ackADCInt() function

//! \brief     Acknowledges an interrupt from the ADC/PWM so that another interrupt
//!            interrupt can happen again.
//! \param[in] handle     The hardware abstraction layer (HAL) handle
static inline void HAL_ackMtr2ADCInt(void)
{
#if defined(MOTOR2_DCLINKSS) && defined(MOTOR2_ESMO)
    // clear the PWM interrupt flag
    EPWM_clearEventTriggerInterruptFlag(MTR2_PWM_INT_BASE);

    // Acknowledge interrupt from PIE group
    Interrupt_clearACKGroup(MTR2_INT_ACK_GROUP);
#else // MOTOR2_FAST or !MOTOR2_DCLINKSS
    // (!MOTOR2_DCLINKSS & MOTOR2_ESMO) or MOTOR2_FAST or (MOTOR2_FAST & MOTOR2_DCLINKSS)
    // clear the ADC interrupt flag
    ADC_clearInterruptStatus(MTR2_ADC_INT_BASE, MTR2_ADC_INT_NUM);

    // Acknowledge interrupt from PIE group
    Interrupt_clearACKGroup(MTR2_INT_ACK_GROUP);
#endif  // !MOTOR2_DCLINKSS or MOTOR2_FAST
    return;
} // end of HAL_ackMtr2Int() function

//! \brief     Acknowledges an interrupt from the ADC so that another ADC
//!            interrupt can happen again.
//! \param[in] handle     The hardware abstraction layer (HAL) handle
static inline void HAL_ackPFCADCInt(void)
{
    // clear the ADC interrupt flag
    ADC_clearInterruptStatus(PFC_ADC_INT_BASE, PFC_ADC_INT_NUM);

    // Acknowledge interrupt from PIE group
    Interrupt_clearACKGroup(PFC_INT_ACK_GROUP);

    return;
} // end of HAL_ackPFCInt() function

//! \brief     Acknowledges an interrupt from the PWM so that another PWM
//!            interrupt can happen again.
//! \param[in] handle     The hardware abstraction layer (HAL) handle
static inline void HAL_ackPFCPWMInt(void)
{
    // clear the PWM interrupt flag
    EPWM_clearEventTriggerInterruptFlag(PFC_PWM_INT_BASE);

    // clear the ADC interrupt flag
    ADC_clearInterruptStatus(PFC_ADC_INT_BASE, PFC_ADC_INT_NUM);

    // Acknowledge interrupt from PIE group
    Interrupt_clearACKGroup(PFC_INT_ACK_GROUP);

    return;
} // end of HAL_ackPFCPWMInt() function

//! \brief      Executes calibration routines
//! \details    Values for offset and gain are programmed into OTP memory at
//!             the TI factory.  This calls and internal function that programs
//!             these offsets and gains into the ADC registers.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_cal(HAL_Handle handle);


//! \brief      Disables global interrupts
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_disableGlobalInts(HAL_Handle handle);

//! \brief      Enables the ADC interrupts
//! \details    Enables the ADC interrupt in the PIE, and CPU.  Enables the 
//!             interrupt to be sent from the ADC peripheral.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_enableCtrlInts(HAL_Handle handle);

//! \brief      Enables the ADC interrupts without CPU interrupts
//! \details    Enables the ADC interrupts to only trigger CLA, and without
//!             interrupting the CPU
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_enableADCIntsToTriggerCLA(HAL_Handle handle);

//! \brief      Enables the debug interrupt
//! \details    The debug interrupt is used for the real-time debugger.  It is
//!             not needed if the real-time debugger is not used.  Clears
//!             bit 1 of ST1.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_enableDebugInt(HAL_Handle handle);

//! \brief      Enables the 8320/8301 device
//! \details    Provides the correct timing to enable the drv8320
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_enableDRV(HAL_MTR_Handle handle);

//! \brief     Enables global interrupts
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_enableGlobalInts(HAL_Handle handle);

//! \brief     Gets the PWM duty cycle times
//! \param[in] handle       The hardware abstraction layer (HAL) handle
//! \param[in] pDutyCycles  A pointer to memory for the duty cycle durations
static inline void
HAL_getDutyCycles(HAL_MTR_Handle handle,uint16_t *pDutyCycles)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  pDutyCycles[0] = EPWM_getCounterCompareValue(obj->pwmHandle[0],
                                               EPWM_COUNTER_COMPARE_A);
  pDutyCycles[1] = EPWM_getCounterCompareValue(obj->pwmHandle[1],
                                               EPWM_COUNTER_COMPARE_A);
  pDutyCycles[2] = EPWM_getCounterCompareValue(obj->pwmHandle[2],
                                               EPWM_COUNTER_COMPARE_A);
  return;
} // end of HAL_getDutyCycles() function


//! \brief     Gets the number of current sensors
//! \param[in] handle  The hardware abstraction layer (HAL) handle
//! \return    The number of current sensors
static inline uint16_t HAL_getNumCurrentSensors(HAL_MTR_Handle handle)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;
  
  return(obj->numCurrentSensors);
} // end of HAL_getNumCurrentSensors() function


//! \brief     Gets the number of voltage sensors
//! \param[in] handle  The hardware abstraction layer (HAL) handle
//! \return    The number of voltage sensors
static inline uint16_t HAL_getNumVoltageSensors(HAL_MTR_Handle handle)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  return(obj->numVoltageSensors);
} // end of HAL_getNumVoltageSensors() function

//! \brief     Gets the pwm enable status
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
//! \return    The pwm enable
static inline bool HAL_getPwmEnableStatus(HAL_MTR_Handle handle)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  return(obj->flagEnablePWM);
} // end of HAL_getPwmStatus() function

//! \brief     Gets the pwm enable status
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
//! \return    The pwm enable
static inline bool HAL_getPFCPwmEnableStatus(HAL_PFC_Handle handle)
{
  HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

  return(obj->flagEnablePWM);
} // end of HAL_getPFCPwmEnableStatus() function

//! \brief     Get the period of EPWM time-base module
//! \param[in] handle  The hardware abstraction layer (HAL) handle
//! \return    The periode of EPWM time-base module
static inline uint16_t
HAL_getTimeBasePeriod(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

    return(EPWM_getTimeBasePeriod(obj->pwmHandle[0]));
} // end of HAL_getTimeBasePeriod() function


//! \brief      Configures the fault protection logic for motor
//! \details    Sets up the trip zone inputs so that when a comparator
//!             signal from outside the micro-controller trips a fault,
//!             the EPWM peripheral blocks will force the
//!             power switches into a high impedance state.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupMtrFaults(HAL_MTR_Handle handle);


//! \brief      Configures the fault protection logic for PFC
//! \details    Sets up the trip zone inputs so that when a comparator
//!             signal from outside the micro-controller trips a fault,
//!             the EPWM peripheral blocks will force the
//!             power switches into a high impedance state.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupPFCFaults(HAL_PFC_Handle handle);

//! \brief      Initializes the hardware abstraction layer (HAL) object
//! \details    Initializes all handles to the microcontroller peripherals.
//!             Returns a handle to the HAL object.
//! \param[in]  pMemory   A pointer to the memory for the hardware abstraction layer object
//! \param[in]  numBytes  The number of bytes allocated for the hardware abstraction layer object, bytes
//! \return     The hardware abstraction layer (HAL) object handle
extern HAL_Handle HAL_init(void *pMemory,const size_t numBytes);


//! \brief      Initializes the hardware abstraction layer (HAL) object
//! \details    Initializes all handles to the microcontroller peripherals.
//!             Returns a handle to the HAL_MTR object.
//! \param[in]  pMemory   A pointer to the memory for the hardware abstraction layer object
//! \param[in]  numBytes  The number of bytes allocated for the hardware abstraction layer object, bytes
//! \return     The hardware abstraction layer (HAL_MTR) object handle
extern HAL_MTR_Handle HAL_MTR_init(void *pMemory,
                                   const size_t numBytes,
                                   const MotorNum_e mtrNum);

//! \brief      Initializes the hardware abstraction layer (HAL) object
//! \details    Initializes all handles to the microcontroller peripherals.
//!             Returns a handle to the HAL_MTR object.
//! \param[in]  pMemory   A pointer to the memory for the hardware abstraction layer object
//! \param[in]  numBytes  The number of bytes allocated for the hardware abstraction layer object, bytes
//! \return     The hardware abstraction layer (HAL_MTR) object handle
extern HAL_PFC_Handle HAL_PFC_init(void *pMemory, const size_t numBytes);

//! \brief      Initializes the hardware abstraction layer (HAL) object
//! \details    Initializes all handles to the microcontroller peripherals.
//!             Returns a handle to the HAL_MTR object.
//! \param[in]  pMemory   A pointer to the memory for the hardware abstraction layer object
//! \param[in]  numBytes  The number of bytes allocated for the hardware abstraction layer object, bytes
//! \return     The hardware abstraction layer (HAL_MTR) object handle
extern void HAL_initMtrHandle(HAL_Handle handle, HAL_MTR_Handle mtr1Handle,
                           HAL_MTR_Handle mtr2Handle);


//! \brief      Initializes the hardware abstraction layer (HAL) object
//! \details    Initializes all handles to the microcontroller peripherals.
//!             Returns a handle to the HAL_MTR object.
//! \param[in]  pMemory   A pointer to the memory for the hardware abstraction layer object
//! \param[in]  numBytes  The number of bytes allocated for the hardware abstraction layer object, bytes
//! \return     The hardware abstraction layer (HAL_MTR) object handle
extern void HAL_initPFCHandle(HAL_Handle handle, HAL_PFC_Handle pfcHandle);

//! \brief      Initializes the interrupt vector table
//! \details    Points the ISR to the function mainISR.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_initIntVectorTable(HAL_Handle handle)
{
#ifndef PFC_DISABLE
    // PFC
    Interrupt_register(PFC_PIE_INT_NUM, &pfcCtrlISR);
#endif  // PFC_DISABLE

#ifndef MOTOR1_DISABLE
    // Motor_1
    Interrupt_register(MTR1_PIE_INT_NUM, &motor1CtrlISR);
#endif  // !MOTOR1_DISABLE

#ifndef MOTOR2_DISABLE
    // Motor_2
    Interrupt_register(MTR2_PIE_INT_NUM, &motor2CtrlISR);
#endif  // !MOTOR2_DISABLE

    return;
} // end of HAL_initIntVectorTable() function

//! \brief      Reads the ADC data with offset
//! \details    Reads in the ADC result registers and scales the values
//!             according to the settings in user_m1.h or user_m2.h.
//!             The structure gAdcData holds three phase voltages,
//!             three line currents, and one DC bus voltage.
//! \param[in]  handle    The hardware abstraction layer (HAL) handle
//! \param[in]  pADCData  A pointer to the ADC data buffer
static inline void HAL_readMtr1ADCData(HAL_ADCData_t *pADCData)
{
    float32_t value;

#if defined(MOTOR1_DCLINKSS)
    // convert dc-link current 1
    value = (float32_t)ADC_readResult(MTR1_IDC1_ADCRES_BASE, MTR1_IDC1_ADC_SOC_NUM);
    pADCData->Idc1_A.value[0] = value * pADCData->current_sf - pADCData->offset_Idc_A;

    // convert dc-link current 2
    value = (float32_t)ADC_readResult(MTR1_IDC2_ADCRES_BASE, MTR1_IDC2_ADC_SOC_NUM);
    pADCData->Idc1_A.value[1] = value * pADCData->current_sf - pADCData->offset_Idc_A;

    // convert dc-link current 3
    value = (float32_t)ADC_readResult(MTR1_IDC3_ADCRES_BASE, MTR1_IDC3_ADC_SOC_NUM);
    pADCData->Idc2_A.value[0] = value * pADCData->current_sf - pADCData->offset_Idc_A;

    // convert dc-link current 4
    value = (float32_t)ADC_readResult(MTR1_IDC4_ADCRES_BASE, MTR1_IDC4_ADC_SOC_NUM);
    pADCData->Idc2_A.value[1] = value * pADCData->current_sf - pADCData->offset_Idc_A;
#else
    // convert phase A current
    value = (float32_t)ADC_readResult(MTR1_IU_ADCRES_BASE, MTR1_IU_ADC_SOC_NUM);
    pADCData->I_A.value[0] = value * pADCData->current_sf - pADCData->offset_I_A[0];

    // convert phase B current
    value = (float32_t)ADC_readResult(MTR1_IV_ADCRES_BASE, MTR1_IV_ADC_SOC_NUM);
    pADCData->I_A.value[1] = value * pADCData->current_sf - pADCData->offset_I_A[1];

    // convert phase C current
    value = (float32_t)ADC_readResult(MTR1_IW_ADCRES_BASE, MTR1_IW_ADC_SOC_NUM);
    pADCData->I_A.value[2] = value * pADCData->current_sf - pADCData->offset_I_A[2];
#endif  // MOTOR1_DCLINKSS

#if defined(MOTOR1_FAST)
    // convert phase A voltage
    value = (float32_t)ADC_readResult(MTR1_VU_ADCRES_BASE, MTR1_VU_ADC_SOC_NUM);
    pADCData->V_V.value[0] = value * pADCData->voltage_sf;

    // convert phase B voltage
    value = (float32_t)ADC_readResult(MTR1_VV_ADCRES_BASE, MTR1_VV_ADC_SOC_NUM);
    pADCData->V_V.value[1] = value * pADCData->voltage_sf;

    // convert phase C voltage
    value = (float32_t)ADC_readResult(MTR1_VW_ADCRES_BASE, MTR1_VW_ADC_SOC_NUM);
    pADCData->V_V.value[2] = value * pADCData->voltage_sf;
#endif  // MOTOR1_FAST

    return;
} // end of HAL_readMtr1ADCData() functions

//! \brief      Reads the ADC data with offset
//! \details    Reads in the ADC result registers and scales the values
//!             according to the settings in user_m1.h or user_m2.h.
//!             The structure gAdcData holds three phase voltages,
//!             three line currents, and one DC bus voltage.
//! \param[in]  handle    The hardware abstraction layer (HAL) handle
//! \param[in]  pADCData  A pointer to the ADC data buffer
static inline void HAL_readMtr2ADCData(HAL_ADCData_t *pADCData)
{
    float32_t value;

#if defined(MOTOR2_DCLINKSS)
    // convert dc-link current 1
    value = (float32_t)ADC_readResult(MTR2_IDC1_ADCRES_BASE, MTR2_IDC1_ADC_SOC_NUM);
    pADCData->Idc1_A.value[0] = value * pADCData->current_sf - pADCData->offset_Idc_A;

    // convert dc-link current 2
    value = (float32_t)ADC_readResult(MTR2_IDC2_ADCRES_BASE, MTR2_IDC2_ADC_SOC_NUM);
    pADCData->Idc1_A.value[1] = value * pADCData->current_sf - pADCData->offset_Idc_A;

    // convert dc-link current 3
    value = (float32_t)ADC_readResult(MTR2_IDC3_ADCRES_BASE, MTR2_IDC3_ADC_SOC_NUM);
    pADCData->Idc2_A.value[0] = value * pADCData->current_sf - pADCData->offset_Idc_A;

    // convert dc-link current 4
    value = (float32_t)ADC_readResult(MTR2_IDC4_ADCRES_BASE, MTR2_IDC4_ADC_SOC_NUM);
    pADCData->Idc2_A.value[1] = value * pADCData->current_sf - pADCData->offset_Idc_A;
#else
    // convert phase A current
    value = (float32_t)ADC_readResult(MTR2_IU_ADCRES_BASE, MTR2_IU_ADC_SOC_NUM);
    pADCData->I_A.value[0] = value * pADCData->current_sf - pADCData->offset_I_A[0];

    // convert phase B current
    value = (float32_t)ADC_readResult(MTR2_IV_ADCRES_BASE, MTR2_IV_ADC_SOC_NUM);
    pADCData->I_A.value[1] = value * pADCData->current_sf - pADCData->offset_I_A[1];

    // convert phase C current
    value = (float32_t)ADC_readResult(MTR2_IW_ADCRES_BASE, MTR2_IW_ADC_SOC_NUM);
    pADCData->I_A.value[2] = value * pADCData->current_sf - pADCData->offset_I_A[2];
#endif  // MOTOR2_DCLINKSS

#if defined(MOTOR2_FAST)
    // convert phase A voltage
    value = (float32_t)ADC_readResult(MTR2_VU_ADCRES_BASE, MTR2_VU_ADC_SOC_NUM);
    pADCData->V_V.value[0] = value * pADCData->voltage_sf;

    // convert phase B voltage
    value = (float32_t)ADC_readResult(MTR2_VV_ADCRES_BASE, MTR2_VV_ADC_SOC_NUM);
    pADCData->V_V.value[1] = value * pADCData->voltage_sf;

    // convert phase C voltage
    value = (float32_t)ADC_readResult(MTR2_VW_ADCRES_BASE, MTR2_VW_ADC_SOC_NUM);
    pADCData->V_V.value[2] = value * pADCData->voltage_sf;
#endif  // MOTOR2_FAST

    return;
} // end of HAL_readMtr2ADCData() functions

//! \brief      Reads the ADC data with offset
//! \details    Reads in the ADC result registers and scales the values
//!             according to the settings in user_m1.h or user_m2.h.
//!             The structure gAdcData holds three phase voltages,
//!             three line currents, and one DC bus voltage.
//! \param[in]  handle    The hardware abstraction layer (HAL) handle
//! \param[in]  pADCData  A pointer to the ADC data buffer
#ifndef PFC_DISABLE
static inline void HAL_readPFCADCData(HAL_PFC_ADCData_t *pADCData)
{
    float32_t value;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    // convert acbus voltage
    value = (float32_t)(ADC_readPPBResult(PFC_VAC_ADCRES_BASE, PFC_VAC1_ADC_PPB_NUM) +
            ADC_readPPBResult(PFC_VAC_ADCRES_BASE, PFC_VAC2_ADC_PPB_NUM));
    pADCData->VacSen = value * pADCData->voltageAC_sf;

    // convert dcBus voltage
    value = (float32_t)(ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC1_ADC_SOC_NUM) +
            ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC2_ADC_SOC_NUM));
    pADCData->VdcBus = value * pADCData->voltageDC_sf;
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    // convert acbus_L voltage
    value = (float32_t)(ADC_readResult(PFC_VAC_ADCRES_BASE, PFC_VAC1_ADC_SOC_NUM) +
            ADC_readResult(PFC_VAC_ADCRES_BASE, PFC_VAC2_ADC_SOC_NUM));
    pADCData->ValBus = value * pADCData->voltageAC_sf;

    // convert acbus_N voltage
    value = (float32_t)(ADC_readResult(PFC_VAN_ADCRES_BASE, PFC_VAN1_ADC_SOC_NUM) +
            ADC_readResult(PFC_VAN_ADCRES_BASE, PFC_VAN2_ADC_SOC_NUM));
    pADCData->VanBus = value * pADCData->voltageAC_sf;

    // convert dcBus voltage
    value = (float32_t)(ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC1_ADC_SOC_NUM) +
            ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC2_ADC_SOC_NUM));
    pADCData->VdcBus = value * pADCData->voltageDC_sf;
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    // convert acbus voltage
    value = (float32_t)(ADC_readPPBResult(PFC_VAC_ADCRES_BASE, PFC_VAC1_ADC_PPB_NUM) +
            ADC_readPPBResult(PFC_VAC_ADCRES_BASE, PFC_VAC2_ADC_PPB_NUM));
    pADCData->VacSen = value * pADCData->voltageAC_sf;

    // convert dcBus voltage
    value = (float32_t)(ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC1_ADC_SOC_NUM) +
            ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC2_ADC_SOC_NUM));
    pADCData->VdcBus = value * pADCData->voltageDC_sf;
    // BSXL8323RH_REVB
#else  // (No Right HW)
#error Not select a right board to read ADC result for PFC
#endif  // (No Right HW)
    return;
} // end of HAL_readPFCADCData() functions
#else  // PFC_DISABLE
#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
static inline void HAL_readPFCADCData(HAL_PFC_ADCData_t *pADCData)
{
    float32_t value;

#if !defined(MOTOR1_DISABLE)
    // convert dcBus voltage
    value = (float32_t)(ADC_readResult(MTR1_VDC_ADCRES_BASE, MTR1_VDC_ADC_SOC_NUM) +
            ADC_readResult(MTR1_VDC_ADCRES_BASE, MTR1_VDC_ADC_SOC_NUM));
    pADCData->VdcBus = value * pADCData->voltageDC_sf;
#elif !defined(MOTOR2_DISABLE)
    // convert dcBus voltage
    value = (float32_t)(ADC_readResult(MTR2_VDC_ADCRES_BASE, MTR2_VDC_ADC_SOC_NUM) +
            ADC_readResult(MTR2_VDC_ADCRES_BASE, MTR2_VDC_ADC_SOC_NUM));
    pADCData->VdcBus = value * pADCData->voltageDC_sf;
#else
#error at least one motor is enabled in this case
#endif  //

    return;
} // end of HAL_readPFCADCData() functions
// DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
static inline void HAL_readPFCADCData(HAL_PFC_ADCData_t *pADCData)
{
    float32_t value;

    // convert dcBus voltage
    value = (float32_t)ADC_readResult(MTR1_VDC_ADCRES_BASE, MTR1_VDC_ADC_SOC_NUM);
    pADCData->VdcBus = value * pADCData->voltageDC_sf;

    return;
} // end of HAL_readPFCADCData() functions
// HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
static inline void HAL_readPFCADCData(HAL_PFC_ADCData_t *pADCData)
{
    float32_t value;

    // convert dcBus voltage
    value = (float32_t)(ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC1_ADC_SOC_NUM) +
            ADC_readResult(PFC_VDC_ADCRES_BASE, PFC_VDC2_ADC_SOC_NUM));
    pADCData->VdcBus = value * pADCData->voltageDC_sf;

    return;
} // end of HAL_readPFCADCData() functions
// BSXL8323RH_REVB
#else  // (!No Right HW)
#error Not select a right board to read ADC result for PFC
#endif  // (!No Right HW)
#endif  // PFC_DISABLE

//! \brief     Reads the timer count
//! \param[in] handle       The hardware abstraction layer (HAL) handle
//! \param[in] timerNumber  The timer number, 0,1 or 2
//! \return    The timer count
static inline uint32_t
HAL_readTimerCnt(HAL_Handle handle,const uint16_t timerNumber)
{
    HAL_Obj *obj = (HAL_Obj *)handle;

    uint32_t timerCnt = CPUTimer_getTimerCount(obj->timerHandle[timerNumber]);

    return(timerCnt);
} // end of HAL_readTimerCnt() function

//! \brief     Sets the GPIO pin high
//! \param[in] handle      The hardware abstraction layer (HAL) handle
//! \param[in] gpioNumber  The GPIO number
static inline void HAL_setGPIOHigh(const uint32_t gpioNumber)
{

  // set GPIO high
  GPIO_writePin(gpioNumber, 1);

  return;
} // end of HAL_setGPIOHigh() function


//! \brief     Read the GPIO pin
//! \param[in] handle      The hardware abstraction layer (HAL) handle
//! \param[in] gpioNumber  The GPIO number
//! \return    The GPIO pin
static inline uint32_t HAL_readGPIOData(const uint32_t gpioNumber)
{
    uint32_t gpioPinData;

    // set GPIO high
    gpioPinData = GPIO_readPin(gpioNumber);

    return(gpioPinData);
} // end of HAL_readGPIOData() function


//! \brief     Sets the GPIO pin low
//! \param[in] handle      The hardware abstraction layer (HAL) handle
//! \param[in] gpioNumber  The GPIO number
static inline void HAL_setGPIOLow(const uint32_t gpioNumber)
{
    // set GPIO low
    GPIO_writePin(gpioNumber, 0);

    return;
} // end of HAL_setGPIOLow() function

//! \brief     Toggles the GPIO pin
//! \param[in] handle      The hardware abstraction layer (HAL) handle
//! \param[in] gpioNumber  The GPIO number
static inline void HAL_toggleGPIO(const uint32_t gpioNumber)
{

    // set GPIO high
    GPIO_togglePin(gpioNumber);

    return;
} // end of HAL_toggleGPIO() function


//! \brief     Sets the value of the internal DAC of the high comparator
//! \param[in] handle      The hardware abstraction layer (HAL) handle
//! \param[in] cmpssNumber The CMPSS number
//! \param[in] dacValue    The DAC value of the high comparator
static inline void
HAL_setCMPSSDACValueHigh(HAL_MTR_Handle handle,
                         const uint16_t cmpssNumber, uint16_t dacValue)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

    // set GPIO low
    CMPSS_setDACValueHigh(obj->cmpssHandle[cmpssNumber], dacValue);

    return;
} // end of HAL_setCMPSSDACValueHigh() function


//! \brief     Sets the value of the internal DAC of the low comparator
//! \param[in] handle      The hardware abstraction layer (HAL) handle
//! \param[in] cmpssNumber The CMPSS number
//! \param[in] dacValue    The DAC value of the low comparator
static inline void
HAL_setCMPSSDACValueLow(HAL_MTR_Handle handle,
                        const uint16_t cmpssNumber, uint16_t dacValue)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  // set GPIO low
  CMPSS_setDACValueLow(obj->cmpssHandle[cmpssNumber], dacValue);

  return;
} // end of HAL_setCMPSSDACValueLow() function

//! \brief     Sets the number of voltage sensors
//! \param[in] handle             The hardware abstraction layer (HAL) handle
//! \param[in] numVoltageSensors  The number of voltage sensors
static inline void
HAL_setNumVoltageSensors(HAL_MTR_Handle handle,const uint16_t numVoltageSensors)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  obj->numVoltageSensors = numVoltageSensors;

  return;
} // end of HAL_setNumVoltageSensors() function

//! \brief     Sets the number of current sensors
//! \param[in] handle             The hardware abstraction layer (HAL) handle
//! \param[in] numCurrentSensors  The number of current sensors
static inline void
HAL_setNumCurrentSensors(HAL_MTR_Handle handle,const uint16_t numCurrentSensors)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  obj->numCurrentSensors = numCurrentSensors;

  return;
} // end of HAL_setNumCurrentSensors() function

//! \brief      Sets the hardware abstraction layer parameters
//! \details    Sets up the microcontroller peripherals.  Creates all of the scale
//!             factors for the ADC voltage and current conversions.  Sets the initial
//!             offset values for voltage and current measurements.
//! \param[in]  handle       The hardware abstraction layer (HAL) handle
extern void HAL_setParams(HAL_Handle handle);

//! \brief      Sets the hardware abstraction layer parameters
//! \details    Sets up the microcontroller peripherals.  Creates all of the scale
//!             factors for the ADC voltage and current conversions.  Sets the initial
//!             offset values for voltage and current measurements.
//! \param[in]  handle       The hardware abstraction layer (HAL) handle
extern void HAL_MTR_setParams(HAL_MTR_Handle handle, USER_Params *pUserParams);

//! \brief      Sets the hardware abstraction layer parameters
//! \details    Sets up the microcontroller peripherals.  Creates all of the scale
//!             factors for the ADC voltage and current conversions.  Sets the initial
//!             offset values for voltage and current measurements.
//! \param[in]  handle       The hardware abstraction layer (HAL) handle
extern void HAL_PFC_setParams(HAL_PFC_Handle handle);

//! \brief      Sets up the ADCs (Analog to Digital Converters)
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupADCs(HAL_Handle handle);

//! \brief      Sets up the CMPSSs (Comparator Subsystems)
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupCMPSSsMTR(HAL_MTR_Handle handle);

//! \brief      Sets up the CMPSSs (Comparator Subsystems)
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupCMPSSsPFC(HAL_PFC_Handle handle);

//! \brief      Sets up the clocks
//! \details    Sets up the micro-controller's main oscillator
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupClks(HAL_Handle handle);

//! \brief     Sets up the GATE object
//! \param[in] handle       The hardware abstraction layer (HAL) handle
extern void HAL_setupGate(HAL_MTR_Handle handle);

//! \brief     Sets up the GPIO (General Purpose I/O) pins
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupGPIOs(HAL_Handle handle);

//! \brief     Sets up the FLASH.
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupFlash(HAL_Handle handle);

//! \brief     Sets up the CLA
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupCLA(HAL_Handle handle);

//! \brief     Sets up the peripheral clocks
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupPeripheralClks(HAL_Handle handle);

//! \brief     Sets up the PIE (Peripheral Interrupt Expansion)
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupPIE(HAL_Handle handle);

#if defined(EPWMDAC_MODE)
//! \brief     Sets up the PWMs (Pulse Width Modulators)
//! \param[in] handle          The hardware abstraction layer (HAL) handle
//! \param[in] systemFreq_MHz  The system frequency, MHz
extern void HAL_setupPWMDACs(HAL_Handle handle,
                   const float32_t systemFreq_MHz);
#endif  // EPWMDAC_MODE

//! \brief     Sets up the QEP peripheral
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupQEP(HAL_MTR_Handle handle);

//! \brief     Sets up the SCIA
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupSCIA(HAL_Handle handle);

//! \brief     Sets up the SCIB
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupSCIB(HAL_Handle handle);

//! \brief     Sets up the SCIC
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupSCIC(HAL_Handle handle);

//! \brief     Sets up the I2CA
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupI2CA(HAL_Handle handle);

//! \brief     Sets up the SPI
//! \param[in] handle  The hardware abstraction layer (HAL) handle
extern void HAL_setupSPI(HAL_MTR_Handle handle);

//! \brief     Sets up the CPU timer for time base
//! \param[in] handle          The hardware abstraction layer (HAL) handle
//! \param[in] systemFreq_MHz  The system frequency, MHz
extern void HAL_setupTimeBaseTimer(HAL_Handle handle,
                                   const float32_t timeBaseFreq_Hz);

//! \brief     Sets up the CPU timer for ADC trigger
//! \param[in] handle          The hardware abstraction layer (HAL) handle
//! \param[in] systemFreq_MHz  The system frequency, MHz
extern void HAL_setupADCTriggerTimer(HAL_Handle handle,
                                     const float32_t adcTriggerFreq_Hz);

//! \brief     Sets up the timers for CPU usage diagnostics
//! \param[in] handle          The hardware abstraction layer (HAL) handle
extern void HAL_setupCPUUsageTimer(HAL_Handle handle);

//! \brief     Sets up the timers
//! \param[in] handle          The hardware abstraction layer (HAL) handle
//! \param[in] cpuTimerNumber  The CPU timer number
static inline void
HAL_clearCPUTimerFlag(HAL_Handle halHandle, const uint16_t cpuTimerNumber)
{
    HAL_Obj   *obj = (HAL_Obj *)halHandle;

    CPUTimer_clearOverflowFlag(obj->timerHandle[cpuTimerNumber]);

    return;
}   // end of HAL_clearTimerFlag() function


//! Sets the CPU timer period count.
//! \param base is the base address of the timer module.
//! \param timerCount is the CPU timer timer count.
static inline void HAL_setCPUTimerCount(HAL_Handle halHandle, uint32_t timerCount)
{
    HAL_Obj   *obj = (HAL_Obj *)halHandle;

    //
    // Load the MSB timer Count
    //
    HWREG(obj->timerHandle[1] + CPUTIMER_O_TIM) = timerCount;

    return;
}

static inline void HAL_loadCPUTimerCount(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

    // Load the MSB timer Count
    HWREG(CPUTIMER1_BASE + CPUTIMER_O_TIM) =
            (uint32_t)(EPWM_getTimeBaseCounterValue(obj->pwmHandle));

    return;
}

//! \brief     Gets CPU Timer status
//! \param[in] handle          The hardware abstraction layer (HAL) handle
//! \param[in] cpuTimerNumber  The CPU timer number
static inline bool
HAL_getCPUTimerStatus(HAL_Handle halHandle, const uint16_t cpuTimerNumber)
{
    HAL_Obj   *obj = (HAL_Obj *)halHandle;

    return (CPUTimer_getTimerOverflowStatus(obj->timerHandle[cpuTimerNumber]));
}

//---------------------------------------BN_ADD_05032024------------------
//static inline bool
//HAL_getCPUTimerStatus(HAL_Handle halHandle, const uint16_t cpuTimerNumber) //CPUTimer_enableInterrupt
//{
//    HAL_Obj   *obj = (HAL_Obj *)halHandle;

//    return (CPUTimer_enableInterrupt(obj->timerHandle[cpuTimerNumber]));
//}
#if defined(EPWMDAC_MODE)
//! \brief     Writes DAC data to the PWM comparators for DAC output
//! \param[in] handle    The hardware abstraction layer (HAL) handle
//! \param[in] pPWMDACData  The pointer to the DAC data
static inline void
HAL_writePWMDACData(HAL_Handle handle, HAL_PWMDACData_t *pPWMDACData)
{
    HAL_Obj *obj = (HAL_Obj *)handle;

    // convert values from float to unit16
    uint16_t cnt;
    float32_t period;
    float32_t dacData_sat_dc;
    float32_t dacData;
    float32_t value;

    int16_t cmpValue[4];

    period = (float32_t)pPWMDACData->periodMax;

    for(cnt = 0; cnt < 4; cnt++)
    {
        dacData = (*pPWMDACData->ptrData[cnt]);
        dacData_sat_dc = dacData * pPWMDACData->gain[cnt] +
                pPWMDACData->offset[cnt];

        value = dacData_sat_dc * period;

        cmpValue[cnt] = (int16_t)__fsat(value, period, 0);
    }

    // write the DAC data
    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmDACHandle[PWMDAC_NUMBER_1],
                                EPWM_COUNTER_COMPARE_A, cmpValue[0]);

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmDACHandle[PWMDAC_NUMBER_2],
                                EPWM_COUNTER_COMPARE_B, cmpValue[1]);

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmDACHandle[PWMDAC_NUMBER_3],
                                EPWM_COUNTER_COMPARE_A, cmpValue[2]);

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmDACHandle[PWMDAC_NUMBER_4],
                                EPWM_COUNTER_COMPARE_B, cmpValue[3]);

    return;
} // end of HAL_writeDacData() function
#endif  // EPWMDAC_MODE

//! \brief     Writes DAC data to the PWM comparators for DAC output
//! \param[in] handle    The hardware abstraction layer (HAL) handle
//! \param[in] pPWMDACData  The pointer to the DAC data
void HAL_setPWMDACParameters(HAL_Handle handle, HAL_PWMDACData_t *pPWMDACData);

//! \brief
//! \param[in]
//! \param[in]
void HAL_clearDataRAM(void *pMemory, uint16_t lengthMemory);

//! \brief     Reads PWM period register
//! \param[in] handle     The hardware abstraction layer (HAL) handle
//! \param[in] pwmNumber  The PWM number
//! \return    The PWM period value
static inline uint16_t
HAL_readPWMPeriod(HAL_MTR_Handle handle,const uint16_t pwmNumber)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  // the period value to be returned
  uint16_t pwmPeriodValue;

  pwmPeriodValue = EPWM_getTimeBasePeriod(obj->pwmHandle[pwmNumber]);

  return(pwmPeriodValue);
} // end of HAL_readPWMPeriod() function

//! \brief     Writes PWM data to the PWM comparators for motor control
//! \param[in] handle    The hardware abstraction layer (HAL) handle
//! \param[in] pPWMData  The pointer to the PWM data
static inline void
HAL_writePWMData(HAL_MTR_Handle handle, HAL_PWMData_t *pPWMData)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

    float32_t period = (float32_t)(EPWM_getTimeBasePeriod(obj->pwmHandle[0]));

    uint16_t pwmCnt;

    for(pwmCnt = 0; pwmCnt < 3; pwmCnt++)
    {
      // compute the value
        float32_t V_pu = -pPWMData->Vabc_pu.value[pwmCnt];      // Negative
        float32_t V_sat_pu = __fsat(V_pu, 0.5, -0.5);           // -0.5~0.5
        float32_t V_sat_dc_pu = V_sat_pu + 0.5;                 // 0~1.0
        pPWMData->cmpValue[pwmCnt]  = (int16_t)(V_sat_dc_pu * period);  //

        // write the PWM data value
        EPWM_setCounterCompareValue(obj->pwmHandle[pwmCnt],
                                    EPWM_COUNTER_COMPARE_A,
                                    pPWMData->cmpValue[pwmCnt]);

        EPWM_setCounterCompareValue(obj->pwmHandle[pwmCnt],
                                    EPWM_COUNTER_COMPARE_B,
                                    pPWMData->cmpValue[pwmCnt]);
    }

    return;
} // end of HAL_writePWMData() function

//! \brief     Writes PWM data to the PWM comparators for motor control
//! \param[in] handle    The hardware abstraction layer (HAL) handle
//! \param[in] pPWMData  The pointer to the PWM data
static inline void
HAL_writePFCPWMData(HAL_PFC_Handle handle, HAL_PFC_PWMData_t *pPWMData)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

    float32_t period = (float32_t)(EPWM_getTimeBasePeriod(obj->pwmHandle));

    pPWMData->cmpValue  = (int16_t)(period * pPWMData->dutyValue);  //

#if defined(ILPFC_DCH_EN)
    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_A,
                                (period - pPWMData->cmpValue));

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_B,
                                pPWMData->cmpValue);
#elif defined(SPPFC_CHA_EN)
    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_A,
                                (period - pPWMData->cmpValue));

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_B,
                                0);
#elif defined(SPPFC_CHB_EN)
    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_A,
                                period);

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_B,
                                pPWMData->cmpValue);
#else      // !(SPPFC_CHA_EN || SPPFC_CHB_EN)
#error Not select a right PFC output mode
#endif      // !(SPPFC_CHA_EN || SPPFC_CHB_EN)

    return;
} // end of HAL_writePWMData() function


//! \brief      Enables the PWM devices for motor control
//! \details    Turns on the outputs of the EPWM peripheral which will allow
//!             the power switches to be controlled.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_enableMtrPWM(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

    obj->flagEnablePWM = true;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
#if defined(MOTOR2_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR2_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR2_DCLINKSS
    }
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    GPIO_writePin(obj->gateEnableGPIO, 0);

    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
    }

    GPIO_writePin(obj->gateEnableGPIO, 1);
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
    }
    // BSXL8323RH_REVB
#else
#error Not select a right board to enable PWM for motors
#endif  // No Hardware Boards

    // Clear any Trip Zone flag
    EPWM_clearTripZoneFlag(obj->pwmHandle[0], HAL_TZFLAG_INTERRUPT_ALL);
    EPWM_clearTripZoneFlag(obj->pwmHandle[1], HAL_TZFLAG_INTERRUPT_ALL);
    EPWM_clearTripZoneFlag(obj->pwmHandle[2], HAL_TZFLAG_INTERRUPT_ALL);

    obj->flagEnablePWM = true;

    return;
} // end of HAL_enableMtrPWM() function


//! \brief      clear fault status of motor control
//! \details
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_clearMtrFaultStatus(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
#if defined(MOTOR2_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR2_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR2_DCLINKSS
    }
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
    }
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        // Clear any comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);

    }
    // BSXL8323RH_REVB
#else
#error Not select a right board to clear the fault trip flag for motors
#endif  // No Hardware Boards

    // Clear any Trip Zone flag
    EPWM_clearTripZoneFlag(obj->pwmHandle[0], HAL_TZFLAG_INTERRUPT_ALL);
    EPWM_clearTripZoneFlag(obj->pwmHandle[1], HAL_TZFLAG_INTERRUPT_ALL);
    EPWM_clearTripZoneFlag(obj->pwmHandle[2], HAL_TZFLAG_INTERRUPT_ALL);

    return;
} // end of HAL_clearMtrFaultStatus() function

//! \brief      Enables the PWM devices for PFC
//! \details    Turns on the outputs of the EPWM peripheral which will allow
//!             the power switches to be controlled.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_enablePFCPWM(HAL_PFC_Handle handle)  // f280013x
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    // Clear any comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    // Clear any comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    // Clear any comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // BSXL8323RH_REVB
#else
#error Not select a right board to clear the fault trip flag for motors
#endif  // No Hardware Boards

    // Clear any Trip Zone flag
    EPWM_clearTripZoneFlag(obj->pwmHandle, HAL_TZFLAG_INTERRUPT_ALL);

#if defined(ILPFC_DCH_EN)
    // setup the Action-qualifier Continuous Software Force Register
    // (AQCSFRC)
    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_A,
                                             EPWM_AQ_SW_DISABLED);

    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_B,
                                             EPWM_AQ_SW_DISABLED);
#elif defined(SPPFC_CHA_EN)
    // setup the Action-qualifier Continuous Software Force Register
    // (AQCSFRC)
    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_A,
                                             EPWM_AQ_SW_DISABLED);

    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_B,
                                             EPWM_AQ_SW_OUTPUT_LOW);
#elif defined(SPPFC_CHB_EN)
    // setup the Action-qualifier Continuous Software Force Register
    // (AQCSFRC)
    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_A,
                                             EPWM_AQ_SW_OUTPUT_LOW);

    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_B,
                                             EPWM_AQ_SW_DISABLED);
#endif

    obj->flagEnablePWM = true;

    return;
} // end of HAL_enablePFCPWM() function

//! \brief      Enables the PWM devices for PFC
//! \details    Turns on the outputs of the EPWM peripheral which will allow
//!             the power switches to be controlled.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_enablePFCILPWM(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

    // setup the Action-qualifier Continuous Software Force Register
    // (AQCSFRC)
    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_B,
                                             EPWM_AQ_SW_DISABLED);

    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_A,
                                             EPWM_AQ_SW_DISABLED);
    return;
} // end of HAL_enablePFCILPWM() function

//! \brief      Disable Channel A for using single phase PFC
//! \details    Turns off channel A
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_disableILPFCPowerChA(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

    // setup the Action-qualifier Continuous Software Force Register
    // (AQCSFRC)
    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_A,
                                             EPWM_AQ_SW_OUTPUT_LOW);
    return;
} // end of HAL_disableILPFCPowerChA() function

//! \brief      Disable Channel B for using single phase PFC
//! \details    Turns off channel B
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_disableILPFCPowerChB(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

    // setup the Action-qualifier Continuous Software Force Register
    // (AQCSFRC)
    EPWM_setActionQualifierContSWForceAction(obj->pwmHandle,
                                             EPWM_AQ_OUTPUT_B,
                                             EPWM_AQ_SW_OUTPUT_LOW);
    return;
} // end of HAL_disableILPFCPowerChB() function


//! \brief      clear fault status of PFC
//! \details
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_clearPFCFaultStatus(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    // Clear any comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    // Clear any comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    // Clear any comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // BSXL8323RH_REVB
#else
#error Not select a right board to clear fault trip flag for PFC
#endif  // No Hardware Boards

    // Clear any Trip Zone flag
    EPWM_clearTripZoneFlag(obj->pwmHandle, HAL_TZFLAG_INTERRUPT_ALL);

    return;
} // end of HAL_clearPFCFaultStatus() function

//! \brief      Disables the PWM device for motor control
//! \details    Turns off the outputs of the EPWM peripherals which will put
//!             the power switches into a high impedance state.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_disableMTRPWM(HAL_MTR_Handle handle)
{
  HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

  EPWM_forceTripZoneEvent(obj->pwmHandle[0], EPWM_TZ_FORCE_EVENT_OST);
  EPWM_forceTripZoneEvent(obj->pwmHandle[1], EPWM_TZ_FORCE_EVENT_OST);
  EPWM_forceTripZoneEvent(obj->pwmHandle[2], EPWM_TZ_FORCE_EVENT_OST);

  obj->flagEnablePWM = false;

  return;
} // end of HAL_disableMTRPWM() function

//! \brief      Disables the PWM device
//! \details    Turns off the outputs of the EPWM peripherals which will put
//!             the power switches into a high impedance state.
//! \param[in]  handle  The hardware abstraction layer (HAL) handle
static inline void HAL_disablePFCPWM(HAL_PFC_Handle handle)     // f280013x
{
  HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

  EPWM_forceTripZoneEvent(obj->pwmHandle, EPWM_TZ_FORCE_EVENT_OST);

  obj->flagEnablePWM = false;

  return;
} // end of HAL_disablePFCPWM() function

#if defined(MOTOR1_DCLINKSS) || defined(MOTOR2_DCLINKSS)
//! \brief     PWM phase shift and ADC SOC timing for dc_link current sensing
//! \details   PWM phase shift compensation based on each phase duty and min duration.
//!            dc_link current sampling point is calcuated with shifted PWM compare value.
//! \param[in] handle       The hardware abstraction layer (HAL) handle
//! \param[in] dclinkHandle The dclink handle
//! \param[in] pVab_out     The pointer to the Vab voltage
//! \param[in] pPWMData     The pointer to the PWM data
static inline void
HAL_runSingleShuntCompensation(HAL_MTR_Handle handle,
                               DCLINK_SS_Handle dclinkHandle,
                               const MATH_vec2 *pVab_out,
                               HAL_PWMData_t *pPWMData, const float32_t Vdc_V)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

    MATH_ui_vec2 upSoc, downSoc;
    MATH_ui_vec3 pwmCMPA, pwmCMPB;

    // get EPWMx CMPA/CMPB values
    pwmCMPA.value[0] = pwmCMPB.value[0] = pPWMData->cmpValue[0];
    pwmCMPA.value[1] = pwmCMPB.value[1] = pPWMData->cmpValue[1];
    pwmCMPA.value[2] = pwmCMPB.value[2] = pPWMData->cmpValue[2];

    // run PWM compensation for single-shunt
    DCLINK_SS_runPWMCompensation(dclinkHandle, pVab_out, Vdc_V,
                              &pwmCMPA, &pwmCMPB, &upSoc, &downSoc);

#if(DMC_BUILDLEVEL >= DMC_LEVEL_2)
    uint16_t pwmCnt;

    for(pwmCnt=0; pwmCnt<3; pwmCnt++)
    {
        EPWM_setCounterCompareValue(obj->pwmHandle[pwmCnt],
                                    EPWM_COUNTER_COMPARE_A,
                                    pwmCMPA.value[pwmCnt]);

        EPWM_setCounterCompareValue(obj->pwmHandle[pwmCnt],
                                    EPWM_COUNTER_COMPARE_B,
                                    pwmCMPB.value[pwmCnt]);
    }
#endif // (DMC_BUILDLEVEL == DMC_LEVEL_2)


    // set the SOC trigger point for UP count
    EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                EPWM_COUNTER_COMPARE_C,
                                upSoc.value[0]);

    EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                EPWM_COUNTER_COMPARE_D,
                                upSoc.value[1]);

    // set the SOC trigger point for DOWN count
    EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                EPWM_COUNTER_COMPARE_C,
                                downSoc.value[0]);

    EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                EPWM_COUNTER_COMPARE_D,
                                downSoc.value[1]);


    return;
} // end of HAL_runSingleShuntCompensation() function

//! \brief     Set trigger point near period for dc-link current offset
//! \param[in] handle       The hardware abstraction layer (HAL) handle
static inline void HAL_setOffsetTrigger(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;
    uint16_t pwmPRD = HAL_getTimeBasePeriod(handle);
    uint16_t offsetUpSoc = pwmPRD*(3.0f/4.0f);
    uint16_t offsetDownSoc = pwmPRD*(1.0f/4.0f);

    //
    // set the SOC trigger point for UP count
    //
    EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                EPWM_COUNTER_COMPARE_C,
                                offsetUpSoc);

    EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                EPWM_COUNTER_COMPARE_D,
                                offsetUpSoc);

    //
    // set the SOC trigger point for DOWN count
    //
    EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                EPWM_COUNTER_COMPARE_C,
                                offsetDownSoc);

    EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                EPWM_COUNTER_COMPARE_D,
                                offsetDownSoc);

    return;
} // end of HAL_setOffsetTrigger() function
#endif  //MOTOR1_DCLINKSS || (MOTOR2_DCLINKSS

//! \brief     Sets up the PWMs (Pulse Width Modulators)
//! \param[in] handle          The hardware abstraction layer (HAL) handle
//! \param[in] systemFreq_MHz  The system frequency, MHz
//! \param[in] pwmPeriod_usec  The PWM period, usec
//! \param[in] numPWMTicksPerISRTick  The number of PWM clock ticks per ISR clock tick
extern void HAL_setupPWMsMTR(HAL_MTR_Handle handle);

//! \brief     Sets up the PWMs (Pulse Width Modulators)
//! \param[in] handle          The hardware abstraction layer (HAL) handle
//! \param[in] systemFreq_MHz  The system frequency, MHz
//! \param[in] pwmPeriod_usec  The PWM period, usec
//! \param[in] numPWMTicksPerISRTick  The number of PWM clock ticks per ISR clock tick
extern void HAL_setupPWMsPFC(HAL_PFC_Handle handle);

//! \brief     Sets up the PWMs (Pulse Width Modulators)
//! \param[in] handle          The hardware abstraction layer (HAL) handle
extern void HAL_setupPWMsPhaseShift(HAL_Handle handle);

static inline uint16_t HAL_getMtrTripFaults(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;
    uint16_t tripFault = 0;

    tripFault = ((EPWM_getTripZoneFlagStatus(obj->pwmHandle[0]) &
                        (EPWM_TZ_FLAG_OST | EPWM_TZ_FLAG_DCAEVT1)) |
                 (EPWM_getTripZoneFlagStatus(obj->pwmHandle[1]) &
                        (EPWM_TZ_FLAG_OST | EPWM_TZ_FLAG_DCAEVT1)) |
                 (EPWM_getTripZoneFlagStatus(obj->pwmHandle[2]) &
                        (EPWM_TZ_FLAG_OST | EPWM_TZ_FLAG_DCAEVT1)) );

    return(tripFault);
}

static inline uint16_t HAL_getPFCTripFaults(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;
    uint16_t tripFault = 0;

    tripFault = (EPWM_getTripZoneFlagStatus(obj->pwmHandle) & PFC_TZ_FLAG);

    return(tripFault);
}


static inline void HAL_enableMtr1NestInterrupt(void)
{
    // save IER register on stack
    mtr1PIEIER = HWREGH(PIECTRL_BASE + MTR1_PIE_O_IER);

    // set the global and group priority to allow CPU interrupts
    // with higher priority
    IER |= PFC_CPU_INT_NUM;
    IER &= PFC_CPU_INT_NUM;

    HWREGH(PIECTRL_BASE + PFC_PIE_O_IER)  |= PFC_PIE_IER_INT;

    // enable Interrupts
    Interrupt_clearACKGroup(0xFFFFU);

    __asm("  NOP");

    // enable interrupts
    EINT;

}

static inline void HAL_resetMtr1NestInterrupt(void)
{
    // disable interrupts
    DINT;

    __asm("  NOP");

    // restore registers saved:
    HWREGH(PIECTRL_BASE + MTR1_PIE_O_IER) = mtr1PIEIER;
}


static inline void HAL_enableMtr2NestInterrupt(void)
{
    // save IER register on stack
    mtr2PIEIER = HWREGH(PIECTRL_BASE + MTR2_PIE_O_IER);

    // set the global and group priority to allow CPU interrupts
    // with higher priority
    IER |= PFC_CPU_INT_NUM;
    IER &= PFC_CPU_INT_NUM;

    HWREGH(PIECTRL_BASE + PFC_PIE_O_IER)  |= PFC_PIE_IER_INT;

    // enable Interrupts
    Interrupt_clearACKGroup(0xFFFFU);

    __asm("  NOP");

    // enable interrupts
    EINT;

}

static inline void HAL_resetMtr2NestInterrupt(void)
{
    // disable interrupts
    DINT;

    __asm("  NOP");

    // restore registers saved:
    HWREGH(PIECTRL_BASE + MTR2_PIE_O_IER) = mtr2PIEIER;
}

extern void HAL_setMtrCMPSSDACValue(HAL_MTR_Handle handle,
                               const uint16_t dacValH, const uint16_t dacValL);

extern void HAL_setPFCCMPSSDACValue(HAL_PFC_Handle handle,
                               const uint16_t dacValH, const uint16_t dacValL);

//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif // extern "C"

#endif // end of HAL_H definition

