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//! \file   solutions/tidm_02010_dmpfc/f280013x/drivers/hal.c
//! \brief  Contains the various functions related to the HAL object
//!


//
// the includes
//
#include "user.h"

#if defined(SYSCONFIG_EN)
#include "board.h"
#endif  // SYSCONFIG_EN

//
// drivers
//

// modules

// platforms
#include "hal.h"            // for f280013x
#include "hal_obj.h"        // for f280013x

// libraries
#include "datalogIF.h"

#ifdef _FLASH
#pragma CODE_SECTION(Flash_initModule, ".TI.ramfunc");
#endif

// **************************************************************************
// the defines


// **************************************************************************
// the globals


// **************************************************************************
// the functions
void HAL_cal(HAL_Handle handle)
{
    SysCtl_deviceCal();

    // Lock VREGCTL Register
    // The register VREGCTL is not supported in this device. It is locked to
    // prevent any writes to this register
    ASysCtl_lockVREG();

    return;
} // end of HAL_cal() function

void HAL_disableGlobalInts(HAL_Handle handle)
{
    // disable global interrupts
    Interrupt_disableMaster();

    return;
} // end of HAL_disableGlobalInts() function

void HAL_disableWdog(HAL_Handle halHandle)
{
    // disable watchdog
    SysCtl_disableWatchdog();

    return;
} // end of HAL_disableWdog() function

#if !defined(SYSCONFIG_EN)
void HAL_enableCtrlInts(HAL_Handle handle)
{
#ifndef MOTOR1_DISABLE
#if !(defined(MOTOR1_DCLINKSS) & defined(MOTOR1_ESMO))
    // enable the ADC interrupts for motor_1
    ADC_enableInterrupt(MTR1_ADC_INT_BASE, MTR1_ADC_INT_NUM);
#endif  // MOTOR1_DCLINKSS && !MOTOR1_ESMO

    // enable the PIE interrupts associated with the ADC/PWM interrupts
    Interrupt_enable(MTR1_PIE_INT_NUM);    // motor_1
#endif  // !MOTOR1_DISABLE

#ifndef MOTOR2_DISABLE
#if !(defined(MOTOR2_DCLINKSS) & defined(MOTOR2_ESMO))
    // enable the ADC interrupts for motor_2
    ADC_enableInterrupt(MTR2_ADC_INT_BASE, MTR2_ADC_INT_NUM);
#endif  // MOTOR2_DCLINKSS && MOTOR2_ESMO

    // enable the PIE interrupts associated with the ADC/PWM interrupts
    Interrupt_enable(MTR2_PIE_INT_NUM);    // motor_2
#endif  // !MOTOR2_DISABLE

#ifndef PFC_DISABLE
    // Enable PWM Interrupt for PFC
    EPWM_enableInterrupt(PFC_PWM_BASE);

    // clear pending INT event
    EPWM_clearEventTriggerInterruptFlag(PFC_PWM_BASE);

    // enable the ADC interrupts for DMA
    ADC_enableInterrupt(PFC_DMA_ADC_INT_BASE, PFC_DMA_ADC_INT_NUM);

    // enable the ADC interrupts for FC
    ADC_enableInterrupt(PFC_ADC_INT_BASE, PFC_ADC_INT_NUM);

    // enable the PIE interrupts associated with the ADC/PWM interrupts
    Interrupt_enable(PFC_PIE_INT_NUM);     // PFC
#endif  // PFC_DISABLE

    return;
} // end of HAL_enableCtrlInts() function
#endif  // !SYSCONFIG_EN

// No HAL_enableADCIntsToTriggerCLA() in this device

void HAL_enableDebugInt(HAL_Handle handle)
{
    // enable debug events
    ERTM;

    return;
} // end of HAL_enableDebugInt() function

void HAL_enableGlobalInts(HAL_Handle handle)
{

    // enable global interrupts
    Interrupt_enableMaster();

    return;
} // end of HAL_enableGlobalInts() function


HAL_Handle HAL_init(void *pMemory,const size_t numBytes)
{
    HAL_Handle handle;
    HAL_Obj *obj;

    if(numBytes < sizeof(HAL_Obj))
    {
        return((HAL_Handle)NULL);
    }

    // assign the handle
    handle = (HAL_Handle)pMemory;

    // assign the object
    obj = (HAL_Obj *)handle;

    // disable watchdog
    SysCtl_disableWatchdog();

    // Two ADC modules in this device
    // initialize the ADC handles
    obj->adcHandle[0] = ADCA_BASE;
    obj->adcHandle[1] = ADCC_BASE;

    // initialize the ADC results
    obj->adcResult[0] = ADCARESULT_BASE;
    obj->adcResult[1] = ADCCRESULT_BASE;

    // No DAC modules in this device
    // Not use

    // No CLA module in this device
    // Not use

    // initialize SCIA/B/C handle
    obj->sciHandle[0] = SCIA_BASE;             //!< the SCIA handle
    obj->sciHandle[1] = SCIB_BASE;             //!< the SCIB handle
    obj->sciHandle[2] = SCIC_BASE;             //!< the SCIC handle

    // initialize LINA handle
    // No LIN module on f280013x

    // initialize I2CA handle
    obj->i2cHandle = I2CA_BASE;                //!< the I2C handle

    // initialize DMA handle
    // No DMA module on f280013x

    // initialize DMA channel handle
    // No DMA module on f280013x

    // initialize timer handles
    obj->timerHandle[0] = CPUTIMER0_BASE;   // 1ms Timer Base
    obj->timerHandle[1] = CPUTIMER1_BASE;   // PFC Current Trigger
    obj->timerHandle[2] = CPUTIMER2_BASE;   // CPU Bandwidth

#ifdef EPWMDAC_MODE
    // initialize pwmdac handles
    obj->pwmDACHandle[0] = EPWMDAC1_BASE;
    obj->pwmDACHandle[1] = EPWMDAC2_BASE;
    obj->pwmDACHandle[2] = EPWMDAC3_BASE;
    obj->pwmDACHandle[3] = EPWMDAC4_BASE;
#endif  // EPWMDAC_MODE

    return(handle);
} // end of HAL_init() function


HAL_MTR_Handle HAL_MTR_init(void *pMemory,
                            const size_t numBytes,
                            const MotorNum_e mtrNum)
{
    HAL_MTR_Handle handle;
    HAL_MTR_Obj *obj;

    if(numBytes < sizeof(HAL_MTR_Obj))
    {
        return((HAL_MTR_Handle)NULL);
    }

    // assign the handle
    handle = (HAL_MTR_Handle)pMemory;

    // assign the object
    obj = (HAL_MTR_Obj *)handle;

    if(mtrNum == MTR_1)
    {
        // initialize PWM handles for Motor 1
        obj->pwmHandle[0] = MTR1_PWM_U_BASE;        //!< the PWM handle
        obj->pwmHandle[1] = MTR1_PWM_V_BASE;        //!< the PWM handle
        obj->pwmHandle[2] = MTR1_PWM_W_BASE;        //!< the PWM handle

        // initialize CMPSS handle
#if defined(MOTOR1_DCLINKSS)    // Single-shunt
        obj->cmpssHandle[0] = MTR1_CMPSS_IDC_BASE;  //!< the CMPSS handle
#else   // !MOTOR1_DCLINKSS, Three-shunt
        obj->cmpssHandle[0] = MTR1_CMPSS_U_BASE;    //!< the CMPSS handle
        obj->cmpssHandle[1] = MTR1_CMPSS_V_BASE;    //!< the CMPSS handle
        obj->cmpssHandle[2] = MTR1_CMPSS_W_BASE;    //!< the CMPSS handle
#endif  // !MOTOR1_DCLINKSS

        // No PGA modules on this device

        #ifdef QEP_ENABLE
        // initialize QEP driver
        obj->qepHandle = MTR1_QEP_BASE;             //!< the QEP handle
        #endif  // QEP_ENABLE

        // initialize DMA channel handle
        // No DMA module on f280013x

#if defined(HVMTRPFC_REV1P1) || defined(BSXL8323RH_REVB)
        obj->gateEnableGPIO = MTR1_GATE_EN_GPIO;
#endif  // HVMTRPFC_REV1P1 | BSXL8323RH_REVB

        obj->motorNum = MTR_1;
    }
    else if(mtrNum == MTR_2)
    {
        // initialize PWM handles for Motor 2
        obj->pwmHandle[0] = MTR2_PWM_U_BASE;        //!< the PWM handle
        obj->pwmHandle[1] = MTR2_PWM_V_BASE;        //!< the PWM handle
        obj->pwmHandle[2] = MTR2_PWM_W_BASE;        //!< the PWM handle

        // initialize CMPSS handle
#if defined(MOTOR2_DCLINKSS)
        obj->cmpssHandle[0] = MTR2_CMPSS_IDC_BASE;  //!< the CMPSS handle
#else   // !MOTOR2_DCLINKSS, Three-shunt
        obj->cmpssHandle[0] = MTR2_CMPSS_U_BASE;    //!< the CMPSS handle
        obj->cmpssHandle[1] = MTR2_CMPSS_V_BASE;    //!< the CMPSS handle
        obj->cmpssHandle[2] = MTR2_CMPSS_W_BASE;    //!< the CMPSS handle
#endif  // !MOTOR2_DCLINKSS

        // No PGA modules on this device

        #ifdef QEP_ENABLE
        // initialize QEP driver
        obj->qepHandle = MTR2_QEP_BASE;             //!< the QEP handle
        #endif  // QEP_ENABLE

        // initialize DMA channel handle
        // No DMA module on f280013x

#if defined(HVMTRPFC_REV1P1) || defined(BSXL8323RH_REVB)
        obj->gateEnableGPIO = MTR2_GATE_EN_GPIO;
#endif  // HVMTRPFC_REV1P1 | BSXL8323RH_REVB

        obj->motorNum = MTR_2;
    }

     return(handle);
} // end of HAL_MTR_init() function


HAL_PFC_Handle HAL_PFC_init(void *pMemory, const size_t numBytes)
{
    HAL_PFC_Handle handle;
    HAL_PFC_Obj *obj;


    // assign the handle
    handle = (HAL_PFC_Handle)pMemory;

    // assign the object
    obj = (HAL_PFC_Obj *)handle;

    // initialize PWM handles for Motor 1
    obj->pwmHandle = PFC_PWM_BASE;         //!< the PWM handle

    // initialize CMPSS handle
#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    obj->cmpssHandle[0] = PFC_CMPSS_IAC_BASE;     //!< the CMPSS handle
    obj->cmpssHandle[1] = PFC_CMPSS_VDC_BASE;     //!< the CMPSS handle
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#else  // !DMCPFC_REV3P2 & !DMCPFC_REV3P1
    obj->cmpssHandle[0] = PFC_CMPSS_IAC_BASE;     //!< the CMPSS handle
#endif  // !DMCPFC_REV3P2 & !DMCPFC_REV3P1

    // No PGA module on this device

    // initialize DMA channel handle
    // No DMA module on f280013x

     return(handle);
} // end of HAL_PFC_init() function

void HAL_initMtrHandle(HAL_Handle handle, HAL_MTR_Handle mtr1Handle,
                     HAL_MTR_Handle mtr2Handle)
{
    HAL_Obj *obj = (HAL_Obj *)handle;

    obj->mtrHandle[0] = mtr1Handle;
    obj->mtrHandle[1] = mtr2Handle;

    return;
}

void HAL_initPFCHandle(HAL_Handle handle, HAL_PFC_Handle pfcHandle)
{
    HAL_Obj *obj = (HAL_Obj *)handle;

    obj->pfcHandle = pfcHandle;

    return;
}

void HAL_setParams(HAL_Handle handle)
{
#ifdef _FLASH
    //
    // Copy time critical code and flash setup code to RAM. This includes the
    // following functions: InitFlash();
    //
    // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols
    // are created by the linker. Refer to the device .cmd file.
    //
    memcpy(&runStart_ctrlfuncs, &loadStart_ctrlfuncs, (size_t)&loadSize_ctrlfuncs);
#endif  // _FLASH

    // disable the ePWM module time base clock sync signal
    // to synchronize all of the PWMs
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

#if defined(SYSCONFIG_EN)

#if defined(EPWMDAC_MODE)
    // setup the PWM DACs
    HAL_setupPWMDACs(handle, USER_SYSTEM_FREQ_MHz);
#endif  //EPWMDAC_MODE

#else

#if defined(EPWMDAC_MODE)
    // setup the PWM DACs
    HAL_setupPWMDACs(handle, USER_SYSTEM_FREQ_MHz);
#endif  //EPWMDAC_MODE

    // setup the GPIOs
    HAL_setupGPIOs(handle);

    // setup the SCIA for PC/Monitor communication
    HAL_setupSCIA(handle);

    // setup the SCIB for system communication
    HAL_setupSCIB(handle);

    // setup the LINA for system communication
    // No LIN module on f280013x

    // setup the I2CA for EEPROM
    HAL_setupI2CA(handle);

    // Sets up the CPU timer for time base
    HAL_setupTimeBaseTimer(handle, USER_TIME_BASE_FREQ_Hz);

    // Sets up the CPU timer for ADC trigger
    HAL_setupADCTriggerTimer(handle, USER_PFC_ADC_TIMER_FREQ_HZ);

    // Sets up the timers for CPU usage diagnostics
    HAL_setupCPUUsageTimer(handle);

    // setup the DMA
    // No DMA module on f280013x

    // setup the ADCs
    HAL_setupADCs(handle);

#endif  // SYSCONFIG_EN

    return;
} // end of HAL_setParams() function

void HAL_MTR_setParams(HAL_MTR_Handle handle, USER_Params *pUserParams)
{
    HAL_setNumCurrentSensors(handle, pUserParams->numCurrentSensors);
    HAL_setNumVoltageSensors(handle, pUserParams->numVoltageSensors);

#if defined(SYSCONFIG_EN)
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

    if(obj->motorNum == MTR_1)
    {
        EPWM_setTimeBasePeriod(obj->pwmHandle[0], USER_M1_PWM_TBPRD_NUM);
        EPWM_setTimeBasePeriod(obj->pwmHandle[1], USER_M1_PWM_TBPRD_NUM);
        EPWM_setTimeBasePeriod(obj->pwmHandle[2], USER_M1_PWM_TBPRD_NUM);
    }
    else
    {
        EPWM_setTimeBasePeriod(obj->pwmHandle[0], USER_M2_PWM_TBPRD_NUM);
        EPWM_setTimeBasePeriod(obj->pwmHandle[1], USER_M2_PWM_TBPRD_NUM);
        EPWM_setTimeBasePeriod(obj->pwmHandle[2], USER_M2_PWM_TBPRD_NUM);
    }
#else
    // setup the PWMs
    HAL_setupPWMsMTR(handle);

    // setup the CMPSSs
    HAL_setupCMPSSsMTR(handle);

    // setup faults
    HAL_setupMtrFaults(handle);
#endif  // SYSCONFIG_EN

#if defined(QEP_ENABLE) && !defined(SYSCONFIG_EN)
    // setup the EQEP
    HAL_setupQEP(handle);
#endif  // QEP_ENABLE &!SYSCONFIG_EN

    return;
} // end of HAL_MTR_setParams() function

void HAL_PFC_setParams(HAL_PFC_Handle handle)
{
#if defined(SYSCONFIG_EN)
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

    EPWM_setTimeBasePeriod(obj->pwmHandle, USER_PFC_PWM_TBPRD_NUM);
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_A,
                                USER_PFC_PWM_TBPRD_NUM);

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_B,
                                0);
#else
    // setup the PWMs
    HAL_setupPWMsPFC(handle);

    // setup the CMPSSs
    HAL_setupCMPSSsPFC(handle);

    // setup faults
    HAL_setupPFCFaults(handle);
#endif  // SYSCONFIG_EN

    return;
} // end of HAL_PFC_setParams() function

#if !defined(SYSCONFIG_EN)
void HAL_setupADCs(HAL_Handle handle)
{
    HAL_Obj *obj = (HAL_Obj *)handle;

    SysCtl_delay(100U);

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    ADC_setVREF(obj->adcHandle[0], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(obj->adcHandle[1], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1) || defined(BSXL8323RH_REVB)
    ADC_setVREF(obj->adcHandle[0], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    ADC_setVREF(obj->adcHandle[1], ADC_REFERENCE_INTERNAL, ADC_REFERENCE_3_3V);
    // HVMTRPFC_REV1P1 || BSXL8323RH_REVB
#else
#error Not select a right board to set ADC reference voltage
#endif

    SysCtl_delay(100U);

    // Set main clock scaling factor (50MHz max clock for the ADC module)
    ADC_setPrescaler(obj->adcHandle[0], ADC_CLK_DIV_2_0);
    ADC_setPrescaler(obj->adcHandle[1], ADC_CLK_DIV_2_0);

    // set the ADC interrupt pulse generation to end of conversion
    ADC_setInterruptPulseMode(obj->adcHandle[0], ADC_PULSE_END_OF_CONV);
    ADC_setInterruptPulseMode(obj->adcHandle[1], ADC_PULSE_END_OF_CONV);

    // set priority of SOCs
    ADC_setSOCPriority(obj->adcHandle[0], ADC_PRI_THRU_SOC5_HIPRI);
    ADC_setSOCPriority(obj->adcHandle[1], ADC_PRI_THRU_SOC7_HIPRI);

    // enable the ADCs
    ADC_enableConverter(obj->adcHandle[0]);
    ADC_enableConverter(obj->adcHandle[1]);

    // delay to allow ADCs to power up
    SysCtl_delay(1000U);

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1) || defined(BSXL8323RH_REVB)
    //-------------------------------------------------------------------------
#ifndef PFC_DISABLE
    // ADC for PFC
    // interrupt for PFC
    ADC_setInterruptSource(PFC_ADC_INT_BASE,
                           PFC_ADC_INT_NUM, PFC_ADC_INT_SOC);

    // ISEN_AC, IAC1
    ADC_setupSOC(PFC_IAC_ADC_BASE, PFC_IAC1_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS1,
                 PFC_IAC_ADC_CH_NUM, PFC_I_ADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_IAC_ADC_BASE, PFC_IAC1_ADC_PPB_NUM, PFC_IAC1_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_IAC_ADC_BASE, PFC_IAC1_ADC_PPB_NUM, 0);

    // ISEN_AC, IAC2
    ADC_setupSOC(PFC_IAC_ADC_BASE, PFC_IAC2_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS2,
                 PFC_IAC_ADC_CH_NUM, PFC_I_ADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_IAC_ADC_BASE, PFC_IAC2_ADC_PPB_NUM, PFC_IAC2_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_IAC_ADC_BASE, PFC_IAC2_ADC_PPB_NUM, 0);

    // VSEN_ACBUS, VAC1->PPB
    ADC_setupSOC(PFC_VAC_ADC_BASE, PFC_VAC1_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS1,
                 PFC_VAC_ADC_CH_NUM, PFC_V_ADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_VAC_ADC_BASE, PFC_VAC1_ADC_PPB_NUM, PFC_VAC1_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_VAC_ADC_BASE, PFC_VAC1_ADC_PPB_NUM, 0);

    // VSEN_ACBUS, VAC2->PPB
    ADC_setupSOC(PFC_VAC_ADC_BASE, PFC_VAC2_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS2,
                 PFC_VAC_ADC_CH_NUM, PFC_V_ADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_VAC_ADC_BASE, PFC_VAC2_ADC_PPB_NUM, PFC_VAC2_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_VAC_ADC_BASE, PFC_VAC2_ADC_PPB_NUM, 0);

    // VSEN_DCBUS, VDC1
    ADC_setupSOC(PFC_VDC_ADC_BASE, PFC_VDC1_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS1,
                 PFC_VDC_ADC_CH_NUM, PFC_V_ADC_SAMPLE_WINDOW);

    // VSEN_DCBUS, VDC2
    ADC_setupSOC(PFC_VDC_ADC_BASE, PFC_VDC2_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS2,
                 PFC_VDC_ADC_CH_NUM, PFC_V_ADC_SAMPLE_WINDOW);
#endif  // PFC_DISABLE

#ifndef MOTOR1_DISABLE
    //-------------------------------------------------------------------------
    // ADC for motor_1
    // configure the interrupt sources for motor 1
#if !defined(MOTOR1_DCLINKSS) || defined(MOTOR1_FAST)
    ADC_setInterruptSource(MTR1_ADC_INT_BASE,
                           MTR1_ADC_INT_NUM, MTR1_ADC_INT_SOC);
#endif  // !MOTOR1_DCLINKSS || MOTOR1_FAST

    // configure the SOCs for M1
#if defined(MOTOR1_DCLINKSS)
    // Idc 1st
    ADC_setupSOC(MTR1_IDC1_ADC_BASE, MTR1_IDC1_ADC_SOC_NUM, MTR1_IDC1_TRIGGER_SOC,
                 MTR1_IDC1_ADC_CH_NUM, MTR1_I_ADC_SAMPLE_WINDOW);

    // Idc 2nd
    ADC_setupSOC(MTR1_IDC2_ADC_BASE, MTR1_IDC2_ADC_SOC_NUM, MTR1_IDC2_TRIGGER_SOC,
                 MTR1_IDC2_ADC_CH_NUM, MTR1_I_ADC_SAMPLE_WINDOW);

    // Idc 3rd
    ADC_setupSOC(MTR1_IDC3_ADC_BASE, MTR1_IDC3_ADC_SOC_NUM, MTR1_IDC3_TRIGGER_SOC,
                 MTR1_IDC3_ADC_CH_NUM, MTR1_I_ADC_SAMPLE_WINDOW);

    // Idc 4th
    ADC_setupSOC(MTR1_IDC4_ADC_BASE, MTR1_IDC4_ADC_SOC_NUM, MTR1_IDC4_TRIGGER_SOC,
                 MTR1_IDC4_ADC_CH_NUM, MTR1_I_ADC_SAMPLE_WINDOW);

#else  // !MOTOR1_DCLINKSS
    // ISEN_A_M1
    ADC_setupSOC(MTR1_IU_ADC_BASE, MTR1_IU_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_IU_ADC_CH_NUM, MTR1_I_ADC_SAMPLE_WINDOW);

    // ISEN_B_M1
    ADC_setupSOC(MTR1_IV_ADC_BASE, MTR1_IV_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_IV_ADC_CH_NUM, MTR1_I_ADC_SAMPLE_WINDOW);

    // ISEN_C_M1
    ADC_setupSOC(MTR1_IW_ADC_BASE, MTR1_IW_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_IW_ADC_CH_NUM, MTR1_I_ADC_SAMPLE_WINDOW);
#endif  // !MOTOR1_DCLINKSS

#if defined(MOTOR1_FAST)
    // VSEN_A_M1
    ADC_setupSOC(MTR1_VU_ADC_BASE, MTR1_VU_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VU_ADC_CH_NUM, MTR1_V_ADC_SAMPLE_WINDOW);

    // VSEN_B_M1
    ADC_setupSOC(MTR1_VV_ADC_BASE, MTR1_VV_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VV_ADC_CH_NUM, MTR1_V_ADC_SAMPLE_WINDOW);

    // VSEN_C_M1 - C2*->RC1-->Trig Interrupt
    ADC_setupSOC(MTR1_VW_ADC_BASE, MTR1_VW_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VW_ADC_CH_NUM, MTR1_V_ADC_SAMPLE_WINDOW);
#endif  // MOTOR1_FAST

#if defined(PFC_DISABLE)
    // VDC
    ADC_setupSOC(MTR1_VDC_ADC_BASE, MTR1_VDC_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VDC_ADC_CH_NUM, MTR1_V_ADC_SAMPLE_WINDOW);
#endif  // PFC_DISABLE && HVMTRPFC_REV1P1
#endif  // !MOTOR1_DISABLE

#ifndef MOTOR2_DISABLE
    //--------------------------------------------------------------------------
    // ADC for motor_2
    // configure the interrupt sources for motor 2
#if !defined(MOTOR2_DCLINKSS) || defined(MOTOR2_FAST)
    ADC_setInterruptSource(MTR2_ADC_INT_BASE,
                           MTR2_ADC_INT_NUM, MTR2_ADC_INT_SOC);
#endif  // !MOTOR2_DCLINKSS || MOTOR2_FAST

    // configure the SOCs for M2
#if defined(MOTOR2_DCLINKSS)        // N/A
    //## Idc1 1st
    ADC_setupSOC(MTR2_IDC1_ADC_BASE, MTR2_IDC1_ADC_SOC_NUM, MTR2_IDC1_TRIGGER_SOC,
                 MTR2_IDC1_ADC_CH_NUM, MTR2_I_ADC_SAMPLE_WINDOW);

    //## Idc2 2nd
    ADC_setupSOC(MTR2_IDC2_ADC_BASE, MTR2_IDC2_ADC_SOC_NUM, MTR2_IDC2_TRIGGER_SOC,
                 MTR2_IDC2_ADC_CH_NUM, MTR2_I_ADC_SAMPLE_WINDOW);

    //## Idc1 3rd
    ADC_setupSOC(MTR2_IDC3_ADC_BASE, MTR2_IDC3_ADC_SOC_NUM, MTR2_IDC3_TRIGGER_SOC,
                 MTR2_IDC3_ADC_CH_NUM, MTR2_I_ADC_SAMPLE_WINDOW);

    //## Idc2 4th
    ADC_setupSOC(MTR2_IDC4_ADC_BASE, MTR2_IDC4_ADC_SOC_NUM, MTR2_IDC4_TRIGGER_SOC,
                 MTR2_IDC4_ADC_CH_NUM, MTR2_I_ADC_SAMPLE_WINDOW);

#else // !MOTOR2_DCLINKSS
    // ISEN_A_M2
    ADC_setupSOC(MTR2_IU_ADC_BASE, MTR2_IU_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_IU_ADC_CH_NUM, MTR2_I_ADC_SAMPLE_WINDOW);

    // ISEN_B_M2
    ADC_setupSOC(MTR2_IV_ADC_BASE, MTR2_IV_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_IV_ADC_CH_NUM, MTR2_I_ADC_SAMPLE_WINDOW);

    // ISEN_C_M2
    ADC_setupSOC(MTR2_IW_ADC_BASE, MTR2_IW_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_IW_ADC_CH_NUM, MTR2_I_ADC_SAMPLE_WINDOW);
#endif  // !MOTOR2_DCLINKSS

#if defined(MOTOR2_FAST)
    // VSEN_A_M2
    ADC_setupSOC(MTR2_VU_ADC_BASE, MTR2_VU_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_VU_ADC_CH_NUM, MTR2_V_ADC_SAMPLE_WINDOW);

    // VSEN_B_M2
    ADC_setupSOC(MTR2_VV_ADC_BASE, MTR2_VV_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_VV_ADC_CH_NUM, MTR2_V_ADC_SAMPLE_WINDOW);

    // VSEN_C_M2
    ADC_setupSOC(MTR2_VW_ADC_BASE, MTR2_VW_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_VW_ADC_CH_NUM, MTR2_V_ADC_SAMPLE_WINDOW);
#endif  // MOTOR2_FAST

#if defined(PFC_DISABLE) && defined(MOTOR1_DISABLE)
    // VDC
    ADC_setupSOC(MTR2_VDC_ADC_BASE, MTR2_VDC_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_VDC_ADC_CH_NUM, MTR2_V_ADC_SAMPLE_WINDOW);
#endif  // PFC_DISABLE
#endif  // !MOTOR2_DISABLE
    // DMCPFC_REV3P2 | DMCPFC_REV3P1 | BSXL8323RH_REVB

#elif defined(HVMTRPFC_REV1P1)
    //-------------------------------------------------------------------------
    // ADC for PFC
    // interrupt for PFC
    ADC_setInterruptSource(PFC_ADC_INT_BASE,
                           PFC_ADC_INT_NUM, PFC_ADC_INT_SOC);

    // ISEN_AC, IAC1
    ADC_setupSOC(PFC_IAC_ADC_BASE, PFC_IAC1_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS1,
                 PFC_IAC_ADC_CH_NUM, PFC_IADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_IAC_ADC_BASE, PFC_IAC1_ADC_PPB_NUM, PFC_IAC1_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_IAC_ADC_BASE, PFC_IAC1_ADC_PPB_NUM, 0);

    // ISEN_AC, IAC2
    ADC_setupSOC(PFC_IAC_ADC_BASE, PFC_IAC2_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS2,
                 PFC_IAC_ADC_CH_NUM, PFC_IADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_IAC_ADC_BASE, PFC_IAC2_ADC_PPB_NUM, PFC_IAC2_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_IAC_ADC_BASE, PFC_IAC2_ADC_PPB_NUM, 0);

    // VSEN_ACBUS, VAL1
    ADC_setupSOC(PFC_VAC_ADC_BASE, PFC_VAC1_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS1,
                 PFC_VAC_ADC_CH_NUM, PFC_VADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_VAC_ADC_BASE, PFC_VAC1_ADC_PPB_NUM, PFC_VAC1_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_VAC_ADC_BASE, PFC_VAC1_ADC_PPB_NUM, 0);

    // VSEN_ACBUS, VAL2
    ADC_setupSOC(PFC_VAC_ADC_BASE, PFC_VAC2_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS2,
                 PFC_VAC_ADC_CH_NUM, PFC_VADC_SAMPLE_WINDOW);

    // Configure PPB to eliminate subtraction related calculation
    // PPB is associated with ADCA_SOC
    ADC_setupPPB(PFC_VAC_ADC_BASE, PFC_VAC2_ADC_PPB_NUM, PFC_VAC2_ADC_SOC_NUM);

    // Write zero to this for now till offset calibration complete
    ADC_setPPBCalibrationOffset(PFC_VAC_ADC_BASE, PFC_VAC2_ADC_PPB_NUM, 0);

    // VSEN_ACBUS, VAN1
    ADC_setupSOC(PFC_VAN_ADC_BASE, PFC_VAN1_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS1,
                 PFC_VAN_ADC_CH_NUM, PFC_VADC_SAMPLE_WINDOW);

    // VSEN_ACBUS, VAN2
    ADC_setupSOC(PFC_VAN_ADC_BASE, PFC_VAN2_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS2,
                 PFC_VAN_ADC_CH_NUM, PFC_VADC_SAMPLE_WINDOW);

    // VSEN_DCBUS, VDC1
    ADC_setupSOC(PFC_VDC_ADC_BASE, PFC_VDC1_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS1,
                 PFC_VDC_ADC_CH_NUM, PFC_VADC_SAMPLE_WINDOW);

    // VSEN_DCBUS, VDC2
    ADC_setupSOC(PFC_VDC_ADC_BASE, PFC_VDC2_ADC_SOC_NUM, PFC_ADC_TRIGGER_VIS2,
                 PFC_VDC_ADC_CH_NUM, PFC_VADC_SAMPLE_WINDOW);

    //-------------------------------------------------------------------------
    // ADC for motor_1
    // configure the interrupt sources for motor 1
    ADC_setInterruptSource(MTR1_ADC_INT_BASE,
                           MTR1_ADC_INT_NUM, MTR1_ADC_INT_SOC);

    // configure the SOCs for M1
    // ISEN_A_M1
    ADC_setupSOC(MTR1_IU_ADC_BASE, MTR1_IU_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_IU_ADC_CH_NUM, MTR1_ADC_SAMPLE_WINDOW);

    // ISEN_B_M1
    ADC_setupSOC(MTR1_IV_ADC_BASE, MTR1_IV_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_IV_ADC_CH_NUM, MTR1_ADC_SAMPLE_WINDOW);

    // ISEN_C_M1
    ADC_setupSOC(MTR1_IW_ADC_BASE, MTR1_IW_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_IW_ADC_CH_NUM, MTR1_ADC_SAMPLE_WINDOW);

#if defined(MOTOR1_FAST)
    // VSEN_A_M1
    ADC_setupSOC(MTR1_VU_ADC_BASE, MTR1_VU_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VU_ADC_CH_NUM, MTR1_ADC_SAMPLE_WINDOW);

    // VSEN_B_M1
    ADC_setupSOC(MTR1_VV_ADC_BASE, MTR1_VV_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VV_ADC_CH_NUM, MTR1_ADC_SAMPLE_WINDOW);

    // VSEN_C_M1 - C2*->RC1-->Trig Interrupt
    ADC_setupSOC(MTR1_VW_ADC_BASE, MTR1_VW_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VW_ADC_CH_NUM, MTR1_ADC_SAMPLE_WINDOW);
#endif  // MOTOR1_FAST

#if defined(PFC_DISABLE) && defined(HVMTRPFC_REV1P1)
    // VDC
    ADC_setupSOC(MTR1_VDC_ADC_BASE, MTR1_VDC_ADC_SOC_NUM, MTR1_ADC_TRIGGER_SOC,
                 MTR1_VDC_ADC_CH_NUM, MTR1_ADC_SAMPLE_WINDOW);
#endif  // PFC_DISABLE && HVMTRPFC_REV1P1

    //--------------------------------------------------------------------------
    // Interrupt for motor 2
    ADC_setInterruptSource(MTR2_ADC_INT_BASE,
                           MTR2_ADC_INT_NUM, MTR2_ADC_INT_SOC);

    // configure the SOCs for M2
    // ISEN_A_M2
    ADC_setupSOC(MTR2_IU_ADC_BASE, MTR2_IU_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_IU_ADC_CH_NUM, MTR2_ADC_SAMPLE_WINDOW);

    // ISEN_B_M2
    ADC_setupSOC(MTR2_IV_ADC_BASE, MTR2_IV_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_IV_ADC_CH_NUM, MTR2_ADC_SAMPLE_WINDOW);

    // ISEN_C_M2
    ADC_setupSOC(MTR2_IW_ADC_BASE, MTR2_IW_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_IW_ADC_CH_NUM, MTR2_ADC_SAMPLE_WINDOW);

#if defined(MOTOR2_FAST)
    // VSEN_A_M2
    ADC_setupSOC(MTR2_VU_ADC_BASE, MTR2_VU_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_VU_ADC_CH_NUM, MTR2_ADC_SAMPLE_WINDOW);

    // VSEN_B_M2
    ADC_setupSOC(MTR2_VV_ADC_BASE, MTR2_VV_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_VV_ADC_CH_NUM, MTR2_ADC_SAMPLE_WINDOW);

    // VSEN_C_M2
    ADC_setupSOC(MTR2_VW_ADC_BASE, MTR2_VW_ADC_SOC_NUM, MTR2_ADC_TRIGGER_SOC,
                 MTR2_VW_ADC_CH_NUM, MTR2_ADC_SAMPLE_WINDOW);
    // HVMTRPFC_REV1P1
#endif  // MOTOR2_FAST

#else   // No Hardware Boards
#error Not select a right board to clear the fault trip flag for motors
#endif  // No Hardware Boards

    return;
} // end of HAL_setupADCs() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
// HAL_setupCMPSSsMTR
void HAL_setupCMPSSsMTR(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
#if !defined(MOTOR1_DCLINKSS) || !defined(MOTOR2_DCLINKSS)
    uint16_t cmpsaDACH;
#endif  // !(MOTOR1_DCLINKSS || MOTOR2_DCLINKSS)
    uint16_t cmpsaDACL;

    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        cmpsaDACL = MTR1_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPLPMux(MTR1_IDC_CMPLP_SEL, MTR1_IDC_CMPLP_MUX);

        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH/L and CTRIPOUTH/L will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[0],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[0], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                    CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[0], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS, Three-shunt
        cmpsaDACH = MTR1_CMPSS_DACH_VALUE;
        cmpsaDACL = MTR1_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPHPMux(MTR1_IU_CMPHP_SEL, MTR1_IU_CMPHP_MUX);

        ASysCtl_selectCMPHPMux(MTR1_IV_CMPHP_SEL, MTR1_IV_CMPHP_MUX);

        ASysCtl_selectCMPLPMux(MTR1_IW_CMPLP_SEL, MTR1_IW_CMPLP_MUX);

        // ------- U Phase, COMP3H ---------------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterHigh(obj->cmpssHandle[0], 16, 8, 8);
        CMPSS_initFilterHigh(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], cmpsaDACH);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        // ------- V Phase, COMP4H ---------------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[1]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        CMPSS_configOutputsHigh(obj->cmpssHandle[1],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterHigh(obj->cmpssHandle[1], 16, 8, 8);
        CMPSS_initFilterHigh(obj->cmpssHandle[1]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[1], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[1],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[1], cmpsaDACH);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);

        // ------- W Phase, COMP4L ---------------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[2]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[2], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[2],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[2], 16, 8, 8);
        CMPSS_initFilterLow(obj->cmpssHandle[2]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[2], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[2],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[2], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
#if defined(MOTOR2_DCLINKSS)
        cmpsaDACL = MTR2_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPLPMux(MTR2_IDC_CMPLP_SEL, MTR2_IDC_CMPLP_MUX);

        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH/L and CTRIPOUTH/L will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[0],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[0], 16, 16, 8);
        CMPSS_initFilterLow(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[0], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR2_DCLINKSS, Three-shunt
        cmpsaDACH = MTR2_CMPSS_DACH_VALUE;
        cmpsaDACL = MTR2_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPHPMux(MTR2_IU_CMPHP_SEL, MTR2_IU_CMPHP_MUX);

        ASysCtl_selectCMPLPMux(MTR2_IV_CMPLP_SEL, MTR2_IV_CMPLP_MUX);

        ASysCtl_selectCMPLPMux(MTR2_IW_CMPLP_SEL, MTR2_IW_CMPLP_MUX);

        // --------------- U-Phase, COMP1H -------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterHigh(obj->cmpssHandle[0], 16, 8, 8);
        CMPSS_initFilterHigh(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], cmpsaDACH);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        // --------------- V-Phase, COMP1L -------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[1]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[1],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[1], 16, 8, 8);
        CMPSS_initFilterLow(obj->cmpssHandle[1]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[1], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[1],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[1], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        // --------------- W-Phase, COMP3L -------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[2]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[2], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[2],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[2], 16, 8, 8);
        CMPSS_initFilterLow(obj->cmpssHandle[2]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[2], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[2],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[2], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR2_DCLINKSS
    }
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
#if !defined(MOTOR1_DCLINKSS) || !defined(MOTOR2_DCLINKSS)
    uint16_t cmpsaDACH;
#endif
    uint16_t cmpsaDACL;

    // Refer to Technical Reference Manual to configure the ePWM X-Bar
    if(obj->motorNum == MTR_1)
    {
#if !defined(MOTOR1_DCLINKSS) && !defined(MOTOR2_DCLINKSS)
        cmpsaDACH = MTR1_CMPSS_DACH_VALUE;
#endif
        cmpsaDACL = MTR1_CMPSS_DACL_VALUE;

#if defined(MOTOR1_DCLINKSS)
        ASysCtl_selectCMPLPMux(MTR1_IDC_CMPLP_SEL, MTR1_IDC_CMPLP_MUX);

        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH/L and CTRIPOUTH/L will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[0],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[0], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[0], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS, Three-shunt
        ASysCtl_selectCMPHPMux(MTR1_IU_CMPHP_SEL, MTR1_IU_CMPHP_MUX);

        ASysCtl_selectCMPHPMux(MTR1_IV_CMPHP_SEL, MTR1_IV_CMPHP_MUX);
        ASysCtl_selectCMPLPMux(MTR1_IV_CMPLP_SEL, MTR1_IV_CMPLP_MUX);

        ASysCtl_selectCMPLPMux(MTR1_IW_CMPLP_SEL, MTR1_IW_CMPLP_MUX);

        // -------------------- U-Phase -----------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        CMPSS_configFilterHigh(obj->cmpssHandle[0], 32, 32, 30);
        CMPSS_initFilterHigh(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], cmpsaDACH);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
        // ----------- V-Phase -------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[1]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        CMPSS_configOutputsHigh(obj->cmpssHandle[1],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[1],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        CMPSS_configFilterHigh(obj->cmpssHandle[1], 32, 32, 30);
        CMPSS_initFilterHigh(obj->cmpssHandle[1]);

        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[1], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[1]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[1], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[1],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[1], cmpsaDACH);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[1], cmpsaDACL);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        // --------------- W-Phase ---------------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[2]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[2], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[2],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[2], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[2]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[2], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[2],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[2], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        cmpsaDACH = MTR2_CMPSS_DACH_VALUE;
        cmpsaDACL = MTR2_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPHPMux(MTR2_IU_CMPHP_SEL, MTR2_IU_CMPHP_MUX);

        ASysCtl_selectCMPHPMux(MTR2_IV_CMPHP_SEL, MTR2_IV_CMPHP_MUX);
        ASysCtl_selectCMPLPMux(MTR2_IV_CMPLP_SEL, MTR2_IV_CMPLP_MUX);

        ASysCtl_selectCMPLPMux(MTR2_IW_CMPLP_SEL, MTR2_IW_CMPLP_MUX);

        // -------------------- U-Phase -----------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        CMPSS_configFilterHigh(obj->cmpssHandle[0], 32, 32, 30);
        CMPSS_initFilterHigh(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], cmpsaDACH);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
        // ----------- V-Phase -------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[1]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        CMPSS_configOutputsHigh(obj->cmpssHandle[1],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[1],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        CMPSS_configFilterHigh(obj->cmpssHandle[1], 32, 32, 30);
        CMPSS_initFilterHigh(obj->cmpssHandle[1]);

        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[1], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[1]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[1], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[1],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[1], cmpsaDACH);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[1], cmpsaDACL);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[1]);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        // --------------- W-Phase ---------------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[2]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[2], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[2],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[2], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[2]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[2], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[2],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[2], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
    }
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
#if !defined(MOTOR1_DCLINKSS) || !defined(MOTOR2_DCLINKSS)
    uint16_t cmpsaDACH;
#endif
    uint16_t cmpsaDACL;

    // Refer to Technical Reference Manual to configure the ePWM X-Bar
    if(obj->motorNum == MTR_1)
    {
#if defined(MOTOR1_DCLINKSS)
        cmpsaDACL = MTR1_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPLPMux(MTR1_IDC_CMPLP_SEL, MTR1_IDC_CMPLP_MUX);

        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH/L and CTRIPOUTH/L will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[0],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[0], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[0], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);
#else   // !MOTOR1_DCLINKSS, Three-shunt
        cmpsaDACH = MTR1_CMPSS_DACH_VALUE;
        cmpsaDACL = MTR1_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPLPMux(MTR1_IU_CMPHP_SEL, MTR1_IU_CMPHP_MUX);

        ASysCtl_selectCMPLPMux(MTR1_IV_CMPLP_SEL, MTR1_IV_CMPLP_MUX);

        ASysCtl_selectCMPLPMux(MTR1_IW_CMPLP_SEL, MTR1_IW_CMPLP_MUX);

        // ------------- U-Phase ------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        CMPSS_configFilterHigh(obj->cmpssHandle[0], 4, 2, 2);
        CMPSS_initFilterHigh(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], cmpsaDACH);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        // --------------- V-Phase -------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[1]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[1],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[1], 4, 2, 2);
        CMPSS_initFilterLow(obj->cmpssHandle[1]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[1], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[1],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[1], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        // -------------------- W-Phase -----------------------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[2]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[2], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[2],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[2], 4, 2, 2);
        CMPSS_initFilterLow(obj->cmpssHandle[2]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[2], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[2],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[2], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
#endif  // MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        cmpsaDACH = MTR2_CMPSS_DACH_VALUE;
        cmpsaDACL = MTR2_CMPSS_DACL_VALUE;

        ASysCtl_selectCMPHPMux(MTR2_IU_CMPHP_SEL, MTR2_IU_CMPHP_MUX);

        ASysCtl_selectCMPLPMux(MTR2_IV_CMPLP_SEL, MTR2_IV_CMPLP_MUX);

        ASysCtl_selectCMPLPMux(MTR2_IW_CMPLP_SEL, MTR2_IW_CMPLP_MUX);

        // ----------- U-Phase -------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[0]);

        // NEG signal from DAC for COMP-H
        CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                                CMPSS_TRIP_FILTER |
                                CMPSS_TRIPOUT_FILTER);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        CMPSS_configFilterHigh(obj->cmpssHandle[0], 32, 32, 30);
        CMPSS_initFilterHigh(obj->cmpssHandle[0]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-H to allowed MAX +ve current
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], cmpsaDACH);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

        // ----------- V-Phase -------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[1]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[1],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[1], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[1]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[1], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[1],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[1], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

        // ----------- W-Phase -------------------------
        // Enable CMPSS and configure the negative input signal to come from the DAC
        CMPSS_enableModule(obj->cmpssHandle[2]);

        // NEG signal from DAC for COMP-L
        CMPSS_configLowComparator(obj->cmpssHandle[2], CMPSS_INSRC_DAC);

        // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
        // the asynchronous comparator output.
        // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
        CMPSS_configOutputsLow(obj->cmpssHandle[2],
                               CMPSS_TRIP_FILTER |
                               CMPSS_TRIPOUT_FILTER |
                               CMPSS_INV_INVERTED);

        // Configure digital filter. For this example, the maxiumum values will be
        // used for the clock prescale, sample window size, and threshold.
        // Initialize the filter logic and start filtering
        CMPSS_configFilterLow(obj->cmpssHandle[2], 32, 32, 30);
        CMPSS_initFilterLow(obj->cmpssHandle[2]);

        // Set up COMPHYSCTL register
        // COMP hysteresis set to 2x typical value
        CMPSS_setHysteresis(obj->cmpssHandle[2], 1);

        // Use VDDA as the reference for the DAC and set DAC value to midpoint for
        // arbitrary reference
        CMPSS_configDAC(obj->cmpssHandle[2],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

        // Set DAC-L to allowed MAX -ve current
        CMPSS_setDACValueLow(obj->cmpssHandle[2], cmpsaDACL);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[2]);
    }
    // BSXL8323RH_REVB
#else
#error Not select a right board to configure the CMPSS for motors
#endif  // No Hardware Boards

    return;
} // end of HAL_setupCMPSSsMTR() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
// HAL_setupCMPSSsPFC
void HAL_setupCMPSSsPFC(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    // Refer to Technical Reference Manual to configure the ePWM X-Bar
    ASysCtl_selectCMPHPMux(PFC_IAC_CMPHP_SEL, PFC_IAC_CMPHP_MUX);
    ASysCtl_selectCMPHPMux(PFC_VDC_CMPHP_SEL, PFC_VDC_CMPHP_MUX);

    //--------------------------------------------------------------------------
    // For Iac
    // Enable CMPSS and configure the negative input signal to come from the DAC
    CMPSS_enableModule(obj->cmpssHandle[0]);

    // NEG signal from DAC for COMP-H
    CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

    // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
    // the asynchronous comparator output.
    // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
    CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                            CMPSS_TRIP_FILTER |
                            CMPSS_TRIPOUT_FILTER |
                            CMPSS_OR_ASYNC_OUT_W_FILT);

    // Configure digital filter. For this example, the maxiumum values will be
    // used for the clock prescale, sample window size, and threshold.
    // Initialize the filter logic and start filtering
    CMPSS_configFilterHigh(obj->cmpssHandle[0], 24, 16, 12);
    CMPSS_initFilterHigh(obj->cmpssHandle[0]);

    // Set up COMPHYSCTL register
    // COMP hysteresis set to 2x typical value
    CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

    // Use VDDA as the reference for the DAC and set DAC value to midpoint for
    // arbitrary reference
    CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

    // Set DAC-H to allowed MAX +ve current
    CMPSS_setDACValueHigh(obj->cmpssHandle[0], PFC_CMPSS_DACH_VALUE);

    // Clear any high comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

    //--------------------------------------------------------------------------
    // For Vdc
    // Enable CMPSS and configure the negative input signal to come from the DAC
    CMPSS_enableModule(obj->cmpssHandle[1]);

    // NEG signal from DAC for COMP-L
    CMPSS_configLowComparator(obj->cmpssHandle[1], CMPSS_INSRC_DAC);

    // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
    // the asynchronous comparator output.
    // Dig filter output ==> CTRIPL, Dig filter output ==> CTRIPOUTL
    CMPSS_configOutputsLow(obj->cmpssHandle[1],
                           CMPSS_TRIP_FILTER |
                           CMPSS_TRIPOUT_FILTER |
                           CMPSS_INV_INVERTED);

    // Configure digital filter. For this example, the maxiumum values will be
    // used for the clock prescale, sample window size, and threshold.
    // Initialize the filter logic and start filtering
    // Initialize the filter logic and start filtering
    CMPSS_configFilterLow(obj->cmpssHandle[1], 16, 20, 16);
    CMPSS_initFilterLow(obj->cmpssHandle[1]);

    // Set up COMPHYSCTL register
    // COMP hysteresis set to 2x typical value
    CMPSS_setHysteresis(obj->cmpssHandle[1], 1);

    // Use VDDA as the reference for the DAC and set DAC value to midpoint for
    // arbitrary reference
    CMPSS_configDAC(obj->cmpssHandle[1],
               CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

    // Set DAC-L to allowed MAX -ve current
    CMPSS_setDACValueLow(obj->cmpssHandle[1], PFC_CMPSS_DACL_VALUE);

    // Clear any low comparator digital filter output latch
    CMPSS_clearFilterLatchLow(obj->cmpssHandle[1]);

    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    // Refer to Technical Reference Manual to configure the ePWM X-Bar
    ASysCtl_selectCMPHPMux(PFC_IAC_CMPHP_SEL, PFC_IAC_CMPHP_MUX);   //

    // Enable CMPSS and configure the negative input signal to come from the DAC
    CMPSS_enableModule(obj->cmpssHandle[0]);

    // NEG signal from DAC for COMP-H
    CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

    // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
    // the asynchronous comparator output.
    // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
    CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                            CMPSS_TRIP_FILTER |
                            CMPSS_TRIPOUT_FILTER |
                            CMPSS_OR_ASYNC_OUT_W_FILT);

    // Configure digital filter. For this example, the maxiumum values will be
    // used for the clock prescale, sample window size, and threshold.
    // Initialize the filter logic and start filtering
    CMPSS_configFilterHigh(obj->cmpssHandle[0], 16, 24, 20);
    CMPSS_initFilterHigh(obj->cmpssHandle[0]);

    // Set up COMPHYSCTL register
    // COMP hysteresis set to 2x typical value
    CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

    // Use VDDA as the reference for the DAC and set DAC value to midpoint for
    // arbitrary reference
    CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

    // Set DAC-H to allowed MAX +ve current
    CMPSS_setDACValueHigh(obj->cmpssHandle[0], PFC_CMPSS_DACH_VALUE);

    // Clear any high comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    // Refer to Technical Reference Manual to configure the ePWM X-Bar
    ASysCtl_selectCMPHPMux(PFC_IAC_CMPHP_SEL, PFC_IAC_CMPHP_MUX);   //

    // Enable CMPSS and configure the negative input signal to come from the DAC
    CMPSS_enableModule(obj->cmpssHandle[0]);

    // NEG signal from DAC for COMP-H
    CMPSS_configHighComparator(obj->cmpssHandle[0], CMPSS_INSRC_DAC);

    // Configure the output signals. Both CTRIPH and CTRIPOUTH will be fed by
    // the asynchronous comparator output.
    // Dig filter output ==> CTRIPH, Dig filter output ==> CTRIPOUTH
    CMPSS_configOutputsHigh(obj->cmpssHandle[0],
                            CMPSS_TRIP_FILTER |
                            CMPSS_TRIPOUT_FILTER |
                            CMPSS_OR_ASYNC_OUT_W_FILT);

    // Configure digital filter. For this example, the maxiumum values will be
    // used for the clock prescale, sample window size, and threshold.
    // Initialize the filter logic and start filtering
    CMPSS_configFilterHigh(obj->cmpssHandle[0], 16, 24, 20);
    CMPSS_initFilterHigh(obj->cmpssHandle[0]);

    // Set up COMPHYSCTL register
    // COMP hysteresis set to 2x typical value
    CMPSS_setHysteresis(obj->cmpssHandle[0], 1);

    // Use VDDA as the reference for the DAC and set DAC value to midpoint for
    // arbitrary reference
    CMPSS_configDAC(obj->cmpssHandle[0],
                   CMPSS_DACVAL_SYSCLK | CMPSS_DACSRC_SHDW);

    // Set DAC-H to allowed MAX +ve current
    CMPSS_setDACValueHigh(obj->cmpssHandle[0], PFC_CMPSS_DACH_VALUE);

    // Clear any high comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);
    // BSXL8323RH_REVB
#else
#error Not select a right board to configure the CMPSS for PFC
#endif  // No Hardware Boards

    return;
} // end of HAL_setupPFCCMPSSs() function


void HAL_setupMtrFaults(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;
    uint16_t cnt = 0;

    uint16_t tzSignal = MTR1_TZ_OSHT;
    uint16_t dcTripIn = MTR1_DCTRIPIN;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    if(obj->motorNum == MTR_1)
    {
        tzSignal = MTR1_TZ_OSHT;            // EPWM_TZ_SIGNAL_OSHT1
        dcTripIn = MTR1_DCTRIPIN;           // TRIPIN7

        // Configure TRIP 7 to OR the High and Low trips from both
        // comparator 5, 3 & 1, clear everything first
        EALLOW;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR1_XBAR_TRIP_ADDRL) = 0;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR1_XBAR_TRIP_ADDRH) = 0;
        EDIS;

#if defined(MOTOR1_DCLINKSS)
        // Configure TRIP7 to be CTRIP4H and CTRIP4L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IDC_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR1_XBAR_TRIP, 0xFFFF);

        // Enable mux to generate TRIP
        XBAR_enableEPWMMux(MTR1_XBAR_TRIP, MTR1_IDC_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR1_XBAR_INPUT, MTR1_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR1_XBAR_INPUT);
#else   // !MOTOR1_DCLINKSS
        // Configure TRIP7 to be CTRIP5H and CTRIP5L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IU_XBAR_EPWM_MUX);

        // Configure TRIP7 to be CTRIP1H and CTRIP1L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IV_XBAR_EPWM_MUX);

        // Configure TRIP7 to be CTRIP3H and CTRIP3L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IW_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR1_XBAR_TRIP, 0xFFFF);

        // Enable mux to generate TRIP
        XBAR_enableEPWMMux(MTR1_XBAR_TRIP, MTR1_IU_XBAR_MUX |
                                           MTR1_IV_XBAR_MUX | MTR1_IW_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR1_XBAR_INPUT, MTR1_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR1_XBAR_INPUT);

#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        tzSignal = MTR2_TZ_OSHT;            // EPWM_TZ_SIGNAL_OSHT2
        dcTripIn = MTR2_DCTRIPIN;           // TRIPIN8

        // Configure TRIP 8 to OR the High and Low trips from both
        // comparator 5, 3 & 1, clear everything first
        EALLOW;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR2_XBAR_TRIP_ADDRL) = 0;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR2_XBAR_TRIP_ADDRH) = 0;
        EDIS;

#if defined(MOTOR2_DCLINKSS)
        // Configure TRIP7 to be CTRIP5H and CTRIP5L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IDC_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR2_XBAR_TRIP, 0xFFFF);

        // Enable mux to generate TRIP
        XBAR_enableEPWMMux(MTR2_XBAR_TRIP, MTR2_IDC_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR2_XBAR_INPUT, MTR2_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR2_XBAR_INPUT);

#else   // !MOTOR2_DCLINKSS
        // Configure TRIP8 to be CTRIP4H and CTRIP4L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IU_XBAR_EPWM_MUX);

        // Configure TRIP8 to be CTRIP2H and CTRIP2L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IV_XBAR_EPWM_MUX);

        // Configure TRIP8 to be CTRIP6H and CTRIP6L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IW_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR2_XBAR_TRIP, 0xFFFF);

        // Enable Mux 0  OR Mux 4 to generate TRIP8
        XBAR_enableEPWMMux(MTR2_XBAR_TRIP, MTR2_IU_XBAR_MUX |
                                           MTR2_IV_XBAR_MUX | MTR2_IW_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR2_XBAR_INPUT, MTR2_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR2_XBAR_INPUT);

#endif  // !MOTOR2_DCLINKSS
    }

    // Configure Trip Mechanism for the Motor control software
    // -Cycle by cycle trip on CPU halt
    // -One shot fault trip zone
    // These trips need to be repeated for EPWM1 ,2 & 3
    for(cnt=0;cnt<3;cnt++)
    {
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], tzSignal);      // OST

        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_CBC6);

        //enable DC TRIP combinational input
        EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
                                                  dcTripIn, EPWM_DC_TYPE_DCAH);

        EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
                                                  dcTripIn, EPWM_DC_TYPE_DCBH);

        // Trigger event when DCAH is High
        EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
                                                     EPWM_TZ_DC_OUTPUT_A1,
                                                     EPWM_TZ_EVENT_DCXH_HIGH);

        // Trigger event when DCBH is High
        EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
                                                     EPWM_TZ_DC_OUTPUT_B1,
                                                     EPWM_TZ_EVENT_DCXL_HIGH);

        // Configure the DCA path to be filtered and asynchronous
        EPWM_setDigitalCompareEventSource(obj->pwmHandle[cnt],
                                          EPWM_DC_MODULE_A,
                                          EPWM_DC_EVENT_1,
                                          EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

        // Configure the DCB path to be filtered and asynchronous
        EPWM_setDigitalCompareEventSource(obj->pwmHandle[cnt],
                                          EPWM_DC_MODULE_B,
                                          EPWM_DC_EVENT_1,
                                          EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

        EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle[cnt],
                                            EPWM_DC_MODULE_A,
                                            EPWM_DC_EVENT_1,
                                            EPWM_DC_EVENT_INPUT_NOT_SYNCED);

        EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle[cnt],
                                            EPWM_DC_MODULE_B,
                                            EPWM_DC_EVENT_1,
                                            EPWM_DC_EVENT_INPUT_NOT_SYNCED);

        // Enable DCA as CBC
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_DCAEVT1);

        // Enable DCB as CBC
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_DCBEVT1);

        // What do we want the OST/CBC events to do?
        // TZA events can force EPWMxA
        // TZB events can force EPWMxB
        EPWM_setTripZoneAction(obj->pwmHandle[cnt],
                               EPWM_TZ_ACTION_EVENT_TZA,
                               EPWM_TZ_ACTION_LOW);

        EPWM_setTripZoneAction(obj->pwmHandle[cnt],
                               EPWM_TZ_ACTION_EVENT_TZB,
                               EPWM_TZ_ACTION_LOW);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[cnt]);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[cnt]);

        // Clear any spurious fault
        EPWM_clearTripZoneFlag(obj->pwmHandle[cnt], HAL_TZFLAG_INTERRUPT_ALL);
    }
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    if(obj->motorNum == MTR_1)
    {
        tzSignal = MTR1_TZ_OSHT;            // EPWM_TZ_SIGNAL_OSHT1
        dcTripIn = MTR1_DCTRIPIN;           // TRIPIN7

        // Configure TRIP 7 to OR the High and Low trips from both
        // comparator 5, 3 & 1, clear everything first
        EALLOW;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR1_XBAR_TRIP_ADDRL) = 0;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR1_XBAR_TRIP_ADDRH) = 0;
        EDIS;

#if defined(MOTOR1_DCLINKSS)
        // Configure TRIP7 to be CTRIP5H and CTRIP5L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IDC_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR1_XBAR_TRIP, 0xFFFF);

        // Enable mux to generate TRIP
        XBAR_enableEPWMMux(MTR1_XBAR_TRIP, MTR1_IDC_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR1_XBAR_INPUT, MTR1_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR1_XBAR_INPUT);
#else   // !MOTOR1_DCLINKSS
        // Configure TRIP7 to be CTRIP5H and CTRIP5L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IU_XBAR_EPWM_MUX);

        // Configure TRIP7 to be CTRIP1H and CTRIP1L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IV_XBAR_EPWM_MUX);

        // Configure TRIP7 to be CTRIP3H and CTRIP3L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IW_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR1_XBAR_TRIP, 0xFFFF);

        // Enable mux to generate TRIP
        XBAR_enableEPWMMux(MTR1_XBAR_TRIP, MTR1_IU_XBAR_MUX |
                                           MTR1_IV_XBAR_MUX | MTR1_IW_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR1_XBAR_INPUT, MTR1_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR1_XBAR_INPUT);

#endif  // !MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        tzSignal = MTR2_TZ_OSHT;            // EPWM_TZ_SIGNAL_OSHT2
        dcTripIn = MTR2_DCTRIPIN;           // TRIPIN8

        // Configure TRIP 8 to OR the High and Low trips from both
        // comparator 5, 3 & 1, clear everything first
        EALLOW;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR2_XBAR_TRIP_ADDRL) = 0;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR2_XBAR_TRIP_ADDRH) = 0;
        EDIS;

        // Configure TRIP8 to be CTRIP4H and CTRIP4L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IU_XBAR_EPWM_MUX);

        // Configure TRIP8 to be CTRIP2H and CTRIP2L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IV_XBAR_EPWM_MUX);

        // Configure TRIP8 to be CTRIP6H and CTRIP6L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IW_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR2_XBAR_TRIP, 0xFFFF);

        // Enable Mux 0  OR Mux 4 to generate TRIP8
        XBAR_enableEPWMMux(MTR2_XBAR_TRIP, MTR2_IU_XBAR_MUX |
                                           MTR2_IV_XBAR_MUX | MTR2_IW_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR2_XBAR_INPUT, MTR2_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR2_XBAR_INPUT);

    }
    // Configure Trip Mechanism for the Motor control software
    // -Cycle by cycle trip on CPU halt
    // -One shot fault trip zone
    // These trips need to be repeated for EPWM1 ,2 & 3
    for(cnt=0;cnt<3;cnt++)
    {
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], tzSignal);      // OST

        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_CBC6);

        //enable DC TRIP combinational input
        EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
                                                  dcTripIn, EPWM_DC_TYPE_DCAH);

        EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
                                                  dcTripIn, EPWM_DC_TYPE_DCBH);

        // Trigger event when DCAH is High
        EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
                                                     EPWM_TZ_DC_OUTPUT_A1,
                                                     EPWM_TZ_EVENT_DCXH_HIGH);

        // Trigger event when DCBH is High
        EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
                                                     EPWM_TZ_DC_OUTPUT_B1,
                                                     EPWM_TZ_EVENT_DCXL_HIGH);

        // Configure the DCA path to be filtered and asynchronous
        EPWM_setDigitalCompareEventSource(obj->pwmHandle[cnt],
                                          EPWM_DC_MODULE_A,
                                          EPWM_DC_EVENT_1,
                                          EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

        // Configure the DCB path to be filtered and asynchronous
        EPWM_setDigitalCompareEventSource(obj->pwmHandle[cnt],
                                          EPWM_DC_MODULE_B,
                                          EPWM_DC_EVENT_1,
                                          EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

        EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle[cnt],
                                            EPWM_DC_MODULE_A,
                                            EPWM_DC_EVENT_1,
                                            EPWM_DC_EVENT_INPUT_NOT_SYNCED);

        EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle[cnt],
                                            EPWM_DC_MODULE_B,
                                            EPWM_DC_EVENT_1,
                                            EPWM_DC_EVENT_INPUT_NOT_SYNCED);

        // Enable DCA as CBC
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_DCAEVT1);

        // Enable DCB as CBC
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_DCBEVT1);

        // What do we want the OST/CBC events to do?
        // TZA events can force EPWMxA
        // TZB events can force EPWMxB
        EPWM_setTripZoneAction(obj->pwmHandle[cnt],
                               EPWM_TZ_ACTION_EVENT_TZA,
                               EPWM_TZ_ACTION_LOW);

        EPWM_setTripZoneAction(obj->pwmHandle[cnt],
                               EPWM_TZ_ACTION_EVENT_TZB,
                               EPWM_TZ_ACTION_LOW);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[cnt]);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[cnt]);

        // Clear any spurious fault
        EPWM_clearTripZoneFlag(obj->pwmHandle[cnt], HAL_TZFLAG_INTERRUPT_ALL);
    }
#elif defined(BSXL8323RH_REVB)
    if(obj->motorNum == MTR_1)
    {
        tzSignal = MTR1_TZ_OSHT;            // EPWM_TZ_SIGNAL_OSHT1
        dcTripIn = MTR1_DCTRIPIN;           // TRIPIN7

        // Configure TRIP 7 to OR the High and Low trips from both
        // comparator 5, 3 & 1, clear everything first
        EALLOW;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR1_XBAR_TRIP_ADDRL) = 0;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR1_XBAR_TRIP_ADDRH) = 0;
        EDIS;

#if defined(MOTOR1_DCLINKSS)
        // Configure TRIP7 to be CTRIP5H and CTRIP5L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IDC_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR1_XBAR_TRIP, 0xFFFF);

        // Enable Mux 0  OR Mux 4 to generate TRIP
        XBAR_enableEPWMMux(MTR1_XBAR_TRIP, MTR1_IDC_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR1_XBAR_INPUT, MTR1_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR1_XBAR_INPUT);
#else   // !MOTOR1_DCLINKSS
        // Configure TRIP7 to be CTRIP5H and CTRIP5L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IU_XBAR_EPWM_MUX);

        // Configure TRIP7 to be CTRIP1H and CTRIP1L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IV_XBAR_EPWM_MUX);

        // Configure TRIP7 to be CTRIP3H and CTRIP3L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR1_XBAR_TRIP, MTR1_IW_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR1_XBAR_TRIP, 0xFFFF);

        // Enable mux to generate TRIP
        XBAR_enableEPWMMux(MTR1_XBAR_TRIP, MTR1_IU_XBAR_MUX |
                                           MTR1_IV_XBAR_MUX | MTR1_IW_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR1_XBAR_INPUT, MTR1_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR1_XBAR_INPUT);

#endif  // MOTOR1_DCLINKSS
    }
    else if(obj->motorNum == MTR_2)
    {
        tzSignal = MTR2_TZ_OSHT;            // EPWM_TZ_SIGNAL_OSHT2
        dcTripIn = MTR2_DCTRIPIN;           // TRIPIN8

        // Configure TRIP 8 to OR the High and Low trips from both
        // comparator 5, 3 & 1, clear everything first
        EALLOW;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR2_XBAR_TRIP_ADDRL) = 0;
        HWREG(XBAR_EPWM_CFG_REG_BASE + MTR2_XBAR_TRIP_ADDRH) = 0;
        EDIS;

        // Configure TRIP8 to be CTRIP4H and CTRIP4L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IU_XBAR_EPWM_MUX);

        // Configure TRIP8 to be CTRIP2H and CTRIP2L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IV_XBAR_EPWM_MUX);

        // Configure TRIP8 to be CTRIP6H and CTRIP6L using the ePWM X-BAR
        XBAR_setEPWMMuxConfig(MTR2_XBAR_TRIP, MTR2_IW_XBAR_EPWM_MUX);

        // Disable all the mux first
        XBAR_disableEPWMMux(MTR2_XBAR_TRIP, 0xFFFF);

        // Enable Mux 0  OR Mux 4 to generate TRIP8
        XBAR_enableEPWMMux(MTR2_XBAR_TRIP, MTR2_IU_XBAR_MUX |
                                           MTR2_IV_XBAR_MUX | MTR2_IW_XBAR_MUX);

        // configure the input x bar for TZ2 to GPIO, where Over Current is connected
        XBAR_setInputPin(INPUTXBAR_BASE, MTR2_XBAR_INPUT, MTR2_PM_nFAULT_GPIO);
        XBAR_lockInput(INPUTXBAR_BASE, MTR2_XBAR_INPUT);

    }
    // Configure Trip Mechanism for the Motor control software
    // -Cycle by cycle trip on CPU halt
    // -One shot fault trip zone
    // These trips need to be repeated for EPWM1 ,2 & 3
    for(cnt=0;cnt<3;cnt++)
    {
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], tzSignal);      // OST

        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_CBC6);

        //enable DC TRIP combinational input
        EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
                                                  dcTripIn, EPWM_DC_TYPE_DCAH);

        EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
                                                  dcTripIn, EPWM_DC_TYPE_DCBH);

        // Trigger event when DCAH is High
        EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
                                                     EPWM_TZ_DC_OUTPUT_A1,
                                                     EPWM_TZ_EVENT_DCXH_HIGH);

        // Trigger event when DCBH is High
        EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
                                                     EPWM_TZ_DC_OUTPUT_B1,
                                                     EPWM_TZ_EVENT_DCXL_HIGH);

        // Configure the DCA path to be filtered and asynchronous
        EPWM_setDigitalCompareEventSource(obj->pwmHandle[cnt],
                                          EPWM_DC_MODULE_A,
                                          EPWM_DC_EVENT_1,
                                          EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

        // Configure the DCB path to be filtered and asynchronous
        EPWM_setDigitalCompareEventSource(obj->pwmHandle[cnt],
                                          EPWM_DC_MODULE_B,
                                          EPWM_DC_EVENT_1,
                                          EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

        EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle[cnt],
                                            EPWM_DC_MODULE_A,
                                            EPWM_DC_EVENT_1,
                                            EPWM_DC_EVENT_INPUT_NOT_SYNCED);

        EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle[cnt],
                                            EPWM_DC_MODULE_B,
                                            EPWM_DC_EVENT_1,
                                            EPWM_DC_EVENT_INPUT_NOT_SYNCED);

        // Enable DCA as CBC
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_DCAEVT1);

        // Enable DCB as CBC
        EPWM_enableTripZoneSignals(obj->pwmHandle[cnt], EPWM_TZ_SIGNAL_DCBEVT1);

        // What do we want the OST/CBC events to do?
        // TZA events can force EPWMxA
        // TZB events can force EPWMxB
        EPWM_setTripZoneAction(obj->pwmHandle[cnt],
                               EPWM_TZ_ACTION_EVENT_TZA,
                               EPWM_TZ_ACTION_LOW);

        EPWM_setTripZoneAction(obj->pwmHandle[cnt],
                               EPWM_TZ_ACTION_EVENT_TZB,
                               EPWM_TZ_ACTION_LOW);

        // Clear any high comparator digital filter output latch
        CMPSS_clearFilterLatchHigh(obj->cmpssHandle[cnt]);

        // Clear any low comparator digital filter output latch
        CMPSS_clearFilterLatchLow(obj->cmpssHandle[cnt]);

        // Clear any spurious fault
        EPWM_clearTripZoneFlag(obj->pwmHandle[cnt], HAL_TZFLAG_INTERRUPT_ALL);
    }
// BSXL8323RH_REVB

#else
#error Not select a right board to configure the fault protection for motors
#endif

    return;
} // end of HAL_setupMtrFaults() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupPFCFaults(HAL_PFC_Handle handle)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    // Configure TRIP 4 to OR the High and Low trips from both
    // comparator 5, 3 & 1, clear everything first
    EALLOW;
    HWREG(XBAR_EPWM_CFG_REG_BASE + PFC_XBAR_TRIP_ADDRL) = 0;
    HWREG(XBAR_EPWM_CFG_REG_BASE + PFC_XBAR_TRIP_ADDRH) = 0;
    EDIS;

    // Configure TRIP7 to be CTRIP7H and CTRIP7L using the ePWM X-BAR
    XBAR_setEPWMMuxConfig(PFC_XBAR_TRIP, PFC_IAC_XBAR_EPWM_MUX);
    XBAR_setEPWMMuxConfig(PFC_XBAR_TRIP, PFC_VDC_XBAR_EPWM_MUX);

    // Disable all the mux first
    XBAR_disableEPWMMux(PFC_XBAR_TRIP, 0xFFFF);

    // Enable Mux12 to generate TRIP4
    XBAR_enableEPWMMux(PFC_XBAR_TRIP, PFC_IAC_XBAR_MUX);


    // Configure Trip Mechanism for the Motor control software
    // -Cycle by cycle trip on CPU halt
    // -One shot fault trip zone
    // These trips need to be repeated for EPWM7
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_CBC6);

    //enable DC TRIP combinational input
    EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle,
                                              PFC_DCTRIPIN, EPWM_DC_TYPE_DCAH);

    EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle,
                                              PFC_DCTRIPIN, EPWM_DC_TYPE_DCBH);

    // Trigger event when DCAH is High
    EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle,
                                                 EPWM_TZ_DC_OUTPUT_A1,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);

    // Trigger event when DCBH is High
    EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle,
                                                 EPWM_TZ_DC_OUTPUT_B1,
                                                 EPWM_TZ_EVENT_DCXL_HIGH);

    // Configure the DCA path to be un-filtered and asynchronous
    EPWM_setDigitalCompareEventSource(obj->pwmHandle,
                                      EPWM_DC_MODULE_A,
                                      EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    // Configure the DCB path to be un-filtered and asynchronous
    EPWM_setDigitalCompareEventSource(obj->pwmHandle,
                                      EPWM_DC_MODULE_B,
                                      EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle,
                                        EPWM_DC_MODULE_A,
                                        EPWM_DC_EVENT_1,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle,
                                        EPWM_DC_MODULE_B,
                                        EPWM_DC_EVENT_1,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    // Enable DCA as OST
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_DCAEVT1);

    // Enable DCB as OST
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_DCBEVT1);

    // What do we want the OST/CBC events to do?
    // TZA events can force EPWMxA
    // TZB events can force EPWMxB
    EPWM_setTripZoneAction(obj->pwmHandle,
                           EPWM_TZ_ACTION_EVENT_TZA,
                           EPWM_TZ_ACTION_LOW);

    EPWM_setTripZoneAction(obj->pwmHandle,
                           EPWM_TZ_ACTION_EVENT_TZB,
                           EPWM_TZ_ACTION_LOW);

    // Clear any high comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

    // Clear any low comparator digital filter output latch
    CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);

    // Clear any spurious fault
    EPWM_clearTripZoneFlag(obj->pwmHandle,
                                    HAL_TZFLAG_INTERRUPT_ALL);
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    // Configure TRIP 4 to OR the High and Low trips from both
    // comparator 5, 3 & 1, clear everything first
    EALLOW;
    HWREG(XBAR_EPWM_CFG_REG_BASE + PFC_XBAR_TRIP_ADDRL) = 0;
    HWREG(XBAR_EPWM_CFG_REG_BASE + PFC_XBAR_TRIP_ADDRH) = 0;
    EDIS;

    // Configure TRIP7 to be CTRIP7H and CTRIP7L using the ePWM X-BAR
    XBAR_setEPWMMuxConfig(PFC_XBAR_TRIP, PFC_IAC_XBAR_EPWM_MUX);

    // Disable all the mux first
    XBAR_disableEPWMMux(PFC_XBAR_TRIP, 0xFFFF);

    // Enable Mux12 to generate TRIP4
    XBAR_enableEPWMMux(PFC_XBAR_TRIP, PFC_IAC_XBAR_MUX);


    // Configure Trip Mechanism for the Motor control software
    // -Cycle by cycle trip on CPU halt
    // -One shot fault trip zone
    // These trips need to be repeated for EPWM7
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_CBC6);

    //enable DC TRIP combinational input
    EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle,
                                              PFC_DCTRIPIN, EPWM_DC_TYPE_DCAH);

    EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle,
                                              PFC_DCTRIPIN, EPWM_DC_TYPE_DCBH);

    // Trigger event when DCAH is High
    EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle,
                                                 EPWM_TZ_DC_OUTPUT_A1,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);

    // Trigger event when DCBH is High
    EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle,
                                                 EPWM_TZ_DC_OUTPUT_B1,
                                                 EPWM_TZ_EVENT_DCXL_HIGH);

    // Configure the DCA path to be un-filtered and asynchronous
    EPWM_setDigitalCompareEventSource(obj->pwmHandle,
                                      EPWM_DC_MODULE_A,
                                      EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    // Configure the DCB path to be un-filtered and asynchronous
    EPWM_setDigitalCompareEventSource(obj->pwmHandle,
                                      EPWM_DC_MODULE_B,
                                      EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle,
                                        EPWM_DC_MODULE_A,
                                        EPWM_DC_EVENT_1,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle,
                                        EPWM_DC_MODULE_B,
                                        EPWM_DC_EVENT_1,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    // Enable DCA as OST
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_DCAEVT1);

    // Enable DCB as OST
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_DCBEVT1);

    // What do we want the OST/CBC events to do?
    // TZA events can force EPWMxA
    // TZB events can force EPWMxB
    EPWM_setTripZoneAction(obj->pwmHandle,
                           EPWM_TZ_ACTION_EVENT_TZA,
                           EPWM_TZ_ACTION_LOW);

    EPWM_setTripZoneAction(obj->pwmHandle,
                           EPWM_TZ_ACTION_EVENT_TZB,
                           EPWM_TZ_ACTION_LOW);

    // Clear any high comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

    // Clear any low comparator digital filter output latch
    CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);

    // Clear any spurious fault
    EPWM_clearTripZoneFlag(obj->pwmHandle,
                                    HAL_TZFLAG_INTERRUPT_ALL);
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    // Configure TRIP 4 to OR the High and Low trips from both
    // comparator 5, 3 & 1, clear everything first
    EALLOW;
    HWREG(XBAR_EPWM_CFG_REG_BASE + PFC_XBAR_TRIP_ADDRL) = 0;
    HWREG(XBAR_EPWM_CFG_REG_BASE + PFC_XBAR_TRIP_ADDRH) = 0;
    EDIS;

    // Configure TRIP7 to be CTRIP7H and CTRIP7L using the ePWM X-BAR
    XBAR_setEPWMMuxConfig(PFC_XBAR_TRIP, PFC_IAC_XBAR_EPWM_MUX);

    // Disable all the mux first
    XBAR_disableEPWMMux(PFC_XBAR_TRIP, 0xFFFF);

    // Enable Mux12 to generate TRIP4
    XBAR_enableEPWMMux(PFC_XBAR_TRIP, PFC_IAC_XBAR_MUX);


    // Configure Trip Mechanism for the Motor control software
    // -Cycle by cycle trip on CPU halt
    // -One shot fault trip zone
    // These trips need to be repeated for EPWM7
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_CBC6);

    //enable DC TRIP combinational input
    EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle,
                                              PFC_DCTRIPIN, EPWM_DC_TYPE_DCAH);

    EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle,
                                              PFC_DCTRIPIN, EPWM_DC_TYPE_DCBH);

    // Trigger event when DCAH is High
    EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle,
                                                 EPWM_TZ_DC_OUTPUT_A2,
                                                 EPWM_TZ_EVENT_DCXH_HIGH);

    // Trigger event when DCBH is High
    EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle,
                                                 EPWM_TZ_DC_OUTPUT_B2,
                                                 EPWM_TZ_EVENT_DCXL_HIGH);

    // Configure the DCA path to be un-filtered and asynchronous
    EPWM_setDigitalCompareEventSource(obj->pwmHandle,
                                      EPWM_DC_MODULE_A,
                                      EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    // Configure the DCB path to be un-filtered and asynchronous
    EPWM_setDigitalCompareEventSource(obj->pwmHandle,
                                      EPWM_DC_MODULE_B,
                                      EPWM_DC_EVENT_1,
                                      EPWM_DC_EVENT_SOURCE_FILT_SIGNAL);

    EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle,
                                        EPWM_DC_MODULE_A,
                                        EPWM_DC_EVENT_1,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    EPWM_setDigitalCompareEventSyncMode(obj->pwmHandle,
                                        EPWM_DC_MODULE_B,
                                        EPWM_DC_EVENT_1,
                                        EPWM_DC_EVENT_INPUT_NOT_SYNCED);

    // Enable DCA as OST
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_DCAEVT2);

    // Enable DCB as OST
    EPWM_enableTripZoneSignals(obj->pwmHandle, EPWM_TZ_SIGNAL_DCBEVT2);

    // What do we want the OST/CBC events to do?
    // TZA events can force EPWMxA
    // TZB events can force EPWMxB
    EPWM_setTripZoneAction(obj->pwmHandle,
                           EPWM_TZ_ACTION_EVENT_TZA,
                           EPWM_TZ_ACTION_LOW);

    EPWM_setTripZoneAction(obj->pwmHandle,
                           EPWM_TZ_ACTION_EVENT_TZB,
                           EPWM_TZ_ACTION_LOW);

    // Clear any high comparator digital filter output latch
    CMPSS_clearFilterLatchHigh(obj->cmpssHandle[0]);

    // Clear any low comparator digital filter output latch
    CMPSS_clearFilterLatchLow(obj->cmpssHandle[0]);

    // Clear any spurious fault
    EPWM_clearTripZoneFlag(obj->pwmHandle,
                                    HAL_TZFLAG_INTERRUPT_ALL);
// BSXL8323RH_REVB

#else
#error Not select a right board to configure the fault protection for PFC
#endif

    return;
} // end of HAL_setupPFCFaults() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupGPIOs(HAL_Handle handle)
{

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    // M1-Compressor Motor, M2-Fan Motor, EEV-EEV Stepper
    // GPIO0->EPWM1A->M1_UH
    GPIO_setPinConfig(GPIO_0_EPWM1_A);
    GPIO_setDirectionMode(0, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD);

    // GPIO1->EPWM1B->M1_UL
    GPIO_setPinConfig(GPIO_1_EPWM1_B);
    GPIO_setDirectionMode(1, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(1, GPIO_PIN_TYPE_STD);

    // GPIO2->GPIO2->EEV_1H
    GPIO_setPinConfig(GPIO_2_GPIO2);
    GPIO_writePin(2, 0);       // Default output is LOW
    GPIO_setDirectionMode(2, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(2, GPIO_PIN_TYPE_STD);

    // GPIO3->GPIO3->EEV_1L
    GPIO_setPinConfig(GPIO_3_GPIO3);
    GPIO_writePin(3, 0);       // Default output is LOW
    GPIO_setDirectionMode(3, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(3, GPIO_PIN_TYPE_STD);

    // GPIO4->EPWM3A->M1_VH
    GPIO_setPinConfig(GPIO_4_EPWM3_A);
    GPIO_setDirectionMode(4, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(4, GPIO_PIN_TYPE_STD);

    // GPIO5->EPWM3B->M1_VL
    GPIO_setPinConfig(GPIO_5_EPWM3_B);
    GPIO_setDirectionMode(5, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(5, GPIO_PIN_TYPE_STD);
    // GPIO6->EPWM4A->M2_UH
    GPIO_setPinConfig(GPIO_6_EPWM4_A);
    GPIO_setDirectionMode(6, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(6, GPIO_PIN_TYPE_STD);

    // GPIO7->EPWM4B->M2_UL
    GPIO_setPinConfig(GPIO_7_EPWM4_B);
    GPIO_setDirectionMode(7, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(7, GPIO_PIN_TYPE_STD);

    // GPIO8->EPWM5A->M1_WH
    GPIO_setPinConfig(GPIO_8_EPWM5_A);
    GPIO_setDirectionMode(8, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(8, GPIO_PIN_TYPE_STD);

    // GPIO9->EPWM5B->M1_WL
    GPIO_setPinConfig(GPIO_9_EPWM5_B);
    GPIO_setDirectionMode(9, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(9, GPIO_PIN_TYPE_STD);

    // GPIO10->EPWM6_A->M2_VH
    GPIO_setPinConfig(GPIO_10_EPWM6_A);
    GPIO_setDirectionMode(10, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(10, GPIO_PIN_TYPE_STD);

    // GPIO11->GPIO11(CLB->APWM)->EMI_INJ_MD
    GPIO_setPinConfig(GPIO_11_GPIO11);
    GPIO_writePin(11, 0);       // Default output is LOW
    GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(11, GPIO_PIN_TYPE_STD);

    // GPIO12->EPWM7_A->PFC_2SC
    GPIO_setPinConfig(GPIO_12_EPWM7_A);
    GPIO_setDirectionMode(12, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(12, GPIO_PIN_TYPE_STD);

    // GPIO13->EPWM7_B->PFC_1SC
    GPIO_setPinConfig(GPIO_13_EPWM7_B);
    GPIO_setDirectionMode(13, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(13, GPIO_PIN_TYPE_STD);

    // GPIO13, GPIO14 are not available on this 64-pin device

    // GPIO16->GPIO16(CLB->APWM)->EMI_INJ_PU
    GPIO_setPinConfig(GPIO_16_GPIO16);
    GPIO_setDirectionMode(16, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(16, GPIO_PIN_TYPE_STD);

    // GPIO17->GPIO17(CLB->APWM)->EMI_INJ_PD
    GPIO_setPinConfig(GPIO_17_GPIO17);
    GPIO_setDirectionMode(17, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(17, GPIO_PIN_TYPE_STD);

    // GPIO18->GPIO18->FW way relay (DMCPFC_REV3P1) / Inrush Power Rleay (DMCPFC_REV3P2)
    GPIO_setPinConfig(GPIO_18_GPIO18);
    GPIO_writePin(18, 0);       // Default output is LOW
    GPIO_setDirectionMode(18, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(18, GPIO_PIN_TYPE_STD);

    // GPIO19->EPWM6_B->M2_VL
    GPIO_setPinConfig(GPIO_19_EPWM6_B);
    GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(19, GPIO_PIN_TYPE_STD);

    // GPIO22->GPIO22(XBARIN)->M1_Fault
    GPIO_setPinConfig(GPIO_22_GPIO22);
    GPIO_setDirectionMode(22, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(22, GPIO_PIN_TYPE_PULLUP);

    // GPIO23->GPIO23(XBARIN)->M2_Fault
    GPIO_setPinConfig(GPIO_23_GPIO23);
    GPIO_setDirectionMode(23, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(23, GPIO_PIN_TYPE_PULLUP);

    // GPIO24->GPIO24->EEV_2L/SDI
#if defined(DAC128S_ENABLE)
    // GPIO24->SPIA_SIMO->DAC_SDI
    GPIO_setPinConfig(GPIO_24_SPIA_SIMO);
    GPIO_setDirectionMode(24, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(24, GPIO_PIN_TYPE_STD);
    GPIO_setQualificationMode(24, GPIO_QUAL_SYNC);
#else   // !DAC128S_ENABLE
    // GPIO24->GPIO24->EEV_2L/TEST_GPIO for Motor_1
    GPIO_setPinConfig(GPIO_24_GPIO24);
    GPIO_writePin(24, 0);       // Default output is LOW
    GPIO_setDirectionMode(24, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(24, GPIO_PIN_TYPE_PULLUP);
#endif  // !DAC128S_ENABLE

    // GPIO25, GPIO26 and GPIO27 are not available on this 64-pin device

#if defined(DAC128S_ENABLE)
    // GPIO28->SPIA_CLK->DAC_SCLK
    GPIO_setPinConfig(GPIO_28_SPIA_CLK);
    GPIO_setDirectionMode(28, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(28, GPIO_PIN_TYPE_STD);
    GPIO_setQualificationMode(28, GPIO_QUAL_SYNC);
#elif defined(SFRA_ENABLE)
    // GPIO28->SCIA_RX->SFRA_RX
    GPIO_setPinConfig(GPIO_28_SCIA_RX);
    GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(28, GPIO_PIN_TYPE_PULLUP);
#else   // !(DAC128S_ENABLE & SFRA_ENABLE)
    // GPIO28->GPIO28->LED_1/TEST_GPIO for Motor_2
    GPIO_setPinConfig(GPIO_28_GPIO28);
    GPIO_setDirectionMode(28, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(28, GPIO_PIN_TYPE_PULLUP);
#endif  // !(DAC128S_ENABLE & SFRA_ENABLE)

#if defined(DAC128S_ENABLE)
    // GPIO29->SPIA_STE->DAC_SCS
    GPIO_setPinConfig(GPIO_29_SPIA_STE);
    GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(29, GPIO_PIN_TYPE_STD);
    GPIO_setQualificationMode(29, GPIO_QUAL_SYNC);
#elif defined(SFRA_ENABLE)
    // GPIO29->SCIA_TX->SFRA_TX
    GPIO_setPinConfig(GPIO_29_SCIA_TX);
    GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(29, GPIO_PIN_TYPE_PULLUP);
#else   // !(DAC128S_ENABLE & SFRA_ENABLE)
    // GPIO29->GPIO29->LED_2/TEST_GPIO for PFC
    GPIO_setPinConfig(GPIO_29_GPIO29);
    GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(29, GPIO_PIN_TYPE_PULLUP);
#endif  // !(DAC128S_ENABLE & SFRA_ENABLE)

    // GPIO30 and GPIO31 are not available on this 64-pin device

    // GPIO32->GPIO32->EEV_2H
    GPIO_setPinConfig(GPIO_32_GPIO32);
    GPIO_writePin(32, 0);       // Default output is Low
    GPIO_setDirectionMode(32, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(32, GPIO_PIN_TYPE_PULLUP);

    // GPIO33->GPIO33->EMI_RESET
    GPIO_setPinConfig(GPIO_33_GPIO33);
    GPIO_writePin(33, 0);       // Default output is LOW
    GPIO_setDirectionMode(33, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(33, GPIO_PIN_TYPE_STD);

    // GPIO34 is not available on this 64-pin device

    // GPIO35->SCIC_RX->System RX
    GPIO_setPinConfig(GPIO_35_SCIC_RX);
    GPIO_setDirectionMode(35, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(35, GPIO_PIN_TYPE_PULLUP);

    // GPIO37->SCIC_TX->System_TX
    GPIO_setPinConfig(GPIO_37_SCIC_TX);
    GPIO_setDirectionMode(37, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(37, GPIO_PIN_TYPE_PULLUP);

    // GPIO39->GPIO39->Inrush Power Rleay (DMCPFC_REV3P1) or FW way relay (DMCPFC_REV3P2)
    GPIO_setPinConfig(GPIO_39_GPIO39);
    GPIO_writePin(39, 0);       // Default output is LOW
    GPIO_setDirectionMode(39, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(39, GPIO_PIN_TYPE_STD);

    // GPIO40->EPWM2_B->FAN_WL
    GPIO_setPinConfig(GPIO_40_EPWM2_B);
    GPIO_setDirectionMode(40, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(40, GPIO_PIN_TYPE_STD);

    // GPIO41->EPWM2_A->FAN_WH
    GPIO_setPinConfig(GPIO_41_EPWM2_A);
    GPIO_setDirectionMode(41, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(41, GPIO_PIN_TYPE_STD);

    // GPIO42~GPIO46 are not available on this 64-pin device
  // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    // GPIO0->EPWM1A->M1_UH
    GPIO_setPinConfig(GPIO_0_EPWM1_A);
    GPIO_setDirectionMode(0, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD);

    // GPIO1->EPWM1B->M1_UL
    GPIO_setPinConfig(GPIO_1_EPWM1_B);
    GPIO_setDirectionMode(1, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(1, GPIO_PIN_TYPE_STD);

    // GPIO2->EPWM2A->M1_VH
    GPIO_setPinConfig(GPIO_2_EPWM2_A);
    GPIO_setDirectionMode(2, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(2, GPIO_PIN_TYPE_STD);

    // GPIO3->EPWM2B->M1_VL
    GPIO_setPinConfig(GPIO_3_EPWM2_B);
    GPIO_setDirectionMode(3, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(3, GPIO_PIN_TYPE_STD);

    // GPIO4->EPWM3A->M1_WH
    GPIO_setPinConfig(GPIO_4_EPWM3_A);
    GPIO_setDirectionMode(4, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(4, GPIO_PIN_TYPE_STD);

    // GPIO5->EPWM3B->M1_WL
    GPIO_setPinConfig(GPIO_5_EPWM3_B);
    GPIO_setDirectionMode(5, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(5, GPIO_PIN_TYPE_STD);

    // GPIO6->EPWM4A->PFC_1H
    GPIO_setPinConfig(GPIO_6_EPWM4_A);
    GPIO_setDirectionMode(6, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(6, GPIO_PIN_TYPE_STD);

    // GPIO7->EPWM4B->PFC_1L
    GPIO_setPinConfig(GPIO_7_EPWM4_B);
    GPIO_setDirectionMode(7, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(7, GPIO_PIN_TYPE_STD);

    // GPIO8->Reserve
    GPIO_setPinConfig(GPIO_8_GPIO8);
    GPIO_setDirectionMode(8, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(8, GPIO_PIN_TYPE_STD);

    // GPIO09->CLR-Fault
    GPIO_setPinConfig(GPIO_9_GPIO9);
    GPIO_writePin(9, 1);
    GPIO_setDirectionMode(9, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(9, GPIO_PIN_TYPE_PULLUP);

#if defined(EPWMDAC_MODE)
    // GPIO10->PWM6A->DAC1
    GPIO_setPinConfig(GPIO_10_EPWM6_A);
    GPIO_setDirectionMode(10, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(10, GPIO_PIN_TYPE_STD);
#else   // !EPWMDAC_MODE
    // GPIO10->Reserve
    GPIO_setPinConfig(GPIO_10_GPIO10);
    GPIO_setDirectionMode(10, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(10, GPIO_PIN_TYPE_STD);
#endif

#if defined(EPWMDAC_MODE)
    // GPIO11-> PWM6B->DAC2
    GPIO_setPinConfig(GPIO_11_EPWM6_B);
    GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(11, GPIO_PIN_TYPE_STD);
#else   // !EPWMDAC_MODE
    // GPIO11-> PWM6B->DAC2
    GPIO_setPinConfig(GPIO_11_GPIO11);
    GPIO_setDirectionMode(11, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(11, GPIO_PIN_TYPE_STD);
#endif

#if defined(EPWMDAC_MODE)
    // GPIO12-> PWM7A->DAC3
    GPIO_setPinConfig(GPIO_12_EPWM7_A);
    GPIO_setDirectionMode(12, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(12, GPIO_PIN_TYPE_STD);
#else   // !EPWMDAC_MODE
    // GPIO12-> PWM7A->DAC3
    GPIO_setPinConfig(GPIO_12_GPIO12);
    GPIO_setDirectionMode(12, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(12, GPIO_PIN_TYPE_STD);
#endif

#if defined(EPWMDAC_MODE)
    // GPIO13-> PWM7B->DAC4
    GPIO_setPinConfig(GPIO_13_EPWM7_B);
    GPIO_setDirectionMode(13, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(13, GPIO_PIN_TYPE_STD);
#else   // !EPWMDAC_MODE
    // GPIO13-> PWM7B->DAC4
    GPIO_setPinConfig(GPIO_13_GPIO13);
    GPIO_setDirectionMode(13, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(13, GPIO_PIN_TYPE_STD);
#endif

    // GPIO16->EPWM5A
#if defined(DAC128S_SPIA) && defined(DAC128S_ENABLE)
    GPIO_setPinConfig(GPIO_16_SPIA_SIMO);
    GPIO_setDirectionMode(16, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(16, GPIO_PIN_TYPE_PULLUP);
#else
    GPIO_setPinConfig(GPIO_16_EPWM5_A);
    GPIO_setDirectionMode(16, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(16, GPIO_PIN_TYPE_STD);
#endif  // !defined(DAC128S_SPIA) || !defined(DAC128S_ENABLE)

    // GPIO17->EPWM5B
#if defined(DAC128S_SPIA) && defined(DAC128S_ENABLE)
    GPIO_setPinConfig(GPIO_17_SPIA_SOMI);
    GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(17, GPIO_PIN_TYPE_PULLUP);
#else
    GPIO_setPinConfig(GPIO_17_EPWM5_B);
    GPIO_setDirectionMode(17, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(17, GPIO_PIN_TYPE_STD);
#endif  // !defined(DAC128S_SPIA) || !defined(DAC128S_ENABLE)

    // GPIO18->Reserve
#if defined(DAC128S_SPIA) && defined(DAC128S_ENABLE)
    GPIO_setPinConfig(GPIO_18_SPIA_CLK);
    GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(18, GPIO_PIN_TYPE_PULLUP);
#else
    GPIO_setPinConfig(GPIO_18_GPIO18);
    GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(18, GPIO_PIN_TYPE_STD);
#endif  // !defined(DAC128S_SPIA) || !defined(DAC128S_ENABLE)

    // GPIO19->Reserve
#if defined(DAC128S_SPIA) && defined(DAC128S_ENABLE)
    GPIO_setPinConfig(GPIO_19_SPIA_STE);
    GPIO_setDirectionMode(19, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(19, GPIO_PIN_TYPE_PULLUP);
#else
    GPIO_setPinConfig(GPIO_19_GPIO19);
    GPIO_setDirectionMode(19, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(19, GPIO_PIN_TYPE_STD);
#endif  // !defined(DAC128S_SPIA) || !defined(DAC128S_ENABLE)

    // GPIO22->Reserve
    GPIO_setPinConfig(GPIO_22_GPIO22);
    GPIO_setDirectionMode(22, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(22, GPIO_PIN_TYPE_STD);

    // GPIO23->QEPI/ ->
#if defined(DAC128S_SPIB) && defined(DAC128S_ENABLE)
    GPIO_setPinConfig(GPIO_23_SPIB_STE);
    GPIO_setDirectionMode(23, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(23, GPIO_PIN_TYPE_PULLUP);
#else
    GPIO_setPinConfig(GPIO_23_EQEP1_INDEX);
    GPIO_setDirectionMode(23, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(23, GPIO_PIN_TYPE_STD);
#endif  // !defined(DAC128S_SPIB) || !defined(DAC128S_ENABLE)

    // GPIO24->CAP1
#if defined(DAC128S_SPIB) && defined(DAC128S_ENABLE)
    GPIO_setPinConfig(GPIO_24_SPIB_SIMO);
    GPIO_setDirectionMode(24, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(24, GPIO_PIN_TYPE_PULLUP);
#else
    GPIO_setPinConfig(GPIO_24_GPIO24);
    GPIO_setDirectionMode(24, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(24, GPIO_PIN_TYPE_STD);
#endif  // !defined(DAC128S_SPIB) || !defined(DAC128S_ENABLE)

    // GPIO28->SCIA_RX
    GPIO_setPinConfig(GPIO_28_SCIA_RX);
    GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(28, GPIO_PIN_TYPE_STD);

    // GPIO28->SCIA_TX
    GPIO_setPinConfig(GPIO_29_SCIA_TX);
    GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(29, GPIO_PIN_TYPE_STD);

    // GPIO32->AC Power Relay
    GPIO_setPinConfig(GPIO_32_GPIO32);
    GPIO_writePin(32, 0);
    GPIO_setDirectionMode(32, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(32, GPIO_PIN_TYPE_STD);

    // GPIO33->Four Way Relay
    GPIO_setPinConfig(GPIO_33_GPIO33);
    GPIO_writePin(33, 0);
    GPIO_setDirectionMode(33, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(33, GPIO_PIN_TYPE_STD);

    // TDI
    GPIO_setPinConfig(GPIO_35_TDI);

    // TDO
    GPIO_setPinConfig(GPIO_37_TDO);

    // GPIO39->nFault
    GPIO_setPinConfig(GPIO_39_GPIO39);
    GPIO_setDirectionMode(39, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(39, GPIO_PIN_TYPE_STD);

    // QEPA
    GPIO_setPinConfig(GPIO_40_EQEP1_A);
    GPIO_setDirectionMode(40, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(40, GPIO_PIN_TYPE_STD);

    // QEPB
    GPIO_setPinConfig(GPIO_41_EQEP1_B);
    GPIO_setDirectionMode(41, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(41, GPIO_PIN_TYPE_STD);

#elif defined(BSXL8323RH_REVB)
    // GPIO0->EPWM1A->M1_UH*
    GPIO_setPinConfig(GPIO_0_EPWM1_A);
    GPIO_setDirectionMode(0, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(0, GPIO_PIN_TYPE_STD);

    // GPIO1->EPWM1B->M1_UL*
    GPIO_setPinConfig(GPIO_1_EPWM1_B);
    GPIO_setDirectionMode(1, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(1, GPIO_PIN_TYPE_STD);

    // GPIO2->EPWM2A->M1_VH*
    GPIO_setPinConfig(GPIO_2_EPWM2_A);
    GPIO_setDirectionMode(2, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(2, GPIO_PIN_TYPE_STD);

    // GPIO3->EPWM2B->M1_VL*
    GPIO_setPinConfig(GPIO_3_EPWM2_B);
    GPIO_setDirectionMode(3, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(3, GPIO_PIN_TYPE_STD);

    // GPIO4->EPWM3A->M1_WH*
    GPIO_setPinConfig(GPIO_4_EPWM3_A);
    GPIO_setDirectionMode(4, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(4, GPIO_PIN_TYPE_STD);

    // GPIO5->Switch Button for testing flying start
    GPIO_setPinConfig(GPIO_5_GPIO5);
    GPIO_setDirectionMode(5, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(5, GPIO_PIN_TYPE_PULLUP);

    // GPIO6->EPWM4A->M2_VH*
    GPIO_setPinConfig(GPIO_6_EPWM4_A);
    GPIO_setDirectionMode(6, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(6, GPIO_PIN_TYPE_STD);

    // GPIO7->EPWM4B->M2_VL*
    GPIO_setPinConfig(GPIO_7_EPWM4_B);
    GPIO_setDirectionMode(7, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(7, GPIO_PIN_TYPE_STD);

    // GPIO8->M1_DRV_nSCS/GAIN
    GPIO_setPinConfig(GPIO_8_GPIO8);
    GPIO_setDirectionMode(8, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(8, GPIO_PIN_TYPE_STD);

    // GPIO09->reserve for verify the control
    GPIO_setPinConfig(GPIO_9_OUTPUTXBAR6);
    GPIO_setDirectionMode(9, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(9, GPIO_PIN_TYPE_PULLUP);

    // GPIO10->EPWM6A->Simulate PFC PWM
    GPIO_setPinConfig(GPIO_10_EPWM6_A);
    GPIO_setDirectionMode(10, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(10, GPIO_PIN_TYPE_PULLUP);

    // GPIO11->EPWM6B->Simulate PFC PWM
    GPIO_setPinConfig(GPIO_11_EPWM6_B);
    GPIO_setDirectionMode(11, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(11, GPIO_PIN_TYPE_PULLUP);

    // GPIO12->EPWM7A->M2_UH*
    GPIO_setPinConfig(GPIO_12_EPWM7_A);
    GPIO_setDirectionMode(12, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(12, GPIO_PIN_TYPE_STD);

    // GPIO13->EPWM7B->M2_UL*
    GPIO_setPinConfig(GPIO_13_EPWM7_B);
    GPIO_setDirectionMode(13, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(13, GPIO_PIN_TYPE_STD);

    // GPIO16->EPWM5A->M2_WH*
    GPIO_setPinConfig(GPIO_16_EPWM5_A);
    GPIO_setDirectionMode(16, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(16, GPIO_PIN_TYPE_STD);

    // GPIO17->EPWM5B->M2_WL*
    GPIO_setPinConfig(GPIO_17_EPWM5_B);
    GPIO_setDirectionMode(17, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(17, GPIO_PIN_TYPE_STD);

    // GPIO18->GPIO18->FW way relay (DMCPFC_REV3P1) / Inrush Power Rleay (DMCPFC_REV3P2)
    GPIO_setPinConfig(GPIO_18_GPIO18);
    GPIO_writePin(18, 0);       // Default output is LOW
    GPIO_setDirectionMode(18, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(18, GPIO_PIN_TYPE_STD);

    // GPIO10->EPWM6_A->M2_VH->Low
    GPIO_setPinConfig(GPIO_19_GPIO19);
    GPIO_writePin(19, 0);       // Default output is LOW
    GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(19, GPIO_PIN_TYPE_STD);

    // GPIO23->
    GPIO_setPinConfig(GPIO_23_GPIO23);
    GPIO_setDirectionMode(23, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(23, GPIO_PIN_TYPE_STD);

    // GPIO24->M2_DRV_ENABLE*
    GPIO_setPinConfig(GPIO_24_GPIO24);
    GPIO_writePin(24, 1);
    GPIO_setDirectionMode(24, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(24, GPIO_PIN_TYPE_PULLUP);

    // GPIO28->M1_DRV_ENABLE
    GPIO_setPinConfig(GPIO_28_GPIO28);
    GPIO_writePin(28, 1);
    GPIO_setDirectionMode(28, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(28, GPIO_PIN_TYPE_PULLUP);

    // GPIO29->M1_DRV_ENABLE*
    GPIO_setPinConfig(GPIO_29_GPIO29);
    GPIO_writePin(29, 1);
    GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(29, GPIO_PIN_TYPE_PULLUP);

    // GPIO32->M2_DRV_nSCS/GAIN*
    GPIO_setPinConfig(GPIO_32_GPIO32);
    GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(32, GPIO_PIN_TYPE_STD);

#if  defined(DAC128S_ENABLE) && defined(DAC128S_SPIB)
    // GPIO33->DAC128S_SYNC
    GPIO_setPinConfig(GPIO_33_SPIB_STE);
    GPIO_writePin(33, 1);
    GPIO_setDirectionMode(33, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(33, GPIO_PIN_TYPE_PULLUP);
#else
    // GPIO33->Reserve
    GPIO_setPinConfig(GPIO_33_GPIO33);
    GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(33, GPIO_PIN_TYPE_STD);
#endif

    // GPIO35->TEST_PFC
    GPIO_setPinConfig(GPIO_35_GPIO35);
    GPIO_setDirectionMode(35, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(35, GPIO_PIN_TYPE_STD);

    // GPIO37->EQEP1_B*
    GPIO_setPinConfig(GPIO_37_EQEP1_B);
    GPIO_setDirectionMode(37, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(37, GPIO_PIN_TYPE_STD);

    // GPIO39->TEST_M1
    GPIO_setPinConfig(GPIO_39_GPIO39);
    GPIO_setDirectionMode(39, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(39, GPIO_PIN_TYPE_STD);

    // GPIO40->TEST_M2
    GPIO_setPinConfig(GPIO_40_GPIO40);
    GPIO_setDirectionMode(40, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(40, GPIO_PIN_TYPE_STD);

    // GPIO41->M1_DRV_nFAULT
    GPIO_setPinConfig(GPIO_41_GPIO41);
    GPIO_setDirectionMode(41, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(41, GPIO_PIN_TYPE_STD);

#else
#error Not select a right board to configure the GPIO
#endif

    return;
}  // end of HAL_setupGPIOs() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupPWMsMTR(HAL_MTR_Handle handle)        // f280013x
{
    HAL_MTR_Obj    *obj = (HAL_MTR_Obj *)handle;
    uint16_t  cnt;

    uint16_t       pwmPeriodCycles;
    uint16_t       numPWMTicksPerISRTick;

    uint16_t       pwmDBRED;
    uint16_t       pwmDBFED;

    // turns off the outputs of the EPWM peripherals which will put the power
    // switches into a high impedance state.
    EPWM_forceTripZoneEvent(obj->pwmHandle[0], EPWM_TZ_FORCE_EVENT_OST);
    EPWM_forceTripZoneEvent(obj->pwmHandle[1], EPWM_TZ_FORCE_EVENT_OST);
    EPWM_forceTripZoneEvent(obj->pwmHandle[2], EPWM_TZ_FORCE_EVENT_OST);

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)   || \
    defined(HVMTRPFC_REV1P1) || defined(BSXL8323RH_REVB)
    if(obj->motorNum == MTR_1)
    {
        pwmPeriodCycles = (uint16_t)(USER_M1_PWM_TBPRD_NUM);
        numPWMTicksPerISRTick = USER_M1_NUM_PWM_TICKS_PER_ISR_TICK;

        pwmDBRED = MTR1_PWM_DBRED_CNT;
        pwmDBFED = MTR1_PWM_DBFED_CNT;

        for(cnt=0; cnt<3; cnt++)
        {
            // setup the Time-Base Control Register (TBCTL)
            EPWM_setTimeBaseCounterMode(obj->pwmHandle[cnt],
                                        EPWM_COUNTER_MODE_UP_DOWN);

            EPWM_disablePhaseShiftLoad(obj->pwmHandle[cnt]);

            EPWM_setPeriodLoadMode(obj->pwmHandle[cnt], EPWM_PERIOD_DIRECT_LOAD);

            EPWM_enableSyncOutPulseSource(obj->pwmHandle[cnt],
                                          EPWM_SYNC_OUT_PULSE_ON_SOFTWARE);

            EPWM_setClockPrescaler(obj->pwmHandle[cnt], EPWM_CLOCK_DIVIDER_1,
                                     EPWM_HSCLOCK_DIVIDER_1);

            EPWM_setCountModeAfterSync(obj->pwmHandle[cnt],
                                       EPWM_COUNT_MODE_UP_AFTER_SYNC);

            EPWM_setEmulationMode(obj->pwmHandle[cnt], EPWM_EMULATION_FREE_RUN);

            // setup the Timer-Based Phase Register (TBPHS)
            EPWM_setPhaseShift(obj->pwmHandle[cnt], 0);

            // setup the Time-Base Counter Register (TBCTR)
            EPWM_setTimeBaseCounter(obj->pwmHandle[cnt], 0);

            // setup the Time-Base Period Register (TBPRD)
            // set to zero initially
            EPWM_setTimeBasePeriod(obj->pwmHandle[cnt], 0);

            // setup the Counter-Compare Control Register (CMPCTL)
            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_A,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);

            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_B,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);

            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_C,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);

            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_D,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);

#if defined(MOTOR1_DCLINKSS)
            // setup the Action-Qualifier Output A Register (AQCTLA)
            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
#else   // !MOTOR1_DCLINKSS
            // setup the Action-Qualifier Output A Register (AQCTLA)
            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
#endif  // !MOTOR1_DCLINKSS

            // setup the Dead-Band Generator Control Register (DBCTL)
            EPWM_setDeadBandDelayMode(obj->pwmHandle[cnt], EPWM_DB_RED, true);
            EPWM_setDeadBandDelayMode(obj->pwmHandle[cnt], EPWM_DB_FED, true);

            // select EPWMA as the input to the dead band generator
            EPWM_setRisingEdgeDeadBandDelayInput(obj->pwmHandle[cnt],
                                                 EPWM_DB_INPUT_EPWMA);

            // configure the right polarity for active high complementary config.
            EPWM_setDeadBandDelayPolarity(obj->pwmHandle[cnt],
                                          EPWM_DB_RED,
                                          EPWM_DB_POLARITY_ACTIVE_HIGH);
            EPWM_setDeadBandDelayPolarity(obj->pwmHandle[cnt],
                                          EPWM_DB_FED,
                                          EPWM_DB_POLARITY_ACTIVE_LOW);

            // setup the Dead-Band Rising Edge Delay Register (DBRED)
            EPWM_setRisingEdgeDelayCount(obj->pwmHandle[cnt], pwmDBRED);

            // setup the Dead-Band Falling Edge Delay Register (DBFED)
            EPWM_setFallingEdgeDelayCount(obj->pwmHandle[cnt], pwmDBFED);

            // setup the PWM-Chopper Control Register (PCCTL)
            EPWM_disableChopper(obj->pwmHandle[cnt]);

            // setup the Trip Zone Select Register (TZSEL)
            EPWM_disableTripZoneSignals(obj->pwmHandle[cnt], HAL_TZSEL_SIGNALS_ALL);
        }

#if defined(MOTOR1_DCLINKSS)
        // setup the Event Trigger Selection Register (ETSEL)
        EPWM_setInterruptSource(obj->pwmHandle[0], EPWM_INT_TBCTR_ZERO);

        EPWM_enableInterrupt(obj->pwmHandle[0]);

        EPWM_setADCTriggerSource(obj->pwmHandle[0], EPWM_SOC_A,
                                 EPWM_SOC_TBCTR_ZERO);

        EPWM_enableADCTrigger(obj->pwmHandle[0], EPWM_SOC_A);

        // ADC SOC trigger for the 1st dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[1],
                                     EPWM_SOC_A,
                                     EPWM_SOC_TBCTR_U_CMPC);

        EPWM_enableADCTrigger(obj->pwmHandle[1], EPWM_SOC_A);

        // ADC SOC trigger for the 2nd dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[1],
                                 EPWM_SOC_B,
                                 EPWM_SOC_TBCTR_U_CMPD);

        EPWM_enableADCTrigger(obj->pwmHandle[1], EPWM_SOC_B);

        // ADC SOC trigger for the 3rd dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[2],
                                     EPWM_SOC_A,
                                     EPWM_SOC_TBCTR_D_CMPC);

        EPWM_enableADCTrigger(obj->pwmHandle[2], EPWM_SOC_A);

        // ADC SOC trigger for the 4th dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[2],
                                 EPWM_SOC_B,
                                 EPWM_SOC_TBCTR_D_CMPD);

        EPWM_enableADCTrigger(obj->pwmHandle[2], EPWM_SOC_B);

        // setup the Event Trigger Prescale Register (ETPS)
        if(numPWMTicksPerISRTick > 15)
        {
            EPWM_setInterruptEventCount(obj->pwmHandle[0], 15);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A, 15);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_A, 15);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_B, 15);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_A, 15);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_B, 15);
        }
        else if(numPWMTicksPerISRTick < 1)
        {
            EPWM_setInterruptEventCount(obj->pwmHandle[0], 1);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A, 1);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_A, 1);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_B, 1);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_A, 1);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_B, 1);
        }
        else
        {
            EPWM_setInterruptEventCount(obj->pwmHandle[0], numPWMTicksPerISRTick);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A,
                                            numPWMTicksPerISRTick);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_A,
                                            numPWMTicksPerISRTick);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_B,
                                            numPWMTicksPerISRTick);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_A,
                                            numPWMTicksPerISRTick);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_B,
                                            numPWMTicksPerISRTick);
        }

        // setup the Event Trigger Clear Register (ETCLR)
        EPWM_clearEventTriggerInterruptFlag(obj->pwmHandle[0]);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[0], EPWM_SOC_A);

        EPWM_clearADCTriggerFlag(obj->pwmHandle[1], EPWM_SOC_A);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[1], EPWM_SOC_B);

        EPWM_clearADCTriggerFlag(obj->pwmHandle[2], EPWM_SOC_A);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[2], EPWM_SOC_B);

        // since the PWM is configured as an up/down counter, the period register is
        // set to one-half of the desired PWM period
        EPWM_setTimeBasePeriod(obj->pwmHandle[0], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[1], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[2], pwmPeriodCycles);

        // write the PWM data value  for ADC trigger
        EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                    EPWM_COUNTER_COMPARE_C, pwmPeriodCycles>>1);
        EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                    EPWM_COUNTER_COMPARE_D, pwmPeriodCycles>>1);

        EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                    EPWM_COUNTER_COMPARE_C, pwmPeriodCycles>>1);
        EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                    EPWM_COUNTER_COMPARE_D, pwmPeriodCycles>>1);
#else   // !MOTOR1_DCLINKSS
        // setup the Event Trigger Selection Register (ETSEL)
        EPWM_setInterruptSource(obj->pwmHandle[0], EPWM_INT_TBCTR_ZERO);

        EPWM_setADCTriggerSource(obj->pwmHandle[0], EPWM_SOC_A,
                                 EPWM_SOC_TBCTR_ZERO);

        EPWM_enableADCTrigger(obj->pwmHandle[0], EPWM_SOC_A);

        // setup the Event Trigger Prescale Register (ETPS)
        if(numPWMTicksPerISRTick > 15)
        {
            numPWMTicksPerISRTick = 15;
        }
        else if(numPWMTicksPerISRTick < 1)
        {
            numPWMTicksPerISRTick = 1;
        }

        EPWM_setInterruptEventCount(obj->pwmHandle[0], numPWMTicksPerISRTick);
        EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A,
                                        numPWMTicksPerISRTick);

        // setup the Event Trigger Clear Register (ETCLR)
        EPWM_clearEventTriggerInterruptFlag(obj->pwmHandle[0]);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[0], EPWM_SOC_A);

        // since the PWM is configured as an up/down counter, the period register is
        // set to one-half of the desired PWM period
        EPWM_setTimeBasePeriod(obj->pwmHandle[0], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[1], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[2], pwmPeriodCycles);
#endif  // !MOTOR1_DCLINKSS

    }
    else if(obj->motorNum == MTR_2)
    {
        pwmPeriodCycles = (uint16_t)(USER_M2_PWM_TBPRD_NUM);
        numPWMTicksPerISRTick = USER_M2_NUM_PWM_TICKS_PER_ISR_TICK;

        pwmDBRED = MTR2_PWM_DBRED_CNT;
        pwmDBFED = MTR2_PWM_DBFED_CNT;

        for(cnt=0; cnt<3; cnt++)
        {
            // setup the Time-Base Control Register (TBCTL)
            EPWM_setTimeBaseCounterMode(obj->pwmHandle[cnt],
                                        EPWM_COUNTER_MODE_UP_DOWN);

            EPWM_disablePhaseShiftLoad(obj->pwmHandle[cnt]);

            EPWM_setPeriodLoadMode(obj->pwmHandle[cnt], EPWM_PERIOD_DIRECT_LOAD);

            EPWM_enableSyncOutPulseSource(obj->pwmHandle[cnt],
                                          EPWM_SYNC_OUT_PULSE_ON_SOFTWARE);

            EPWM_setClockPrescaler(obj->pwmHandle[cnt], EPWM_CLOCK_DIVIDER_1,
                                     EPWM_HSCLOCK_DIVIDER_1);

            EPWM_setCountModeAfterSync(obj->pwmHandle[cnt],
                                       EPWM_COUNT_MODE_UP_AFTER_SYNC);

            EPWM_setEmulationMode(obj->pwmHandle[cnt], EPWM_EMULATION_FREE_RUN);

            // setup the Timer-Based Phase Register (TBPHS)
            EPWM_setPhaseShift(obj->pwmHandle[cnt], 0);

            // setup the Time-Base Counter Register (TBCTR)
            EPWM_setTimeBaseCounter(obj->pwmHandle[cnt], 0);

            // setup the Time-Base Period Register (TBPRD)
            // set to zero initially
            EPWM_setTimeBasePeriod(obj->pwmHandle[cnt], 0);

            // setup the Counter-Compare Control Register (CMPCTL)
            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_A,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);

            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_B,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);

            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_C,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);

            EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                                 EPWM_COUNTER_COMPARE_D,
                                                 EPWM_COMP_LOAD_ON_CNTR_ZERO);
#if defined(MOTOR2_DCLINKSS)
            // setup the Action-Qualifier Output A Register (AQCTLA)
            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
#else   // !MOTOR2_DCLINKSS
            // setup the Action-Qualifier Output A Register (AQCTLA)
            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_LOW,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

            EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                          EPWM_AQ_OUTPUT_A,
                                          EPWM_AQ_OUTPUT_HIGH,
                                          EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);
#endif  // !MOTOR2_DCLINKSS

            // setup the Dead-Band Generator Control Register (DBCTL)
            EPWM_setDeadBandDelayMode(obj->pwmHandle[cnt], EPWM_DB_RED, true);
            EPWM_setDeadBandDelayMode(obj->pwmHandle[cnt], EPWM_DB_FED, true);

            // select EPWMA as the input to the dead band generator
            EPWM_setRisingEdgeDeadBandDelayInput(obj->pwmHandle[cnt],
                                                 EPWM_DB_INPUT_EPWMA);

            // configure the right polarity for active high complementary config.
            EPWM_setDeadBandDelayPolarity(obj->pwmHandle[cnt],
                                          EPWM_DB_RED,
                                          EPWM_DB_POLARITY_ACTIVE_HIGH);
            EPWM_setDeadBandDelayPolarity(obj->pwmHandle[cnt],
                                          EPWM_DB_FED,
                                          EPWM_DB_POLARITY_ACTIVE_LOW);

            // setup the Dead-Band Rising Edge Delay Register (DBRED)
            EPWM_setRisingEdgeDelayCount(obj->pwmHandle[cnt], pwmDBRED);

            // setup the Dead-Band Falling Edge Delay Register (DBFED)
            EPWM_setFallingEdgeDelayCount(obj->pwmHandle[cnt], pwmDBFED);

            // setup the PWM-Chopper Control Register (PCCTL)
            EPWM_disableChopper(obj->pwmHandle[cnt]);

            // setup the Trip Zone Select Register (TZSEL)
            EPWM_disableTripZoneSignals(obj->pwmHandle[cnt], HAL_TZSEL_SIGNALS_ALL);
        }
#if defined(MOTOR2_DCLINKSS)
#ifndef MOTOR2_DISABLE
        // setup the Event Trigger Selection Register (ETSEL)
        EPWM_setInterruptSource(obj->pwmHandle[0], EPWM_INT_TBCTR_ZERO);

        EPWM_enableInterrupt(obj->pwmHandle[0]);

        EPWM_setADCTriggerSource(obj->pwmHandle[0], EPWM_SOC_A,
                                 EPWM_SOC_TBCTR_ZERO);

        EPWM_enableADCTrigger(obj->pwmHandle[0], EPWM_SOC_A);
#endif  // !MOTOR2_DISABLE

        // ADC SOC trigger for the 1st dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[1],
                                     EPWM_SOC_A,
                                     EPWM_SOC_TBCTR_U_CMPC);

        EPWM_enableADCTrigger(obj->pwmHandle[1], EPWM_SOC_A);

        // ADC SOC trigger for the 2nd dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[1],
                                 EPWM_SOC_B,
                                 EPWM_SOC_TBCTR_U_CMPD);

        EPWM_enableADCTrigger(obj->pwmHandle[1], EPWM_SOC_B);

        // ADC SOC trigger for the 3rd dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[2],
                                     EPWM_SOC_A,
                                     EPWM_SOC_TBCTR_D_CMPC);

        EPWM_enableADCTrigger(obj->pwmHandle[2], EPWM_SOC_A);

        // ADC SOC trigger for the 4th dc-link current sampling
        EPWM_setADCTriggerSource(obj->pwmHandle[2],
                                 EPWM_SOC_B,
                                 EPWM_SOC_TBCTR_D_CMPD);

        EPWM_enableADCTrigger(obj->pwmHandle[2], EPWM_SOC_B);

        // setup the Event Trigger Prescale Register (ETPS)
        if(numPWMTicksPerISRTick > 15)
        {
            EPWM_setInterruptEventCount(obj->pwmHandle[0], 15);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A, 15);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_A, 15);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_B, 15);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_A, 15);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_B, 15);
        }
        else if(numPWMTicksPerISRTick < 1)
        {
            EPWM_setInterruptEventCount(obj->pwmHandle[0], 1);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A, 1);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_A, 1);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_B, 1);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_A, 1);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_B, 1);
        }
        else
        {
            EPWM_setInterruptEventCount(obj->pwmHandle[0], numPWMTicksPerISRTick);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A,
                                            numPWMTicksPerISRTick);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_A,
                                            numPWMTicksPerISRTick);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[1], EPWM_SOC_B,
                                            numPWMTicksPerISRTick);

            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_A,
                                            numPWMTicksPerISRTick);
            EPWM_setADCTriggerEventPrescale(obj->pwmHandle[2], EPWM_SOC_B,
                                            numPWMTicksPerISRTick);
        }

        // setup the Event Trigger Clear Register (ETCLR)
        EPWM_clearEventTriggerInterruptFlag(obj->pwmHandle[0]);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[0], EPWM_SOC_A);

        EPWM_clearADCTriggerFlag(obj->pwmHandle[1], EPWM_SOC_A);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[1], EPWM_SOC_B);

        EPWM_clearADCTriggerFlag(obj->pwmHandle[2], EPWM_SOC_A);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[2], EPWM_SOC_B);

        // since the PWM is configured as an up/down counter, the period register is
        // set to one-half of the desired PWM period
        EPWM_setTimeBasePeriod(obj->pwmHandle[0], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[1], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[2], pwmPeriodCycles);

        // write the PWM data value  for ADC trigger
        EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                    EPWM_COUNTER_COMPARE_C, pwmPeriodCycles>>1);
        EPWM_setCounterCompareValue(obj->pwmHandle[1],
                                    EPWM_COUNTER_COMPARE_D, pwmPeriodCycles>>1);

        EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                    EPWM_COUNTER_COMPARE_C, pwmPeriodCycles>>1);
        EPWM_setCounterCompareValue(obj->pwmHandle[2],
                                    EPWM_COUNTER_COMPARE_D, pwmPeriodCycles>>1);
#else   // !MOTOR2_DCLINKSS
#ifndef MOTOR2_DISABLE
        // setup the Event Trigger Selection Register (ETSEL)
        EPWM_setInterruptSource(obj->pwmHandle[0], EPWM_INT_TBCTR_ZERO);

        EPWM_setADCTriggerSource(obj->pwmHandle[0], EPWM_SOC_A,
                                 EPWM_SOC_TBCTR_ZERO);

        EPWM_enableADCTrigger(obj->pwmHandle[0], EPWM_SOC_A);
#endif  // !MOTOR2_DISABLE

        // setup the Event Trigger Prescale Register (ETPS)
        if(numPWMTicksPerISRTick > 15)
        {
            numPWMTicksPerISRTick = 15;
        }
        else if(numPWMTicksPerISRTick < 1)
        {
            numPWMTicksPerISRTick = 1;
        }

        EPWM_setInterruptEventCount(obj->pwmHandle[0], numPWMTicksPerISRTick);
        EPWM_setADCTriggerEventPrescale(obj->pwmHandle[0], EPWM_SOC_A,
                                        numPWMTicksPerISRTick);

        // setup the Event Trigger Clear Register (ETCLR)
        EPWM_clearEventTriggerInterruptFlag(obj->pwmHandle[0]);
        EPWM_clearADCTriggerFlag(obj->pwmHandle[0], EPWM_SOC_A);

        // since the PWM is configured as an up/down counter, the period register is
        // set to one-half of the desired PWM period
        EPWM_setTimeBasePeriod(obj->pwmHandle[0], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[1], pwmPeriodCycles);
        EPWM_setTimeBasePeriod(obj->pwmHandle[2], pwmPeriodCycles);
#endif  // !MOTOR2_DCLINKSS
    }
    // DMCPFC_REV3P2 | DMCPFC_REV3P1 | HVMTRPFC_REV1P1 | BSXL8323RH_REVB
#else
#error Not select a right board to clear the fault trip flag for motors
#endif  // No Hardware Boards

    return;
}  // end of HAL_setupPWMsMTR() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupPWMsPFC(HAL_PFC_Handle handle)        // f280013x
{
    HAL_PFC_Obj    *obj = (HAL_PFC_Obj *)handle;

    uint16_t pwmPeriodCycles = (uint16_t)(USER_PFC_PWM_TBPRD_NUM);
    uint16_t numPWMTicksPerISRTick = USER_PFC_NUM_PWM_TICKS_PER_ISR_TICK;

    // turns off the outputs of the EPWM peripherals which will put the power
    // switches into a high impedance state.
    EPWM_forceTripZoneEvent(obj->pwmHandle, EPWM_TZ_FORCE_EVENT_OST);

    // setup the Time-Base Control Register (TBCTL)
    EPWM_setTimeBaseCounterMode(obj->pwmHandle,
                                EPWM_COUNTER_MODE_UP_DOWN);

    EPWM_disablePhaseShiftLoad(obj->pwmHandle);

    EPWM_setPeriodLoadMode(obj->pwmHandle, EPWM_PERIOD_DIRECT_LOAD);

    EPWM_enableSyncOutPulseSource(obj->pwmHandle,
                                  EPWM_SYNC_OUT_PULSE_ON_SOFTWARE);

    EPWM_setClockPrescaler(obj->pwmHandle, EPWM_CLOCK_DIVIDER_1,
                             EPWM_HSCLOCK_DIVIDER_1);

    EPWM_setCountModeAfterSync(obj->pwmHandle,
                               EPWM_COUNT_MODE_UP_AFTER_SYNC);

    EPWM_setEmulationMode(obj->pwmHandle, EPWM_EMULATION_FREE_RUN);

    // setup the Timer-Based Phase Register (TBPHS)
    EPWM_setPhaseShift(obj->pwmHandle, 0);

    // setup the Time-Base Counter Register (TBCTR)
    EPWM_setTimeBaseCounter(obj->pwmHandle, 0);

    // setup the Time-Base Period Register (TBPRD)
    // set to zero initially
    EPWM_setTimeBasePeriod(obj->pwmHandle, 0);

    // setup the Counter-Compare Control Register (CMPCTL)
    EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle,
                                         EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);

    EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle,
                                         EPWM_COUNTER_COMPARE_B,
                                         EPWM_COMP_LOAD_ON_CNTR_ZERO);

    // setup the Action-Qualifier Output A Register (AQCTLA)
    EPWM_setActionQualifierAction(obj->pwmHandle,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

    EPWM_setActionQualifierAction(obj->pwmHandle,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

    EPWM_setActionQualifierAction(obj->pwmHandle,
                                  EPWM_AQ_OUTPUT_A,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

    // setup the Action-Qualifier Output A Register (AQCTLB)
    EPWM_setActionQualifierAction(obj->pwmHandle,
                                  EPWM_AQ_OUTPUT_B,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);

    EPWM_setActionQualifierAction(obj->pwmHandle,
                                  EPWM_AQ_OUTPUT_B,
                                  EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);

    EPWM_setActionQualifierAction(obj->pwmHandle,
                                  EPWM_AQ_OUTPUT_B,
                                  EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);

    // setup the Dead-Band Generator Control Register (DBCTL)
    EPWM_setDeadBandDelayMode(obj->pwmHandle, EPWM_DB_RED, false);
    EPWM_setDeadBandDelayMode(obj->pwmHandle, EPWM_DB_FED, false);

    // setup the PWM-Chopper Control Register (PCCTL)
    EPWM_disableChopper(obj->pwmHandle);

    // setup the Trip Zone Select Register (TZSEL)
    EPWM_disableTripZoneSignals(obj->pwmHandle, HAL_TZSEL_SIGNALS_ALL);

#ifndef PFC_DISABLE
    // setup the Event Trigger Selection Register (ETSEL)
    EPWM_setInterruptSource(obj->pwmHandle, EPWM_INT_TBCTR_ZERO);

    EPWM_disableInterrupt(obj->pwmHandle);

    EPWM_setADCTriggerSource(obj->pwmHandle,
                             EPWM_SOC_A,
                             EPWM_SOC_TBCTR_PERIOD);

    EPWM_setADCTriggerSource(obj->pwmHandle,
                             EPWM_SOC_B,
                             EPWM_SOC_TBCTR_ZERO);

    EPWM_enableADCTrigger(obj->pwmHandle, EPWM_SOC_A);
    EPWM_enableADCTrigger(obj->pwmHandle, EPWM_SOC_B);
#endif  // PFC_DISABLE

    // setup the Event Trigger Prescale Register (ETPS)
    if(numPWMTicksPerISRTick > 15)
    {
        numPWMTicksPerISRTick = 15;
    }
    else if(numPWMTicksPerISRTick < 1)
    {
        numPWMTicksPerISRTick = 1;
    }

    EPWM_setInterruptEventCount(obj->pwmHandle, numPWMTicksPerISRTick);


    EPWM_setADCTriggerEventPrescale(obj->pwmHandle, EPWM_SOC_A,
                                    numPWMTicksPerISRTick);
    EPWM_setADCTriggerEventPrescale(obj->pwmHandle, EPWM_SOC_B,
                                    numPWMTicksPerISRTick);

    // setup the Event Trigger Clear Register (ETCLR)
    EPWM_clearEventTriggerInterruptFlag(obj->pwmHandle);
    EPWM_clearADCTriggerFlag(obj->pwmHandle, EPWM_SOC_A);
    EPWM_clearADCTriggerFlag(obj->pwmHandle, EPWM_SOC_B);

    // since the PWM is configured as an up/down counter, the period register is
    // set to one-half of the desired PWM period
    EPWM_setTimeBasePeriod(obj->pwmHandle, pwmPeriodCycles);

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_A,
                                pwmPeriodCycles);

    // write the PWM data value
    EPWM_setCounterCompareValue(obj->pwmHandle, EPWM_COUNTER_COMPARE_B,
                                0);

    EPWM_forceTripZoneEvent(obj->pwmHandle, EPWM_TZ_FORCE_EVENT_OST);

    return;
}  // end of HAL_setupPWMsPFC() function
#endif  // !SYSCONFIG_EN

void HAL_setupPWMsPhaseShift(HAL_Handle handle)     // f280013x
{
    HAL_Obj        *obj     = (HAL_Obj *)handle;
    HAL_MTR_Obj    *objMtr1 = (HAL_MTR_Obj *)obj->mtrHandle[0];
    HAL_MTR_Obj    *objMtr2 = (HAL_MTR_Obj *)obj->mtrHandle[1];
    HAL_PFC_Obj    *objPFC  = (HAL_PFC_Obj *)obj->pfcHandle;

    // disable the ePWM module time base clock sync signal
    // to synchronize all of the PWMs
    SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    uint16_t periodPFC = EPWM_getTimeBasePeriod(objPFC->pwmHandle);
    uint16_t periodMtr1 = EPWM_getTimeBasePeriod(objMtr1->pwmHandle[0]);
    uint16_t periodMtr2 = EPWM_getTimeBasePeriod(objMtr2->pwmHandle[0]);

    uint16_t shiftPFC  = PFC_EPWM_SYSN_O_TIME;
    uint16_t shiftMtr1 = periodMtr1 - MTR_EPWM_SYSN_O_TIME;     // with 180' shift between Motor_1 and Motor_2
    uint16_t shiftMtr2 = MTR_EPWM_SYSN_O_TIME;

    // Clear period
    EPWM_setTimeBasePeriod(objPFC->pwmHandle, 0);

    EPWM_setTimeBasePeriod(objMtr1->pwmHandle[0], 0);
    EPWM_setTimeBasePeriod(objMtr1->pwmHandle[1], 0);
    EPWM_setTimeBasePeriod(objMtr1->pwmHandle[2], 0);


    EPWM_setTimeBasePeriod(objMtr2->pwmHandle[0], 0);
    EPWM_setTimeBasePeriod(objMtr2->pwmHandle[1], 0);
    EPWM_setTimeBasePeriod(objMtr2->pwmHandle[2], 0);

    // Clear time base counter
    EPWM_setTimeBaseCounter(objPFC->pwmHandle, 0);

    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[0], 0);
    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[1], 0);
    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[2], 0);

    EPWM_setTimeBaseCounter(objMtr2->pwmHandle[0], 0);
    EPWM_setTimeBaseCounter(objMtr2->pwmHandle[1], 0);
    EPWM_setTimeBaseCounter(objMtr2->pwmHandle[2], 0);

    // Set period
    EPWM_setTimeBasePeriod(objPFC->pwmHandle, periodPFC);

    EPWM_setTimeBasePeriod(objMtr1->pwmHandle[0], periodMtr1);
    EPWM_setTimeBasePeriod(objMtr1->pwmHandle[1], periodMtr1);
    EPWM_setTimeBasePeriod(objMtr1->pwmHandle[2], periodMtr1);


    EPWM_setTimeBasePeriod(objMtr2->pwmHandle[0], periodMtr2);
    EPWM_setTimeBasePeriod(objMtr2->pwmHandle[1], periodMtr2);
    EPWM_setTimeBasePeriod(objMtr2->pwmHandle[2], periodMtr2);

    // enable the ePWM module time base clock sync signal
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);

    EPWM_setTimeBaseCounter(objPFC->pwmHandle, shiftPFC);

    // setup the Time-Base Counter Register (TBCTR)
    EPWM_setTimeBaseCounter(objMtr2->pwmHandle[0], shiftMtr2);
    EPWM_setTimeBaseCounter(objMtr2->pwmHandle[1], shiftMtr2 + 2);
    EPWM_setTimeBaseCounter(objMtr2->pwmHandle[2], shiftMtr2 + 4);

    // setup the Time-Base Counter Register (TBCTR)
    // without phase shift between Motor_1 and Motor_2
//    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[0], shiftMtr2 + 6);
//    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[1], shiftMtr2 + 8);
//    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[2], shiftMtr2 + 10);

    // with 180' shift between Motor_1 and Motor_2
    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[0], shiftMtr1 + 6);
    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[1], shiftMtr1 + 8);
    EPWM_setTimeBaseCounter(objMtr1->pwmHandle[2], shiftMtr1 + 10);


    return;
} // end of HAL_setupPWMsPhaseShift() function

#if defined(EPWMDAC_MODE) && !defined(SYSCONFIG_EN)
void HAL_setupPWMDACs(HAL_Handle handle,
                   const float32_t systemFreq_MHz)
{
    HAL_Obj   *obj = (HAL_Obj *)handle;

    // PWMDAC frequency = 100kHz, calculate the period for pwm
    uint16_t  period_cycles = (uint16_t)(systemFreq_MHz *
                                  (float32_t)(1000.0f / HAL_PWMDAC_FREQ_KHZ));
    uint16_t  cnt;

    for(cnt = 0; cnt < 4; cnt++)
    {
        // setup the Time-Base Control Register (TBCTL)
        EPWM_setTimeBaseCounterMode(obj->pwmDACHandle[cnt],
                                    EPWM_COUNTER_MODE_UP);

        EPWM_disablePhaseShiftLoad(obj->pwmDACHandle[cnt]);

        EPWM_setPeriodLoadMode(obj->pwmDACHandle[cnt], EPWM_PERIOD_DIRECT_LOAD);

        EPWM_enableSyncOutPulseSource(obj->pwmDACHandle[cnt],
                                      EPWM_SYNC_OUT_PULSE_ON_SOFTWARE);

        EPWM_setClockPrescaler(obj->pwmDACHandle[cnt], EPWM_CLOCK_DIVIDER_1,
                                 EPWM_HSCLOCK_DIVIDER_1);

        EPWM_setCountModeAfterSync(obj->pwmDACHandle[cnt],
                                   EPWM_COUNT_MODE_UP_AFTER_SYNC);

        EPWM_setEmulationMode(obj->pwmDACHandle[cnt], EPWM_EMULATION_FREE_RUN);

        // setup the Timer-Based Phase Register (TBPHS)
        EPWM_setPhaseShift(obj->pwmDACHandle[cnt], 0);

        // setup the Time-Base Counter Register (TBCTR)
        EPWM_setTimeBaseCounter(obj->pwmDACHandle[cnt], 0);

        // setup the Time-Base Period Register (TBPRD)
        // set to zero initially
        EPWM_setTimeBasePeriod(obj->pwmDACHandle[cnt], 0);

        // setup the Counter-Compare Control Register (CMPCTL)
        EPWM_setCounterCompareShadowLoadMode(obj->pwmDACHandle[cnt],
                                             EPWM_COUNTER_COMPARE_A,
                                             EPWM_COMP_LOAD_ON_CNTR_ZERO);

        // setup the Action-Qualifier Output A Register (AQCTLA)
        EPWM_setActionQualifierAction(obj->pwmDACHandle[cnt],
                                      EPWM_AQ_OUTPUT_A,
                                      EPWM_AQ_OUTPUT_LOW,
                                      EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

        EPWM_setActionQualifierAction(obj->pwmDACHandle[cnt],
                                      EPWM_AQ_OUTPUT_A,
                                      EPWM_AQ_OUTPUT_HIGH,
                                      EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

        // setup the Action-Qualifier Output B Register (AQCTLB)
        EPWM_setActionQualifierAction(obj->pwmDACHandle[cnt],
                                      EPWM_AQ_OUTPUT_B,
                                      EPWM_AQ_OUTPUT_LOW,
                                      EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);

        EPWM_setActionQualifierAction(obj->pwmDACHandle[cnt],
                                      EPWM_AQ_OUTPUT_B,
                                      EPWM_AQ_OUTPUT_HIGH,
                                      EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);


        // setup the Dead-Band Generator Control Register (DBCTL)
        EPWM_setDeadBandDelayMode(obj->pwmDACHandle[cnt], EPWM_DB_RED, false);

        EPWM_setDeadBandDelayMode(obj->pwmDACHandle[cnt], EPWM_DB_FED, false);

        // setup the PWM-Chopper Control Register (PCCTL)
        EPWM_disableChopper(obj->pwmDACHandle[cnt]);

        // setup the Trip Zone Select Register (TZSEL)
        EPWM_disableTripZoneSignals(obj->pwmDACHandle[cnt], HAL_TZSEL_SIGNALS_ALL);

        // since the PWM is configured as an up/down counter, the period
        // register is set to one-half of the desired PWM period
        EPWM_setTimeBasePeriod(obj->pwmDACHandle[cnt], period_cycles);
    }

    return;
}  // end of HAL_setupPWMDACs() function
#endif // EPWMDAC_MODE && !SYSCONFIG_EN

#if defined(QEP_ENABLE) && !defined(SYSCONFIG_EN)
void HAL_setupQEP(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj   *obj = (HAL_MTR_Obj *)handle;

    //
    // Configure the decoder for quadrature count mode
    //
    EQEP_setDecoderConfig(obj->qepHandle, (EQEP_CONFIG_1X_RESOLUTION |
                                       EQEP_CONFIG_QUADRATURE |
                                       EQEP_CONFIG_NO_SWAP));

    EQEP_setEmulationMode(obj->qepHandle, EQEP_EMULATIONMODE_RUNFREE);

    //
    // Configure the position counter to reset on an index event
    //
    EQEP_setPositionCounterConfig(obj->qepHandle, EQEP_POSITION_RESET_IDX,
                                  0xFFFFFFFF);

    //
    // Enable the unit timer, setting the frequency to 100 Hz
    //
    EQEP_enableUnitTimer(obj->qepHandle, (DEVICE_SYSCLK_FREQ / 100));

    //
    // Configure the position counter to be latched on a unit time out
    //
    EQEP_setLatchMode(obj->qepHandle, EQEP_LATCH_UNIT_TIME_OUT);

    //
    // Enable the eQEP module
    //
    EQEP_enableModule(obj->qepHandle);

    //
    // Configure and enable the edge-capture unit. The capture clock divider is
    // SYSCLKOUT/64. The unit-position event divider is QCLK/32.
    //
    EQEP_setCaptureConfig(obj->qepHandle, EQEP_CAPTURE_CLK_DIV_64,
                          EQEP_UNIT_POS_EVNT_DIV_32);

    EQEP_enableCapture(obj->qepHandle);

    return;
}
#endif  // QEP_ENABLE && !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupI2CA(HAL_Handle halHandle)
{
    HAL_Obj *obj = (HAL_Obj *)halHandle;

    // Must put I2C into reset before configuring it
    I2C_disableModule(obj->i2cHandle);

    // I2C configuration. Use a 400kHz I2CCLK with a 33% duty cycle.
    I2C_initMaster(obj->i2cHandle, DEVICE_SYSCLK_FREQ, 400000, I2C_DUTYCYCLE_33);
    I2C_setBitCount(obj->i2cHandle, I2C_BITCOUNT_8);
    I2C_setSlaveAddress(obj->i2cHandle, EEPROM_SLAVE_ADDRESS);
    I2C_setEmulationMode(obj->i2cHandle, I2C_EMULATION_FREE_RUN);

    // Enable stop condition and register-access-ready interrupts
    I2C_enableInterrupt(obj->i2cHandle, I2C_INT_STOP_CONDITION |
                                   I2C_INT_REG_ACCESS_RDY);

    // FIFO configuration
    I2C_enableFIFO(obj->i2cHandle);
    I2C_clearInterruptStatus(obj->i2cHandle, I2C_INT_RXFF | I2C_INT_TXFF);

    // Configuration complete. Enable the module.
    I2C_enableModule(obj->i2cHandle);

}  // end of HAL_setupI2CA() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupSCIA(HAL_Handle halHandle)
{
    HAL_Obj *obj = (HAL_Obj *)halHandle;

    // Initialize SCIA and its FIFO.
    SCI_performSoftwareReset(obj->sciHandle[0]);

    // Configure SCIA for echoback.
    SCI_setConfig(obj->sciHandle[0], DEVICE_LSPCLK_FREQ, 9600,
                        ( SCI_CONFIG_WLEN_8 |
                          SCI_CONFIG_STOP_ONE |
                          SCI_CONFIG_PAR_NONE ) );

    SCI_resetChannels(obj->sciHandle[0]);

    SCI_resetRxFIFO(obj->sciHandle[0]);

    SCI_resetTxFIFO(obj->sciHandle[0]);

    SCI_clearInterruptStatus(obj->sciHandle[0], SCI_INT_TXFF | SCI_INT_RXFF);

    SCI_enableFIFO(obj->sciHandle[0]);

    SCI_enableModule(obj->sciHandle[0]);

    SCI_performSoftwareReset(obj->sciHandle[0]);

}  // end of HAL_setupSCIA() function


void HAL_setupSCIB(HAL_Handle halHandle)
{
    HAL_Obj *obj = (HAL_Obj *)halHandle;

    // Initialize SCIA and its FIFO.
    SCI_performSoftwareReset(obj->sciHandle[1]);

    // Configure SCIA for echoback.
    SCI_setConfig(obj->sciHandle[1], DEVICE_LSPCLK_FREQ, 9600,
                        ( SCI_CONFIG_WLEN_8 |
                          SCI_CONFIG_STOP_ONE |
                          SCI_CONFIG_PAR_NONE ) );

    SCI_resetChannels(obj->sciHandle[1]);

    SCI_resetRxFIFO(obj->sciHandle[1]);

    SCI_resetTxFIFO(obj->sciHandle[1]);

    SCI_clearInterruptStatus(obj->sciHandle[1], SCI_INT_TXFF | SCI_INT_RXFF);

    SCI_enableFIFO(obj->sciHandle[1]);

    SCI_enableModule(obj->sciHandle[1]);

    SCI_performSoftwareReset(obj->sciHandle[1]);

}  // end of HAL_setupSCIB() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupSCIC(HAL_Handle halHandle)
{
    HAL_Obj *obj = (HAL_Obj *)halHandle;

    // Initialize SCIA and its FIFO.
    SCI_performSoftwareReset(obj->sciHandle[2]);

    // Configure SCIA for echoback.
    SCI_setConfig(obj->sciHandle[2], DEVICE_LSPCLK_FREQ, 9600,
                        ( SCI_CONFIG_WLEN_8 |
                          SCI_CONFIG_STOP_ONE |
                          SCI_CONFIG_PAR_NONE ) );

    SCI_resetChannels(obj->sciHandle[2]);

    SCI_resetRxFIFO(obj->sciHandle[2]);

    SCI_resetTxFIFO(obj->sciHandle[2]);

    SCI_clearInterruptStatus(obj->sciHandle[2], SCI_INT_TXFF | SCI_INT_RXFF);

    SCI_enableFIFO(obj->sciHandle[2]);

    SCI_enableModule(obj->sciHandle[2]);

    SCI_performSoftwareReset(obj->sciHandle[2]);

}  // end of HAL_setupSCIC() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupTimeBaseTimer(HAL_Handle handle, const float32_t timeBaseFreq_Hz)
{
    HAL_Obj  *obj = (HAL_Obj *)handle;

    uint32_t timerPeriod = (uint32_t)((USER_SYSTEM_FREQ_MHz * 1000.0f *1000.0f) /
                                      timeBaseFreq_Hz);

    // use timer 0 for CPU usage diagnostics
    CPUTimer_setPreScaler(obj->timerHandle[0], 0);

    CPUTimer_setEmulationMode(obj->timerHandle[0],
                              CPUTIMER_EMULATIONMODE_RUNFREE);

    CPUTimer_setPeriod(obj->timerHandle[0], timerPeriod);

    CPUTimer_startTimer(obj->timerHandle[0]);

    return;
}  // end of HAL_setupTimeBaseTimer() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupADCTriggerTimer(HAL_Handle handle, const float32_t adcTriggerFreq_Hz)
{
    HAL_Obj  *obj = (HAL_Obj *)handle;

    uint32_t timerPeriod = (uint32_t)((USER_SYSTEM_FREQ_MHz * 1000.0f *1000.0f) /
                                      adcTriggerFreq_Hz);

    // use timer 1 for CPU usage diagnostics
    CPUTimer_setPreScaler(obj->timerHandle[1], 0);

    CPUTimer_setEmulationMode(obj->timerHandle[1],
                              CPUTIMER_EMULATIONMODE_RUNFREE);

    CPUTimer_setPeriod(obj->timerHandle[1], timerPeriod);

    CPUTimer_enableInterrupt(obj->timerHandle[1]);

    CPUTimer_startTimer(obj->timerHandle[1]);

    return;
}  // end of HAL_setupADCTriggerTimer() function
#endif  // !SYSCONFIG_EN

#if !defined(SYSCONFIG_EN)
void HAL_setupCPUUsageTimer(HAL_Handle handle)
{
    HAL_Obj  *obj = (HAL_Obj *)handle;

    // use timer 2 for CPU usage diagnostics
    CPUTimer_setPreScaler(obj->timerHandle[2], 0);

    CPUTimer_setEmulationMode(obj->timerHandle[2],
                              CPUTIMER_EMULATIONMODE_RUNFREE);

    CPUTimer_setPeriod(obj->timerHandle[2], 0xFFFFFFFF);

    CPUTimer_startTimer(obj->timerHandle[2]);

    return;
}  // end of HAL_setupCPUUsageTimer() function
#endif  // !SYSCONFIG_EN

#if defined(EPWMDAC_MODE)
void HAL_setEPWMDACParameters(HAL_Handle handle, HAL_PWMDACData_t *pPWMDACData)
{
    HAL_Obj *obj = (HAL_Obj *)handle;

    pPWMDACData->periodMax =
            PWMDAC_getPeriod(obj->pwmDACHandle[0]);

    pPWMDACData->offset[0] = 0.0;
    pPWMDACData->offset[1] = 0.0;

    pPWMDACData->gain[0] = MATH_ONE_OVER_TWO_PI;
    pPWMDACData->gain[1] = MATH_ONE_OVER_TWO_PI;

    return;
}   //end of HAL_setPWMDACParameters() function
#endif  // EPWMDAC_MODE

// No DMA on f280013x, so the DMA based datalog is not supported in this project

// No DMA on f280013x, so the DMA based PFC is not supported in this project

void HAL_clearDataRAM(void *pMemory, uint16_t lengthMemory)
{
    uint16_t *pMemoryStart;
    uint16_t loopCount, loopLength;

    pMemoryStart = pMemory;
    loopLength = lengthMemory;

    for(loopCount = 0; loopCount < loopLength; loopCount++)
    {
        *(pMemoryStart + loopCount) = 0x0000;
    }

    return;
}   //end of HAL_clearDataRAM() function


void HAL_setMtrCMPSSDACValue(HAL_MTR_Handle handle,
                             const uint16_t dacValH, const uint16_t dacValL)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    if(handle == halMtrHandle[0])
    {
#if defined(MOTOR1_DCLINKSS)
        CMPSS_setDACValueLow(obj->cmpssHandle[0], dacValL);
#else   // !MOTOR1_DCLINKSS
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);

        CMPSS_setDACValueHigh(obj->cmpssHandle[1], dacValH);

        CMPSS_setDACValueLow(obj->cmpssHandle[2], dacValL);
#endif  // !MOTOR1_DCLINKSS
    }
    else
    {
#if defined(MOTOR2_DCLINKSS)
        CMPSS_setDACValueLow(obj->cmpssHandle[0], dacValL);
#else   // !MOTOR2_DCLINKSS
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);

        CMPSS_setDACValueLow(obj->cmpssHandle[1], dacValL);

        CMPSS_setDACValueLow(obj->cmpssHandle[2], dacValL);
#endif  // MOTOR2_DCLINKSS
    }
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    if(handle == halMtrHandle[0])
    {
#if defined(MOTOR1_DCLINKSS)
        CMPSS_setDACValueLow(obj->cmpssHandle[0], dacValL);
#else   // !MOTOR1_DCLINKSS
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);

        CMPSS_setDACValueHigh(obj->cmpssHandle[1], dacValH);
        CMPSS_setDACValueLow(obj->cmpssHandle[1], dacValL);

        CMPSS_setDACValueLow(obj->cmpssHandle[2], dacValL);
#endif  // !MOTOR1_DCLINKSS
    }
    else
    {
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);

        CMPSS_setDACValueHigh(obj->cmpssHandle[1], dacValH);
        CMPSS_setDACValueLow(obj->cmpssHandle[1], dacValL);

        CMPSS_setDACValueLow(obj->cmpssHandle[2], dacValL);
    }
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    if(handle == halMtrHandle[0])
    {
#if defined(MOTOR1_DCLINKSS)
        CMPSS_setDACValueLow(obj->cmpssHandle[0], dacValL);
#else   // !MOTOR1_DCLINKSS
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);

        CMPSS_setDACValueLow(obj->cmpssHandle[1], dacValL);

        CMPSS_setDACValueLow(obj->cmpssHandle[2], dacValL);
#endif  // MOTOR1_DCLINKSS
    }
    else
    {
        CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);

        CMPSS_setDACValueLow(obj->cmpssHandle[1], dacValL);

        CMPSS_setDACValueLow(obj->cmpssHandle[2], dacValL);
    }
    // BSXL8323RH_REVB
#else
#error Not select a right board to set the CMPSS DAC value for motors
#endif  // No Hardware Boards

    return;
}   // HAL_setMtrCMPSSDACValue()

void HAL_setPFCCMPSSDACValue(HAL_PFC_Handle handle,
                               const uint16_t dacValH, const uint16_t dacValL)
{
    HAL_PFC_Obj *obj = (HAL_PFC_Obj *)handle;

#if defined(DMCPFC_REV3P2) || defined(DMCPFC_REV3P1)
    CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);
    // DMCPFC_REV3P2 | DMCPFC_REV3P1
#elif defined(HVMTRPFC_REV1P1)
    CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);
    // HVMTRPFC_REV1P1
#elif defined(BSXL8323RH_REVB)
    CMPSS_setDACValueHigh(obj->cmpssHandle[0], dacValH);
    // BSXL8323RH_REVB
#else
#error Not select a right board to set the CMPSS DAC value for PFC
#endif  // No Hardware Boards

    return;
}   // HAL_setPFCCMPSSDACValue()

// end of file
