-----[Print the board config pathname(s)]------------------------------------

/home/ganesh/.ti/ccs2002/0/1/BrdDat/testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'libbh560v2u.out'.
Loaded FPGA Image: /home/ganesh/ti/ccs2002/ccs/ccs_base/common/uscif/./././././dtc_top.jbc
The library build date was 'Jan 21 2025'.
The library build time was '18:27:29'.
The library package version is '20.0.0.3344'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '6' (0x00000006).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: /home/ganesh/ti/ccs2002/ccs/ccs_base/common/uscif/./././././dtc_top.jbc

An error occurred while hard opening the controller.
Segmentation fault (core dumped)