%%{
let device_common   				= system.getScript("/driverlib/.meta/device/functions_c/device_common.js");
let clocktree_common   				= system.getScript("../../../clocktree/clocktree_common.js");
let Common   					= system.getScript("/driverlib/Common.js");
var XTAL_OR_X1 					= system.clockTree.XTAL_OR_X1;
var OSCCLKSRCSEL				= system.clockTree.OSCCLKSRCSEL;
var DIVSRCSEL					= system.clockTree.DIVSRCSEL;
var CANASRCSEL					= system.clockTree.CANABCLKSEL;
var CANBSRCSEL					= system.clockTree.CANBBCLKSEL;
var oscclkSrc 					= "SYSCTL_OSCSRC_OSC2";
var ecatclkSrc 					= "SYSCTL_SOURCE_AUXPLL";
var enetclkSrc 					= "SYSCTL_SOURCE_AUXPLL";
var canAclkSrc
var canBclkSrc
var oscclksource
var oscclk = 10

const clocktree_Asserts_Type0 			= device_common.clocktree_Asserts_Type0;
const clocktree_Asserts_Type1 			= device_common.clocktree_Asserts_Type1;
const clocktree_Asserts_Type2 			= device_common.clocktree_Asserts_Type2;
const clocktree_Asserts_Type3 			= device_common.clocktree_Asserts_Type3;
const clocktree_Asserts_Type4 			= device_common.clocktree_Asserts_Type4;
const clocktree_Asserts_Type5 			= device_common.clocktree_Asserts_Type5;
const clocktree_Asserts_Type6 			= device_common.clocktree_Asserts_Type6;
const xtal_x1_macro 				= clocktree_common.xtal_x1_macro;
const device  					= device_common.device;
%%}
% if(clocktree_Asserts_Type0.includes(device))
% 	{
%if(!system.clockTree.EMIF1CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF_DIV = system.clockTree.EMIF1CLKDIV.divideValue;
%}
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
%	case "INTOSC1":
%		oscclkSrc 		= "SYSCTL_OSCSRC_OSC1"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "INTOSC2":
%		oscclkSrc 	 	= "SYSCTL_OSCSRC_OSC2"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "X1_XTAL":
%		if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL"
%		}
%		else
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL_SE"
%		}
%			oscclksource 	= XTAL_OR_X1.inputSelect
%			oscclk 			= XTAL_OR_X1.External_Clock
%			break
%}
%switch(CANASRCSEL.inputSelect){
%	case "SYSCLK":
%		canAclkSrc 		= "CAN_CLOCK_SOURCE_SYS"
%		break
%	case "XTAL":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_XTAL"
%		break
%   	case "AUXCLKIN":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_AUX"
%		break
%}
%switch(CANBSRCSEL.inputSelect){
%	case "SYSCLK":
%		canBclkSrc 		= "CAN_CLOCK_SOURCE_SYS"
%		break
%	case "XTAL":
%		canBclkSrc 	 	= "CAN_CLOCK_SOURCE_XTAL"
%		break
%   	case "AUXCLKIN":
%		canBclkSrc 	 	= "CAN_CLOCK_SOURCE_AUX"
%		break
%}
    //
    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ and
    // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
    // expected if these are not correct.
    //
    //
    // From ClockTree Configurations
    //
    SysCtl_selectOscSourceAuxPLL(`oscclkSrc`);
    CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
    CAN_selectClockSource(CANB_BASE, `canBclkSrc`);
    SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_`DEVICE_CLK_EPWM_DIV`);
    SysCtl_setEMIF1ClockDivider(`DEVICE_CLK_EMIF_DIV`);
    ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
    ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% 	}
% if(clocktree_Asserts_Type1.includes(device))
% 	{
%if(!system.clockTree.EMIF1CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF_DIV =system.clockTree.EMIF1CLKDIV.divideValue;
%}
%if(!system.clockTree.ECATDIV){
%var DEVICE_CLK_ECAT_DIV = 4;
%}
%else{
%var DEVICE_CLK_ECAT_DIV = system.clockTree.ECATDIV.divideValue;
%}
%var DEVICE_CLK_ENET_DIV = system.clockTree.ENETDIV.divideValue;                             
%var DEVICE_CLK_MCAN_DIV = system.clockTree.MCANACLKDIV.divideValue;  
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
%	case "INTOSC1":
%		oscclkSrc 		= "SYSCTL_OSCSRC_OSC1"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "INTOSC2":
%		oscclkSrc 	 	= "SYSCTL_OSCSRC_OSC2"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "X1_XTAL":
%		if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL"
%		}
%		else
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL_SE"
%		}
%			oscclksource 	= XTAL_OR_X1.inputSelect
%			oscclk 			= XTAL_OR_X1.External_Clock
%			break
%}
%switch(DIVSRCSEL.inputSelect){
%	case "AUXPLLRAWCLK":
%		ecatclkSrc 		= "SYSCTL_SOURCE_AUXPLL"
%		enetclkSrc 		= "SYSCTL_SOURCE_AUXPLL"
%		break
%	case "PLLSYSCLK":
%		ecatclkSrc 	 	= "SYSCTL_SOURCE_SYSPLL"
%		enetclkSrc 	 	= "SYSCTL_SOURCE_SYSPLL"
%		break
%}
%switch(CANASRCSEL.inputSelect){
%	case "SYSCLK":
%		canAclkSrc 		= "CAN_CLOCK_SOURCE_SYS"
%		break
%	case "XTAL":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_XTAL"
%		break
%   	case "AUXCLKIN":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_AUX"
%		break
%}
%switch(CANBSRCSEL.inputSelect){
%	case "SYSCLK":
%		canBclkSrc 		= "CAN_CLOCK_SOURCE_SYS"
%		break
%	case "XTAL":
%		canBclkSrc 	 	= "CAN_CLOCK_SOURCE_XTAL"
%		break
%   	case "AUXCLKIN":
%		canBclkSrc 	 	= "CAN_CLOCK_SOURCE_AUX"
%		break
%}
    //
    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ, 
    // DEVICE_LSPCLK_FREQ and DEVICE_AUXCLK_FREQ are accurate. Some
    // examples will not perform as expected if these are not correct.
    //
    //
    // From ClockTree Configurations
    //
    SysCtl_selectOscSourceAuxPLL(`oscclkSrc`);
    CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
    CAN_selectClockSource(CANB_BASE, `canBclkSrc`);
    SysCtl_setMCANClk(SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCAN_DIV`);
    SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_`DEVICE_CLK_EPWM_DIV`);
    SysCtl_setEMIF1ClockDivider(`DEVICE_CLK_EMIF_DIV`);
    SysCtl_setECatClk(SYSCTL_ECATCLKOUT_DIV_`DEVICE_CLK_ECAT_DIV`, `ecatclkSrc`, 0x1U);
    SysCtl_setEnetClk(SYSCTL_ENETCLKOUT_DIV_`DEVICE_CLK_ENET_DIV`, `enetclkSrc`);
    ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
    ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
    ASSERT(SysCtl_getAuxClock(DEVICE_OSCSRC_FREQ) == DEVICE_AUXCLK_FREQ);
% 	}
% if(clocktree_Asserts_Type2.includes(device))
% 	{
%if(!system.clockTree.EMIF1CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF_DIV = system.clockTree.EMIF1CLKDIV.divideValue;
%}
%if(!system.clockTree.ECATDIV){
%var DEVICE_CLK_ECAT_DIV = 4;
%}
%else{
%var DEVICE_CLK_ECAT_DIV = system.clockTree.ECATDIV.divideValue;
%}
%var DEVICE_CLK_MCANA_DIV = system.clockTree.MCANACLKDIV.divideValue;
%var DEVICE_CLK_MCANB_DIV = system.clockTree.MCANBCLKDIV.divideValue;
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
%	case "INTOSC1":
%		oscclkSrc 		= "SYSCTL_OSCSRC_OSC1"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "INTOSC2":
%		oscclkSrc 	 	= "SYSCTL_OSCSRC_OSC2"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "X1_XTAL":
%		if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL"
%		}
%		else
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL_SE"
%		}
%			oscclksource 	= XTAL_OR_X1.inputSelect
%			oscclk 			= XTAL_OR_X1.External_Clock
%			break
%}
%switch(DIVSRCSEL.inputSelect){
%	case "AUXPLLRAWCLK":
%		ecatclkSrc 		= "SYSCTL_SOURCE_AUXPLL"
%		break
%	case "PLLSYSCLK":
%		ecatclkSrc 	 	= "SYSCTL_SOURCE_SYSPLL"
%		break
%}
%switch(DIVSRCSEL.inputSelect){
%	case "AUXPLLRAWCLK":
%		ecatclkSrc 		= "SYSCTL_SOURCE_AUXPLL"
%		break
%	case "PLLSYSCLK":
%		ecatclkSrc 	 	= "SYSCTL_SOURCE_SYSPLL"
%		break
%}
%switch(CANASRCSEL.inputSelect){
%	case "PERx.SYSCLK":
%		canAclkSrc 		= "CAN_CLOCK_SOURCE_SYS"
%		break
%	case "XTAL":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_XTAL"
%		break
%   	case "AUXCLKIN":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_AUX"
%		break
%}
    //
    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ and
    // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
    // expected if these are not correct.
    //
    //
    // From ClockTree Configurations
    //
    SysCtl_selectOscSourceAuxPLL(`oscclkSrc`);
    CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
    SysCtl_setMCANClk(SYSCTL_MCANA, SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCANA_DIV`);
    SysCtl_setMCANClk(SYSCTL_MCANB, SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCANB_DIV`);
    SysCtl_setEPWMClockDivider(SYSCTL_EPWMCLK_DIV_`DEVICE_CLK_EPWM_DIV`);
    SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_`DEVICE_CLK_EMIF_DIV`);
    SysCtl_setECatClk(SYSCTL_ECATCLKOUT_DIV_`DEVICE_CLK_ECAT_DIV`, `ecatclkSrc`, 0x1U);
    ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
    ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
    ASSERT(SysCtl_getAuxClock(DEVICE_OSCSRC_FREQ) == DEVICE_AUXCLK_FREQ);
% }
% if(clocktree_Asserts_Type3.includes(device))
% 	{
%var DEVICE_CLK_MCANA_DIV = system.clockTree.MCANACLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
%	case "INTOSC1":
%		oscclkSrc 		= "SYSCTL_OSCSRC_OSC1"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "INTOSC2":
%		oscclkSrc 	 	= "SYSCTL_OSCSRC_OSC2"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "X1_XTAL":
%		if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL"
%		}
%		else
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL_SE"
%		}
%			oscclksource 	= XTAL_OR_X1.inputSelect
%			oscclk 			= XTAL_OR_X1.External_Clock
%			break
%}
%switch(CANASRCSEL.inputSelect){
%	case "SYSCLK":
%		canAclkSrc 		= "CAN_CLOCK_SOURCE_SYS"
%		break
%	case "XTAL":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_XTAL"
%		break
%   	case "AUXCLKIN":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_AUX"
%		break
%}
    //
    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ and
    // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
    // expected if these are not correct.
    //
    CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
    SysCtl_setMCANClk(SYSCTL_MCANCLK_DIV_`DEVICE_CLK_MCANA_DIV`);
    ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
    ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% }
% if(clocktree_Asserts_Type4.includes(device))
% {
%switch(OSCCLKSRCSEL.inputSelect){
%	case "INTOSC1":
%		oscclkSrc 		= "SYSCTL_OSCSRC_OSC1"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "INTOSC2":
%		oscclkSrc 	 	= "SYSCTL_OSCSRC_OSC2"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "X1_XTAL":
%		if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL"
%		}
%		else
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL_SE"
%		}
%			oscclksource 	= XTAL_OR_X1.inputSelect
%			oscclk 			= XTAL_OR_X1.External_Clock
%			break
%}
%switch(CANASRCSEL.inputSelect){
%	case "SYSCLK":
%		canAclkSrc 		= "CAN_CLOCK_SOURCE_SYS"
%		break
%	case "XTAL":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_XTAL"
%		break
%   	case "AUXCLKIN":
%		canAclkSrc 	 	= "CAN_CLOCK_SOURCE_AUX"
%		break
%}
    //
    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ and
    // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
    // expected if these are not correct.
    //
    CAN_selectClockSource(CANA_BASE, `canAclkSrc`);
    ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
    ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% 	}
% if(clocktree_Asserts_Type5.includes(device))
%{
    //
    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ and
    // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as
    // expected if these are not correct.
    //
    ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
    ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ);
% 	}
% if(clocktree_Asserts_Type6.includes(device))
% 	{
%if(!system.clockTree.EMIF1CLKDIV){
%console.log("In here")
%var DEVICE_CLK_EMIF_DIV = "SYSCTL_EMIF1CLK_DIV_1";
%}
%else{
%console.log("should not be In here")
%var DEVICE_CLK_EMIF_DIV = system.clockTree.EMIF1CLKDIV.divideValue;
%}
%if(!system.clockTree.ECATDIV){
%var DEVICE_CLK_ECAT_DIV = 4;
%}
%else{
%var DEVICE_CLK_ECAT_DIV = system.clockTree.ECATDIV.divideValue;
%}
%var DEVICE_CLK_MCANA_DIV = system.clockTree.MCANACLKDIV.divideValue;
%var DEVICE_CLK_MCANB_DIV = system.clockTree.MCANBCLKDIV.divideValue;
%var DEVICE_CLK_MCANC_DIV = system.clockTree.MCANCCLKDIV.divideValue;
%var DEVICE_CLK_MCAND_DIV = system.clockTree.MCANDCLKDIV.divideValue;
%var DEVICE_CLK_MCANE_DIV = system.clockTree.MCANECLKDIV.divideValue;
%var DEVICE_CLK_MCANF_DIV = system.clockTree.MCANFCLKDIV.divideValue;
%var DEVICE_CLK_EPWM_DIV = system.clockTree.EPWMCLKDIV.divideValue;
%switch(OSCCLKSRCSEL.inputSelect){
%	case "INTOSC1":
%		oscclkSrc 		= "SYSCTL_OSCSRC_OSC1"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "INTOSC2":
%		oscclkSrc 	 	= "SYSCTL_OSCSRC_OSC2"
%		oscclksource 	= OSCCLKSRCSEL.inputSelect
%		oscclk = 10
%		break
%	case "X1_XTAL":
%		if((XTAL_OR_X1.inputSelect == "XTAL") || xtal_x1_macro.includes(device))
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL"
%		}
%		else
%		{
%			oscclkSrc 	 	= "SYSCTL_OSCSRC_XTAL_SE"
%		}
%			oscclksource 	= XTAL_OR_X1.inputSelect
%			oscclk 			= XTAL_OR_X1.External_Clock
%			break
%}
    //
    // These asserts will check that the #defines for the clock rates in
    // device.h match the actual rates that have been configured. If they do
    // not match, check that the calculations of DEVICE_SYSCLK_FREQ
    // are accurate. Some examples will not perform as expected if these are not correct.
    //
    //
    // From ClockTree Configurations
    //
    // ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ);
% }