/* * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include "board.h" void Board_init() { EALLOW; PinMux_init(); INPUTXBAR_init(); SYNC_init(); ASYSCTL_init(); ADC_init(); CAN_init(); CLB_init(); CLBXBAR_init(); CMPSS_init(); EPWM_init(); EPWMXBAR_init(); GPIO_init(); OUTPUTXBAR_init(); SCI_init(); INTERRUPT_init(); EDIS; } void PinMux_init() { // // ANALOG -> myANALOGPinMux0 Pinmux // // Analog PinMux for A0/C15 GPIO_setPinConfig(GPIO_231_GPIO231); // AIO -> Analog mode selected GPIO_setAnalogMode(231, GPIO_ANALOG_ENABLED); // Analog PinMux for A1 GPIO_setPinConfig(GPIO_232_GPIO232); // AIO -> Analog mode selected GPIO_setAnalogMode(232, GPIO_ANALOG_ENABLED); // Analog PinMux for A10/C10 GPIO_setPinConfig(GPIO_230_GPIO230); // AIO -> Analog mode selected GPIO_setAnalogMode(230, GPIO_ANALOG_ENABLED); // Analog PinMux for A12/C1 GPIO_setPinConfig(GPIO_238_GPIO238); // AIO -> Analog mode selected GPIO_setAnalogMode(238, GPIO_ANALOG_ENABLED); // Analog PinMux for A14/C4 GPIO_setPinConfig(GPIO_239_GPIO239); // AIO -> Analog mode selected GPIO_setAnalogMode(239, GPIO_ANALOG_ENABLED); // Analog PinMux for A15/C7 GPIO_setPinConfig(GPIO_233_GPIO233); // AIO -> Analog mode selected GPIO_setAnalogMode(233, GPIO_ANALOG_ENABLED); // Analog PinMux for A2/C9 GPIO_setPinConfig(GPIO_224_GPIO224); // AIO -> Analog mode selected GPIO_setAnalogMode(224, GPIO_ANALOG_ENABLED); // Analog PinMux for A3/C5/VDAC GPIO_setPinConfig(GPIO_242_GPIO242); // AIO -> Analog mode selected GPIO_setAnalogMode(242, GPIO_ANALOG_ENABLED); // Analog PinMux for A6 GPIO_setPinConfig(GPIO_228_GPIO228); // AIO -> Analog mode selected GPIO_setAnalogMode(228, GPIO_ANALOG_ENABLED); // Analog PinMux for C6 GPIO_setPinConfig(GPIO_226_GPIO226); // AIO -> Analog mode selected GPIO_setAnalogMode(226, GPIO_ANALOG_ENABLED); // // CANA -> myCAN0 Pinmux // GPIO_setPinConfig(GPIO_18_CANA_RX); GPIO_setPinConfig(GPIO_17_CANA_TX); // // EPWM1 -> EPWM1_RefA Pinmux // GPIO_setPinConfig(GPIO_30_EPWM1_A); // // EPWM2 -> EPWM2_DT2 Pinmux // GPIO_setPinConfig(GPIO_41_EPWM2_A); // // EPWM3 -> EPWM3_DinA Pinmux // GPIO_setPinConfig(GPIO_4_EPWM3_A); GPIO_setPinConfig(GPIO_5_EPWM3_B); // // EPWM4 -> EPWM4_DinB Pinmux // GPIO_setPinConfig(GPIO_6_EPWM4_A); GPIO_setPinConfig(GPIO_7_EPWM4_B); // // EPWM5 -> EPWM5_RefB Pinmux // GPIO_setPinConfig(GPIO_16_EPWM5_A); // // EPWM6 -> EPWM6_DT1 Pinmux // GPIO_setPinConfig(GPIO_10_EPWM6_A); // // EPWM7 -> EPWM7_J_Out Pinmux // GPIO_setPinConfig(GPIO_12_EPWM7_A); GPIO_setPinConfig(GPIO_13_EPWM7_B); // GPIO31 -> DEVICE_GPIO_PIN_FAULT Pinmux GPIO_setPinConfig(GPIO_31_GPIO31); // GPIO34 -> DEVICE_GPIO_PIN_SLEEP Pinmux GPIO_setPinConfig(GPIO_34_GPIO34); // GPIO40 -> DEVICE_GPIO_PIN_DRVR_CDR_A Pinmux GPIO_setPinConfig(GPIO_40_GPIO40); // GPIO46 -> DEVICE_GPIO_PIN_DRVR_CDR_B Pinmux GPIO_setPinConfig(GPIO_46_GPIO46); // GPIO8 -> DEVICE_GPIO_PIN_DECAY_1 Pinmux GPIO_setPinConfig(GPIO_8_GPIO8); // GPIO43 -> DEVICE_GPIO_PIN_DECAY_2 Pinmux GPIO_setPinConfig(GPIO_43_GPIO43); // GPIO25 -> DEVICE_GPIO_PIN_ENA Pinmux GPIO_setPinConfig(GPIO_25_GPIO25); // GPIO45 -> DEVICE_GPIO_PIN_COMM_LED Pinmux GPIO_setPinConfig(GPIO_45_GPIO45); // GPIO27 -> DEVICE_GPIO_PIN_LIFE Pinmux GPIO_setPinConfig(GPIO_27_GPIO27); // GPIO42 -> DEVICE_GPIO_PIN_485_ENA Pinmux GPIO_setPinConfig(GPIO_42_GPIO42); // GPIO44 -> GPIO44_Interrupt_Line Pinmux GPIO_setPinConfig(GPIO_44_GPIO44); // GPIO33 -> DEVICE_GPIO_PIN_ENB Pinmux GPIO_setPinConfig(GPIO_33_GPIO33); // // OUTPUTXBAR1 -> myOUTPUTXBAR0 Pinmux // GPIO_setPinConfig(GPIO_2_OUTPUTXBAR1); // // SCIA -> mySCI0 Pinmux // GPIO_setPinConfig(GPIO_28_SCIA_RX); GPIO_setPinConfig(GPIO_29_SCIA_TX); } void ADC_init(){ //myADC0 initialization // ADC Initialization: Write ADC configurations and power up the ADC // Configures the ADC module's offset trim ADC_setOffsetTrimAll(ADC_REFERENCE_INTERNAL,ADC_REFERENCE_2_5V); // Configures the analog-to-digital converter module prescaler. ADC_setPrescaler(myADC0_BASE, ADC_CLK_DIV_2_0); // Sets the timing of the end-of-conversion pulse ADC_setInterruptPulseMode(myADC0_BASE, ADC_PULSE_END_OF_CONV); // Powers up the analog-to-digital converter core. ADC_enableConverter(myADC0_BASE); // Delay for 1ms to allow ADC time to power up DEVICE_DELAY_US(5000); // SOC Configuration: Setup ADC EPWM channel and trigger settings // Disables SOC burst mode. ADC_disableBurstMode(myADC0_BASE); // Sets the priority mode of the SOCs. ADC_setSOCPriority(myADC0_BASE, ADC_PRI_ALL_ROUND_ROBIN); // Start of Conversion 0 Configuration // Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger. // SOC number : 0 // Trigger : ADC_TRIGGER_EPWM1_SOCA // Channel : ADC_CH_ADCIN10 // Sample Window : 50 SYSCLK cycles // Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE ADC_setupSOC(myADC0_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA, ADC_CH_ADCIN10, 50U); ADC_setInterruptSOCTrigger(myADC0_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE); // Start of Conversion 1 Configuration // Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger. // SOC number : 1 // Trigger : ADC_TRIGGER_EPWM1_SOCA // Channel : ADC_CH_ADCIN15 // Sample Window : 50 SYSCLK cycles // Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE ADC_setupSOC(myADC0_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM1_SOCA, ADC_CH_ADCIN15, 50U); ADC_setInterruptSOCTrigger(myADC0_BASE, ADC_SOC_NUMBER1, ADC_INT_SOC_TRIGGER_NONE); // ADC Interrupt 1 Configuration // SOC/EOC number : 0 // Interrupt Source: enabled // Continuous Mode : disabled ADC_setInterruptSource(myADC0_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER0); ADC_enableInterrupt(myADC0_BASE, ADC_INT_NUMBER1); ADC_clearInterruptStatus(myADC0_BASE, ADC_INT_NUMBER1); ADC_disableContinuousMode(myADC0_BASE, ADC_INT_NUMBER1); } void ASYSCTL_init(){ // asysctl initialization // Disables the temperature sensor output to the ADC. ASysCtl_disableTemperatureSensor(); // Set the analog voltage reference selection to internal. ASysCtl_setAnalogReferenceInternal( ASYSCTL_VREFHIA | ASYSCTL_VREFHIC ); // Set the internal analog voltage reference selection to 2.5V. ASysCtl_setAnalogReference2P5( ASYSCTL_VREFHIA | ASYSCTL_VREFHIC ); } void CAN_init(){ //myCAN0 initialization CAN_initModule(myCAN0_BASE); // Refer to the Driver Library User Guide for information on how to set // tighter timing control. Additionally, consult the device data sheet // for more information about the CAN module clocking. // CAN_setBitTiming(myCAN0_BASE, 7, 0, 15, 7, 3); // Enable CAN Interrupts CAN_enableInterrupt(myCAN0_BASE, CAN_INT_IE0|CAN_INT_STATUS); CAN_enableGlobalInterrupt(myCAN0_BASE, CAN_GLOBAL_INT_CANINT0); // Initialize the transmit message object used for sending CAN messages. // Message Object Parameters: // Message Object ID Number: 1 // Message Identifier: 32 // Message Frame: CAN_MSG_FRAME_STD // Message Type: CAN_MSG_OBJ_TYPE_RX // Message ID Mask: 0 // Message Object Flags: CAN_MSG_OBJ_RX_INT_ENABLE // Message Data Length: 0 Bytes // CAN_setupMessageObject(myCAN0_BASE, 1, myCAN0_MessageObj1_ID, CAN_MSG_FRAME_STD,CAN_MSG_OBJ_TYPE_RX, 0, CAN_MSG_OBJ_RX_INT_ENABLE,0); // Initialize the transmit message object used for sending CAN messages. // Message Object Parameters: // Message Object ID Number: 2 // Message Identifier: 32 // Message Frame: CAN_MSG_FRAME_STD // Message Type: CAN_MSG_OBJ_TYPE_TX // Message ID Mask: 0 // Message Object Flags: CAN_MSG_OBJ_TX_INT_ENABLE // Message Data Length: 8 Bytes // CAN_setupMessageObject(myCAN0_BASE, 2, myCAN0_MessageObj2_ID, CAN_MSG_FRAME_STD,CAN_MSG_OBJ_TYPE_TX, 0, CAN_MSG_OBJ_TX_INT_ENABLE,8); CAN_setInterruptMux(myCAN0_BASE, 0); // // Start CAN module operations // CAN_startModule(myCAN0_BASE); } void CLB_init(){ //myCLB0 initialization CLB_setOutputMask(myCLB0_BASE, (0UL << 0UL), true); CLB_enableOutputMaskUpdates(myCLB0_BASE); CLB_disableSPIBufferAccess(myCLB0_BASE); CLB_configSPIBufferLoadSignal(myCLB0_BASE, 0); CLB_configSPIBufferShift(myCLB0_BASE, 0); //myCLB0 CLB_IN0 initialization CLB_configLocalInputMux(myCLB0_BASE, CLB_IN0, CLB_LOCAL_IN_MUX_GLOBAL_IN); CLB_configGlobalInputMux(myCLB0_BASE, CLB_IN0, CLB_GLOBAL_IN_MUX_CLB_AUXSIG0); CLB_configGPInputMux(myCLB0_BASE, CLB_IN0, CLB_GP_IN_MUX_EXTERNAL); CLB_selectInputFilter(myCLB0_BASE, CLB_IN0, CLB_FILTER_NONE); CLB_disableInputPipelineMode(myCLB0_BASE, CLB_IN0); //myCLB0 CLB_IN1 initialization CLB_configLocalInputMux(myCLB0_BASE, CLB_IN1, CLB_LOCAL_IN_MUX_GLOBAL_IN); CLB_configGlobalInputMux(myCLB0_BASE, CLB_IN1, CLB_GLOBAL_IN_MUX_EPWM1A); CLB_configGPInputMux(myCLB0_BASE, CLB_IN1, CLB_GP_IN_MUX_GP_REG); CLB_selectInputFilter(myCLB0_BASE, CLB_IN1, CLB_FILTER_NONE); CLB_disableInputPipelineMode(myCLB0_BASE, CLB_IN1); CLB_setGPREG(myCLB0_BASE,0); CLB_disableCLB(myCLB0_BASE); } void CLBXBAR_init(){ //myCLBXBAR0 initialization XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX00_CMPSS1_CTRIPH); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX01_CMPSS1_CTRIPL); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX02_CMPSS2_CTRIPH); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX03_CMPSS2_CTRIPL); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX04_CMPSS3_CTRIPH); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX05_CMPSS3_CTRIPL); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX06_CMPSS4_CTRIPH); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX07_CMPSS4_CTRIPL); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX09_INPUTXBAR5); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX11_INPUTXBAR6); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX13_ADCSOCA); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX14_EXTSYNCOUT); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX15_ADCSOCB); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX17_INPUTXBAR7); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX19_INPUTXBAR8); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX21_INPUTXBAR9); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX23_INPUTXBAR10); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX25_INPUTXBAR11); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX27_INPUTXBAR12); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX29_INPUTXBAR13); XBAR_setCLBMuxConfig(XBAR_AUXSIG0, XBAR_CLB_MUX31_INPUTXBAR14); XBAR_enableCLBMux(XBAR_AUXSIG0, XBAR_MUX00 | XBAR_MUX01 | XBAR_MUX02 | XBAR_MUX03 | XBAR_MUX04 | XBAR_MUX05 | XBAR_MUX06 | XBAR_MUX07 | XBAR_MUX09 | XBAR_MUX11 | XBAR_MUX13 | XBAR_MUX14 | XBAR_MUX15 | XBAR_MUX17 | XBAR_MUX19 | XBAR_MUX21 | XBAR_MUX23 | XBAR_MUX25 | XBAR_MUX27 | XBAR_MUX29 | XBAR_MUX31); } void CMPSS_init(){ // Select the value for CMPHNMXSEL. ASysCtl_selectCMPHNMux(ASYSCTL_CMPHNMUX_SELECT_4 | ASYSCTL_CMPHNMUX_SELECT_2); // Select the value for CMPLNMXSEL. ASysCtl_selectCMPLNMux(ASYSCTL_CMPLNMUX_SELECT_4 | ASYSCTL_CMPLNMUX_SELECT_2); // Select the value for CMPHPM[object Object]SEL. ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_4,2U); // Select the value for CMPLPM[object Object]SEL. ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_4,2U); // Select the value for CMPHPM[object Object]SEL. ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_2,3U); // Select the value for CMPLPM[object Object]SEL. ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_2,3U); //Phase_A_CMPSS initialization // Sets the configuration for the high comparator. CMPSS_configHighComparator(Phase_A_CMPSS_BASE,(CMPSS_INSRC_DAC)); // Sets the configuration for the high comparator. CMPSS_configLowComparator(Phase_A_CMPSS_BASE,(CMPSS_INSRC_DAC)); // Sets the configuration for the internal comparator DACs. CMPSS_configDAC(Phase_A_CMPSS_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW)); // Sets the value of the internal DAC of the high comparator. CMPSS_setDACValueHigh(Phase_A_CMPSS_BASE,0U); // Sets the value of the internal DAC of the low comparator. CMPSS_setDACValueLow(Phase_A_CMPSS_BASE,0U); // Configures the digital filter of the high comparator. CMPSS_configFilterHigh(Phase_A_CMPSS_BASE, 0U, 32U, 17U); // Configures the digital filter of the low comparator. CMPSS_configFilterLow(Phase_A_CMPSS_BASE, 0U, 1U, 1U); // Initializes the digital filter of the high comparator. CMPSS_initFilterHigh(Phase_A_CMPSS_BASE); // Sets the output signal configuration for the high comparator. CMPSS_configOutputsHigh(Phase_A_CMPSS_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_FILTER)); // Sets the output signal configuration for the low comparator. CMPSS_configOutputsLow(Phase_A_CMPSS_BASE,(CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_ASYNC_COMP)); // Sets the comparator hysteresis settings. CMPSS_setHysteresis(Phase_A_CMPSS_BASE,0U); // Configures the comparator subsystem's ramp generator. CMPSS_configRamp(Phase_A_CMPSS_BASE,0U,0U,0U,1U,true); // Disables reset of HIGH comparator digital filter output latch on PWMSYNC CMPSS_disableLatchResetOnPWMSYNCHigh(Phase_A_CMPSS_BASE); // Disables reset of LOW comparator digital filter output latch on PWMSYNC CMPSS_disableLatchResetOnPWMSYNCLow(Phase_A_CMPSS_BASE); // Sets the ePWM module blanking signal that holds trip in reset. CMPSS_configBlanking(Phase_A_CMPSS_BASE,1U); // Disables an ePWM blanking signal from holding trip in reset. CMPSS_disableBlanking(Phase_A_CMPSS_BASE); // Configures whether or not the digital filter latches are reset by PWMSYNC CMPSS_configLatchOnPWMSYNC(Phase_A_CMPSS_BASE,true,false); // Enables the CMPSS module. CMPSS_enableModule(Phase_A_CMPSS_BASE); //Phase_B_CMPSS initialization // Sets the configuration for the high comparator. CMPSS_configHighComparator(Phase_B_CMPSS_BASE,(CMPSS_INSRC_DAC)); // Sets the configuration for the high comparator. CMPSS_configLowComparator(Phase_B_CMPSS_BASE,(CMPSS_INSRC_DAC)); // Sets the configuration for the internal comparator DACs. CMPSS_configDAC(Phase_B_CMPSS_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW)); // Sets the value of the internal DAC of the high comparator. CMPSS_setDACValueHigh(Phase_B_CMPSS_BASE,0U); // Sets the value of the internal DAC of the low comparator. CMPSS_setDACValueLow(Phase_B_CMPSS_BASE,0U); // Configures the digital filter of the high comparator. CMPSS_configFilterHigh(Phase_B_CMPSS_BASE, 0U, 32U, 17U); // Configures the digital filter of the low comparator. CMPSS_configFilterLow(Phase_B_CMPSS_BASE, 0U, 1U, 1U); // Initializes the digital filter of the high comparator. CMPSS_initFilterHigh(Phase_B_CMPSS_BASE); // Sets the output signal configuration for the high comparator. CMPSS_configOutputsHigh(Phase_B_CMPSS_BASE,(CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_FILTER)); // Sets the output signal configuration for the low comparator. CMPSS_configOutputsLow(Phase_B_CMPSS_BASE,(CMPSS_TRIPOUT_FILTER | CMPSS_TRIP_ASYNC_COMP)); // Sets the comparator hysteresis settings. CMPSS_setHysteresis(Phase_B_CMPSS_BASE,2U); // Configures the comparator subsystem's ramp generator. CMPSS_configRamp(Phase_B_CMPSS_BASE,0U,0U,0U,1U,true); // Disables reset of HIGH comparator digital filter output latch on PWMSYNC CMPSS_disableLatchResetOnPWMSYNCHigh(Phase_B_CMPSS_BASE); // Disables reset of LOW comparator digital filter output latch on PWMSYNC CMPSS_disableLatchResetOnPWMSYNCLow(Phase_B_CMPSS_BASE); // Sets the ePWM module blanking signal that holds trip in reset. CMPSS_configBlanking(Phase_B_CMPSS_BASE,1U); // Disables an ePWM blanking signal from holding trip in reset. CMPSS_disableBlanking(Phase_B_CMPSS_BASE); // Configures whether or not the digital filter latches are reset by PWMSYNC CMPSS_configLatchOnPWMSYNC(Phase_B_CMPSS_BASE,true,false); // Enables the CMPSS module. CMPSS_enableModule(Phase_B_CMPSS_BASE); // Delay for CMPSS DAC to power up. DEVICE_DELAY_US(500); // Causes a software reset of the high comparator digital filter output latch. CMPSS_clearFilterLatchHigh(Phase_A_CMPSS_BASE); // Causes a software reset of the high comparator digital filter output latch. CMPSS_clearFilterLatchHigh(Phase_B_CMPSS_BASE); } void EPWM_init(){ EPWM_setClockPrescaler(EPWM1_RefA_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); EPWM_setTimeBasePeriod(EPWM1_RefA_BASE, 5000); EPWM_setTimeBaseCounter(EPWM1_RefA_BASE, 0); EPWM_setTimeBaseCounterMode(EPWM1_RefA_BASE, EPWM_COUNTER_MODE_UP); EPWM_disablePhaseShiftLoad(EPWM1_RefA_BASE); EPWM_setPhaseShift(EPWM1_RefA_BASE, 0); EPWM_setCounterCompareValue(EPWM1_RefA_BASE, EPWM_COUNTER_COMPARE_A, 1250); EPWM_setCounterCompareShadowLoadMode(EPWM1_RefA_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(EPWM1_RefA_BASE, EPWM_COUNTER_COMPARE_B, 1250); EPWM_setCounterCompareShadowLoadMode(EPWM1_RefA_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM1_RefA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_enableADCTrigger(EPWM1_RefA_BASE, EPWM_SOC_A); EPWM_setADCTriggerSource(EPWM1_RefA_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO); EPWM_setADCTriggerEventPrescale(EPWM1_RefA_BASE, EPWM_SOC_A, 1); EPWM_setClockPrescaler(EPWM2_DT2_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2); EPWM_setTimeBasePeriod(EPWM2_DT2_BASE, 0); EPWM_setTimeBaseCounter(EPWM2_DT2_BASE, 0); EPWM_setTimeBaseCounterMode(EPWM2_DT2_BASE, EPWM_COUNTER_MODE_STOP_FREEZE); EPWM_disablePhaseShiftLoad(EPWM2_DT2_BASE); EPWM_setPhaseShift(EPWM2_DT2_BASE, 0); EPWM_setCounterCompareValue(EPWM2_DT2_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareShadowLoadMode(EPWM2_DT2_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(EPWM2_DT2_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setCounterCompareShadowLoadMode(EPWM2_DT2_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM2_DT2_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setClockPrescaler(EPWM3_DinA_BASE, EPWM_CLOCK_DIVIDER_2, EPWM_HSCLOCK_DIVIDER_1); EPWM_setTimeBasePeriod(EPWM3_DinA_BASE, 2500); EPWM_setTimeBaseCounter(EPWM3_DinA_BASE, 0); EPWM_setTimeBaseCounterMode(EPWM3_DinA_BASE, EPWM_COUNTER_MODE_UP); EPWM_disablePhaseShiftLoad(EPWM3_DinA_BASE); EPWM_setPhaseShift(EPWM3_DinA_BASE, 0); EPWM_setCounterCompareValue(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_disableCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_C); EPWM_disableCounterCompareShadowLoadMode(EPWM3_DinA_BASE, EPWM_COUNTER_COMPARE_D); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierT1TriggerSource(EPWM3_DinA_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1); EPWM_setActionQualifierT2TriggerSource(EPWM3_DinA_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM3_DinA_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_enableTripZoneSignals(EPWM3_DinA_BASE, EPWM_TZ_SIGNAL_DCAEVT2); EPWM_selectDigitalCompareTripInput(EPWM3_DinA_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(EPWM3_DinA_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCAL); EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_DinA_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setDigitalCompareEventSyncMode(EPWM3_DinA_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); EPWM_selectDigitalCompareTripInput(EPWM3_DinA_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(EPWM3_DinA_BASE, EPWM_DC_TRIP_TRIPIN4, EPWM_DC_TYPE_DCBL); EPWM_enableADCTrigger(EPWM3_DinA_BASE, EPWM_SOC_A); EPWM_setADCTriggerSource(EPWM3_DinA_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO); EPWM_setClockPrescaler(EPWM4_DinB_BASE, EPWM_CLOCK_DIVIDER_2, EPWM_HSCLOCK_DIVIDER_1); EPWM_setTimeBasePeriod(EPWM4_DinB_BASE, 2500); EPWM_setTimeBaseCounter(EPWM4_DinB_BASE, 0); EPWM_setTimeBaseCounterMode(EPWM4_DinB_BASE, EPWM_COUNTER_MODE_UP); EPWM_disablePhaseShiftLoad(EPWM4_DinB_BASE); EPWM_setPhaseShift(EPWM4_DinB_BASE, 0); EPWM_setCounterCompareValue(EPWM4_DinB_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareShadowLoadMode(EPWM4_DinB_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(EPWM4_DinB_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setCounterCompareShadowLoadMode(EPWM4_DinB_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_disableCounterCompareShadowLoadMode(EPWM4_DinB_BASE, EPWM_COUNTER_COMPARE_C); EPWM_disableCounterCompareShadowLoadMode(EPWM4_DinB_BASE, EPWM_COUNTER_COMPARE_D); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierT1TriggerSource(EPWM4_DinB_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1); EPWM_setActionQualifierT2TriggerSource(EPWM4_DinB_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM4_DinB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setTripZoneAction(EPWM4_DinB_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(EPWM4_DinB_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_enableTripZoneSignals(EPWM4_DinB_BASE, EPWM_TZ_SIGNAL_DCAEVT2); EPWM_selectDigitalCompareTripInput(EPWM4_DinB_BASE, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(EPWM4_DinB_BASE, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCAL); EPWM_selectDigitalCompareTripInput(EPWM4_DinB_BASE, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(EPWM4_DinB_BASE, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCBL); EPWM_setDigitalCompareFilterInput(EPWM4_DinB_BASE, EPWM_DC_WINDOW_SOURCE_DCAEVT2); EPWM_enableADCTrigger(EPWM4_DinB_BASE, EPWM_SOC_A); EPWM_setADCTriggerSource(EPWM4_DinB_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO); EPWM_setClockPrescaler(EPWM5_RefB_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2); EPWM_setTimeBasePeriod(EPWM5_RefB_BASE, 0); EPWM_setTimeBaseCounter(EPWM5_RefB_BASE, 0); EPWM_setTimeBaseCounterMode(EPWM5_RefB_BASE, EPWM_COUNTER_MODE_STOP_FREEZE); EPWM_disablePhaseShiftLoad(EPWM5_RefB_BASE); EPWM_setPhaseShift(EPWM5_RefB_BASE, 0); EPWM_setCounterCompareValue(EPWM5_RefB_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareShadowLoadMode(EPWM5_RefB_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(EPWM5_RefB_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setCounterCompareShadowLoadMode(EPWM5_RefB_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM5_RefB_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setClockPrescaler(EPWM6_DT1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2); EPWM_setTimeBasePeriod(EPWM6_DT1_BASE, 0); EPWM_setTimeBaseCounter(EPWM6_DT1_BASE, 0); EPWM_setTimeBaseCounterMode(EPWM6_DT1_BASE, EPWM_COUNTER_MODE_STOP_FREEZE); EPWM_disablePhaseShiftLoad(EPWM6_DT1_BASE); EPWM_setPhaseShift(EPWM6_DT1_BASE, 0); EPWM_setCounterCompareValue(EPWM6_DT1_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareShadowLoadMode(EPWM6_DT1_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(EPWM6_DT1_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setCounterCompareShadowLoadMode(EPWM6_DT1_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM6_DT1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setClockPrescaler(EPWM7_J_Out_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2); EPWM_setTimeBasePeriod(EPWM7_J_Out_BASE, 0); EPWM_setTimeBaseCounter(EPWM7_J_Out_BASE, 0); EPWM_setTimeBaseCounterMode(EPWM7_J_Out_BASE, EPWM_COUNTER_MODE_STOP_FREEZE); EPWM_disablePhaseShiftLoad(EPWM7_J_Out_BASE); EPWM_setPhaseShift(EPWM7_J_Out_BASE, 0); EPWM_setCounterCompareValue(EPWM7_J_Out_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareShadowLoadMode(EPWM7_J_Out_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(EPWM7_J_Out_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setCounterCompareShadowLoadMode(EPWM7_J_Out_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(EPWM7_J_Out_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); } void EPWMXBAR_init(){ //myEPWMXBAR0 initialization XBAR_setEPWMMuxConfig(XBAR_TRIP7, XBAR_EPWM_MUX01_CLB1_OUT4); XBAR_enableEPWMMux(XBAR_TRIP7, XBAR_MUX01); } void GPIO_init(){ //DEVICE_GPIO_PIN_FAULT initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_FAULT, GPIO_DIR_MODE_IN); GPIO_setPadConfig(DEVICE_GPIO_PIN_FAULT, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_FAULT, GPIO_QUAL_SYNC); //DEVICE_GPIO_PIN_SLEEP initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_SLEEP, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_SLEEP, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_SLEEP, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_SLEEP, 1); //DEVICE_GPIO_PIN_DRVR_CDR_A initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_DRVR_CDR_A, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_DRVR_CDR_A, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_DRVR_CDR_A, GPIO_QUAL_SYNC); //DEVICE_GPIO_PIN_DRVR_CDR_B initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_DRVR_CDR_B, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_DRVR_CDR_B, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_DRVR_CDR_B, GPIO_QUAL_SYNC); //DEVICE_GPIO_PIN_DECAY_1 initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_DECAY_1, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_DECAY_1, GPIO_PIN_TYPE_OD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_DECAY_1, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_DECAY_1, 1); //DEVICE_GPIO_PIN_DECAY_2 initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_DECAY_2, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_DECAY_2, GPIO_PIN_TYPE_OD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_DECAY_2, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_DECAY_2, 1); //DEVICE_GPIO_PIN_ENA initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_ENA, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_ENA, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_ENA, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_ENA, 0); //DEVICE_GPIO_PIN_COMM_LED initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_COMM_LED, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_COMM_LED, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_COMM_LED, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_COMM_LED, 1); //DEVICE_GPIO_PIN_LIFE initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_LIFE, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_LIFE, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_LIFE, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_LIFE, 1); //DEVICE_GPIO_PIN_485_ENA initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_485_ENA, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_485_ENA, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_485_ENA, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_485_ENA, 0); //GPIO44_Interrupt_Line initialization GPIO_setDirectionMode(GPIO44_Interrupt_Line, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(GPIO44_Interrupt_Line, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(GPIO44_Interrupt_Line, GPIO_QUAL_SYNC); //DEVICE_GPIO_PIN_ENB initialization GPIO_setDirectionMode(DEVICE_GPIO_PIN_ENB, GPIO_DIR_MODE_OUT); GPIO_setPadConfig(DEVICE_GPIO_PIN_ENB, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DEVICE_GPIO_PIN_ENB, GPIO_QUAL_SYNC); GPIO_writePin(DEVICE_GPIO_PIN_ENB, 0); } void INPUTXBAR_init(){ //myINPUTXBAR0 initialization XBAR_setInputPin(INPUTXBAR_BASE, XBAR_INPUT5, 245); } void INTERRUPT_init(){ // Interrupt Setings for INT_myADC0_1 Interrupt_register(INT_myADC0_1, &INT_myADC0_1_ISR); Interrupt_enable(INT_myADC0_1); // Interrupt Setings for INT_myCAN0_0 Interrupt_register(INT_myCAN0_0, &canISR); Interrupt_enable(INT_myCAN0_0); // Interrupt Setings for INT_myCAN0_1 Interrupt_register(INT_myCAN0_1, &canISR); Interrupt_disable(INT_myCAN0_1); // Interrupt Setings for INT_mySCI0_RX Interrupt_register(INT_mySCI0_RX, &SCIRXINTA_ISR); Interrupt_disable(INT_mySCI0_RX); // Interrupt Setings for INT_mySCI0_TX Interrupt_register(INT_mySCI0_TX, &SCITXINTA_ISR); Interrupt_enable(INT_mySCI0_TX); } void OUTPUTXBAR_init(){ //myOUTPUTXBAR0 initialization XBAR_setOutputLatchMode(OUTPUTXBAR_BASE, XBAR_OUTPUT1, false); XBAR_invertOutputSignal(OUTPUTXBAR_BASE, XBAR_OUTPUT1, false); //Mux configuration } void SCI_init(){ //mySCI0 initialization SCI_clearInterruptStatus(mySCI0_BASE, SCI_INT_RXFF | SCI_INT_TXFF | SCI_INT_FE | SCI_INT_OE | SCI_INT_PE | SCI_INT_RXERR | SCI_INT_RXRDY_BRKDT | SCI_INT_TXRDY); SCI_clearOverflowStatus(mySCI0_BASE); SCI_disableFIFO(mySCI0_BASE); SCI_resetChannels(mySCI0_BASE); SCI_setConfig(mySCI0_BASE, DEVICE_LSPCLK_FREQ, mySCI0_BAUDRATE, (SCI_CONFIG_WLEN_8|SCI_CONFIG_STOP_ONE|SCI_CONFIG_PAR_NONE)); SCI_disableLoopback(mySCI0_BASE); SCI_performSoftwareReset(mySCI0_BASE); SCI_enableInterrupt(mySCI0_BASE, SCI_INT_TXRDY); SCI_enableModule(mySCI0_BASE); } void SYNC_init(){ SysCtl_setSyncOutputConfig(SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT); // SOCA SysCtl_enableExtADCSOCSource(0); // SOCB SysCtl_enableExtADCSOCSource(0); }