Excerpt from "SysCtrl.h":

#define  OSCCLK_MHZ       20        /* input clock = 20 Mhz */
#define  PLL_FACTOR        2        /* factor, n = 2 */

#define  SYSCLKOUT_MHZ (OSCCLK_MHZ*PLL_FACTOR/2)  /* SYSCLKOUT = OSCCLK*n/2, sys_clk = 20 Mhz */

#define  HIGH_SPD_CLD_DIV 50     /* high peripheral clock = sys_clk / (HIGH_SPD_CLD_DIV*2) */
#define  LOW_SPD_CLD_DIV   1     /* low peripheral clock = sys_clk / (LOW_SPD_CLD_DIV*2)   */

#define  HSPCLK_KHZ    (SYSCLKOUT_MHZ*(1000/2)/HIGH_SPD_CLD_DIV) 
#define  LSPCLK_KHZ    (SYSCLKOUT_MHZ*(1000/2)/LOW_SPD_CLD_DIV) 



Excerpt from "SysCtrl.c":

void InitModClocks (void)
{
   EALLOW;

   // HISPCP/LOSPCP pre-scale register settings.  Note that
   // HISPCP (for ADC) is running considerably slower than
   // LOSPCP (for SCI-A).
   SysCtrlRegs.HISPCP.all = HIGH_SPD_CLD_DIV;
   SysCtrlRegs.LOSPCP.all = LOW_SPD_CLD_DIV;

   // XCLKOUT to SYSCLKOUT ratio.  Disable XclkOut Sig. Gen.
   SysCtrlRegs.XCLK.bit.XCLKOUTDIV    = 3;
      	
   // Clock enables set for the selected peripheral Modules.   
   // If you are not using a Module, leave the clock off to
   // save on power. 
   // 
   // Note: not all peripheral Modules are available on all
   // 280x derivatives.
   // Refer to the datasheet for your particular device. 

   SysCtrlRegs.PCLKCR0.bit.ADCENCLK   = 1;  // ADC
   SysCtrlRegs.PCLKCR0.bit.I2CAENCLK  = 0;  // I2C
   SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 0;  // eCAN-A
   SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 0;  // eCAP1
   SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 0;  // eCAP2
   SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 0;  // ePWM1
   SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 0;  // ePWM2
   SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 0;  // ePWM3
   SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 0;  // eQEP1
   SysCtrlRegs.PCLKCR0.bit.SCIAENCLK  = 1;  // SCI-A
   SysCtrlRegs.PCLKCR0.bit.SPIAENCLK  = 0;  // SPI-A
   SysCtrlRegs.PCLKCR0.bit.SPIBENCLK  = 0;  // SPI-B

   if ( (DevEmuRegs.PARTID.bit.PARTNO == PARTNO_2808) || 
        (DevEmuRegs.PARTID.bit.PARTNO == PARTNO_2806) )
   {
	   SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 0;  // eCAP3
	   SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 0;  // eCAP4
	   SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 0;  // ePWM4
	   SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 0;  // ePWM5
	   SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 0;  // ePWM6
	   SysCtrlRegs.PCLKCR0.bit.SCIBENCLK  = 0;  // SCI-B
	   SysCtrlRegs.PCLKCR0.bit.SPICENCLK  = 0;  // SPI-C
	   SysCtrlRegs.PCLKCR0.bit.SPIDENCLK  = 0;  // SPI-D
	   SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 0;  // eQEP2
   }

   if (DevEmuRegs.PARTID.bit.PARTNO == PARTNO_2808)
   {  
	   SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 0;  // eCAN-B
   }

   // Disable TBCLK within the ePWM  
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC  = 0;
                           
   EDIS;
}