    1/*

    2 * File: Inverter_000_test.c

    3 *

    4 * Code generated for Simulink model 'Inverter_000_test'.

    5 *

    6 * Model version                  : 1.126

    7 * Simulink Coder version         : 8.14 (R2018a) 06-Feb-2018

    8 * C/C++ source code generated on : Wed Apr 14 17:29:45 2021

    9 *

    10 * Target selection: ert.tlc

    11 * Embedded hardware selection: Texas Instruments->C2000

    12 * Code generation objectives: Unspecified

    13 * Validation result: Not run

    14 */

    15

    16#include "Inverter_000_test.h"

    17#include "Inverter_000_test_private.h"

    18

    19/* Block signals (default storage) */

    20B_Inverter_000_test_T Inverter_000_test_B;

    21

    22/* Block states (default storage) */

    23DW_Inverter_000_test_T Inverter_000_test_DW;

    24

    25/* Real-time model */

    26RT_MODEL_Inverter_000_test_T Inverter_000_test_M_;

    27RT_MODEL_Inverter_000_test_T *const Inverter_000_test_M = &Inverter_000_test_M_;

    28static void rate_monotonic_scheduler(void);

    29

    30/*

    31 * Set which subrates need to run this base step (base rate always runs).

    32 * This function must be called prior to calling the model step function

    33 * in order to "remember" which rates need to run this base step.  The

    34 * buffering of events allows for overlapping preemption.

    35 */

    36void Inverter_000_test_SetEventsForThisBaseStep(boolean_T *eventFlags)

    37{

    38  /* Task runs when its counter is zero, computed via rtmStepTask macro */

    39  eventFlags[1] = ((boolean_T)rtmStepTask(Inverter_000_test_M, 1));

    40}

    41

    42/*

    43 *   This function updates active task flag for each subrate

    44 * and rate transition flags for tasks that exchange data.

    45 * The function assumes rate-monotonic multitasking scheduler.

    46 * The function must be called at model base rate so that

    47 * the generated code self-manages all its subrates and rate

    48 * transition flags.

    49 */

    50static void rate_monotonic_scheduler(void)

    51{

    52  /* To ensure a deterministic data transfer between two rates,

    53   * data is transferred at the priority of a fast task and the frequency

    54   * of the slow task.  The following flags indicate when the data transfer

    55   * happens.  That is, a rate interaction flag is set true when both rates

    56   * will run, and false otherwise.

    57   */

    58

    59  /* tid 0 shares data with slower tid rate: 1 */

    60  Inverter_000_test_M->Timing.RateInteraction.TID0_1 =

    61    (Inverter_000_test_M->Timing.TaskCounters.TID[1] == 0);

    62

    63  /* Compute which subrates run during the next base time step.  Subrates

    64   * are an integer multiple of the base rate counter.  Therefore, the subtask

    65   * counter is reset when it reaches its limit (zero means run).

    66   */

    67  (Inverter_000_test_M->Timing.TaskCounters.TID[1])++;

    68  if ((Inverter_000_test_M->Timing.TaskCounters.TID[1]) > 1) {/* Sample time: [0.0001s, 0.0s] */

    69    Inverter_000_test_M->Timing.TaskCounters.TID[1] = 0;

    70  }

    71}

    72

    73real_T rt_roundd_snf(real_T u)

    74{

    75  real_T y;

    76  if (fabs(u) < 4.503599627370496E+15) {

    77    if (u >= 0.5) {

    78      y = floor(u + 0.5);

    79    } else if (u > -0.5) {

    80      y = u * 0.0;

    81    } else {

    82      y = ceil(u - 0.5);

    83    }

    84  } else {

    85    y = u;

    86  }

    87

    88  return y;

    89}

    90

    91real32_T rt_roundf_snf(real32_T u)

    92{

    93  real32_T y;

    94  if (fabsf(u) < 8.388608E+6F) {

    95    if (u >= 0.5F) {

    96      y = (real32_T)floor(u + 0.5F);

    97    } else if (u > -0.5F) {

    98      y = u * 0.0F;

    99    } else {

    100      y = (real32_T)ceil(u - 0.5F);

    101    }

    102  } else {

    103    y = u;

    104  }

    105

    106  return y;

    107}

    108

    109/* Model step function for TID0 */

    110void Inverter_000_test_step0(void)     /* Sample time: [5.0E-5s, 0.0s] */

    111{

    112  /* local block i/o variables */

    113  int32_T rtb_FloattoIQN[3];

    114  int32_T rtb_Sum5;

    115  int32_T rtb_Sum4_p;

    116  int32_T rtb_Sum1_p;

    117  int32_T rtb_u;

    118  int32_T rtb_Product7;

    119  int32_T rtb_u_g;

    120  int32_T rtb_u_a;

    121  int32_T rtb_Product5;

    122  int32_T rtb_Sum1;

    123  real32_T rtb_DataTypeConversion2[3];

    124  real32_T rtb_Gain2_b;

    125  real_T tmp;

    126  uint16_T tmp_0;

    127  real32_T rtb_DataTypeConversion2_tmp;

    128

    129  {                                    /* Sample time: [5.0E-5s, 0.0s] */

    130    rate_monotonic_scheduler();

    131  }

    132

    133  /* RateTransition: '<Root>/Rate Transition1' */

    134  if (Inverter_000_test_M->Timing.RateInteraction.TID0_1) {

    135    Inverter_000_test_B.RateTransition1 =

    136      Inverter_000_test_DW.RateTransition1_Buffer0;

    137  }

    138

    139  /* End of RateTransition: '<Root>/Rate Transition1' */

    140

    141  /* Gain: '<S4>/Gain3' */

    142  rtb_Gain2_b = Inverter_000_test_P.Gain3_Gain *

    143    Inverter_000_test_B.RateTransition1;

    144

    145  /* S-Function (stiiqmath_iq): '<S4>/Float to IQN2' */

    146

    147  /* C28x IQmath Library (stiiqmath_iq) - '<S4>/Float to IQN2' */

    148  {

    149    rtb_u_a = _IQ10 (rtb_Gain2_b);

    150  }

    151

    152  /* Product: '<S4>/Product5' incorporates:

    153   *  Constant: '<S4>/Constant10'

    154   *  Constant: '<S4>/Constant13'

    155   *  Constant: '<S4>/Constant14'

    156   */

    157  rtb_DataTypeConversion2_tmp = (real32_T)rtb_u_a * 0.0009765625F;

    158  rtb_DataTypeConversion2[0] = rtb_DataTypeConversion2_tmp *

    159    Inverter_000_test_P.Constant13_Value;

    160  rtb_DataTypeConversion2[1] = rtb_DataTypeConversion2_tmp *

    161    Inverter_000_test_P.Constant14_Value;

    162  rtb_DataTypeConversion2[2] = rtb_DataTypeConversion2_tmp *

    163    Inverter_000_test_P.Constant10_Value;

    164

    165  /* S-Function (stiiqmath_iq): '<S4>/Float to IQN' */

    166

    167  /* C28x IQmath Library (stiiqmath_iq) - '<S4>/Float to IQN' */

    168  {

    169    rtb_FloattoIQN[0] = _IQ10 (rtb_DataTypeConversion2[0]);

    170    rtb_FloattoIQN[1] = _IQ10 (rtb_DataTypeConversion2[1]);

    171    rtb_FloattoIQN[2] = _IQ10 (rtb_DataTypeConversion2[2]);

    172  }

    173

    174  /* S-Function (scheckfractionlength): '<S11>/ ' */

    175  rtb_u_a = rtb_FloattoIQN[0];

    176

    177  /* S-Function (scheckfractionlength): '<S12>/ ' incorporates:

    178   *  Constant: '<S4>/Constant11'

    179   */

    180  rtb_u = Inverter_000_test_P.Constant11_Value;

    181

    182  /* S-Function (scheckfractionlength): '<S12>/ 1' incorporates:

    183   *  Constant: '<S4>/Constant8'

    184   */

    185  rtb_Product5 = Inverter_000_test_P.Constant8_Value_e;

    186

    187  /* S-Function (scheckfractionlength): '<S12>/ 2' incorporates:

    188   *  Constant: '<S4>/Constant9'

    189   */

    190  rtb_u_g = Inverter_000_test_P.Constant9_Value;

    191

    192  /* Product: '<S12>/Product1' */

    193  rtb_Sum1 = rtb_u;

    194

    195  /* Sum: '<S12>/Sum2' incorporates:

    196   *  UnitDelay: '<S12>/Unit Delay'

    197   */

    198  Inverter_000_test_DW.UnitDelay_DSTATE += rtb_Sum1;

    199

    200  /* Switch: '<S14>/Switch' incorporates:

    201   *  Constant: '<S14>/1'

    202   *  RelationalOperator: '<S14>/Relational Operator'

    203   *  Sum: '<S14>/Sum2'

    204   */

    205  if (Inverter_000_test_DW.UnitDelay_DSTATE > Inverter_000_test_P.u_Value) {

    206    Inverter_000_test_DW.UnitDelay_DSTATE -= Inverter_000_test_P.u_Value;

    207  }

    208

    209  /* End of Switch: '<S14>/Switch' */

    210

    211  /* Switch: '<S14>/Switch1' incorporates:

    212   *  Constant: '<S14>/-1'

    213   *  Constant: '<S14>/1'

    214   *  RelationalOperator: '<S14>/Relational Operator1'

    215   *  Sum: '<S14>/Sum1'

    216   *  UnitDelay: '<S12>/Unit Delay'

    217   */

    218  if (Inverter_000_test_DW.UnitDelay_DSTATE < Inverter_000_test_P.u_Value_e) {

    219    Inverter_000_test_DW.UnitDelay_DSTATE += Inverter_000_test_P.u_Value;

    220  }

    221

    222  /* End of Switch: '<S14>/Switch1' */

    223

    224  /* Product: '<S12>/Product2' incorporates:

    225   *  UnitDelay: '<S12>/Unit Delay'

    226   */

    227  rtb_Sum1 = __IQmpy(Inverter_000_test_DW.UnitDelay_DSTATE, rtb_Product5, 29);

    228

    229  /* Sum: '<S12>/Sum1' */

    230  rtb_Sum1 += rtb_u_g;

    231

    232  /* Switch: '<S15>/Switch2' incorporates:

    233   *  Constant: '<S15>/1'

    234   *  RelationalOperator: '<S15>/Relational Operator2'

    235   *  Sum: '<S15>/Sum4'

    236   */

    237  if (rtb_Sum1 > Inverter_000_test_P.u_Value_f) {

    238    rtb_Sum1 -= Inverter_000_test_P.u_Value_f;

    239  }

    240

    241  /* End of Switch: '<S15>/Switch2' */

    242

    243  /* Switch: '<S15>/Switch3' incorporates:

    244   *  Constant: '<S15>/-1'

    245   *  Constant: '<S15>/1'

    246   *  RelationalOperator: '<S15>/Relational Operator3'

    247   *  Sum: '<S15>/Sum3'

    248   */

    249  if (rtb_Sum1 < Inverter_000_test_P.u_Value_c) {

    250    rtb_Sum1 += Inverter_000_test_P.u_Value_f;

    251  }

    252

    253  /* End of Switch: '<S15>/Switch3' */

    254

    255  /* S-Function (stiiqmath_iqtof): '<S4>/IQN to Float3' */

    256

    257  /* C28x IQmath Library (stiiqmath_iqtof) - '<S4>/IQN to Float3' */

    258  {

    259    rtb_Gain2_b = _IQ29toF (rtb_Sum1);

    260  }

    261

    262  /* Gain: '<S4>/Gain2' */

    263  rtb_Gain2_b *= Inverter_000_test_P.Gain2_Gain;

    264

    265  /* S-Function (stiiqmath_iq): '<S4>/Float to IQN1' */

    266

    267  /* C28x IQmath Library (stiiqmath_iq) - '<S4>/Float to IQN1' */

    268  {

    269    rtb_Sum1 = _IQ10 (rtb_Gain2_b);

    270  }

    271

    272  /* S-Function (stiiqmath_iqtrig): '<S11>/cos IQN' */

    273

    274  /* C28x IQmath Library (stiiqmath_iqtrig) - '<S11>/cos IQN' */

    275  {

    276    rtb_u_g = _IQ10cos(rtb_Sum1);

    277  }

    278

    279  /* Product: '<S11>/Product2' */

    280  rtb_Product5 = __IQmpy(rtb_u_a, rtb_u_g, 10);

    281

    282  /* S-Function (scheckfractionlength): '<S11>/ 1' */

    283  rtb_u_g = rtb_FloattoIQN[1];

    284

    285  /* S-Function (stiiqmath_iqtrig): '<S11>/sin IQN' */

    286

    287  /* C28x IQmath Library (stiiqmath_iqtrig) - '<S11>/sin IQN' */

    288  {

    289    rtb_u = _IQ10sin(rtb_Sum1);

    290  }

    291

    292  /* Product: '<S11>/Product3' */

    293  rtb_Sum5 = __IQmpy(rtb_u_g, rtb_u, 10);

    294

    295  /* S-Function (scheckfractionlength): '<S11>/ 3' */

    296  rtb_u = rtb_FloattoIQN[2];

    297

    298  /* Sum: '<S11>/Sum1' */

    299  rtb_Sum1_p = (rtb_Product5 - rtb_Sum5) + rtb_u;

    300

    301  /* S-Function (stiiqmath_iq): '<S11>/Float to IQN' incorporates:

    302   *  Constant: '<S11>/Constant'

    303   */

    304

    305  /* C28x IQmath Library (stiiqmath_iq) - '<S11>/Float to IQN' */

    306  {

    307    rtb_Sum5 = _IQ10 (Inverter_000_test_P.Constant_Value_j);

    308  }

    309

    310  /* Sum: '<S11>/Sum3' */

    311  rtb_Product5 = rtb_Sum1 - rtb_Sum5;

    312

    313  /* S-Function (stiiqmath_iqtrig): '<S11>/cos IQN1' */

    314

    315  /* C28x IQmath Library (stiiqmath_iqtrig) - '<S11>/cos IQN1' */

    316  {

    317    rtb_Sum4_p = _IQ10cos(rtb_Product5);

    318  }

    319

    320  /* Product: '<S11>/Product4' */

    321  rtb_Product7 = __IQmpy(rtb_u_a, rtb_Sum4_p, 10);

    322

    323  /* S-Function (stiiqmath_iqtrig): '<S11>/sin IQN1' */

    324

    325  /* C28x IQmath Library (stiiqmath_iqtrig) - '<S11>/sin IQN1' */

    326  {

    327    rtb_Sum4_p = _IQ10sin(rtb_Product5);

    328  }

    329

    330  /* Product: '<S11>/Product5' */

    331  rtb_Product5 = __IQmpy(rtb_u_g, rtb_Sum4_p, 10);

    332

    333  /* Sum: '<S11>/Sum4' */

    334  rtb_Sum4_p = (rtb_Product7 - rtb_Product5) + rtb_u;

    335

    336  /* Sum: '<S11>/Sum' */

    337  rtb_Product7 = rtb_Sum1 + rtb_Sum5;

    338

    339  /* S-Function (stiiqmath_iqtrig): '<S11>/cos IQN2' */

    340

    341  /* C28x IQmath Library (stiiqmath_iqtrig) - '<S11>/cos IQN2' */

    342  {

    343    rtb_Sum5 = _IQ10cos(rtb_Product7);

    344  }

    345

    346  /* Product: '<S11>/Product6' */

    347  rtb_Sum1 = __IQmpy(rtb_u_a, rtb_Sum5, 10);

    348

    349  /* S-Function (stiiqmath_iqtrig): '<S11>/sin IQN2' */

    350

    351  /* C28x IQmath Library (stiiqmath_iqtrig) - '<S11>/sin IQN2' */

    352  {

    353    rtb_Sum5 = _IQ10sin(rtb_Product7);

    354  }

    355

    356  /* Product: '<S11>/Product7' */

    357  rtb_Product7 = __IQmpy(rtb_u_g, rtb_Sum5, 10);

    358

    359  /* Sum: '<S11>/Sum5' */

    360  rtb_Sum5 = (rtb_Sum1 - rtb_Product7) + rtb_u;

    361

    362  /* RateTransition: '<Root>/Rate Transition60' */

    363  if (Inverter_000_test_M->Timing.RateInteraction.TID0_1) {

    364    Inverter_000_test_B.RateTransition60[0] = rtb_Sum1_p;

    365    Inverter_000_test_B.RateTransition60[1] = rtb_Sum4_p;

    366    Inverter_000_test_B.RateTransition60[2] = rtb_Sum5;

    367  }

    368

    369  /* End of RateTransition: '<Root>/Rate Transition60' */

    370

    371  /* RelationalOperator: '<Root>/Relational Operator2' incorporates:

    372   *  Constant: '<Root>/Constant3'

    373   */

    374  Inverter_000_test_B.RelationalOperator2[0] = (rtb_Sum1_p >

    375    Inverter_000_test_P.Constant3_Value);

    376  Inverter_000_test_B.RelationalOperator2[1] = (rtb_Sum4_p >

    377    Inverter_000_test_P.Constant3_Value);

    378  Inverter_000_test_B.RelationalOperator2[2] = (rtb_Sum5 >

    379    Inverter_000_test_P.Constant3_Value);

    380

    381  /* S-Function (c280xgpio_do): '<Root>/Digital Output' */

    382  {

    383    if (Inverter_000_test_B.RelationalOperator2[0])

    384      GpioDataRegs.GPBSET.bit.GPIO61 = 1;

    385    else

    386      GpioDataRegs.GPBCLEAR.bit.GPIO61 = 1;

    387  }

    388

    389  /* S-Function (c280xgpio_do): '<Root>/Digital Output1' */

    390  {

    391    if (Inverter_000_test_B.RelationalOperator2[1])

    392      GpioDataRegs.GPBSET.bit.GPIO63 = 1;

    393    else

    394      GpioDataRegs.GPBCLEAR.bit.GPIO63 = 1;

    395  }

    396

    397  /* S-Function (c280xgpio_do): '<Root>/Digital Output2' */

    398  {

    399    if (Inverter_000_test_B.RelationalOperator2[2])

    400      GpioDataRegs.GPCSET.bit.GPIO66 = 1;

    401    else

    402      GpioDataRegs.GPCCLEAR.bit.GPIO66 = 1;

    403  }

    404

    405  /* DataTypeConversion: '<Root>/Data Type Conversion2' */

    406  rtb_DataTypeConversion2[0] = (real32_T)rtb_Sum1_p * 0.0009765625F;

    407  rtb_DataTypeConversion2[1] = (real32_T)rtb_Sum4_p * 0.0009765625F;

    408  rtb_DataTypeConversion2[2] = (real32_T)rtb_Sum5 * 0.0009765625F;

    409

    410  /* RateTransition: '<Root>/Rate Transition5' */

    411  if (Inverter_000_test_M->Timing.RateInteraction.TID0_1) {

    412    Inverter_000_test_B.RateTransition5[0] = rtb_DataTypeConversion2[0];

    413    Inverter_000_test_B.RateTransition5[1] = rtb_DataTypeConversion2[1];

    414    Inverter_000_test_B.RateTransition5[2] = rtb_DataTypeConversion2[2];

    415  }

    416

    417  /* End of RateTransition: '<Root>/Rate Transition5' */

    418

    419  /* MATLABSystem: '<Root>/DAC2' incorporates:

    420   *  Constant: '<Root>/Constant'

    421   */

    422  tmp = rt_roundd_snf(Inverter_000_test_P.Constant_Value);

    423  if (tmp < 65536.0) {

    424    if (tmp >= 0.0) {

    425      tmp_0 = (uint16_T)tmp;

    426    } else {

    427      tmp_0 = 0U;

    428    }

    429  } else {

    430    tmp_0 = MAX_uint16_T;

    431  }

    432

    433  MW_C2000DACSat(2U, tmp_0);

    434

    435  /* End of MATLABSystem: '<Root>/DAC2' */

    436}

    437

    438/* Model step function for TID1 */

    439void Inverter_000_test_step1(void)     /* Sample time: [0.0001s, 0.0s] */

    440{

    441  /* local block i/o variables */

    442  real32_T rtb_Product19;

    443  int32_T rtb_IQNIQN;

    444  int32_T rtb_IQNIQN1;

    445  int32_T rtb_IQNIQN2;

    446  int64_T rtb_Sum;

    447  int64_T rtb_PhaseB;

    448  int32_T rtb_MinMax1;

    449  int32_T rtb_Saturation4[3];

    450  real32_T tmp;

    451  uint16_T tmp_0;

    452

    453  /* Saturate: '<Root>/Saturation4' */

    454  if (Inverter_000_test_B.RateTransition60[0] >

    455      Inverter_000_test_P.Saturation4_UpperSat) {

    456    rtb_Saturation4[0] = Inverter_000_test_P.Saturation4_UpperSat;

    457  } else if (Inverter_000_test_B.RateTransition60[0] <

    458             Inverter_000_test_P.Saturation4_LowerSat) {

    459    rtb_Saturation4[0] = Inverter_000_test_P.Saturation4_LowerSat;

    460  } else {

    461    rtb_Saturation4[0] = Inverter_000_test_B.RateTransition60[0];

    462  }

    463

    464  if (Inverter_000_test_B.RateTransition60[1] >

    465      Inverter_000_test_P.Saturation4_UpperSat) {

    466    rtb_Saturation4[1] = Inverter_000_test_P.Saturation4_UpperSat;

    467  } else if (Inverter_000_test_B.RateTransition60[1] <

    468             Inverter_000_test_P.Saturation4_LowerSat) {

    469    rtb_Saturation4[1] = Inverter_000_test_P.Saturation4_LowerSat;

    470  } else {

    471    rtb_Saturation4[1] = Inverter_000_test_B.RateTransition60[1];

    472  }

    473

    474  if (Inverter_000_test_B.RateTransition60[2] >

    475      Inverter_000_test_P.Saturation4_UpperSat) {

    476    rtb_Saturation4[2] = Inverter_000_test_P.Saturation4_UpperSat;

    477  } else if (Inverter_000_test_B.RateTransition60[2] <

    478             Inverter_000_test_P.Saturation4_LowerSat) {

    479    rtb_Saturation4[2] = Inverter_000_test_P.Saturation4_LowerSat;

    480  } else {

    481    rtb_Saturation4[2] = Inverter_000_test_B.RateTransition60[2];

    482  }

    483

    484  /* End of Saturate: '<Root>/Saturation4' */

    485

    486  /* Saturate: '<Root>/Saturation5' incorporates:

    487   *  Constant: '<Root>/Constant8'

    488   */

    489  if (Inverter_000_test_P.Constant8_Value >

    490      Inverter_000_test_P.Saturation5_UpperSat) {

    491    rtb_MinMax1 = Inverter_000_test_P.Saturation5_UpperSat;

    492  } else if (Inverter_000_test_P.Constant8_Value <

    493             Inverter_000_test_P.Saturation5_LowerSat) {

    494    rtb_MinMax1 = Inverter_000_test_P.Saturation5_LowerSat;

    495  } else {

    496    rtb_MinMax1 = Inverter_000_test_P.Constant8_Value;

    497  }

    498

    499  /* End of Saturate: '<Root>/Saturation5' */

    500

    501  /* Gain: '<S2>/Gain' */

    502  rtb_Product19 = (real32_T)Inverter_000_test_P.Gain_Gain * 4.65661287E-10F *

    503    ((real32_T)rtb_MinMax1 * 0.0009765625F);

    504

    505  /* S-Function (stiiqmath_iq): '<S2>/Float to IQN1' */

    506

    507  /* C28x IQmath Library (stiiqmath_iq) - '<S2>/Float to IQN1' */

    508  {

    509    rtb_MinMax1 = _IQ10 (rtb_Product19);

    510  }

    511

    512  /* S-Function (stiiqmath_iqdiv): '<S2>/IQN // IQN' */

    513

    514  /* C28x IQmath Library (stiiqmath_iqdiv) - '<S2>/IQN // IQN' */

    515  {

    516    rtb_IQNIQN = _IQ10div (rtb_Saturation4[0], rtb_MinMax1);

    517  }

    518

    519  /* S-Function (stiiqmath_iqdiv): '<S2>/IQN // IQN1' */

    520

    521  /* C28x IQmath Library (stiiqmath_iqdiv) - '<S2>/IQN // IQN1' */

    522  {

    523    rtb_IQNIQN1 = _IQ10div (rtb_Saturation4[1], rtb_MinMax1);

    524  }

    525

    526  /* S-Function (stiiqmath_iqdiv): '<S2>/IQN // IQN2' */

    527

    528  /* C28x IQmath Library (stiiqmath_iqdiv) - '<S2>/IQN // IQN2' */

    529  {

    530    rtb_IQNIQN2 = _IQ10div (rtb_Saturation4[2], rtb_MinMax1);

    531  }

    532

    533  /* MinMax: '<S5>/MinMax' */

    534  rtb_MinMax1 = rtb_IQNIQN;

    535  if (!(rtb_IQNIQN < rtb_IQNIQN1)) {

    536    rtb_MinMax1 = rtb_IQNIQN1;

    537  }

    538

    539  if (!(rtb_MinMax1 < rtb_IQNIQN2)) {

    540    rtb_MinMax1 = rtb_IQNIQN2;

    541  }

    542

    543  /* End of MinMax: '<S5>/MinMax' */

    544

    545  /* Gain: '<S5>/Gain' */

    546  rtb_PhaseB = (int64_T)Inverter_000_test_P.Gain_Gain_h * rtb_MinMax1;

    547

    548  /* MinMax: '<S5>/MinMax1' */

    549  rtb_MinMax1 = rtb_IQNIQN;

    550  if (!(rtb_IQNIQN > rtb_IQNIQN1)) {

    551    rtb_MinMax1 = rtb_IQNIQN1;

    552  }

    553

    554  if (!(rtb_MinMax1 > rtb_IQNIQN2)) {

    555    rtb_MinMax1 = rtb_IQNIQN2;

    556  }

    557

    558  /* End of MinMax: '<S5>/MinMax1' */

    559

    560  /* Sum: '<S5>/Sum' incorporates:

    561   *  Gain: '<S5>/Gain1'

    562   */

    563  rtb_Sum = (int64_T)Inverter_000_test_P.Gain1_Gain * rtb_MinMax1 + rtb_PhaseB;

    564

    565  /* Sum: '<S2>/Add17' */

    566  rtb_PhaseB = ((int64_T)rtb_IQNIQN1 << 32U) + rtb_Sum;

    567

    568  /* MATLABSystem: '<Root>/DAC' incorporates:

    569   *  Bias: '<Root>/Bias1'

    570   */

    571  tmp = rt_roundf_snf(Inverter_000_test_B.RateTransition5[1] +

    572                      Inverter_000_test_P.Bias1_Bias);

    573  if (tmp < 65536.0F) {

    574    if (tmp >= 0.0F) {

    575      tmp_0 = (uint16_T)tmp;

    576    } else {

    577      tmp_0 = 0U;

    578    }

    579  } else {

    580    tmp_0 = MAX_uint16_T;

    581  }

    582

    583  MW_C2000DACSat(0U, tmp_0);

    584

    585  /* End of MATLABSystem: '<Root>/DAC' */

    586

    587  /* Product: '<S1>/Product21' incorporates:

    588   *  Constant: '<S1>/Constant13'

    589   *  Constant: '<S1>/Constant14'

    590   *  Constant: '<S1>/Constant15'

    591   *  Product: '<S1>/Product20'

    592   *  Sum: '<S1>/Add15'

    593   *  Sum: '<S2>/Add16'

    594   */

    595  rtb_Product19 = ((real32_T)(((int64_T)rtb_IQNIQN << 32U) + rtb_Sum) *

    596                   2.27373675E-13F + Inverter_000_test_P.Constant15_Value) *

    597    Inverter_000_test_P.Constant13_Value_a *

    598    Inverter_000_test_P.Constant14_Value_m;

    599

    600  /* S-Function (c2802xpwm): '<S1>/ePWM' incorporates:

    601   *  Constant: '<Root>/Constant2'

    602   */

    603

    604  /*-- Update CMPA value for ePWM5 --*/

    605  {

    606    EPwm5Regs.CMPA.bit.CMPA = (uint16_T)(rtb_Product19);

    607  }

    608

    609  /*-- Update CMPB value for ePWM5 --*/

    610  {

    611    EPwm5Regs.CMPB.bit.CMPB = (uint16_T)(rtb_Product19);

    612  }

    613

    614  EPwm5Regs.DBRED.bit.DBRED = Inverter_000_test_P.Constant2_Value;

    615  EPwm5Regs.DBFED.bit.DBFED = Inverter_000_test_P.Constant2_Value;

    616

    617  /* Product: '<S1>/Product17' incorporates:

    618   *  Constant: '<S1>/Constant13'

    619   *  Constant: '<S1>/Constant14'

    620   *  Constant: '<S1>/Constant15'

    621   *  Product: '<S1>/Product16'

    622   *  Sum: '<S1>/Add13'

    623   *  Sum: '<S2>/Add18'

    624   */

    625  rtb_Product19 = ((real32_T)(((int64_T)rtb_IQNIQN2 << 32U) + rtb_Sum) *

    626                   2.27373675E-13F + Inverter_000_test_P.Constant15_Value) *

    627    Inverter_000_test_P.Constant13_Value_a *

    628    Inverter_000_test_P.Constant14_Value_m;

    629

    630  /* S-Function (c2802xpwm): '<S1>/ePWM1' incorporates:

    631   *  Constant: '<Root>/Constant2'

    632   */

    633

    634  /*-- Update CMPA value for ePWM3 --*/

    635  {

    636    EPwm3Regs.CMPA.bit.CMPA = (uint16_T)(rtb_Product19);

    637  }

    638

    639  /*-- Update CMPB value for ePWM3 --*/

    640  {

    641    EPwm3Regs.CMPB.bit.CMPB = (uint16_T)(rtb_Product19);

    642  }

    643

    644  EPwm3Regs.DBRED.bit.DBRED = Inverter_000_test_P.Constant2_Value;

    645  EPwm3Regs.DBFED.bit.DBFED = Inverter_000_test_P.Constant2_Value;

    646

    647  /* Product: '<S1>/Product15' incorporates:

    648   *  Constant: '<S1>/Constant13'

    649   *  Constant: '<S1>/Constant14'

    650   *  Constant: '<S1>/Constant15'

    651   *  Product: '<S1>/Product'

    652   *  Sum: '<S1>/Add'

    653   */

    654  rtb_Product19 = ((real32_T)rtb_PhaseB * 2.27373675E-13F +

    655                   Inverter_000_test_P.Constant15_Value) *

    656    Inverter_000_test_P.Constant13_Value_a *

    657    Inverter_000_test_P.Constant14_Value_m;

    658

    659  /* S-Function (c2802xpwm): '<S1>/ePWM2' incorporates:

    660   *  Constant: '<Root>/Constant2'

    661   */

    662

    663  /*-- Update CMPA value for ePWM6 --*/

    664  {

    665    EPwm6Regs.CMPA.bit.CMPA = (uint16_T)(rtb_Product19);

    666  }

    667

    668  /*-- Update CMPB value for ePWM6 --*/

    669  {

    670    EPwm6Regs.CMPB.bit.CMPB = (uint16_T)(rtb_Product19);

    671  }

    672

    673  EPwm6Regs.DBRED.bit.DBRED = Inverter_000_test_P.Constant2_Value;

    674  EPwm6Regs.DBFED.bit.DBFED = Inverter_000_test_P.Constant2_Value;

    675

    676  /* Product: '<S1>/Product19' incorporates:

    677   *  Constant: '<S1>/Constant13'

    678   *  Constant: '<S1>/Constant14'

    679   *  Constant: '<S1>/Constant15'

    680   *  Product: '<S1>/Product18'

    681   *  Sum: '<S1>/Add14'

    682   */

    683  rtb_Product19 = ((real32_T)rtb_Sum * 2.27373675E-13F +

    684                   Inverter_000_test_P.Constant15_Value) *

    685    Inverter_000_test_P.Constant13_Value_a *

    686    Inverter_000_test_P.Constant14_Value_m;

    687

    688  /* S-Function (c2802xpwm): '<S1>/ePWM3' incorporates:

    689   *  Constant: '<Root>/Constant2'

    690   */

    691

    692  /*-- Update CMPA value for ePWM4 --*/

    693  {

    694    EPwm4Regs.CMPA.bit.CMPA = (uint16_T)(rtb_Product19);

    695  }

    696

    697  /*-- Update CMPB value for ePWM4 --*/

    698  {

    699    EPwm4Regs.CMPB.bit.CMPB = (uint16_T)(rtb_Product19);

    700  }

    701

    702  EPwm4Regs.DBRED.bit.DBRED = Inverter_000_test_P.Constant2_Value;

    703  EPwm4Regs.DBFED.bit.DBFED = Inverter_000_test_P.Constant2_Value;

    704

    705  /* MATLABSystem: '<Root>/DAC1' incorporates:

    706   *  Bias: '<Root>/Bias2'

    707   *  DataTypeConversion: '<Root>/Data Type Conversion3'

    708   *  Gain: '<Root>/Gain2'

    709   */

    710  tmp = rt_roundf_snf((real32_T)rtb_PhaseB * 2.27373675E-13F *

    711                      Inverter_000_test_P.Gain2_Gain_f +

    712                      Inverter_000_test_P.Bias2_Bias);

    713  if (tmp < 65536.0F) {

    714    if (tmp >= 0.0F) {

    715      tmp_0 = (uint16_T)tmp;

    716    } else {

    717      tmp_0 = 0U;

    718    }

    719  } else {

    720    tmp_0 = MAX_uint16_T;

    721  }

    722

    723  MW_C2000DACSat(1U, tmp_0);

    724

    725  /* End of MATLABSystem: '<Root>/DAC1' */

    726

    727  /* Update for RateTransition: '<Root>/Rate Transition1' incorporates:

    728   *  Constant: '<Root>/Constant14'

    729   */

    730  Inverter_000_test_DW.RateTransition1_Buffer0 =

    731    Inverter_000_test_P.Constant14_Value_mo;

    732}

    733

    734/* Model initialize function */

    735void Inverter_000_test_initialize(void)

    736{

    737  /* Registration code */

    738

    739  /* initialize real-time model */

    740  (void) memset((void *)Inverter_000_test_M, 0,

    741                sizeof(RT_MODEL_Inverter_000_test_T));

    742

    743  /* block I/O */

    744  (void) memset(((void *) &Inverter_000_test_B), 0,

    745                sizeof(B_Inverter_000_test_T));

    746

    747  /* states (dwork) */

    748  (void) memset((void *)&Inverter_000_test_DW, 0,

    749                sizeof(DW_Inverter_000_test_T));

    750

    751  /* Start for RateTransition: '<Root>/Rate Transition1' */

    752  Inverter_000_test_B.RateTransition1 =

    753    Inverter_000_test_P.RateTransition1_InitialConditio;

    754

    755  /* Start for S-Function (c280xgpio_do): '<Root>/Digital Output' */

    756  EALLOW;

    757  GpioCtrlRegs.GPBMUX2.all &= 0xF3FFFFFF;

    758  GpioCtrlRegs.GPBDIR.all |= 0x20000000;

    759  EDIS;

    760

    761  /* Start for S-Function (c280xgpio_do): '<Root>/Digital Output1' */

    762  EALLOW;

    763  GpioCtrlRegs.GPBMUX2.all &= 0x3FFFFFFF;

    764  GpioCtrlRegs.GPBDIR.all |= 0x80000000;

    765  EDIS;

    766

    767  /* Start for S-Function (c280xgpio_do): '<Root>/Digital Output2' */

    768  EALLOW;

    769  GpioCtrlRegs.GPCMUX1.all &= 0xFFFFFFCF;

    770  GpioCtrlRegs.GPCDIR.all |= 0x4;

    771  EDIS;

    772

    773  /* Start for MATLABSystem: '<Root>/DAC' */

    774  MW_ConfigureDACA();

    775

    776  /* Start for S-Function (c2802xpwm): '<S1>/ePWM' incorporates:

    777   *  Constant: '<Root>/Constant2'

    778   */

    779  EALLOW;

    780  CpuSysRegs.PCLKCR2.bit.EPWM5 = 1;

    781  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

    782  EDIS;

    783

    784  /*** Initialize ePWM5 modules ***/

    785  {

    786    /*  // Time Base Control Register

    787       EPwm5Regs.TBCTL.bit.CTRMODE              = 2;          // Counter Mode

    788       EPwm5Regs.TBCTL.bit.SYNCOSEL             = 3;          // Sync Output Select

    789       EPwm5Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select

    790       EPwm5Regs.TBCTL.bit.PHSEN                = 0;          // Phase Load Enable

    791       EPwm5Regs.TBCTL.bit.PHSDIR               = 0;          // Phase Direction Bit

    792       EPwm5Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler

    793       EPwm5Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler

    794       EPwm5Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse

    795     */

    796    EPwm5Regs.TBCTL.all = (EPwm5Regs.TBCTL.all & ~0x3FFF) | 0x32;

    797

    798    /*-- Setup Time-Base (TB) Submodule --*/

    799    EPwm5Regs.TBPRD = 12500;           // Time Base Period Register

    800

    801    /* // Time-Base Phase Register

    802       EPwm5Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register

    803     */

    804    EPwm5Regs.TBPHS.all = (EPwm5Regs.TBPHS.all & ~0xFFFF0000) | 0x0;

    805

    806    // Time Base Counter Register

    807    EPwm5Regs.TBCTR = 0x0000;          /* Clear counter*/

    808

    809    /*-- Setup Counter_Compare (CC) Submodule --*/

    810    /*	// Counter Compare Control Register

    811       EPwm5Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode

    812       EPwm5Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode

    813       EPwm5Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load

    814       EPwm5Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load

    815     */

    816    EPwm5Regs.CMPCTL.all = (EPwm5Regs.CMPCTL.all & ~0x5F) | 0x0;

    817

    818    /* EPwm5Regs.CMPCTL2.bit.SHDWCMODE           = 0;  // Compare C Register Block Operating Mode

    819

    820       EPwm5Regs.CMPCTL2.bit.SHDWDMODE           = 0;  // Compare D Register Block Operating Mode

    821     */

    822    EPwm5Regs.CMPCTL2.all = (EPwm5Regs.CMPCTL2.all & ~0x50) | 0x0;

    823    EPwm5Regs.CMPA.bit.CMPA = 3750;    // Counter Compare A Register

    824    EPwm5Regs.CMPB.bit.CMPB = 3750;    // Counter Compare B Register

    825    EPwm5Regs.CMPC = 32000;            // Counter Compare C Register

    826    EPwm5Regs.CMPD = 32000;            // Counter Compare D Register

    827

    828    /*-- Setup Action-Qualifier (AQ) Submodule --*/

    829    EPwm5Regs.AQCTLA.all = 150;        // Action Qualifier Control Register For Output A

    830    EPwm5Regs.AQCTLB.all = 1545;       // Action Qualifier Control Register For Output B

    831

    832    /*	// Action Qualifier Software Force Register

    833       EPwm5Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options

    834     */

    835    EPwm5Regs.AQSFRC.all = (EPwm5Regs.AQSFRC.all & ~0xC0) | 0x0;

    836

    837    /*	// Action Qualifier Continuous S/W Force Register

    838       EPwm5Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A

    839       EPwm5Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B

    840     */

    841    EPwm5Regs.AQCSFRC.all = (EPwm5Regs.AQCSFRC.all & ~0xF) | 0x0;

    842

    843    /*-- Setup Dead-Band Generator (DB) Submodule --*/

    844    /*	// Dead-Band Generator Control Register

    845       EPwm5Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control

    846       EPwm5Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control

    847       EPwm5Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control

    848       EPwm5Regs.DBCTL.bit.HALFCYCLE            = 0;          // Half Cycle Clocking Enable

    849     */

    850    EPwm5Regs.DBCTL.all = (EPwm5Regs.DBCTL.all & ~0x803F) | 0xB;

    851    EPwm5Regs.DBRED.bit.DBRED = 0;     // Dead-Band Generator Rising Edge Delay Count Register

    852    EPwm5Regs.DBFED.bit.DBFED = 0;     // Dead-Band Generator Falling Edge Delay Count Register

    853

    854    /*-- Setup Event-Trigger (ET) Submodule --*/

    855    /*	// Event Trigger Selection and Pre-Scale Register

    856       EPwm5Regs.ETSEL.bit.SOCAEN               = 0;          // Start of Conversion A Enable

    857       EPwm5Regs.ETSEL.bit.SOCASELCMP = 0;

    858       EPwm5Regs.ETSEL.bit.SOCASEL              = 0 ;          // Start of Conversion A Select

    859       EPwm5Regs.ETPS.bit.SOCAPRD               = 1;          // EPWM5SOCA Period Select

    860

    861       EPwm5Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable

    862

    863       EPwm5Regs.ETSEL.bit.SOCBSELCMP = 0;

    864       EPwm5Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select

    865       EPwm5Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM5SOCB Period Select

    866       EPwm5Regs.ETSEL.bit.INTEN                = 0;          // EPWM5INTn Enable

    867       EPwm5Regs.ETSEL.bit.INTSELCMP = 0;

    868       EPwm5Regs.ETSEL.bit.INTSEL              = 1;          // Start of Conversion A Select

    869

    870       EPwm5Regs.ETPS.bit.INTPRD                = 1;          // EPWM5INTn Period Select

    871     */

    872    EPwm5Regs.ETSEL.all = (EPwm5Regs.ETSEL.all & ~0xFF7F) | 0x1001;

    873    EPwm5Regs.ETPS.all = (EPwm5Regs.ETPS.all & ~0x3303) | 0x1101;

    874

    875    /*-- Setup PWM-Chopper (PC) Submodule --*/

    876    /*	// PWM Chopper Control Register

    877       EPwm5Regs.PCCTL.bit.CHPEN                = 0;          // PWM chopping enable

    878       EPwm5Regs.PCCTL.bit.CHPFREQ              = 0;          // Chopping clock frequency

    879       EPwm5Regs.PCCTL.bit.OSHTWTH              = 0;          // One-shot pulse width

    880       EPwm5Regs.PCCTL.bit.CHPDUTY              = 0;          // Chopping clock Duty cycle

    881     */

    882    EPwm5Regs.PCCTL.all = (EPwm5Regs.PCCTL.all & ~0x7FF) | 0x0;

    883

    884    /*-- Set up Trip-Zone (TZ) Submodule --*/

    885    EALLOW;

    886    EPwm5Regs.TZSEL.all = 0;           // Trip Zone Select Register

    887

    888    /*	// Trip Zone Control Register

    889       EPwm5Regs.TZCTL.bit.TZA                  = 3;          // TZ1 to TZ6 Trip Action On EPWM5A

    890       EPwm5Regs.TZCTL.bit.TZB                  = 3;          // TZ1 to TZ6 Trip Action On EPWM5B

    891       EPwm5Regs.TZCTL.bit.DCAEVT1              = 3;          // EPWM5A action on DCAEVT1

    892       EPwm5Regs.TZCTL.bit.DCAEVT2              = 3;          // EPWM5A action on DCAEVT2

    893       EPwm5Regs.TZCTL.bit.DCBEVT1              = 3;          // EPWM5B action on DCBEVT1

    894       EPwm5Regs.TZCTL.bit.DCBEVT2              = 3;          // EPWM5B action on DCBEVT2

    895     */

    896    EPwm5Regs.TZCTL.all = (EPwm5Regs.TZCTL.all & ~0xFFF) | 0xFFF;

    897

    898    /*	// Trip Zone Enable Interrupt Register

    899       EPwm5Regs.TZEINT.bit.OST                 = 0;          // Trip Zones One Shot Int Enable

    900       EPwm5Regs.TZEINT.bit.CBC                 = 0;          // Trip Zones Cycle By Cycle Int Enable

    901       EPwm5Regs.TZEINT.bit.DCAEVT1             = 0;          // Digital Compare A Event 1 Int Enable

    902       EPwm5Regs.TZEINT.bit.DCAEVT2             = 0;          // Digital Compare A Event 2 Int Enable

    903       EPwm5Regs.TZEINT.bit.DCBEVT1             = 0;          // Digital Compare B Event 1 Int Enable

    904       EPwm5Regs.TZEINT.bit.DCBEVT2             = 0;          // Digital Compare B Event 2 Int Enable

    905     */

    906    EPwm5Regs.TZEINT.all = (EPwm5Regs.TZEINT.all & ~0x7E) | 0x0;

    907

    908    /*	// Digital Compare A Control Register

    909       EPwm5Regs.DCACTL.bit.EVT1SYNCE           = 0;          // DCAEVT1 SYNC Enable

    910       EPwm5Regs.DCACTL.bit.EVT1SOCE            = 1;          // DCAEVT1 SOC Enable

    911       EPwm5Regs.DCACTL.bit.EVT1FRCSYNCSEL      = 0;          // DCAEVT1 Force Sync Signal

    912       EPwm5Regs.DCACTL.bit.EVT1SRCSEL          = 0;          // DCAEVT1 Source Signal

    913       EPwm5Regs.DCACTL.bit.EVT2FRCSYNCSEL      = 0;          // DCAEVT2 Force Sync Signal

    914       EPwm5Regs.DCACTL.bit.EVT2SRCSEL          = 0;          // DCAEVT2 Source Signal

    915     */

    916    EPwm5Regs.DCACTL.all = (EPwm5Regs.DCACTL.all & ~0x30F) | 0x4;

    917

    918    /*	// Digital Compare B Control Register

    919       EPwm5Regs.DCBCTL.bit.EVT1SYNCE           = 0;          // DCBEVT1 SYNC Enable

    920       EPwm5Regs.DCBCTL.bit.EVT1SOCE            = 0;          // DCBEVT1 SOC Enable

    921       EPwm5Regs.DCBCTL.bit.EVT1FRCSYNCSEL      = 0;          // DCBEVT1 Force Sync Signal

    922       EPwm5Regs.DCBCTL.bit.EVT1SRCSEL          = 0;          // DCBEVT1 Source Signal

    923       EPwm5Regs.DCBCTL.bit.EVT2FRCSYNCSEL      = 0;          // DCBEVT2 Force Sync Signal

    924       EPwm5Regs.DCBCTL.bit.EVT2SRCSEL          = 0;          // DCBEVT2 Source Signal

    925     */

    926    EPwm5Regs.DCBCTL.all = (EPwm5Regs.DCBCTL.all & ~0x30F) | 0x0;

    927

    928    /*	// Digital Compare Trip Select Register

    929       EPwm5Regs.DCTRIPSEL.bit.DCAHCOMPSEL      = 0;          // Digital Compare A High COMP Input Select

    930

    931       EPwm5Regs.DCTRIPSEL.bit.DCALCOMPSEL      = 1;          // Digital Compare A Low COMP Input Select

    932       EPwm5Regs.DCTRIPSEL.bit.DCBHCOMPSEL      = 0;          // Digital Compare B High COMP Input Select

    933       EPwm5Regs.DCTRIPSEL.bit.DCBLCOMPSEL      = 1;          // Digital Compare B Low COMP Input Select

    934

    935

    936

    937

    938

    939     */

    940    EPwm5Regs.DCTRIPSEL.all = (EPwm5Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;

    941

    942    /*	// Trip Zone Digital Comparator Select Register

    943       EPwm5Regs.TZDCSEL.bit.DCAEVT1            = 0;          // Digital Compare Output A Event 1

    944       EPwm5Regs.TZDCSEL.bit.DCAEVT2            = 0;          // Digital Compare Output A Event 2

    945       EPwm5Regs.TZDCSEL.bit.DCBEVT1            = 0;          // Digital Compare Output B Event 1

    946       EPwm5Regs.TZDCSEL.bit.DCBEVT2            = 0;          // Digital Compare Output B Event 2

    947     */

    948    EPwm5Regs.TZDCSEL.all = (EPwm5Regs.TZDCSEL.all & ~0xFFF) | 0x0;

    949

    950    /*	// Digital Compare Filter Control Register

    951       EPwm5Regs.DCFCTL.bit.BLANKE              = 0;          // Blanking Enable/Disable

    952       EPwm5Regs.DCFCTL.bit.PULSESEL            = 1;          // Pulse Select for Blanking & Capture Alignment

    953       EPwm5Regs.DCFCTL.bit.BLANKINV            = 0;          // Blanking Window Inversion

    954       EPwm5Regs.DCFCTL.bit.SRCSEL              = 0;          // Filter Block Signal Source Select

    955     */

    956    EPwm5Regs.DCFCTL.all = (EPwm5Regs.DCFCTL.all & ~0x3F) | 0x10;

    957    EPwm5Regs.DCFOFFSET = 0;           // Digital Compare Filter Offset Register

    958    EPwm5Regs.DCFWINDOW = 0;           // Digital Compare Filter Window Register

    959

    960    /*	// Digital Compare Capture Control Register

    961       EPwm5Regs.DCCAPCTL.bit.CAPE              = 0;          // Counter Capture Enable

    962     */

    963    EPwm5Regs.DCCAPCTL.all = (EPwm5Regs.DCCAPCTL.all & ~0x1) | 0x0;

    964

    965    /*	// HRPWM Configuration Register

    966       EPwm5Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit

    967       EPwm5Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit

    968     */

    969    EPwm5Regs.HRCNFG.all = (EPwm5Regs.HRCNFG.all & ~0xA0) | 0x0;

    970

    971    /* Update the Link Registers with the link value for all the Compare values and TBPRD */

    972    /* No error is thrown if the ePWM register exists in the model or not */

    973    EPwm5Regs.EPWMXLINK.bit.TBPRDLINK = 4;

    974    EPwm5Regs.EPWMXLINK.bit.CMPALINK = 4;

    975    EPwm5Regs.EPWMXLINK.bit.CMPBLINK = 4;

    976    EPwm5Regs.EPWMXLINK.bit.CMPCLINK = 4;

    977    EPwm5Regs.EPWMXLINK.bit.CMPDLINK = 4;

    978    EDIS;

    979    EALLOW;

    980    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

    981    EDIS;

    982  }

    983

    984  /* Start for S-Function (c2802xpwm): '<S1>/ePWM1' incorporates:

    985   *  Constant: '<Root>/Constant2'

    986   */

    987  EALLOW;

    988  CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;

    989  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

    990  EDIS;

    991

    992  /*** Initialize ePWM3 modules ***/

    993  {

    994    /*  // Time Base Control Register

    995       EPwm3Regs.TBCTL.bit.CTRMODE              = 2;          // Counter Mode

    996       EPwm3Regs.TBCTL.bit.SYNCOSEL             = 3;          // Sync Output Select

    997       EPwm3Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select

    998       EPwm3Regs.TBCTL.bit.PHSEN                = 0;          // Phase Load Enable

    999       EPwm3Regs.TBCTL.bit.PHSDIR               = 0;          // Phase Direction Bit

    1000       EPwm3Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler

    1001       EPwm3Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler

    1002       EPwm3Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse

    1003     */

    1004    EPwm3Regs.TBCTL.all = (EPwm3Regs.TBCTL.all & ~0x3FFF) | 0x32;

    1005

    1006    /*-- Setup Time-Base (TB) Submodule --*/

    1007    EPwm3Regs.TBPRD = 12500;           // Time Base Period Register

    1008

    1009    /* // Time-Base Phase Register

    1010       EPwm3Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register

    1011     */

    1012    EPwm3Regs.TBPHS.all = (EPwm3Regs.TBPHS.all & ~0xFFFF0000) | 0x0;

    1013

    1014    // Time Base Counter Register

    1015    EPwm3Regs.TBCTR = 0x0000;          /* Clear counter*/

    1016

    1017    /*-- Setup Counter_Compare (CC) Submodule --*/

    1018    /*	// Counter Compare Control Register

    1019       EPwm3Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode

    1020       EPwm3Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode

    1021       EPwm3Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load

    1022       EPwm3Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load

    1023     */

    1024    EPwm3Regs.CMPCTL.all = (EPwm3Regs.CMPCTL.all & ~0x5F) | 0x0;

    1025

    1026    /* EPwm3Regs.CMPCTL2.bit.SHDWCMODE           = 0;  // Compare C Register Block Operating Mode

    1027

    1028       EPwm3Regs.CMPCTL2.bit.SHDWDMODE           = 0;  // Compare D Register Block Operating Mode

    1029     */

    1030    EPwm3Regs.CMPCTL2.all = (EPwm3Regs.CMPCTL2.all & ~0x50) | 0x0;

    1031    EPwm3Regs.CMPA.bit.CMPA = 3750;    // Counter Compare A Register

    1032    EPwm3Regs.CMPB.bit.CMPB = 3750;    // Counter Compare B Register

    1033    EPwm3Regs.CMPC = 32000;            // Counter Compare C Register

    1034    EPwm3Regs.CMPD = 32000;            // Counter Compare D Register

    1035

    1036    /*-- Setup Action-Qualifier (AQ) Submodule --*/

    1037    EPwm3Regs.AQCTLA.all = 150;        // Action Qualifier Control Register For Output A

    1038    EPwm3Regs.AQCTLB.all = 1545;       // Action Qualifier Control Register For Output B

    1039

    1040    /*	// Action Qualifier Software Force Register

    1041       EPwm3Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options

    1042     */

    1043    EPwm3Regs.AQSFRC.all = (EPwm3Regs.AQSFRC.all & ~0xC0) | 0x0;

    1044

    1045    /*	// Action Qualifier Continuous S/W Force Register

    1046       EPwm3Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A

    1047       EPwm3Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B

    1048     */

    1049    EPwm3Regs.AQCSFRC.all = (EPwm3Regs.AQCSFRC.all & ~0xF) | 0x0;

    1050

    1051    /*-- Setup Dead-Band Generator (DB) Submodule --*/

    1052    /*	// Dead-Band Generator Control Register

    1053       EPwm3Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control

    1054       EPwm3Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control

    1055       EPwm3Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control

    1056       EPwm3Regs.DBCTL.bit.HALFCYCLE            = 0;          // Half Cycle Clocking Enable

    1057     */

    1058    EPwm3Regs.DBCTL.all = (EPwm3Regs.DBCTL.all & ~0x803F) | 0xB;

    1059    EPwm3Regs.DBRED.bit.DBRED = 0;     // Dead-Band Generator Rising Edge Delay Count Register

    1060    EPwm3Regs.DBFED.bit.DBFED = 0;     // Dead-Band Generator Falling Edge Delay Count Register

    1061

    1062    /*-- Setup Event-Trigger (ET) Submodule --*/

    1063    /*	// Event Trigger Selection and Pre-Scale Register

    1064       EPwm3Regs.ETSEL.bit.SOCAEN               = 0;          // Start of Conversion A Enable

    1065       EPwm3Regs.ETSEL.bit.SOCASELCMP = 0;

    1066       EPwm3Regs.ETSEL.bit.SOCASEL              = 0 ;          // Start of Conversion A Select

    1067       EPwm3Regs.ETPS.bit.SOCAPRD               = 1;          // EPWM3SOCA Period Select

    1068

    1069       EPwm3Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable

    1070

    1071       EPwm3Regs.ETSEL.bit.SOCBSELCMP = 0;

    1072       EPwm3Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select

    1073       EPwm3Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM3SOCB Period Select

    1074       EPwm3Regs.ETSEL.bit.INTEN                = 0;          // EPWM3INTn Enable

    1075       EPwm3Regs.ETSEL.bit.INTSELCMP = 0;

    1076       EPwm3Regs.ETSEL.bit.INTSEL              = 1;          // Start of Conversion A Select

    1077

    1078       EPwm3Regs.ETPS.bit.INTPRD                = 1;          // EPWM3INTn Period Select

    1079     */

    1080    EPwm3Regs.ETSEL.all = (EPwm3Regs.ETSEL.all & ~0xFF7F) | 0x1001;

    1081    EPwm3Regs.ETPS.all = (EPwm3Regs.ETPS.all & ~0x3303) | 0x1101;

    1082

    1083    /*-- Setup PWM-Chopper (PC) Submodule --*/

    1084    /*	// PWM Chopper Control Register

    1085       EPwm3Regs.PCCTL.bit.CHPEN                = 0;          // PWM chopping enable

    1086       EPwm3Regs.PCCTL.bit.CHPFREQ              = 0;          // Chopping clock frequency

    1087       EPwm3Regs.PCCTL.bit.OSHTWTH              = 0;          // One-shot pulse width

    1088       EPwm3Regs.PCCTL.bit.CHPDUTY              = 0;          // Chopping clock Duty cycle

    1089     */

    1090    EPwm3Regs.PCCTL.all = (EPwm3Regs.PCCTL.all & ~0x7FF) | 0x0;

    1091

    1092    /*-- Set up Trip-Zone (TZ) Submodule --*/

    1093    EALLOW;

    1094    EPwm3Regs.TZSEL.all = 0;           // Trip Zone Select Register

    1095

    1096    /*	// Trip Zone Control Register

    1097       EPwm3Regs.TZCTL.bit.TZA                  = 3;          // TZ1 to TZ6 Trip Action On EPWM3A

    1098       EPwm3Regs.TZCTL.bit.TZB                  = 3;          // TZ1 to TZ6 Trip Action On EPWM3B

    1099       EPwm3Regs.TZCTL.bit.DCAEVT1              = 3;          // EPWM3A action on DCAEVT1

    1100       EPwm3Regs.TZCTL.bit.DCAEVT2              = 3;          // EPWM3A action on DCAEVT2

    1101       EPwm3Regs.TZCTL.bit.DCBEVT1              = 3;          // EPWM3B action on DCBEVT1

    1102       EPwm3Regs.TZCTL.bit.DCBEVT2              = 3;          // EPWM3B action on DCBEVT2

    1103     */

    1104    EPwm3Regs.TZCTL.all = (EPwm3Regs.TZCTL.all & ~0xFFF) | 0xFFF;

    1105

    1106    /*	// Trip Zone Enable Interrupt Register

    1107       EPwm3Regs.TZEINT.bit.OST                 = 0;          // Trip Zones One Shot Int Enable

    1108       EPwm3Regs.TZEINT.bit.CBC                 = 0;          // Trip Zones Cycle By Cycle Int Enable

    1109       EPwm3Regs.TZEINT.bit.DCAEVT1             = 0;          // Digital Compare A Event 1 Int Enable

    1110       EPwm3Regs.TZEINT.bit.DCAEVT2             = 0;          // Digital Compare A Event 2 Int Enable

    1111       EPwm3Regs.TZEINT.bit.DCBEVT1             = 0;          // Digital Compare B Event 1 Int Enable

    1112       EPwm3Regs.TZEINT.bit.DCBEVT2             = 0;          // Digital Compare B Event 2 Int Enable

    1113     */

    1114    EPwm3Regs.TZEINT.all = (EPwm3Regs.TZEINT.all & ~0x7E) | 0x0;

    1115

    1116    /*	// Digital Compare A Control Register

    1117       EPwm3Regs.DCACTL.bit.EVT1SYNCE           = 0;          // DCAEVT1 SYNC Enable

    1118       EPwm3Regs.DCACTL.bit.EVT1SOCE            = 1;          // DCAEVT1 SOC Enable

    1119       EPwm3Regs.DCACTL.bit.EVT1FRCSYNCSEL      = 0;          // DCAEVT1 Force Sync Signal

    1120       EPwm3Regs.DCACTL.bit.EVT1SRCSEL          = 0;          // DCAEVT1 Source Signal

    1121       EPwm3Regs.DCACTL.bit.EVT2FRCSYNCSEL      = 0;          // DCAEVT2 Force Sync Signal

    1122       EPwm3Regs.DCACTL.bit.EVT2SRCSEL          = 0;          // DCAEVT2 Source Signal

    1123     */

    1124    EPwm3Regs.DCACTL.all = (EPwm3Regs.DCACTL.all & ~0x30F) | 0x4;

    1125

    1126    /*	// Digital Compare B Control Register

    1127       EPwm3Regs.DCBCTL.bit.EVT1SYNCE           = 0;          // DCBEVT1 SYNC Enable

    1128       EPwm3Regs.DCBCTL.bit.EVT1SOCE            = 0;          // DCBEVT1 SOC Enable

    1129       EPwm3Regs.DCBCTL.bit.EVT1FRCSYNCSEL      = 0;          // DCBEVT1 Force Sync Signal

    1130       EPwm3Regs.DCBCTL.bit.EVT1SRCSEL          = 0;          // DCBEVT1 Source Signal

    1131       EPwm3Regs.DCBCTL.bit.EVT2FRCSYNCSEL      = 0;          // DCBEVT2 Force Sync Signal

    1132       EPwm3Regs.DCBCTL.bit.EVT2SRCSEL          = 0;          // DCBEVT2 Source Signal

    1133     */

    1134    EPwm3Regs.DCBCTL.all = (EPwm3Regs.DCBCTL.all & ~0x30F) | 0x0;

    1135

    1136    /*	// Digital Compare Trip Select Register

    1137       EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL      = 0;          // Digital Compare A High COMP Input Select

    1138

    1139       EPwm3Regs.DCTRIPSEL.bit.DCALCOMPSEL      = 1;          // Digital Compare A Low COMP Input Select

    1140       EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL      = 0;          // Digital Compare B High COMP Input Select

    1141       EPwm3Regs.DCTRIPSEL.bit.DCBLCOMPSEL      = 1;          // Digital Compare B Low COMP Input Select

    1142

    1143

    1144

    1145

    1146

    1147     */

    1148    EPwm3Regs.DCTRIPSEL.all = (EPwm3Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;

    1149

    1150    /*	// Trip Zone Digital Comparator Select Register

    1151       EPwm3Regs.TZDCSEL.bit.DCAEVT1            = 0;          // Digital Compare Output A Event 1

    1152       EPwm3Regs.TZDCSEL.bit.DCAEVT2            = 0;          // Digital Compare Output A Event 2

    1153       EPwm3Regs.TZDCSEL.bit.DCBEVT1            = 0;          // Digital Compare Output B Event 1

    1154       EPwm3Regs.TZDCSEL.bit.DCBEVT2            = 0;          // Digital Compare Output B Event 2

    1155     */

    1156    EPwm3Regs.TZDCSEL.all = (EPwm3Regs.TZDCSEL.all & ~0xFFF) | 0x0;

    1157

    1158    /*	// Digital Compare Filter Control Register

    1159       EPwm3Regs.DCFCTL.bit.BLANKE              = 0;          // Blanking Enable/Disable

    1160       EPwm3Regs.DCFCTL.bit.PULSESEL            = 1;          // Pulse Select for Blanking & Capture Alignment

    1161       EPwm3Regs.DCFCTL.bit.BLANKINV            = 0;          // Blanking Window Inversion

    1162       EPwm3Regs.DCFCTL.bit.SRCSEL              = 0;          // Filter Block Signal Source Select

    1163     */

    1164    EPwm3Regs.DCFCTL.all = (EPwm3Regs.DCFCTL.all & ~0x3F) | 0x10;

    1165    EPwm3Regs.DCFOFFSET = 0;           // Digital Compare Filter Offset Register

    1166    EPwm3Regs.DCFWINDOW = 0;           // Digital Compare Filter Window Register

    1167

    1168    /*	// Digital Compare Capture Control Register

    1169       EPwm3Regs.DCCAPCTL.bit.CAPE              = 0;          // Counter Capture Enable

    1170     */

    1171    EPwm3Regs.DCCAPCTL.all = (EPwm3Regs.DCCAPCTL.all & ~0x1) | 0x0;

    1172

    1173    /*	// HRPWM Configuration Register

    1174       EPwm3Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit

    1175       EPwm3Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit

    1176     */

    1177    EPwm3Regs.HRCNFG.all = (EPwm3Regs.HRCNFG.all & ~0xA0) | 0x0;

    1178

    1179    /* Update the Link Registers with the link value for all the Compare values and TBPRD */

    1180    /* No error is thrown if the ePWM register exists in the model or not */

    1181    EPwm3Regs.EPWMXLINK.bit.TBPRDLINK = 2;

    1182    EPwm3Regs.EPWMXLINK.bit.CMPALINK = 2;

    1183    EPwm3Regs.EPWMXLINK.bit.CMPBLINK = 2;

    1184    EPwm3Regs.EPWMXLINK.bit.CMPCLINK = 2;

    1185    EPwm3Regs.EPWMXLINK.bit.CMPDLINK = 2;

    1186    EDIS;

    1187    EALLOW;

    1188    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

    1189    EDIS;

    1190  }

    1191

    1192  /* Start for S-Function (c2802xpwm): '<S1>/ePWM2' incorporates:

    1193   *  Constant: '<Root>/Constant2'

    1194   */

    1195  EALLOW;

    1196  CpuSysRegs.PCLKCR2.bit.EPWM6 = 1;

    1197  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

    1198  EDIS;

    1199

    1200  /*** Initialize ePWM6 modules ***/

    1201  {

    1202    /*  // Time Base Control Register

    1203       EPwm6Regs.TBCTL.bit.CTRMODE              = 2;          // Counter Mode

    1204       EPwm6Regs.TBCTL.bit.SYNCOSEL             = 3;          // Sync Output Select

    1205       EPwm6Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select

    1206       EPwm6Regs.TBCTL.bit.PHSEN                = 0;          // Phase Load Enable

    1207       EPwm6Regs.TBCTL.bit.PHSDIR               = 0;          // Phase Direction Bit

    1208       EPwm6Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler

    1209       EPwm6Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler

    1210       EPwm6Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse

    1211     */

    1212    EPwm6Regs.TBCTL.all = (EPwm6Regs.TBCTL.all & ~0x3FFF) | 0x32;

    1213

    1214    /*-- Setup Time-Base (TB) Submodule --*/

    1215    EPwm6Regs.TBPRD = 12500;           // Time Base Period Register

    1216

    1217    /* // Time-Base Phase Register

    1218       EPwm6Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register

    1219     */

    1220    EPwm6Regs.TBPHS.all = (EPwm6Regs.TBPHS.all & ~0xFFFF0000) | 0x0;

    1221

    1222    // Time Base Counter Register

    1223    EPwm6Regs.TBCTR = 0x0000;          /* Clear counter*/

    1224

    1225    /*-- Setup Counter_Compare (CC) Submodule --*/

    1226    /*	// Counter Compare Control Register

    1227       EPwm6Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode

    1228       EPwm6Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode

    1229       EPwm6Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load

    1230       EPwm6Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load

    1231     */

    1232    EPwm6Regs.CMPCTL.all = (EPwm6Regs.CMPCTL.all & ~0x5F) | 0x0;

    1233

    1234    /* EPwm6Regs.CMPCTL2.bit.SHDWCMODE           = 0;  // Compare C Register Block Operating Mode

    1235

    1236       EPwm6Regs.CMPCTL2.bit.SHDWDMODE           = 0;  // Compare D Register Block Operating Mode

    1237     */

    1238    EPwm6Regs.CMPCTL2.all = (EPwm6Regs.CMPCTL2.all & ~0x50) | 0x0;

    1239    EPwm6Regs.CMPA.bit.CMPA = 3750;    // Counter Compare A Register

    1240    EPwm6Regs.CMPB.bit.CMPB = 3750;    // Counter Compare B Register

    1241    EPwm6Regs.CMPC = 32000;            // Counter Compare C Register

    1242    EPwm6Regs.CMPD = 32000;            // Counter Compare D Register

    1243

    1244    /*-- Setup Action-Qualifier (AQ) Submodule --*/

    1245    EPwm6Regs.AQCTLA.all = 150;        // Action Qualifier Control Register For Output A

    1246    EPwm6Regs.AQCTLB.all = 1545;       // Action Qualifier Control Register For Output B

    1247

    1248    /*	// Action Qualifier Software Force Register

    1249       EPwm6Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options

    1250     */

    1251    EPwm6Regs.AQSFRC.all = (EPwm6Regs.AQSFRC.all & ~0xC0) | 0x0;

    1252

    1253    /*	// Action Qualifier Continuous S/W Force Register

    1254       EPwm6Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A

    1255       EPwm6Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B

    1256     */

    1257    EPwm6Regs.AQCSFRC.all = (EPwm6Regs.AQCSFRC.all & ~0xF) | 0x0;

    1258

    1259    /*-- Setup Dead-Band Generator (DB) Submodule --*/

    1260    /*	// Dead-Band Generator Control Register

    1261       EPwm6Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control

    1262       EPwm6Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control

    1263       EPwm6Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control

    1264       EPwm6Regs.DBCTL.bit.HALFCYCLE            = 0;          // Half Cycle Clocking Enable

    1265     */

    1266    EPwm6Regs.DBCTL.all = (EPwm6Regs.DBCTL.all & ~0x803F) | 0xB;

    1267    EPwm6Regs.DBRED.bit.DBRED = 0;     // Dead-Band Generator Rising Edge Delay Count Register

    1268    EPwm6Regs.DBFED.bit.DBFED = 0;     // Dead-Band Generator Falling Edge Delay Count Register

    1269

    1270    /*-- Setup Event-Trigger (ET) Submodule --*/

    1271    /*	// Event Trigger Selection and Pre-Scale Register

    1272       EPwm6Regs.ETSEL.bit.SOCAEN               = 0;          // Start of Conversion A Enable

    1273       EPwm6Regs.ETSEL.bit.SOCASELCMP = 0;

    1274       EPwm6Regs.ETSEL.bit.SOCASEL              = 0 ;          // Start of Conversion A Select

    1275       EPwm6Regs.ETPS.bit.SOCAPRD               = 1;          // EPWM6SOCA Period Select

    1276

    1277       EPwm6Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable

    1278

    1279       EPwm6Regs.ETSEL.bit.SOCBSELCMP = 0;

    1280       EPwm6Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select

    1281       EPwm6Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM6SOCB Period Select

    1282       EPwm6Regs.ETSEL.bit.INTEN                = 0;          // EPWM6INTn Enable

    1283       EPwm6Regs.ETSEL.bit.INTSELCMP = 0;

    1284       EPwm6Regs.ETSEL.bit.INTSEL              = 1;          // Start of Conversion A Select

    1285

    1286       EPwm6Regs.ETPS.bit.INTPRD                = 1;          // EPWM6INTn Period Select

    1287     */

    1288    EPwm6Regs.ETSEL.all = (EPwm6Regs.ETSEL.all & ~0xFF7F) | 0x1001;

    1289    EPwm6Regs.ETPS.all = (EPwm6Regs.ETPS.all & ~0x3303) | 0x1101;

    1290

    1291    /*-- Setup PWM-Chopper (PC) Submodule --*/

    1292    /*	// PWM Chopper Control Register

    1293       EPwm6Regs.PCCTL.bit.CHPEN                = 0;          // PWM chopping enable

    1294       EPwm6Regs.PCCTL.bit.CHPFREQ              = 0;          // Chopping clock frequency

    1295       EPwm6Regs.PCCTL.bit.OSHTWTH              = 0;          // One-shot pulse width

    1296       EPwm6Regs.PCCTL.bit.CHPDUTY              = 0;          // Chopping clock Duty cycle

    1297     */

    1298    EPwm6Regs.PCCTL.all = (EPwm6Regs.PCCTL.all & ~0x7FF) | 0x0;

    1299

    1300    /*-- Set up Trip-Zone (TZ) Submodule --*/

    1301    EALLOW;

    1302    EPwm6Regs.TZSEL.all = 0;           // Trip Zone Select Register

    1303

    1304    /*	// Trip Zone Control Register

    1305       EPwm6Regs.TZCTL.bit.TZA                  = 3;          // TZ1 to TZ6 Trip Action On EPWM6A

    1306       EPwm6Regs.TZCTL.bit.TZB                  = 3;          // TZ1 to TZ6 Trip Action On EPWM6B

    1307       EPwm6Regs.TZCTL.bit.DCAEVT1              = 3;          // EPWM6A action on DCAEVT1

    1308       EPwm6Regs.TZCTL.bit.DCAEVT2              = 3;          // EPWM6A action on DCAEVT2

    1309       EPwm6Regs.TZCTL.bit.DCBEVT1              = 3;          // EPWM6B action on DCBEVT1

    1310       EPwm6Regs.TZCTL.bit.DCBEVT2              = 3;          // EPWM6B action on DCBEVT2

    1311     */

    1312    EPwm6Regs.TZCTL.all = (EPwm6Regs.TZCTL.all & ~0xFFF) | 0xFFF;

    1313

    1314    /*	// Trip Zone Enable Interrupt Register

    1315       EPwm6Regs.TZEINT.bit.OST                 = 0;          // Trip Zones One Shot Int Enable

    1316       EPwm6Regs.TZEINT.bit.CBC                 = 0;          // Trip Zones Cycle By Cycle Int Enable

    1317       EPwm6Regs.TZEINT.bit.DCAEVT1             = 0;          // Digital Compare A Event 1 Int Enable

    1318       EPwm6Regs.TZEINT.bit.DCAEVT2             = 0;          // Digital Compare A Event 2 Int Enable

    1319       EPwm6Regs.TZEINT.bit.DCBEVT1             = 0;          // Digital Compare B Event 1 Int Enable

    1320       EPwm6Regs.TZEINT.bit.DCBEVT2             = 0;          // Digital Compare B Event 2 Int Enable

    1321     */

    1322    EPwm6Regs.TZEINT.all = (EPwm6Regs.TZEINT.all & ~0x7E) | 0x0;

    1323

    1324    /*	// Digital Compare A Control Register

    1325       EPwm6Regs.DCACTL.bit.EVT1SYNCE           = 0;          // DCAEVT1 SYNC Enable

    1326       EPwm6Regs.DCACTL.bit.EVT1SOCE            = 1;          // DCAEVT1 SOC Enable

    1327       EPwm6Regs.DCACTL.bit.EVT1FRCSYNCSEL      = 0;          // DCAEVT1 Force Sync Signal

    1328       EPwm6Regs.DCACTL.bit.EVT1SRCSEL          = 0;          // DCAEVT1 Source Signal

    1329       EPwm6Regs.DCACTL.bit.EVT2FRCSYNCSEL      = 0;          // DCAEVT2 Force Sync Signal

    1330       EPwm6Regs.DCACTL.bit.EVT2SRCSEL          = 0;          // DCAEVT2 Source Signal

    1331     */

    1332    EPwm6Regs.DCACTL.all = (EPwm6Regs.DCACTL.all & ~0x30F) | 0x4;

    1333

    1334    /*	// Digital Compare B Control Register

    1335       EPwm6Regs.DCBCTL.bit.EVT1SYNCE           = 0;          // DCBEVT1 SYNC Enable

    1336       EPwm6Regs.DCBCTL.bit.EVT1SOCE            = 0;          // DCBEVT1 SOC Enable

    1337       EPwm6Regs.DCBCTL.bit.EVT1FRCSYNCSEL      = 0;          // DCBEVT1 Force Sync Signal

    1338       EPwm6Regs.DCBCTL.bit.EVT1SRCSEL          = 0;          // DCBEVT1 Source Signal

    1339       EPwm6Regs.DCBCTL.bit.EVT2FRCSYNCSEL      = 0;          // DCBEVT2 Force Sync Signal

    1340       EPwm6Regs.DCBCTL.bit.EVT2SRCSEL          = 0;          // DCBEVT2 Source Signal

    1341     */

    1342    EPwm6Regs.DCBCTL.all = (EPwm6Regs.DCBCTL.all & ~0x30F) | 0x0;

    1343

    1344    /*	// Digital Compare Trip Select Register

    1345       EPwm6Regs.DCTRIPSEL.bit.DCAHCOMPSEL      = 0;          // Digital Compare A High COMP Input Select

    1346

    1347       EPwm6Regs.DCTRIPSEL.bit.DCALCOMPSEL      = 1;          // Digital Compare A Low COMP Input Select

    1348       EPwm6Regs.DCTRIPSEL.bit.DCBHCOMPSEL      = 0;          // Digital Compare B High COMP Input Select

    1349       EPwm6Regs.DCTRIPSEL.bit.DCBLCOMPSEL      = 1;          // Digital Compare B Low COMP Input Select

    1350

    1351

    1352

    1353

    1354

    1355     */

    1356    EPwm6Regs.DCTRIPSEL.all = (EPwm6Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;

    1357

    1358    /*	// Trip Zone Digital Comparator Select Register

    1359       EPwm6Regs.TZDCSEL.bit.DCAEVT1            = 0;          // Digital Compare Output A Event 1

    1360       EPwm6Regs.TZDCSEL.bit.DCAEVT2            = 0;          // Digital Compare Output A Event 2

    1361       EPwm6Regs.TZDCSEL.bit.DCBEVT1            = 0;          // Digital Compare Output B Event 1

    1362       EPwm6Regs.TZDCSEL.bit.DCBEVT2            = 0;          // Digital Compare Output B Event 2

    1363     */

    1364    EPwm6Regs.TZDCSEL.all = (EPwm6Regs.TZDCSEL.all & ~0xFFF) | 0x0;

    1365

    1366    /*	// Digital Compare Filter Control Register

    1367       EPwm6Regs.DCFCTL.bit.BLANKE              = 0;          // Blanking Enable/Disable

    1368       EPwm6Regs.DCFCTL.bit.PULSESEL            = 1;          // Pulse Select for Blanking & Capture Alignment

    1369       EPwm6Regs.DCFCTL.bit.BLANKINV            = 0;          // Blanking Window Inversion

    1370       EPwm6Regs.DCFCTL.bit.SRCSEL              = 0;          // Filter Block Signal Source Select

    1371     */

    1372    EPwm6Regs.DCFCTL.all = (EPwm6Regs.DCFCTL.all & ~0x3F) | 0x10;

    1373    EPwm6Regs.DCFOFFSET = 0;           // Digital Compare Filter Offset Register

    1374    EPwm6Regs.DCFWINDOW = 0;           // Digital Compare Filter Window Register

    1375

    1376    /*	// Digital Compare Capture Control Register

    1377       EPwm6Regs.DCCAPCTL.bit.CAPE              = 0;          // Counter Capture Enable

    1378     */

    1379    EPwm6Regs.DCCAPCTL.all = (EPwm6Regs.DCCAPCTL.all & ~0x1) | 0x0;

    1380

    1381    /*	// HRPWM Configuration Register

    1382       EPwm6Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit

    1383       EPwm6Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit

    1384     */

    1385    EPwm6Regs.HRCNFG.all = (EPwm6Regs.HRCNFG.all & ~0xA0) | 0x0;

    1386

    1387    /* Update the Link Registers with the link value for all the Compare values and TBPRD */

    1388    /* No error is thrown if the ePWM register exists in the model or not */

    1389    EPwm6Regs.EPWMXLINK.bit.TBPRDLINK = 5;

    1390    EPwm6Regs.EPWMXLINK.bit.CMPALINK = 5;

    1391    EPwm6Regs.EPWMXLINK.bit.CMPBLINK = 5;

    1392    EPwm6Regs.EPWMXLINK.bit.CMPCLINK = 5;

    1393    EPwm6Regs.EPWMXLINK.bit.CMPDLINK = 5;

    1394    EDIS;

    1395    EALLOW;

    1396    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

    1397    EDIS;

    1398  }

    1399

    1400  /* Start for S-Function (c2802xpwm): '<S1>/ePWM3' incorporates:

    1401   *  Constant: '<Root>/Constant2'

    1402   */

    1403  EALLOW;

    1404  CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;

    1405  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

    1406  EDIS;

    1407

    1408  /*** Initialize ePWM4 modules ***/

    1409  {

    1410    /*  // Time Base Control Register

    1411       EPwm4Regs.TBCTL.bit.CTRMODE              = 2;          // Counter Mode

    1412       EPwm4Regs.TBCTL.bit.SYNCOSEL             = 3;          // Sync Output Select

    1413       EPwm4Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select

    1414       EPwm4Regs.TBCTL.bit.PHSEN                = 0;          // Phase Load Enable

    1415       EPwm4Regs.TBCTL.bit.PHSDIR               = 0;          // Phase Direction Bit

    1416       EPwm4Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler

    1417       EPwm4Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler

    1418       EPwm4Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse

    1419     */

    1420    EPwm4Regs.TBCTL.all = (EPwm4Regs.TBCTL.all & ~0x3FFF) | 0x32;

    1421

    1422    /*-- Setup Time-Base (TB) Submodule --*/

    1423    EPwm4Regs.TBPRD = 12500;           // Time Base Period Register

    1424

    1425    /* // Time-Base Phase Register

    1426       EPwm4Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register

    1427     */

    1428    EPwm4Regs.TBPHS.all = (EPwm4Regs.TBPHS.all & ~0xFFFF0000) | 0x0;

    1429

    1430    // Time Base Counter Register

    1431    EPwm4Regs.TBCTR = 0x0000;          /* Clear counter*/

    1432

    1433    /*-- Setup Counter_Compare (CC) Submodule --*/

    1434    /*	// Counter Compare Control Register

    1435       EPwm4Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode

    1436       EPwm4Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode

    1437       EPwm4Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load

    1438       EPwm4Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load

    1439     */

    1440    EPwm4Regs.CMPCTL.all = (EPwm4Regs.CMPCTL.all & ~0x5F) | 0x0;

    1441

    1442    /* EPwm4Regs.CMPCTL2.bit.SHDWCMODE           = 0;  // Compare C Register Block Operating Mode

    1443

    1444       EPwm4Regs.CMPCTL2.bit.SHDWDMODE           = 0;  // Compare D Register Block Operating Mode

    1445     */

    1446    EPwm4Regs.CMPCTL2.all = (EPwm4Regs.CMPCTL2.all & ~0x50) | 0x0;

    1447    EPwm4Regs.CMPA.bit.CMPA = 3750;    // Counter Compare A Register

    1448    EPwm4Regs.CMPB.bit.CMPB = 3750;    // Counter Compare B Register

    1449    EPwm4Regs.CMPC = 32000;            // Counter Compare C Register

    1450    EPwm4Regs.CMPD = 32000;            // Counter Compare D Register

    1451

    1452    /*-- Setup Action-Qualifier (AQ) Submodule --*/

    1453    EPwm4Regs.AQCTLA.all = 150;        // Action Qualifier Control Register For Output A

    1454    EPwm4Regs.AQCTLB.all = 1545;       // Action Qualifier Control Register For Output B

    1455

    1456    /*	// Action Qualifier Software Force Register

    1457       EPwm4Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options

    1458     */

    1459    EPwm4Regs.AQSFRC.all = (EPwm4Regs.AQSFRC.all & ~0xC0) | 0x0;

    1460

    1461    /*	// Action Qualifier Continuous S/W Force Register

    1462       EPwm4Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A

    1463       EPwm4Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B

    1464     */

    1465    EPwm4Regs.AQCSFRC.all = (EPwm4Regs.AQCSFRC.all & ~0xF) | 0x0;

    1466

    1467    /*-- Setup Dead-Band Generator (DB) Submodule --*/

    1468    /*	// Dead-Band Generator Control Register

    1469       EPwm4Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control

    1470       EPwm4Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control

    1471       EPwm4Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control

    1472       EPwm4Regs.DBCTL.bit.HALFCYCLE            = 0;          // Half Cycle Clocking Enable

    1473     */

    1474    EPwm4Regs.DBCTL.all = (EPwm4Regs.DBCTL.all & ~0x803F) | 0xB;

    1475    EPwm4Regs.DBRED.bit.DBRED = 0;     // Dead-Band Generator Rising Edge Delay Count Register

    1476    EPwm4Regs.DBFED.bit.DBFED = 0;     // Dead-Band Generator Falling Edge Delay Count Register

    1477

    1478    /*-- Setup Event-Trigger (ET) Submodule --*/

    1479    /*	// Event Trigger Selection and Pre-Scale Register

    1480       EPwm4Regs.ETSEL.bit.SOCAEN               = 0;          // Start of Conversion A Enable

    1481       EPwm4Regs.ETSEL.bit.SOCASELCMP = 0;

    1482       EPwm4Regs.ETSEL.bit.SOCASEL              = 0 ;          // Start of Conversion A Select

    1483       EPwm4Regs.ETPS.bit.SOCAPRD               = 1;          // EPWM4SOCA Period Select

    1484

    1485       EPwm4Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable

    1486

    1487       EPwm4Regs.ETSEL.bit.SOCBSELCMP = 0;

    1488       EPwm4Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select

    1489       EPwm4Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM4SOCB Period Select

    1490       EPwm4Regs.ETSEL.bit.INTEN                = 0;          // EPWM4INTn Enable

    1491       EPwm4Regs.ETSEL.bit.INTSELCMP = 0;

    1492       EPwm4Regs.ETSEL.bit.INTSEL              = 1;          // Start of Conversion A Select

    1493

    1494       EPwm4Regs.ETPS.bit.INTPRD                = 1;          // EPWM4INTn Period Select

    1495     */

    1496    EPwm4Regs.ETSEL.all = (EPwm4Regs.ETSEL.all & ~0xFF7F) | 0x1001;

    1497    EPwm4Regs.ETPS.all = (EPwm4Regs.ETPS.all & ~0x3303) | 0x1101;

    1498

    1499    /*-- Setup PWM-Chopper (PC) Submodule --*/

    1500    /*	// PWM Chopper Control Register

    1501       EPwm4Regs.PCCTL.bit.CHPEN                = 0;          // PWM chopping enable

    1502       EPwm4Regs.PCCTL.bit.CHPFREQ              = 0;          // Chopping clock frequency

    1503       EPwm4Regs.PCCTL.bit.OSHTWTH              = 0;          // One-shot pulse width

    1504       EPwm4Regs.PCCTL.bit.CHPDUTY              = 0;          // Chopping clock Duty cycle

    1505     */

    1506    EPwm4Regs.PCCTL.all = (EPwm4Regs.PCCTL.all & ~0x7FF) | 0x0;

    1507

    1508    /*-- Set up Trip-Zone (TZ) Submodule --*/

    1509    EALLOW;

    1510    EPwm4Regs.TZSEL.all = 0;           // Trip Zone Select Register

    1511

    1512    /*	// Trip Zone Control Register

    1513       EPwm4Regs.TZCTL.bit.TZA                  = 3;          // TZ1 to TZ6 Trip Action On EPWM4A

    1514       EPwm4Regs.TZCTL.bit.TZB                  = 3;          // TZ1 to TZ6 Trip Action On EPWM4B

    1515       EPwm4Regs.TZCTL.bit.DCAEVT1              = 3;          // EPWM4A action on DCAEVT1

    1516       EPwm4Regs.TZCTL.bit.DCAEVT2              = 3;          // EPWM4A action on DCAEVT2

    1517       EPwm4Regs.TZCTL.bit.DCBEVT1              = 3;          // EPWM4B action on DCBEVT1

    1518       EPwm4Regs.TZCTL.bit.DCBEVT2              = 3;          // EPWM4B action on DCBEVT2

    1519     */

    1520    EPwm4Regs.TZCTL.all = (EPwm4Regs.TZCTL.all & ~0xFFF) | 0xFFF;

    1521

    1522    /*	// Trip Zone Enable Interrupt Register

    1523       EPwm4Regs.TZEINT.bit.OST                 = 0;          // Trip Zones One Shot Int Enable

    1524       EPwm4Regs.TZEINT.bit.CBC                 = 0;          // Trip Zones Cycle By Cycle Int Enable

    1525       EPwm4Regs.TZEINT.bit.DCAEVT1             = 0;          // Digital Compare A Event 1 Int Enable

    1526       EPwm4Regs.TZEINT.bit.DCAEVT2             = 0;          // Digital Compare A Event 2 Int Enable

    1527       EPwm4Regs.TZEINT.bit.DCBEVT1             = 0;          // Digital Compare B Event 1 Int Enable

    1528       EPwm4Regs.TZEINT.bit.DCBEVT2             = 0;          // Digital Compare B Event 2 Int Enable

    1529     */

    1530    EPwm4Regs.TZEINT.all = (EPwm4Regs.TZEINT.all & ~0x7E) | 0x0;

    1531

    1532    /*	// Digital Compare A Control Register

    1533       EPwm4Regs.DCACTL.bit.EVT1SYNCE           = 0;          // DCAEVT1 SYNC Enable

    1534       EPwm4Regs.DCACTL.bit.EVT1SOCE            = 1;          // DCAEVT1 SOC Enable

    1535       EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL      = 0;          // DCAEVT1 Force Sync Signal

    1536       EPwm4Regs.DCACTL.bit.EVT1SRCSEL          = 0;          // DCAEVT1 Source Signal

    1537       EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL      = 0;          // DCAEVT2 Force Sync Signal

    1538       EPwm4Regs.DCACTL.bit.EVT2SRCSEL          = 0;          // DCAEVT2 Source Signal

    1539     */

    1540    EPwm4Regs.DCACTL.all = (EPwm4Regs.DCACTL.all & ~0x30F) | 0x4;

    1541

    1542    /*	// Digital Compare B Control Register

    1543       EPwm4Regs.DCBCTL.bit.EVT1SYNCE           = 0;          // DCBEVT1 SYNC Enable

    1544       EPwm4Regs.DCBCTL.bit.EVT1SOCE            = 0;          // DCBEVT1 SOC Enable

    1545       EPwm4Regs.DCBCTL.bit.EVT1FRCSYNCSEL      = 0;          // DCBEVT1 Force Sync Signal

    1546       EPwm4Regs.DCBCTL.bit.EVT1SRCSEL          = 0;          // DCBEVT1 Source Signal

    1547       EPwm4Regs.DCBCTL.bit.EVT2FRCSYNCSEL      = 0;          // DCBEVT2 Force Sync Signal

    1548       EPwm4Regs.DCBCTL.bit.EVT2SRCSEL          = 0;          // DCBEVT2 Source Signal

    1549     */

    1550    EPwm4Regs.DCBCTL.all = (EPwm4Regs.DCBCTL.all & ~0x30F) | 0x0;

    1551

    1552    /*	// Digital Compare Trip Select Register

    1553       EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL      = 0;          // Digital Compare A High COMP Input Select

    1554

    1555       EPwm4Regs.DCTRIPSEL.bit.DCALCOMPSEL      = 1;          // Digital Compare A Low COMP Input Select

    1556       EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL      = 0;          // Digital Compare B High COMP Input Select

    1557       EPwm4Regs.DCTRIPSEL.bit.DCBLCOMPSEL      = 1;          // Digital Compare B Low COMP Input Select

    1558

    1559

    1560

    1561

    1562

    1563     */

    1564    EPwm4Regs.DCTRIPSEL.all = (EPwm4Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;

    1565

    1566    /*	// Trip Zone Digital Comparator Select Register

    1567       EPwm4Regs.TZDCSEL.bit.DCAEVT1            = 0;          // Digital Compare Output A Event 1

    1568       EPwm4Regs.TZDCSEL.bit.DCAEVT2            = 0;          // Digital Compare Output A Event 2

    1569       EPwm4Regs.TZDCSEL.bit.DCBEVT1            = 0;          // Digital Compare Output B Event 1

    1570       EPwm4Regs.TZDCSEL.bit.DCBEVT2            = 0;          // Digital Compare Output B Event 2

    1571     */

    1572    EPwm4Regs.TZDCSEL.all = (EPwm4Regs.TZDCSEL.all & ~0xFFF) | 0x0;

    1573

    1574    /*	// Digital Compare Filter Control Register

    1575       EPwm4Regs.DCFCTL.bit.BLANKE              = 0;          // Blanking Enable/Disable

    1576       EPwm4Regs.DCFCTL.bit.PULSESEL            = 1;          // Pulse Select for Blanking & Capture Alignment

    1577       EPwm4Regs.DCFCTL.bit.BLANKINV            = 0;          // Blanking Window Inversion

    1578       EPwm4Regs.DCFCTL.bit.SRCSEL              = 0;          // Filter Block Signal Source Select

    1579     */

    1580    EPwm4Regs.DCFCTL.all = (EPwm4Regs.DCFCTL.all & ~0x3F) | 0x10;

    1581    EPwm4Regs.DCFOFFSET = 0;           // Digital Compare Filter Offset Register

    1582    EPwm4Regs.DCFWINDOW = 0;           // Digital Compare Filter Window Register

    1583

    1584    /*	// Digital Compare Capture Control Register

    1585       EPwm4Regs.DCCAPCTL.bit.CAPE              = 0;          // Counter Capture Enable

    1586     */

    1587    EPwm4Regs.DCCAPCTL.all = (EPwm4Regs.DCCAPCTL.all & ~0x1) | 0x0;

    1588

    1589    /*	// HRPWM Configuration Register

    1590       EPwm4Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit

    1591       EPwm4Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit

    1592     */

    1593    EPwm4Regs.HRCNFG.all = (EPwm4Regs.HRCNFG.all & ~0xA0) | 0x0;

    1594

    1595    /* Update the Link Registers with the link value for all the Compare values and TBPRD */

    1596    /* No error is thrown if the ePWM register exists in the model or not */

    1597    EPwm4Regs.EPWMXLINK.bit.TBPRDLINK = 3;

    1598    EPwm4Regs.EPWMXLINK.bit.CMPALINK = 3;

    1599    EPwm4Regs.EPWMXLINK.bit.CMPBLINK = 3;

    1600    EPwm4Regs.EPWMXLINK.bit.CMPCLINK = 3;

    1601    EPwm4Regs.EPWMXLINK.bit.CMPDLINK = 3;

    1602    EDIS;

    1603    EALLOW;

    1604    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

    1605    EDIS;

    1606  }

    1607

    1608  /* Start for MATLABSystem: '<Root>/DAC1' */

    1609  MW_ConfigureDACB();

    1610

    1611  /* Start for MATLABSystem: '<Root>/DAC2' */

    1612  MW_ConfigureDACC();

    1613

    1614  /* InitializeConditions for RateTransition: '<Root>/Rate Transition1' */

    1615  Inverter_000_test_DW.RateTransition1_Buffer0 =

    1616    Inverter_000_test_P.RateTransition1_InitialConditio;

    1617

    1618  /* InitializeConditions for UnitDelay: '<S12>/Unit Delay' */

    1619  Inverter_000_test_DW.UnitDelay_DSTATE =

    1620    Inverter_000_test_P.UnitDelay_InitialCondition;

    1621}

    1622

    1623/* Model terminate function */

    1624void Inverter_000_test_terminate(void)

    1625{

    1626  /* (no terminate code required) */

    1627}

    1628

    1629/*

    1630 * File trailer for generated code.

    1631 *

    1632 * [EOF]

    1633 */

    1634