| 1 | #include "F2837xD_device.h" |
| 2 | #include "F2837xD_Examples.h" |
| 3 | #include "F2837xD_GlobalPrototypes.h" |
| 4 | #include "rtwtypes.h" |
| 5 | #include "Inverter_001.h" |
| 6 | #include "Inverter_001_private.h" |
| 7 | |
| 8 | void config_ADCC_SOC11() |
| 9 | { |
| 10 | EALLOW; |
| 11 | AdccRegs.ADCSOC11CTL.bit.CHSEL = 3; /* Set SOC11 channel select to ADCIN3*/ |
| 12 | AdccRegs.ADCSOC11CTL.bit.TRIGSEL = 0; |
| 13 | AdccRegs.ADCSOC11CTL.bit.ACQPS = 14; /* Set SOC11 S/H Window to 15 ADC Clock Cycles*/ |
| 14 | AdccRegs.ADCINTSOCSEL2.bit.SOC11 = 1;/* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 15 | AdccRegs.ADCOFFTRIM.bit.OFFTRIM = AdccRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 16 | AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 17 | AdccRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 18 | EDIS; |
| 19 | } |
| 20 | |
| 21 | void config_ADCC_SOC12() |
| 22 | { |
| 23 | EALLOW; |
| 24 | AdccRegs.ADCSOC12CTL.bit.CHSEL = 4; /* Set SOC12 channel select to ADCIN4*/ |
| 25 | AdccRegs.ADCSOC12CTL.bit.TRIGSEL = 0; |
| 26 | AdccRegs.ADCSOC12CTL.bit.ACQPS = 14; /* Set SOC12 S/H Window to 15 ADC Clock Cycles*/ |
| 27 | AdccRegs.ADCINTSOCSEL2.bit.SOC12 = 1;/* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 28 | AdccRegs.ADCOFFTRIM.bit.OFFTRIM = AdccRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 29 | AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 30 | AdccRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 31 | EDIS; |
| 32 | } |
| 33 | |
| 34 | void config_ADCD_SOC2() |
| 35 | { |
| 36 | EALLOW; |
| 37 | AdcdRegs.ADCSOC2CTL.bit.CHSEL = 2; /* Set SOC2 channel select to ADCIN2*/ |
| 38 | AdcdRegs.ADCSOC2CTL.bit.TRIGSEL = 0; |
| 39 | AdcdRegs.ADCSOC2CTL.bit.ACQPS = 14; /* Set SOC2 S/H Window to 15 ADC Clock Cycles*/ |
| 40 | AdcdRegs.ADCINTSOCSEL1.bit.SOC2 = 1; /* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 41 | AdcdRegs.ADCOFFTRIM.bit.OFFTRIM = AdcdRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 42 | AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 43 | AdcdRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 44 | EDIS; |
| 45 | } |
| 46 | |
| 47 | void config_ADCD_SOC5() |
| 48 | { |
| 49 | EALLOW; |
| 50 | AdcdRegs.ADCSOC5CTL.bit.CHSEL = 3; /* Set SOC5 channel select to ADCIN3*/ |
| 51 | AdcdRegs.ADCSOC5CTL.bit.TRIGSEL = 0; |
| 52 | AdcdRegs.ADCSOC5CTL.bit.ACQPS = 14; /* Set SOC5 S/H Window to 15 ADC Clock Cycles*/ |
| 53 | AdcdRegs.ADCINTSOCSEL1.bit.SOC5 = 1; /* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 54 | AdcdRegs.ADCOFFTRIM.bit.OFFTRIM = AdcdRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 55 | AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 56 | AdcdRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 57 | EDIS; |
| 58 | } |
| 59 | |
| 60 | void config_ADCD_SOC7() |
| 61 | { |
| 62 | EALLOW; |
| 63 | AdcdRegs.ADCSOC7CTL.bit.CHSEL = 4; /* Set SOC7 channel select to ADCIN4*/ |
| 64 | AdcdRegs.ADCSOC7CTL.bit.TRIGSEL = 0; |
| 65 | AdcdRegs.ADCSOC7CTL.bit.ACQPS = 14; /* Set SOC7 S/H Window to 15 ADC Clock Cycles*/ |
| 66 | AdcdRegs.ADCINTSOCSEL1.bit.SOC7 = 1; /* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 67 | AdcdRegs.ADCOFFTRIM.bit.OFFTRIM = AdcdRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 68 | AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 69 | AdcdRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 70 | EDIS; |
| 71 | } |
| 72 | |
| 73 | void config_ADCA_SOC4() |
| 74 | { |
| 75 | EALLOW; |
| 76 | AdcaRegs.ADCSOC4CTL.bit.CHSEL = 2; /* Set SOC4 channel select to ADCIN2*/ |
| 77 | AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = 0; |
| 78 | AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; /* Set SOC4 S/H Window to 15 ADC Clock Cycles*/ |
| 79 | AdcaRegs.ADCINTSOCSEL1.bit.SOC4 = 1; /* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 80 | AdcaRegs.ADCOFFTRIM.bit.OFFTRIM = AdcaRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 81 | AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 82 | AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 83 | EDIS; |
| 84 | } |
| 85 | |
| 86 | void config_ADCA_SOC6() |
| 87 | { |
| 88 | EALLOW; |
| 89 | AdcaRegs.ADCSOC6CTL.bit.CHSEL = 3; /* Set SOC6 channel select to ADCIN3*/ |
| 90 | AdcaRegs.ADCSOC6CTL.bit.TRIGSEL = 0; |
| 91 | AdcaRegs.ADCSOC6CTL.bit.ACQPS = 14; /* Set SOC6 S/H Window to 15 ADC Clock Cycles*/ |
| 92 | AdcaRegs.ADCINTSOCSEL1.bit.SOC6 = 1; /* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 93 | AdcaRegs.ADCOFFTRIM.bit.OFFTRIM = AdcaRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 94 | AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 95 | AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 96 | EDIS; |
| 97 | } |
| 98 | |
| 99 | void config_ADCA_SOC8() |
| 100 | { |
| 101 | EALLOW; |
| 102 | AdcaRegs.ADCSOC8CTL.bit.CHSEL = 4; /* Set SOC8 channel select to ADCIN4*/ |
| 103 | AdcaRegs.ADCSOC8CTL.bit.TRIGSEL = 0; |
| 104 | AdcaRegs.ADCSOC8CTL.bit.ACQPS = 14; /* Set SOC8 S/H Window to 15 ADC Clock Cycles*/ |
| 105 | AdcaRegs.ADCINTSOCSEL2.bit.SOC8 = 1; /* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 106 | AdcaRegs.ADCOFFTRIM.bit.OFFTRIM = AdcaRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 107 | AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 108 | AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 109 | EDIS; |
| 110 | } |
| 111 | |
| 112 | void config_ADCC_SOC10() |
| 113 | { |
| 114 | EALLOW; |
| 115 | AdccRegs.ADCSOC10CTL.bit.CHSEL = 2; /* Set SOC10 channel select to ADCIN2*/ |
| 116 | AdccRegs.ADCSOC10CTL.bit.TRIGSEL = 0; |
| 117 | AdccRegs.ADCSOC10CTL.bit.ACQPS = 14; /* Set SOC10 S/H Window to 15 ADC Clock Cycles*/ |
| 118 | AdccRegs.ADCINTSOCSEL2.bit.SOC10 = 1;/* SOCx ADCINT1 Interrupt Trigger Select.*/ |
| 119 | AdccRegs.ADCOFFTRIM.bit.OFFTRIM = AdccRegs.ADCOFFTRIM.bit.OFFTRIM;/* Set Offset Error Correctino Value*/ |
| 120 | AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;/* Late interrupt pulse trips AdcResults latch*/ |
| 121 | AdccRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0;/* All in round robin mode SOC Priority*/ |
| 122 | EDIS; |
| 123 | } |
| 124 | |
| 125 | void InitAdcA() |
| 126 | { |
| 127 | EALLOW; |
| 128 | CpuSysRegs.PCLKCR13.bit.ADC_A = 1; |
| 129 | AdcaRegs.ADCCTL2.bit.PRESCALE = 8; |
| 130 | AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); |
| 131 | |
| 132 | //power up the ADC |
| 133 | AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; |
| 134 | |
| 135 | //delay for 1ms to allow ADC time to power up |
| 136 | DELAY_US(1000); |
| 137 | EDIS; |
| 138 | } |
| 139 | |
| 140 | void InitAdcC() |
| 141 | { |
| 142 | EALLOW; |
| 143 | CpuSysRegs.PCLKCR13.bit.ADC_C = 1; |
| 144 | AdccRegs.ADCCTL2.bit.PRESCALE = 8; |
| 145 | AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); |
| 146 | |
| 147 | //power up the ADC |
| 148 | AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1; |
| 149 | |
| 150 | //delay for 1ms to allow ADC time to power up |
| 151 | DELAY_US(1000); |
| 152 | EDIS; |
| 153 | } |
| 154 | |
| 155 | void InitAdcD() |
| 156 | { |
| 157 | EALLOW; |
| 158 | CpuSysRegs.PCLKCR13.bit.ADC_D = 1; |
| 159 | AdcdRegs.ADCCTL2.bit.PRESCALE = 8; |
| 160 | AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE); |
| 161 | |
| 162 | //power up the ADC |
| 163 | AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1; |
| 164 | |
| 165 | //delay for 1ms to allow ADC time to power up |
| 166 | DELAY_US(1000); |
| 167 | EDIS; |
| 168 | } |
| 169 |