//#include "PeripheralHeaderIncludes.h" // DSP2802x Headerfile Include File and BLR global definitions //########################################################################### // // FILE: F2802x_Device.h // // TITLE: F2802x Device Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // User To Select Target Device: //--------------------------------------------------------------------------- // Common CPU Definitions: // extern cregister volatile unsigned int IFR; extern cregister volatile unsigned int IER; //--------------------------------------------------------------------------- // For Portability, User Is Recommended To Use the C99 Standard integer types // /*****************************************************************************/ /* assert.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*****************************************************************************/ /* _ti_config.h */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") #pragma CHECK_MISRA("-19.1") /* Common definitions */ /* C */ /* C89/C99 */ /* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It is intended to be used for functions like abort and atexit that are supposed to be declared noexcept only in C++14 mode. */ /* Target-specific definitions */ /*****************************************************************************/ /* linkage.h */ /* */ /* Copyright (c) 1998 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ /* No modifiers needed to access code */ /*--------------------------------------------------------------------------*/ /* Define _DATA_ACCESS ==> how to access RTS global or static data */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _IDECL ==> how inline functions are declared */ /*--------------------------------------------------------------------------*/ #pragma diag_pop #pragma diag_pop #pragma diag_push #pragma CHECK_MISRA("-6.3") /* standard types required for standard headers */ #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ #pragma CHECK_MISRA("-19.7") /* macros required for implementation */ #pragma CHECK_MISRA("-19.13") /* # and ## required for implementation */ extern void _abort_msg(const char *msg); #pragma diag_pop /*****************************************************************************/ /* stdarg.h */ /* */ /* Copyright (c) 1996 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ #pragma CHECK_MISRA("-19.7") /* macros required for implementation */ #pragma CHECK_MISRA("-19.10") /* need types as macro arguments */ typedef char *va_list; /****************************************************************************/ /* RETURN THE NEXT VALUE ON THE STACK ... */ /* */ /* (, ) BECOMES ... */ /* */ /* ap -= 1 (stack grows toward high addresses) */ /* ap -= 1 more if type is long or float */ /* ap -= 1 more if type is long or float and to account for alignment */ /* if necessary */ /* */ /* if () return **ap; */ /* else if () return *ap; */ /* */ /* LONG/FLOATS ARE ALWAYS ALIGNED ON AN EVEN WORD BOUNDARY, EVEN WHEN */ /* PASSED AS PARAMETERS, THUS ap MUST BE ALIGNED FOR THOSE ACCESSES. */ /****************************************************************************/ #pragma diag_pop /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /*****************************************************************************/ /* stddef.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.7") /* macros required for implementation */ #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ typedef long ptrdiff_t; typedef unsigned long size_t; typedef unsigned int wchar_t; /*----------------------------------------------------------------------------*/ /* C++11 and C11 required max_align_t to be defined. The libc++ cstddef */ /* header expects the macro __DEFINED_max_align_t to be defined if it is to */ /* use the definintion of max_align_t from stddef.h. Only define it if */ /* compiling for C11 or we're in non strict ansi mode. */ /*----------------------------------------------------------------------------*/ typedef long double max_align_t; #pragma diag_push #pragma CHECK_MISRA("-19.10") /* need types as macro arguments */ #pragma diag_pop #pragma diag_pop /*****************************************************************************/ /* STDINT.H */ /* */ /* Copyright (c) 2002 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /* 7.18.1.1 Exact-width integer types */ typedef int int16_t; typedef unsigned int uint16_t; typedef long int32_t; typedef unsigned long uint32_t; typedef long long int64_t; typedef unsigned long long uint64_t; /* 7.18.1.2 Minimum-width integer types */ typedef int16_t int_least8_t; typedef uint16_t uint_least8_t; typedef int16_t int_least16_t; typedef uint16_t uint_least16_t; typedef int32_t int_least32_t; typedef uint32_t uint_least32_t; typedef int64_t int_least64_t; typedef uint64_t uint_least64_t; /* 7.18.1.3 Fastest minimum-width integer types */ typedef int16_t int_fast8_t; typedef uint16_t uint_fast8_t; typedef int16_t int_fast16_t; typedef uint16_t uint_fast16_t; typedef int32_t int_fast32_t; typedef uint32_t uint_fast32_t; typedef int64_t int_fast64_t; typedef uint64_t uint_fast64_t; /* 7.18.1.4 Integer types capable of holding object pointers */ typedef long intptr_t; typedef unsigned long uintptr_t; /* 7.18.1.5 Greatest-width integer types */ typedef long long intmax_t; typedef unsigned long long uintmax_t; /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ /* 7.18.2 Limits of specified width integer types */ /* 7.18.3 Limits of other integer types */ /* 7.18.4.1 Macros for minimum-width integer constants */ /* There is a defect report filed against the C99 standard concerning how the (U)INTN_C macros should be implemented. Please refer to -- http://wwwold.dkuug.dk/JTC1/SC22/WG14/www/docs/dr_209.htm for more information. These macros are implemented according to the suggestion given at this web site. */ /* 7.18.4.2 Macros for greatest-width integer constants */ // C99 defines boolean type to be _Bool, but this doesn't match the format of // the other standard integer types. bool_t has been defined to fill this gap. typedef _Bool bool_t; // Work around for code that might accidentally use uint8_t typedef unsigned char uint8_t; //--------------------------------------------------------------------------- // The following data types are included for compatibility with legacy code, // they are not recommended for use in new software. Please use the C99 // types included above // typedef int int16; typedef long int32; typedef unsigned int Uint16; typedef unsigned long Uint32; typedef float float32; typedef long double float64; //--------------------------------------------------------------------------- // Include All Peripheral Header Files: // //########################################################################### // // FILE: F2802x_Adc.h // // TITLE: F2802x Device ADC Register Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // ADC Individual Register Bit Definitions: struct ADCCTL1_BITS { // bits description uint16_t TEMPCONV:1; // 0 Temperature sensor connection uint16_t VREFLOCONV:1; // 1 VSSA connection uint16_t INTPULSEPOS:1; // 2 INT pulse generation control uint16_t ADCREFSEL:1; // 3 Internal/external reference select uint16_t rsvd1:1; // 4 reserved uint16_t ADCREFPWD:1; // 5 Reference buffers powerdown uint16_t ADCBGPWD:1; // 6 ADC bandgap powerdown uint16_t ADCPWDN:1; // 7 ADC powerdown uint16_t ADCBSYCHN:5; // 12:8 ADC busy on a channel uint16_t ADCBSY:1; // 13 ADC busy signal uint16_t ADCENABLE:1; // 14 ADC enable uint16_t RESET:1; // 15 ADC master reset }; union ADCCTL1_REG { uint16_t all; struct ADCCTL1_BITS bit; }; // This register is not supported in Rev. 0 silicon. struct ADCCTL2_BITS { // bits description uint16_t CLKDIV2EN:1; // 0 ADC input clock /2 enable uint16_t ADCNONOVERLAP:1; // 1 ADCNONOVERLAP Control bit uint16_t rsvd1:14; // 15:2 reserved }; union ADCCTL2_REG { uint16_t all; struct ADCCTL2_BITS bit; }; struct ADCINT_BITS { // bits description uint16_t ADCINT1:1; // 0 ADC Interrupt Flag 1 uint16_t ADCINT2:1; // 1 ADC Interrupt Flag 2 uint16_t ADCINT3:1; // 2 ADC Interrupt Flag 3 uint16_t ADCINT4:1; // 3 ADC Interrupt Flag 4 uint16_t ADCINT5:1; // 4 ADC Interrupt Flag 5 uint16_t ADCINT6:1; // 5 ADC Interrupt Flag 6 uint16_t ADCINT7:1; // 6 ADC Interrupt Flag 7 uint16_t ADCINT8:1; // 7 ADC Interrupt Flag 8 uint16_t ADCINT9:1; // 8 ADC Interrupt Flag 9 uint16_t rsvd1:7; // 15:9 reserved }; union ADCINT_REG { uint16_t all; struct ADCINT_BITS bit; }; struct INTSEL1N2_BITS { // bits description uint16_t INT1SEL:5; // 4:0 INTx EOC Source Select uint16_t INT1E:1; // 5 INTx Interrupt Enable uint16_t INT1CONT:1; // 6 INTx Continuous Mode Enable uint16_t rsvd1:1; // 7 reserved uint16_t INT2SEL:5; // 12:8 INTy EOC Source Select uint16_t INT2E:1; // 13 INTy Interrupt Enable uint16_t INT2CONT:1; // 14 INTy Continuous Mode Enable uint16_t rsvd2:1; // 15 reserved }; union INTSEL1N2_REG { uint16_t all; struct INTSEL1N2_BITS bit; }; struct INTSEL3N4_BITS { // bits description uint16_t INT3SEL:5; // 4:0 INTx EOC Source Select uint16_t INT3E:1; // 5 INTx Interrupt Enable uint16_t INT3CONT:1; // 6 INTx Continuous Mode Enable uint16_t rsvd1:1; // 7 reserved uint16_t INT4SEL:5; // 12:8 INTy EOC Source Select uint16_t INT4E:1; // 13 INTy Interrupt Enable uint16_t INT4CONT:1; // 14 INTy Continuous Mode Enable uint16_t rsvd2:1; // 15 reserved }; union INTSEL3N4_REG { uint16_t all; struct INTSEL3N4_BITS bit; }; struct INTSEL5N6_BITS { // bits description uint16_t INT5SEL:5; // 4:0 INTx EOC Source Select uint16_t INT5E:1; // 5 INTx Interrupt Enable uint16_t INT5CONT:1; // 6 INTx Continuous Mode Enable uint16_t rsvd1:1; // 7 reserved uint16_t INT6SEL:5; // 12:8 INTy EOC Source Select uint16_t INT6E:1; // 13 INTy Interrupt Enable uint16_t INT6CONT:1; // 14 INTy Continuous Mode Enable uint16_t rsvd2:1; // 15 reserved }; union INTSEL5N6_REG { uint16_t all; struct INTSEL5N6_BITS bit; }; struct INTSEL7N8_BITS { // bits description uint16_t INT7SEL:5; // 4:0 INTx EOC Source Select uint16_t INT7E:1; // 5 INTx Interrupt Enable uint16_t INT7CONT:1; // 6 INTx Continuous Mode Enable uint16_t rsvd1:1; // 7 reserved uint16_t INT8SEL:5; // 12:8 INTy EOC Source Select uint16_t INT8E:1; // 13 INTy Interrupt Enable uint16_t INT8CONT:1; // 14 INTy Continuous Mode Enable uint16_t rsvd2:1; // 15 reserved }; union INTSEL7N8_REG { uint16_t all; struct INTSEL7N8_BITS bit; }; struct INTSEL9N10_BITS { // bits description uint16_t INT9SEL:5; // 4:0 INTx EOC Source Select uint16_t INT9E:1; // 5 INTx Interrupt Enable uint16_t INT9CONT:1; // 6 INTx Continuous Mode Enable uint16_t rsvd1:1; // 7 reserved uint16_t INT10SEL:5; // 12:8 INTy EOC Source Select uint16_t INT10E:1; // 13 INTy Interrupt Enable uint16_t INT10CONT:1; // 14 INTy Continuous Mode Enable uint16_t rsvd2:1; // 15 reserved }; union INTSEL9N10_REG { uint16_t all; struct INTSEL9N10_BITS bit; }; struct SOCPRICTL_BITS { // bits description uint16_t SOCPRIORITY:5; // 4:0 Start-of-conversion Priority uint16_t RRPOINTER:6; // 10:5 Round Robin Pointer uint16_t rsvd1:4; // 14:11 reserved uint16_t ONESHOT:1; // 15 One Shot Mode Enabled - bit does not exist in Rev. 0 silicon }; union SOCPRICTL_REG { uint16_t all; struct SOCPRICTL_BITS bit; }; struct ADCSAMPLEMODE_BITS { // bits description uint16_t SIMULEN0:1; // 0 SOC0 Simultaneous Sampling Enable uint16_t SIMULEN2:1; // 1 SOC2 Simultaneous Sampling Enable uint16_t SIMULEN4:1; // 2 SOC4 Simultaneous Sampling Enable uint16_t SIMULEN6:1; // 3 SOC6 Simultaneous Sampling Enable uint16_t SIMULEN8:1; // 4 SOC8 Simultaneous Sampling Enable uint16_t SIMULEN10:1; // 5 SOC10 Simultaneous Sampling Enable uint16_t SIMULEN12:1; // 6 SOC12 Simultaneous Sampling Enable uint16_t SIMULEN14:1; // 7 SOC14 Simultaneous Sampling Enable uint16_t rsvd1:8; //15:8 reserved }; union ADCSAMPLEMODE_REG { uint16_t all; struct ADCSAMPLEMODE_BITS bit; }; struct ADCINTSOCSEL1_BITS { // bits description uint16_t SOC0:2; // 1:0 ADCINT Start-of-conversion Select uint16_t SOC1:2; // 3:2 ADCINT Start-of-conversion Select uint16_t SOC2:2; // 5:4 ADCINT Start-of-conversion Select uint16_t SOC3:2; // 7:6 ADCINT Start-of-conversion Select uint16_t SOC4:2; // 9:8 ADCINT Start-of-conversion Select uint16_t SOC5:2; // 11:10 ADCINT Start-of-conversion Select uint16_t SOC6:2; // 13:12 ADCINT Start-of-conversion Select uint16_t SOC7:2; // 15:14 ADCINT Start-of-conversion Select }; union ADCINTSOCSEL1_REG { uint16_t all; struct ADCINTSOCSEL1_BITS bit; }; struct ADCINTSOCSEL2_BITS { // bits description uint16_t SOC8:2; // 1:0 ADCINT Start-of-conversion Select uint16_t SOC9:2; // 3:2 ADCINT Start-of-conversion Select uint16_t SOC10:2; // 5:4 ADCINT Start-of-conversion Select uint16_t SOC11:2; // 7:6 ADCINT Start-of-conversion Select uint16_t SOC12:2; // 9:8 ADCINT Start-of-conversion Select uint16_t SOC13:2; // 11:10 ADCINT Start-of-conversion Select uint16_t SOC14:2; // 13:12 ADCINT Start-of-conversion Select uint16_t SOC15:2; // 15:14 ADCINT Start-of-conversion Select }; union ADCINTSOCSEL2_REG { uint16_t all; struct ADCINTSOCSEL2_BITS bit; }; struct ADCSOC_BITS { // bits description uint16_t SOC0:1; // 0 Start-of-conversion for CONV0 uint16_t SOC1:1; // 1 Start-of-conversion for CONV1 uint16_t SOC2:1; // 2 Start-of-conversion for CONV2 uint16_t SOC3:1; // 3 Start-of-conversion for CONV3 uint16_t SOC4:1; // 4 Start-of-conversion for CONV4 uint16_t SOC5:1; // 5 Start-of-conversion for CONV5 uint16_t SOC6:1; // 6 Start-of-conversion for CONV6 uint16_t SOC7:1; // 7 Start-of-conversion for CONV7 uint16_t SOC8:1; // 8 Start-of-conversion for CONV8 uint16_t SOC9:1; // 9 Start-of-conversion for CONV9 uint16_t SOC10:1; // 10 Start-of-conversion for CONV10 uint16_t SOC11:1; // 11 Start-of-conversion for CONV11 uint16_t SOC12:1; // 12 Start-of-conversion for CONV12 uint16_t SOC13:1; // 13 Start-of-conversion for CONV13 uint16_t SOC14:1; // 14 Start-of-conversion for CONV14 uint16_t SOC15:1; // 15 Start-of-conversion for CONV15 }; union ADCSOC_REG { uint16_t all; struct ADCSOC_BITS bit; }; struct ADCSOCxCTL_BITS { // bits description uint16_t ACQPS:6; // 5:0 Acquisition Pulse Size uint16_t CHSEL:4; // 9:6 SOCx Channel Select uint16_t rsvd1:1; // 10 reserved uint16_t TRIGSEL:5; // 15:11 SOCx Trigger Select }; union ADCSOCxCTL_REG { uint16_t all; struct ADCSOCxCTL_BITS bit; }; // Rev. 0 silicon - BG_FINE_TRIM = bits 3:0. // BG_COARSE_TRIM = bits : 8:4 // Rev. A and beyond silicon = below register definition: struct ADCREFTRIM_BITS{ // bits description uint16_t BG_FINE_TRIM:5; // 4:0 Coarse trim for internal BG uint16_t BG_COARSE_TRIM:4; // 8:5 Fine trim for internal BG uint16_t EXTREF_FINE_TRIM:5; // 13:9 Fine trim for external reference uint16_t rsvd1:2; // 15:14 reserved }; union ADCREFTRIM_REG{ uint16_t all; struct ADCREFTRIM_BITS bit; }; struct ADCOFFTRIM_BITS{ // bits description int16_t OFFTRIM:9; // 8:0 Offset Trim uint16_t rsvd1:7; // 15:9 reserved }; union ADCOFFTRIM_REG{ uint16_t all; struct ADCOFFTRIM_BITS bit; }; struct COMPHYSTCTL_BITS{ // bits description uint16_t rsvd1:1; // 0 reserved uint16_t COMP1_HYST_DISABLE:1; // 1 Comparator 1 Hysteresis Disable uint16_t rsvd2:4; // 5:2 reserved uint16_t COMP2_HYST_DISABLE:1; // 6 Comparator 2 Hysteresis Disable uint16_t rsvd3:10; // 15:7 reserved }; union COMPHYSTCTL_REG{ uint16_t all; struct COMPHYSTCTL_BITS bit; }; //--------------------------------------------------------------------------- // ADC Register Definitions: struct ADC_REGS { union ADCCTL1_REG ADCCTL1; // ADC Control 1 union ADCCTL2_REG ADCCTL2; // ADC Control 2 - not available in Rev. 0 silicon uint16_t rsvd1[2]; // reserved union ADCINT_REG ADCINTFLG; // ADC Interrupt Flag union ADCINT_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear union ADCINT_REG ADCINTOVF; // ADC Interrupt Overflow union ADCINT_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear union INTSEL1N2_REG INTSEL1N2; // ADC Interrupt 1 and 2 Selection union INTSEL3N4_REG INTSEL3N4; // ADC Interrupt 3 and 4 Selection union INTSEL5N6_REG INTSEL5N6; // ADC Interrupt 5 and 6 Selection union INTSEL7N8_REG INTSEL7N8; // ADC Interrupt 7 and 8 Selection union INTSEL9N10_REG INTSEL9N10; // ADC Interrupt 9 and 10 Selection uint16_t rsvd2[3]; // reserved union SOCPRICTL_REG SOCPRICTL; // ADC SOC Priority Control uint16_t rsvd3; // reserved union ADCSAMPLEMODE_REG ADCSAMPLEMODE; // ADC Sampling Mode uint16_t rsvd4; // reserved union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 uint16_t rsvd5[2]; // reserved union ADCSOC_REG ADCSOCFLG1; // ADC SOC Flag 1 uint16_t rsvd6; // reserved union ADCSOC_REG ADCSOCFRC1; // ADC SOC Flag Force 1 uint16_t rsvd7; // reserved union ADCSOC_REG ADCSOCOVF1; // ADC SOC Overflow 1 uint16_t rsvd8; // reserved union ADCSOC_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 uint16_t rsvd9; // reserved union ADCSOCxCTL_REG ADCSOC0CTL; // ADC SOC0 Control union ADCSOCxCTL_REG ADCSOC1CTL; // ADC SOC1 Control union ADCSOCxCTL_REG ADCSOC2CTL; // ADC SOC2 Control union ADCSOCxCTL_REG ADCSOC3CTL; // ADC SOC3 Control union ADCSOCxCTL_REG ADCSOC4CTL; // ADC SOC4 Control union ADCSOCxCTL_REG ADCSOC5CTL; // ADC SOC5 Control union ADCSOCxCTL_REG ADCSOC6CTL; // ADC SOC6 Control union ADCSOCxCTL_REG ADCSOC7CTL; // ADC SOC7 Control union ADCSOCxCTL_REG ADCSOC8CTL; // ADC SOC8 Control union ADCSOCxCTL_REG ADCSOC9CTL; // ADC SOC9 Control union ADCSOCxCTL_REG ADCSOC10CTL; // ADC SOC10 Control union ADCSOCxCTL_REG ADCSOC11CTL; // ADC SOC11 Control union ADCSOCxCTL_REG ADCSOC12CTL; // ADC SOC12 Control union ADCSOCxCTL_REG ADCSOC13CTL; // ADC SOC13 Control union ADCSOCxCTL_REG ADCSOC14CTL; // ADC SOC14 Control union ADCSOCxCTL_REG ADCSOC15CTL; // ADC SOC15 Control uint16_t rsvd10 [16]; // reserved union ADCREFTRIM_REG ADCREFTRIM; // Reference Trim Register union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register uint16_t rsvd11 [10]; // reserved union COMPHYSTCTL_REG COMPHYSTCTL; // COMP Hysteresis Control Register uint16_t rsvd12 [3]; // reserved }; struct ADC_RESULT_REGS { uint16_t ADCRESULT0; // Conversion Result Buffer 0 uint16_t ADCRESULT1; // Conversion Result Buffer 1 uint16_t ADCRESULT2; // Conversion Result Buffer 2 uint16_t ADCRESULT3; // Conversion Result Buffer 3 uint16_t ADCRESULT4; // Conversion Result Buffer 4 uint16_t ADCRESULT5; // Conversion Result Buffer 5 uint16_t ADCRESULT6; // Conversion Result Buffer 6 uint16_t ADCRESULT7; // Conversion Result Buffer 7 uint16_t ADCRESULT8; // Conversion Result Buffer 8 uint16_t ADCRESULT9; // Conversion Result Buffer 9 uint16_t ADCRESULT10; // Conversion Result Buffer 10 uint16_t ADCRESULT11; // Conversion Result Buffer 11 uint16_t ADCRESULT12; // Conversion Result Buffer 12 uint16_t ADCRESULT13; // Conversion Result Buffer 13 uint16_t ADCRESULT14; // Conversion Result Buffer 14 uint16_t ADCRESULT15; // Conversion Result Buffer 15 uint16_t rsvd[16]; // reserved }; //--------------------------------------------------------------------------- // ADC External References & Function Declarations: // extern volatile struct ADC_REGS AdcRegs; extern volatile struct ADC_RESULT_REGS AdcResult; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_BootVars.h // // TITLE: F2802x Boot Variable Definitions. // // NOTES: // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // External Boot ROM variable definitions: // extern uint16_t EmuKey; extern uint16_t EmuBMode; extern uint32_t Flash_CPUScaleFactor; extern void (*Flash_CallbackPtr) (void); //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_DevEmu.h // // TITLE: F2802x Device Emulation Register Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // Device Emulation Register Bit Definitions: // // Device Configuration Register Bit Definitions struct DEVICECNF_BITS { // bits description uint16_t rsvd1:3; // 2:0 reserved uint16_t VMAPS:1; // 3 VMAP Status uint16_t rsvd2:1; // 4 reserved uint16_t XRSn:1; // 5 XRSn Signal Status uint16_t rsvd3:10; // 15:6 reserved uint16_t rsvd4:3; // 18:16 reserved uint16_t ENPROT:1; // 19 Enable/Disable pipeline protection uint16_t rsvd5:7; // 26:21 reserved uint16_t TRSTn:1; // 27 Status of TRSTn signal uint16_t rsvd6:4; // 31:28 reserved }; union DEVICECNF_REG { uint32_t all; struct DEVICECNF_BITS bit; }; // CLASSID struct CLASSID_BITS { // bits description uint16_t CLASSNO:8; // 7:0 Class Number uint16_t PARTTYPE:8; // 15:8 Part Type }; union CLASSID_REG { uint16_t all; struct CLASSID_BITS bit; }; struct DEV_EMU_REGS { union DEVICECNF_REG DEVICECNF; // Device Configuration union CLASSID_REG CLASSID; // Class ID uint16_t REVID; // Device ID }; // PARTID struct PARTID_BITS { // bits description uint16_t PARTNO:8; // 7:0 Part Number uint16_t PARTTYPE:8; // 15:8 Part Type }; union PARTID_REG { uint16_t all; struct PARTID_BITS bit; }; struct PARTID_REGS { union PARTID_REG PARTID; // Part ID }; //--------------------------------------------------------------------------- // Device Emulation Register References & Function Declarations: // extern volatile struct DEV_EMU_REGS DevEmuRegs; extern volatile struct PARTID_REGS PartIdRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_Comp.h // // TITLE: F2802x Device Comparator Register Definitions // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //=========================================================================== // Comparator Register Bit Definitions // struct COMPCTL_BITS { // bit description uint16_t COMPDACEN:1; // 0 Comparator/DAC Enable uint16_t COMPSOURCE:1; // 1 Source select for comparator inverting input uint16_t CMPINV:1; // 2 Invert select for Comparator uint16_t QUALSEL:5; // 7:03 Qualification Period for synchronized output of the comparator uint16_t SYNCSEL:1; // 8 Synchronization select for output of the comparator uint16_t rsvd1:7; // 15:09 reserved }; union COMPCTL_REG { uint16_t all; struct COMPCTL_BITS bit; }; struct COMPSTS_BITS { // bit description uint16_t COMPSTS:1; // 0 Logical latched value of the comparator uint16_t rsvd1:15; // 15:01 reserved }; union COMPSTS_REG { uint16_t all; struct COMPSTS_BITS bit; }; struct DACVAL_BITS { // bit description uint16_t DACVAL:10; // 9:00 DAC Value bit uint16_t rsvd1:6; // 15:10 reserved }; union DACVAL_REG { uint16_t all; struct DACVAL_BITS bit; }; //=========================================================================== // Comparator Register Definitions // struct COMP_REGS { union COMPCTL_REG COMPCTL; uint16_t rsvd1; union COMPSTS_REG COMPSTS; uint16_t rsvd2[3]; union DACVAL_REG DACVAL; uint16_t rsvd4[10]; }; //=========================================================================== // Comparator External References and Function Declarations // extern volatile struct COMP_REGS Comp1Regs; extern volatile struct COMP_REGS Comp2Regs; //=========================================================================== // End of file //=========================================================================== //########################################################################### // // FILE: F2802x_CpuTimers.h // // TITLE: F2802x CPU 32-bit Timers Register Definitions. // // NOTES: CpuTimer2 is reserved for use with DSP BIOS and // other realtime operating systems. // // Do not use these CpuTimer2 in your application if you ever plan // on integrating DSP-BIOS or another realtime OS. // // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // CPU Timer Register Bit Definitions: // // // TCR: Control register bit definitions: struct TCR_BITS { // bits description uint16_t rsvd1:4; // 3:0 reserved uint16_t TSS:1; // 4 Timer Start/Stop uint16_t TRB:1; // 5 Timer reload uint16_t rsvd2:4; // 9:6 reserved uint16_t SOFT:1; // 10 Emulation modes uint16_t FREE:1; // 11 uint16_t rsvd3:2; // 12:13 reserved uint16_t TIE:1; // 14 Output enable uint16_t TIF:1; // 15 Interrupt flag }; union TCR_REG { uint16_t all; struct TCR_BITS bit; }; // TPR: Pre-scale low bit definitions: struct TPR_BITS { // bits description uint16_t TDDR:8; // 7:0 Divide-down low uint16_t PSC:8; // 15:8 Prescale counter low }; union TPR_REG { uint16_t all; struct TPR_BITS bit; }; // TPRH: Pre-scale high bit definitions: struct TPRH_BITS { // bits description uint16_t TDDRH:8; // 7:0 Divide-down high uint16_t PSCH:8; // 15:8 Prescale counter high }; union TPRH_REG { uint16_t all; struct TPRH_BITS bit; }; // TIM, TIMH: Timer register definitions: struct TIM_REG { uint16_t LSW; uint16_t MSW; }; union TIM_GROUP { uint32_t all; struct TIM_REG half; }; // PRD, PRDH: Period register definitions: struct PRD_REG { uint16_t LSW; uint16_t MSW; }; union PRD_GROUP { uint32_t all; struct PRD_REG half; }; //--------------------------------------------------------------------------- // CPU Timer Register File: // struct CPUTIMER_REGS { union TIM_GROUP TIM; // Timer counter register union PRD_GROUP PRD; // Period register union TCR_REG TCR; // Timer control register uint16_t rsvd1; // reserved union TPR_REG TPR; // Timer pre-scale low union TPRH_REG TPRH; // Timer pre-scale high }; //--------------------------------------------------------------------------- // CPU Timer Support Variables: // struct CPUTIMER_VARS { volatile struct CPUTIMER_REGS *RegsAddr; uint32_t InterruptCount; float CPUFreqInMHz; float PeriodInUSec; }; //--------------------------------------------------------------------------- // Function prototypes and external definitions: // void InitCpuTimers(void); void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); extern volatile struct CPUTIMER_REGS CpuTimer0Regs; extern struct CPUTIMER_VARS CpuTimer0; // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS extern volatile struct CPUTIMER_REGS CpuTimer1Regs; extern volatile struct CPUTIMER_REGS CpuTimer2Regs; extern struct CPUTIMER_VARS CpuTimer1; extern struct CPUTIMER_VARS CpuTimer2; //--------------------------------------------------------------------------- // Usefull Timer Operations: // // Start Timer: // Stop Timer: // Reload Timer With period Value: // Read 32-Bit Timer Value: // Read 32-Bit Period Value: // CpuTimer2 is reserved for DSP BIOS & other RTOS // Do not use this timers if you ever plan on integrating // DSP-BIOS or another realtime OS. // // For this reason, comment out the code to manipulate this timers // if using DSP-BIOS or another realtime OS. // Start Timer: // Stop Timer: // Reload Timer With period Value: // Read 32-Bit Timer Value: // Read 32-Bit Period Value: //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_ECap.h // // TITLE: F2802x Enhanced Capture Module Register Bit Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //---------------------------------------------------- // Capture control register 1 bit definitions */ struct ECCTL1_BITS { // bits description uint16_t CAP1POL:1; // 0 Capture Event 1 Polarity select uint16_t CTRRST1:1; // 1 Counter Reset on Capture Event 1 uint16_t CAP2POL:1; // 2 Capture Event 2 Polarity select uint16_t CTRRST2:1; // 3 Counter Reset on Capture Event 2 uint16_t CAP3POL:1; // 4 Capture Event 3 Polarity select uint16_t CTRRST3:1; // 5 Counter Reset on Capture Event 3 uint16_t CAP4POL:1; // 6 Capture Event 4 Polarity select uint16_t CTRRST4:1; // 7 Counter Reset on Capture Event 4 uint16_t CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event uint16_t PRESCALE:5; // 13:9 Event Filter prescale select uint16_t FREE_SOFT:2; // 15:14 Emulation mode }; union ECCTL1_REG { uint16_t all; struct ECCTL1_BITS bit; }; // In V1.1 the STOPVALUE bit field was changed to // STOP_WRAP. This correlated to a silicon change from // F2802x Rev 0 to Rev A. //---------------------------------------------------- // Capture control register 2 bit definitions */ struct ECCTL2_BITS { // bits description uint16_t CONT_ONESHT:1; // 0 Continuous or one-shot uint16_t STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous uint16_t REARM:1; // 3 One-shot re-arm uint16_t TSCTRSTOP:1; // 4 TSCNT counter stop uint16_t SYNCI_EN:1; // 5 Counter sync-in select uint16_t SYNCO_SEL:2; // 7:6 Sync-out mode uint16_t SWSYNC:1; // 8 SW forced counter sync uint16_t CAP_APWM:1; // 9 CAP/APWM operating mode select uint16_t APWMPOL:1; // 10 APWM output polarity select uint16_t rsvd1:5; // 15:11 }; union ECCTL2_REG { uint16_t all; struct ECCTL2_BITS bit; }; //---------------------------------------------------- // ECAP interrupt enable register bit definitions */ struct ECEINT_BITS { // bits description uint16_t rsvd1:1; // 0 reserved uint16_t CEVT1:1; // 1 Capture Event 1 Interrupt Enable uint16_t CEVT2:1; // 2 Capture Event 2 Interrupt Enable uint16_t CEVT3:1; // 3 Capture Event 3 Interrupt Enable uint16_t CEVT4:1; // 4 Capture Event 4 Interrupt Enable uint16_t CTROVF:1; // 5 Counter Overflow Interrupt Enable uint16_t CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable uint16_t CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable uint16_t rsvd2:8; // 15:8 reserved }; union ECEINT_REG { uint16_t all; struct ECEINT_BITS bit; }; //---------------------------------------------------- // ECAP interrupt flag register bit definitions */ struct ECFLG_BITS { // bits description uint16_t INT:1; // 0 Global Flag uint16_t CEVT1:1; // 1 Capture Event 1 Interrupt Flag uint16_t CEVT2:1; // 2 Capture Event 2 Interrupt Flag uint16_t CEVT3:1; // 3 Capture Event 3 Interrupt Flag uint16_t CEVT4:1; // 4 Capture Event 4 Interrupt Flag uint16_t CTROVF:1; // 5 Counter Overflow Interrupt Flag uint16_t CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag uint16_t CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag uint16_t rsvd2:8; // 15:8 reserved }; union ECFLG_REG { uint16_t all; struct ECFLG_BITS bit; }; //---------------------------------------------------- struct ECAP_REGS { uint32_t TSCTR; // Time stamp counter uint32_t CTRPHS; // Counter phase uint32_t CAP1; // Capture 1 uint32_t CAP2; // Capture 2 uint32_t CAP3; // Capture 3 uint32_t CAP4; // Capture 4 uint16_t rsvd1[8]; // reserved union ECCTL1_REG ECCTL1; // Capture Control Reg 1 union ECCTL2_REG ECCTL2; // Capture Control Reg 2 union ECEINT_REG ECEINT; // ECAP interrupt enable union ECFLG_REG ECFLG; // ECAP interrupt flags union ECFLG_REG ECCLR; // ECAP interrupt clear union ECEINT_REG ECFRC; // ECAP interrupt force uint16_t rsvd2[6]; // reserved }; //--------------------------------------------------------------------------- // GPI/O External References & Function Declarations: // extern volatile struct ECAP_REGS ECap1Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_EPWM.h // // TITLE: F2802x Enhanced PWM Module Register Bit Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //---------------------------------------------------- // Time base control register bit definitions */ struct TBCTL_BITS { // bits description uint16_t CTRMODE:2; // 1:0 Counter Mode uint16_t PHSEN:1; // 2 Phase load enable uint16_t PRDLD:1; // 3 Active period load uint16_t SYNCOSEL:2; // 5:4 Sync output select uint16_t SWFSYNC:1; // 6 Software force sync pulse uint16_t HSPCLKDIV:3; // 9:7 High speed time pre-scale uint16_t CLKDIV:3; // 12:10 Timebase clock pre-scale uint16_t PHSDIR:1; // 13 Phase Direction uint16_t FREE_SOFT:2; // 15:14 Emulation mode }; union TBCTL_REG { uint16_t all; struct TBCTL_BITS bit; }; //---------------------------------------------------- // Time base status register bit definitions */ struct TBSTS_BITS { // bits description uint16_t CTRDIR:1; // 0 Counter direction status uint16_t SYNCI:1; // 1 External input sync status uint16_t CTRMAX:1; // 2 Counter max latched status uint16_t rsvd1:13; // 15:3 reserved }; union TBSTS_REG { uint16_t all; struct TBSTS_BITS bit; }; //---------------------------------------------------- // Compare control register bit definitions */ struct CMPCTL_BITS { // bits description uint16_t LOADAMODE:2; // 0:1 Active compare A uint16_t LOADBMODE:2; // 3:2 Active compare B uint16_t SHDWAMODE:1; // 4 Compare A block operating mode uint16_t rsvd1:1; // 5 reserved uint16_t SHDWBMODE:1; // 6 Compare B block operating mode uint16_t rsvd2:1; // 7 reserved uint16_t SHDWAFULL:1; // 8 Compare A Shadow registers full Status uint16_t SHDWBFULL:1; // 9 Compare B Shadow registers full Status uint16_t rsvd3:6; // 15:10 reserved }; union CMPCTL_REG { uint16_t all; struct CMPCTL_BITS bit; }; //---------------------------------------------------- // Action qualifier register bit definitions */ struct AQCTL_BITS { // bits description uint16_t ZRO:2; // 1:0 Action Counter = Zero uint16_t PRD:2; // 3:2 Action Counter = Period uint16_t CAU:2; // 5:4 Action Counter = Compare A up uint16_t CAD:2; // 7:6 Action Counter = Compare A down uint16_t CBU:2; // 9:8 Action Counter = Compare B up uint16_t CBD:2; // 11:10 Action Counter = Compare B down uint16_t rsvd:4; // 15:12 reserved }; union AQCTL_REG { uint16_t all; struct AQCTL_BITS bit; }; //---------------------------------------------------- // Action qualifier SW force register bit definitions */ struct AQSFRC_BITS { // bits description uint16_t ACTSFA:2; // 1:0 Action when One-time SW Force A invoked uint16_t OTSFA:1; // 2 One-time SW Force A output uint16_t ACTSFB:2; // 4:3 Action when One-time SW Force B invoked uint16_t OTSFB:1; // 5 One-time SW Force A output uint16_t RLDCSF:2; // 7:6 Reload from Shadow options uint16_t rsvd1:8; // 15:8 reserved }; union AQSFRC_REG { uint16_t all; struct AQSFRC_BITS bit; }; //---------------------------------------------------- // Action qualifier continuous SW force register bit definitions */ struct AQCSFRC_BITS { // bits description uint16_t CSFA:2; // 1:0 Continuous Software Force on output A uint16_t CSFB:2; // 3:2 Continuous Software Force on output B uint16_t rsvd1:12; // 15:4 reserved }; union AQCSFRC_REG { uint16_t all; struct AQCSFRC_BITS bit; }; //---------------------------------------------------- // Dead-band generator control register bit definitions struct DBCTL_BITS { // bits description uint16_t OUT_MODE:2; // 1:0 Dead Band Output Mode Control uint16_t POLSEL:2; // 3:2 Polarity Select Control uint16_t IN_MODE:2; // 5:4 Dead Band Input Select Mode Control uint16_t rsvd1:9; // 14:4 reserved uint16_t HALFCYCLE:1; // 15 Half Cycle Clocking Enable }; union DBCTL_REG { uint16_t all; struct DBCTL_BITS bit; }; //---------------------------------------------------- // Trip zone select register bit definitions struct TZSEL_BITS { // bits description uint16_t CBC1:1; // 0 TZ1 CBC select uint16_t CBC2:1; // 1 TZ2 CBC select uint16_t CBC3:1; // 2 TZ3 CBC select uint16_t CBC4:1; // 3 TZ4 CBC select uint16_t CBC5:1; // 4 TZ5 CBC select uint16_t CBC6:1; // 5 TZ6 CBC select uint16_t DCAEVT2:1; // 6 DCAEVT2 uint16_t DCBEVT2:1; // 7 DCBEVT2 uint16_t OSHT1:1; // 8 One-shot TZ1 select uint16_t OSHT2:1; // 9 One-shot TZ2 select uint16_t OSHT3:1; // 10 One-shot TZ3 select uint16_t OSHT4:1; // 11 One-shot TZ4 select uint16_t OSHT5:1; // 12 One-shot TZ5 select uint16_t OSHT6:1; // 13 One-shot TZ6 select uint16_t DCAEVT1:1; // 14 DCAEVT1 uint16_t DCBEVT1:1; // 15 DCBEVT1 }; union TZSEL_REG { uint16_t all; struct TZSEL_BITS bit; }; //---------------------------------------------------- // Trip zone digital compare event select register struct TZDCSEL_BITS { // bits description uint16_t DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 uint16_t DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 uint16_t DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 uint16_t DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 uint16_t rsvd1:4; // 15:12 reserved }; union TZDCSEL_REG { uint16_t all; struct TZDCSEL_BITS bit; }; //---------------------------------------------------- // Trip zone control register bit definitions */ struct TZCTL_BITS { // bits description uint16_t TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA uint16_t TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB uint16_t DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 uint16_t DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 uint16_t DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 uint16_t DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 uint16_t rsvd:4; // 15:12 reserved }; union TZCTL_REG { uint16_t all; struct TZCTL_BITS bit; }; //---------------------------------------------------- // Trip zone control register bit definitions */ struct TZEINT_BITS { // bits description uint16_t rsvd1:1; // 0 reserved uint16_t CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable uint16_t OST:1; // 2 Trip Zones One Shot Int Enable uint16_t DCAEVT1:1; // 3 Force DCAEVT1 event uint16_t DCAEVT2:1; // 4 Force DCAEVT2 event uint16_t DCBEVT1:1; // 5 Force DCBEVT1 event uint16_t DCBEVT2:1; // 6 Force DCBEVT2 event uint16_t rsvd2:9; // 15:7 reserved }; union TZEINT_REG { uint16_t all; struct TZEINT_BITS bit; }; //---------------------------------------------------- // Trip zone flag register bit definitions */ struct TZFLG_BITS { // bits description uint16_t INT:1; // 0 Global status uint16_t CBC:1; // 1 Trip Zones Cycle By Cycle Int uint16_t OST:1; // 2 Trip Zones One Shot Int uint16_t DCAEVT1:1; // 3 Force DCAEVT1 event uint16_t DCAEVT2:1; // 4 Force DCAEVT2 event uint16_t DCBEVT1:1; // 5 Force DCBEVT1 event uint16_t DCBEVT2:1; // 6 Force DCBEVT2 event uint16_t rsvd2:9; // 15:7 reserved }; union TZFLG_REG { uint16_t all; struct TZFLG_BITS bit; }; //---------------------------------------------------- // Trip zone flag clear register bit definitions */ struct TZCLR_BITS { // bits description uint16_t INT:1; // 0 Global status uint16_t CBC:1; // 1 Trip Zones Cycle By Cycle Int uint16_t OST:1; // 2 Trip Zones One Shot Int uint16_t DCAEVT1:1; // 3 Force DCAEVT1 event uint16_t DCAEVT2:1; // 4 Force DCAEVT2 event uint16_t DCBEVT1:1; // 5 Force DCBEVT1 event uint16_t DCBEVT2:1; // 6 Force DCBEVT2 event uint16_t rsvd2:9; // 15:7 reserved }; union TZCLR_REG { uint16_t all; struct TZCLR_BITS bit; }; //---------------------------------------------------- // Trip zone flag force register bit definitions */ struct TZFRC_BITS { // bits description uint16_t rsvd1:1; // 0 reserved uint16_t CBC:1; // 1 Trip Zones Cycle By Cycle Int uint16_t OST:1; // 2 Trip Zones One Shot Int uint16_t DCAEVT1:1; // 3 Force DCAEVT1 event uint16_t DCAEVT2:1; // 4 Force DCAEVT2 event uint16_t DCBEVT1:1; // 5 Force DCBEVT1 event uint16_t DCBEVT2:1; // 6 Force DCBEVT2 event uint16_t rsvd2:9; // 15:7 reserved }; union TZFRC_REG { uint16_t all; struct TZFRC_BITS bit; }; //---------------------------------------------------- // Event trigger select register bit definitions */ struct ETSEL_BITS { // bits description uint16_t INTSEL:3; // 2:0 EPWMxINTn Select uint16_t INTEN:1; // 3 EPWMxINTn Enable uint16_t rsvd1:4; // 7:4 reserved uint16_t SOCASEL:3; // 10:8 Start of conversion A Select uint16_t SOCAEN:1; // 11 Start of conversion A Enable uint16_t SOCBSEL:3; // 14:12 Start of conversion B Select uint16_t SOCBEN:1; // 15 Start of conversion B Enable }; union ETSEL_REG { uint16_t all; struct ETSEL_BITS bit; }; //---------------------------------------------------- // Event trigger pre-scale register bit definitions */ struct ETPS_BITS { // bits description uint16_t INTPRD:2; // 1:0 EPWMxINTn Period Select uint16_t INTCNT:2; // 3:2 EPWMxINTn Counter Register uint16_t rsvd1:4; // 7:4 reserved uint16_t SOCAPRD:2; // 9:8 EPWMxSOCA Period Select uint16_t SOCACNT:2; // 11:10 EPWMxSOCA Counter Register uint16_t SOCBPRD:2; // 13:12 EPWMxSOCB Period Select uint16_t SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register }; union ETPS_REG { uint16_t all; struct ETPS_BITS bit; }; //---------------------------------------------------- // Event trigger Flag register bit definitions */ struct ETFLG_BITS { // bits description uint16_t INT:1; // 0 EPWMxINTn Flag uint16_t rsvd1:1; // 1 reserved uint16_t SOCA:1; // 2 EPWMxSOCA Flag uint16_t SOCB:1; // 3 EPWMxSOCB Flag uint16_t rsvd2:12; // 15:4 reserved }; union ETFLG_REG { uint16_t all; struct ETFLG_BITS bit; }; //---------------------------------------------------- // Event trigger Clear register bit definitions */ struct ETCLR_BITS { // bits description uint16_t INT:1; // 0 EPWMxINTn Clear uint16_t rsvd1:1; // 1 reserved uint16_t SOCA:1; // 2 EPWMxSOCA Clear uint16_t SOCB:1; // 3 EPWMxSOCB Clear uint16_t rsvd2:12; // 15:4 reserved }; union ETCLR_REG { uint16_t all; struct ETCLR_BITS bit; }; //---------------------------------------------------- // Event trigger Force register bit definitions */ struct ETFRC_BITS { // bits description uint16_t INT:1; // 0 EPWMxINTn Force uint16_t rsvd1:1; // 1 reserved uint16_t SOCA:1; // 2 EPWMxSOCA Force uint16_t SOCB:1; // 3 EPWMxSOCB Force uint16_t rsvd2:12; // 15:4 reserved }; union ETFRC_REG { uint16_t all; struct ETFRC_BITS bit; }; //---------------------------------------------------- // PWM chopper control register bit definitions */ struct PCCTL_BITS { // bits description uint16_t CHPEN:1; // 0 PWM chopping enable uint16_t OSHTWTH:4; // 4:1 One-shot pulse width uint16_t CHPFREQ:3; // 7:5 Chopping clock frequency uint16_t CHPDUTY:3; // 10:8 Chopping clock Duty cycle uint16_t rsvd1:5; // 15:11 reserved }; union PCCTL_REG { uint16_t all; struct PCCTL_BITS bit; }; //---------------------------------------------------- // Enhanced Trip register bit definitions */ struct DCTRIPSEL_BITS { // bits description uint16_t DCAHCOMPSEL:4; // 3:0 Digital Compare A High, COMP Input Select uint16_t DCALCOMPSEL:4; // 7:4 Digital Compare A Low, COMP Input Select uint16_t DCBHCOMPSEL:4; // 11:8 Digital Compare B High, COMP Input Select uint16_t DCBLCOMPSEL:4; // 15:12 Digital Compare B Low, COMP Input Select }; union DCTRIPSEL_REG { uint16_t all; struct DCTRIPSEL_BITS bit; }; struct DCCTL_BITS { // bits description uint16_t EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal Select uint16_t EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Cynchronization Signal Select uint16_t EVT1SOCE:1; // 2 DCEVT1 SOC, Enable/Disable uint16_t EVT1SYNCE:1; // 3 DCEVT1 Sync, Enable/Disable uint16_t rsvd1:4; // 7:4 reserved uint16_t EVT2SRCSEL:1; // 8 DCEVT2 Source Signal Select uint16_t EVT2FRCSYNCSEL:1; // 9 DCEVT2 Force Synchronization Signal Select uint16_t rsvd2:6; // 15:10 reserved }; union DCCTL_REG { uint16_t all; struct DCCTL_BITS bit; }; struct DCCAPCTL_BITS { // bits description uint16_t CAPE:1; // 0 Counter Capture Enable/Disable uint16_t SHDWMODE:1; // 1 Counter Capture Mode uint16_t rsvd:14; // 15:2 reserved }; union DCCAPCTL_REG { uint16_t all; struct DCCAPCTL_BITS bit; }; struct DCFCTL_BITS { // bits description uint16_t SRCSEL:2; // 1:0 Filter Block Signal Source Select uint16_t BLANKE:1; // 2 Blanking Enable/Disable uint16_t BLANKINV:1; // 3 Blanking Window Inversion uint16_t PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment uint16_t rsvd:10; // 15:6 reserved }; union DCFCTL_REG { uint16_t all; struct DCFCTL_BITS bit; }; //---------------------------------------------------- // High resolution period control register bit definitions */ struct HRPCTL_BITS { // bits description uint16_t HRPE:1; // 0 High resolution period enable uint16_t PWMSYNCSEL:1; // 1 PWMSYNC Source Select Bit uint16_t TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable Bit uint16_t rsvd2:13; // 15:3 reserved }; union HRPCTL_REG { uint16_t all; struct HRPCTL_BITS bit; }; //---------------------------------------------------- // High Resolution Register bit definitions */ struct HRCNFG_BITS { // bits description uint16_t EDGMODE:2; // 1:0 Edge Mode select Bits uint16_t CTLMODE:1; // 2 Control mode Select Bit uint16_t HRLOAD:2; // 4:3 Shadow mode Select Bit uint16_t SELOUTB:1; // 5 EPWMB Output Select Bit uint16_t AUTOCONV:1; // 6 Autoconversion Bit uint16_t SWAPAB:1; // 7 Swap EPWMA & EPWMB Outputs Bit uint16_t rsvd1:8; // 15:8 reserved }; union HRCNFG_REG { uint16_t all; struct HRCNFG_BITS bit; }; struct HRPWR_BITS { // bits description uint16_t rsvd1:6; // 5:0 reserved uint16_t MEPOFF:4; // 9:6 MEP Calibration Off Bits uint16_t rsvd2:6; // 15:10 reserved }; union HRPWR_REG { uint16_t all; struct HRPWR_BITS bit; }; struct TBPHS_HRPWM_REG { // bits description uint16_t TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits) uint16_t TBPHS; // 31:16 Phase offset register }; union TBPHS_HRPWM_GROUP { uint32_t all; struct TBPHS_HRPWM_REG half; }; struct CMPA_HRPWM_REG { // bits description uint16_t CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) uint16_t CMPA; // 31:16 Compare A reg }; union CMPA_HRPWM_GROUP { uint32_t all; struct CMPA_HRPWM_REG half; }; struct TBPRD_HRPWM_REG { // bits description uint16_t TBPRDHR; // 15:0 Extension register for HRPWM Period (8 bits) uint16_t TBPRD; // 31:16 Timebase Period Register }; union TBPRD_HRPWM_GROUP { uint32_t all; struct TBPRD_HRPWM_REG half; }; struct EPWM_REGS { union TBCTL_REG TBCTL; // Time Base Control Register union TBSTS_REG TBSTS; // Time Base Status Register union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR uint16_t TBCTR; // Time Base Counter uint16_t TBPRD; // Time Base Period register set uint16_t TBPRDHR; // Time Base Period High Res Register union CMPCTL_REG CMPCTL; // Compare control union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR uint16_t CMPB; // Compare B reg union AQCTL_REG AQCTLA; // Action qual output A union AQCTL_REG AQCTLB; // Action qual output B union AQSFRC_REG AQSFRC; // Action qual SW force union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force union DBCTL_REG DBCTL; // Dead-band control uint16_t DBRED; // Dead-band rising edge delay uint16_t DBFED; // Dead-band falling edge delay union TZSEL_REG TZSEL; // Trip zone select union TZDCSEL_REG TZDCSEL; // Trip zone digital comparator select union TZCTL_REG TZCTL; // Trip zone control union TZEINT_REG TZEINT; // Trip zone interrupt enable union TZFLG_REG TZFLG; // Trip zone interrupt flags union TZCLR_REG TZCLR; // Trip zone clear union TZFRC_REG TZFRC; // Trip zone force interrupt union ETSEL_REG ETSEL; // Event trigger selection union ETPS_REG ETPS; // Event trigger pre-scaler union ETFLG_REG ETFLG; // Event trigger flags union ETCLR_REG ETCLR; // Event trigger clear union ETFRC_REG ETFRC; // Event trigger force union PCCTL_REG PCCTL; // PWM chopper control uint16_t rsvd3; union HRCNFG_REG HRCNFG; // HRPWM Config Reg union HRPWR_REG HRPWR; // HRPWM Power Register uint16_t rsvd4[4]; uint16_t HRMSTEP; // HRPWM MEP Step Register uint16_t rsvd5; union HRPCTL_REG HRPCTL; // High Resolution Period Control uint16_t rsvd6; union TBPRD_HRPWM_GROUP TBPRDM; // Union of TBPRD:TBPRDHR mirror registers union CMPA_HRPWM_GROUP CMPAM; // Union of CMPA:CMPAHR mirror registers uint16_t rsvd7[2]; union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select union DCCTL_REG DCACTL; // Digital Compare A Control union DCCTL_REG DCBCTL; // Digital Compare B Control union DCFCTL_REG DCFCTL; // Digital Compare Filter Control union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control uint16_t DCFOFFSET; // Digital Compare Filter Offset uint16_t DCFOFFSETCNT;// Digital Compare Filter Offset Counter uint16_t DCFWINDOW; // Digital Compare Filter Window uint16_t DCFWINDOWCNT;// Digital Compare Filter Window Counter uint16_t DCCAP; // Digital Compare Filter Counter Capture uint16_t rsvd8[6]; }; //--------------------------------------------------------------------------- // External References & Function Declarations: // extern volatile struct EPWM_REGS EPwm1Regs; extern volatile struct EPWM_REGS EPwm2Regs; extern volatile struct EPWM_REGS EPwm3Regs; extern volatile struct EPWM_REGS EPwm4Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_Gpio.h // // TITLE: F2802x General Purpose I/O Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //---------------------------------------------------- // GPIO A control register bit definitions */ struct GPACTRL_BITS { // bits description uint16_t QUALPRD0:8; // 7:0 Qual period uint16_t QUALPRD1:8; // 15:8 Qual period uint16_t QUALPRD2:8; // 23:16 Qual period uint16_t QUALPRD3:8; // 31:24 Qual period }; union GPACTRL_REG { uint32_t all; struct GPACTRL_BITS bit; }; //---------------------------------------------------- // GPIO B control register bit definitions */ struct GPBCTRL_BITS { // bits description uint16_t QUALPRD0:8; // 7:0 Qual period uint16_t rsvd1:8; // 15:8 reserved uint16_t rsvd2:16; // 31:16 reserved }; union GPBCTRL_REG { uint32_t all; struct GPBCTRL_BITS bit; }; //---------------------------------------------------- // GPIO Qual/MUX select register bit definitions */ struct GPA1_BITS { // bits description uint16_t GPIO0:2; // 1:0 GPIO0 uint16_t GPIO1:2; // 3:2 GPIO1 uint16_t GPIO2:2; // 5:4 GPIO2 uint16_t GPIO3:2; // 7:6 GPIO3 uint16_t GPIO4:2; // 9:8 GPIO4 uint16_t GPIO5:2; // 11:10 GPIO5 uint16_t GPIO6:2; // 13:12 GPIO6 uint16_t GPIO7:2; // 15:14 GPIO7 uint16_t GPIO8:2; // 17:16 GPIO8 uint16_t GPIO9:2; // 19:18 GPIO9 uint16_t GPIO10:2; // 21:20 GPIO10 uint16_t GPIO11:2; // 23:22 GPIO11 uint16_t GPIO12:2; // 25:24 GPIO12 uint16_t GPIO13:2; // 27:26 GPIO13 uint16_t GPIO14:2; // 29:28 GPIO14 uint16_t GPIO15:2; // 31:30 GPIO15 }; struct GPA2_BITS { // bits description uint16_t GPIO16:2; // 1:0 GPIO16 uint16_t GPIO17:2; // 3:2 GPIO17 uint16_t GPIO18:2; // 5:4 GPIO18 uint16_t GPIO19:2; // 7:6 GPIO19 uint16_t GPIO20:2; // 9:8 GPIO20 uint16_t GPIO21:2; // 11:10 GPIO21 uint16_t GPIO22:2; // 13:12 GPIO22 uint16_t GPIO23:2; // 15:14 GPIO23 uint16_t GPIO24:2; // 17:16 GPIO24 uint16_t GPIO25:2; // 19:18 GPIO25 uint16_t GPIO26:2; // 21:20 GPIO26 uint16_t GPIO27:2; // 23:22 GPIO27 uint16_t GPIO28:2; // 25:24 GPIO28 uint16_t GPIO29:2; // 27:26 GPIO29 uint16_t GPIO30:2; // 29:28 GPIO30 uint16_t GPIO31:2; // 31:30 GPIO31 }; struct GPB1_BITS { // bits description uint16_t GPIO32:2; // 1:0 GPIO32 uint16_t GPIO33:2; // 3:2 GPIO33 uint16_t GPIO34:2; // 5:4 GPIO34 uint16_t GPIO35:2; // 7:6 GPIO35 uint16_t GPIO36:2; // 9:8 GPIO36 uint16_t GPIO37:2; // 11:10 GPIO37 uint16_t GPIO38:2; // 13:12 GPIO38 uint16_t rsvd1:2; // 15:14 reserved uint16_t rsvd2:16; // 31:16 reserved }; struct AIO_BITS { // bits description uint16_t rsvd1:2; // 1:0 GPIO0 uint16_t rsvd2:2; // 3:2 GPIO1 uint16_t AIO2:2; // 5:4 GPIO2 uint16_t rsvd3:2; // 7:6 GPIO3 uint16_t AIO4:2; // 9:8 GPIO4 uint16_t rsvd4:2; // 11:10 GPIO5 uint16_t AIO6:2; // 13:12 GPIO6 uint16_t rsvd5:2; // 15:14 GPIO7 uint16_t rsvd6:2; // 17:16 GPIO8 uint16_t rsvd7:2; // 19:18 GPIO9 uint16_t AIO10:2; // 21:20 GPIO10 uint16_t rsvd8:2; // 23:22 GPIO11 uint16_t AIO12:2; // 25:24 GPIO12 uint16_t rsvd9:2; // 27:26 GPIO13 uint16_t AIO14:2; // 29:28 GPIO14 uint16_t rsvd10:2; // 31:30 GPIO15 }; union GPA1_REG { uint32_t all; struct GPA1_BITS bit; }; union GPA2_REG { uint32_t all; struct GPA2_BITS bit; }; union GPB1_REG { uint32_t all; struct GPB1_BITS bit; }; union AIO_REG { uint32_t all; struct AIO_BITS bit; }; //---------------------------------------------------- // GPIO DIR/TOGGLE/SET/CLEAR register bit definitions */ struct GPADAT_BITS { // bits description uint16_t GPIO0:1; // 0 GPIO0 uint16_t GPIO1:1; // 1 GPIO1 uint16_t GPIO2:1; // 2 GPIO2 uint16_t GPIO3:1; // 3 GPIO3 uint16_t GPIO4:1; // 4 GPIO4 uint16_t GPIO5:1; // 5 GPIO5 uint16_t GPIO6:1; // 6 GPIO6 uint16_t GPIO7:1; // 7 GPIO7 uint16_t GPIO8:1; // 8 GPIO8 uint16_t GPIO9:1; // 9 GPIO9 uint16_t GPIO10:1; // 10 GPIO10 uint16_t GPIO11:1; // 11 GPIO11 uint16_t GPIO12:1; // 12 GPIO12 uint16_t GPIO13:1; // 13 GPIO13 uint16_t GPIO14:1; // 14 GPIO14 uint16_t GPIO15:1; // 15 GPIO15 uint16_t GPIO16:1; // 16 GPIO16 uint16_t GPIO17:1; // 17 GPIO17 uint16_t GPIO18:1; // 18 GPIO18 uint16_t GPIO19:1; // 19 GPIO19 uint16_t GPIO20:1; // 20 GPIO20 uint16_t GPIO21:1; // 21 GPIO21 uint16_t GPIO22:1; // 22 GPIO22 uint16_t GPIO23:1; // 23 GPIO23 uint16_t GPIO24:1; // 24 GPIO24 uint16_t GPIO25:1; // 25 GPIO25 uint16_t GPIO26:1; // 26 GPIO26 uint16_t GPIO27:1; // 27 GPIO27 uint16_t GPIO28:1; // 28 GPIO28 uint16_t GPIO29:1; // 29 GPIO29 uint16_t GPIO30:1; // 30 GPIO30 uint16_t GPIO31:1; // 31 GPIO31 }; struct GPBDAT_BITS { // bits description uint16_t GPIO32:1; // 0 GPIO32 uint16_t GPIO33:1; // 1 GPIO33 uint16_t GPIO34:1; // 2 GPIO34 uint16_t GPIO35:1; // 3 GPIO35 uint16_t GPIO36:1; // 4 GPIO36 uint16_t GPIO37:1; // 5 GPIO37 uint16_t GPIO38:1; // 6 GPIO38 uint16_t rsvd1:9; // 15:7 reserved uint16_t rsvd2:16; // 31:16 reserved }; struct AIODAT_BITS { // bits description uint16_t rsvd1:1; // 0 reserved uint16_t rsvd2:1; // 1 reserved uint16_t AIO2:1; // 2 AIO2 uint16_t rsvd3:1; // 3 reserved uint16_t AIO4:1; // 4 AIO4 uint16_t rsvd4:1; // 5 reserved uint16_t AIO6:1; // 6 AIO6 uint16_t rsvd5:1; // 7 reserved uint16_t rsvd6:1; // 8 reserved uint16_t rsvd7:1; // 9 reserved uint16_t AIO10:1; // 10 AIO10 uint16_t rsvd8:1; // 11 reserved uint16_t AIO12:1; // 12 AIO12 uint16_t rsvd9:1; // 13 reserved uint16_t AIO14:1; // 14 AIO14 uint16_t rsvd10:1; // 15 reserved }; union GPADAT_REG { uint32_t all; struct GPADAT_BITS bit; }; union GPBDAT_REG { uint32_t all; struct GPBDAT_BITS bit; }; union AIODAT_REG { uint16_t all; struct AIODAT_BITS bit; }; //---------------------------------------------------------------- // GPIO XINT1/XINT2/XNMI/XCLKIN select register bit definitions */ struct GPIOXINT_BITS { // bits description uint16_t GPIOSEL:5; // 4:0 Select GPIO interrupt input source uint16_t rsvd1:11; // 15:5 reserved }; union GPIOXINT_REG { uint16_t all; struct GPIOXINT_BITS bit; }; struct GPIO_CTRL_REGS { union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) uint32_t rsvd1; // reserved union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 38) union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 38) uint32_t rsvd2; // reserved union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 38) uint32_t rsvd3; // reserved union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 38) union GPBDAT_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 38) uint16_t rsvd4[24]; // reserved union AIO_REG AIOMUX1; // Analog IO Mux 1 Register (AIO0 to 15) uint32_t rsvd5; // reserved union AIODAT_REG AIODIR; // Analog IO Direction Register (AIO0 to 15) uint16_t rsvd6[5]; // reserved }; struct GPIO_DATA_REGS { union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31) union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31) union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31) union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 38) union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 38) union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 38) union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 38) uint16_t rsvd1[8]; // reserved union AIODAT_REG AIODAT; // Analog IO Data Register (AIO0-15) uint16_t rsvd2; union AIODAT_REG AIOSET; // Analog IO Data Set Register (AIO0-15) uint16_t rsvd3; union AIODAT_REG AIOCLEAR; // Analog IO Data Clear Register (AIO0-15) uint16_t rsvd4; union AIODAT_REG AIOTOGGLE; // Analog IO Data Toggle Register (AIO0-15) uint16_t rsvd5; }; struct GPIO_INT_REGS { union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO Input Selection uint16_t rsvd1[5]; union GPADAT_REG GPIOLPMSEL; // Low power modes GPIO input select }; //--------------------------------------------------------------------------- // GPI/O External References & Function Declarations: // extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; extern volatile struct GPIO_DATA_REGS GpioDataRegs; extern volatile struct GPIO_INT_REGS GpioIntRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_I2c.h // // TITLE: F2802x Inter-Integrated Circuit (I2C) Module // Register Bit Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //---------------------------------------------------- // I2C interrupt vector register bit definitions */ struct I2CISRC_BITS { // bits description uint16_t INTCODE:3; // 2:0 Interrupt code uint16_t rsvd1:13; // 15:3 reserved }; union I2CISRC_REG { uint16_t all; struct I2CISRC_BITS bit; }; //---------------------------------------------------- // I2C interrupt mask register bit definitions */ struct I2CIER_BITS { // bits description uint16_t ARBL:1; // 0 Arbitration lost interrupt uint16_t NACK:1; // 1 No ack interrupt uint16_t ARDY:1; // 2 Register access ready interrupt uint16_t RRDY:1; // 3 Recieve data ready interrupt uint16_t XRDY:1; // 4 Transmit data ready interrupt uint16_t SCD:1; // 5 Stop condition detection uint16_t AAS:1; // 6 Address as slave uint16_t rsvd:9; // 15:7 reserved }; union I2CIER_REG { uint16_t all; struct I2CIER_BITS bit; }; //---------------------------------------------------- // I2C status register bit definitions */ struct I2CSTR_BITS { // bits description uint16_t ARBL:1; // 0 Arbitration lost interrupt uint16_t NACK:1; // 1 No ack interrupt uint16_t ARDY:1; // 2 Register access ready interrupt uint16_t RRDY:1; // 3 Recieve data ready interrupt uint16_t XRDY:1; // 4 Transmit data ready interrupt uint16_t SCD:1; // 5 Stop condition detection uint16_t rsvd1:2; // 7:6 reserved uint16_t AD0:1; // 8 Address Zero uint16_t AAS:1; // 9 Address as slave uint16_t XSMT:1; // 10 XMIT shift empty uint16_t RSFULL:1; // 11 Recieve shift full uint16_t BB:1; // 12 Bus busy uint16_t NACKSNT:1; // 13 A no ack sent uint16_t SDIR:1; // 14 Slave direction uint16_t rsvd2:1; // 15 reserved }; union I2CSTR_REG { uint16_t all; struct I2CSTR_BITS bit; }; //---------------------------------------------------- // I2C mode control register bit definitions */ struct I2CMDR_BITS { // bits description uint16_t BC:3; // 2:0 Bit count uint16_t FDF:1; // 3 Free data format uint16_t STB:1; // 4 Start byte uint16_t IRS:1; // 5 I2C Reset not uint16_t DLB:1; // 6 Digital loopback uint16_t RM:1; // 7 Repeat mode uint16_t XA:1; // 8 Expand address uint16_t TRX:1; // 9 Transmitter/reciever uint16_t MST:1; // 10 Master/slave uint16_t STP:1; // 11 Stop condition uint16_t rsvd1:1; // 12 reserved uint16_t STT:1; // 13 Start condition uint16_t FREE:1; // 14 Emulation mode uint16_t NACKMOD:1; // 15 No Ack mode }; union I2CMDR_REG { uint16_t all; struct I2CMDR_BITS bit; }; //---------------------------------------------------- // I2C extended mode control register bit definitions */ struct I2CEMDR_BITS { // bits description uint16_t BCM:1; // 0 Bit count uint16_t rsvd1:15; // 15:1 reserved }; union I2CEMDR_REG { uint16_t all; struct I2CEMDR_BITS bit; }; //---------------------------------------------------- // I2C pre-scaler register bit definitions */ struct I2CPSC_BITS { // bits description uint16_t IPSC:8; // 7:0 pre-scaler uint16_t rsvd1:8; // 15:8 reserved }; union I2CPSC_REG { uint16_t all; struct I2CPSC_BITS bit; }; //---------------------------------------------------- // TX FIFO control register bit definitions */ struct I2CFFTX_BITS { // bits description uint16_t TXFFIL:5; // 4:0 FIFO interrupt level uint16_t TXFFIENA:1; // 5 FIFO interrupt enable/disable uint16_t TXFFINTCLR:1; // 6 FIFO clear uint16_t TXFFINT:1; // 7 FIFO interrupt flag uint16_t TXFFST:5; // 12:8 FIFO level status uint16_t TXFFRST:1; // 13 FIFO reset uint16_t I2CFFEN:1; // 14 enable/disable TX & RX FIFOs uint16_t rsvd1:1; // 15 reserved }; union I2CFFTX_REG { uint16_t all; struct I2CFFTX_BITS bit; }; //---------------------------------------------------- // RX FIFO control register bit definitions */ struct I2CFFRX_BITS { // bits description uint16_t RXFFIL:5; // 4:0 FIFO interrupt level uint16_t RXFFIENA:1; // 5 FIFO interrupt enable/disable uint16_t RXFFINTCLR:1; // 6 FIFO clear uint16_t RXFFINT:1; // 7 FIFO interrupt flag uint16_t RXFFST:5; // 12:8 FIFO level uint16_t RXFFRST:1; // 13 FIFO reset uint16_t rsvd1:2; // 15:14 reserved }; union I2CFFRX_REG { uint16_t all; struct I2CFFRX_BITS bit; }; //---------------------------------------------------- struct I2C_REGS { uint16_t I2COAR; // Own address register union I2CIER_REG I2CIER; // Interrupt enable union I2CSTR_REG I2CSTR; // Interrupt status uint16_t I2CCLKL; // Clock divider low uint16_t I2CCLKH; // Clock divider high uint16_t I2CCNT; // Data count uint16_t I2CDRR; // Data recieve uint16_t I2CSAR; // Slave address uint16_t I2CDXR; // Data transmit union I2CMDR_REG I2CMDR; // Mode union I2CISRC_REG I2CISRC; // Interrupt source union I2CEMDR_REG I2CEMDR; // Extended mode union I2CPSC_REG I2CPSC; // Pre-scaler uint16_t rsvd2[19]; // reserved union I2CFFTX_REG I2CFFTX; // Transmit FIFO union I2CFFRX_REG I2CFFRX; // Recieve FIFO }; //--------------------------------------------------------------------------- // External References & Function Declarations: // extern volatile struct I2C_REGS I2caRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_NmiIntrupt.h // // TITLE: F2802x Device NMI Interrupt Register Definitions // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //=========================================================================== // NMI Interrupt Register Bit Definitions // struct NMICFG_BITS { // bits description uint16_t rsvd1:1; // 0 reserved uint16_t CLOCKFAIL:1; // 1 Fail Interrupt Enable Bits uint16_t rsvd2:14; // 15:02 reserved }; union NMICFG_REG { uint16_t all; struct NMICFG_BITS bit; }; struct NMIFLG_BITS { // bits description uint16_t NMIINT:1; // 0 NMI Interrupt Flag uint16_t CLOCKFAIL:1; // 1 Clock Fail Interrupt Flags uint16_t rsvd1:14; // 15:02 reserved }; union NMIFLG_REG { uint16_t all; struct NMIFLG_BITS bit; }; struct NMIFLGCLR_BITS { // bits description uint16_t NMIINT:1; // 0 NMIINT Flag Clear Bit uint16_t CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear Bit uint16_t rsvd1:14; // 15:02 reserved }; union NMIFLGCLR_REG { uint16_t all; struct NMIFLGCLR_BITS bit; }; struct NMIFLGFRC_BITS { // bits description uint16_t rsvd1:1; // 0 reserved uint16_t CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force Bit uint16_t rsvd2:14; // 15:02 reserved }; union NMIFLGFRC_REG { uint16_t all; struct NMIFLGFRC_BITS bit; }; //=========================================================================== // NMI Interrupt Register Definitions // struct NMIINTRUPT_REGS { union NMICFG_REG NMICFG; union NMIFLG_REG NMIFLG; union NMIFLGCLR_REG NMIFLGCLR; union NMIFLGFRC_REG NMIFLGFRC; uint16_t NMIWDCNT; uint16_t NMIWDPRD; uint16_t rsvd1[10]; }; //=========================================================================== // NMI Interrupt External References and Function Declarations // extern volatile struct NMIINTRUPT_REGS NmiIntruptRegs; //=========================================================================== // End of file //=========================================================================== //########################################################################### // // FILE: F2802x_PieCtrl.h // // TITLE: F2802x Device PIE Control Register Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // PIE Control Register Bit Definitions: // // PIECTRL: Register bit definitions: struct PIECTRL_BITS { // bits description uint16_t ENPIE:1; // 0 Enable PIE block uint16_t PIEVECT:15; // 15:1 Fetched vector address }; union PIECTRL_REG { uint16_t all; struct PIECTRL_BITS bit; }; // PIEIER: Register bit definitions: struct PIEIER_BITS { // bits description uint16_t INTx1:1; // 0 INTx.1 uint16_t INTx2:1; // 1 INTx.2 uint16_t INTx3:1; // 2 INTx.3 uint16_t INTx4:1; // 3 INTx.4 uint16_t INTx5:1; // 4 INTx.5 uint16_t INTx6:1; // 5 INTx.6 uint16_t INTx7:1; // 6 INTx.7 uint16_t INTx8:1; // 7 INTx.8 uint16_t rsvd:8; // 15:8 reserved }; union PIEIER_REG { uint16_t all; struct PIEIER_BITS bit; }; // PIEIFR: Register bit definitions: struct PIEIFR_BITS { // bits description uint16_t INTx1:1; // 0 INTx.1 uint16_t INTx2:1; // 1 INTx.2 uint16_t INTx3:1; // 2 INTx.3 uint16_t INTx4:1; // 3 INTx.4 uint16_t INTx5:1; // 4 INTx.5 uint16_t INTx6:1; // 5 INTx.6 uint16_t INTx7:1; // 6 INTx.7 uint16_t INTx8:1; // 7 INTx.8 uint16_t rsvd:8; // 15:8 reserved }; union PIEIFR_REG { uint16_t all; struct PIEIFR_BITS bit; }; // PIEACK: Register bit definitions: struct PIEACK_BITS { // bits description uint16_t ACK1:1; // 0 Acknowledge PIE interrupt group 1 uint16_t ACK2:1; // 1 Acknowledge PIE interrupt group 2 uint16_t ACK3:1; // 2 Acknowledge PIE interrupt group 3 uint16_t ACK4:1; // 3 Acknowledge PIE interrupt group 4 uint16_t ACK5:1; // 4 Acknowledge PIE interrupt group 5 uint16_t ACK6:1; // 5 Acknowledge PIE interrupt group 6 uint16_t ACK7:1; // 6 Acknowledge PIE interrupt group 7 uint16_t ACK8:1; // 7 Acknowledge PIE interrupt group 8 uint16_t ACK9:1; // 8 Acknowledge PIE interrupt group 9 uint16_t ACK10:1; // 9 Acknowledge PIE interrupt group 10 uint16_t ACK11:1; // 10 Acknowledge PIE interrupt group 11 uint16_t ACK12:1; // 11 Acknowledge PIE interrupt group 12 uint16_t rsvd:4; // 15:12 reserved }; union PIEACK_REG { uint16_t all; struct PIEACK_BITS bit; }; //--------------------------------------------------------------------------- // PIE Control Register File: // struct PIE_CTRL_REGS { union PIECTRL_REG PIECTRL; // PIE control register union PIEACK_REG PIEACK; // PIE acknowledge union PIEIER_REG PIEIER1; // PIE INT1 IER register union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register union PIEIER_REG PIEIER2; // PIE INT2 IER register union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register union PIEIER_REG PIEIER3; // PIE INT3 IER register union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register union PIEIER_REG PIEIER4; // PIE INT4 IER register union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register union PIEIER_REG PIEIER5; // PIE INT5 IER register union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register union PIEIER_REG PIEIER6; // PIE INT6 IER register union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register union PIEIER_REG PIEIER7; // PIE INT7 IER register union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register union PIEIER_REG PIEIER8; // PIE INT8 IER register union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register union PIEIER_REG PIEIER9; // PIE INT9 IER register union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register union PIEIER_REG PIEIER10; // PIE INT10 IER register union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register union PIEIER_REG PIEIER11; // PIE INT11 IER register union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register union PIEIER_REG PIEIER12; // PIE INT12 IER register union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register }; //--------------------------------------------------------------------------- // PIE Control Registers External References & Function Declarations: // extern volatile struct PIE_CTRL_REGS PieCtrlRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_PieVect.h // // TITLE: F2802x Devices PIE Vector Table Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // PIE Interrupt Vector Table Definition: // // Create a user type called PINT (pointer to interrupt): typedef interrupt void(*PINT)(void); // Define Vector Table: struct PIE_VECT_TABLE { // Reset is never fetched from this table. // It will always be fetched from 0x3FFFC0 in // boot ROM PINT PIE1_RESERVED; PINT PIE2_RESERVED; PINT PIE3_RESERVED; PINT PIE4_RESERVED; PINT PIE5_RESERVED; PINT PIE6_RESERVED; PINT PIE7_RESERVED; PINT PIE8_RESERVED; PINT PIE9_RESERVED; PINT PIE10_RESERVED; PINT PIE11_RESERVED; PINT PIE12_RESERVED; PINT PIE13_RESERVED; // Non-Peripheral Interrupts: PINT TINT1; // CPU-Timer1 PINT TINT2; // CPU-Timer2 PINT DATALOG; // Datalogging interrupt PINT RTOSINT; // RTOS interrupt PINT EMUINT; // Emulation interrupt PINT NMI; // Non-maskable interrupt PINT ILLEGAL; // Illegal operation TRAP PINT USER1; // User Defined trap 1 PINT USER2; // User Defined trap 2 PINT USER3; // User Defined trap 3 PINT USER4; // User Defined trap 4 PINT USER5; // User Defined trap 5 PINT USER6; // User Defined trap 6 PINT USER7; // User Defined trap 7 PINT USER8; // User Defined trap 8 PINT USER9; // User Defined trap 9 PINT USER10; // User Defined trap 10 PINT USER11; // User Defined trap 11 PINT USER12; // User Defined trap 12 // Group 1 PIE Peripheral Vectors: PINT ADCINT1; // ADC - if Group 10 ADCINT1 is enabled, this must be rsvd1_1 PINT ADCINT2; // ADC - if Group 10 ADCINT2 is enabled, this must be rsvd1_2 PINT rsvd1_3; PINT XINT1; PINT XINT2; PINT ADCINT9; // ADC PINT TINT0; // Timer 0 PINT WAKEINT; // WD // Group 2 PIE Peripheral Vectors: PINT EPWM1_TZINT; // EPWM-1 PINT EPWM2_TZINT; // EPWM-2 PINT EPWM3_TZINT; // EPWM-3 PINT EPWM4_TZINT; // EPWM-4 PINT rsvd2_5; PINT rsvd2_6; PINT rsvd2_7; PINT rsvd2_8; // Group 3 PIE Peripheral Vectors: PINT EPWM1_INT; // EPWM-1 PINT EPWM2_INT; // EPWM-2 PINT EPWM3_INT; // EPWM-3 PINT EPWM4_INT; // EPWM-4 PINT rsvd3_5; PINT rsvd3_6; PINT rsvd3_7; PINT rsvd3_8; // Group 4 PIE Peripheral Vectors: PINT ECAP1_INT; // ECAP-1 PINT rsvd4_2; PINT rsvd4_3; PINT rsvd4_4; PINT rsvd4_5; PINT rsvd4_6; PINT rsvd4_7; PINT rsvd4_8; // Group 5 PIE Peripheral Vectors: PINT rsvd5_1; PINT rsvd5_2; PINT rsvd5_3; PINT rsvd5_4; PINT rsvd5_5; PINT rsvd5_6; PINT rsvd5_7; PINT rsvd5_8; // Group 6 PIE Peripheral Vectors: PINT SPIRXINTA; // SPI-A PINT SPITXINTA; // SPI-A PINT rsvd6_3; PINT rsvd6_4; PINT rsvd6_5; PINT rsvd6_6; PINT rsvd6_7; PINT rsvd6_8; // Group 7 PIE Peripheral Vectors: PINT rsvd7_1; PINT rsvd7_2; PINT rsvd7_3; PINT rsvd7_4; PINT rsvd7_5; PINT rsvd7_6; PINT rsvd7_7; PINT rsvd7_8; // Group 8 PIE Peripheral Vectors: PINT I2CINT1A; // I2C-A PINT I2CINT2A; // I2C-A PINT rsvd8_3; PINT rsvd8_4; PINT rsvd8_5; PINT rsvd8_6; PINT rsvd8_7; PINT rsvd8_8; // Group 9 PIE Peripheral Vectors: PINT SCIRXINTA; // SCI-A PINT SCITXINTA; // SCI-A PINT rsvd9_3; PINT rsvd9_4; PINT rsvd9_5; PINT rsvd9_6; PINT rsvd9_7; PINT rsvd9_8; // Group 10 PIE Peripheral Vectors: PINT rsvd10_1; // Can be ADCINT1, but must make ADCINT1 in Group 1 space "reserved". PINT rsvd10_2; // Can be ADCINT2, but must make ADCINT2 in Group 1 space "reserved". PINT ADCINT3; // ADC PINT ADCINT4; // ADC PINT ADCINT5; // ADC PINT ADCINT6; // ADC PINT ADCINT7; // ADC PINT ADCINT8; // ADC // Group 11 PIE Peripheral Vectors: PINT rsvd11_1; PINT rsvd11_2; PINT rsvd11_3; PINT rsvd11_4; PINT rsvd11_5; PINT rsvd11_6; PINT rsvd11_7; PINT rsvd11_8; // Group 12 PIE Peripheral Vectors: PINT XINT3; PINT rsvd12_2; PINT rsvd12_3; PINT rsvd12_4; PINT rsvd12_5; PINT rsvd12_6; PINT rsvd12_7; PINT rsvd12_8; }; //--------------------------------------------------------------------------- // PIE Interrupt Vector Table External References & Function Declarations: // extern volatile struct PIE_VECT_TABLE PieVectTable; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_Spi.h // // TITLE: F2802x Device SPI Register Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // SPI Individual Register Bit Definitions: // // SPI FIFO Transmit register bit definitions: struct SPIFFTX_BITS { // bit description uint16_t TXFFIL:5; // 4:0 Interrupt level uint16_t TXFFIENA:1; // 5 Interrupt enable uint16_t TXFFINTCLR:1; // 6 Clear INT flag uint16_t TXFFINT:1; // 7 INT flag uint16_t TXFFST:5; // 12:8 FIFO status uint16_t TXFIFO:1; // 13 FIFO reset uint16_t SPIFFENA:1; // 14 Enhancement enable uint16_t SPIRST:1; // 15 Reset SPI }; union SPIFFTX_REG { uint16_t all; struct SPIFFTX_BITS bit; }; //-------------------------------------------- // SPI FIFO recieve register bit definitions: // // struct SPIFFRX_BITS { // bits description uint16_t RXFFIL:5; // 4:0 Interrupt level uint16_t RXFFIENA:1; // 5 Interrupt enable uint16_t RXFFINTCLR:1; // 6 Clear INT flag uint16_t RXFFINT:1; // 7 INT flag uint16_t RXFFST:5; // 12:8 FIFO status uint16_t RXFIFORESET:1; // 13 FIFO reset uint16_t RXFFOVFCLR:1; // 14 Clear overflow uint16_t RXFFOVF:1; // 15 FIFO overflow }; union SPIFFRX_REG { uint16_t all; struct SPIFFRX_BITS bit; }; //-------------------------------------------- // SPI FIFO control register bit definitions: // // struct SPIFFCT_BITS { // bits description uint16_t TXDLY:8; // 7:0 FIFO transmit delay uint16_t rsvd:8; // 15:8 reserved }; union SPIFFCT_REG { uint16_t all; struct SPIFFCT_BITS bit; }; //--------------------------------------------- // SPI configuration register bit definitions: // // struct SPICCR_BITS { // bits description uint16_t SPICHAR:4; // 3:0 Character length control uint16_t SPILBK:1; // 4 Loop-back enable/disable uint16_t rsvd1:1; // 5 reserved uint16_t CLKPOLARITY:1; // 6 Clock polarity uint16_t SPISWRESET:1; // 7 SPI SW Reset uint16_t rsvd2:8; // 15:8 reserved }; union SPICCR_REG { uint16_t all; struct SPICCR_BITS bit; }; //------------------------------------------------- // SPI operation control register bit definitions: // // struct SPICTL_BITS { // bits description uint16_t SPIINTENA:1; // 0 Interrupt enable uint16_t TALK:1; // 1 Master/Slave transmit enable uint16_t MASTER_SLAVE:1; // 2 Network control mode uint16_t CLK_PHASE:1; // 3 Clock phase select uint16_t OVERRUNINTENA:1; // 4 Overrun interrupt enable uint16_t rsvd:11; // 15:5 reserved }; union SPICTL_REG { uint16_t all; struct SPICTL_BITS bit; }; //-------------------------------------- // SPI status register bit definitions: // // struct SPISTS_BITS { // bits description uint16_t rsvd1:5; // 4:0 reserved uint16_t BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag uint16_t INT_FLAG:1; // 6 SPI interrupt flag uint16_t OVERRUN_FLAG:1; // 7 SPI reciever overrun flag uint16_t rsvd2:8; // 15:8 reserved }; union SPISTS_REG { uint16_t all; struct SPISTS_BITS bit; }; //------------------------------------------------ // SPI priority control register bit definitions: // // struct SPIPRI_BITS { // bits description uint16_t TRIWIRE:1; // 0 3-wire mode select bit uint16_t rsvd1:3; // 3:1 reserved uint16_t FREE:1; // 4 Free emulation mode control uint16_t SOFT:1; // 5 Soft emulation mode control uint16_t PRIORITY:1; // 6 Interrupt priority select uint16_t rsvd2:9; // 15:7 reserved }; union SPIPRI_REG { uint16_t all; struct SPIPRI_BITS bit; }; //--------------------------------------------------------------------------- // SPI Register File: // struct SPI_REGS { union SPICCR_REG SPICCR; // Configuration register union SPICTL_REG SPICTL; // Operation control register union SPISTS_REG SPISTS; // Status register uint16_t rsvd1; // reserved uint16_t SPIBRR; // Baud Rate uint16_t rsvd2; // reserved uint16_t SPIRXEMU; // Emulation buffer uint16_t SPIRXBUF; // Serial input buffer uint16_t SPITXBUF; // Serial output buffer uint16_t SPIDAT; // Serial data union SPIFFTX_REG SPIFFTX; // FIFO transmit register union SPIFFRX_REG SPIFFRX; // FIFO recieve register union SPIFFCT_REG SPIFFCT; // FIFO control register uint16_t rsvd3[2]; // reserved union SPIPRI_REG SPIPRI; // FIFO Priority control }; //--------------------------------------------------------------------------- // SPI External References & Function Declarations: // extern volatile struct SPI_REGS SpiaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_Sci.h // // TITLE: F2802x Device SCI Register Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // SCI Individual Register Bit Definitions //---------------------------------------------------------- // SCICCR communication control register bit definitions: // struct SCICCR_BITS { // bit description uint16_t SCICHAR:3; // 2:0 Character length control uint16_t ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control uint16_t LOOPBKENA:1; // 4 Loop Back enable uint16_t PARITYENA:1; // 5 Parity enable uint16_t PARITY:1; // 6 Even or Odd Parity uint16_t STOPBITS:1; // 7 Number of Stop Bits uint16_t rsvd1:8; // 15:8 reserved }; union SCICCR_REG { uint16_t all; struct SCICCR_BITS bit; }; //------------------------------------------- // SCICTL1 control register 1 bit definitions: // struct SCICTL1_BITS { // bit description uint16_t RXENA:1; // 0 SCI receiver enable uint16_t TXENA:1; // 1 SCI transmitter enable uint16_t SLEEP:1; // 2 SCI sleep uint16_t TXWAKE:1; // 3 Transmitter wakeup method uint16_t rsvd:1; // 4 reserved uint16_t SWRESET:1; // 5 Software reset uint16_t RXERRINTENA:1; // 6 Recieve interrupt enable uint16_t rsvd1:9; // 15:7 reserved }; union SCICTL1_REG { uint16_t all; struct SCICTL1_BITS bit; }; //--------------------------------------------- // SCICTL2 control register 2 bit definitions: // struct SCICTL2_BITS { // bit description uint16_t TXINTENA:1; // 0 Transmit interrupt enable uint16_t RXBKINTENA:1; // 1 Receiver-buffer break enable uint16_t rsvd:4; // 5:2 reserved uint16_t TXEMPTY:1; // 6 Transmitter empty flag uint16_t TXRDY:1; // 7 Transmitter ready flag uint16_t rsvd1:8; // 15:8 reserved }; union SCICTL2_REG { uint16_t all; struct SCICTL2_BITS bit; }; //--------------------------------------------------- // SCIRXST Receiver status register bit definitions: // struct SCIRXST_BITS { // bit description uint16_t rsvd:1; // 0 reserved uint16_t RXWAKE:1; // 1 Receiver wakeup detect flag uint16_t PE:1; // 2 Parity error flag uint16_t OE:1; // 3 Overrun error flag uint16_t FE:1; // 4 Framing error flag uint16_t BRKDT:1; // 5 Break-detect flag uint16_t RXRDY:1; // 6 Receiver ready flag uint16_t RXERROR:1; // 7 Receiver error flag }; union SCIRXST_REG { uint16_t all; struct SCIRXST_BITS bit; }; //---------------------------------------------------- // SCIRXBUF Receiver Data Buffer with FIFO bit definitions: // struct SCIRXBUF_BITS { // bits description uint16_t RXDT:8; // 7:0 Receive word uint16_t rsvd:6; // 13:8 reserved uint16_t SCIFFPE:1; // 14 SCI PE error in FIFO mode uint16_t SCIFFFE:1; // 15 SCI FE error in FIFO mode }; union SCIRXBUF_REG { uint16_t all; struct SCIRXBUF_BITS bit; }; //-------------------------------------------------- // SCIPRI Priority control register bit definitions: // // struct SCIPRI_BITS { // bit description uint16_t rsvd:3; // 2:0 reserved uint16_t FREE:1; // 3 Free emulation suspend mode uint16_t SOFT:1; // 4 Soft emulation suspend mode uint16_t rsvd1:3; // 7:5 reserved }; union SCIPRI_REG { uint16_t all; struct SCIPRI_BITS bit; }; //------------------------------------------------- // SCI FIFO Transmit register bit definitions: // // struct SCIFFTX_BITS { // bit description uint16_t TXFFIL:5; // 4:0 Interrupt level uint16_t TXFFIENA:1; // 5 Interrupt enable uint16_t TXFFINTCLR:1; // 6 Clear INT flag uint16_t TXFFINT:1; // 7 INT flag uint16_t TXFFST:5; // 12:8 FIFO status uint16_t TXFIFOXRESET:1; // 13 FIFO reset uint16_t SCIFFENA:1; // 14 Enhancement enable uint16_t SCIRST:1; // 15 SCI reset rx/tx channels }; union SCIFFTX_REG { uint16_t all; struct SCIFFTX_BITS bit; }; //------------------------------------------------ // SCI FIFO recieve register bit definitions: // // struct SCIFFRX_BITS { // bits description uint16_t RXFFIL:5; // 4:0 Interrupt level uint16_t RXFFIENA:1; // 5 Interrupt enable uint16_t RXFFINTCLR:1; // 6 Clear INT flag uint16_t RXFFINT:1; // 7 INT flag uint16_t RXFFST:5; // 12:8 FIFO status uint16_t RXFIFORESET:1; // 13 FIFO reset uint16_t RXFFOVRCLR:1; // 14 Clear overflow uint16_t RXFFOVF:1; // 15 FIFO overflow }; union SCIFFRX_REG { uint16_t all; struct SCIFFRX_BITS bit; }; // SCI FIFO control register bit definitions: struct SCIFFCT_BITS { // bits description uint16_t FFTXDLY:8; // 7:0 FIFO transmit delay uint16_t rsvd:5; // 12:8 reserved uint16_t CDC:1; // 13 Auto baud mode enable uint16_t ABDCLR:1; // 14 Auto baud clear uint16_t ABD:1; // 15 Auto baud detect }; union SCIFFCT_REG { uint16_t all; struct SCIFFCT_BITS bit; }; //--------------------------------------------------------------------------- // SCI Register File: // struct SCI_REGS { union SCICCR_REG SCICCR; // Communications control register union SCICTL1_REG SCICTL1; // Control register 1 uint16_t SCIHBAUD; // Baud rate (high) register uint16_t SCILBAUD; // Baud rate (low) register union SCICTL2_REG SCICTL2; // Control register 2 union SCIRXST_REG SCIRXST; // Recieve status register uint16_t SCIRXEMU; // Recieve emulation buffer register union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer uint16_t rsvd1; // reserved uint16_t SCITXBUF; // Transmit data buffer union SCIFFTX_REG SCIFFTX; // FIFO transmit register union SCIFFRX_REG SCIFFRX; // FIFO recieve register union SCIFFCT_REG SCIFFCT; // FIFO control register uint16_t rsvd2; // reserved uint16_t rsvd3; // reserved union SCIPRI_REG SCIPRI; // FIFO Priority control }; //--------------------------------------------------------------------------- // SCI External References & Function Declarations: // extern volatile struct SCI_REGS SciaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_SysCtrl.h // // TITLE: F2802x Device System Control Register Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- // System Control Individual Register Bit Definitions: // // XCLKOUT Control struct XCLK_BITS { // bits description Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Ratio Uint16 rsvd1:3; // 4:2 reserved Uint16 rsvd2:1; // 5 reserved Uint16 XCLKINSEL:1; // 6 XCLKIN Source Select bit Uint16 rsvd3:9; // 15:7 reserved }; union XCLK_REG { Uint16 all; struct XCLK_BITS bit; }; // PLL Status Register struct PLLSTS_BITS { // bits description Uint16 PLLLOCKS:1; // 0 PLL lock status Uint16 rsvd1:1; // 1 reserved Uint16 PLLOFF:1; // 2 PLL off bit Uint16 MCLKSTS:1; // 3 Missing clock status bit Uint16 MCLKCLR:1; // 4 Missing clock clear bit Uint16 OSCOFF:1; // 5 Oscillator clock off Uint16 MCLKOFF:1; // 6 Missing clock detect Uint16 DIVSEL:2; // 8:7 Divide select (/4 default) Uint16 rsvd2:6; // 14:9 reserved Uint16 NORMRDYE:1; // 15 VREG NORMRDY enable bit }; union PLLSTS_REG { Uint16 all; struct PLLSTS_BITS bit; }; // Clock Control Register struct CLKCTL_BITS { // bits description Uint16 OSCCLKSRCSEL:1; // 0 Oscillator clock source select bit Uint16 OSCCLKSRC2SEL:1; // 1 Oscillator 2 clock source select bit Uint16 WDCLKSRCSEL:1; // 2 Watchdog clock source select bit Uint16 TMR2CLKSRCSEL:2; // 4:3 CPU timer 2 clock source select bit Uint16 TMR2CLKPRESCALE:3; // 7:5 CPU timer 2 clock pre-scale value Uint16 INTOSC1OFF:1; // 8 Internal oscillator off bit Uint16 INTOSC1HALTI:1; // 9 Internal oscillator 1 halt mode ignore bit Uint16 INTOSC2OFF:1; // 10 Internal oscillator 2 off bit Uint16 INTOSC2HALTI:1; // 11 Internal oscillator 2 halt mode ignore bit Uint16 WDHALTI:1; // 12 Watchdog halt mode ignore bit Uint16 XCLKINOFF:1; // 13 XCLKIN off bit Uint16 XTALOSCOFF:1; // 14 Crystal (External) oscillator off bit Uint16 NMIRESETSEL:1; // 15 NMI reset select bit }; union CLKCTL_REG { Uint16 all; struct CLKCTL_BITS bit; }; // Internal Oscillator 1 Trim struct INTOSC1TRIM_BITS { // bits description Uint16 COARSETRIM:8; // 7:0 8-bit coarse trim value Uint16 rsvd1:1; // 8 reserved Uint16 FINETRIM:6; // 9:14 6-bit fine trim value Uint16 rsvd2:1; // 15 reserved }; union INTOSC1TRIM_REG { Uint16 all; struct INTOSC1TRIM_BITS bit; }; // Internal Oscillator 2 Trim struct INTOSC2TRIM_BITS { // bits description Uint16 COARSETRIM:8; // 7:0 8-bit coarse trim value Uint16 rsvd1:1; // 8 reserved Uint16 FINETRIM:6; // 9:14 6-bit fine trim value Uint16 rsvd2:1; // 15 reserved }; union INTOSC2TRIM_REG { Uint16 all; struct INTOSC2TRIM_BITS bit; }; // Low speed peripheral clock register bit definitions: struct LOSPCP_BITS { // bits description Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT Uint16 rsvd1:13; // 15:3 reserved }; union LOSPCP_REG { Uint16 all; struct LOSPCP_BITS bit; }; // Peripheral clock control register 0 bit definitions: struct PCLKCR0_BITS { // bits description Uint16 HRPWMENCLK:1; // 0 Enable low speed clk to HRPWM Uint16 rsvd1:1; // 1 reserved Uint16 TBCLKSYNC:1; // 2 ETWPM Module TBCLK enable/sync Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A Uint16 rsvd2:3; // 7:5 reserved Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A Uint16 rsvd3:1; // 9 reserved Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A Uint16 rsvd4:5; // 15:11 reserved }; union PCLKCR0_REG { Uint16 all; struct PCLKCR0_BITS bit; }; // Peripheral clock control register 1 bit definitions: struct PCLKCR1_BITS { // bits description Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 Uint16 rsvd1:4; // 7:4 reserved Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 Uint16 rsvd2:7; // 15:9 reserved }; union PCLKCR1_REG { Uint16 all; struct PCLKCR1_BITS bit; }; // Peripheral clock control register 3 bit definitions: struct PCLKCR3_BITS { // bits description Uint16 COMP1ENCLK:1; // 0 Enable SYSCLKOUT to COMP1 Uint16 COMP2ENCLK:1; // 1 Enable SYSCLKOUT to COMP2 Uint16 rsvd1:1; // 2 reserved Uint16 rsvd2:5; // 7:3 reserved Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPUTIMER0 Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPUTIMER1 Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPUTIMER2 Uint16 rsvd3:2; // 12:11 reserved Uint16 GPIOINENCLK:1; // 13 Enable SYSCLKOUT to GPIO Uint16 rsvd4:2; // 15:14 }; union PCLKCR3_REG { Uint16 all; struct PCLKCR3_BITS bit; }; // PLL control register bit definitions: struct PLLCR_BITS { // bits description Uint16 DIV:4; // 3:0 Set clock ratio for the PLL Uint16 rsvd1:12; // 15:4 reserved }; union PLLCR_REG { Uint16 all; struct PLLCR_BITS bit; }; // Low Power Mode 0 control register bit definitions: struct LPMCR0_BITS { // bits description Uint16 LPM:2; // 1:0 Set the low power mode Uint16 QUALSTDBY:6; // 7:2 Qualification Uint16 rsvd1:7; // 14:8 reserved Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY }; union LPMCR0_REG { Uint16 all; struct LPMCR0_BITS bit; }; //--------------------------------------------------------------------------- // System Control Register File: // struct SYS_CTRL_REGS { union XCLK_REG XCLK; // 0: XCLKOUT Control union PLLSTS_REG PLLSTS; // 1: PLL Status Register union CLKCTL_REG CLKCTL; // 2: Clock Control Register Uint16 PLLLOCKPRD; // 3: PLL Lock Period Register union INTOSC1TRIM_REG INTOSC1TRIM; // 4: Internal Oscillator 1 Trim Uint16 rsvd1; // 5: reserved union INTOSC2TRIM_REG INTOSC2TRIM; // 6: Internal Oscillator 2 Trim Uint16 rsvd2[4]; // 7-10 union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 Uint16 rsvd3; // 15: reserved union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock register union PLLCR_REG PLLCR; // 17: PLL control register // No bit definitions are defined for SCSR because // a read-modify-write instruction can clear the WDOVERRIDE bit Uint16 SCSR; // 18: System control and status register Uint16 WDCNTR; // 19: WD counter register Uint16 rsvd4; // 20 Uint16 WDKEY; // 21: WD reset key register Uint16 rsvd5[3]; // 22-24 // No bit definitions are defined for WDCR because // the proper value must be written to the WDCHK field // whenever writing to this register. Uint16 WDCR; // 25: WD timer control register Uint16 rsvd6[5]; // 26-28 }; //--------------------------------------------------------------------------- // System Power Control Registers: // // BOR configuration register bit definitions: struct BORCFG_BITS { // bits description Uint16 BORENZ:1; // 0 BOR enable active low bit Uint16 rsvd1:15; // 15:1 reserved }; union BORCFG_REG { Uint16 all; struct BORCFG_BITS bit; }; struct SYS_PWR_CTRL_REGS { union BORCFG_REG BORCFG; // 0: BOR Configuration Register Uint16 rsvd1[2]; // 1-2 }; /* --------------------------------------------------- */ /* CSM Registers */ /* */ /* ----------------------------------------------------*/ /* CSM Status & Control register bit definitions */ struct CSMSCR_BITS { // bit description Uint16 SECURE:1; // 0 Secure flag Uint16 rsvd1:14; // 14-1 reserved Uint16 FORCESEC:1; // 15 Force Secure control bit }; /* Allow access to the bit fields or entire register */ union CSMSCR_REG { Uint16 all; struct CSMSCR_BITS bit; }; /* CSM Register File */ struct CSM_REGS { Uint16 KEY0; // KEY reg bits 15-0 Uint16 KEY1; // KEY reg bits 31-16 Uint16 KEY2; // KEY reg bits 47-32 Uint16 KEY3; // KEY reg bits 63-48 Uint16 KEY4; // KEY reg bits 79-64 Uint16 KEY5; // KEY reg bits 95-80 Uint16 KEY6; // KEY reg bits 111-96 Uint16 KEY7; // KEY reg bits 127-112 Uint16 rsvd1; // reserved Uint16 rsvd2; // reserved Uint16 rsvd3; // reserved Uint16 rsvd4; // reserved Uint16 rsvd5; // reserved Uint16 rsvd6; // reserved Uint16 rsvd7; // reserved union CSMSCR_REG CSMSCR; // CSM Status & Control register }; /* Password locations */ struct CSM_PWL { Uint16 PSWD0; // PSWD bits 15-0 Uint16 PSWD1; // PSWD bits 31-16 Uint16 PSWD2; // PSWD bits 47-32 Uint16 PSWD3; // PSWD bits 63-48 Uint16 PSWD4; // PSWD bits 79-64 Uint16 PSWD5; // PSWD bits 95-80 Uint16 PSWD6; // PSWD bits 111-96 Uint16 PSWD7; // PSWD bits 127-112 }; /* Flash Registers */ /* Flash Option Register bit definitions */ struct FOPT_BITS { // bit description Uint16 ENPIPE:1; // 0 Enable Pipeline Mode Uint16 rsvd:15; // 1-15 reserved }; /* Allow access to the bit fields or entire register */ union FOPT_REG { Uint16 all; struct FOPT_BITS bit; }; /* Flash Power Modes Register bit definitions */ struct FPWR_BITS { // bit description Uint16 PWR:2; // 0-1 Power Mode bits Uint16 rsvd:14; // 2-15 reserved }; /* Allow access to the bit fields or entire register */ union FPWR_REG { Uint16 all; struct FPWR_BITS bit; }; /* Flash Status Register bit definitions */ struct FSTATUS_BITS { // bit description Uint16 PWRS:2; // 0-1 Power Mode Status bits Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits Uint16 rsvd1:4; // 4-7 reserved Uint16 V3STAT:1; // 8 VDD3V Status Latch bit Uint16 rsvd2:7; // 9-15 reserved }; /* Allow access to the bit fields or entire register */ union FSTATUS_REG { Uint16 all; struct FSTATUS_BITS bit; }; /* Flash Sleep to Standby Wait Counter Register bit definitions */ struct FSTDBYWAIT_BITS { // bit description Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits Uint16 rsvd:7; // 9-15 reserved }; /* Allow access to the bit fields or entire register */ union FSTDBYWAIT_REG { Uint16 all; struct FSTDBYWAIT_BITS bit; }; /* Flash Standby to Active Wait Counter Register bit definitions */ struct FACTIVEWAIT_BITS { // bit description Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits Uint16 rsvd:7; // 9-15 reserved }; /* Allow access to the bit fields or entire register */ union FACTIVEWAIT_REG { Uint16 all; struct FACTIVEWAIT_BITS bit; }; /* Bank Read Access Wait State Register bit definitions */ struct FBANKWAIT_BITS { // bit description Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits Uint16 rsvd1:4; // 4-7 reserved Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits Uint16 rsvd2:4; // 12-15 reserved }; /* Allow access to the bit fields or entire register */ union FBANKWAIT_REG { Uint16 all; struct FBANKWAIT_BITS bit; }; /* OTP Read Access Wait State Register bit definitions */ struct FOTPWAIT_BITS { // bit description Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits Uint16 rsvd:11; // 5-15 reserved }; /* Allow access to the bit fields or entire register */ union FOTPWAIT_REG { Uint16 all; struct FOTPWAIT_BITS bit; }; struct FLASH_REGS { union FOPT_REG FOPT; // Option Register Uint16 rsvd1; // reserved union FPWR_REG FPWR; // Power Modes Register union FSTATUS_REG FSTATUS; // Status Register union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register }; //--------------------------------------------------------------------------- // System Control External References & Function Declarations: // extern volatile struct SYS_CTRL_REGS SysCtrlRegs; extern volatile struct SYS_PWR_CTRL_REGS SysPwrCtrlRegs; extern volatile struct CSM_REGS CsmRegs; extern volatile struct CSM_PWL CsmPwl; extern volatile struct FLASH_REGS FlashRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2802x_XIntrupt.h // // TITLE: F2802x Device External Interrupt Register Definitions. // //########################################################################### // $TI Release: F2802x Support Library v230 $ // $Release Date: Fri May 8 07:43:05 CDT 2015 $ // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated - // http://www.ti.com/ ALL RIGHTS RESERVED $ //########################################################################### //--------------------------------------------------------------------------- struct XINTCR_BITS { uint16_t ENABLE:1; // 0 enable/disable uint16_t rsvd1:1; // 1 reserved uint16_t POLARITY:2; // 3:2 pos/neg, both triggered uint16_t rsvd2:12; //15:4 reserved }; union XINTCR_REG { uint16_t all; struct XINTCR_BITS bit; }; //--------------------------------------------------------------------------- // External Interrupt Register File: // struct XINTRUPT_REGS { union XINTCR_REG XINT1CR; union XINTCR_REG XINT2CR; union XINTCR_REG XINT3CR; uint16_t rsvd1[5]; uint16_t XINT1CTR; uint16_t XINT2CTR; uint16_t XINT3CTR; uint16_t rsvd[5]; }; //--------------------------------------------------------------------------- // External Interrupt References & Function Declarations: // extern volatile struct XINTRUPT_REGS XIntruptRegs; //=========================================================================== // End of file. //=========================================================================== // Timer definitions based on System Clock // 60 MHz devices (28027/28026) // --- BL modification - u menya 50Mhz cpu /* #if (DSP28_28026PT||DSP28_28026DA||DSP28_28027PT||DSP28_28027DA) #define mSec0_5 30000 // 0.5 mS #define mSec0_75 45000 // 0.75 mS #define mSec1 60000 // 1.0 mS #define mSec2 120000 // 2.0 mS #define mSec5 300000 // 5.0 mS #define mSec7_5 450000 // 7.5 mS #define mSec10 600000 // 10 mS #define mSec20 1200000 // 20 mS #define mSec50 3000000 // 50 mS #define mSec75 4500000 // 75 mS #define mSec100 6000000 // 100 mS #define mSec200 12000000 // 200 mS #define mSec500 30000000 // 500 mS #define mSec750 45000000 // 750 mS #define mSec1000 60000000 // 1000 mS #define mSec2000 120000000 // 2000 mS #define mSec5000 300000000 // 5000 mS #endif */ // 50 MHz devices (28023/28022) // --- BL modification. Ya ispolzuyu 50Mhz //#if (DSP28_28022PT||DSP28_28022DA||DSP28_28023PT||DSP28_28023DA) //40 MHz devices (28021/28020/280200) //=========================================================================== // End of file. //=========================================================================== // BLR global definitions //#include "PeripheralHeaderIncludes.h" // TI File $Revision: /main/1 $ // Checkin $Date: June 22, 2007 17:02:08 $ //########################################################################### // // FILE: Flash2802x_API_Config.h // // TITLE: F2802x Flash Algo's - User Settings // // NOTE: This file contains user defined settings that // are used by the F2802x Flash APIs. // //########################################################################### // $TI Release:$ // $Release Date:$ //########################################################################### // Variables that can be configured by the user. /*----------------------------------------------------------------------------- 1. Specify the device. Define the device to be programmed as "1" (no quotes). Define all other devices as "0" (no quotes). -----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------- 2. Specify the clock rate of the CPU (SYSCLKOUT) in nS. Take into account the input clock frequency and the PLL multiplier that your application will use. Use one of the values provided, or define your own. The trailing L is required tells the compiler to treat the number as a 64-bit value. Only one statement should be uncommented. Example: CLKIN is 10MHz. If the application will set PLLCR = 0xC and the DIVSEL to /2 then the CPU clock will be 60Mhz (SYSCLKOUT = 60MHz). In this case, the CPU_RATE will be 16.667L Uncomment the line: #define CPU_RATE 16.667L -----------------------------------------------------------------------------*/ //#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 25.000L // for a 40MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) //---------------------------------------------------------------------------- //----------------------------------------------------------------------------- // **** DO NOT modify the code below this line **** //----------------------------------------------------------------------------- // TI File $Revision: /main/2 $ // Checkin $Date: February 5, 2008 11:10:00 $ //########################################################################### // // FILE: Flash2802x_API_Library.h // // TITLE: F2802x Flash Algo's main include file // // DESCRIPTION: // // This file should be included in any project that uses any of the // the F2802x flash APIs. // //########################################################################### // $TI Release:$ // $Release Date:$ //########################################################################### /*--------------------------------------------------------------------------- 28x Datatypes For Portability, User Is Recommended To Use Following Data Type Size Definitions For 16/32/64-Bit Signed/Unsigned Integers and floating point variables: ---------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------- API Status Messages The following status values are returned from the API to the calling program. These can be used to determine if the API function passed or failed. ---------------------------------------------------------------------------*/ // Operation passed, no errors were flagged // The CSM is preventing the function from performing its operation // Device REVID does not match that required by the API // Invalid address passed to the API // Incorrect PARTID // For example the F2806 API was used on a F2808 device. // API/Silicon missmatch. An old version of the // API is being used on silicon it is not valid for // Please update to the latest API. // ---- Erase Specific errors ---- // ---- Program Specific errors ---- // ---- Verify Specific errors ---- // Busy is set by each API function before it determines // a pass or fail condition for that operation. // The calling function will will not receive this // status condition back from the API /*--------------------------------------------------------------------------- Flash sector mask definitions The following macros can be used to form a mask specifying which sectors will be erased by the erase API function. Bit0 = Sector A Bit1 = Sector B Bit2 = Sector C Bit3 = Sector D ---------------------------------------------------------------------------*/ // All sectors on an F2802x - Sectors A - D /*--------------------------------------------------------------------------- API Status Structure This structure is used to pass debug data back to the calling routine. Note that the Erase API function has 3 parts: precondition, erase and and compaction. Erase and compaction failures will not populate the expected and actual data fields. ---------------------------------------------------------------------------*/ typedef struct { Uint32 FirstFailAddr; Uint16 ExpectedData; Uint16 ActualData; }FLASH_ST; /*--------------------------------------------------------------------------- Interface Function prototypes For each 28x Flash API library, the function names are of the form: Flash_() Where is the device: ie 2808, 2806, 2801 is the operation such as Erase, Program... For portability for users who may move between the F2808, F2806 and F2801, the following macro definitions are supplied. Using these macro definitions, the user can use instead make a generic call: Flash_ and the macro will map the call to the proper device function Note except for the toggle test function, all of the function prototypes are compatible with F281x devices as well. ---------------------------------------------------------------------------*/ extern Uint16 Flash2802x_Erase(Uint16 SectorMask,FLASH_ST *FEraseStat); extern Uint16 Flash2802x_Program(Uint16 *FlashAddr,Uint16 *BufAddr,Uint32 Length,FLASH_ST *FProgStatus); extern Uint16 Flash2802x_Verify(Uint16 *StartAddr,Uint16 *BufAddr,Uint32 Length,FLASH_ST *FVerifyStat); extern void Flash2802x_ToggleTest(volatile Uint32 *ToggleReg,Uint32 Mask); extern Uint16 Flash2802x_DepRecover(); extern float32 Flash2802x_APIVersion(); extern Uint16 Flash2802x_APIVersionHex(); /*--------------------------------------------------------------------------- Frequency Scale factor: The calling program must provide this global parameter used for frequency scaling the algo's. ----------------------------------------------------------------------------*/ extern Uint32 Flash_CPUScaleFactor; /*--------------------------------------------------------------------------- Callback Function Pointer: A callback function can be specified. This function will be called at safe times during erase, program and verify. This function can then be used to service an external watchdog or send a communications packet. Note: THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL. THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL ----------------------------------------------------------------------------*/ extern void (*Flash_CallbackPtr) (void); /*--------------------------------------------------------------------------- API load/run symbols: These symbols are defined by the linker during the link. Refer to the Flash28_API section in the example .cmd file: Flash28_API: { Flash28027_API_Library.lib(.econst) Flash28027_API_Library.lib(.text) } LOAD = FLASH, RUN = SARAM, LOAD_START(_Flash28_API_LoadStart), LOAD_END(_Flash28_API_LoadEnd), RUN_START(_Flash28_API_RunStart), PAGE = 0 These are used to copy the flash API from flash to SARAM ----------------------------------------------------------------------------*/ extern Uint16 Flash28_API_LoadStart; extern Uint16 Flash28_API_LoadEnd; extern Uint16 Flash28_API_RunStart; // --------- END OF FILE ---------------------------------- /*Useful links * http://software-dl.ti.com/ccs/esd/documents/sdto_cgt_How-to-Submit-a-Compiler-Test-Case.html * https://e2e.ti.com/support/development_tools/compiler/f/343/t/201557 * http://e2e.ti.com/support/development_tools/compiler/f/343/t/31416 */ //BL_WD_A = __TI_COMPILER_VERSION__; //todo /*volatile*/ //signed int BL_ZC_HIGH_RPM_ZC_FUNC[BL_ZC_HIGH_RPM_ZC_FUNC_ARRAY_MASK + 1];//[32]; //poka davay 32, esli budet bistree chem 100 taktov dlya zamera, to budem chto-to dumat typedef struct { signed long a; signed long b; signed long c; signed long d; } BL_FLASH_DATA_STRUCT; extern volatile BL_FLASH_DATA_STRUCT BL_FLASH_DATA_2_SAVE; //dannie dlya zapisi v FLASH. extern const BL_FLASH_DATA_STRUCT BL_FLASH_DATA_DEFAULT; //#pragma DATA_SECTION(BL_FLASH_DATA, "BL_EEPROM_SECT"); extern const BL_FLASH_DATA_STRUCT BL_FLASH_DATA; //eti mozhno ubrat esline yuzat v Si kode extern Uint16 RamfuncsLoadStart; extern Uint16 RamfuncsLoadEnd; extern Uint16 RamfuncsRunStart; extern Uint16 BL_FLASH_INIT(void); //OPTIMIZATION. Vopros na forume - mozhno li eto bez razmesheniya v RAM? Pohozhe nelzya #pragma CODE_SECTION(BL_FLASH_WRITE, "ramfuncs"); //OPTIMIZATION - vot eto funkcii pochemu-to ne linkuet v etu sekciyu... extern void BL_FLASH_WRITE(/*volatile*/ BL_FLASH_DATA_STRUCT *bl_data, Uint16 bl_data_len); #pragma CODE_SECTION(BL_FLASH_Error, "ramfuncs"); extern void BL_FLASH_Error(Uint16 Status); volatile signed int up_dwn; interrupt void BL_I2CINT1A_ISR(void) { PieCtrlRegs.PIEACK.bit.ACK8 = 1; } interrupt void BL_TINT0_ISR() { //(*BL_TIMER0_INT_HANDLER_ADDR)(); PieCtrlRegs.PIEACK.bit.ACK1 = 1; } interrupt void BL_TINT1_ISR1() { } interrupt void BL_WD_TIMER2_ISR_WDOFF() { } interrupt void BL_ZC_PHASE_SAMPLE_ADC_DUMMY_ISR() { } void BLR2_main(void) { //sdelat eto loc peremennoy //#define BL_ZC_HIGH_RPM_ZC_FUNC_ARRAY_MASK 127 // 127 //63 /*volatile*/ signed int BL_ZC_HIGH_RPM_ZC_FUNC[63 + 1];//[32]; //poka davay 32, esli budet bistree chem 100 taktov dlya zamera, to budem chto-to dumat Uint16 a; if(up_dwn == 1) { __rpt_mov_imm(BL_ZC_HIGH_RPM_ZC_FUNC, 1, 63/*konec*/); } else { //s otricatelnimi pochemuto ne rabotaet //__rpt_mov_imm(BL_ZC_HIGH_RPM_ZC_FUNC, -1, BL_ZC_HIGH_RPM_ZC_FUNC_ARRAY_MASK/*konec*/); for(a = 0; a <= 63; a++) { BL_ZC_HIGH_RPM_ZC_FUNC[a] = -1; } } while(1) { asm(" nop"); asm(" nop"); asm(" nop"); } }