/* ============================================================================== File Name: CommonVariables.c Description: This file defines variables that are commonly used in CPU1 and CPU2. These variables are put in the GsRAM owned by CPU1, so they are read-only for CPU2. The common variables are instanced within both CPUs (assigned value in CPU 1), and they are mapped to the same memory zone (via pragma instruction). ================================================================================= */ //########################################################################### // // FILE: f2838x_device.h // // TITLE: F2838x Device Definitions. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### // // User To Select Target Device: // // // Common CPU Definitions: // extern __cregister volatile unsigned int IFR; extern __cregister volatile unsigned int IER; // // For Portability, User Is Recommended To Use the C99 Standard integer types // /*****************************************************************************/ /* assert.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*****************************************************************************/ /* _ti_config.h */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*Unsupported pragmas are omitted */ # pragma diag_push # pragma CHECK_MISRA("-19.7") # pragma CHECK_MISRA("-19.4") # pragma CHECK_MISRA("-19.1") # pragma CHECK_MISRA("-19.15") # pragma diag_pop _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") _Pragma("CHECK_MISRA(\"-19.1\")") _Pragma("CHECK_MISRA(\"-19.6\")") /* Hide uses of the TI proprietary macros behind other macros. Implementations that don't implement these features should leave these macros undefined. */ /* Common definitions */ /* C */ /* C89/C99 */ /* _TI_NOEXCEPT_CPP14 is defined to noexcept only when compiling for C++14. It is intended to be used for functions like abort and atexit that are supposed to be declared noexcept only in C++14 mode. */ /* Target-specific definitions */ /*****************************************************************************/ /* linkage.h */ /* */ /* Copyright (c) 1998 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-19.4") /* macros required for implementation */ /* No modifiers needed to access code */ /*--------------------------------------------------------------------------*/ /* Define _DATA_ACCESS ==> how to access RTS global or static data */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _OPTIMIZE_FOR_SPACE ==> Always optimize for space. */ /*--------------------------------------------------------------------------*/ /*--------------------------------------------------------------------------*/ /* Define _IDECL ==> how inline functions are declared */ /*--------------------------------------------------------------------------*/ #pragma diag_pop _Pragma("diag_pop") _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-6.3\")") /* standard types required for standard headers */ _Pragma("CHECK_MISRA(\"-19.4\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-19.13\")") /* # and ## required for implementation */ extern void _abort_msg(const char *msg); _Pragma("diag_pop") /*****************************************************************************/ /* stdarg.h */ /* */ /* Copyright (c) 1996 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push #pragma CHECK_MISRA("-20.1") /* standard headers must define standard names */ #pragma CHECK_MISRA("-20.2") /* standard headers must define standard names */ #pragma CHECK_MISRA("-19.7") /* macros required for implementation */ #pragma CHECK_MISRA("-19.10") /* need types as macro arguments */ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2002 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1991, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Berkeley Software Design, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 * $FreeBSD$ */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"none\")") /* * Testing against Clang-specific extensions. */ /* * This code has been put in place to help reduce the addition of * compiler specific defines in FreeBSD code. It helps to aid in * having a compiler-agnostic source tree. */ /* * Macro to test if we're using a specific version of gcc or later. */ /* * The __CONCAT macro is used to concatenate parts of symbol names, e.g. * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI * mode -- there must be no spaces between its arguments, and for nested * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also * concatenate double-quoted strings produced by the __STRING macro, but * this only works with ANSI C. * * __XSTRING is like __STRING, but it expands any macros in its argument * first. It is only available with ANSI C. */ /* * Compiler-dependent macros to help declare dead (non-returning) and * pure (no side effects) functions, and unused variables. They are * null except for versions of gcc that are known to support the features * properly (old versions of gcc-2 supported the dead and pure features * in a different (wrong) way). If we do not provide an implementation * for a given compiler, let the compile fail if it is told to use * a feature that we cannot live without. */ /* * TI ADD - check that __GNUC__ is defined before referencing it to avoid * generating an error when __GNUC__ treated as zero warning is * promoted to an error via -pdse195 option. */ /* * Keywords added in C11. */ /* * No native support for _Atomic(). Place object in structure to prevent * most forms of direct non-atomic access. */ /* * XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode * without actually supporting the thread_local keyword. Don't check for * the presence of C++11 when defining _Thread_local. */ /* * Emulation of C11 _Generic(). Unlike the previously defined C11 * keywords, it is not possible to implement this using exactly the same * syntax. Therefore implement something similar under the name * __generic(). Unlike _Generic(), this macro can only distinguish * between a single type, so it requires nested invocations to * distinguish multiple cases. */ /* * C99 Static array indices in function parameter declarations. Syntax such as: * void bar(int myArray[static 10]); * is allowed in C99 but not in C++. Define __min_size appropriately so * headers using it can be compiled in either language. Use like this: * void bar(int myArray[__min_size(10)]); */ /* XXX: should use `#if __STDC_VERSION__ < 199901'. */ /* C++11 exposes a load of C99 stuff */ /* * GCC 2.95 provides `__restrict' as an extension to C90 to support the * C99-specific `restrict' type qualifier. We happen to use `__restrict' as * a way to define the `restrict' type qualifier without disturbing older * software that is unaware of C99 keywords. * The TI compiler supports __restrict in all compilation modes. */ /* * GNU C version 2.96 adds explicit branch prediction so that * the CPU back-end can hint the processor and also so that * code blocks can be reordered such that the predicted path * sees a more linear flow, thus improving cache behavior, etc. * * The following two macros provide us with a way to utilize this * compiler feature. Use __predict_true() if you expect the expression * to evaluate to true, and __predict_false() if you expect the * expression to evaluate to false. * * A few notes about usage: * * * Generally, __predict_false() error condition checks (unless * you have some _strong_ reason to do otherwise, in which case * document it), and/or __predict_true() `no-error' condition * checks, assuming you want to optimize for the no-error case. * * * Other than that, if you don't know the likelihood of a test * succeeding from empirical or other `hard' evidence, don't * make predictions. * * * These are meant to be used in places that are run `a lot'. * It is wasteful to make predictions in code that is run * seldomly (e.g. at subsystem initialization time) as the * basic block reordering that this affects can often generate * larger code. */ /* * We define this here since , , and * require it. */ /* * Given the pointer x to the member m of the struct s, return * a pointer to the containing structure. When using GCC, we first * assign pointer x to a local variable, to check that its type is * compatible with member m. */ /* * Compiler-dependent macros to declare that functions take printf-like * or scanf-like arguments. They are null except for versions of gcc * that are known to support the features properly (old versions of gcc-2 * didn't permit keeping the keywords out of the application namespace). */ /* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ /* * The following definition might not work well if used in header files, * but it should be better than nothing. If you want a "do nothing" * version, then it should generate some harmless declaration, such as: * #define __IDSTRING(name,string) struct __hack */ /* * Embed the rcs id of a source file in the resulting library. Note that in * more recent ELF binutils, we use .ident allowing the ID to be stripped. * Usage: * __FBSDID("$FreeBSD$"); */ /*- * The following definitions are an extension of the behavior originally * implemented in , but with a different level of granularity. * POSIX.1 requires that the macros we test be defined before any standard * header file is included. * * Here's a quick run-down of the versions: * defined(_POSIX_SOURCE) 1003.1-1988 * _POSIX_C_SOURCE == 1 1003.1-1990 * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option * _POSIX_C_SOURCE == 199309 1003.1b-1993 * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, * and the omnibus ISO/IEC 9945-1: 1996 * _POSIX_C_SOURCE == 200112 1003.1-2001 * _POSIX_C_SOURCE == 200809 1003.1-2008 * * In addition, the X/Open Portability Guide, which is now the Single UNIX * Specification, defines a feature-test macro which indicates the version of * that specification, and which subsumes _POSIX_C_SOURCE. * * Our macros begin with two underscores to avoid namespace screwage. */ /* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ /* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ /* Deal with various X/Open Portability Guides and Single UNIX Spec. */ /* * Deal with all versions of POSIX. The ordering relative to the tests above is * important. */ /*- * Deal with _ANSI_SOURCE: * If it is defined, and no other compilation environment is explicitly * requested, then define our internal feature-test macros to zero. This * makes no difference to the preprocessor (undefined symbols in preprocessing * expressions are defined to have value zero), but makes it more convenient for * a test program to print out the values. * * If a program mistakenly defines _ANSI_SOURCE and some other macro such as * _POSIX_C_SOURCE, we will assume that it wants the broader compilation * environment (and in fact we will never get here). */ /* User override __EXT1_VISIBLE */ /* * Old versions of GCC use non-standard ARM arch symbols; acle-compat.h * translates them to __ARM_ARCH and the modern feature symbols defined by ARM. */ /* * Nullability qualifiers: currently only supported by Clang. */ /* * Type Safety Checking * * Clang provides additional attributes to enable checking type safety * properties that cannot be enforced by the C type system. */ /* * Lock annotations. * * Clang provides support for doing basic thread-safety tests at * compile-time, by marking which locks will/should be held when * entering/leaving a functions. * * Furthermore, it is also possible to annotate variables and structure * members to enforce that they are only accessed when certain locks are * held. */ /* Structure implements a lock. */ /* Function acquires an exclusive or shared lock. */ /* Function attempts to acquire an exclusive or shared lock. */ /* Function releases a lock. */ /* Function asserts that an exclusive or shared lock is held. */ /* Function requires that an exclusive or shared lock is or is not held. */ /* Function should not be analyzed. */ /* Guard variables and structure members by lock. */ _Pragma("diag_pop") /*****************************************************************************/ /* _TYPES.H */ /* */ /* Copyright (c) 2017 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ #pragma diag_push /* This file is required to use base types */ #pragma CHECK_MISRA("-6.3") /* * Basic types upon which most other types are built. */ typedef int __int16_t; typedef unsigned int __uint16_t; typedef long __int32_t; typedef unsigned long __uint32_t; /* LONGLONG */ typedef long long __int64_t; /* LONGLONG */ typedef unsigned long long __uint64_t; /* * Standard type definitions. */ typedef __uint32_t __clock_t; /* clock()... */ typedef __int32_t __critical_t; typedef double __double_t; typedef float __float_t; typedef __int32_t __intfptr_t; typedef __int64_t __intmax_t; typedef __int32_t __intptr_t; typedef __int16_t __int_fast8_t; typedef __int16_t __int_fast16_t; typedef __int32_t __int_fast32_t; typedef __int64_t __int_fast64_t; typedef __int16_t __int_least8_t; typedef __int16_t __int_least16_t; typedef __int32_t __int_least32_t; typedef __int64_t __int_least64_t; typedef long __ptrdiff_t; /* ptr1 - ptr2 */ typedef __int16_t __register_t; typedef __int32_t __segsz_t; /* segment size (in pages) */ typedef unsigned long __size_t; /* sizeof() */ typedef __int32_t __ssize_t; /* byte count or error */ typedef __int64_t __time_t; /* time()... */ typedef __uint32_t __uintfptr_t; typedef __uint64_t __uintmax_t; typedef __uint32_t __uintptr_t; typedef __uint16_t __uint_fast8_t; typedef __uint16_t __uint_fast16_t; typedef __uint32_t __uint_fast32_t; typedef __uint64_t __uint_fast64_t; typedef __uint16_t __uint_least8_t; typedef __uint16_t __uint_least16_t; typedef __uint32_t __uint_least32_t; typedef __uint64_t __uint_least64_t; typedef __uint16_t __u_register_t; typedef __uint32_t __vm_offset_t; typedef __uint32_t __vm_paddr_t; typedef __uint32_t __vm_size_t; typedef unsigned long ___wchar_t; /* * POSIX target specific _off_t type definition */ typedef long int _off_t; /* * Unusual type definitions. */ typedef char* __va_list; #pragma diag_pop _Pragma("diag_push") /* This file is required to use types without size and signedness */ _Pragma("CHECK_MISRA(\"-6.3\")") /* * Standard type definitions. */ typedef __int32_t __blksize_t; /* file block size */ typedef __int64_t __blkcnt_t; /* file block count */ typedef __int32_t __clockid_t; /* clock_gettime()... */ typedef __uint32_t __fflags_t; /* file flags */ typedef __uint64_t __fsblkcnt_t; typedef __uint64_t __fsfilcnt_t; typedef __uint32_t __gid_t; typedef __int64_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ typedef __uint64_t __ino_t; /* inode number */ typedef long __key_t; /* IPC key (for Sys V IPC) */ typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ typedef __uint16_t __mode_t; /* permissions */ typedef int __accmode_t; /* access permissions */ typedef int __nl_item; typedef __uint64_t __nlink_t; /* link count */ typedef _off_t __off_t; /* file offset (target-specific) */ typedef __int64_t __off64_t; /* file offset (always 64-bit) */ typedef __int32_t __pid_t; /* process [group] */ typedef __int64_t __rlim_t; /* resource limit - intentionally */ /* signed, because of legacy code */ /* that uses -1 for RLIM_INFINITY */ typedef __uint16_t __sa_family_t; typedef __uint32_t __socklen_t; typedef long __suseconds_t; /* microseconds (signed) */ typedef struct __timer *__timer_t; /* timer_gettime()... */ typedef struct __mq *__mqd_t; /* mq_open()... */ typedef __uint32_t __uid_t; typedef unsigned int __useconds_t; /* microseconds (unsigned) */ typedef int __cpuwhich_t; /* which parameter for cpuset. */ typedef int __cpulevel_t; /* level parameter for cpuset. */ typedef int __cpusetid_t; /* cpuset identifier. */ /* * Unusual type definitions. */ /* * rune_t is declared to be an ``int'' instead of the more natural * ``unsigned long'' or ``long''. Two things are happening here. It is not * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, * it looks like 10646 will be a 31 bit standard. This means that if your * ints cannot hold 32 bits, you will be in trouble. The reason an int was * chosen over a long is that the is*() and to*() routines take ints (says * ANSI C), but they use __ct_rune_t instead of int. * * NOTE: rune_t is not covered by ANSI nor other standards, and should not * be instantiated outside of lib/libc/locale. Use wchar_t. wint_t and * rune_t must be the same type. Also, wint_t should be able to hold all * members of the largest character set plus one extra value (WEOF), and * must be at least 16 bits. */ typedef unsigned long __ct_rune_t; /* arg type for ctype funcs */ typedef __ct_rune_t __rune_t; /* rune_t (see above) */ typedef __ct_rune_t __wint_t; /* wint_t (see above) */ /* Clang already provides these types as built-ins, but only in C++ mode. */ typedef __uint_least16_t __char16_t; typedef __uint_least32_t __char32_t; /* In C++11, char16_t and char32_t are built-in types. */ typedef struct { long long __max_align1 __attribute__((aligned(__alignof__(long long)))); long double __max_align2 __attribute__((aligned(__alignof__(long double)))); } __max_align_t; typedef __uint64_t __dev_t; /* device number */ typedef __uint32_t __fixpt_t; /* fixed point number */ /* * mbstate_t is an opaque object to keep conversion state during multibyte * stream conversions. */ typedef int _Mbstatet; typedef _Mbstatet __mbstate_t; typedef __uintmax_t __rman_res_t; /* * When the following macro is defined, the system uses 64-bit inode numbers. * Programs can use this to avoid including , with its associated * namespace pollution. */ _Pragma("diag_pop") typedef __va_list va_list; /****************************************************************************/ /* RETURN THE NEXT VALUE ON THE STACK ... */ /* */ /* (, ) BECOMES ... */ /* */ /* ap -= 1 (stack grows toward high addresses) */ /* ap -= 1 more if type is long or float */ /* ap -= 1 more if type is long or float and to account for alignment */ /* if necessary */ /* */ /* if () return **ap; */ /* else if () return *ap; */ /* */ /* LONG/FLOATS ARE ALWAYS ALIGNED ON AN EVEN WORD BOUNDARY, EVEN WHEN */ /* PASSED AS PARAMETERS, THUS ap MUST BE ALIGNED FOR THOSE ACCESSES. */ /****************************************************************************/ #pragma diag_pop /* * Copyright (c) 2000 Jeroen Ruigrok van der Werven * All rights reserved. * * Copyright (c) 2014-2014 Texas Instruments Incorporated * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: release/10.0.0/include/stdbool.h 228878 2011-12-25 20:15:41Z ed $ */ /* If this file is included in C99 mode, _Bool is a builtin, so no definition. */ /* If this is C89 mode and this file is included, _Bool is pre-defined in C89 */ /* relaxed mode by the EDG parser, so it needs to be defined in strict mode. */ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") _Pragma("CHECK_MISRA(\"-19.11\")") _Pragma("diag_pop") /*****************************************************************************/ /* stddef.h */ /* */ /* Copyright (c) 1993 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */ _Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */ _Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */ typedef long ptrdiff_t; typedef unsigned long size_t; typedef unsigned long wchar_t; /*----------------------------------------------------------------------------*/ /* C++11 and C11 required max_align_t to be defined. The libc++ cstddef */ /* header expects the macro __DEFINED_max_align_t to be defined if it is to */ /* use the definintion of max_align_t from stddef.h. Only define it if */ /* compiling for C11 or we're in non strict ansi mode. */ /*----------------------------------------------------------------------------*/ typedef long double max_align_t; _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.10\")") /* need types as macro arguments */ _Pragma("diag_pop") _Pragma("diag_pop") /*****************************************************************************/ /* STDINT.H */ /* */ /* Copyright (c) 2002 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.1\")") /* no code before #include */ _Pragma("CHECK_MISRA(\"-19.7\")") /* prefer functions to macros */ /*****************************************************************************/ /* _STDINT40.H */ /* */ /* Copyright (c) 2018 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.7\")") /* prefer functions to macros */ /* According to footnotes in the 1999 C standard, "C++ implementations should define these macros only when __STDC_LIMIT_MACROS is defined before is included." */ _Pragma("diag_pop") /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /*****************************************************************************/ /* _STDINT.H */ /* */ /* Copyright (c) 2019 Texas Instruments Incorporated */ /* http://www.ti.com/ */ /* */ /* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: */ /* */ /* Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* */ /* Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in */ /* the documentation and/or other materials provided with the */ /* distribution. */ /* */ /* Neither the name of Texas Instruments Incorporated nor the names */ /* of its contributors may be used to endorse or promote products */ /* derived from this software without specific prior written */ /* permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ /* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ /* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ /* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ /* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ /* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ /* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ /* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* */ /*****************************************************************************/ /*- * SPDX-License-Identifier: BSD-2-Clause-NetBSD * * Copyright (c) 2001, 2002 Mike Barcroft * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Klaus Klein. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #pragma diag_push /* 19.4 is issued for macros that are defined in terms of other macros. */ #pragma CHECK_MISRA("-19.4") #pragma CHECK_MISRA("-19.7") #pragma CHECK_MISRA("-19.13") /* * ISO/IEC 9899:1999 * 7.18.2.1 Limits of exact-width integer types */ /* Minimum values of exact-width signed integer types. */ /* Maximum values of exact-width signed integer types. */ /* Maximum values of exact-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.2 Limits of minimum-width integer types */ /* Minimum values of minimum-width signed integer types. */ /* Maximum values of minimum-width signed integer types. */ /* Maximum values of minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.3 Limits of fastest minimum-width integer types */ /* Minimum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width signed integer types. */ /* Maximum values of fastest minimum-width unsigned integer types. */ /* * ISO/IEC 9899:1999 * 7.18.2.4 Limits of integer types capable of holding object pointers */ /* * ISO/IEC 9899:1999 * 7.18.2.5 Limits of greatest-width integer types */ /* * ISO/IEC 9899:1999 * 7.18.3 Limits of other integer types */ /* Limits of ptrdiff_t. */ /* Limits of sig_atomic_t. */ /* Limit of size_t. */ /* Limits of wint_t. */ #pragma diag_pop /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 David E. O'Brien * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ typedef __int16_t int16_t; typedef __int32_t int32_t; typedef __int64_t int64_t; typedef __uint16_t uint16_t; typedef __uint32_t uint32_t; typedef __uint64_t uint64_t; typedef __intptr_t intptr_t; typedef __uintptr_t uintptr_t; typedef __intmax_t intmax_t; typedef __uintmax_t uintmax_t; typedef __int_least8_t int_least8_t; typedef __int_least16_t int_least16_t; typedef __int_least32_t int_least32_t; typedef __int_least64_t int_least64_t; typedef __uint_least8_t uint_least8_t; typedef __uint_least16_t uint_least16_t; typedef __uint_least32_t uint_least32_t; typedef __uint_least64_t uint_least64_t; typedef __int_fast8_t int_fast8_t; typedef __int_fast16_t int_fast16_t; typedef __int_fast32_t int_fast32_t; typedef __int_fast64_t int_fast64_t; typedef __uint_fast8_t uint_fast8_t; typedef __uint_fast16_t uint_fast16_t; typedef __uint_fast32_t uint_fast32_t; typedef __uint_fast64_t uint_fast64_t; _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-10.1\")") /* GNU and Darwin define this and people seem to think it's portable */ _Pragma("diag_pop") _Pragma("diag_push") _Pragma("CHECK_MISRA(\"-19.4\")") /* Limits of wchar_t. */ _Pragma("diag_pop") /* ISO/IEC 9899:2011 K.3.4.4 */ _Pragma("diag_pop") // // C++ Bool Compatibility // // // C99 defines boolean type to be _Bool, but this doesn't match the format of // the other standard integer types. bool_t has been defined to fill this gap. // typedef _Bool bool_t; // //used for a bool function return status // typedef _Bool status_t; // // The following data types are included for compatibility with legacy code, // they are not recommended for use in new software. Please use the C99 // types included above // typedef int int16; typedef long int32; typedef long long int64; typedef unsigned int Uint16; typedef unsigned long Uint32; typedef unsigned long long Uint64; typedef float float32; typedef long double float64; // // The following data types are for use with byte addressable peripherals. // See compiler documentation on the byte_peripheral type attribute. // typedef unsigned int bp_16 __attribute__((byte_peripheral)); typedef unsigned long bp_32 __attribute__((byte_peripheral)); //########################################################################### // // FILE: f2838x_can.h // // TITLE: Definitions for the CAN registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CAN Individual Register Bit Definitions: struct CAN_CTL_BITS { // bits description bp_16 Init:1; // 0 Initialization bp_16 IE0:1; // 1 Interrupt line 0 Enable bp_16 SIE:1; // 2 Status Change Interrupt Enable bp_16 EIE:1; // 3 Error Interrupt Enable bp_16 rsvd1:1; // 4 Reserved bp_16 DAR:1; // 5 Disable Automatic Retransmission bp_16 CCE:1; // 6 Configuration Change Enable bp_16 Test:1; // 7 Test Mode Enable bp_16 IDS:1; // 8 Interruption Debug Support Enable bp_16 ABO:1; // 9 Auto-Bus-On Enable bp_16 PMD:4; // 13:10 Parity on/off bp_16 rsvd2:1; // 14 Reserved bp_16 SWR:1; // 15 SW Reset Enable bp_32 INITDBG:1; // 16 Debug Mode Status bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled bp_32 DE1:1; // 18 Enable DMA request line bp_32 DE2:1; // 19 Enable DMA request line bp_32 DE3:1; // 20 Enable DMA request line bp_32 rsvd3:3; // 23:21 Reserved bp_32 rsvd4:1; // 24 Reserved bp_32 rsvd5:1; // 25 Reserved bp_32 rsvd6:6; // 31:26 Reserved }; union CAN_CTL_REG { bp_32 all; struct CAN_CTL_BITS bit; }; struct CAN_ES_BITS { // bits description bp_16 LEC:3; // 2:0 Last Error Code bp_16 TxOk:1; // 3 Transmission status bp_16 RxOk:1; // 4 Reception status bp_16 EPass:1; // 5 Error Passive State bp_16 EWarn:1; // 6 Warning State bp_16 BOff:1; // 7 Bus-Off State bp_16 PER:1; // 8 Parity Error Detected bp_16 rsvd1:1; // 9 Reserved bp_16 rsvd2:1; // 10 Reserved bp_16 rsvd3:5; // 15:11 Reserved bp_32 rsvd4:16; // 31:16 Reserved }; union CAN_ES_REG { bp_32 all; struct CAN_ES_BITS bit; }; struct CAN_ERRC_BITS { // bits description bp_16 TEC:8; // 7:0 Transmit Error Counter bp_16 REC:7; // 14:8 Receive Error Counter bp_16 RP:1; // 15 Receive Error Passive bp_32 rsvd1:16; // 31:16 Reserved }; union CAN_ERRC_REG { bp_32 all; struct CAN_ERRC_BITS bit; }; struct CAN_BTR_BITS { // bits description bp_16 BRP:6; // 5:0 Baud Rate Prescaler bp_16 SJW:2; // 7:6 Synchronization Jump Width bp_16 TSEG1:4; // 11:8 Time segment bp_16 TSEG2:3; // 14:12 Time segment bp_16 rsvd1:1; // 15 Reserved bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension bp_32 rsvd2:12; // 31:20 Reserved }; union CAN_BTR_REG { bp_32 all; struct CAN_BTR_BITS bit; }; struct CAN_INT_BITS { // bits description bp_16 INT0ID:16; // 15:0 Interrupt Identifier bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier bp_32 rsvd1:8; // 31:24 Reserved }; union CAN_INT_REG { bp_32 all; struct CAN_INT_BITS bit; }; struct CAN_TEST_BITS { // bits description bp_16 rsvd1:3; // 2:0 Reserved bp_16 SILENT:1; // 3 Silent Mode bp_16 LBACK:1; // 4 Loopback Mode bp_16 TX:2; // 6:5 CANTX Pin Control bp_16 RX:1; // 7 CANRX Pin Status bp_16 EXL:1; // 8 External Loopback Mode bp_16 RDA:1; // 9 RAM Direct Access Enable: bp_16 rsvd2:6; // 15:10 Reserved bp_32 rsvd3:16; // 31:16 Reserved }; union CAN_TEST_REG { bp_32 all; struct CAN_TEST_BITS bit; }; struct CAN_PERR_BITS { // bits description bp_16 MSG_NUM:8; // 7:0 Message Number bp_16 WORD_NUM:3; // 10:8 Word Number bp_16 rsvd1:5; // 15:11 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_PERR_REG { bp_32 all; struct CAN_PERR_BITS bit; }; struct CAN_RAM_INIT_BITS { // bits description bp_16 KEY0:1; // 0 KEY0 bp_16 KEY1:1; // 1 KEY1 bp_16 KEY2:1; // 2 KEY2 bp_16 KEY3:1; // 3 KEY3 bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete bp_16 rsvd1:10; // 15:6 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_RAM_INIT_REG { bp_32 all; struct CAN_RAM_INIT_BITS bit; }; struct CAN_GLB_INT_EN_BITS { // bits description bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 bp_16 rsvd1:14; // 15:2 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_GLB_INT_EN_REG { bp_32 all; struct CAN_GLB_INT_EN_BITS bit; }; struct CAN_GLB_INT_FLG_BITS { // bits description bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 bp_16 rsvd1:14; // 15:2 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_GLB_INT_FLG_REG { bp_32 all; struct CAN_GLB_INT_FLG_BITS bit; }; struct CAN_GLB_INT_CLR_BITS { // bits description bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 bp_16 rsvd1:14; // 15:2 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_GLB_INT_CLR_REG { bp_32 all; struct CAN_GLB_INT_CLR_BITS bit; }; struct CAN_TXRQ_X_BITS { // bits description bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_TXRQ_X_REG { bp_32 all; struct CAN_TXRQ_X_BITS bit; }; struct CAN_NDAT_X_BITS { // bits description bp_16 NewDatReg1:2; // 1:0 New Data Register 1 bp_16 NewDatReg2:2; // 3:2 New Data Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_NDAT_X_REG { bp_32 all; struct CAN_NDAT_X_BITS bit; }; struct CAN_IPEN_X_BITS { // bits description bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IPEN_X_REG { bp_32 all; struct CAN_IPEN_X_BITS bit; }; struct CAN_MVAL_X_BITS { // bits description bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 bp_16 rsvd1:12; // 15:4 Reserved bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_MVAL_X_REG { bp_32 all; struct CAN_MVAL_X_BITS bit; }; struct CAN_IF1CMD_BITS { // bits description bp_16 MSG_NUM:8; // 7:0 Message Number bp_16 rsvd1:6; // 13:8 Reserved bp_16 DMAactive:1; // 14 DMA Status bp_16 Busy:1; // 15 Busy Flag bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 bp_32 TXRQST:1; // 18 Access Transmission Request Bit bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit bp_32 Control:1; // 20 Access Control Bits bp_32 Arb:1; // 21 Access Arbitration Bits bp_32 Mask:1; // 22 Access Mask Bits bp_32 DIR:1; // 23 Write/Read Direction bp_32 rsvd2:8; // 31:24 Reserved }; union CAN_IF1CMD_REG { bp_32 all; struct CAN_IF1CMD_BITS bit; }; struct CAN_IF1MSK_BITS { // bits description bp_32 Msk:29; // 28:0 Identifier Mask bp_32 rsvd1:1; // 29 Reserved bp_32 MDir:1; // 30 Mask Message Direction bp_32 MXtd:1; // 31 Mask Extended Identifier }; union CAN_IF1MSK_REG { bp_32 all; struct CAN_IF1MSK_BITS bit; }; struct CAN_IF1ARB_BITS { // bits description bp_32 ID:29; // 28:0 ` bp_32 Dir:1; // 29 Message Direction bp_32 Xtd:1; // 30 Extended Identifier bp_32 MsgVal:1; // 31 Message Valid }; union CAN_IF1ARB_REG { bp_32 all; struct CAN_IF1ARB_BITS bit; }; struct CAN_IF1MCTL_BITS { // bits description bp_16 DLC:4; // 3:0 Data length code bp_16 rsvd1:3; // 6:4 Reserved bp_16 EoB:1; // 7 End of Block bp_16 TxRqst:1; // 8 Transmit Request bp_16 RmtEn:1; // 9 Remote Enable bp_16 RxIE:1; // 10 Receive Interrupt Enable bp_16 TxIE:1; // 11 Transmit Interrupt Enable bp_16 UMask:1; // 12 Use Acceptance Mask bp_16 IntPnd:1; // 13 Interrupt Pending bp_16 MsgLst:1; // 14 Message Lost bp_16 NewDat:1; // 15 New Data bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IF1MCTL_REG { bp_32 all; struct CAN_IF1MCTL_BITS bit; }; struct CAN_IF1DATA_BITS { // bits description bp_16 Data_0:8; // 7:0 Data Byte 0 bp_16 Data_1:8; // 15:8 Data Byte 1 bp_32 Data_2:8; // 23:16 Data Byte 2 bp_32 Data_3:8; // 31:24 Data Byte 3 }; union CAN_IF1DATA_REG { bp_32 all; struct CAN_IF1DATA_BITS bit; }; struct CAN_IF1DATB_BITS { // bits description bp_16 Data_4:8; // 7:0 Data Byte 4 bp_16 Data_5:8; // 15:8 Data Byte 5 bp_32 Data_6:8; // 23:16 Data Byte 6 bp_32 Data_7:8; // 31:24 Data Byte 7 }; union CAN_IF1DATB_REG { bp_32 all; struct CAN_IF1DATB_BITS bit; }; struct CAN_IF2CMD_BITS { // bits description bp_16 MSG_NUM:8; // 7:0 Message Number bp_16 rsvd1:6; // 13:8 Reserved bp_16 DMAactive:1; // 14 DMA Status bp_16 Busy:1; // 15 Busy Flag bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 bp_32 TxRqst:1; // 18 Access Transmission Request Bit bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit bp_32 Control:1; // 20 Access Control Bits bp_32 Arb:1; // 21 Access Arbitration Bits bp_32 Mask:1; // 22 Access Mask Bits bp_32 DIR:1; // 23 Write/Read Direction bp_32 rsvd2:8; // 31:24 Reserved }; union CAN_IF2CMD_REG { bp_32 all; struct CAN_IF2CMD_BITS bit; }; struct CAN_IF2MSK_BITS { // bits description bp_32 Msk:29; // 28:0 Identifier Mask bp_32 rsvd1:1; // 29 Reserved bp_32 MDir:1; // 30 Mask Message Direction bp_32 MXtd:1; // 31 Mask Extended Identifier }; union CAN_IF2MSK_REG { bp_32 all; struct CAN_IF2MSK_BITS bit; }; struct CAN_IF2ARB_BITS { // bits description bp_32 ID:29; // 28:0 Message Identifier bp_32 Dir:1; // 29 Message Direction bp_32 Xtd:1; // 30 Extended Identifier bp_32 MsgVal:1; // 31 Message Valid }; union CAN_IF2ARB_REG { bp_32 all; struct CAN_IF2ARB_BITS bit; }; struct CAN_IF2MCTL_BITS { // bits description bp_16 DLC:4; // 3:0 Data length code bp_16 rsvd1:3; // 6:4 Reserved bp_16 EoB:1; // 7 End of Block bp_16 TxRqst:1; // 8 Transmit Request bp_16 RmtEn:1; // 9 Remote Enable bp_16 RxIE:1; // 10 Receive Interrupt Enable bp_16 TxIE:1; // 11 Transmit Interrupt Enable bp_16 UMask:1; // 12 Use Acceptance Mask bp_16 IntPnd:1; // 13 Interrupt Pending bp_16 MsgLst:1; // 14 Message Lost bp_16 NewDat:1; // 15 New Data bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IF2MCTL_REG { bp_32 all; struct CAN_IF2MCTL_BITS bit; }; struct CAN_IF2DATA_BITS { // bits description bp_16 Data_0:8; // 7:0 Data Byte 0 bp_16 Data_1:8; // 15:8 Data Byte 1 bp_32 Data_2:8; // 23:16 Data Byte 2 bp_32 Data_3:8; // 31:24 Data Byte 3 }; union CAN_IF2DATA_REG { bp_32 all; struct CAN_IF2DATA_BITS bit; }; struct CAN_IF2DATB_BITS { // bits description bp_16 Data_4:8; // 7:0 Data Byte 4 bp_16 Data_5:8; // 15:8 Data Byte 5 bp_32 Data_6:8; // 23:16 Data Byte 6 bp_32 Data_7:8; // 31:24 Data Byte 7 }; union CAN_IF2DATB_REG { bp_32 all; struct CAN_IF2DATB_BITS bit; }; struct CAN_IF3OBS_BITS { // bits description bp_16 Mask:1; // 0 Mask data read observation bp_16 Arb:1; // 1 Arbitration data read observation bp_16 Ctrl:1; // 2 Ctrl read observation bp_16 Data_A:1; // 3 Data A read observation bp_16 Data_B:1; // 4 Data B read observation bp_16 rsvd1:3; // 7:5 Reserved bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access bp_16 rsvd2:2; // 14:13 Reserved bp_16 IF3Upd:1; // 15 IF3 Update Data bp_32 rsvd3:16; // 31:16 Reserved }; union CAN_IF3OBS_REG { bp_32 all; struct CAN_IF3OBS_BITS bit; }; struct CAN_IF3MSK_BITS { // bits description bp_32 Msk:29; // 28:0 Mask bp_32 rsvd1:1; // 29 Reserved bp_32 MDir:1; // 30 Mask Message Direction bp_32 MXtd:1; // 31 Mask Extended Identifier }; union CAN_IF3MSK_REG { bp_32 all; struct CAN_IF3MSK_BITS bit; }; struct CAN_IF3ARB_BITS { // bits description bp_32 ID:29; // 28:0 Message Identifier bp_32 Dir:1; // 29 Message Direction bp_32 Xtd:1; // 30 Extended Identifier bp_32 MsgVal:1; // 31 Message Valid }; union CAN_IF3ARB_REG { bp_32 all; struct CAN_IF3ARB_BITS bit; }; struct CAN_IF3MCTL_BITS { // bits description bp_16 DLC:4; // 3:0 Data length code bp_16 rsvd1:3; // 6:4 Reserved bp_16 EoB:1; // 7 End of Block bp_16 TxRqst:1; // 8 Transmit Request bp_16 RmtEn:1; // 9 Remote Enable bp_16 RxIE:1; // 10 Receive Interrupt Enable bp_16 TxIE:1; // 11 Transmit Interrupt Enable bp_16 UMask:1; // 12 Use Acceptance Mask bp_16 IntPnd:1; // 13 Interrupt Pending bp_16 MsgLst:1; // 14 Message Lost bp_16 NewDat:1; // 15 New Data bp_32 rsvd2:16; // 31:16 Reserved }; union CAN_IF3MCTL_REG { bp_32 all; struct CAN_IF3MCTL_BITS bit; }; struct CAN_IF3DATA_BITS { // bits description bp_16 Data_0:8; // 7:0 Data Byte 0 bp_16 Data_1:8; // 15:8 Data Byte 1 bp_32 Data_2:8; // 23:16 Data Byte 2 bp_32 Data_3:8; // 31:24 Data Byte 3 }; union CAN_IF3DATA_REG { bp_32 all; struct CAN_IF3DATA_BITS bit; }; struct CAN_IF3DATB_BITS { // bits description bp_16 Data_4:8; // 7:0 Data Byte 4 bp_16 Data_5:8; // 15:8 Data Byte 5 bp_32 Data_6:8; // 23:16 Data Byte 6 bp_32 Data_7:8; // 31:24 Data Byte 7 }; union CAN_IF3DATB_REG { bp_32 all; struct CAN_IF3DATB_BITS bit; }; struct CAN_REGS { union CAN_CTL_REG CAN_CTL; // CAN Control Register union CAN_ES_REG CAN_ES; // Error and Status Register union CAN_ERRC_REG CAN_ERRC; // Error Counter Register union CAN_BTR_REG CAN_BTR; // Bit Timing Register union CAN_INT_REG CAN_INT; // Interrupt Register union CAN_TEST_REG CAN_TEST; // Test Register uint32_t rsvd1[2]; // Reserved union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register uint32_t rsvd2[16]; // Reserved union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register uint32_t rsvd3[6]; // Reserved union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register uint32_t rsvd4[18]; // Reserved bp_32 CAN_ABOTR; // Auto-Bus-On Time Register union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register uint32_t rsvd5[6]; // Reserved union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register uint32_t rsvd6[6]; // Reserved union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register uint32_t rsvd7[6]; // Reserved union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register uint32_t rsvd8[8]; // Reserved bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register uint32_t rsvd9[18]; // Reserved union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register uint32_t rsvd10[4]; // Reserved union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register uint32_t rsvd11[4]; // Reserved union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register uint32_t rsvd12[4]; // Reserved bp_32 CAN_IF3UPD; // IF3 Update Enable Register }; //--------------------------------------------------------------------------- // CAN External References & Function Declarations: // extern volatile struct CAN_REGS CanaRegs; extern volatile struct CAN_REGS CanbRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_dcc.h // // TITLE: Definitions for the DCC registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // DCC Individual Register Bit Definitions: struct DCCGCTRL_BITS { // bits description bp_16 DCCENA:4; // 3:0 DCC Enable bp_16 ERRENA:4; // 7:4 Error Enable bp_16 SINGLESHOT:4; // 11:8 Single-Shot Enable bp_16 DONEENA:4; // 15:12 DONE Enable bp_16 rsvd1:16; // 31:16 Reserved }; union DCCGCTRL_REG { bp_32 all; struct DCCGCTRL_BITS bit; }; struct DCCCNTSEED0_BITS { // bits description bp_32 COUNTSEED0:20; // 19:0 Seed Value for Counter 0 bp_16 rsvd1:12; // 31:20 Reserved }; union DCCCNTSEED0_REG { bp_32 all; struct DCCCNTSEED0_BITS bit; }; struct DCCVALIDSEED0_BITS { // bits description bp_16 VALIDSEED:16; // 15:0 Seed Value for Valid Duration Counter 0 bp_16 rsvd1:16; // 31:16 Reserved }; union DCCVALIDSEED0_REG { bp_32 all; struct DCCVALIDSEED0_BITS bit; }; struct DCCCNTSEED1_BITS { // bits description bp_32 COUNTSEED1:20; // 19:0 Seed Value for Counter 1 bp_16 rsvd1:12; // 31:20 Reserved }; union DCCCNTSEED1_REG { bp_32 all; struct DCCCNTSEED1_BITS bit; }; struct DCCSTATUS_BITS { // bits description bp_16 ERR:1; // 0 Error Flag bp_16 DONE:1; // 1 Single-Shot Done Flag bp_16 rsvd1:14; // 15:2 Reserved bp_16 rsvd2:16; // 31:16 Reserved }; union DCCSTATUS_REG { bp_32 all; struct DCCSTATUS_BITS bit; }; struct DCCCNT0_BITS { // bits description bp_32 COUNT0:20; // 19:0 Current Value of Counter 0 bp_16 rsvd1:12; // 31:20 Reserved }; union DCCCNT0_REG { bp_32 all; struct DCCCNT0_BITS bit; }; struct DCCVALID0_BITS { // bits description bp_16 VALID0:16; // 15:0 Current Value of Valid 0 bp_16 rsvd1:16; // 31:16 Reserved }; union DCCVALID0_REG { bp_32 all; struct DCCVALID0_BITS bit; }; struct DCCCNT1_BITS { // bits description bp_32 COUNT1:20; // 19:0 Current Value of Counter 1 bp_16 rsvd1:12; // 31:20 Reserved }; union DCCCNT1_REG { bp_32 all; struct DCCCNT1_BITS bit; }; struct DCCCLKSRC1_BITS { // bits description bp_16 CLKSRC1:5; // 4:0 Clock Source Select for Counter 1 bp_16 rsvd1:7; // 11:5 Reserved bp_16 KEY:4; // 15:12 Enables or Disables Clock Source Selection for COUNT1 bp_16 rsvd2:16; // 31:16 Reserved }; union DCCCLKSRC1_REG { bp_32 all; struct DCCCLKSRC1_BITS bit; }; struct DCCCLKSRC0_BITS { // bits description bp_16 CLKSRC0:4; // 3:0 Clock Source Select for Counter 0 bp_16 rsvd1:8; // 11:4 Reserved bp_16 KEY:4; // 15:12 Enables or Disables Clock Source Selection for COUNT0 bp_16 rsvd2:16; // 31:16 Reserved }; union DCCCLKSRC0_REG { bp_32 all; struct DCCCLKSRC0_BITS bit; }; struct DCC_REGS { union DCCGCTRL_REG DCCGCTRL; // Starts / stops the counters. Clears the error signal. Uint16 rsvd1[2]; // Reserved union DCCCNTSEED0_REG DCCCNTSEED0; // Seed value for the counter attached to Clock Source 0. union DCCVALIDSEED0_REG DCCVALIDSEED0; // Seed value for the timeout counter attached to Clock Source 0. union DCCCNTSEED1_REG DCCCNTSEED1; // Seed value for the counter attached to Clock Source 1. union DCCSTATUS_REG DCCSTATUS; // Specifies the status of the DCC Module. union DCCCNT0_REG DCCCNT0; // Value of the counter attached to Clock Source 0. union DCCVALID0_REG DCCVALID0; // Value of the valid counter attached to Clock Source 0. union DCCCNT1_REG DCCCNT1; // Value of the counter attached to Clock Source 1. union DCCCLKSRC1_REG DCCCLKSRC1; // Selects the clock source for Counter 1. union DCCCLKSRC0_REG DCCCLKSRC0; // Selects the clock source for Counter 0. }; //--------------------------------------------------------------------------- // DCC External References & Function Declarations: // extern volatile struct DCC_REGS Dcc0Regs; extern volatile struct DCC_REGS Dcc1Regs; extern volatile struct DCC_REGS Dcc2Regs; //=========================================================================== // End of file. //=========================================================================== // // Include All Peripheral Header Files: // //########################################################################### // // FILE: f2838x_adc.h // // TITLE: Definitions for the ADC registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ADC Individual Register Bit Definitions: struct ADCCTL1_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position Uint16 rsvd2:4; // 6:3 Reserved Uint16 ADCPWDNZ:1; // 7 ADC Power Down Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel Uint16 rsvd3:1; // 12 Reserved Uint16 ADCBSY:1; // 13 ADC Busy Uint16 rsvd4:2; // 15:14 Reserved }; union ADCCTL1_REG { Uint16 all; struct ADCCTL1_BITS bit; }; struct ADCCTL2_BITS { // bits description Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler Uint16 rsvd1:2; // 5:4 Reserved Uint16 RESOLUTION:1; // 6 SOC Conversion Resolution Uint16 SIGNALMODE:1; // 7 SOC Signaling Mode Uint16 rsvd2:5; // 12:8 Reserved Uint16 rsvd3:3; // 15:13 Reserved }; union ADCCTL2_REG { Uint16 all; struct ADCCTL2_BITS bit; }; struct ADCBURSTCTL_BITS { // bits description Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select Uint16 rsvd1:2; // 7:6 Reserved Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select Uint16 rsvd2:3; // 14:12 Reserved Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable }; union ADCBURSTCTL_REG { Uint16 all; struct ADCBURSTCTL_BITS bit; }; struct ADCINTFLG_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTFLG_REG { Uint16 all; struct ADCINTFLG_BITS bit; }; struct ADCINTFLGCLR_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTFLGCLR_REG { Uint16 all; struct ADCINTFLGCLR_BITS bit; }; struct ADCINTOVF_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTOVF_REG { Uint16 all; struct ADCINTOVF_BITS bit; }; struct ADCINTOVFCLR_BITS { // bits description Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits Uint16 rsvd1:12; // 15:4 Reserved }; union ADCINTOVFCLR_REG { Uint16 all; struct ADCINTOVFCLR_BITS bit; }; struct ADCINTSEL1N2_BITS { // bits description Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select Uint16 rsvd1:1; // 4 Reserved Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable Uint16 INT1CONT:1; // 6 ADCINT1 Continue to Interrupt Mode Uint16 rsvd2:1; // 7 Reserved Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select Uint16 rsvd3:1; // 12 Reserved Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable Uint16 INT2CONT:1; // 14 ADCINT2 Continue to Interrupt Mode Uint16 rsvd4:1; // 15 Reserved }; union ADCINTSEL1N2_REG { Uint16 all; struct ADCINTSEL1N2_BITS bit; }; struct ADCINTSEL3N4_BITS { // bits description Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select Uint16 rsvd1:1; // 4 Reserved Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable Uint16 INT3CONT:1; // 6 ADCINT3 Continue to Interrupt Mode Uint16 rsvd2:1; // 7 Reserved Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select Uint16 rsvd3:1; // 12 Reserved Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable Uint16 INT4CONT:1; // 14 ADCINT4 Continue to Interrupt Mode Uint16 rsvd4:1; // 15 Reserved }; union ADCINTSEL3N4_REG { Uint16 all; struct ADCINTSEL3N4_BITS bit; }; struct ADCSOCPRICTL_BITS { // bits description Uint16 SOCPRIORITY:5; // 4:0 SOC Priority Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer Uint16 rsvd1:6; // 15:10 Reserved }; union ADCSOCPRICTL_REG { Uint16 all; struct ADCSOCPRICTL_BITS bit; }; struct ADCINTSOCSEL1_BITS { // bits description Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select }; union ADCINTSOCSEL1_REG { Uint16 all; struct ADCINTSOCSEL1_BITS bit; }; struct ADCINTSOCSEL2_BITS { // bits description Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select }; union ADCINTSOCSEL2_REG { Uint16 all; struct ADCINTSOCSEL2_BITS bit; }; struct ADCSOCFLG1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag }; union ADCSOCFLG1_REG { Uint16 all; struct ADCSOCFLG1_BITS bit; }; struct ADCSOCFRC1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit }; union ADCSOCFRC1_REG { Uint16 all; struct ADCSOCFRC1_BITS bit; }; struct ADCSOCOVF1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag }; union ADCSOCOVF1_REG { Uint16 all; struct ADCSOCOVF1_BITS bit; }; struct ADCSOCOVFCLR1_BITS { // bits description Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit }; union ADCSOCOVFCLR1_REG { Uint16 all; struct ADCSOCOVFCLR1_BITS bit; }; struct ADCSOC0CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC0 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC0 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC0CTL_REG { Uint32 all; struct ADCSOC0CTL_BITS bit; }; struct ADCSOC1CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC1 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC1 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC1CTL_REG { Uint32 all; struct ADCSOC1CTL_BITS bit; }; struct ADCSOC2CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC2 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC2 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC2CTL_REG { Uint32 all; struct ADCSOC2CTL_BITS bit; }; struct ADCSOC3CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC3 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC3 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC3CTL_REG { Uint32 all; struct ADCSOC3CTL_BITS bit; }; struct ADCSOC4CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC4 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC4 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC4CTL_REG { Uint32 all; struct ADCSOC4CTL_BITS bit; }; struct ADCSOC5CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC5 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC5 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC5CTL_REG { Uint32 all; struct ADCSOC5CTL_BITS bit; }; struct ADCSOC6CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC6 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC6 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC6CTL_REG { Uint32 all; struct ADCSOC6CTL_BITS bit; }; struct ADCSOC7CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC7 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC7 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC7CTL_REG { Uint32 all; struct ADCSOC7CTL_BITS bit; }; struct ADCSOC8CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC8 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC8 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC8CTL_REG { Uint32 all; struct ADCSOC8CTL_BITS bit; }; struct ADCSOC9CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC9 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC9 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC9CTL_REG { Uint32 all; struct ADCSOC9CTL_BITS bit; }; struct ADCSOC10CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC10 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC10 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC10CTL_REG { Uint32 all; struct ADCSOC10CTL_BITS bit; }; struct ADCSOC11CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC11 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC11 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC11CTL_REG { Uint32 all; struct ADCSOC11CTL_BITS bit; }; struct ADCSOC12CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC12 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC12 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC12CTL_REG { Uint32 all; struct ADCSOC12CTL_BITS bit; }; struct ADCSOC13CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC13 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC13 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC13CTL_REG { Uint32 all; struct ADCSOC13CTL_BITS bit; }; struct ADCSOC14CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC14 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC14 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC14CTL_REG { Uint32 all; struct ADCSOC14CTL_BITS bit; }; struct ADCSOC15CTL_BITS { // bits description Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale Uint16 rsvd1:6; // 14:9 Reserved Uint32 CHSEL:4; // 18:15 SOC15 Channel Select Uint16 rsvd2:1; // 19 Reserved Uint16 TRIGSEL:6; // 25:20 SOC15 Trigger Source Select Uint16 rsvd3:6; // 31:26 Reserved }; union ADCSOC15CTL_REG { Uint32 all; struct ADCSOC15CTL_BITS bit; }; struct ADCEVTSTAT_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTSTAT_REG { Uint16 all; struct ADCEVTSTAT_BITS bit; }; struct ADCEVTCLR_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTCLR_REG { Uint16 all; struct ADCEVTCLR_BITS bit; }; struct ADCEVTSEL_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTSEL_REG { Uint16 all; struct ADCEVTSEL_BITS bit; }; struct ADCEVTINTSEL_BITS { // bits description Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable Uint16 rsvd2:1; // 7 Reserved Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable Uint16 rsvd3:1; // 11 Reserved Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable Uint16 rsvd4:1; // 15 Reserved }; union ADCEVTINTSEL_REG { Uint16 all; struct ADCEVTINTSEL_BITS bit; }; struct ADCCOUNTER_BITS { // bits description Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value Uint16 rsvd1:4; // 15:12 Reserved }; union ADCCOUNTER_REG { Uint16 all; struct ADCCOUNTER_BITS bit; }; struct ADCREV_BITS { // bits description Uint16 TYPE:8; // 7:0 ADC Type Uint16 REV:8; // 15:8 ADC Revision }; union ADCREV_REG { Uint16 all; struct ADCREV_BITS bit; }; struct ADCOFFTRIM_BITS { // bits description Uint16 OFFTRIM:8; // 7:0 ADC Offset Trim Uint16 rsvd1:8; // 15:8 Reserved }; union ADCOFFTRIM_REG { Uint16 all; struct ADCOFFTRIM_BITS bit; }; struct ADCPPB1CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB1CONFIG_REG { Uint16 all; struct ADCPPB1CONFIG_BITS bit; }; struct ADCPPB1STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB1STAMP_REG { Uint16 all; struct ADCPPB1STAMP_BITS bit; }; struct ADCPPB1OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB1OFFCAL_REG { Uint16 all; struct ADCPPB1OFFCAL_BITS bit; }; struct ADCPPB1TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB1TRIPHI_REG { Uint32 all; struct ADCPPB1TRIPHI_BITS bit; }; struct ADCPPB1TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp }; union ADCPPB1TRIPLO_REG { Uint32 all; struct ADCPPB1TRIPLO_BITS bit; }; struct ADCPPB2CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB2CONFIG_REG { Uint16 all; struct ADCPPB2CONFIG_BITS bit; }; struct ADCPPB2STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB2STAMP_REG { Uint16 all; struct ADCPPB2STAMP_BITS bit; }; struct ADCPPB2OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB2OFFCAL_REG { Uint16 all; struct ADCPPB2OFFCAL_BITS bit; }; struct ADCPPB2TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB2TRIPHI_REG { Uint32 all; struct ADCPPB2TRIPHI_BITS bit; }; struct ADCPPB2TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp }; union ADCPPB2TRIPLO_REG { Uint32 all; struct ADCPPB2TRIPLO_BITS bit; }; struct ADCPPB3CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB3CONFIG_REG { Uint16 all; struct ADCPPB3CONFIG_BITS bit; }; struct ADCPPB3STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB3STAMP_REG { Uint16 all; struct ADCPPB3STAMP_BITS bit; }; struct ADCPPB3OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB3OFFCAL_REG { Uint16 all; struct ADCPPB3OFFCAL_BITS bit; }; struct ADCPPB3TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB3TRIPHI_REG { Uint32 all; struct ADCPPB3TRIPHI_BITS bit; }; struct ADCPPB3TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp }; union ADCPPB3TRIPLO_REG { Uint32 all; struct ADCPPB3TRIPLO_BITS bit; }; struct ADCPPB4CONFIG_BITS { // bits description Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable Uint16 CBCEN:1; // 5 Cycle By Cycle Enable Uint16 rsvd1:10; // 15:6 Reserved }; union ADCPPB4CONFIG_REG { Uint16 all; struct ADCPPB4CONFIG_BITS bit; }; struct ADCPPB4STAMP_BITS { // bits description Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp Uint16 rsvd1:4; // 15:12 Reserved }; union ADCPPB4STAMP_REG { Uint16 all; struct ADCPPB4STAMP_BITS bit; }; struct ADCPPB4OFFCAL_BITS { // bits description Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction Uint16 rsvd1:6; // 15:10 Reserved }; union ADCPPB4OFFCAL_REG { Uint16 all; struct ADCPPB4OFFCAL_BITS bit; }; struct ADCPPB4TRIPHI_BITS { // bits description Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit Uint16 HSIGN:1; // 16 High Limit Sign Bit Uint16 rsvd1:15; // 31:17 Reserved }; union ADCPPB4TRIPHI_REG { Uint32 all; struct ADCPPB4TRIPHI_BITS bit; }; struct ADCPPB4TRIPLO_BITS { // bits description Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit Uint16 LSIGN:1; // 16 Low Limit Sign Bit Uint16 rsvd1:3; // 19:17 Reserved Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp }; union ADCPPB4TRIPLO_REG { Uint32 all; struct ADCPPB4TRIPLO_BITS bit; }; struct ADC_REGS { union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register Uint16 rsvd1; // Reserved union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register Uint16 rsvd2; // Reserved union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register Uint16 rsvd3; // Reserved union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register Uint16 rsvd4[2]; // Reserved union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register union ADCREV_REG ADCREV; // ADC Revision Register union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register Uint16 rsvd5[4]; // Reserved union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register Uint16 rsvd6[15]; // Reserved Uint16 ADCINTCYCLE; // ADC Early Interrupt Generation Cycle Uint32 ADCINLTRIM1; // ADC Linearity Trim 1 Register Uint32 ADCINLTRIM2; // ADC Linearity Trim 2 Register Uint32 ADCINLTRIM3; // ADC Linearity Trim 3 Register Uint32 ADCINLTRIM4; // ADC Linearity Trim 4 Register Uint32 ADCINLTRIM5; // ADC Linearity Trim 5 Register Uint32 ADCINLTRIM6; // ADC Linearity Trim 6 Register }; struct ADCPPB1RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB1RESULT_REG { Uint32 all; struct ADCPPB1RESULT_BITS bit; }; struct ADCPPB2RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB2RESULT_REG { Uint32 all; struct ADCPPB2RESULT_BITS bit; }; struct ADCPPB3RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB3RESULT_REG { Uint32 all; struct ADCPPB3RESULT_BITS bit; }; struct ADCPPB4RESULT_BITS { // bits description Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result Uint16 SIGN:16; // 31:16 Sign Extended Bits }; union ADCPPB4RESULT_REG { Uint32 all; struct ADCPPB4RESULT_BITS bit; }; struct ADC_RESULT_REGS { Uint16 ADCRESULT0; // ADC Result 0 Register Uint16 ADCRESULT1; // ADC Result 1 Register Uint16 ADCRESULT2; // ADC Result 2 Register Uint16 ADCRESULT3; // ADC Result 3 Register Uint16 ADCRESULT4; // ADC Result 4 Register Uint16 ADCRESULT5; // ADC Result 5 Register Uint16 ADCRESULT6; // ADC Result 6 Register Uint16 ADCRESULT7; // ADC Result 7 Register Uint16 ADCRESULT8; // ADC Result 8 Register Uint16 ADCRESULT9; // ADC Result 9 Register Uint16 ADCRESULT10; // ADC Result 10 Register Uint16 ADCRESULT11; // ADC Result 11 Register Uint16 ADCRESULT12; // ADC Result 12 Register Uint16 ADCRESULT13; // ADC Result 13 Register Uint16 ADCRESULT14; // ADC Result 14 Register Uint16 ADCRESULT15; // ADC Result 15 Register union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register }; //--------------------------------------------------------------------------- // ADC External References & Function Declarations: // extern volatile struct ADC_RESULT_REGS AdcaResultRegs; extern volatile struct ADC_RESULT_REGS AdcbResultRegs; extern volatile struct ADC_RESULT_REGS AdccResultRegs; extern volatile struct ADC_RESULT_REGS AdcdResultRegs; extern volatile struct ADC_REGS AdcaRegs; extern volatile struct ADC_REGS AdcbRegs; extern volatile struct ADC_REGS AdccRegs; extern volatile struct ADC_REGS AdcdRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_analogsubsys.h // // TITLE: Definitions for the ANALOGSUBSYS registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ANALOGSUBSYS Individual Register Bit Definitions: struct INTOSC1TRIM_BITS { // bits description Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:8; // 23:16 Reserved Uint16 rsvd3:8; // 31:24 Reserved }; union INTOSC1TRIM_REG { Uint32 all; struct INTOSC1TRIM_BITS bit; }; struct INTOSC2TRIM_BITS { // bits description Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits Uint16 rsvd1:4; // 15:12 Reserved Uint16 rsvd2:8; // 23:16 Reserved Uint16 rsvd3:8; // 31:24 Reserved }; union INTOSC2TRIM_REG { Uint32 all; struct INTOSC2TRIM_BITS bit; }; struct TSNSCTL_BITS { // bits description Uint16 ENABLE:1; // 0 Temperature Sensor Enable Uint16 rsvd1:15; // 15:1 Reserved }; union TSNSCTL_REG { Uint16 all; struct TSNSCTL_BITS bit; }; struct LOCK_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 TSNSCTL:1; // 3 Temperature Sensor Control Register Lock Uint16 rsvd4:1; // 4 Reserved Uint16 rsvd5:1; // 5 Reserved Uint16 rsvd6:1; // 6 Reserved Uint32 rsvd7:12; // 18:7 Reserved Uint16 rsvd8:1; // 19 Reserved Uint16 rsvd9:1; // 20 Reserved Uint16 rsvd10:1; // 21 Reserved Uint16 rsvd11:1; // 22 Reserved Uint16 rsvd12:1; // 23 Reserved Uint16 rsvd13:1; // 24 Reserved Uint16 rsvd14:1; // 25 Reserved Uint16 rsvd15:1; // 26 Reserved Uint16 rsvd16:1; // 27 Reserved Uint16 rsvd17:1; // 28 Reserved Uint16 rsvd18:1; // 29 Reserved Uint16 rsvd19:1; // 30 Reserved Uint16 rsvd20:1; // 31 Reserved }; union LOCK_REG { Uint32 all; struct LOCK_BITS bit; }; struct ANAREFTRIMA_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMA_REG { Uint32 all; struct ANAREFTRIMA_BITS bit; }; struct ANAREFTRIMB_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMB_REG { Uint32 all; struct ANAREFTRIMB_BITS bit; }; struct ANAREFTRIMC_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMC_REG { Uint32 all; struct ANAREFTRIMC_BITS bit; }; struct ANAREFTRIMD_BITS { // bits description Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim Uint16 IREFTRIM:5; // 15:11 Reference Current Trim Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union ANAREFTRIMD_REG { Uint32 all; struct ANAREFTRIMD_BITS bit; }; struct ANALOG_SUBSYS_REGS { Uint16 rsvd1[32]; // Reserved union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim Register Uint16 rsvd2[2]; // Reserved union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register Uint16 rsvd3[7]; // Reserved union LOCK_REG LOCK; // Lock Register Uint16 rsvd4[6]; // Reserved union ANAREFTRIMA_REG ANAREFTRIMA; // Analog Reference Trim A Register union ANAREFTRIMB_REG ANAREFTRIMB; // Analog Reference Trim B Register union ANAREFTRIMC_REG ANAREFTRIMC; // Analog Reference Trim C Register union ANAREFTRIMD_REG ANAREFTRIMD; // Analog Reference Trim D Register }; //--------------------------------------------------------------------------- // ANALOGSUBSYS External References & Function Declarations: // extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_bgcrc.h // // TITLE: Definitions for the BGCRC registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // BGCRC Individual Register Bit Definitions: struct BGCRC_EN_BITS { // bits description Uint16 START:4; // 3:0 Start Bit used to Kick-off CRC calulations Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:15; // 30:16 Reserved Uint16 RUN_STS:1; // 31 CRC module activity monitor }; union BGCRC_EN_REG { Uint32 all; struct BGCRC_EN_BITS bit; }; struct BGCRC_CTRL1_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 FREE_SOFT:1; // 4 emulation control bit Uint16 rsvd2:11; // 15:5 Reserved Uint16 NMIDIS:4; // 19:16 NMI disable configuration Uint16 rsvd3:12; // 31:20 Reserved }; union BGCRC_CTRL1_REG { Uint32 all; struct BGCRC_CTRL1_BITS bit; }; struct BGCRC_CTRL2_BITS { // bits description Uint16 BLOCK_SIZE:10; // 9:0 block size for memory check Uint16 rsvd1:2; // 11:10 Reserved Uint16 TEST_HALT:4; // 15:12 TEST_HALT configuration Uint16 SCRUB_MODE:4; // 19:16 Scrub mode configuration Uint16 rsvd2:12; // 31:20 Reserved }; union BGCRC_CTRL2_REG { Uint32 all; struct BGCRC_CTRL2_BITS bit; }; struct BGCRC_WD_CFG_BITS { // bits description Uint16 WDDIS:4; // 3:0 CRC Watchdog disable Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union BGCRC_WD_CFG_REG { Uint32 all; struct BGCRC_WD_CFG_BITS bit; }; struct BGCRC_NMIFLG_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CRC_FAIL:1; // 2 CRC computation failed Uint16 UNCORRECTABLE_ERR:1; // 3 Uncorrectable error obtained during memory data read. Uint16 CORRECTABLE_ERR:1; // 4 Correctable ECC error obtained during memory data read. Uint16 WD_UNDERFLOW:1; // 5 CRC/scrubbing completed before BGCRC_WD_MIN Uint16 WD_OVERFLOW:1; // 6 CRC/scrubbing did not complete within BGCRC_WD_MAX Uint16 rsvd3:9; // 15:7 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union BGCRC_NMIFLG_REG { Uint32 all; struct BGCRC_NMIFLG_BITS bit; }; struct BGCRC_NMICLR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CRC_FAIL:1; // 2 CRC_FAIL NMI flag clear Uint16 UNCORRECTABLE_ERR:1; // 3 UNCORRECTABLE_ERR NMI flag clear Uint16 CORRECTABLE_ERR:1; // 4 CORRECTABLE_ERR NMI flag clear Uint16 WD_UNDERFLOW:1; // 5 WD_UNDERFLOW NMI flag clear Uint16 WD_OVERFLOW:1; // 6 WD_OVERFLOW NMI flag clear Uint16 rsvd3:9; // 15:7 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union BGCRC_NMICLR_REG { Uint32 all; struct BGCRC_NMICLR_BITS bit; }; struct BGCRC_NMIFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CRC_FAIL:1; // 2 CRC_FAIL NMI force Uint16 UNCORRECTABLE_ERR:1; // 3 UNCORRECTABLE_ERR NMI force Uint16 CORRECTABLE_ERR:1; // 4 CORRECTABLE_ERR NMI force Uint16 WD_UNDERFLOW:1; // 5 WD_UNDERFLOW NMI force Uint16 WD_OVERFLOW:1; // 6 WD_OVERFLOW NMI force Uint16 rsvd3:9; // 15:7 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union BGCRC_NMIFRC_REG { Uint32 all; struct BGCRC_NMIFRC_BITS bit; }; struct BGCRC_INTEN_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 _TEST_DONE:1; // 1 _TEST_DONE interrupt enable register Uint16 CRC_FAIL:1; // 2 CRC_FAIL interrupt enable register Uint16 UNCORRECTABLE_ERR:1; // 3 UNCORRECTABLE_ERR interrupt enable register Uint16 CORRECTABLE_ERR:1; // 4 CORRECTABLE_ERR interrupt enable register Uint16 WD_UNDERFLOW:1; // 5 WD_UNDERFLOW interrupt enable register Uint16 WD_OVERFLOW:1; // 6 WD_OVERFLOW interrupt enable register Uint16 rsvd2:9; // 15:7 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union BGCRC_INTEN_REG { Uint32 all; struct BGCRC_INTEN_BITS bit; }; struct BGCRC_INTFLG_BITS { // bits description Uint16 INT:1; // 0 Global Interrupt status flag Uint16 _TEST_DONE:1; // 1 _TEST_DONE Interrupt status flag Uint16 CRC_FAIL:1; // 2 CRC computation failed Uint16 UNCORRECTABLE_ERR:1; // 3 Uncorrectable error obtained during memory data read. Uint16 CORRECTABLE_ERR:1; // 4 Correctable ECC error obtained during memory data read. Uint16 WD_UNDERFLOW:1; // 5 CRC/scrubbing completed before BGCRC_WD_MIN Uint16 WD_OVERFLOW:1; // 6 CRC/scrubbing did not complete within BGCRC_WD_MAX Uint16 rsvd1:9; // 15:7 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union BGCRC_INTFLG_REG { Uint32 all; struct BGCRC_INTFLG_BITS bit; }; struct BGCRC_INTCLR_BITS { // bits description Uint16 INT:1; // 0 Global Interrupt clear Uint16 _TEST_DONE:1; // 1 _TEST_DONE Interrupt clear Uint16 CRC_FAIL:1; // 2 CRC_FAIL interrupt clear Uint16 UNCORRECTABLE_ERR:1; // 3 UNCORRECTABLE_ERR interrupt clear Uint16 CORRECTABLE_ERR:1; // 4 CORRECTABLE_ERR interrupt clear Uint16 WD_UNDERFLOW:1; // 5 WD_UNDERFLOW interrupt clear Uint16 WD_OVERFLOW:1; // 6 WD_OVERFLOW interrupt clear Uint16 rsvd1:9; // 15:7 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union BGCRC_INTCLR_REG { Uint32 all; struct BGCRC_INTCLR_BITS bit; }; struct BGCRC_INTFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 _TEST_DONE:1; // 1 _TEST_DONE Interrupt force Uint16 CRC_FAIL:1; // 2 CRC_FAIL interrupt force Uint16 UNCORRECTABLE_ERR:1; // 3 UNCORRECTABLE_ERR interrupt force Uint16 CORRECTABLE_ERR:1; // 4 CORRECTABLE_ERR interrupt force Uint16 WD_UNDERFLOW:1; // 5 WD_UNDERFLOW interrupt force Uint16 WD_OVERFLOW:1; // 6 WD_OVERFLOW interrupt force Uint16 rsvd2:9; // 15:7 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union BGCRC_INTFRC_REG { Uint32 all; struct BGCRC_INTFRC_BITS bit; }; struct BGCRC_LOCK_BITS { // bits description Uint16 BGCRC_EN:1; // 0 Register lock configuration Uint16 BGCRC_CTRL1:1; // 1 Register lock configuration Uint16 BGCRC_CTRL2:1; // 2 Register lock configuration Uint16 BGCRC_START_ADDR:1; // 3 Register lock configuration Uint16 BGCRC_SEED:1; // 4 Register lock configuration Uint16 rsvd1:1; // 5 Reserved Uint16 rsvd2:1; // 6 Reserved Uint16 BGCRC_GOLDEN:1; // 7 Register lock configuration Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 rsvd5:1; // 10 Reserved Uint16 rsvd6:1; // 11 Reserved Uint16 rsvd7:1; // 12 Reserved Uint16 rsvd8:1; // 13 Reserved Uint16 BGCRC_WD_CFG:1; // 14 Register lock configuration Uint16 BGCRC_WD_MIN:1; // 15 Register lock configuration Uint16 BGCRC_WD_MAX:1; // 16 Register lock configuration Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 BGCRC_NMIFRC:1; // 23 Register lock configuration Uint16 rsvd15:1; // 24 Reserved Uint16 rsvd16:1; // 25 Reserved Uint16 BGCRC_INTEN:1; // 26 Register lock configuration Uint16 rsvd17:1; // 27 Reserved Uint16 rsvd18:1; // 28 Reserved Uint16 BGCRC_INTFRC:1; // 29 Register lock configuration Uint16 rsvd19:1; // 30 Reserved Uint16 rsvd20:1; // 31 Reserved }; union BGCRC_LOCK_REG { Uint32 all; struct BGCRC_LOCK_BITS bit; }; struct BGCRC_COMMIT_BITS { // bits description Uint16 BGCRC_EN:1; // 0 Register lock committed Uint16 BGCRC_CTRL1:1; // 1 Register lock committed Uint16 BGCRC_CTRL2:1; // 2 Register lock committed Uint16 BGCRC_START_ADDR:1; // 3 Register lock committed Uint16 BGCRC_SEED:1; // 4 Register lock committed Uint16 rsvd1:1; // 5 Reserved Uint16 rsvd2:1; // 6 Reserved Uint16 BGCRC_GOLDEN:1; // 7 Register lock committed Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 rsvd5:1; // 10 Reserved Uint16 rsvd6:1; // 11 Reserved Uint16 rsvd7:1; // 12 Reserved Uint16 rsvd8:1; // 13 Reserved Uint16 BGCRC_WD_CFG:1; // 14 Register lock committed Uint16 BGCRC_WD_MIN:1; // 15 Register lock committed Uint16 BGCRC_WD_MAX:1; // 16 Register lock committed Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 BGCRC_NMIFRC:1; // 23 Register lock committed Uint16 rsvd15:1; // 24 Reserved Uint16 rsvd16:1; // 25 Reserved Uint16 BGCRC_INTEN:1; // 26 Register lock committed Uint16 rsvd17:1; // 27 Reserved Uint16 rsvd18:1; // 28 Reserved Uint16 BGCRC_INTFRC:1; // 29 Register lock committed Uint16 rsvd19:1; // 30 Reserved Uint16 rsvd20:1; // 31 Reserved }; union BGCRC_COMMIT_REG { Uint32 all; struct BGCRC_COMMIT_BITS bit; }; struct BGCRC_REGS { union BGCRC_EN_REG BGCRC_EN; // BGCRC Enable union BGCRC_CTRL1_REG BGCRC_CTRL1; // BGCRC Control register 1 union BGCRC_CTRL2_REG BGCRC_CTRL2; // BGCRC Control register 2 Uint32 BGCRC_START_ADDR; // Start address for the BGCRC check Uint32 BGCRC_SEED; // Seed for CRC calculation Uint16 rsvd1[4]; // Reserved Uint32 BGCRC_GOLDEN; // Golden CRC to be compared against Uint32 BGCRC_RESULT; // CRC calculated Uint32 BGCRC_CURR_ADDR; // Current address regsiter Uint16 rsvd2[8]; // Reserved union BGCRC_WD_CFG_REG BGCRC_WD_CFG; // BGCRC windowed watchdog configuration Uint32 BGCRC_WD_MIN; // BGCRC windowed watchdog min value Uint32 BGCRC_WD_MAX; // BGCRC windowed watchdog max value Uint32 BGCRC_WD_CNT; // BGCRC windowed watchdog count Uint16 rsvd3[6]; // Reserved union BGCRC_NMIFLG_REG BGCRC_NMIFLG; // BGCRC NMI flag register union BGCRC_NMICLR_REG BGCRC_NMICLR; // BGCRC NMI flag clear register union BGCRC_NMIFRC_REG BGCRC_NMIFRC; // BGCRC NMI flag force register Uint16 rsvd4[4]; // Reserved union BGCRC_INTEN_REG BGCRC_INTEN; // Interrupt enable union BGCRC_INTFLG_REG BGCRC_INTFLG; // Interrupt flag union BGCRC_INTCLR_REG BGCRC_INTCLR; // Interrupt flag clear union BGCRC_INTFRC_REG BGCRC_INTFRC; // Interrupt flag force union BGCRC_LOCK_REG BGCRC_LOCK; // BGCRC register map lockconfiguration union BGCRC_COMMIT_REG BGCRC_COMMIT; // BGCRC register map commit configuration }; //--------------------------------------------------------------------------- // BGCRC External References & Function Declarations: // extern volatile struct BGCRC_REGS BgcrcCla1Regs; extern volatile struct BGCRC_REGS BgcrcCpuRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_cla.h // // TITLE: Definitions for the CLA registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CLA Individual Register Bit Definitions: struct MCTL_BITS { // bits description Uint16 HARDRESET:1; // 0 Hard Reset Uint16 SOFTRESET:1; // 1 Soft Reset Uint16 IACKE:1; // 2 IACK enable Uint16 rsvd1:13; // 15:3 Reserved }; union MCTL_REG { Uint16 all; struct MCTL_BITS bit; }; struct SOFTINTEN_BITS { // bits description Uint16 TASK1:1; // 0 Configure Software Interrupt or End of Task interrupt. Uint16 TASK2:1; // 1 Configure Software Interrupt or End of Task interrupt. Uint16 TASK3:1; // 2 Configure Software Interrupt or End of Task interrupt. Uint16 TASK4:1; // 3 Configure Software Interrupt or End of Task interrupt. Uint16 TASK5:1; // 4 Configure Software Interrupt or End of Task interrupt. Uint16 TASK6:1; // 5 Configure Software Interrupt or End of Task interrupt. Uint16 TASK7:1; // 6 Configure Software Interrupt or End of Task interrupt. Uint16 TASK8:1; // 7 Configure Software Interrupt or End of Task interrupt. Uint16 rsvd1:8; // 15:8 Reserved }; union SOFTINTEN_REG { Uint16 all; struct SOFTINTEN_BITS bit; }; struct MSTSBGRND_BITS { // bits description Uint16 RUN:1; // 0 Background task run status bit. Uint16 BGINTM:1; // 1 Indicates whether background task can be interrupted. Uint16 BGOVF:1; // 2 background task harware trigger overflow. Uint16 rsvd1:13; // 15:3 Reserved }; union MSTSBGRND_REG { Uint16 all; struct MSTSBGRND_BITS bit; }; struct MCTLBGRND_BITS { // bits description Uint16 BGSTART:1; // 0 Background task start bit Uint16 TRIGEN:1; // 1 Background task hardware trigger enable Uint16 rsvd1:13; // 14:2 Reserved Uint16 BGEN:1; // 15 Enable background task }; union MCTLBGRND_REG { Uint16 all; struct MCTLBGRND_BITS bit; }; struct MIFR_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Flag Uint16 INT2:1; // 1 Task 2 Interrupt Flag Uint16 INT3:1; // 2 Task 3 Interrupt Flag Uint16 INT4:1; // 3 Task 4 Interrupt Flag Uint16 INT5:1; // 4 Task 5 Interrupt Flag Uint16 INT6:1; // 5 Task 6 Interrupt Flag Uint16 INT7:1; // 6 Task 7 Interrupt Flag Uint16 INT8:1; // 7 Task 8 Interrupt Flag Uint16 rsvd1:8; // 15:8 Reserved }; union MIFR_REG { Uint16 all; struct MIFR_BITS bit; }; struct MIOVF_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Uint16 rsvd1:8; // 15:8 Reserved }; union MIOVF_REG { Uint16 all; struct MIOVF_BITS bit; }; struct MIFRC_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Force Uint16 INT2:1; // 1 Task 2 Interrupt Force Uint16 INT3:1; // 2 Task 3 Interrupt Force Uint16 INT4:1; // 3 Task 4 Interrupt Force Uint16 INT5:1; // 4 Task 5 Interrupt Force Uint16 INT6:1; // 5 Task 6 Interrupt Force Uint16 INT7:1; // 6 Task 7 Interrupt Force Uint16 INT8:1; // 7 Task 8 Interrupt Force Uint16 rsvd1:8; // 15:8 Reserved }; union MIFRC_REG { Uint16 all; struct MIFRC_BITS bit; }; struct MICLR_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear Uint16 rsvd1:8; // 15:8 Reserved }; union MICLR_REG { Uint16 all; struct MICLR_BITS bit; }; struct MICLROVF_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear Uint16 rsvd1:8; // 15:8 Reserved }; union MICLROVF_REG { Uint16 all; struct MICLROVF_BITS bit; }; struct MIER_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Interrupt Enable Uint16 INT2:1; // 1 Task 2 Interrupt Enable Uint16 INT3:1; // 2 Task 3 Interrupt Enable Uint16 INT4:1; // 3 Task 4 Interrupt Enable Uint16 INT5:1; // 4 Task 5 Interrupt Enable Uint16 INT6:1; // 5 Task 6 Interrupt Enable Uint16 INT7:1; // 6 Task 7 Interrupt Enable Uint16 INT8:1; // 7 Task 8 Interrupt Enable Uint16 rsvd1:8; // 15:8 Reserved }; union MIER_REG { Uint16 all; struct MIER_BITS bit; }; struct MIRUN_BITS { // bits description Uint16 INT1:1; // 0 Task 1 Run Status Uint16 INT2:1; // 1 Task 2 Run Status Uint16 INT3:1; // 2 Task 3 Run Status Uint16 INT4:1; // 3 Task 4 Run Status Uint16 INT5:1; // 4 Task 5 Run Status Uint16 INT6:1; // 5 Task 6 Run Status Uint16 INT7:1; // 6 Task 7 Run Status Uint16 INT8:1; // 7 Task 8 Run Status Uint16 rsvd1:8; // 15:8 Reserved }; union MIRUN_REG { Uint16 all; struct MIRUN_BITS bit; }; struct MSTF_BITS { // bits description Uint16 LVF:1; // 0 Latched Overflow Flag Uint16 LUF:1; // 1 Latched Underflow Flag Uint16 NF:1; // 2 Negative Float Flag Uint16 ZF:1; // 3 Zero Float Flag Uint16 rsvd1:2; // 5:4 Reserved Uint16 TF:1; // 6 Test Flag Uint16 rsvd2:2; // 8:7 Reserved Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode Uint16 rsvd3:1; // 10 Reserved Uint16 MEALLOW:1; // 11 MEALLOW Status Uint32 _RPC:16; // 27:12 Return PC Uint16 rsvd4:4; // 31:28 Reserved }; union MSTF_REG { Uint32 all; struct MSTF_BITS bit; }; struct MPSACTL_BITS { // bits description Uint16 MPABSTART:1; // 0 Start logging PAB onto PSA1 Uint16 MPABCYC:1; // 1 PAB logging into PSA1 is on every cycle or when PAB changes. Uint16 MDWDBSTART:1; // 2 Start logging DWDB onto PSA2 Uint16 MDWDBCYC:1; // 3 DWDB logging into PSA2 is on every cycle. Uint16 MPSA1CLEAR:1; // 4 PSA1 clear Uint16 MPSA2CLEAR:1; // 5 PSA2 Clear Uint16 MPSA2CFG:2; // 7:6 PSA2 Polynomial Configuration Uint16 rsvd1:8; // 15:8 Reserved }; union MPSACTL_REG { Uint16 all; struct MPSACTL_BITS bit; }; union MR_REG { Uint32 i32; float f32; }; struct CLA_REGS { Uint16 MVECT1; // Task Interrupt Vector Uint16 MVECT2; // Task Interrupt Vector Uint16 MVECT3; // Task Interrupt Vector Uint16 MVECT4; // Task Interrupt Vector Uint16 MVECT5; // Task Interrupt Vector Uint16 MVECT6; // Task Interrupt Vector Uint16 MVECT7; // Task Interrupt Vector Uint16 MVECT8; // Task Interrupt Vector Uint16 rsvd1[8]; // Reserved union MCTL_REG MCTL; // Control Register Uint16 rsvd2[10]; // Reserved Uint16 MVECTBGRNDACTIVE; // Active register for MVECTBGRND. union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register union MSTSBGRND_REG MSTSBGRND; // Status register for the back ground task. union MCTLBGRND_REG MCTLBGRND; // Control register for the back ground task. Uint16 MVECTBGRND; // Vector for the back ground task. union MIFR_REG MIFR; // Interrupt Flag Register union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register union MIFRC_REG MIFRC; // Interrupt Force Register union MICLR_REG MICLR; // Interrupt Flag Clear Register union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register union MIER_REG MIER; // Interrupt Enable Register union MIRUN_REG MIRUN; // Interrupt Run Status Register Uint16 rsvd3; // Reserved Uint16 MPC; // CLA Program Counter Uint16 rsvd4; // Reserved Uint16 MAR0; // CLA Auxiliary Register 0 Uint16 MAR1; // CLA Auxiliary Register 1 Uint16 rsvd5[2]; // Reserved union MSTF_REG MSTF; // CLA Floating-Point Status Register union MR_REG MR0; // CLA Floating-Point Result Register 0 Uint16 rsvd6[2]; // Reserved union MR_REG MR1; // CLA Floating-Point Result Register 1 Uint16 rsvd7[2]; // Reserved union MR_REG MR2; // CLA Floating-Point Result Register 2 Uint16 rsvd8[2]; // Reserved union MR_REG MR3; // CLA Floating-Point Result Register 3 Uint16 rsvd9[4]; // Reserved union MPSACTL_REG MPSACTL; // CLA PSA Control Register Uint16 rsvd10; // Reserved Uint32 MPSA1; // CLA PSA1 Register Uint32 MPSA2; // CLA PSA2 Register }; struct SOFTINTFRC_BITS { // bits description Uint16 TASK1:1; // 0 Force CLA software interrupt for the corresponding task. Uint16 TASK2:1; // 1 Force CLA software interrupt for the corresponding task. Uint16 TASK3:1; // 2 Force CLA software interrupt for the corresponding task. Uint16 TASK4:1; // 3 Force CLA software interrupt for the corresponding task. Uint16 TASK5:1; // 4 Force CLA software interrupt for the corresponding task. Uint16 TASK6:1; // 5 Force CLA software interrupt for the corresponding task. Uint16 TASK7:1; // 6 Force CLA software interrupt for the corresponding task. Uint16 TASK8:1; // 7 Force CLA software interrupt for the corresponding task. Uint16 rsvd1:8; // 15:8 Reserved }; union SOFTINTFRC_REG { Uint16 all; struct SOFTINTFRC_BITS bit; }; struct CLA_ONLY_REGS { Uint16 rsvd1[128]; // Reserved Uint16 MVECTBGRNDACTIVE; // Active register for MVECTBGRND. Uint16 rsvd2[63]; // Reserved union MPSACTL_REG MPSACTL; // CLA PSA Control Register Uint16 rsvd3; // Reserved Uint32 MPSA1; // CLA PSA1 Register Uint32 MPSA2; // CLA PSA2 Register Uint16 rsvd4[26]; // Reserved union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register Uint16 rsvd5; // Reserved union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register }; struct CLA_SOFTINT_REGS { union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register Uint16 rsvd1; // Reserved union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register }; //--------------------------------------------------------------------------- // CLA External References & Function Declarations: // extern volatile struct CLA_REGS Cla1Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_clb.h // // TITLE: Definitions for the CLB registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CLB Individual Register Bit Definitions: struct CLB_COUNT_RESET_BITS { // bits description Uint16 SEL_0:5; // 4:0 Count Reset Select 0 Uint16 SEL_1:5; // 9:5 Count Reset Select 1 Uint16 SEL_2:5; // 14:10 Count Reset Select 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_COUNT_RESET_REG { Uint32 all; struct CLB_COUNT_RESET_BITS bit; }; struct CLB_COUNT_MODE_1_BITS { // bits description Uint16 SEL_0:5; // 4:0 Counter mode 1 select 0 Uint16 SEL_1:5; // 9:5 Counter mode 1 select 1 Uint16 SEL_2:5; // 14:10 Counter mode 1 select 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_COUNT_MODE_1_REG { Uint32 all; struct CLB_COUNT_MODE_1_BITS bit; }; struct CLB_COUNT_MODE_0_BITS { // bits description Uint16 SEL_0:5; // 4:0 Counter mode 0 select 0 Uint16 SEL_1:5; // 9:5 Counter mode 0 select 1 Uint16 SEL_2:5; // 14:10 Counter mode 0 select 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_COUNT_MODE_0_REG { Uint32 all; struct CLB_COUNT_MODE_0_BITS bit; }; struct CLB_COUNT_EVENT_BITS { // bits description Uint16 SEL_0:5; // 4:0 Counter event select 0 Uint16 SEL_1:5; // 9:5 Counter event select 1 Uint16 SEL_2:5; // 14:10 Counter event select 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_COUNT_EVENT_REG { Uint32 all; struct CLB_COUNT_EVENT_BITS bit; }; struct CLB_FSM_EXTRA_IN0_BITS { // bits description Uint16 SEL_0:5; // 4:0 FSM extra ext input select 0 Uint16 SEL_1:5; // 9:5 FSM extra ext input select 1 Uint16 SEL_2:5; // 14:10 FSM extra ext input select 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_FSM_EXTRA_IN0_REG { Uint32 all; struct CLB_FSM_EXTRA_IN0_BITS bit; }; struct CLB_FSM_EXTERNAL_IN0_BITS { // bits description Uint16 SEL_0:5; // 4:0 FSM EXT_IN0 select input for unit 0 Uint16 SEL_1:5; // 9:5 FSM EXT_IN0 select input for unit 1 Uint16 SEL_2:5; // 14:10 FSM EXT_IN0 select input for unit 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_FSM_EXTERNAL_IN0_REG { Uint32 all; struct CLB_FSM_EXTERNAL_IN0_BITS bit; }; struct CLB_FSM_EXTERNAL_IN1_BITS { // bits description Uint16 SEL_0:5; // 4:0 FSM EXT_IN1 select input for unit 0 Uint16 SEL_1:5; // 9:5 FSM EXT_IN1 select input for unit 1 Uint16 SEL_2:5; // 14:10 FSM EXT_IN1 select input for unit 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_FSM_EXTERNAL_IN1_REG { Uint32 all; struct CLB_FSM_EXTERNAL_IN1_BITS bit; }; struct CLB_FSM_EXTRA_IN1_BITS { // bits description Uint16 SEL_0:5; // 4:0 FSM extra ext input select 0 Uint16 SEL_1:5; // 9:5 FSM extra ext input select 1 Uint16 SEL_2:5; // 14:10 FSM extra ext input select 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_FSM_EXTRA_IN1_REG { Uint32 all; struct CLB_FSM_EXTRA_IN1_BITS bit; }; struct CLB_LUT4_IN0_BITS { // bits description Uint16 SEL_0:5; // 4:0 Select inputs for unit 0 Uint16 SEL_1:5; // 9:5 Select inputs for unit 1 Uint16 SEL_2:5; // 14:10 Select inputs for unit 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_LUT4_IN0_REG { Uint32 all; struct CLB_LUT4_IN0_BITS bit; }; struct CLB_LUT4_IN1_BITS { // bits description Uint16 SEL_0:5; // 4:0 Select inputs for unit 0 Uint16 SEL_1:5; // 9:5 Select inputs for unit 1 Uint16 SEL_2:5; // 14:10 Select inputs for unit 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_LUT4_IN1_REG { Uint32 all; struct CLB_LUT4_IN1_BITS bit; }; struct CLB_LUT4_IN2_BITS { // bits description Uint16 SEL_0:5; // 4:0 Select inputs for unit 0 Uint16 SEL_1:5; // 9:5 Select inputs for unit 1 Uint16 SEL_2:5; // 14:10 Select inputs for unit 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_LUT4_IN2_REG { Uint32 all; struct CLB_LUT4_IN2_BITS bit; }; struct CLB_LUT4_IN3_BITS { // bits description Uint16 SEL_0:5; // 4:0 Select inputs for unit 0 Uint16 SEL_1:5; // 9:5 Select inputs for unit 1 Uint16 SEL_2:5; // 14:10 Select inputs for unit 2 Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_LUT4_IN3_REG { Uint32 all; struct CLB_LUT4_IN3_BITS bit; }; struct CLB_FSM_LUT_FN1_0_BITS { // bits description Uint16 FN0:16; // 15:0 FSM LUT output function for unit 0 Uint16 FN1:16; // 31:16 FSM LUT output function for unit 1 }; union CLB_FSM_LUT_FN1_0_REG { Uint32 all; struct CLB_FSM_LUT_FN1_0_BITS bit; }; struct CLB_FSM_LUT_FN2_BITS { // bits description Uint16 FN1:16; // 15:0 FSM LUT output function for unit 2 Uint16 rsvd1:16; // 31:16 Reserved }; union CLB_FSM_LUT_FN2_REG { Uint32 all; struct CLB_FSM_LUT_FN2_BITS bit; }; struct CLB_LUT4_FN1_0_BITS { // bits description Uint16 FN0:16; // 15:0 LUT4 output function for unit 0 Uint16 FN1:16; // 31:16 LUT4 output function for unit 1 }; union CLB_LUT4_FN1_0_REG { Uint32 all; struct CLB_LUT4_FN1_0_BITS bit; }; struct CLB_LUT4_FN2_BITS { // bits description Uint16 FN1:16; // 15:0 LUT4 output function for unit 2 Uint16 rsvd1:16; // 31:16 Reserved }; union CLB_LUT4_FN2_REG { Uint32 all; struct CLB_LUT4_FN2_BITS bit; }; struct CLB_FSM_NEXT_STATE_0_BITS { // bits description Uint16 S0:16; // 15:0 FSM next state function for S0 Uint16 S1:16; // 31:16 FSM next state function for S1 }; union CLB_FSM_NEXT_STATE_0_REG { Uint32 all; struct CLB_FSM_NEXT_STATE_0_BITS bit; }; struct CLB_FSM_NEXT_STATE_1_BITS { // bits description Uint16 S0:16; // 15:0 FSM next state function for S0 Uint16 S1:16; // 31:16 FSM next state function for S1 }; union CLB_FSM_NEXT_STATE_1_REG { Uint32 all; struct CLB_FSM_NEXT_STATE_1_BITS bit; }; struct CLB_FSM_NEXT_STATE_2_BITS { // bits description Uint16 S0:16; // 15:0 FSM next state function for S0 Uint16 S1:16; // 31:16 FSM next state function for S1 }; union CLB_FSM_NEXT_STATE_2_REG { Uint32 all; struct CLB_FSM_NEXT_STATE_2_BITS bit; }; struct CLB_MISC_CONTROL_BITS { // bits description Uint16 COUNT_ADD_SHIFT_0:1; // 0 Add/Shift for counter 0 Uint16 COUNT_DIR_0:1; // 1 Direction for counter 0 Uint16 COUNT_EVENT_CTRL_0:1; // 2 Event control for counter 0 Uint16 COUNT_ADD_SHIFT_1:1; // 3 Add/Shift for counter 1 Uint16 COUNT_DIR_1:1; // 4 Direction for counter 1 Uint16 COUNT_EVENT_CTRL_1:1; // 5 Event control for counter 1 Uint16 COUNT_ADD_SHIFT_2:1; // 6 Add/Shift for counter 2 Uint16 COUNT_DIR_2:1; // 7 Direction for counter 2 Uint16 COUNT_EVENT_CTRL_2:1; // 8 Event control for counter 2 Uint16 COUNT_SERIALIZER_0:1; // 9 Serializer enable 0 Uint16 COUNT_SERIALIZER_1:1; // 10 Serializer enable 1 Uint16 COUNT_SERIALIZER_2:1; // 11 Serializer enable 2 Uint16 FSM_EXTRA_SEL0_0:1; // 12 FSM extra_sel0 for 0 Uint16 FSM_EXTRA_SEL1_0:1; // 13 FSM extra_sel1 for 0 Uint16 FSM_EXTRA_SEL0_1:1; // 14 FSM extra_sel0 for 1 Uint16 FSM_EXTRA_SEL1_1:1; // 15 FSM extra_sel1 for 1 Uint16 FSM_EXTRA_SEL0_2:1; // 16 FSM extra_sel0 for 2 Uint16 FSM_EXTRA_SEL1_2:1; // 17 FSM extra_sel1 for 2 Uint16 COUNT0_MATCH1_TAP_EN:1; // 18 Match1 Tap Enable for Counter 0 Uint16 COUNT1_MATCH1_TAP_EN:1; // 19 Match1 Tap Enable for Counter 1 Uint16 COUNT2_MATCH1_TAP_EN:1; // 20 Match1 Tap Enable for Counter 2 Uint16 COUNT0_MATCH2_TAP_EN:1; // 21 Match2 Tap Enable for Counter 0 Uint16 COUNT1_MATCH2_TAP_EN:1; // 22 Match2 Tap Enable for Counter 1 Uint16 COUNT2_MATCH2_TAP_EN:1; // 23 Match2 Tap Enable for Counter 2 Uint16 COUNT0_LFSR_EN:1; // 24 Enable LFSR mode for Counter 0 Uint16 COUNT1_LFSR_EN:1; // 25 Enable LFSR mode for Counter 1 Uint16 COUNT2_LFSR_EN:1; // 26 Enable LFSR mode for Counter 2 Uint16 rsvd1:5; // 31:27 Reserved }; union CLB_MISC_CONTROL_REG { Uint32 all; struct CLB_MISC_CONTROL_BITS bit; }; struct CLB_OUTPUT_LUT_0_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_0_REG { Uint32 all; struct CLB_OUTPUT_LUT_0_BITS bit; }; struct CLB_OUTPUT_LUT_1_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_1_REG { Uint32 all; struct CLB_OUTPUT_LUT_1_BITS bit; }; struct CLB_OUTPUT_LUT_2_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_2_REG { Uint32 all; struct CLB_OUTPUT_LUT_2_BITS bit; }; struct CLB_OUTPUT_LUT_3_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_3_REG { Uint32 all; struct CLB_OUTPUT_LUT_3_BITS bit; }; struct CLB_OUTPUT_LUT_4_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_4_REG { Uint32 all; struct CLB_OUTPUT_LUT_4_BITS bit; }; struct CLB_OUTPUT_LUT_5_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_5_REG { Uint32 all; struct CLB_OUTPUT_LUT_5_BITS bit; }; struct CLB_OUTPUT_LUT_6_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_6_REG { Uint32 all; struct CLB_OUTPUT_LUT_6_BITS bit; }; struct CLB_OUTPUT_LUT_7_BITS { // bits description Uint16 IN0:5; // 4:0 Select value for IN0 of output LUT Uint16 IN1:5; // 9:5 Select value for IN1 of output LUT Uint16 IN2:5; // 14:10 Select value for IN2 of output LUT Uint32 FN:8; // 22:15 Output function for output LUT Uint16 rsvd1:9; // 31:23 Reserved }; union CLB_OUTPUT_LUT_7_REG { Uint32 all; struct CLB_OUTPUT_LUT_7_BITS bit; }; struct CLB_HLC_EVENT_SEL_BITS { // bits description Uint16 EVENT0_SEL:5; // 4:0 Event Select 0 Uint16 EVENT1_SEL:5; // 9:5 Event Select 1 Uint16 EVENT2_SEL:5; // 14:10 Event Select 2 Uint32 EVENT3_SEL:5; // 19:15 Event Select 3 Uint16 ALT_EVENT0_SEL:1; // 20 Event Select 3 Uint16 ALT_EVENT1_SEL:1; // 21 Event Select 3 Uint16 ALT_EVENT2_SEL:1; // 22 Event Select 3 Uint16 ALT_EVENT3_SEL:1; // 23 Event Select 3 Uint16 rsvd1:8; // 31:24 Reserved }; union CLB_HLC_EVENT_SEL_REG { Uint32 all; struct CLB_HLC_EVENT_SEL_BITS bit; }; struct CLB_COUNT_MATCH_TAP_SEL_BITS { // bits description Uint16 COUNT0_MATCH1:5; // 4:0 Match1 tap select for Counter 0 Uint16 COUNT1_MATCH1:5; // 9:5 Match1 tap select for Counter 1 Uint16 COUNT2_MATCH1:5; // 14:10 Match1 tap select for Counter 2 Uint16 rsvd1:1; // 15 Reserved Uint16 COUNT0_MATCH2:5; // 20:16 Match2 tap select for Counter 0 Uint16 COUNT1_MATCH2:5; // 25:21 Match2 tap select for Counter 1 Uint16 COUNT2_MATCH2:5; // 30:26 Match2 tap select for Counter 2 Uint16 rsvd2:1; // 31 Reserved }; union CLB_COUNT_MATCH_TAP_SEL_REG { Uint32 all; struct CLB_COUNT_MATCH_TAP_SEL_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_0_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_0_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_0_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_1_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_1_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_1_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_2_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_2_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_2_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_3_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_3_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_3_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_4_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_4_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_4_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_5_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_5_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_5_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_6_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_6_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_6_BITS bit; }; struct CLB_OUTPUT_COND_CTRL_7_BITS { // bits description Uint16 LEVEL_1_SEL:1; // 0 Level 1 Mux Select Uint16 LEVEL_2_SEL:2; // 2:1 Level 2 Mux Select Uint16 LEVEL_3_SEL:2; // 4:3 Level 3 Mux Select Uint16 SEL_GATING_CTRL:3; // 7:5 Gating control mux select Uint16 SEL_RELEASE_CTRL:3; // 10:8 Releast control mux select Uint16 HW_GATING_CTRL_SEL:1; // 11 Select HW for gating control Uint16 HW_RLS_CTRL_SEL:1; // 12 Select HW for release control Uint16 SEL_RAW_IN:1; // 13 Select Input for Uint16 ASYNC_COND_EN:1; // 14 Enable for conditioning Uint16 rsvd1:1; // 15 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_OUTPUT_COND_CTRL_7_REG { Uint32 all; struct CLB_OUTPUT_COND_CTRL_7_BITS bit; }; struct CLB_MISC_ACCESS_CTRL_BITS { // bits description Uint16 SPIEN:1; // 0 Enable CLB SPI Buffer feature Uint16 BLKEN:1; // 1 Block Register write Uint16 rsvd1:14; // 15:2 Reserved }; union CLB_MISC_ACCESS_CTRL_REG { Uint16 all; struct CLB_MISC_ACCESS_CTRL_BITS bit; }; struct CLB_SPI_DATA_CTRL_HI_BITS { // bits description Uint16 STRB:5; // 4:0 Select value for strobe Uint16 rsvd1:3; // 7:5 Reserved Uint16 SHIFT:5; // 12:8 Shift value select Uint16 rsvd2:3; // 15:13 Reserved }; union CLB_SPI_DATA_CTRL_HI_REG { Uint16 all; struct CLB_SPI_DATA_CTRL_HI_BITS bit; }; struct CLB_LOGIC_CONFIG_REGS { Uint16 rsvd1[2]; // Reserved union CLB_COUNT_RESET_REG CLB_COUNT_RESET; // Counter Block RESET union CLB_COUNT_MODE_1_REG CLB_COUNT_MODE_1; // Counter Block MODE_1 union CLB_COUNT_MODE_0_REG CLB_COUNT_MODE_0; // Counter Block MODE_0 union CLB_COUNT_EVENT_REG CLB_COUNT_EVENT; // Counter Block EVENT union CLB_FSM_EXTRA_IN0_REG CLB_FSM_EXTRA_IN0; // FSM Extra EXT_IN0 union CLB_FSM_EXTERNAL_IN0_REG CLB_FSM_EXTERNAL_IN0; // FSM EXT_IN0 union CLB_FSM_EXTERNAL_IN1_REG CLB_FSM_EXTERNAL_IN1; // FSM_EXT_IN1 union CLB_FSM_EXTRA_IN1_REG CLB_FSM_EXTRA_IN1; // FSM Extra_EXT_IN1 union CLB_LUT4_IN0_REG CLB_LUT4_IN0; // LUT4_0/1/2 IN0 input source union CLB_LUT4_IN1_REG CLB_LUT4_IN1; // LUT4_0/1/2 IN1 input source union CLB_LUT4_IN2_REG CLB_LUT4_IN2; // LUT4_0/1/2 IN2 input source union CLB_LUT4_IN3_REG CLB_LUT4_IN3; // LUT4_0/1/2 IN3 input source Uint16 rsvd2[2]; // Reserved union CLB_FSM_LUT_FN1_0_REG CLB_FSM_LUT_FN1_0; // LUT function for FSM Unit 1 and Unit 0 union CLB_FSM_LUT_FN2_REG CLB_FSM_LUT_FN2; // LUT function for FSM Unit 2 union CLB_LUT4_FN1_0_REG CLB_LUT4_FN1_0; // LUT function for LUT4 block of Unit 1 and 0 union CLB_LUT4_FN2_REG CLB_LUT4_FN2; // LUT function for LUT4 block of Unit 2 union CLB_FSM_NEXT_STATE_0_REG CLB_FSM_NEXT_STATE_0; // FSM Next state equations for Unit 0 union CLB_FSM_NEXT_STATE_1_REG CLB_FSM_NEXT_STATE_1; // FSM Next state equations for Unit 1 union CLB_FSM_NEXT_STATE_2_REG CLB_FSM_NEXT_STATE_2; // FSM Next state equations for Unit 2 union CLB_MISC_CONTROL_REG CLB_MISC_CONTROL; // Static controls for Ctr,FSM union CLB_OUTPUT_LUT_0_REG CLB_OUTPUT_LUT_0; // Inp Sel, LUT fns for Out0 union CLB_OUTPUT_LUT_1_REG CLB_OUTPUT_LUT_1; // Inp Sel, LUT fns for Out1 union CLB_OUTPUT_LUT_2_REG CLB_OUTPUT_LUT_2; // Inp Sel, LUT fns for Out2 union CLB_OUTPUT_LUT_3_REG CLB_OUTPUT_LUT_3; // Inp Sel, LUT fns for Out3 union CLB_OUTPUT_LUT_4_REG CLB_OUTPUT_LUT_4; // Inp Sel, LUT fns for Out4 union CLB_OUTPUT_LUT_5_REG CLB_OUTPUT_LUT_5; // Inp Sel, LUT fns for Out5 union CLB_OUTPUT_LUT_6_REG CLB_OUTPUT_LUT_6; // Inp Sel, LUT fns for Out6 union CLB_OUTPUT_LUT_7_REG CLB_OUTPUT_LUT_7; // Inp Sel, LUT fns for Out7 union CLB_HLC_EVENT_SEL_REG CLB_HLC_EVENT_SEL; // Event Selector register for the High Level controller union CLB_COUNT_MATCH_TAP_SEL_REG CLB_COUNT_MATCH_TAP_SEL; // Counter tap values for match1 and match2 outputs union CLB_OUTPUT_COND_CTRL_0_REG CLB_OUTPUT_COND_CTRL_0; // Output conditioning control for output 0 union CLB_OUTPUT_COND_CTRL_1_REG CLB_OUTPUT_COND_CTRL_1; // Output conditioning control for output 1 union CLB_OUTPUT_COND_CTRL_2_REG CLB_OUTPUT_COND_CTRL_2; // Output conditioning control for output 2 union CLB_OUTPUT_COND_CTRL_3_REG CLB_OUTPUT_COND_CTRL_3; // Output conditioning control for output 3 union CLB_OUTPUT_COND_CTRL_4_REG CLB_OUTPUT_COND_CTRL_4; // Output conditioning control for output 4 union CLB_OUTPUT_COND_CTRL_5_REG CLB_OUTPUT_COND_CTRL_5; // Output conditioning control for output 5 union CLB_OUTPUT_COND_CTRL_6_REG CLB_OUTPUT_COND_CTRL_6; // Output conditioning control for output 6 union CLB_OUTPUT_COND_CTRL_7_REG CLB_OUTPUT_COND_CTRL_7; // Output conditioning control for output 7 union CLB_MISC_ACCESS_CTRL_REG CLB_MISC_ACCESS_CTRL; // Miscellaneous Access and enable control union CLB_SPI_DATA_CTRL_HI_REG CLB_SPI_DATA_CTRL_HI; // CLB to SPI buffer control High }; struct CLB_LOAD_EN_BITS { // bits description Uint16 LOAD_EN:1; // 0 Load Enable Uint16 GLOBAL_EN:1; // 1 Global Enable Uint16 STOP:1; // 2 Debug stop control Uint16 NMI_EN:1; // 3 NMI output enable Uint16 PIPELINE_EN:1; // 4 Enable input pipelining Uint16 rsvd1:11; // 15:5 Reserved }; union CLB_LOAD_EN_REG { Uint16 all; struct CLB_LOAD_EN_BITS bit; }; struct CLB_LOAD_ADDR_BITS { // bits description Uint16 ADDR:6; // 5:0 Indirect Address Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_LOAD_ADDR_REG { Uint32 all; struct CLB_LOAD_ADDR_BITS bit; }; struct CLB_INPUT_FILTER_BITS { // bits description Uint16 FIN0:2; // 1:0 Input filter control 0 Uint16 FIN1:2; // 3:2 Input filter control 1 Uint16 FIN2:2; // 5:4 Input filter control 2 Uint16 FIN3:2; // 7:6 Input filter control 3 Uint16 FIN4:2; // 9:8 Input filter control 4 Uint16 FIN5:2; // 11:10 Input filter control 5 Uint16 FIN6:2; // 13:12 Input filter control 6 Uint16 FIN7:2; // 15:14 Input filter control 7 Uint16 SYNC0:1; // 16 Synchronizer control 0 Uint16 SYNC1:1; // 17 Synchronizer control 1 Uint16 SYNC2:1; // 18 Synchronizer control 2 Uint16 SYNC3:1; // 19 Synchronizer control 3 Uint16 SYNC4:1; // 20 Synchronizer control 4 Uint16 SYNC5:1; // 21 Synchronizer control 5 Uint16 SYNC6:1; // 22 Synchronizer control 6 Uint16 SYNC7:1; // 23 Synchronizer control 7 Uint16 PIPE0:1; // 24 Enable pipeline 0 Uint16 PIPE1:1; // 25 Enable pipeline 1 Uint16 PIPE2:1; // 26 Enable pipeline 2 Uint16 PIPE3:1; // 27 Enable pipeline 3 Uint16 PIPE4:1; // 28 Enable pipeline 4 Uint16 PIPE5:1; // 29 Enable pipeline 5 Uint16 PIPE6:1; // 30 Enable pipeline 6 Uint16 PIPE7:1; // 31 Enable pipeline 7 }; union CLB_INPUT_FILTER_REG { Uint32 all; struct CLB_INPUT_FILTER_BITS bit; }; struct CLB_IN_MUX_SEL_0_BITS { // bits description Uint16 SEL_GP_IN_0:1; // 0 Select GP register 0 Uint16 SEL_GP_IN_1:1; // 1 Select GP register 1 Uint16 SEL_GP_IN_2:1; // 2 Select GP register 2 Uint16 SEL_GP_IN_3:1; // 3 Select GP register 3 Uint16 SEL_GP_IN_4:1; // 4 Select GP register 4 Uint16 SEL_GP_IN_5:1; // 5 Select GP register 5 Uint16 SEL_GP_IN_6:1; // 6 Select GP register 6 Uint16 SEL_GP_IN_7:1; // 7 Select GP register 7 Uint16 rsvd1:8; // 15:8 Reserved Uint16 SW_RLS_CTRL_0:1; // 16 Software release control 0 Uint16 SW_RLS_CTRL_1:1; // 17 Software release control 1 Uint16 SW_RLS_CTRL_2:1; // 18 Software release control 2 Uint16 SW_RLS_CTRL_3:1; // 19 Software release control 3 Uint16 SW_RLS_CTRL_4:1; // 20 Software release control 4 Uint16 SW_RLS_CTRL_5:1; // 21 Software release control 5 Uint16 SW_RLS_CTRL_6:1; // 22 Software release control 6 Uint16 SW_RLS_CTRL_7:1; // 23 Software release control 7 Uint16 SW_GATING_CTRL_0:1; // 24 Software gating control 0 Uint16 SW_GATING_CTRL_1:1; // 25 Software gating control 1 Uint16 SW_GATING_CTRL_2:1; // 26 Software gating control 2 Uint16 SW_GATING_CTRL_3:1; // 27 Software gating control 3 Uint16 SW_GATING_CTRL_4:1; // 28 Software gating control 4 Uint16 SW_GATING_CTRL_5:1; // 29 Software gating control 5 Uint16 SW_GATING_CTRL_6:1; // 30 Software gating control 6 Uint16 SW_GATING_CTRL_7:1; // 31 Software gating control 7 }; union CLB_IN_MUX_SEL_0_REG { Uint32 all; struct CLB_IN_MUX_SEL_0_BITS bit; }; struct CLB_LCL_MUX_SEL_1_BITS { // bits description Uint16 LCL_MUX_SEL_IN_0:5; // 4:0 Local Mux select 0 Uint16 LCL_MUX_SEL_IN_1:5; // 9:5 Local Mux select 1 Uint16 LCL_MUX_SEL_IN_2:5; // 14:10 Local Mux select 2 Uint32 LCL_MUX_SEL_IN_3:5; // 19:15 Local Mux select 3 Uint16 rsvd1:8; // 27:20 Reserved Uint16 MISC_INPUT_SEL_0:1; // 28 Select MISC_INPUT Uint16 MISC_INPUT_SEL_1:1; // 29 Select MISC_INPUT Uint16 MISC_INPUT_SEL_2:1; // 30 Select MISC_INPUT Uint16 MISC_INPUT_SEL_3:1; // 31 Select MISC_INPUT }; union CLB_LCL_MUX_SEL_1_REG { Uint32 all; struct CLB_LCL_MUX_SEL_1_BITS bit; }; struct CLB_LCL_MUX_SEL_2_BITS { // bits description Uint16 LCL_MUX_SEL_IN_4:5; // 4:0 Local Mux select 4 Uint16 LCL_MUX_SEL_IN_5:5; // 9:5 Local Mux select 5 Uint16 LCL_MUX_SEL_IN_6:5; // 14:10 Local Mux select 6 Uint32 LCL_MUX_SEL_IN_7:5; // 19:15 Local Mux select 7 Uint16 rsvd1:8; // 27:20 Reserved Uint16 MISC_INPUT_SEL_4:1; // 28 Select MISC_INPUT Uint16 MISC_INPUT_SEL_5:1; // 29 Select MISC_INPUT Uint16 MISC_INPUT_SEL_6:1; // 30 Select MISC_INPUT Uint16 MISC_INPUT_SEL_7:1; // 31 Select MISC_INPUT }; union CLB_LCL_MUX_SEL_2_REG { Uint32 all; struct CLB_LCL_MUX_SEL_2_BITS bit; }; struct CLB_BUF_PTR_BITS { // bits description Uint16 PULL:8; // 7:0 Data pointer for pull Uint16 rsvd1:8; // 15:8 Reserved Uint16 PUSH:8; // 23:16 Data pointer for pull Uint16 rsvd2:8; // 31:24 Reserved }; union CLB_BUF_PTR_REG { Uint32 all; struct CLB_BUF_PTR_BITS bit; }; struct CLB_GP_REG_BITS { // bits description Uint16 REG:8; // 7:0 General Purpose bit register Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLB_GP_REG_REG { Uint32 all; struct CLB_GP_REG_BITS bit; }; struct CLB_GLBL_MUX_SEL_1_BITS { // bits description Uint16 GLBL_MUX_SEL_IN_0:7; // 6:0 Global Mux select 0 Uint16 GLBL_MUX_SEL_IN_1:7; // 13:7 Global Mux select 1 Uint32 GLBL_MUX_SEL_IN_2:7; // 20:14 Global Mux select 2 Uint16 GLBL_MUX_SEL_IN_3:7; // 27:21 Global Mux select 3 Uint16 rsvd1:4; // 31:28 Reserved }; union CLB_GLBL_MUX_SEL_1_REG { Uint32 all; struct CLB_GLBL_MUX_SEL_1_BITS bit; }; struct CLB_GLBL_MUX_SEL_2_BITS { // bits description Uint16 GLBL_MUX_SEL_IN_4:7; // 6:0 Global Mux select 4 Uint16 GLBL_MUX_SEL_IN_5:7; // 13:7 Global Mux select 5 Uint32 GLBL_MUX_SEL_IN_6:7; // 20:14 Global Mux select 6 Uint16 GLBL_MUX_SEL_IN_7:7; // 27:21 Global Mux select 7 Uint16 rsvd1:4; // 31:28 Reserved }; union CLB_GLBL_MUX_SEL_2_REG { Uint32 all; struct CLB_GLBL_MUX_SEL_2_BITS bit; }; struct CLB_PRESCALE_CTRL_BITS { // bits description Uint16 CLKEN:1; // 0 Enable the prescale clock generator Uint16 STRB:1; // 1 Enable the Strobe mode of operation Uint16 TAP:4; // 5:2 TAP Select value Uint16 rsvd1:10; // 15:6 Reserved Uint16 PRESCALE:16; // 31:16 Value of prescale register }; union CLB_PRESCALE_CTRL_REG { Uint32 all; struct CLB_PRESCALE_CTRL_BITS bit; }; struct CLB_INTR_TAG_REG_BITS { // bits description Uint16 TAG:6; // 5:0 Interrupt tag Uint16 rsvd1:10; // 15:6 Reserved }; union CLB_INTR_TAG_REG_REG { Uint16 all; struct CLB_INTR_TAG_REG_BITS bit; }; struct CLB_LOCK_BITS { // bits description Uint16 LOCK:1; // 0 LOCK enable Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Key for enabling write }; union CLB_LOCK_REG { Uint32 all; struct CLB_LOCK_BITS bit; }; struct CLB_HLC_INSTR_READ_PTR_BITS { // bits description Uint16 READ_PTR:5; // 4:0 HLC instruction read pointer Uint16 rsvd1:11; // 15:5 Reserved }; union CLB_HLC_INSTR_READ_PTR_REG { Uint16 all; struct CLB_HLC_INSTR_READ_PTR_BITS bit; }; struct CLB_HLC_INSTR_VALUE_BITS { // bits description Uint16 INSTR:12; // 11:0 HLC instruction value Uint16 rsvd1:4; // 15:12 Reserved }; union CLB_HLC_INSTR_VALUE_REG { Uint16 all; struct CLB_HLC_INSTR_VALUE_BITS bit; }; struct CLB_DBG_OUT_2_BITS { // bits description Uint16 OUT:8; // 7:0 Outputs of CLB Async block Uint16 IN:8; // 15:8 CLB CELL Inputs Uint16 rsvd1:16; // 31:16 Reserved }; union CLB_DBG_OUT_2_REG { Uint32 all; struct CLB_DBG_OUT_2_BITS bit; }; struct CLB_DBG_OUT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 COUNT0_MATCH2:1; // 1 COUNT_MATCH2 UNIT 0 Uint16 COUNT0_ZERO:1; // 2 COUNT_ZERO UNIT 0 Uint16 COUNT0_MATCH1:1; // 3 COUNT_MATCH1 UNIT 0 Uint16 FSM0_S0:1; // 4 FSM_S0 UNIT 0 Uint16 FSM0_S1:1; // 5 FSM_S1 UNIT 0 Uint16 FSM0_LUTOUT:1; // 6 FSM_LUT_OUT UNIT 0 Uint16 LUT40_OUT:1; // 7 LUT4_OUT UNIT 0 Uint16 rsvd2:1; // 8 Reserved Uint16 COUNT1_MATCH2:1; // 9 COUNT_MATCH2 UNIT 1 Uint16 COUNT1_ZERO:1; // 10 COUNT_ZERO UNIT 1 Uint16 COUNT1_MATCH1:1; // 11 COUNT_MATCH1 UNIT 1 Uint16 FSM1_S0:1; // 12 FSM_S0 UNIT 1 Uint16 FSM1_S1:1; // 13 FSM_S1 UNIT 1 Uint16 FSM1_LUTOUT:1; // 14 FSM_LUT_OUT UNIT 1 Uint16 LUT41_OUT:1; // 15 LUT4_OUT UNIT 1 Uint16 rsvd3:1; // 16 Reserved Uint16 COUNT2_MATCH2:1; // 17 COUNT_MATCH2 UNIT 2 Uint16 COUNT2_ZERO:1; // 18 COUNT_ZERO UNIT 2 Uint16 COUNT2_MATCH1:1; // 19 COUNT_MATCH1 UNIT 2 Uint16 FSM2_S0:1; // 20 FSM_S0 UNIT 2 Uint16 FSM2_S1:1; // 21 FSM_S1 UNIT 2 Uint16 FSM2_LUTOUT:1; // 22 FSM_LUT_OUT UNIT 2 Uint16 LUT42_OUT:1; // 23 LUT4_OUT UNIT 2 Uint16 OUT0:1; // 24 CELL Output 0 Uint16 OUT1:1; // 25 CELL Output 1 Uint16 OUT2:1; // 26 CELL Output 2 Uint16 OUT3:1; // 27 CELL Output 3 Uint16 OUT4:1; // 28 CELL Output 4 Uint16 OUT5:1; // 29 CELL Output 5 Uint16 OUT6:1; // 30 CELL Output 6 Uint16 OUT7:1; // 31 CELL Output 7 }; union CLB_DBG_OUT_REG { Uint32 all; struct CLB_DBG_OUT_BITS bit; }; struct CLB_LOGIC_CONTROL_REGS { union CLB_LOAD_EN_REG CLB_LOAD_EN; // Global enable & indirect load enable control Uint16 rsvd1; // Reserved union CLB_LOAD_ADDR_REG CLB_LOAD_ADDR; // Indirect address Uint32 CLB_LOAD_DATA; // Data for indirect loads union CLB_INPUT_FILTER_REG CLB_INPUT_FILTER; // Input filter selection for both edge detection and synchronizers union CLB_IN_MUX_SEL_0_REG CLB_IN_MUX_SEL_0; // Input selection to decide between Signals and GP register union CLB_LCL_MUX_SEL_1_REG CLB_LCL_MUX_SEL_1; // Input Mux selection for local mux union CLB_LCL_MUX_SEL_2_REG CLB_LCL_MUX_SEL_2; // Input Mux selection for local mux union CLB_BUF_PTR_REG CLB_BUF_PTR; // PUSH and PULL pointers union CLB_GP_REG_REG CLB_GP_REG; // General purpose register for CELL inputs Uint32 CLB_OUT_EN; // CELL output enable register union CLB_GLBL_MUX_SEL_1_REG CLB_GLBL_MUX_SEL_1; // Global Mux select for CELL inputs union CLB_GLBL_MUX_SEL_2_REG CLB_GLBL_MUX_SEL_2; // Global Mux select for CELL inputs union CLB_PRESCALE_CTRL_REG CLB_PRESCALE_CTRL; // Prescaler register control Uint16 rsvd2[6]; // Reserved union CLB_INTR_TAG_REG_REG CLB_INTR_TAG_REG; // Interrupt Tag register Uint16 rsvd3; // Reserved union CLB_LOCK_REG CLB_LOCK; // Lock control register union CLB_HLC_INSTR_READ_PTR_REG CLB_HLC_INSTR_READ_PTR; // HLC instruction read pointer Uint16 rsvd4; // Reserved union CLB_HLC_INSTR_VALUE_REG CLB_HLC_INSTR_VALUE; // HLC instruction read value Uint16 rsvd5[7]; // Reserved union CLB_DBG_OUT_2_REG CLB_DBG_OUT_2; // Visibility for CLB inputs and final asynchronous outputs Uint32 CLB_DBG_R0; // R0 of High level Controller Uint32 CLB_DBG_R1; // R1 of High level Controller Uint32 CLB_DBG_R2; // R2 of High level Controller Uint32 CLB_DBG_R3; // R3 of High level Controller Uint32 CLB_DBG_C0; // Count of Unit 0 Uint32 CLB_DBG_C1; // Count of Unit 1 Uint32 CLB_DBG_C2; // Count of Unit 2 union CLB_DBG_OUT_REG CLB_DBG_OUT; // Outputs of various units in the Cell }; struct CLB_DATA_EXCHANGE_REGS { Uint32 CLB_PUSH; // CLB_PUSH FIFO Registers (from HLC) Uint16 rsvd1[56]; // Reserved Uint32 CLB_PULL; // CLB_PULL FIFO Registers (TO HLC) }; //--------------------------------------------------------------------------- // CLB External References & Function Declarations: // extern volatile struct CLB_LOGIC_CONFIG_REGS Clb1LogicCfgRegs; extern volatile struct CLB_LOGIC_CONFIG_REGS Clb2LogicCfgRegs; extern volatile struct CLB_LOGIC_CONFIG_REGS Clb3LogicCfgRegs; extern volatile struct CLB_LOGIC_CONFIG_REGS Clb4LogicCfgRegs; extern volatile struct CLB_LOGIC_CONTROL_REGS Clb1LogicCtrlRegs; extern volatile struct CLB_LOGIC_CONTROL_REGS Clb2LogicCtrlRegs; extern volatile struct CLB_LOGIC_CONTROL_REGS Clb3LogicCtrlRegs; extern volatile struct CLB_LOGIC_CONTROL_REGS Clb4LogicCtrlRegs; extern volatile struct CLB_DATA_EXCHANGE_REGS Clb1DataExchgRegs; extern volatile struct CLB_DATA_EXCHANGE_REGS Clb2DataExchgRegs; extern volatile struct CLB_DATA_EXCHANGE_REGS Clb3DataExchgRegs; extern volatile struct CLB_DATA_EXCHANGE_REGS Clb4DataExchgRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_clbxbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XBAR Individual Register Bit Definitions: struct AUXSIG0MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG0 of CLB-XBAR }; union AUXSIG0MUX0TO15CFG_REG { Uint32 all; struct AUXSIG0MUX0TO15CFG_BITS bit; }; struct AUXSIG0MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG0 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG0 of CLB-XBAR }; union AUXSIG0MUX16TO31CFG_REG { Uint32 all; struct AUXSIG0MUX16TO31CFG_BITS bit; }; struct AUXSIG1MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG1 of CLB-XBAR }; union AUXSIG1MUX0TO15CFG_REG { Uint32 all; struct AUXSIG1MUX0TO15CFG_BITS bit; }; struct AUXSIG1MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG1 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG1 of CLB-XBAR }; union AUXSIG1MUX16TO31CFG_REG { Uint32 all; struct AUXSIG1MUX16TO31CFG_BITS bit; }; struct AUXSIG2MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG2 of CLB-XBAR }; union AUXSIG2MUX0TO15CFG_REG { Uint32 all; struct AUXSIG2MUX0TO15CFG_BITS bit; }; struct AUXSIG2MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG2 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG2 of CLB-XBAR }; union AUXSIG2MUX16TO31CFG_REG { Uint32 all; struct AUXSIG2MUX16TO31CFG_BITS bit; }; struct AUXSIG3MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG3 of CLB-XBAR }; union AUXSIG3MUX0TO15CFG_REG { Uint32 all; struct AUXSIG3MUX0TO15CFG_BITS bit; }; struct AUXSIG3MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG3 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG3 of CLB-XBAR }; union AUXSIG3MUX16TO31CFG_REG { Uint32 all; struct AUXSIG3MUX16TO31CFG_BITS bit; }; struct AUXSIG4MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG4 of CLB-XBAR }; union AUXSIG4MUX0TO15CFG_REG { Uint32 all; struct AUXSIG4MUX0TO15CFG_BITS bit; }; struct AUXSIG4MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG4 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG4 of CLB-XBAR }; union AUXSIG4MUX16TO31CFG_REG { Uint32 all; struct AUXSIG4MUX16TO31CFG_BITS bit; }; struct AUXSIG5MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG5 of CLB-XBAR }; union AUXSIG5MUX0TO15CFG_REG { Uint32 all; struct AUXSIG5MUX0TO15CFG_BITS bit; }; struct AUXSIG5MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG5 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG5 of CLB-XBAR }; union AUXSIG5MUX16TO31CFG_REG { Uint32 all; struct AUXSIG5MUX16TO31CFG_BITS bit; }; struct AUXSIG6MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG6 of CLB-XBAR }; union AUXSIG6MUX0TO15CFG_REG { Uint32 all; struct AUXSIG6MUX0TO15CFG_BITS bit; }; struct AUXSIG6MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG6 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG6 of CLB-XBAR }; union AUXSIG6MUX16TO31CFG_REG { Uint32 all; struct AUXSIG6MUX16TO31CFG_BITS bit; }; struct AUXSIG7MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 MUX0 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX1:2; // 3:2 MUX1 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX2:2; // 5:4 MUX2 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX3:2; // 7:6 MUX3 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX4:2; // 9:8 MUX4 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX5:2; // 11:10 MUX5 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX6:2; // 13:12 MUX6 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX7:2; // 15:14 MUX7 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX8:2; // 17:16 MUX8 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX9:2; // 19:18 MUX9 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX10:2; // 21:20 MUX10 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX11:2; // 23:22 MUX11 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX12:2; // 25:24 MUX12 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX13:2; // 27:26 MUX13 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX14:2; // 29:28 MUX14 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX15:2; // 31:30 MUX15 Configuration for AUXSIG7 of CLB-XBAR }; union AUXSIG7MUX0TO15CFG_REG { Uint32 all; struct AUXSIG7MUX0TO15CFG_BITS bit; }; struct AUXSIG7MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 MUX16 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX17:2; // 3:2 MUX17 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX18:2; // 5:4 MUX18 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX19:2; // 7:6 MUX19 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX20:2; // 9:8 MUX20 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX21:2; // 11:10 MUX21 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX22:2; // 13:12 MUX22 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX23:2; // 15:14 MUX23 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX24:2; // 17:16 MUX24 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX25:2; // 19:18 MUX25 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX26:2; // 21:20 MUX26 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX27:2; // 23:22 MUX27 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX28:2; // 25:24 MUX28 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX29:2; // 27:26 MUX29 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX30:2; // 29:28 MUX30 Configuration for AUXSIG7 of CLB-XBAR Uint16 MUX31:2; // 31:30 MUX31 Configuration for AUXSIG7 of CLB-XBAR }; union AUXSIG7MUX16TO31CFG_REG { Uint32 all; struct AUXSIG7MUX16TO31CFG_BITS bit; }; struct AUXSIG0MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG0 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG0 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG0 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG0 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG0 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG0 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG0 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG0 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG0 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG0 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG0 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG0 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG0 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG0 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG0 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG0 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG0 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG0 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG0 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG0 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG0 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG0 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG0 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG0 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG0 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG0 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG0 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG0 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG0 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG0 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG0 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG0 of CLB-XBAR }; union AUXSIG0MUXENABLE_REG { Uint32 all; struct AUXSIG0MUXENABLE_BITS bit; }; struct AUXSIG1MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG1 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG1 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG1 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG1 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG1 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG1 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG1 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG1 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG1 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG1 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG1 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG1 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG1 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG1 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG1 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG1 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG1 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG1 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG1 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG1 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG1 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG1 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG1 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG1 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG1 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG1 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG1 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG1 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG1 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG1 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG1 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG1 of CLB-XBAR }; union AUXSIG1MUXENABLE_REG { Uint32 all; struct AUXSIG1MUXENABLE_BITS bit; }; struct AUXSIG2MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG2 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG2 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG2 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG2 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG2 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG2 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG2 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG2 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG2 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG2 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG2 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG2 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG2 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG2 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG2 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG2 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG2 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG2 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG2 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG2 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG2 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG2 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG2 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG2 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG2 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG2 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG2 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG2 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG2 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG2 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG2 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG2 of CLB-XBAR }; union AUXSIG2MUXENABLE_REG { Uint32 all; struct AUXSIG2MUXENABLE_BITS bit; }; struct AUXSIG3MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG3 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG3 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG3 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG3 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG3 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG3 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG3 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG3 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG3 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG3 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG3 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG3 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG3 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG3 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG3 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG3 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG3 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG3 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG3 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG3 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG3 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG3 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG3 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG3 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG3 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG3 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG3 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG3 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG3 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG3 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG3 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG3 of CLB-XBAR }; union AUXSIG3MUXENABLE_REG { Uint32 all; struct AUXSIG3MUXENABLE_BITS bit; }; struct AUXSIG4MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG4 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG4 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG4 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG4 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG4 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG4 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG4 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG4 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG4 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG4 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG4 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG4 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG4 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG4 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG4 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG4 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG4 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG4 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG4 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG4 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG4 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG4 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG4 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG4 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG4 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG4 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG4 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG4 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG4 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG4 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG4 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG4 of CLB-XBAR }; union AUXSIG4MUXENABLE_REG { Uint32 all; struct AUXSIG4MUXENABLE_BITS bit; }; struct AUXSIG5MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG5 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG5 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG5 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG5 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG5 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG5 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG5 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG5 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG5 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG5 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG5 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG5 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG5 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG5 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG5 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG5 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG5 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG5 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG5 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG5 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG5 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG5 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG5 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG5 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG5 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG5 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG5 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG5 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG5 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG5 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG5 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG5 of CLB-XBAR }; union AUXSIG5MUXENABLE_REG { Uint32 all; struct AUXSIG5MUXENABLE_BITS bit; }; struct AUXSIG6MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG6 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG6 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG6 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG6 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG6 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG6 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG6 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG6 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG6 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG6 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG6 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG6 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG6 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG6 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG6 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG6 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG6 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG6 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG6 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG6 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG6 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG6 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG6 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG6 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG6 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG6 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG6 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG6 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG6 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG6 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG6 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG6 of CLB-XBAR }; union AUXSIG6MUXENABLE_REG { Uint32 all; struct AUXSIG6MUXENABLE_BITS bit; }; struct AUXSIG7MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive AUXSIG7 of CLB-XBAR Uint16 MUX1:1; // 1 MUX1 to drive AUXSIG7 of CLB-XBAR Uint16 MUX2:1; // 2 MUX2 to drive AUXSIG7 of CLB-XBAR Uint16 MUX3:1; // 3 MUX3 to drive AUXSIG7 of CLB-XBAR Uint16 MUX4:1; // 4 MUX4 to drive AUXSIG7 of CLB-XBAR Uint16 MUX5:1; // 5 MUX5 to drive AUXSIG7 of CLB-XBAR Uint16 MUX6:1; // 6 MUX6 to drive AUXSIG7 of CLB-XBAR Uint16 MUX7:1; // 7 MUX7 to drive AUXSIG7 of CLB-XBAR Uint16 MUX8:1; // 8 MUX8 to drive AUXSIG7 of CLB-XBAR Uint16 MUX9:1; // 9 MUX9 to drive AUXSIG7 of CLB-XBAR Uint16 MUX10:1; // 10 MUX10 to drive AUXSIG7 of CLB-XBAR Uint16 MUX11:1; // 11 MUX11 to drive AUXSIG7 of CLB-XBAR Uint16 MUX12:1; // 12 MUX12 to drive AUXSIG7 of CLB-XBAR Uint16 MUX13:1; // 13 MUX13 to drive AUXSIG7 of CLB-XBAR Uint16 MUX14:1; // 14 MUX14 to drive AUXSIG7 of CLB-XBAR Uint16 MUX15:1; // 15 MUX15 to drive AUXSIG7 of CLB-XBAR Uint16 MUX16:1; // 16 MUX16 to drive AUXSIG7 of CLB-XBAR Uint16 MUX17:1; // 17 MUX17 to drive AUXSIG7 of CLB-XBAR Uint16 MUX18:1; // 18 MUX18 to drive AUXSIG7 of CLB-XBAR Uint16 MUX19:1; // 19 MUX19 to drive AUXSIG7 of CLB-XBAR Uint16 MUX20:1; // 20 MUX20 to drive AUXSIG7 of CLB-XBAR Uint16 MUX21:1; // 21 MUX21 to drive AUXSIG7 of CLB-XBAR Uint16 MUX22:1; // 22 MUX22 to drive AUXSIG7 of CLB-XBAR Uint16 MUX23:1; // 23 MUX23 to drive AUXSIG7 of CLB-XBAR Uint16 MUX24:1; // 24 MUX24 to drive AUXSIG7 of CLB-XBAR Uint16 MUX25:1; // 25 MUX25 to drive AUXSIG7 of CLB-XBAR Uint16 MUX26:1; // 26 MUX26 to drive AUXSIG7 of CLB-XBAR Uint16 MUX27:1; // 27 MUX27 to drive AUXSIG7 of CLB-XBAR Uint16 MUX28:1; // 28 MUX28 to drive AUXSIG7 of CLB-XBAR Uint16 MUX29:1; // 29 MUX29 to drive AUXSIG7 of CLB-XBAR Uint16 MUX30:1; // 30 MUX30 to drive AUXSIG7 of CLB-XBAR Uint16 MUX31:1; // 31 MUX31 to drive AUXSIG7 of CLB-XBAR }; union AUXSIG7MUXENABLE_REG { Uint32 all; struct AUXSIG7MUXENABLE_BITS bit; }; struct AUXSIGOUTINV_BITS { // bits description Uint16 OUT0:1; // 0 Selects polarity for AUXSIG0 of CLB-XBAR Uint16 OUT1:1; // 1 Selects polarity for AUXSIG1 of CLB-XBAR Uint16 OUT2:1; // 2 Selects polarity for AUXSIG2 of CLB-XBAR Uint16 OUT3:1; // 3 Selects polarity for AUXSIG3 of CLB-XBAR Uint16 OUT4:1; // 4 Selects polarity for AUXSIG4 of CLB-XBAR Uint16 OUT5:1; // 5 Selects polarity for AUXSIG5 of CLB-XBAR Uint16 OUT6:1; // 6 Selects polarity for AUXSIG6 of CLB-XBAR Uint16 OUT7:1; // 7 Selects polarity for AUXSIG7 of CLB-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union AUXSIGOUTINV_REG { Uint32 all; struct AUXSIGOUTINV_BITS bit; }; struct AUXSIGLOCK_BITS { // bits description Uint16 LOCK:1; // 0 Locks the configuration for CLB-XBAR Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Write Protection KEY }; union AUXSIGLOCK_REG { Uint32 all; struct AUXSIGLOCK_BITS bit; }; struct CLB_XBAR_REGS { union AUXSIG0MUX0TO15CFG_REG AUXSIG0MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-0 union AUXSIG0MUX16TO31CFG_REG AUXSIG0MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-0 union AUXSIG1MUX0TO15CFG_REG AUXSIG1MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-1 union AUXSIG1MUX16TO31CFG_REG AUXSIG1MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-1 union AUXSIG2MUX0TO15CFG_REG AUXSIG2MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-2 union AUXSIG2MUX16TO31CFG_REG AUXSIG2MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-2 union AUXSIG3MUX0TO15CFG_REG AUXSIG3MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-3 union AUXSIG3MUX16TO31CFG_REG AUXSIG3MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-3 union AUXSIG4MUX0TO15CFG_REG AUXSIG4MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-4 union AUXSIG4MUX16TO31CFG_REG AUXSIG4MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-4 union AUXSIG5MUX0TO15CFG_REG AUXSIG5MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-5 union AUXSIG5MUX16TO31CFG_REG AUXSIG5MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-5 union AUXSIG6MUX0TO15CFG_REG AUXSIG6MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-6 union AUXSIG6MUX16TO31CFG_REG AUXSIG6MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-6 union AUXSIG7MUX0TO15CFG_REG AUXSIG7MUX0TO15CFG; // CLB XBAR Mux Configuration for Output-7 union AUXSIG7MUX16TO31CFG_REG AUXSIG7MUX16TO31CFG; // CLB XBAR Mux Configuration for Output-7 union AUXSIG0MUXENABLE_REG AUXSIG0MUXENABLE; // CLB XBAR Mux Enable Register for Output-0 union AUXSIG1MUXENABLE_REG AUXSIG1MUXENABLE; // CLB XBAR Mux Enable Register for Output-1 union AUXSIG2MUXENABLE_REG AUXSIG2MUXENABLE; // CLB XBAR Mux Enable Register for Output-2 union AUXSIG3MUXENABLE_REG AUXSIG3MUXENABLE; // CLB XBAR Mux Enable Register for Output-3 union AUXSIG4MUXENABLE_REG AUXSIG4MUXENABLE; // CLB XBAR Mux Enable Register for Output-4 union AUXSIG5MUXENABLE_REG AUXSIG5MUXENABLE; // CLB XBAR Mux Enable Register for Output-5 union AUXSIG6MUXENABLE_REG AUXSIG6MUXENABLE; // CLB XBAR Mux Enable Register for Output-6 union AUXSIG7MUXENABLE_REG AUXSIG7MUXENABLE; // CLB XBAR Mux Enable Register for Output-7 Uint16 rsvd1[8]; // Reserved union AUXSIGOUTINV_REG AUXSIGOUTINV; // CLB XBAR Output Inversion Register Uint16 rsvd2[4]; // Reserved union AUXSIGLOCK_REG AUXSIGLOCK; // ClbXbar Configuration Lock register }; //--------------------------------------------------------------------------- // CLB_Xbar External References & Function Declarations: // extern volatile struct CLB_XBAR_REGS CLBXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_cmpss.h // // TITLE: Definitions for the CMPSS registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CMPSS Individual Register Bit Definitions: struct COMPCTL_BITS { // bits description Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select Uint16 COMPHINV:1; // 1 High Comparator Invert Select Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable Uint16 rsvd1:1; // 7 Reserved Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select Uint16 COMPLINV:1; // 9 Low Comparator Invert Select Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable Uint16 COMPDACE:1; // 15 Comparator/DAC Enable }; union COMPCTL_REG { Uint16 all; struct COMPCTL_BITS bit; }; struct COMPHYSCTL_BITS { // bits description Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim Uint16 rsvd1:13; // 15:3 Reserved }; union COMPHYSCTL_REG { Uint16 all; struct COMPHYSCTL_BITS bit; }; struct COMPSTS_BITS { // bits description Uint16 COMPHSTS:1; // 0 High Comparator Status Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status Uint16 rsvd1:6; // 7:2 Reserved Uint16 COMPLSTS:1; // 8 Low Comparator Status Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status Uint16 rsvd2:6; // 15:10 Reserved }; union COMPSTS_REG { Uint16 all; struct COMPSTS_BITS bit; }; struct COMPSTSCLR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear Uint16 HSYNCCLREN:1; // 2 High Comparator EPWMSYNCPER Clear Enable Uint16 rsvd2:6; // 8:3 Reserved Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear Uint16 LSYNCCLREN:1; // 10 Low Comparator EPWMSYNCPER Clear Enable Uint16 rsvd3:5; // 15:11 Reserved }; union COMPSTSCLR_REG { Uint16 all; struct COMPSTSCLR_BITS bit; }; struct COMPDACCTL_BITS { // bits description Uint16 DACSOURCE:1; // 0 DAC Source Control Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control Uint16 SELREF:1; // 5 DAC Reference Select Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select Uint16 SWLOADSEL:1; // 7 Software Load Select Uint16 BLANKSOURCE:4; // 11:8 EPWMBLANK Source Select Uint16 BLANKEN:1; // 12 EPWMBLANK Enable Uint16 rsvd1:1; // 13 Reserved Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits }; union COMPDACCTL_REG { Uint16 all; struct COMPDACCTL_BITS bit; }; struct DACHVALS_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACHVALS_REG { Uint16 all; struct DACHVALS_BITS bit; }; struct DACHVALA_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACHVALA_REG { Uint16 all; struct DACHVALA_BITS bit; }; struct DACLVALS_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACLVALS_REG { Uint16 all; struct DACLVALS_BITS bit; }; struct DACLVALA_BITS { // bits description Uint16 DACVAL:12; // 11:0 DAC Value Control Uint16 rsvd1:4; // 15:12 Reserved }; union DACLVALA_REG { Uint16 all; struct DACLVALA_BITS bit; }; struct RAMPDLYA_BITS { // bits description Uint16 DELAY:13; // 12:0 Ramp Delay Value Uint16 rsvd1:3; // 15:13 Reserved }; union RAMPDLYA_REG { Uint16 all; struct RAMPDLYA_BITS bit; }; struct RAMPDLYS_BITS { // bits description Uint16 DELAY:13; // 12:0 Ramp Delay Value Uint16 rsvd1:3; // 15:13 Reserved }; union RAMPDLYS_REG { Uint16 all; struct RAMPDLYS_BITS bit; }; struct CTRIPLFILCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union CTRIPLFILCTL_REG { Uint16 all; struct CTRIPLFILCTL_BITS bit; }; struct CTRIPLFILCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union CTRIPLFILCLKCTL_REG { Uint16 all; struct CTRIPLFILCLKCTL_BITS bit; }; struct CTRIPHFILCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union CTRIPHFILCTL_REG { Uint16 all; struct CTRIPHFILCTL_BITS bit; }; struct CTRIPHFILCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union CTRIPHFILCLKCTL_REG { Uint16 all; struct CTRIPHFILCLKCTL_BITS bit; }; struct COMPLOCK_BITS { // bits description Uint16 COMPCTL:1; // 0 COMPCTL Lock Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock Uint16 DACCTL:1; // 2 DACCTL Lock Uint16 CTRIP:1; // 3 CTRIP Lock Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:11; // 15:5 Reserved }; union COMPLOCK_REG { Uint16 all; struct COMPLOCK_BITS bit; }; struct CMPSS_REGS { union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register Uint16 rsvd1; // Reserved union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register Uint16 rsvd2; // Reserved Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register Uint16 rsvd3; // Reserved Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register Uint16 rsvd4; // Reserved Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register Uint16 rsvd5; // Reserved Uint16 RAMPSTS; // CMPSS Ramp Status Register Uint16 rsvd6; // Reserved union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register }; //--------------------------------------------------------------------------- // CMPSS External References & Function Declarations: // extern volatile struct CMPSS_REGS Cmpss1Regs; extern volatile struct CMPSS_REGS Cmpss2Regs; extern volatile struct CMPSS_REGS Cmpss3Regs; extern volatile struct CMPSS_REGS Cmpss4Regs; extern volatile struct CMPSS_REGS Cmpss5Regs; extern volatile struct CMPSS_REGS Cmpss6Regs; extern volatile struct CMPSS_REGS Cmpss7Regs; extern volatile struct CMPSS_REGS Cmpss8Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_cputimer.h // // TITLE: Definitions for the CPUTIMER registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // CPUTIMER Individual Register Bit Definitions: struct TIM_BITS { // bits description Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High }; union TIM_REG { Uint32 all; struct TIM_BITS bit; }; struct PRD_BITS { // bits description Uint16 LSW:16; // 15:0 CPU-Timer Period Registers Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High }; union PRD_REG { Uint32 all; struct PRD_BITS bit; }; struct TCR_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 TSS:1; // 4 CPU-Timer stop status bit. Uint16 TRB:1; // 5 Timer reload Uint16 rsvd2:4; // 9:6 Reserved Uint16 SOFT:1; // 10 Emulation modes Uint16 FREE:1; // 11 Emulation modes Uint16 rsvd3:2; // 13:12 Reserved Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. }; union TCR_REG { Uint16 all; struct TCR_BITS bit; }; struct TPR_BITS { // bits description Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. }; union TPR_REG { Uint16 all; struct TPR_BITS bit; }; struct TPRH_BITS { // bits description Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. }; union TPRH_REG { Uint16 all; struct TPRH_BITS bit; }; struct CPUTIMER_REGS { union TIM_REG TIM; // CPU-Timer, Counter Register union PRD_REG PRD; // CPU-Timer, Period Register union TCR_REG TCR; // CPU-Timer, Control Register Uint16 rsvd1; // Reserved union TPR_REG TPR; // CPU-Timer, Prescale Register union TPRH_REG TPRH; // CPU-Timer, Prescale Register High }; //--------------------------------------------------------------------------- // CPUTIMER External References & Function Declarations: // extern volatile struct CPUTIMER_REGS CpuTimer0Regs; extern volatile struct CPUTIMER_REGS CpuTimer1Regs; extern volatile struct CPUTIMER_REGS CpuTimer2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_dac.h // // TITLE: Definitions for the DAC registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // DAC Individual Register Bit Definitions: struct DACREV_BITS { // bits description Uint16 REV:8; // 7:0 DAC Revision Register Uint16 rsvd1:8; // 15:8 Reserved }; union DACREV_REG { Uint16 all; struct DACREV_BITS bit; }; struct DACCTL_BITS { // bits description Uint16 DACREFSEL:1; // 0 DAC Reference Select Uint16 rsvd1:1; // 1 Reserved Uint16 LOADMODE:1; // 2 DACVALA Load Mode Uint16 rsvd2:1; // 3 Reserved Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select Uint16 rsvd3:8; // 15:8 Reserved }; union DACCTL_REG { Uint16 all; struct DACCTL_BITS bit; }; struct DACVALA_BITS { // bits description Uint16 DACVALA:12; // 11:0 DAC Active Output Code Uint16 rsvd1:4; // 15:12 Reserved }; union DACVALA_REG { Uint16 all; struct DACVALA_BITS bit; }; struct DACVALS_BITS { // bits description Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code Uint16 rsvd1:4; // 15:12 Reserved }; union DACVALS_REG { Uint16 all; struct DACVALS_BITS bit; }; struct DACOUTEN_BITS { // bits description Uint16 DACOUTEN:1; // 0 DAC Output Code Uint16 rsvd1:15; // 15:1 Reserved }; union DACOUTEN_REG { Uint16 all; struct DACOUTEN_BITS bit; }; struct DACLOCK_BITS { // bits description Uint16 DACCTL:1; // 0 DAC Control Register Lock Uint16 DACVAL:1; // 1 DAC Value Register Lock Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock Uint16 rsvd1:9; // 11:3 Reserved Uint16 KEY:4; // 15:12 DAC Register Lock Key }; union DACLOCK_REG { Uint16 all; struct DACLOCK_BITS bit; }; struct DACTRIM_BITS { // bits description Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim Uint16 rsvd1:4; // 11:8 Reserved Uint16 rsvd2:4; // 15:12 Reserved }; union DACTRIM_REG { Uint16 all; struct DACTRIM_BITS bit; }; struct DAC_REGS { union DACREV_REG DACREV; // DAC Revision Register union DACCTL_REG DACCTL; // DAC Control Register union DACVALA_REG DACVALA; // DAC Value Register - Active union DACVALS_REG DACVALS; // DAC Value Register - Shadow union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register union DACLOCK_REG DACLOCK; // DAC Lock Register union DACTRIM_REG DACTRIM; // DAC Trim Register }; //--------------------------------------------------------------------------- // DAC External References & Function Declarations: // extern volatile struct DAC_REGS DacaRegs; extern volatile struct DAC_REGS DacbRegs; extern volatile struct DAC_REGS DaccRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_dcsm.h // // TITLE: Definitions for the DCSM registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // DCSM Individual Register Bit Definitions: struct DCSM_Z1_OTP { Uint32 Z1OTP_LINKPOINTER1; // Zone 1 Link Pointer1 Uint32 Z1OTP_LINKPOINTER2; // Zone 1 Link Pointer2 Uint32 Z1OTP_LINKPOINTER3; // Zone 1 Link Pointer3 Uint32 Z1OTP_JLM_ENABLE; // Zone 1 JTAGLOCK Enable Register Uint32 Z1OTP_GPREG1; // Zone 1 General Purpose Register 1 Uint32 Z1OTP_GPREG2; // Zone 1 General Purpose Register 2 Uint32 Z1OTP_GPREG3; // Zone 1 General Purpose Register 3 Uint32 Z1OTP_GPREG4; // Zone 1 General Purpose Register 4 Uint32 Z1OTP_PSWDLOCK; // Secure Password Lock Uint32 Z1OTP_CRCLOCK; // Secure CRC Lock Uint32 Z1OTP_JTAGPSWDH0; // JTAG Lock Permanent Password 0 Uint32 Z1OTP_JTAGPSWDH1; // JTAG Lock Permanent Password 1 Uint32 Z1OTP_CMACKEY0; // Secure Boot CMAC Key 0 Uint32 Z1OTP_CMACKEY1; // Secure Boot CMAC Key 1 Uint32 Z1OTP_CMACKEY2; // Secure Boot CMAC Key 2 Uint32 Z1OTP_CMACKEY3; // Secure Boot CMAC Key 3 }; struct DCSM_Z2_OTP { Uint32 Z2OTP_LINKPOINTER1; // Zone 2 Link Pointer1 Uint32 Z2OTP_LINKPOINTER2; // Zone 2 Link Pointer2 Uint32 Z2OTP_LINKPOINTER3; // Zone 2 Link Pointer3 Uint16 rsvd1[2]; // Reserved Uint32 Z2OTP_GPREG1; // Zone 2 General Purpose Register 1 Uint32 Z2OTP_GPREG2; // Zone 2 General Purpose Register 2 Uint32 Z2OTP_GPREG3; // Zone 2 General Purpose Register 3 Uint32 Z2OTP_GPREG4; // Zone 2 General Purpose Register 4 Uint32 Z2OTP_PSWDLOCK; // Secure Password Lock Uint32 Z2OTP_CRCLOCK; // Secure CRC Lock }; struct Z1_LINKPOINTER_BITS { // bits description Uint16 LINKPOINTER:14; // 13:0 Zone1 LINK Pointer Uint16 rsvd1:2; // 15:14 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z1_LINKPOINTER_REG { Uint32 all; struct Z1_LINKPOINTER_BITS bit; }; struct Z1_OTPSECLOCK_BITS { // bits description Uint16 JTAGLOCK:1; // 0 JTAG Lock Status Uint16 rsvd1:3; // 3:1 Reserved Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. Uint16 rsvd2:4; // 15:12 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union Z1_OTPSECLOCK_REG { Uint32 all; struct Z1_OTPSECLOCK_BITS bit; }; struct Z1_JLM_ENABLE_BITS { // bits description Uint16 Z1_JLM_ENABLE:4; // 3:0 Zone1 JLM_ENABLE register. Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z1_JLM_ENABLE_REG { Uint32 all; struct Z1_JLM_ENABLE_BITS bit; }; struct Z1_LINKPOINTERERR_BITS { // bits description Uint16 Z1_LINKPOINTERERR:14; // 13:0 Error to Resolve Z1 Link pointer from OTP loaded values Uint16 rsvd1:2; // 15:14 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z1_LINKPOINTERERR_REG { Uint32 all; struct Z1_LINKPOINTERERR_BITS bit; }; struct Z1_CR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 rsvd6:3; // 18:16 Reserved Uint16 ALLZERO:1; // 19 CSMPSWD All Zeros Uint16 ALLONE:1; // 20 CSMPSWD All Ones Uint16 UNSECURE:1; // 21 CSMPSWD Match CSMKEY Uint16 ARMED:1; // 22 CSM Passwords Read Status Uint16 rsvd7:1; // 23 Reserved Uint16 rsvd8:7; // 30:24 Reserved Uint16 FORCESEC:1; // 31 Force Secure }; union Z1_CR_REG { Uint32 all; struct Z1_CR_BITS bit; }; struct Z1_GRABSECT1R_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in CPU1 BANK Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in CPU1 BANK Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in CPU1 BANK Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in CPU1 BANK Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in CPU1 BANK Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in CPU1 BANK Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in CPU1 BANK Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in CPU1 BANK Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in CPU1 BANK Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in CPU1 BANK Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in CPU1 BANK Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in CPU1 BANK Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in CPU1 BANK Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in CPU1 BANK Uint16 rsvd1:4; // 31:28 Reserved }; union Z1_GRABSECT1R_REG { Uint32 all; struct Z1_GRABSECT1R_BITS bit; }; struct Z1_GRABSECT2R_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in CM BANK Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in CM BANK Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in CM BANK Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in CM BANK Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in CM BANK Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in CM BANK Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in CM BANK Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in CM BANK Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in CM BANK Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in CM BANK Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in CM BANK Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in CM BANK Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in CM BANK Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in CM BANK Uint16 rsvd1:4; // 31:28 Reserved }; union Z1_GRABSECT2R_REG { Uint32 all; struct Z1_GRABSECT2R_BITS bit; }; struct Z1_GRABSECT3R_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in CPU2 BANK Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in CPU2 BANK Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in CPU2 BANK Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in CPU2 BANK Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in CPU2 BANK Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in CPU2 BANK Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in CPU2 BANK Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in CPU2 BANK Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in CPU2 BANK Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in CPU2 BANK Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in CPU2 BANK Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in CPU2 BANK Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in CPU2 BANK Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in CPU2 BANK Uint16 rsvd1:4; // 31:28 Reserved }; union Z1_GRABSECT3R_REG { Uint32 all; struct Z1_GRABSECT3R_BITS bit; }; struct Z1_GRABRAM1R_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM CPU1.LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM CPU1.LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM CPU1.LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM CPU1.LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM CPU1.LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM CPU1.LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM CPU1.LS6 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM CPU1.LS7 Uint16 GRAB_RAM8:2; // 17:16 Grab RAM CPU1.D0 Uint16 GRAB_RAM9:2; // 19:18 Grab RAM CPU1.D1 Uint16 rsvd1:12; // 31:20 Reserved }; union Z1_GRABRAM1R_REG { Uint32 all; struct Z1_GRABRAM1R_BITS bit; }; struct Z1_GRABRAM2R_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM CM.C0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM CM.C1 Uint16 rsvd1:4; // 7:4 Reserved Uint16 GRAB_RAM4:2; // 9:8 Grab RAM CPU1TOCM MSGRAM0_L Uint16 GRAB_RAM5:2; // 11:10 Grab RAM CPU1TOCM MSGRAM0_H Uint16 GRAB_RAM6:2; // 13:12 Grab RAM CMTOCPU1 MSGRAM0_L Uint16 GRAB_RAM7:2; // 15:14 Grab RAM CMTOCPU1 MSGRAM0_H Uint16 GRAB_RAM8:2; // 17:16 Grab RAM CPU2TOCM MSGRAM0_L Uint16 GRAB_RAM9:2; // 19:18 Grab RAM CPU2TOCM MSGRAM0_H Uint16 GRAB_RAM10:2; // 21:20 Grab RAM CMTOCPU2 MSGRAM0_L Uint16 GRAB_RAM11:2; // 23:22 Grab RAM CMTOCPU2 MSGRAM0_H Uint16 GRAB_RAM12:2; // 25:24 Grab RAM CPU1TOCPU2 MSGRAM0_L Uint16 GRAB_RAM13:2; // 27:26 Grab RAM CPU1TOCPU2 MSGRAM0_H Uint16 GRAB_RAM14:2; // 29:28 Grab RAM CPU2TOCPU1 MSGRAM0_L Uint16 GRAB_RAM15:2; // 31:30 Grab RAM CPU2TOCPU1 MSGRAM0_H }; union Z1_GRABRAM2R_REG { Uint32 all; struct Z1_GRABRAM2R_BITS bit; }; struct Z1_GRABRAM3R_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM CPU2.LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM CPU2.LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM CPU2.LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM CPU2.LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM CPU2.LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM CPU2.LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM CPU2.LS6 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM CPU2.LS7 Uint16 GRAB_RAM8:2; // 17:16 Grab RAM CPU2.D0 Uint16 GRAB_RAM9:2; // 19:18 Grab RAM CPU2.D1 Uint16 rsvd1:12; // 31:20 Reserved }; union Z1_GRABRAM3R_REG { Uint32 all; struct Z1_GRABRAM3R_BITS bit; }; struct Z1_EXEONLYSECT1R_BITS { // bits description Uint16 EXEONLY_CPU1_SECT0:1; // 0 Execute-Only Flash Sector 0 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT1:1; // 1 Execute-Only Flash Sector 1 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT2:1; // 2 Execute-Only Flash Sector 2 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT3:1; // 3 Execute-Only Flash Sector 3 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT4:1; // 4 Execute-Only Flash Sector 4 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT5:1; // 5 Execute-Only Flash Sector 5 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT6:1; // 6 Execute-Only Flash Sector 6 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT7:1; // 7 Execute-Only Flash Sector 7 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT8:1; // 8 Execute-Only Flash Sector 8 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT9:1; // 9 Execute-Only Flash Sector 9 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT10:1; // 10 Execute-Only Flash Sector 10 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT11:1; // 11 Execute-Only Flash Sector 11 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT12:1; // 12 Execute-Only Flash Sector 12 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT13:1; // 13 Execute-Only Flash Sector 13 in flash CPU1 BANK Uint16 rsvd1:2; // 15:14 Reserved Uint16 EXEONLY_CM_SECT0:1; // 16 Execute-Only Flash Sector 0 in flash CM BANK Uint16 EXEONLY_CM_SECT1:1; // 17 Execute-Only Flash Sector 1 in flash CM BANK Uint16 EXEONLY_CM_SECT2:1; // 18 Execute-Only Flash Sector 2 in flash CM BANK Uint16 EXEONLY_CM_SECT3:1; // 19 Execute-Only Flash Sector 3 in flash CM BANK Uint16 EXEONLY_CM_SECT4:1; // 20 Execute-Only Flash Sector 4 in flash CM BANK Uint16 EXEONLY_CM_SECT5:1; // 21 Execute-Only Flash Sector 5 in flash CM BANK Uint16 EXEONLY_CM_SECT6:1; // 22 Execute-Only Flash Sector 6 in flash CM BANK Uint16 EXEONLY_CM_SECT7:1; // 23 Execute-Only Flash Sector 7 in flash CM BANK Uint16 EXEONLY_CM_SECT8:1; // 24 Execute-Only Flash Sector 8 in flash CM BANK Uint16 EXEONLY_CM_SECT9:1; // 25 Execute-Only Flash Sector 9 in flash CM BANK Uint16 EXEONLY_CM_SECT10:1; // 26 Execute-Only Flash Sector 10 in flash CM BANK Uint16 EXEONLY_CM_SECT11:1; // 27 Execute-Only Flash Sector 11 in flash CM BANK Uint16 EXEONLY_CM_SECT12:1; // 28 Execute-Only Flash Sector 12 in flash CM BANK Uint16 EXEONLY_CM_SECT13:1; // 29 Execute-Only Flash Sector 13 in flash CM BANK Uint16 rsvd2:2; // 31:30 Reserved }; union Z1_EXEONLYSECT1R_REG { Uint32 all; struct Z1_EXEONLYSECT1R_BITS bit; }; struct Z1_EXEONLYSECT2R_BITS { // bits description Uint16 EXEONLY_CPU2_SECT0:1; // 0 Execute-Only Flash Sector 0 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT1:1; // 1 Execute-Only Flash Sector 1 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT2:1; // 2 Execute-Only Flash Sector 2 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT3:1; // 3 Execute-Only Flash Sector 3 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT4:1; // 4 Execute-Only Flash Sector 4 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT5:1; // 5 Execute-Only Flash Sector 5 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT6:1; // 6 Execute-Only Flash Sector 6 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT7:1; // 7 Execute-Only Flash Sector 7 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT8:1; // 8 Execute-Only Flash Sector 8 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT9:1; // 9 Execute-Only Flash Sector 9 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT10:1; // 10 Execute-Only Flash Sector 10 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT11:1; // 11 Execute-Only Flash Sector 11 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT12:1; // 12 Execute-Only Flash Sector 12 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT13:1; // 13 Execute-Only Flash Sector 13 in flash CPU2 BANK Uint16 rsvd1:2; // 15:14 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z1_EXEONLYSECT2R_REG { Uint32 all; struct Z1_EXEONLYSECT2R_BITS bit; }; struct Z1_EXEONLYRAM1R_BITS { // bits description Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM CPU1.LS0 Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM CPU1.LS1 Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM CPU1.LS2 Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM CPU1.LS3 Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM CPU1.LS4 Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM CPU1.LS5 Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM CPU1.LS6 Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM CPU1.LS7 Uint16 EXEONLY_RAM8:1; // 8 Execute-Only RAM CPU1.D0 Uint16 EXEONLY_RAM9:1; // 9 Execute-Only RAM CPU1.D1 Uint16 rsvd1:6; // 15:10 Reserved Uint16 EXEONLY_RAM16:1; // 16 Execute-Only RAM on CM.C0 Uint16 EXEONLY_RAM17:1; // 17 Execute-Only RAM on CM.C1 Uint16 rsvd2:4; // 21:18 Reserved Uint16 EXEONLY_RAM22:1; // 22 Execute-Only RAM CPU2.D1 Uint16 EXEONLY_RAM23:1; // 23 Execute-Only RAM CPU2.D0 Uint16 EXEONLY_RAM24:1; // 24 Execute-Only RAM CPU2.LS7 Uint16 EXEONLY_RAM25:1; // 25 Execute-Only RAM CPU2.LS6 Uint16 EXEONLY_RAM26:1; // 26 Execute-Only RAM CPU2.LS5 Uint16 EXEONLY_RAM27:1; // 27 Execute-Only RAM CPU2.LS4 Uint16 EXEONLY_RAM28:1; // 28 Execute-Only RAM CPU2.LS3 Uint16 EXEONLY_RAM29:1; // 29 Execute-Only RAM CPU2.LS2 Uint16 EXEONLY_RAM30:1; // 30 Execute-Only RAM CPU2.LS1 Uint16 EXEONLY_RAM31:1; // 31 Execute-Only RAM CPU2.LS0 }; union Z1_EXEONLYRAM1R_REG { Uint32 all; struct Z1_EXEONLYRAM1R_BITS bit; }; struct DCSM_Z1_REGS { union Z1_LINKPOINTER_REG Z1_LINKPOINTER; // Zone 1 Link Pointer union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure Lock union Z1_JLM_ENABLE_REG Z1_JLM_ENABLE; // Zone 1 JTAGLOCK Enable Register union Z1_LINKPOINTERERR_REG Z1_LINKPOINTERERR; // Link Pointer Error Uint32 Z1_GPREG1; // Zone 1 General Purpose Register-1 Uint32 Z1_GPREG2; // Zone 1 General Purpose Register-2 Uint32 Z1_GPREG3; // Zone 1 General Purpose Register-3 Uint32 Z1_GPREG4; // Zone 1 General Purpose Register-4 Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register union Z1_GRABSECT1R_REG Z1_GRABSECT1R; // Zone 1 Grab Flash Status Register 1 union Z1_GRABSECT2R_REG Z1_GRABSECT2R; // Zone 1 Grab Flash Status Register 2 union Z1_GRABSECT3R_REG Z1_GRABSECT3R; // Zone 1 Grab Flash Status Register 3 union Z1_GRABRAM1R_REG Z1_GRABRAM1R; // Zone 1 Grab RAM Status Register 1 union Z1_GRABRAM2R_REG Z1_GRABRAM2R; // Zone 1 Grab RAM Status Register 2 union Z1_GRABRAM3R_REG Z1_GRABRAM3R; // Zone 1 Grab RAM Status Register 3 union Z1_EXEONLYSECT1R_REG Z1_EXEONLYSECT1R; // Zone 1 Execute Only Flash Status Register 1 union Z1_EXEONLYSECT2R_REG Z1_EXEONLYSECT2R; // Zone 1 Execute Only Flash Status Register 2 union Z1_EXEONLYRAM1R_REG Z1_EXEONLYRAM1R; // Zone 1 Execute Only RAM Status Register 1 Uint16 rsvd1[2]; // Reserved Uint32 Z1_JTAGKEY0; // JTAG Unlock Key Register 0 Uint32 Z1_JTAGKEY1; // JTAG Unlock Key Register 1 Uint32 Z1_JTAGKEY2; // JTAG Unlock Key Register 2 Uint32 Z1_JTAGKEY3; // JTAG Unlock Key Register 3 Uint32 Z1_CMACKEY0; // Secure Boot CMAC Key Status Register 0 Uint32 Z1_CMACKEY1; // Secure Boot CMAC Key Status Register 1 Uint32 Z1_CMACKEY2; // Secure Boot CMAC Key Status Register 2 Uint32 Z1_CMACKEY3; // Secure Boot CMAC Key Status Register 3 }; struct Z2_LINKPOINTER_BITS { // bits description Uint16 LINKPOINTER:14; // 13:0 Zone2 LINK Pointer Uint16 rsvd1:2; // 15:14 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z2_LINKPOINTER_REG { Uint32 all; struct Z2_LINKPOINTER_BITS bit; }; struct Z2_OTPSECLOCK_BITS { // bits description Uint16 JTAGLOCK:1; // 0 JTAG Lock Status Uint16 rsvd1:3; // 3:1 Reserved Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. Uint16 rsvd2:4; // 15:12 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union Z2_OTPSECLOCK_REG { Uint32 all; struct Z2_OTPSECLOCK_BITS bit; }; struct Z2_LINKPOINTERERR_BITS { // bits description Uint16 Z2_LINKPOINTERERR:14; // 13:0 Error to Resolve Z2 Link pointer from OTP loaded values Uint16 rsvd1:2; // 15:14 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z2_LINKPOINTERERR_REG { Uint32 all; struct Z2_LINKPOINTERERR_BITS bit; }; struct Z2_CR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:12; // 15:4 Reserved Uint16 rsvd6:3; // 18:16 Reserved Uint16 ALLZERO:1; // 19 CSMPSWD All Zeros Uint16 ALLONE:1; // 20 CSMPSWD All Ones Uint16 UNSECURE:1; // 21 CSMPSWD Match CSMKEY Uint16 ARMED:1; // 22 CSM Passwords Read Status Uint16 rsvd7:1; // 23 Reserved Uint16 rsvd8:7; // 30:24 Reserved Uint16 FORCESEC:1; // 31 Force Secure }; union Z2_CR_REG { Uint32 all; struct Z2_CR_BITS bit; }; struct Z2_GRABSECT1R_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in CPU1 BANK Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in CPU1 BANK Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in CPU1 BANK Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in CPU1 BANK Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in CPU1 BANK Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in CPU1 BANK Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in CPU1 BANK Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in CPU1 BANK Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in CPU1 BANK Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in CPU1 BANK Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in CPU1 BANK Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in CPU1 BANK Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in CPU1 BANK Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in CPU1 BANK Uint16 rsvd1:4; // 31:28 Reserved }; union Z2_GRABSECT1R_REG { Uint32 all; struct Z2_GRABSECT1R_BITS bit; }; struct Z2_GRABSECT2R_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in CM BANK Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in CM BANK Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in CM BANK Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in CM BANK Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in CM BANK Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in CM BANK Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in CM BANK Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in CM BANK Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in CM BANK Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in CM BANK Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in CM BANK Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in CM BANK Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in CM BANK Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in CM BANK Uint16 rsvd1:4; // 31:28 Reserved }; union Z2_GRABSECT2R_REG { Uint32 all; struct Z2_GRABSECT2R_BITS bit; }; struct Z2_GRABSECT3R_BITS { // bits description Uint16 GRAB_SECT0:2; // 1:0 Grab Flash Sector 0 in CPU2 BANK Uint16 GRAB_SECT1:2; // 3:2 Grab Flash Sector 1 in CPU2 BANK Uint16 GRAB_SECT2:2; // 5:4 Grab Flash Sector 2 in CPU2 BANK Uint16 GRAB_SECT3:2; // 7:6 Grab Flash Sector 3 in CPU2 BANK Uint16 GRAB_SECT4:2; // 9:8 Grab Flash Sector 4 in CPU2 BANK Uint16 GRAB_SECT5:2; // 11:10 Grab Flash Sector 5 in CPU2 BANK Uint16 GRAB_SECT6:2; // 13:12 Grab Flash Sector 6 in CPU2 BANK Uint16 GRAB_SECT7:2; // 15:14 Grab Flash Sector 7 in CPU2 BANK Uint16 GRAB_SECT8:2; // 17:16 Grab Flash Sector 8 in CPU2 BANK Uint16 GRAB_SECT9:2; // 19:18 Grab Flash Sector 9 in CPU2 BANK Uint16 GRAB_SECT10:2; // 21:20 Grab Flash Sector 10 in CPU2 BANK Uint16 GRAB_SECT11:2; // 23:22 Grab Flash Sector 11 in CPU2 BANK Uint16 GRAB_SECT12:2; // 25:24 Grab Flash Sector 12 in CPU2 BANK Uint16 GRAB_SECT13:2; // 27:26 Grab Flash Sector 13 in CPU2 BANK Uint16 rsvd1:4; // 31:28 Reserved }; union Z2_GRABSECT3R_REG { Uint32 all; struct Z2_GRABSECT3R_BITS bit; }; struct Z2_GRABRAM1R_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM CPU1.LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM CPU1.LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM CPU1.LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM CPU1.LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM CPU1.LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM CPU1.LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM CPU1.LS6 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM CPU1.LS7 Uint16 GRAB_RAM8:2; // 17:16 Grab RAM CPU1.D0 Uint16 GRAB_RAM9:2; // 19:18 Grab RAM CPU1.D1 Uint16 rsvd1:12; // 31:20 Reserved }; union Z2_GRABRAM1R_REG { Uint32 all; struct Z2_GRABRAM1R_BITS bit; }; struct Z2_GRABRAM2R_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM CM.C0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM CM.C1 Uint16 rsvd1:4; // 7:4 Reserved Uint16 GRAB_RAM4:2; // 9:8 Grab RAM CPU1TOCM MSGRAM0_L Uint16 GRAB_RAM5:2; // 11:10 Grab RAM CPU1TOCM MSGRAM0_H Uint16 GRAB_RAM6:2; // 13:12 Grab RAM CMTOCPU1 MSGRAM0_L Uint16 GRAB_RAM7:2; // 15:14 Grab RAM CMTOCPU1 MSGRAM0_H Uint16 GRAB_RAM8:2; // 17:16 Grab RAM CPU2TOCM MSGRAM0_L Uint16 GRAB_RAM9:2; // 19:18 Grab RAM CPU2TOCM MSGRAM0_H Uint16 GRAB_RAM10:2; // 21:20 Grab RAM CMTOCPU2 MSGRAM0_L Uint16 GRAB_RAM11:2; // 23:22 Grab RAM CMTOCPU2 MSGRAM0_H Uint16 GRAB_RAM12:2; // 25:24 Grab RAM CPU1TOCPU2 MSGRAM0_L Uint16 GRAB_RAM13:2; // 27:26 Grab RAM CPU1TOCPU2 MSGRAM0_H Uint16 GRAB_RAM14:2; // 29:28 Grab RAM CPU2TOCPU1 MSGRAM0_L Uint16 GRAB_RAM15:2; // 31:30 Grab RAM CPU2TOCPU1 MSGRAM0_H }; union Z2_GRABRAM2R_REG { Uint32 all; struct Z2_GRABRAM2R_BITS bit; }; struct Z2_GRABRAM3R_BITS { // bits description Uint16 GRAB_RAM0:2; // 1:0 Grab RAM CPU2.LS0 Uint16 GRAB_RAM1:2; // 3:2 Grab RAM CPU2.LS1 Uint16 GRAB_RAM2:2; // 5:4 Grab RAM CPU2.LS2 Uint16 GRAB_RAM3:2; // 7:6 Grab RAM CPU2.LS3 Uint16 GRAB_RAM4:2; // 9:8 Grab RAM CPU2.LS4 Uint16 GRAB_RAM5:2; // 11:10 Grab RAM CPU2.LS5 Uint16 GRAB_RAM6:2; // 13:12 Grab RAM CPU2.LS6 Uint16 GRAB_RAM7:2; // 15:14 Grab RAM CPU2.LS7 Uint16 GRAB_RAM8:2; // 17:16 Grab RAM CPU2.D0 Uint16 GRAB_RAM9:2; // 19:18 Grab RAM CPU2.D1 Uint16 rsvd1:12; // 31:20 Reserved }; union Z2_GRABRAM3R_REG { Uint32 all; struct Z2_GRABRAM3R_BITS bit; }; struct Z2_EXEONLYSECT1R_BITS { // bits description Uint16 EXEONLY_CPU1_SECT0:1; // 0 Execute-Only Flash Sector 0 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT1:1; // 1 Execute-Only Flash Sector 1 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT2:1; // 2 Execute-Only Flash Sector 2 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT3:1; // 3 Execute-Only Flash Sector 3 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT4:1; // 4 Execute-Only Flash Sector 4 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT5:1; // 5 Execute-Only Flash Sector 5 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT6:1; // 6 Execute-Only Flash Sector 6 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT7:1; // 7 Execute-Only Flash Sector 7 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT8:1; // 8 Execute-Only Flash Sector 8 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT9:1; // 9 Execute-Only Flash Sector 9 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT10:1; // 10 Execute-Only Flash Sector 10 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT11:1; // 11 Execute-Only Flash Sector 11 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT12:1; // 12 Execute-Only Flash Sector 12 in flash CPU1 BANK Uint16 EXEONLY_CPU1_SECT13:1; // 13 Execute-Only Flash Sector 13 in flash CPU1 BANK Uint16 rsvd1:2; // 15:14 Reserved Uint16 EXEONLY_CM_SECT0:1; // 16 Execute-Only Flash Sector 0 in flash CM BANK Uint16 EXEONLY_CM_SECT1:1; // 17 Execute-Only Flash Sector 1 in flash CM BANK Uint16 EXEONLY_CM_SECT2:1; // 18 Execute-Only Flash Sector 2 in flash CM BANK Uint16 EXEONLY_CM_SECT3:1; // 19 Execute-Only Flash Sector 3 in flash CM BANK Uint16 EXEONLY_CM_SECT4:1; // 20 Execute-Only Flash Sector 4 in flash CM BANK Uint16 EXEONLY_CM_SECT5:1; // 21 Execute-Only Flash Sector 5 in flash CM BANK Uint16 EXEONLY_CM_SECT6:1; // 22 Execute-Only Flash Sector 6 in flash CM BANK Uint16 EXEONLY_CM_SECT7:1; // 23 Execute-Only Flash Sector 7 in flash CM BANK Uint16 EXEONLY_CM_SECT8:1; // 24 Execute-Only Flash Sector 8 in flash CM BANK Uint16 EXEONLY_CM_SECT9:1; // 25 Execute-Only Flash Sector 9 in flash CM BANK Uint16 EXEONLY_CM_SECT10:1; // 26 Execute-Only Flash Sector 10 in flash CM BANK Uint16 EXEONLY_CM_SECT11:1; // 27 Execute-Only Flash Sector 11 in flash CM BANK Uint16 EXEONLY_CM_SECT12:1; // 28 Execute-Only Flash Sector 12 in flash CM BANK Uint16 EXEONLY_CM_SECT13:1; // 29 Execute-Only Flash Sector 13 in flash CM BANK Uint16 rsvd2:2; // 31:30 Reserved }; union Z2_EXEONLYSECT1R_REG { Uint32 all; struct Z2_EXEONLYSECT1R_BITS bit; }; struct Z2_EXEONLYSECT2R_BITS { // bits description Uint16 EXEONLY_CPU2_SECT0:1; // 0 Execute-Only Flash Sector 0 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT1:1; // 1 Execute-Only Flash Sector 1 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT2:1; // 2 Execute-Only Flash Sector 2 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT3:1; // 3 Execute-Only Flash Sector 3 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT4:1; // 4 Execute-Only Flash Sector 4 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT5:1; // 5 Execute-Only Flash Sector 5 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT6:1; // 6 Execute-Only Flash Sector 6 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT7:1; // 7 Execute-Only Flash Sector 7 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT8:1; // 8 Execute-Only Flash Sector 8 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT9:1; // 9 Execute-Only Flash Sector 9 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT10:1; // 10 Execute-Only Flash Sector 10 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT11:1; // 11 Execute-Only Flash Sector 11 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT12:1; // 12 Execute-Only Flash Sector 12 in flash CPU2 BANK Uint16 EXEONLY_CPU2_SECT13:1; // 13 Execute-Only Flash Sector 13 in flash CPU2 BANK Uint16 rsvd1:2; // 15:14 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union Z2_EXEONLYSECT2R_REG { Uint32 all; struct Z2_EXEONLYSECT2R_BITS bit; }; struct Z2_EXEONLYRAM1R_BITS { // bits description Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM CPU1.LS0 Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM CPU1.LS1 Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM CPU1.LS2 Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM CPU1.LS3 Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM CPU1.LS4 Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM CPU1.LS5 Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM CPU1.LS6 Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM CPU1.LS7 Uint16 EXEONLY_RAM8:1; // 8 Execute-Only RAM CPU1.D0 Uint16 EXEONLY_RAM9:1; // 9 Execute-Only RAM CPU1.D1 Uint16 rsvd1:6; // 15:10 Reserved Uint16 EXEONLY_RAM16:1; // 16 Execute-Only RAM on CM.C0 Uint16 EXEONLY_RAM17:1; // 17 Execute-Only RAM on CM.C1 Uint16 rsvd2:4; // 21:18 Reserved Uint16 EXEONLY_RAM22:1; // 22 Execute-Only RAM CPU2.D1 Uint16 EXEONLY_RAM23:1; // 23 Execute-Only RAM CPU2.D0 Uint16 EXEONLY_RAM24:1; // 24 Execute-Only RAM CPU2.LS7 Uint16 EXEONLY_RAM25:1; // 25 Execute-Only RAM CPU2.LS6 Uint16 EXEONLY_RAM26:1; // 26 Execute-Only RAM CPU2.LS5 Uint16 EXEONLY_RAM27:1; // 27 Execute-Only RAM CPU2.LS4 Uint16 EXEONLY_RAM28:1; // 28 Execute-Only RAM CPU2.LS3 Uint16 EXEONLY_RAM29:1; // 29 Execute-Only RAM CPU2.LS2 Uint16 EXEONLY_RAM30:1; // 30 Execute-Only RAM CPU2.LS1 Uint16 EXEONLY_RAM31:1; // 31 Execute-Only RAM CPU2.LS0 }; union Z2_EXEONLYRAM1R_REG { Uint32 all; struct Z2_EXEONLYRAM1R_BITS bit; }; struct DCSM_Z2_REGS { union Z2_LINKPOINTER_REG Z2_LINKPOINTER; // Zone 2 Link Pointer union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure Lock Uint16 rsvd1[2]; // Reserved union Z2_LINKPOINTERERR_REG Z2_LINKPOINTERERR; // Link Pointer Error Uint32 Z2_GPREG1; // Zone 2 General Purpose Register-1 Uint32 Z2_GPREG2; // Zone 2 General Purpose Register-2 Uint32 Z2_GPREG3; // Zone 2 General Purpose Register-3 Uint32 Z2_GPREG4; // Zone 2 General Purpose Register-4 Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register union Z2_GRABSECT1R_REG Z2_GRABSECT1R; // Zone 2 Grab Flash Status Register 1 union Z2_GRABSECT2R_REG Z2_GRABSECT2R; // Zone 2 Grab Flash Status Register 2 union Z2_GRABSECT3R_REG Z2_GRABSECT3R; // Zone 2 Grab Flash Status Register 3 union Z2_GRABRAM1R_REG Z2_GRABRAM1R; // Zone 2 Grab RAM Status Register 1 union Z2_GRABRAM2R_REG Z2_GRABRAM2R; // Zone 2 Grab RAM Status Register 2 union Z2_GRABRAM3R_REG Z2_GRABRAM3R; // Zone 2 Grab RAM Status Register 3 union Z2_EXEONLYSECT1R_REG Z2_EXEONLYSECT1R; // Zone 2 Execute Only Flash Status Register 1 union Z2_EXEONLYSECT2R_REG Z2_EXEONLYSECT2R; // Zone 2 Execute Only Flash Status Register 2 union Z2_EXEONLYRAM1R_REG Z2_EXEONLYRAM1R; // Zone 2 Execute Only RAM Status Register 1 }; struct FLSEM_BITS { // bits description Uint16 SEM:2; // 1:0 Flash Semaphore Bit Uint16 rsvd1:6; // 7:2 Reserved Uint16 KEY:8; // 15:8 Semaphore Key Uint16 rsvd2:16; // 31:16 Reserved }; union FLSEM_REG { Uint32 all; struct FLSEM_BITS bit; }; struct SECTSTAT1_BITS { // bits description Uint16 STATUS_SECT0:2; // 1:0 Zone Status flash CPU1 BANK Sector 0 Uint16 STATUS_SECT1:2; // 3:2 Zone Status flash CPU1 BANK sector 1 Uint16 STATUS_SECT2:2; // 5:4 Zone Status flash CPU1 BANK Sector 2 Uint16 STATUS_SECT3:2; // 7:6 Zone Status flash CPU1 BANK Sector 3 Uint16 STATUS_SECT4:2; // 9:8 Zone Status flash CPU1 BANK Sector 4 Uint16 STATUS_SECT5:2; // 11:10 Zone Status flash CPU1 BANK Sector 5 Uint16 STATUS_SECT6:2; // 13:12 Zone Status flash CPU1 BANK Sector 6 Uint16 STATUS_SECT7:2; // 15:14 Zone Status flash CPU1 BANK Sector 7 Uint16 STATUS_SECT8:2; // 17:16 Zone Status flash CPU1 BANK sector 8 Uint16 STATUS_SECT9:2; // 19:18 Zone Status flash CPU1 BANK Sector 9 Uint16 STATUS_SECT10:2; // 21:20 Zone Status flash CPU1 BANK Sector 10 Uint16 STATUS_SECT11:2; // 23:22 Zone Status flash CPU1 BANK Sector 11 Uint16 STATUS_SECT12:2; // 25:24 Zone Status flash CPU1 BANK Sector 12 Uint16 STATUS_SECT13:2; // 27:26 Zone Status flash CPU1 BANK Sector 13 Uint16 rsvd1:4; // 31:28 Reserved }; union SECTSTAT1_REG { Uint32 all; struct SECTSTAT1_BITS bit; }; struct SECTSTAT2_BITS { // bits description Uint16 STATUS_SECT0:2; // 1:0 Zone Status flash CM BANK Sector 0 Uint16 STATUS_SECT1:2; // 3:2 Zone Status flash CM BANK sector 1 Uint16 STATUS_SECT2:2; // 5:4 Zone Status flash CM BANK Sector 2 Uint16 STATUS_SECT3:2; // 7:6 Zone Status flash CM BANK Sector 3 Uint16 STATUS_SECT4:2; // 9:8 Zone Status flash CM BANK Sector 4 Uint16 STATUS_SECT5:2; // 11:10 Zone Status flash CM BANK Sector 5 Uint16 STATUS_SECT6:2; // 13:12 Zone Status flash CM BANK Sector 6 Uint16 STATUS_SECT7:2; // 15:14 Zone Status flash CM BANK Sector 7 Uint16 STATUS_SECT8:2; // 17:16 Zone Status flash CM BANK sector 8 Uint16 STATUS_SECT9:2; // 19:18 Zone Status flash CM BANK Sector 9 Uint16 STATUS_SECT10:2; // 21:20 Zone Status flash CM BANK Sector 10 Uint16 STATUS_SECT11:2; // 23:22 Zone Status flash CM BANK Sector 11 Uint16 STATUS_SECT12:2; // 25:24 Zone Status flash CM BANK Sector 12 Uint16 STATUS_SECT13:2; // 27:26 Zone Status flash CM BANK Sector 13 Uint16 rsvd1:4; // 31:28 Reserved }; union SECTSTAT2_REG { Uint32 all; struct SECTSTAT2_BITS bit; }; struct SECTSTAT3_BITS { // bits description Uint16 STATUS_SECT0:2; // 1:0 Zone Status flash CPU2 BANK Sector 0 Uint16 STATUS_SECT1:2; // 3:2 Zone Status flash CPU2 BANK sector 1 Uint16 STATUS_SECT2:2; // 5:4 Zone Status flash CPU2 BANK Sector 2 Uint16 STATUS_SECT3:2; // 7:6 Zone Status flash CPU2 BANK Sector 3 Uint16 STATUS_SECT4:2; // 9:8 Zone Status flash CPU2 BANK Sector 4 Uint16 STATUS_SECT5:2; // 11:10 Zone Status flash CPU2 BANK Sector 5 Uint16 STATUS_SECT6:2; // 13:12 Zone Status flash CPU2 BANK Sector 6 Uint16 STATUS_SECT7:2; // 15:14 Zone Status flash CPU2 BANK Sector 7 Uint16 STATUS_SECT8:2; // 17:16 Zone Status flash CPU2 BANK sector 8 Uint16 STATUS_SECT9:2; // 19:18 Zone Status flash CPU2 BANK Sector 9 Uint16 STATUS_SECT10:2; // 21:20 Zone Status flash CPU2 BANK Sector 10 Uint16 STATUS_SECT11:2; // 23:22 Zone Status flash CPU2 BANK Sector 11 Uint16 STATUS_SECT12:2; // 25:24 Zone Status flash CPU2 BANK Sector 12 Uint16 STATUS_SECT13:2; // 27:26 Zone Status flash CPU2 BANK Sector 13 Uint16 rsvd1:4; // 31:28 Reserved }; union SECTSTAT3_REG { Uint32 all; struct SECTSTAT3_BITS bit; }; struct RAMSTAT1_BITS { // bits description Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM CPU1.LS0 Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM CPU1.LS1 Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM CPU1.LS2 Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM CPU1.LS3 Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM CPU1.LS4 Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM CPU1.LS5 Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM CPU1.LS6 Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM CPU1.LS7 Uint16 STATUS_RAM8:2; // 17:16 Zone Status RAM CPU1.D0 Uint16 STATUS_RAM9:2; // 19:18 Zone Status RAM CPU1.D1 Uint16 rsvd1:12; // 31:20 Reserved }; union RAMSTAT1_REG { Uint32 all; struct RAMSTAT1_BITS bit; }; struct RAMSTAT2_BITS { // bits description Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM CM.C0 Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM CM.C1 Uint16 rsvd1:4; // 7:4 Reserved Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM CPU1 to CM MSG RAM 1 Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM CPU1 to CM MSG RAM 2 Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM CM to CPU1 MSG RAM 1 Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM CM to CPU1 MSG RAM 2 Uint16 STATUS_RAM8:2; // 17:16 Zone Status RAM CPU2 to CM MSG RAM 1 Uint16 STATUS_RAM9:2; // 19:18 Zone Status RAM CPU2 to CM MSG RAM 2 Uint16 STATUS_RAM10:2; // 21:20 Zone Status RAM CM to CPU2 MSG RAM 1 Uint16 STATUS_RAM11:2; // 23:22 Zone Status RAM CM to CPU2 MSG RAM 2 Uint16 STATUS_RAM12:2; // 25:24 Zone Status RAM CPU1 to CPU2 MSG RAM 1 Uint16 STATUS_RAM13:2; // 27:26 Zone Status RAM CPU1 to CPU2 MSG RAM 2 Uint16 STATUS_RAM14:2; // 29:28 Zone Status RAM CPU2 to CPU1 MSG RAM 1 Uint16 STATUS_RAM15:2; // 31:30 Zone Status RAM CPU2 to CPU1 MSG RAM 2 }; union RAMSTAT2_REG { Uint32 all; struct RAMSTAT2_BITS bit; }; struct RAMSTAT3_BITS { // bits description Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM CPU2.LS0 Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM CPU2.LS1 Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM CPU2.LS2 Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM CPU2.LS3 Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM CPU2.LS4 Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM CPU2.LS5 Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM CPU2.LS6 Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM CPU2.LS7 Uint16 STATUS_RAM8:2; // 17:16 Zone Status RAM CPU2.D0 Uint16 STATUS_RAM9:2; // 19:18 Zone Status RAM CPU2.D1 Uint16 rsvd1:12; // 31:20 Reserved }; union RAMSTAT3_REG { Uint32 all; struct RAMSTAT3_BITS bit; }; struct SECERRSTAT_BITS { // bits description Uint16 ERR:1; // 0 Security Configuration load Error Status Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SECERRSTAT_REG { Uint32 all; struct SECERRSTAT_BITS bit; }; struct SECERRCLR_BITS { // bits description Uint16 ERR:1; // 0 Clear Security Configuration Load Error Status Bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SECERRCLR_REG { Uint32 all; struct SECERRCLR_BITS bit; }; struct SECERRFRC_BITS { // bits description Uint16 ERR:1; // 0 Set Security Configuration Load Error Status Bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Valid Register Write Key }; union SECERRFRC_REG { Uint32 all; struct SECERRFRC_BITS bit; }; struct DCSM_COMMON_REGS { union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register Uint16 rsvd1[6]; // Reserved union SECTSTAT1_REG SECTSTAT1; // Flash Sectors Status Register 1 union SECTSTAT2_REG SECTSTAT2; // Flash Sectors Status Register 2 union SECTSTAT3_REG SECTSTAT3; // Flash Sectors Status Register 3 Uint16 rsvd2[2]; // Reserved union RAMSTAT1_REG RAMSTAT1; // RAM Status Register 1 union RAMSTAT2_REG RAMSTAT2; // RAM Status Register 2 union RAMSTAT3_REG RAMSTAT3; // RAM Status Register 3 Uint16 rsvd3[2]; // Reserved union SECERRSTAT_REG SECERRSTAT; // Security Error Status Register union SECERRCLR_REG SECERRCLR; // Security Error Clear Register union SECERRFRC_REG SECERRFRC; // Security Error Force Register }; //--------------------------------------------------------------------------- // DCSM External References & Function Declarations: // extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: F2837x_Dma.h // // TITLE: F2837x Device DMA Register Definitions. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ //########################################################################### //--------------------------------------------------------------------------- // DMA Individual Register Bit Definitions: struct MODE_BITS { // bits description Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Uint16 rsvd1:2; // 6:5 Reserved Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Uint16 ONESHOT:1; // 10 One Shot Mode Bit Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit Uint16 rsvd2:1; // 12 Reserved Uint16 rsvd3:1; // 13 Reserved Uint16 DATASIZE:1; // 14 Data Size Mode Bit Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit }; union MODE_REG { Uint16 all; struct MODE_BITS bit; }; struct CONTROL_BITS { // bits description Uint16 RUN:1; // 0 Run Bit Uint16 HALT:1; // 1 Halt Bit Uint16 SOFTRESET:1; // 2 Soft Reset Bit Uint16 PERINTFRC:1; // 3 Interrupt Force Bit Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit Uint16 rsvd1:1; // 5 Reserved Uint16 rsvd2:1; // 6 Reserved Uint16 ERRCLR:1; // 7 Error Clear Bit Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:1; // 10 Reserved Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit Uint16 BURSTSTS:1; // 12 Burst Status Bit Uint16 RUNSTS:1; // 13 Run Status Bit Uint16 OVRFLG:1; // 14 Overflow Flag Bit Uint16 rsvd5:1; // 15 Reserved }; union CONTROL_REG { Uint16 all; struct CONTROL_BITS bit; }; struct DMACTRL_BITS { // bits description Uint16 HARDRESET:1; // 0 Hard Reset Bit Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit Uint16 rsvd1:14; // 15:2 Reserved }; union DMACTRL_REG { Uint16 all; struct DMACTRL_BITS bit; }; struct DEBUGCTRL_BITS { // bits description Uint16 rsvd1:15; // 14:0 Reserved Uint16 FREE:1; // 15 Debug Mode Bit }; union DEBUGCTRL_REG { Uint16 all; struct DEBUGCTRL_BITS bit; }; struct PRIORITYCTRL1_BITS { // bits description Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit Uint16 rsvd1:15; // 15:1 Reserved }; union PRIORITYCTRL1_REG { Uint16 all; struct PRIORITYCTRL1_BITS bit; }; struct PRIORITYSTAT_BITS { // bits description Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits Uint16 rsvd1:1; // 3 Reserved Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits Uint16 rsvd2:9; // 15:7 Reserved }; union PRIORITYSTAT_REG { Uint16 all; struct PRIORITYSTAT_BITS bit; }; struct BURST_SIZE_BITS { // bits description Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size Uint16 rsvd1:11; // 15:5 Reserved }; union BURST_SIZE_REG { Uint16 all; struct BURST_SIZE_BITS bit; }; struct BURST_COUNT_BITS { // bits description Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count Uint16 rsvd1:11; // 15:5 Reserved }; union BURST_COUNT_REG { Uint16 all; struct BURST_COUNT_BITS bit; }; struct CH_REGS { union MODE_REG MODE; // Mode Register union CONTROL_REG CONTROL; // Control Register union BURST_SIZE_REG BURST_SIZE; // Burst Size Register union BURST_COUNT_REG BURST_COUNT; // Burst Count Register int16 SRC_BURST_STEP; // Source Burst Step Register int16 DST_BURST_STEP; // Destination Burst Step Register Uint16 TRANSFER_SIZE; // Transfer Size Register Uint16 TRANSFER_COUNT; // Transfer Count Register int16 SRC_TRANSFER_STEP; // Source Transfer Step Register int16 DST_TRANSFER_STEP; // Destination Transfer Step Register Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register int16 SRC_WRAP_STEP; // Source Wrap Step Register Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register int16 DST_WRAP_STEP; // Destination Wrap Step Register Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register }; struct DMA_REGS { union DMACTRL_REG DMACTRL; // DMA Control Register union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register Uint16 rsvd1[2]; // Reserved union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register Uint16 rsvd2; // Reserved union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register Uint16 rsvd3[25]; // Reserved struct CH_REGS CH1; // DMA Channel 1 Registers struct CH_REGS CH2; // DMA Channel 2 Registers struct CH_REGS CH3; // DMA Channel 3 Registers struct CH_REGS CH4; // DMA Channel 4 Registers struct CH_REGS CH5; // DMA Channel 5 Registers struct CH_REGS CH6; // DMA Channel 6 Registers }; //--------------------------------------------------------------------------- // Dma External References & Function Declarations: // extern volatile struct DMA_REGS DmaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_ecap.h // // TITLE: Definitions for the ECAP registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ECAP Individual Register Bit Definitions: struct ECCTL0_BITS { // bits description Uint16 INPUTSEL:7; // 6:0 INPUT source select Uint16 rsvd1:9; // 15:7 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECCTL0_REG { Uint32 all; struct ECCTL0_BITS bit; }; struct ECCTL1_BITS { // bits description Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event Uint16 PRESCALE:5; // 13:9 Event Filter prescale select Uint16 FREE_SOFT:2; // 15:14 Emulation mode }; union ECCTL1_REG { Uint16 all; struct ECCTL1_BITS bit; }; struct ECCTL2_BITS { // bits description Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous Uint16 REARM:1; // 3 One-shot re-arm Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop Uint16 SYNCI_EN:1; // 5 Counter sync-in select Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode Uint16 SWSYNC:1; // 8 SW forced counter sync Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select Uint16 APWMPOL:1; // 10 APWM output polarity select Uint16 CTRFILTRESET:1; // 11 Reset event filter, modulus counter, and interrupt flags. Uint16 DMAEVTSEL:2; // 13:12 DMA event select Uint16 MODCNTRSTS:2; // 15:14 modulo counter status }; union ECCTL2_REG { Uint16 all; struct ECCTL2_BITS bit; }; struct ECEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:7; // 15:9 Reserved }; union ECEINT_REG { Uint16 all; struct ECEINT_BITS bit; }; struct ECFLG_BITS { // bits description Uint16 INT:1; // 0 Global Flag Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:7; // 15:9 Reserved }; union ECFLG_REG { Uint16 all; struct ECFLG_BITS bit; }; struct ECCLR_BITS { // bits description Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear Uint16 CTROVF:1; // 5 Counter Overflow Status Clear Uint16 CTR_PRD:1; // 6 Period Equal Status Clear Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:7; // 15:9 Reserved }; union ECCLR_REG { Uint16 all; struct ECCLR_BITS bit; }; struct ECFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:7; // 15:9 Reserved }; union ECFRC_REG { Uint16 all; struct ECFRC_BITS bit; }; struct ECAPSYNCINSEL_BITS { // bits description Uint16 SEL:5; // 4:0 SYNCIN source select Uint16 rsvd1:11; // 15:5 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAPSYNCINSEL_REG { Uint32 all; struct ECAPSYNCINSEL_BITS bit; }; struct ECAP_REGS { Uint32 TSCTR; // Time-Stamp Counter Uint32 CTRPHS; // Counter Phase Offset Value Register Uint32 CAP1; // Capture 1 Register Uint32 CAP2; // Capture 2 Register Uint32 CAP3; // Capture 3 Register Uint32 CAP4; // Capture 4 Register Uint16 rsvd1[6]; // Reserved union ECCTL0_REG ECCTL0; // Capture Control Register 0 union ECCTL1_REG ECCTL1; // Capture Control Register 1 union ECCTL2_REG ECCTL2; // Capture Control Register 2 union ECEINT_REG ECEINT; // Capture Interrupt Enable Register union ECFLG_REG ECFLG; // Capture Interrupt Flag Register union ECCLR_REG ECCLR; // Capture Interrupt Clear Register union ECFRC_REG ECFRC; // Capture Interrupt Force Register Uint16 rsvd2[4]; // Reserved union ECAPSYNCINSEL_REG ECAPSYNCINSEL; // SYNC source select register }; struct HRCTL_BITS { // bits description Uint16 HRE:1; // 0 High Resolution Enable Uint16 HRCLKE:1; // 1 High Resolution Clock Enable Uint16 PRDSEL:1; // 2 Calibration Period Match Uint16 CALIBSTART:1; // 3 Calibration start Uint16 CALIBSTS:1; // 4 Calibration status Uint16 CALIBCONT:1; // 5 Continuous mode Calibration Select Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRCTL_REG { Uint32 all; struct HRCTL_BITS bit; }; struct HRINTEN_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CALIBDONE:1; // 1 Calibration doe interrupt enable Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status enable Uint16 rsvd2:13; // 15:3 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union HRINTEN_REG { Uint32 all; struct HRINTEN_BITS bit; }; struct HRFLG_BITS { // bits description Uint16 CALIBINT:1; // 0 Global calibration Interrupt Status Flag Uint16 CALIBDONE:1; // 1 Calibration Done Interrupt Flag Bit Uint16 CALPRDCHKSTS:1; // 2 Calibration period check status Flag Bi Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRFLG_REG { Uint32 all; struct HRFLG_BITS bit; }; struct HRCLR_BITS { // bits description Uint16 CALIBINT:1; // 0 Clear Global calibration Interrupt Flag Uint16 CALIBDONE:1; // 1 Clear Calibration Done Interrupt Flag Bit Uint16 CALPRDCHKSTS:1; // 2 Clear Calibration period check status Flag Bit: Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRCLR_REG { Uint32 all; struct HRCLR_BITS bit; }; struct HRFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CALIBDONE:1; // 1 Force Calibration Done Interrupt Flag Bit Uint16 CALPRDCHKSTS:1; // 2 Force Calibration period check status Flag Bit: Uint16 rsvd2:13; // 15:3 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union HRFRC_REG { Uint32 all; struct HRFRC_BITS bit; }; struct HRCAP_REGS { union HRCTL_REG HRCTL; // High-Res Control Register Uint16 rsvd1[2]; // Reserved union HRINTEN_REG HRINTEN; // High-Res Calibration Interrupt Enable Register union HRFLG_REG HRFLG; // High-Res Calibration Interrupt Flag Register union HRCLR_REG HRCLR; // High-Res Calibration Interrupt Clear Register union HRFRC_REG HRFRC; // High-Res Calibration Interrupt Force Register Uint32 HRCALPRD; // High-Res Calibration Period Register Uint32 HRSYSCLKCTR; // High-Res Calibration SYSCLK Counter Register Uint32 HRSYSCLKCAP; // High-Res Calibration SYSCLK Capture Register Uint32 HRCLKCTR; // High-Res Calibration HRCLK Counter Register Uint32 HRCLKCAP; // High-Res Calibration HRCLK Capture Register }; //--------------------------------------------------------------------------- // ECAP External References & Function Declarations: // extern volatile struct ECAP_REGS ECap1Regs; extern volatile struct ECAP_REGS ECap2Regs; extern volatile struct ECAP_REGS ECap3Regs; extern volatile struct ECAP_REGS ECap4Regs; extern volatile struct ECAP_REGS ECap5Regs; extern volatile struct ECAP_REGS ECap6Regs; extern volatile struct ECAP_REGS ECap7Regs; extern volatile struct HRCAP_REGS HRCap6Regs; extern volatile struct HRCAP_REGS HRCap7Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_ecat_ss.h // // TITLE: Definitions for the ECAT_SS registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ECAT_SS Individual Register Bit Definitions: struct ECATSS_IPREVNUM_BITS { // bits description Uint16 IP_REV_MINOR:4; // 3:0 Minor IP Revision Number Uint16 IP_REV_MAJOR:4; // 7:4 Major IP Revision Number Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECATSS_IPREVNUM_REG { Uint32 all; struct ECATSS_IPREVNUM_BITS bit; }; struct ECAT_INTR_RIS_BITS { // bits description Uint16 SYNC0_RIS:1; // 0 SYNC0 feature RIS Uint16 SYNC1_RIS:1; // 1 SYNC1 feature RIS Uint16 ECATSS_IRQ_RIS:1; // 2 EtherCATSS IRQ RIS Uint16 DMA_DONE_RIS:1; // 3 DMA Done RIS Uint16 TIMEOUT_ERR_RIS:1; // 4 PDI bus Timeout Error RIS Uint16 ECAT_MASTER_RESET_RIS:1; // 5 ECAT RESET RIS Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_INTR_RIS_REG { Uint32 all; struct ECAT_INTR_RIS_BITS bit; }; struct ECAT_INTR_MASK_BITS { // bits description Uint16 SYNC0_MASK:1; // 0 SYNC0 feature Mask Uint16 SYNC1_MASK:1; // 1 SYNC1 feature Mask Uint16 ECATSS_IRQ_MASK:1; // 2 EtherCATSS IRQ Mask Uint16 DMA_DONE_MASK:1; // 3 DMA Done Mask Uint16 TIMEOUT_ERR_MASK:1; // 4 PDI Access Timeout Error Mask Uint16 ECAT_MASTER_RESET_MASK:1; // 5 EtherCAT Master Reset Mask Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_INTR_MASK_REG { Uint32 all; struct ECAT_INTR_MASK_BITS bit; }; struct ECAT_INTR_MIS_BITS { // bits description Uint16 SYNC0_MIS:1; // 0 SYNC0 feature MIS Uint16 SYNC1_MIS:1; // 1 SYNC1 feature MIS Uint16 ECATSS_IRQ_MIS:1; // 2 EtherCATSS IRQ MIS Uint16 DMA_DONE_MIS:1; // 3 DMA Done MIS Uint16 TIMEOUT_ERR_MIS:1; // 4 PDI bus Timeout Error MIS Uint16 ECAT_MASTER_RESET_MIS:1; // 5 EtherCAT Master Reset MIS Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_INTR_MIS_REG { Uint32 all; struct ECAT_INTR_MIS_BITS bit; }; struct ECAT_INTR_CLR_BITS { // bits description Uint16 SYNC0_CLR:1; // 0 SYNC0 feature Clear Uint16 SYNC1_CLR:1; // 1 SYNC1 feature Clear Uint16 ECATSS_IRQ_CLR:1; // 2 EtherCATSS IRQ Clear Uint16 DMA_DONE_CLR:1; // 3 DMA Done Clear Uint16 TIMEOUT_ERR_CLR:1; // 4 PDI Access Timeout Error Clear Uint16 ECAT_MASTER_RESET_CLR:1; // 5 EtherCAT Master Reset Clear Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_INTR_CLR_REG { Uint32 all; struct ECAT_INTR_CLR_BITS bit; }; struct ECAT_INTR_SET_BITS { // bits description Uint16 SYNC0_SET:1; // 0 SYNC0 Set Emulate Uint16 SYNC1_SET:1; // 1 SYNC1 Set Emulate Uint16 ECATSS_IRQ_SET:1; // 2 EtherCATSS IRQ Set Emulate Uint16 DMA_DONE_SET:1; // 3 DMA Done Set Emulate Uint16 TIMEOUT_ERR_SET:1; // 4 PDI Access Timeout Error Set Emulate Uint16 ECAT_MASTER_RESET_SET:1; // 5 EtherCAT Master Reset Emulate Uint16 rsvd1:2; // 7:6 Reserved Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_INTR_SET_REG { Uint32 all; struct ECAT_INTR_SET_BITS bit; }; struct ECAT_LATCH_SEL_BITS { // bits description Uint16 LATCH0_SELECT:5; // 4:0 LATCH0 Inputs mux select Uint16 rsvd1:3; // 7:5 Reserved Uint16 LATCH1_SELECT:5; // 12:8 LATCH1 Inputs mux select Uint16 rsvd2:3; // 15:13 Reserved Uint16 rsvd3:1; // 16 Reserved Uint16 rsvd4:15; // 31:17 Reserved }; union ECAT_LATCH_SEL_REG { Uint32 all; struct ECAT_LATCH_SEL_BITS bit; }; struct ECAT_ACCESS_CTRL_BITS { // bits description Uint16 WAIT_STATES:7; // 6:0 Minimum Wait States for VBUS Bridge Uint16 EN_TIMEOUT:1; // 7 PDI Timeout enable Uint16 rsvd1:1; // 8 Reserved Uint16 ENABLE_DEBUG_ACCESS:1; // 9 Debug access enable Uint16 ENABLE_PARALLEL_PORT_ACCESS:1; // 10 Parallel port access enable Uint16 rsvd2:5; // 15:11 Reserved Uint16 TIMEOUT_COUNT:12; // 27:16 Max timecount programmed and count while enabled. Uint16 rsvd3:4; // 31:28 Reserved }; union ECAT_ACCESS_CTRL_REG { Uint32 all; struct ECAT_ACCESS_CTRL_BITS bit; }; struct ECAT_GPIN_GRP_CAP_SEL_BITS { // bits description Uint16 GPI_GRP_CAP_SEL0:3; // 2:0 GPI7-0 capture trigger select Uint16 rsvd1:1; // 3 Reserved Uint16 GPI_GRP_CAP_SEL1:3; // 6:4 GPI15-8 capture trigger select Uint16 rsvd2:1; // 7 Reserved Uint16 GPI_GRP_CAP_SEL2:3; // 10:8 GPI23-16 capture trigger select Uint16 rsvd3:1; // 11 Reserved Uint16 GPI_GRP_CAP_SEL3:3; // 14:12 GPI31-24 capture trigger select Uint16 rsvd4:1; // 15 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union ECAT_GPIN_GRP_CAP_SEL_REG { Uint32 all; struct ECAT_GPIN_GRP_CAP_SEL_BITS bit; }; struct ECAT_GPOUT_GRP_CAP_SEL_BITS { // bits description Uint16 GPO_GRP_CAP_SEL0:2; // 1:0 GPO7-0 capture trigger select Uint16 rsvd1:2; // 3:2 Reserved Uint16 GPO_GRP_CAP_SEL1:2; // 5:4 GPO15-8 capture trigger select Uint16 rsvd2:2; // 7:6 Reserved Uint16 GPO_GRP_CAP_SEL2:2; // 9:8 GPO23-16 capture trigger select Uint16 rsvd3:2; // 11:10 Reserved Uint16 GPO_GRP_CAP_SEL3:2; // 13:12 GPO31-24 capture trigger select Uint16 rsvd4:2; // 15:14 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union ECAT_GPOUT_GRP_CAP_SEL_REG { Uint32 all; struct ECAT_GPOUT_GRP_CAP_SEL_BITS bit; }; struct ECAT_MEM_TEST_BITS { // bits description Uint16 INITIATE_MEM_INIT:1; // 0 Initialize memory init Uint16 MEM_INIT_DONE:1; // 1 Memory Init done status Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_MEM_TEST_REG { Uint32 all; struct ECAT_MEM_TEST_BITS bit; }; struct ECAT_RESET_DEST_CONFIG_BITS { // bits description Uint16 CPU_RESET_EN:1; // 0 CPU reset enable for ResetOut Uint16 CPU_NMI_EN:1; // 1 CPU NMI enable for ResetOut Uint16 CPU_INT_EN:1; // 2 CPU Interrupt enable for ResetOut Uint16 rsvd1:4; // 6:3 Reserved Uint16 DEVICE_RESET_EN:1; // 7 Enables RESET_OUT to impact the device reset Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_RESET_DEST_CONFIG_REG { Uint32 all; struct ECAT_RESET_DEST_CONFIG_BITS bit; }; struct ECAT_SYNC0_CONFIG_BITS { // bits description Uint16 C28x_PIE_EN:1; // 0 Connects the SYNC0 to C28x PIE Interrupt Uint16 CLA_INT_EN:1; // 1 Connects the SYNC0 to CLA Interrupt Uint16 C28x_DMA_EN:1; // 2 Connects the SYNC0 to C28x DMA Trigger Uint16 CM4_NVIC_EN:1; // 3 Connects the SYNC0 to CM4 NVIC Interrupt Uint16 uDMA_TRIG_EN:1; // 4 Connects the SYNC0 to uDMA Trigger Uint16 rsvd1:3; // 7:5 Reserved Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_SYNC0_CONFIG_REG { Uint32 all; struct ECAT_SYNC0_CONFIG_BITS bit; }; struct ECAT_SYNC1_CONFIG_BITS { // bits description Uint16 C28x_PIE_EN:1; // 0 Connects the SYNC1 to C28x PIE Interrupt Uint16 CLA_INT_EN:1; // 1 Connects the SYNC1 to CLA Interrupt Uint16 C28x_DMA_EN:1; // 2 Connects the SYNC1 to C28x DMA Trigger Uint16 CM4_NVIC_EN:1; // 3 Connects the SYNC1 to CM4 NVIC Interrupt Uint16 uDMA_TRIG_EN:1; // 4 Connects the SYNC1 to uDMA Trigger Uint16 rsvd1:3; // 7:5 Reserved Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_SYNC1_CONFIG_REG { Uint32 all; struct ECAT_SYNC1_CONFIG_BITS bit; }; struct ECATSS_REGS { union ECATSS_IPREVNUM_REG ECATSS_IPREVNUM; // IP Revision Number union ECAT_INTR_RIS_REG ECAT_INTR_RIS; // EtherCATSS Interrupt Raw Status union ECAT_INTR_MASK_REG ECAT_INTR_MASK; // EtherCATSS Interrupt Mask union ECAT_INTR_MIS_REG ECAT_INTR_MIS; // EtherCATSS Masked Interrupt Status union ECAT_INTR_CLR_REG ECAT_INTR_CLR; // EtherCATSS Interrupt Clear union ECAT_INTR_SET_REG ECAT_INTR_SET; // EtherCATSS Interrupt Set to emulate union ECAT_LATCH_SEL_REG ECAT_LATCH_SEL; // Select for Latch0/1 inputs and LATCHIN input union ECAT_ACCESS_CTRL_REG ECAT_ACCESS_CTRL; // PDI interface access control config. Uint32 ECAT_GPIN_DAT; // GPIN data capture for debug & override Uint32 ECAT_GPIN_PIPE; // GPIN pipeline select union ECAT_GPIN_GRP_CAP_SEL_REG ECAT_GPIN_GRP_CAP_SEL; // GPIN pipe group capture trigger Uint32 ECAT_GPOUT_DAT; // GPOUT data capture for debug & override Uint32 ECAT_GPOUT_PIPE; // GPOUT pipeline select union ECAT_GPOUT_GRP_CAP_SEL_REG ECAT_GPOUT_GRP_CAP_SEL; // GPOUT pipe group capture trigger union ECAT_MEM_TEST_REG ECAT_MEM_TEST; // Memory Test Control union ECAT_RESET_DEST_CONFIG_REG ECAT_RESET_DEST_CONFIG; // ResetOut impact or destination config union ECAT_SYNC0_CONFIG_REG ECAT_SYNC0_CONFIG; // SYNC0 Configuration for various triggers union ECAT_SYNC1_CONFIG_REG ECAT_SYNC1_CONFIG; // SYNC1 Configuration for various triggers }; struct ECAT_CONFIG_LOCK_BITS { // bits description Uint16 LOCK_ENABLE:1; // 0 Locking writes to ECATSS Uint16 rsvd1:3; // 3:1 Reserved Uint16 IO_CONFIG_ENABLE:1; // 4 Locking the IO Configuration Uint16 rsvd2:3; // 7:5 Reserved Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd3:16; // 31:16 Reserved }; union ECAT_CONFIG_LOCK_REG { Uint32 all; struct ECAT_CONFIG_LOCK_BITS bit; }; struct ECAT_MISC_IO_CONFIG_BITS { // bits description Uint16 RESETIN_GPIO_EN:1; // 0 Enabled ResetIN from GPIO Uint16 EEPROM_I2C_IO_EN:1; // 1 Enables the EEPROM I2C IOPAD connection Uint16 rsvd1:6; // 7:2 Reserved Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_MISC_IO_CONFIG_REG { Uint32 all; struct ECAT_MISC_IO_CONFIG_BITS bit; }; struct ECAT_PHY_IO_CONFIG_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 PHY_PORT_CNT:2; // 3:2 Number of PHY port counts Uint16 PHY_INTF_IOPAD_SEL:2; // 5:4 IO Combination select for PHY Interface Uint16 TX_CLK_AUTO_COMP:1; // 6 Selects TX_CLK IO to do Auto compensation Uint16 rsvd2:1; // 7 Reserved Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd3:16; // 31:16 Reserved }; union ECAT_PHY_IO_CONFIG_REG { Uint32 all; struct ECAT_PHY_IO_CONFIG_BITS bit; }; struct ECAT_SYNC_IO_CONFIG_BITS { // bits description Uint16 SYNC0_IOPAD_SEL:2; // 1:0 SYNC0 IO PAD select option Uint16 rsvd1:1; // 2 Reserved Uint16 SYNC0_GPIO_EN:1; // 3 SYNC0 connection to OUT pad enabled Uint16 SYNC1_IOPAD_SEL:2; // 5:4 SYNC1 IO PAD select option Uint16 rsvd2:1; // 6 Reserved Uint16 SYNC1_GPIO_EN:1; // 7 SYNC1 connection to OUT pad enabled Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd3:16; // 31:16 Reserved }; union ECAT_SYNC_IO_CONFIG_REG { Uint32 all; struct ECAT_SYNC_IO_CONFIG_BITS bit; }; struct ECAT_LATCH_IO_CONFIG_BITS { // bits description Uint16 LATCH0_IOPAD_SEL:2; // 1:0 LATCH0 IO PAD select option Uint16 rsvd1:1; // 2 Reserved Uint16 LATCH0_GPIO_EN:1; // 3 LATCH0 connection to IN pad enabled Uint16 LATCH1_IOPAD_SEL:2; // 5:4 LATCH1 IO PAD select option Uint16 rsvd2:1; // 6 Reserved Uint16 LATCH1_GPIO_EN:1; // 7 LATCH1 connection to IN pad enabled Uint16 WRITE_KEY:8; // 15:8 Key to enable writing lock Uint16 rsvd3:16; // 31:16 Reserved }; union ECAT_LATCH_IO_CONFIG_REG { Uint32 all; struct ECAT_LATCH_IO_CONFIG_BITS bit; }; struct ECAT_LED_CONFIG_BITS { // bits description Uint16 LINKACT0:1; // 0 GPIO enable for LINKACT0 LED Uint16 LINKACT1:1; // 1 GPIO enable for LINKACT1 LED Uint16 STATE:1; // 2 GPIO enable for STATE LED Uint16 ERR:1; // 3 GPIO enable for ERR LED Uint16 RUN:1; // 4 GPIO enable for RUN LED Uint16 rsvd1:1; // 5 Reserved Uint16 LINKACT0_IOPAD_SEL:2; // 7:6 LINKACT0 LED IO PAD select Uint16 LINKACT1_IOPAD_SEL:2; // 9:8 LINKACT1 LED IO PAD select Uint16 STATE_IOPAD_SEL:2; // 11:10 STATE LED IO PAD select Uint16 ERR_IOPAD_SEL:2; // 13:12 ERROR LED IO PAD select Uint16 RUN_IOPAD_SEL:2; // 15:14 RUN LED IO PAD select Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_LED_CONFIG_REG { Uint32 all; struct ECAT_LED_CONFIG_BITS bit; }; struct ECAT_MISC_CONFIG_BITS { // bits description Uint16 TX0_SHIFT_CONFIG:2; // 1:0 TX Shift configuration for Port0 Uint16 TX1_SHIFT_CONFIG:2; // 3:2 TX Shift configuration for Port1 Uint16 EEPROM_SIZE:1; // 4 EEPROM Size bound select Uint16 PDI_EMULATION:1; // 5 PDI Emulation enable Uint16 PHY_ADDR:5; // 10:6 PHY Address Offset Uint16 rsvd1:5; // 15:11 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAT_MISC_CONFIG_REG { Uint32 all; struct ECAT_MISC_CONFIG_BITS bit; }; struct ECATSS_CONFIG_REGS { union ECAT_CONFIG_LOCK_REG ECAT_CONFIG_LOCK; // EtherCATSS Configuration Lock union ECAT_MISC_IO_CONFIG_REG ECAT_MISC_IO_CONFIG; // RESET_IN, EEPROM IO connections select union ECAT_PHY_IO_CONFIG_REG ECAT_PHY_IO_CONFIG; // Control Register of ECATSS union ECAT_SYNC_IO_CONFIG_REG ECAT_SYNC_IO_CONFIG; // SYNC Signals IO configurations union ECAT_LATCH_IO_CONFIG_REG ECAT_LATCH_IO_CONFIG; // LATCH inputs IO pad select Uint32 ECAT_GPIN_SEL; // GPIN Select between IO PAD & tieoff Uint32 ECAT_GPIN_IOPAD_SEL; // GPIN IO pad Select Uint32 ECAT_GPOUT_SEL; // GPOUT IO pad connect select Uint32 ECAT_GPOUT_IOPAD_SEL; // GPOUT IO pad select union ECAT_LED_CONFIG_REG ECAT_LED_CONFIG; // Selection of LED o/p connect to IO pad union ECAT_MISC_CONFIG_REG ECAT_MISC_CONFIG; // Miscelleneous Configuration }; //--------------------------------------------------------------------------- // ECAT External References & Function Declarations: // extern volatile struct ECATSS_CONFIG_REGS EcatssConfigRegs; extern volatile struct ECATSS_REGS EcatssRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_emif.h // // TITLE: Definitions for the EMIF registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // EMIF Individual Register Bit Definitions: struct RCSR_BITS { // bits description Uint16 MINOR_REVISION:8; // 7:0 Minor Revision. Uint16 MAJOR_REVISION:8; // 15:8 Major Revision. Uint16 MODULE_ID:14; // 29:16 EMIF module ID. Uint16 FR:1; // 30 EMIF is running in full rate or half rate. Uint16 BE:1; // 31 EMIF endian mode. }; union RCSR_REG { Uint32 all; struct RCSR_BITS bit; }; struct ASYNC_WCCR_BITS { // bits description Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:2; // 17:16 Reserved Uint16 rsvd3:2; // 19:18 Reserved Uint16 rsvd4:2; // 21:20 Reserved Uint16 rsvd5:2; // 23:22 Reserved Uint16 rsvd6:4; // 27:24 Reserved Uint16 WP0:1; // 28 Polarity for EMxWAIT. Uint16 rsvd7:1; // 29 Reserved Uint16 rsvd8:1; // 30 Reserved Uint16 rsvd9:1; // 31 Reserved }; union ASYNC_WCCR_REG { Uint32 all; struct ASYNC_WCCR_BITS bit; }; struct SDRAM_CR_BITS { // bits description Uint16 PAGESIGE:3; // 2:0 Page Size. Uint16 rsvd1:1; // 3 Reserved Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices. Uint16 rsvd2:1; // 7 Reserved Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set. Uint16 CL:3; // 11:9 CAS Latency. Uint16 rsvd3:1; // 12 Reserved Uint16 rsvd4:1; // 13 Reserved Uint16 NM:1; // 14 Narrow Mode. Uint16 rsvd5:1; // 15 Reserved Uint16 rsvd6:1; // 16 Reserved Uint16 rsvd7:2; // 18:17 Reserved Uint16 rsvd8:1; // 19 Reserved Uint16 rsvd9:3; // 22:20 Reserved Uint16 rsvd10:3; // 25:23 Reserved Uint16 rsvd11:3; // 28:26 Reserved Uint16 PDWR:1; // 29 Perform refreshes during Power Down. Uint16 PD:1; // 30 Power Down. Uint16 SR:1; // 31 Self Refresh. }; union SDRAM_CR_REG { Uint32 all; struct SDRAM_CR_BITS bit; }; struct SDRAM_RCR_BITS { // bits description Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate. Uint16 rsvd1:3; // 15:13 Reserved Uint16 rsvd2:3; // 18:16 Reserved Uint16 rsvd3:13; // 31:19 Reserved }; union SDRAM_RCR_REG { Uint32 all; struct SDRAM_RCR_BITS bit; }; struct ASYNC_CS2_CR_BITS { // bits description Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. Uint16 TA:2; // 3:2 Turn Around cycles. Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. Uint16 EW:1; // 30 Extend Wait mode. Uint16 SS:1; // 31 Select Strobe mode. }; union ASYNC_CS2_CR_REG { Uint32 all; struct ASYNC_CS2_CR_BITS bit; }; struct ASYNC_CS3_CR_BITS { // bits description Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. Uint16 TA:2; // 3:2 Turn Around cycles. Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. Uint16 EW:1; // 30 Extend Wait mode. Uint16 SS:1; // 31 Select Strobe mode. }; union ASYNC_CS3_CR_REG { Uint32 all; struct ASYNC_CS3_CR_BITS bit; }; struct ASYNC_CS4_CR_BITS { // bits description Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. Uint16 TA:2; // 3:2 Turn Around cycles. Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. Uint16 EW:1; // 30 Extend Wait mode. Uint16 SS:1; // 31 Select Strobe mode. }; union ASYNC_CS4_CR_REG { Uint32 all; struct ASYNC_CS4_CR_BITS bit; }; struct SDRAM_TR_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank. Uint16 rsvd2:1; // 7 Reserved Uint16 T_RC:4; // 11:8 Activate to Activate timing . Uint16 T_RAS:4; // 15:12 Activate to Precharge timing. Uint16 T_WR:3; // 18:16 Last Write to Precharge timing. Uint16 rsvd3:1; // 19 Reserved Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing. Uint16 rsvd4:1; // 23 Reserved Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing. Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing }; union SDRAM_TR_REG { Uint32 all; struct SDRAM_TR_BITS bit; }; struct SDR_EXT_TMNG_BITS { // bits description Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing. Uint16 rsvd1:11; // 15:5 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SDR_EXT_TMNG_REG { Uint32 all; struct SDR_EXT_TMNG_BITS bit; }; struct INT_RAW_BITS { // bits description Uint16 AT:1; // 0 Asynchronous Timeout. Uint16 LT:1; // 1 Line Trap. Uint16 WR:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_RAW_REG { Uint32 all; struct INT_RAW_BITS bit; }; struct INT_MSK_BITS { // bits description Uint16 AT_MASKED:1; // 0 Asynchronous Timeout. Uint16 LT_MASKED:1; // 1 Line Trap. Uint16 WR_MASKED:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_MSK_REG { Uint32 all; struct INT_MSK_BITS bit; }; struct INT_MSK_SET_BITS { // bits description Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout. Uint16 LT_MASK_SET:1; // 1 Line Trap. Uint16 WR_MASK_SET:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_MSK_SET_REG { Uint32 all; struct INT_MSK_SET_BITS bit; }; struct INT_MSK_CLR_BITS { // bits description Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout. Uint16 LT_MASK_CLR:1; // 1 Line Trap. Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise. Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union INT_MSK_CLR_REG { Uint32 all; struct INT_MSK_CLR_BITS bit; }; struct EMIF_REGS { union RCSR_REG RCSR; // Revision Code and Status Register union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register Uint16 rsvd1[2]; // Reserved union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register Uint16 rsvd2[6]; // Reserved Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register Uint16 rsvd3[2]; // Reserved union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register union INT_RAW_REG INT_RAW; // Interrupt Raw Register union INT_MSK_REG INT_MSK; // Interrupt Masked Register union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register }; //--------------------------------------------------------------------------- // EMIF External References & Function Declarations: // extern volatile struct EMIF_REGS Emif1Regs; extern volatile struct EMIF_REGS Emif2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_epwm.h // // TITLE: Definitions for the EPWM registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // EPWM Individual Register Bit Definitions: struct TBCTL_BITS { // bits description Uint16 CTRMODE:2; // 1:0 Counter Mode Uint16 PHSEN:1; // 2 Phase Load Enable Uint16 PRDLD:1; // 3 Active Period Load Uint16 rsvd1:2; // 5:4 Reserved Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler Uint16 PHSDIR:1; // 13 Phase Direction Bit Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits }; union TBCTL_REG { Uint16 all; struct TBCTL_BITS bit; }; struct TBCTL2_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode Uint16 OSHTSYNC:1; // 7 One shot sync Uint16 rsvd3:4; // 11:8 Reserved Uint16 rsvd4:2; // 13:12 Reserved Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event }; union TBCTL2_REG { Uint16 all; struct TBCTL2_BITS bit; }; struct EPWMSYNCINSEL_BITS { // bits description Uint16 SEL:5; // 4:0 EPWMxSYNCI source select Uint16 rsvd1:11; // 15:5 Reserved }; union EPWMSYNCINSEL_REG { Uint16 all; struct EPWMSYNCINSEL_BITS bit; }; struct TBSTS_BITS { // bits description Uint16 CTRDIR:1; // 0 Counter Direction Status Uint16 SYNCI:1; // 1 External Input Sync Status Uint16 CTRMAX:1; // 2 Counter Max Latched Status Uint16 rsvd1:13; // 15:3 Reserved }; union TBSTS_REG { Uint16 all; struct TBSTS_BITS bit; }; struct EPWMSYNCOUTEN_BITS { // bits description Uint16 SWEN:1; // 0 EPWMxSYNCO Software Force Enable Uint16 ZEROEN:1; // 1 EPWMxSYNCO Zero Count Event Enable Uint16 CMPBEN:1; // 2 EPWMxSYNCO Compare B Event Enable Uint16 CMPCEN:1; // 3 EPWMxSYNCO Compare C Event Enable Uint16 CMPDEN:1; // 4 EPWMxSYNCO Compare D Event Enable Uint16 DCAEVT1EN:1; // 5 EPWMxSYNCO Digital Compare A Event 1 Sync Enable Uint16 DCBEVT1EN:1; // 6 EPWMxSYNCO Digital Compare B Event 1 Sync Enable Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved }; union EPWMSYNCOUTEN_REG { Uint16 all; struct EPWMSYNCOUTEN_BITS bit; }; struct TBCTL3_BITS { // bits description Uint16 OSSFRCEN:1; // 0 One Shot Sync Force Enable Uint16 Rerserved:15; // 15:1 Reserved }; union TBCTL3_REG { Uint16 all; struct TBCTL3_BITS bit; }; struct CMPCTL_BITS { // bits description Uint16 LOADAMODE:2; // 1:0 Active Compare A Load Uint16 LOADBMODE:2; // 3:2 Active Compare B Load Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode Uint16 rsvd2:1; // 7 Reserved Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC Uint16 rsvd3:2; // 15:14 Reserved }; union CMPCTL_REG { Uint16 all; struct CMPCTL_BITS bit; }; struct CMPCTL2_BITS { // bits description Uint16 LOADCMODE:2; // 1:0 Active Compare C Load Uint16 LOADDMODE:2; // 3:2 Active Compare D load Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode Uint16 rsvd2:3; // 9:7 Reserved Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC Uint16 rsvd3:2; // 15:14 Reserved }; union CMPCTL2_REG { Uint16 all; struct CMPCTL2_BITS bit; }; struct DBCTL_BITS { // bits description Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control Uint16 POLSEL:2; // 3:2 Polarity Select Control Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable }; union DBCTL_REG { Uint16 all; struct DBCTL_BITS bit; }; struct DBCTL2_BITS { // bits description Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select Uint16 rsvd1:13; // 15:3 Reserved }; union DBCTL2_REG { Uint16 all; struct DBCTL2_BITS bit; }; struct AQCTL_BITS { // bits description Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode Uint16 rsvd1:1; // 5 Reserved Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode Uint16 rsvd2:1; // 7 Reserved Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC Uint16 rsvd3:4; // 15:12 Reserved }; union AQCTL_REG { Uint16 all; struct AQCTL_BITS bit; }; struct AQTSRCSEL_BITS { // bits description Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits Uint16 rsvd1:8; // 15:8 Reserved }; union AQTSRCSEL_REG { Uint16 all; struct AQTSRCSEL_BITS bit; }; struct PCCTL_BITS { // bits description Uint16 CHPEN:1; // 0 PWM chopping enable Uint16 OSHTWTH:4; // 4:1 One-shot pulse width Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle Uint16 rsvd1:5; // 15:11 Reserved }; union PCCTL_REG { Uint16 all; struct PCCTL_BITS bit; }; struct VCAPCTL_BITS { // bits description Uint16 VCAPE:1; // 0 Valley Capture mode Uint16 VCAPSTART:1; // 1 Valley Capture Start Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select Uint16 rsvd1:2; // 6:5 Reserved Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select Uint16 rsvd2:5; // 15:11 Reserved }; union VCAPCTL_REG { Uint16 all; struct VCAPCTL_BITS bit; }; struct VCNTCFG_BITS { // bits description Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection Uint16 rsvd1:3; // 6:4 Reserved Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection Uint16 rsvd2:3; // 14:12 Reserved Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit }; union VCNTCFG_REG { Uint16 all; struct VCNTCFG_BITS bit; }; struct HRCNFG_BITS { // bits description Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit Uint16 AUTOCONV:1; // 6 Autoconversion Bit Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits Uint16 rsvd1:1; // 13 Reserved Uint16 rsvd2:2; // 15:14 Reserved }; union HRCNFG_REG { Uint16 all; struct HRCNFG_BITS bit; }; struct HRPWR_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 rsvd3:1; // 3 Reserved Uint16 rsvd4:1; // 4 Reserved Uint16 rsvd5:1; // 5 Reserved Uint16 rsvd6:4; // 9:6 Reserved Uint16 rsvd7:5; // 14:10 Reserved Uint16 CALPWRON:1; // 15 Calibration Power On }; union HRPWR_REG { Uint16 all; struct HRPWR_BITS bit; }; struct HRMSTEP_BITS { // bits description Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value Uint16 rsvd1:8; // 15:8 Reserved }; union HRMSTEP_REG { Uint16 all; struct HRMSTEP_BITS bit; }; struct HRCNFG2_BITS { // bits description Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits Uint16 rsvd1:8; // 13:6 Reserved Uint16 rsvd2:1; // 14 Reserved Uint16 rsvd3:1; // 15 Reserved }; union HRCNFG2_REG { Uint16 all; struct HRCNFG2_BITS bit; }; struct HRPCTL_BITS { // bits description Uint16 HRPE:1; // 0 High Resolution Period Enable Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable Uint16 rsvd1:1; // 3 Reserved Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: Uint16 rsvd2:9; // 15:7 Reserved }; union HRPCTL_REG { Uint16 all; struct HRPCTL_BITS bit; }; struct TRREM_BITS { // bits description Uint16 TRREM:11; // 10:0 Translator Remainder Bits Uint16 rsvd1:5; // 15:11 Reserved }; union TRREM_REG { Uint16 all; struct TRREM_BITS bit; }; struct GLDCTL_BITS { // bits description Uint16 GLD:1; // 0 Global Shadow to Active load event control Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit Uint16 rsvd1:1; // 6 Reserved Uint16 GLDPRD:3; // 9:7 Global Load Strobe Period Select Register Uint16 GLDCNT:3; // 12:10 Global Load Strobe Counter Register Uint16 rsvd2:3; // 15:13 Reserved }; union GLDCTL_REG { Uint16 all; struct GLDCTL_BITS bit; }; struct GLDCFG_BITS { // bits description Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR Uint16 CMPC:1; // 3 Global load event configuration for CMPC Uint16 CMPD:1; // 4 Global load event configuration for CMPD Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC Uint16 rsvd1:5; // 15:11 Reserved }; union GLDCFG_REG { Uint16 all; struct GLDCFG_BITS bit; }; struct EPWMXLINK_BITS { // bits description Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link Uint16 CMPCLINK:4; // 15:12 CMPC Link Uint16 CMPDLINK:4; // 19:16 CMPD Link Uint16 rsvd1:8; // 27:20 Reserved Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link }; union EPWMXLINK_REG { Uint32 all; struct EPWMXLINK_BITS bit; }; struct AQCTLA_BITS { // bits description Uint16 ZRO:2; // 1:0 Action Counter = Zero Uint16 PRD:2; // 3:2 Action Counter = Period Uint16 CAU:2; // 5:4 Action Counter = Compare A Up Uint16 CAD:2; // 7:6 Action Counter = Compare A Down Uint16 CBU:2; // 9:8 Action Counter = Compare B Up Uint16 CBD:2; // 11:10 Action Counter = Compare B Down Uint16 rsvd1:4; // 15:12 Reserved }; union AQCTLA_REG { Uint16 all; struct AQCTLA_BITS bit; }; struct AQCTLA2_BITS { // bits description Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count Uint16 rsvd1:8; // 15:8 Reserved }; union AQCTLA2_REG { Uint16 all; struct AQCTLA2_BITS bit; }; struct AQCTLB_BITS { // bits description Uint16 ZRO:2; // 1:0 Action Counter = Zero Uint16 PRD:2; // 3:2 Action Counter = Period Uint16 CAU:2; // 5:4 Action Counter = Compare A Up Uint16 CAD:2; // 7:6 Action Counter = Compare A Down Uint16 CBU:2; // 9:8 Action Counter = Compare B Up Uint16 CBD:2; // 11:10 Action Counter = Compare B Down Uint16 rsvd1:4; // 15:12 Reserved }; union AQCTLB_REG { Uint16 all; struct AQCTLB_BITS bit; }; struct AQCTLB2_BITS { // bits description Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count Uint16 rsvd1:8; // 15:8 Reserved }; union AQCTLB2_REG { Uint16 all; struct AQCTLB2_BITS bit; }; struct AQSFRC_BITS { // bits description Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked Uint16 OTSFA:1; // 2 One-time SW Force A Output Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked Uint16 OTSFB:1; // 5 One-time SW Force A Output Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options Uint16 rsvd1:8; // 15:8 Reserved }; union AQSFRC_REG { Uint16 all; struct AQSFRC_BITS bit; }; struct AQCSFRC_BITS { // bits description Uint16 CSFA:2; // 1:0 Continuous Software Force on output A Uint16 CSFB:2; // 3:2 Continuous Software Force on output B Uint16 rsvd1:12; // 15:4 Reserved }; union AQCSFRC_REG { Uint16 all; struct AQCSFRC_BITS bit; }; struct DBREDHR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:7; // 7:1 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits }; union DBREDHR_REG { Uint16 all; struct DBREDHR_BITS bit; }; struct DBRED_BITS { // bits description Uint16 DBRED:14; // 13:0 Rising edge delay value Uint16 rsvd1:2; // 15:14 Reserved }; union DBRED_REG { Uint16 all; struct DBRED_BITS bit; }; struct DBFEDHR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:7; // 7:1 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits }; union DBFEDHR_REG { Uint16 all; struct DBFEDHR_BITS bit; }; struct DBFED_BITS { // bits description Uint16 DBFED:14; // 13:0 Falling edge delay value Uint16 rsvd1:2; // 15:14 Reserved }; union DBFED_REG { Uint16 all; struct DBFED_BITS bit; }; struct TBPHS_BITS { // bits description Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) Uint16 TBPHS:16; // 31:16 Phase Offset Register }; union TBPHS_REG { Uint32 all; struct TBPHS_BITS bit; }; struct CMPA_BITS { // bits description Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register Uint16 CMPA:16; // 31:16 Compare A Register }; union CMPA_REG { Uint32 all; struct CMPA_BITS bit; }; struct CMPB_BITS { // bits description Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits Uint16 CMPB:16; // 31:16 Compare B Register }; union CMPB_REG { Uint32 all; struct CMPB_BITS bit; }; struct GLDCTL2_BITS { // bits description Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode Uint16 GFRCLD:1; // 1 Force reload event in one shot mode Uint16 rsvd1:14; // 15:2 Reserved }; union GLDCTL2_REG { Uint16 all; struct GLDCTL2_BITS bit; }; struct TZSEL_BITS { // bits description Uint16 CBC1:1; // 0 TZ1 CBC select Uint16 CBC2:1; // 1 TZ2 CBC select Uint16 CBC3:1; // 2 TZ3 CBC select Uint16 CBC4:1; // 3 TZ4 CBC select Uint16 CBC5:1; // 4 TZ5 CBC select Uint16 CBC6:1; // 5 TZ6 CBC select Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select Uint16 OSHT1:1; // 8 One-shot TZ1 select Uint16 OSHT2:1; // 9 One-shot TZ2 select Uint16 OSHT3:1; // 10 One-shot TZ3 select Uint16 OSHT4:1; // 11 One-shot TZ4 select Uint16 OSHT5:1; // 12 One-shot TZ5 select Uint16 OSHT6:1; // 13 One-shot TZ6 select Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select }; union TZSEL_REG { Uint16 all; struct TZSEL_BITS bit; }; struct TZDCSEL_BITS { // bits description Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 Uint16 rsvd1:4; // 15:12 Reserved }; union TZDCSEL_REG { Uint16 all; struct TZDCSEL_BITS bit; }; struct TZCTL_BITS { // bits description Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTL_REG { Uint16 all; struct TZCTL_BITS bit; }; struct TZCTL2_BITS { // bits description Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN Uint16 rsvd1:3; // 14:12 Reserved Uint16 ETZE:1; // 15 TZCTL2 Enable }; union TZCTL2_REG { Uint16 all; struct TZCTL2_BITS bit; }; struct TZCTLDCA_BITS { // bits description Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTLDCA_REG { Uint16 all; struct TZCTLDCA_BITS bit; }; struct TZCTLDCB_BITS { // bits description Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN Uint16 rsvd1:4; // 15:12 Reserved }; union TZCTLDCB_REG { Uint16 all; struct TZCTLDCB_BITS bit; }; struct TZEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable Uint16 OST:1; // 2 Trip Zones One Shot Int Enable Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable Uint16 rsvd2:9; // 15:7 Reserved }; union TZEINT_REG { Uint16 all; struct TZEINT_BITS bit; }; struct TZFLG_BITS { // bits description Uint16 INT:1; // 0 Global Int Status Flag Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag Uint16 OST:1; // 2 Trip Zones One Shot Flag Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag Uint16 rsvd1:9; // 15:7 Reserved }; union TZFLG_REG { Uint16 all; struct TZFLG_BITS bit; }; struct TZCBCFLG_BITS { // bits description Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 Uint16 rsvd1:8; // 15:8 Reserved }; union TZCBCFLG_REG { Uint16 all; struct TZCBCFLG_BITS bit; }; struct TZOSTFLG_BITS { // bits description Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 Uint16 rsvd1:8; // 15:8 Reserved }; union TZOSTFLG_REG { Uint16 all; struct TZOSTFLG_BITS bit; }; struct TZCLR_BITS { // bits description Uint16 INT:1; // 0 Global Interrupt Clear Flag Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear Uint16 OST:1; // 2 One-Shot Flag Clear Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear Uint16 rsvd1:7; // 13:7 Reserved Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch }; union TZCLR_REG { Uint16 all; struct TZCLR_BITS bit; }; struct TZCBCCLR_BITS { // bits description Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC Uint16 rsvd1:8; // 15:8 Reserved }; union TZCBCCLR_REG { Uint16 all; struct TZCBCCLR_BITS bit; }; struct TZOSTCLR_BITS { // bits description Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST Uint16 rsvd1:8; // 15:8 Reserved }; union TZOSTCLR_REG { Uint16 all; struct TZOSTCLR_BITS bit; }; struct TZFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event Uint16 OST:1; // 2 Force Trip Zones One Shot Event Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 Uint16 rsvd2:9; // 15:7 Reserved }; union TZFRC_REG { Uint16 all; struct TZFRC_BITS bit; }; struct ETSEL_BITS { // bits description Uint16 INTSEL:3; // 2:0 EPWMxINTn Select Uint16 INTEN:1; // 3 EPWMxINTn Enable Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select Uint16 rsvd1:1; // 7 Reserved Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select Uint16 SOCAEN:1; // 11 Start of Conversion A Enable Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select Uint16 SOCBEN:1; // 15 Start of Conversion B Enable }; union ETSEL_REG { Uint16 all; struct ETSEL_BITS bit; }; struct ETPS_BITS { // bits description Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits Uint16 rsvd1:2; // 7:6 Reserved Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter }; union ETPS_REG { Uint16 all; struct ETPS_BITS bit; }; struct ETFLG_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Flag Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Flag Uint16 SOCB:1; // 3 EPWMxSOCB Flag Uint16 rsvd2:12; // 15:4 Reserved }; union ETFLG_REG { Uint16 all; struct ETFLG_BITS bit; }; struct ETCLR_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Clear Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Clear Uint16 SOCB:1; // 3 EPWMxSOCB Clear Uint16 rsvd2:12; // 15:4 Reserved }; union ETCLR_REG { Uint16 all; struct ETCLR_BITS bit; }; struct ETFRC_BITS { // bits description Uint16 INT:1; // 0 EPWMxINTn Force Uint16 rsvd1:1; // 1 Reserved Uint16 SOCA:1; // 2 EPWMxSOCA Force Uint16 SOCB:1; // 3 EPWMxSOCB Force Uint16 rsvd2:12; // 15:4 Reserved }; union ETFRC_REG { Uint16 all; struct ETFRC_BITS bit; }; struct ETINTPS_BITS { // bits description Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register Uint16 rsvd1:8; // 15:8 Reserved }; union ETINTPS_REG { Uint16 all; struct ETINTPS_BITS bit; }; struct ETSOCPS_BITS { // bits description Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register }; union ETSOCPS_REG { Uint16 all; struct ETSOCPS_BITS bit; }; struct ETCNTINITCTL_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable }; union ETCNTINITCTL_REG { Uint16 all; struct ETCNTINITCTL_BITS bit; }; struct ETCNTINIT_BITS { // bits description Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits Uint16 rsvd1:4; // 15:12 Reserved }; union ETCNTINIT_REG { Uint16 all; struct ETCNTINIT_BITS bit; }; struct DCTRIPSEL_BITS { // bits description Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select }; union DCTRIPSEL_REG { Uint16 all; struct DCTRIPSEL_BITS bit; }; struct DCACTL_BITS { // bits description Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable Uint16 EVT1LATSEL:1; // 4 DCAEVT1 Latched signal select Uint16 EVT1LATCLRSEL:2; // 6:5 DCAEVT1 Latched clear source select Uint16 EVT1LAT:1; // 7 Indicates the status of DCAEVT1LAT signal. Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal Uint16 rsvd1:2; // 11:10 Reserved Uint16 EVT2LATSEL:1; // 12 DCAEVT2 Latched signal select Uint16 EVT2LATCLRSEL:2; // 14:13 DCAEVT2 Latched clear source select Uint16 EVT2LAT:1; // 15 Indicates the status of DCAEVT2LAT signal. }; union DCACTL_REG { Uint16 all; struct DCACTL_BITS bit; }; struct DCBCTL_BITS { // bits description Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable Uint16 EVT1LATSEL:1; // 4 DCBEVT1 Latched signal select Uint16 EVT1LATCLRSEL:2; // 6:5 DCBEVT1 Latched clear source select Uint16 EVT1LAT:1; // 7 Indicates the status of DCBEVT1LAT signal. Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal Uint16 rsvd1:2; // 11:10 Reserved Uint16 EVT2LATSEL:1; // 12 DCBEVT2 Latched signal select Uint16 EVT2LATCLRSEL:2; // 14:13 DCBEVT2 Latched clear source select Uint16 EVT2LAT:1; // 15 Indicates the status of DCBEVT2LAT signal. }; union DCBCTL_REG { Uint16 all; struct DCBCTL_BITS bit; }; struct DCFCTL_BITS { // bits description Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select Uint16 BLANKE:1; // 2 Blanking Enable/Disable Uint16 BLANKINV:1; // 3 Blanking Window Inversion Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select Uint16 rsvd1:1; // 7 Reserved Uint16 EDGEMODE:2; // 9:8 Edge Mode Uint16 EDGECOUNT:3; // 12:10 Edge Count Uint16 EDGESTATUS:3; // 15:13 Edge Status }; union DCFCTL_REG { Uint16 all; struct DCFCTL_BITS bit; }; struct DCCAPCTL_BITS { // bits description Uint16 CAPE:1; // 0 Counter Capture Enable Uint16 SHDWMODE:1; // 1 Counter Capture Mode Uint16 rsvd1:11; // 12:2 Reserved Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag Uint16 CAPMODE:1; // 15 Counter Capture Mode }; union DCCAPCTL_REG { Uint16 all; struct DCCAPCTL_BITS bit; }; struct DCAHTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux Uint16 rsvd2:1; // 15 Reserved }; union DCAHTRIPSEL_REG { Uint16 all; struct DCAHTRIPSEL_BITS bit; }; struct DCALTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux Uint16 rsvd2:1; // 15 Reserved }; union DCALTRIPSEL_REG { Uint16 all; struct DCALTRIPSEL_BITS bit; }; struct DCBHTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux Uint16 rsvd2:1; // 15 Reserved }; union DCBHTRIPSEL_REG { Uint16 all; struct DCBHTRIPSEL_BITS bit; }; struct DCBLTRIPSEL_BITS { // bits description Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux Uint16 rsvd1:1; // 12 Reserved Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux Uint16 rsvd2:1; // 15 Reserved }; union DCBLTRIPSEL_REG { Uint16 all; struct DCBLTRIPSEL_BITS bit; }; struct EPWMLOCK_BITS { // bits description Uint16 HRLOCK:1; // 0 HRPWM Register Set Lock Uint16 GLLOCK:1; // 1 Global Load Register Set Lock Uint16 TZCFGLOCK:1; // 2 TripZone Register Set Lock Uint16 TZCLRLOCK:1; // 3 TripZone Clear Register Set Lock Uint16 DCLOCK:1; // 4 Digital Compare Register Set Lock Uint16 rsvd1:11; // 15:5 Reserved Uint16 KEY:16; // 31:16 Key to write to this register }; union EPWMLOCK_REG { Uint32 all; struct EPWMLOCK_BITS bit; }; struct EPWM_REGS { union TBCTL_REG TBCTL; // Time Base Control Register union TBCTL2_REG TBCTL2; // Time Base Control Register 2 Uint16 rsvd1; // Reserved union EPWMSYNCINSEL_REG EPWMSYNCINSEL; // EPWMxSYNCIN Source Select Register Uint16 TBCTR; // Time Base Counter Register union TBSTS_REG TBSTS; // Time Base Status Register union EPWMSYNCOUTEN_REG EPWMSYNCOUTEN; // EPWMxSYNCOUT Source Enable Register union TBCTL3_REG TBCTL3; // Time Base Control Register 3 union CMPCTL_REG CMPCTL; // Counter Compare Control Register union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 Uint16 rsvd2[2]; // Reserved union DBCTL_REG DBCTL; // Dead-Band Generator Control Register union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 Uint16 rsvd3[2]; // Reserved union AQCTL_REG AQCTL; // Action Qualifier Control Register union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register Uint16 rsvd4[2]; // Reserved union PCCTL_REG PCCTL; // PWM Chopper Control Register Uint16 rsvd5[3]; // Reserved union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register Uint16 rsvd6[6]; // Reserved union HRCNFG_REG HRCNFG; // HRPWM Configuration Register union HRPWR_REG HRPWR; // HRPWM Power Register Uint16 rsvd7[4]; // Reserved union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register Uint16 rsvd8[5]; // Reserved union HRPCTL_REG HRPCTL; // High Resolution Period Control Register union TRREM_REG TRREM; // Translator High Resolution Remainder Register Uint16 rsvd9[5]; // Reserved union GLDCTL_REG GLDCTL; // Global PWM Load Control Register union GLDCFG_REG GLDCFG; // Global PWM Load Config Register Uint16 rsvd10[2]; // Reserved union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register Uint16 rsvd11[6]; // Reserved union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B Uint16 rsvd12[3]; // Reserved union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register Uint16 rsvd13; // Reserved union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register Uint16 rsvd14[6]; // Reserved union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register Uint16 rsvd15[12]; // Reserved union TBPHS_REG TBPHS; // Time Base Phase High Uint16 TBPRDHR; // Time Base Period High Resolution Register Uint16 TBPRD; // Time Base Period Register Uint16 rsvd16[6]; // Reserved union CMPA_REG CMPA; // Counter Compare A Register union CMPB_REG CMPB; // Compare B Register Uint16 rsvd17; // Reserved Uint16 CMPC; // Counter Compare C Register Uint16 rsvd18; // Reserved Uint16 CMPD; // Counter Compare D Register Uint16 rsvd19[2]; // Reserved union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 Uint16 rsvd20[2]; // Reserved Uint16 SWVDELVAL; // Software Valley Mode Delay Register Uint16 rsvd21[8]; // Reserved union TZSEL_REG TZSEL; // Trip Zone Select Register Uint16 rsvd22; // Reserved union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register Uint16 rsvd23; // Reserved union TZCTL_REG TZCTL; // Trip Zone Control Register union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B Uint16 rsvd24[5]; // Reserved union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register Uint16 rsvd25[5]; // Reserved union TZFLG_REG TZFLG; // Trip Zone Flag Register union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register Uint16 rsvd26; // Reserved union TZCLR_REG TZCLR; // Trip Zone Clear Register union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register Uint16 rsvd27; // Reserved union TZFRC_REG TZFRC; // Trip Zone Force Register Uint16 rsvd28[8]; // Reserved union ETSEL_REG ETSEL; // Event Trigger Selection Register Uint16 rsvd29; // Reserved union ETPS_REG ETPS; // Event Trigger Pre-Scale Register Uint16 rsvd30; // Reserved union ETFLG_REG ETFLG; // Event Trigger Flag Register Uint16 rsvd31; // Reserved union ETCLR_REG ETCLR; // Event Trigger Clear Register Uint16 rsvd32; // Reserved union ETFRC_REG ETFRC; // Event Trigger Force Register Uint16 rsvd33; // Reserved union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register Uint16 rsvd34; // Reserved union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register Uint16 rsvd35; // Reserved union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register Uint16 rsvd36; // Reserved union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register Uint16 rsvd37[11]; // Reserved union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register Uint16 rsvd38[2]; // Reserved union DCACTL_REG DCACTL; // Digital Compare A Control Register union DCBCTL_REG DCBCTL; // Digital Compare B Control Register Uint16 rsvd39[2]; // Reserved union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register Uint16 DCFOFFSET; // Digital Compare Filter Offset Register Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register Uint16 DCFWINDOW; // Digital Compare Filter Window Register Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register Uint16 rsvd40[2]; // Reserved Uint16 DCCAP; // Digital Compare Counter Capture Register Uint16 rsvd41[2]; // Reserved union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select Uint16 rsvd42[36]; // Reserved union EPWMLOCK_REG EPWMLOCK; // EPWM Lock Register Uint16 rsvd43; // Reserved Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register Uint16 VCNTVAL; // Hardware Valley Counter Register }; //--------------------------------------------------------------------------- // EPWM External References & Function Declarations: // extern volatile struct EPWM_REGS EPwm1Regs; extern volatile struct EPWM_REGS EPwm2Regs; extern volatile struct EPWM_REGS EPwm3Regs; extern volatile struct EPWM_REGS EPwm4Regs; extern volatile struct EPWM_REGS EPwm5Regs; extern volatile struct EPWM_REGS EPwm6Regs; extern volatile struct EPWM_REGS EPwm7Regs; extern volatile struct EPWM_REGS EPwm8Regs; extern volatile struct EPWM_REGS EPwm9Regs; extern volatile struct EPWM_REGS EPwm10Regs; extern volatile struct EPWM_REGS EPwm11Regs; extern volatile struct EPWM_REGS EPwm12Regs; extern volatile struct EPWM_REGS EPwm13Regs; extern volatile struct EPWM_REGS EPwm14Regs; extern volatile struct EPWM_REGS EPwm15Regs; extern volatile struct EPWM_REGS EPwm16Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_epwmxbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XBAR Individual Register Bit Definitions: struct TRIP4MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR }; union TRIP4MUX0TO15CFG_REG { Uint32 all; struct TRIP4MUX0TO15CFG_BITS bit; }; struct TRIP4MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR }; union TRIP4MUX16TO31CFG_REG { Uint32 all; struct TRIP4MUX16TO31CFG_BITS bit; }; struct TRIP5MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR }; union TRIP5MUX0TO15CFG_REG { Uint32 all; struct TRIP5MUX0TO15CFG_BITS bit; }; struct TRIP5MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR }; union TRIP5MUX16TO31CFG_REG { Uint32 all; struct TRIP5MUX16TO31CFG_BITS bit; }; struct TRIP7MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR }; union TRIP7MUX0TO15CFG_REG { Uint32 all; struct TRIP7MUX0TO15CFG_BITS bit; }; struct TRIP7MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR }; union TRIP7MUX16TO31CFG_REG { Uint32 all; struct TRIP7MUX16TO31CFG_BITS bit; }; struct TRIP8MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR }; union TRIP8MUX0TO15CFG_REG { Uint32 all; struct TRIP8MUX0TO15CFG_BITS bit; }; struct TRIP8MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR }; union TRIP8MUX16TO31CFG_REG { Uint32 all; struct TRIP8MUX16TO31CFG_BITS bit; }; struct TRIP9MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR }; union TRIP9MUX0TO15CFG_REG { Uint32 all; struct TRIP9MUX0TO15CFG_BITS bit; }; struct TRIP9MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR }; union TRIP9MUX16TO31CFG_REG { Uint32 all; struct TRIP9MUX16TO31CFG_BITS bit; }; struct TRIP10MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR }; union TRIP10MUX0TO15CFG_REG { Uint32 all; struct TRIP10MUX0TO15CFG_BITS bit; }; struct TRIP10MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR }; union TRIP10MUX16TO31CFG_REG { Uint32 all; struct TRIP10MUX16TO31CFG_BITS bit; }; struct TRIP11MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR }; union TRIP11MUX0TO15CFG_REG { Uint32 all; struct TRIP11MUX0TO15CFG_BITS bit; }; struct TRIP11MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR }; union TRIP11MUX16TO31CFG_REG { Uint32 all; struct TRIP11MUX16TO31CFG_BITS bit; }; struct TRIP12MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR }; union TRIP12MUX0TO15CFG_REG { Uint32 all; struct TRIP12MUX0TO15CFG_BITS bit; }; struct TRIP12MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR }; union TRIP12MUX16TO31CFG_REG { Uint32 all; struct TRIP12MUX16TO31CFG_BITS bit; }; struct TRIP4MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR }; union TRIP4MUXENABLE_REG { Uint32 all; struct TRIP4MUXENABLE_BITS bit; }; struct TRIP5MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR }; union TRIP5MUXENABLE_REG { Uint32 all; struct TRIP5MUXENABLE_BITS bit; }; struct TRIP7MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR }; union TRIP7MUXENABLE_REG { Uint32 all; struct TRIP7MUXENABLE_BITS bit; }; struct TRIP8MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR }; union TRIP8MUXENABLE_REG { Uint32 all; struct TRIP8MUXENABLE_BITS bit; }; struct TRIP9MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR }; union TRIP9MUXENABLE_REG { Uint32 all; struct TRIP9MUXENABLE_BITS bit; }; struct TRIP10MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR }; union TRIP10MUXENABLE_REG { Uint32 all; struct TRIP10MUXENABLE_BITS bit; }; struct TRIP11MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR }; union TRIP11MUXENABLE_REG { Uint32 all; struct TRIP11MUXENABLE_BITS bit; }; struct TRIP12MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR }; union TRIP12MUXENABLE_REG { Uint32 all; struct TRIP12MUXENABLE_BITS bit; }; struct TRIPOUTINV_BITS { // bits description Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union TRIPOUTINV_REG { Uint32 all; struct TRIPOUTINV_BITS bit; }; struct TRIPLOCK_BITS { // bits description Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Write protection KEY }; union TRIPLOCK_REG { Uint32 all; struct TRIPLOCK_BITS bit; }; struct EPWM_XBAR_REGS { union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 Uint16 rsvd1[8]; // Reserved union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register Uint16 rsvd2[4]; // Reserved union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register }; //--------------------------------------------------------------------------- // EPWM_XBAR External References & Function Declarations: // extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_eqep.h // // TITLE: Definitions for the EQEP registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // EQEP Individual Register Bit Definitions: struct QDECCTL_BITS { // bits description Uint16 QIDIRE:1; // 0 Qep Index Direction Enhancement enable Uint16 rsvd1:4; // 4:1 Reserved Uint16 QSP:1; // 5 QEPS input polarity Uint16 QIP:1; // 6 QEPI input polarity Uint16 QBP:1; // 7 QEPB input polarity Uint16 QAP:1; // 8 QEPA input polarity Uint16 IGATE:1; // 9 Index pulse gating option Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter Uint16 XCR:1; // 11 External Clock Rate Uint16 SPSEL:1; // 12 Sync output pin selection Uint16 SOEN:1; // 13 Sync output-enable Uint16 QSRC:2; // 15:14 Position-counter source selection }; union QDECCTL_REG { Uint16 all; struct QDECCTL_BITS bit; }; struct QEPCTL_BITS { // bits description Uint16 WDE:1; // 0 QEP watchdog enable Uint16 UTE:1; // 1 QEP unit timer enable Uint16 QCLM:1; // 2 QEP capture latch mode Uint16 QPEN:1; // 3 Quadrature postotion counter enable Uint16 IEL:2; // 5:4 Index event latch Uint16 SEL:1; // 6 Strobe event latch Uint16 SWI:1; // 7 Software init position counter Uint16 IEI:2; // 9:8 Index event init of position count Uint16 SEI:2; // 11:10 Strobe event init Uint16 PCRM:2; // 13:12 Postion counter reset Uint16 FREE_SOFT:2; // 15:14 Emulation mode }; union QEPCTL_REG { Uint16 all; struct QEPCTL_BITS bit; }; struct QCAPCTL_BITS { // bits description Uint16 UPPS:4; // 3:0 Unit position event prescaler Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler Uint16 rsvd1:8; // 14:7 Reserved Uint16 CEN:1; // 15 Enable eQEP capture }; union QCAPCTL_REG { Uint16 all; struct QCAPCTL_BITS bit; }; struct QPOSCTL_BITS { // bits description Uint16 PCSPW:12; // 11:0 Position compare sync pulse width Uint16 PCE:1; // 12 Position compare enable/disable Uint16 PCPOL:1; // 13 Polarity of sync output Uint16 PCLOAD:1; // 14 Position compare of shadow load Uint16 PCSHDW:1; // 15 Position compare of shadow enable }; union QPOSCTL_REG { Uint16 all; struct QPOSCTL_BITS bit; }; struct QEINT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PCE:1; // 1 Position counter error interrupt enable Uint16 QPE:1; // 2 Quadrature phase error interrupt enable Uint16 QDC:1; // 3 Quadrature direction change interrupt enable Uint16 WTO:1; // 4 Watchdog time out interrupt enable Uint16 PCU:1; // 5 Position counter underflow interrupt enable Uint16 PCO:1; // 6 Position counter overflow interrupt enable Uint16 PCR:1; // 7 Position-compare ready interrupt enable Uint16 PCM:1; // 8 Position-compare match interrupt enable Uint16 SEL:1; // 9 Strobe event latch interrupt enable Uint16 IEL:1; // 10 Index event latch interrupt enable Uint16 UTO:1; // 11 Unit time out interrupt enable Uint16 QMAE:1; // 12 QMA error interrupt enable Uint16 rsvd2:3; // 15:13 Reserved }; union QEINT_REG { Uint16 all; struct QEINT_BITS bit; }; struct QFLG_BITS { // bits description Uint16 INT:1; // 0 Global interrupt status flag Uint16 PCE:1; // 1 Position counter error interrupt flag Uint16 PHE:1; // 2 Quadrature phase error interrupt flag Uint16 QDC:1; // 3 Quadrature direction change interrupt flag Uint16 WTO:1; // 4 Watchdog timeout interrupt flag Uint16 PCU:1; // 5 Position counter underflow interrupt flag Uint16 PCO:1; // 6 Position counter overflow interrupt flag Uint16 PCR:1; // 7 Position-compare ready interrupt flag Uint16 PCM:1; // 8 eQEP compare match event interrupt flag Uint16 SEL:1; // 9 Strobe event latch interrupt flag Uint16 IEL:1; // 10 Index event latch interrupt flag Uint16 UTO:1; // 11 Unit time out interrupt flag Uint16 QMAE:1; // 12 QMA error interrupt flag Uint16 rsvd1:3; // 15:13 Reserved }; union QFLG_REG { Uint16 all; struct QFLG_BITS bit; }; struct QCLR_BITS { // bits description Uint16 INT:1; // 0 Global interrupt clear flag Uint16 PCE:1; // 1 Clear position counter error interrupt flag Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag Uint16 IEL:1; // 10 Clear index event latch interrupt flag Uint16 UTO:1; // 11 Clear unit time out interrupt flag Uint16 QMAE:1; // 12 Clear QMA error interrupt flag Uint16 rsvd1:3; // 15:13 Reserved }; union QCLR_REG { Uint16 all; struct QCLR_BITS bit; }; struct QFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PCE:1; // 1 Force position counter error interrupt Uint16 PHE:1; // 2 Force quadrature phase error interrupt Uint16 QDC:1; // 3 Force quadrature direction change interrupt Uint16 WTO:1; // 4 Force watchdog time out interrupt Uint16 PCU:1; // 5 Force position counter underflow interrupt Uint16 PCO:1; // 6 Force position counter overflow interrupt Uint16 PCR:1; // 7 Force position-compare ready interrupt Uint16 PCM:1; // 8 Force position-compare match interrupt Uint16 SEL:1; // 9 Force strobe event latch interrupt Uint16 IEL:1; // 10 Force index event latch interrupt Uint16 UTO:1; // 11 Force unit time out interrupt Uint16 QMAE:1; // 12 Force QMA error interrupt Uint16 rsvd2:3; // 15:13 Reserved }; union QFRC_REG { Uint16 all; struct QFRC_BITS bit; }; struct QEPSTS_BITS { // bits description Uint16 PCEF:1; // 0 Position counter error flag. Uint16 FIMF:1; // 1 First index marker flag Uint16 CDEF:1; // 2 Capture direction error flag Uint16 COEF:1; // 3 Capture overflow error flag Uint16 QDLF:1; // 4 eQEP direction latch flag Uint16 QDF:1; // 5 Quadrature direction flag Uint16 FIDF:1; // 6 The first index marker Uint16 UPEVNT:1; // 7 Unit position event flag Uint16 rsvd1:8; // 15:8 Reserved }; union QEPSTS_REG { Uint16 all; struct QEPSTS_BITS bit; }; struct REV_BITS { // bits description Uint16 MAJOR:3; // 2:0 Major Revision Number Uint16 MINOR:3; // 5:3 Minor Revision Number Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union REV_REG { Uint32 all; struct REV_BITS bit; }; struct QEPSTROBESEL_BITS { // bits description Uint16 STROBESEL:2; // 1:0 QMA Mode Select Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union QEPSTROBESEL_REG { Uint32 all; struct QEPSTROBESEL_BITS bit; }; struct QMACTRL_BITS { // bits description Uint16 MODE:3; // 2:0 QMA Mode Select Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union QMACTRL_REG { Uint32 all; struct QMACTRL_BITS bit; }; struct QEPSRCSEL_BITS { // bits description Uint16 QEPASEL:4; // 3:0 QEPA Source select Uint16 QEPBSEL:4; // 7:4 QEPB Source select Uint16 QEPISEL:4; // 11:8 QEPI Source select Uint16 QEPSSEL:4; // 15:12 QEPS Source select Uint16 rsvd1:16; // 31:16 Reserved }; union QEPSRCSEL_REG { Uint32 all; struct QEPSRCSEL_BITS bit; }; struct EQEP_REGS { Uint32 QPOSCNT; // Position Counter Uint32 QPOSINIT; // Position Counter Init Uint32 QPOSMAX; // Maximum Position Count Uint32 QPOSCMP; // Position Compare Uint32 QPOSILAT; // Index Position Latch Uint32 QPOSSLAT; // Strobe Position Latch Uint32 QPOSLAT; // Position Latch Uint32 QUTMR; // QEP Unit Timer Uint32 QUPRD; // QEP Unit Period Uint16 QWDTMR; // QEP Watchdog Timer Uint16 QWDPRD; // QEP Watchdog Period union QDECCTL_REG QDECCTL; // Quadrature Decoder Control union QEPCTL_REG QEPCTL; // QEP Control union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control union QPOSCTL_REG QPOSCTL; // Position Compare Control union QEINT_REG QEINT; // QEP Interrupt Control union QFLG_REG QFLG; // QEP Interrupt Flag union QCLR_REG QCLR; // QEP Interrupt Clear union QFRC_REG QFRC; // QEP Interrupt Force union QEPSTS_REG QEPSTS; // QEP Status Uint16 QCTMR; // QEP Capture Timer Uint16 QCPRD; // QEP Capture Period Uint16 QCTMRLAT; // QEP Capture Latch Uint16 QCPRDLAT; // QEP Capture Period Latch Uint16 rsvd1[15]; // Reserved union REV_REG REV; // QEP Revision Number union QEPSTROBESEL_REG QEPSTROBESEL; // QEP Strobe select register union QMACTRL_REG QMACTRL; // QMA Control register union QEPSRCSEL_REG QEPSRCSEL; // QEP Source Select Register }; //--------------------------------------------------------------------------- // EQEP External References & Function Declarations: // extern volatile struct EQEP_REGS EQep1Regs; extern volatile struct EQEP_REGS EQep2Regs; extern volatile struct EQEP_REGS EQep3Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_erad.h // // TITLE: Definitions for the ERAD registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // ERAD Individual Register Bit Definitions: struct GLBL_EVENT_STAT_BITS { // bits description Uint16 HWBP1:1; // 0 Bus Comparator Module Event Status Uint16 HWBP2:1; // 1 Bus Comparator Module Event Status Uint16 HWBP3:1; // 2 Bus Comparator Module Event Status Uint16 HWBP4:1; // 3 Bus Comparator Module Event Status Uint16 HWBP5:1; // 4 Bus Comparator Module Event Status Uint16 HWBP6:1; // 5 Bus Comparator Module Event Status Uint16 HWBP7:1; // 6 Bus Comparator Module Event Status Uint16 HWBP8:1; // 7 Bus Comparator Module Event Status Uint16 CTM1:1; // 8 Counter Module Event Status Uint16 CTM2:1; // 9 Counter Module Event Status Uint16 CTM3:1; // 10 Counter Module Event Status Uint16 CTM4:1; // 11 Counter Module Event Status Uint16 rsvd1:4; // 15:12 Reserved }; union GLBL_EVENT_STAT_REG { Uint16 all; struct GLBL_EVENT_STAT_BITS bit; }; struct GLBL_HALT_STAT_BITS { // bits description Uint16 HWBP1:1; // 0 Bus Comparator Module Halt Status Uint16 HWBP2:1; // 1 Bus Comparator Module Halt Status Uint16 HWBP3:1; // 2 Bus Comparator Module Halt Status Uint16 HWBP4:1; // 3 Bus Comparator Module Halt Status Uint16 HWBP5:1; // 4 Bus Comparator Module Halt Status Uint16 HWBP6:1; // 5 Bus Comparator Module Halt Status Uint16 HWBP7:1; // 6 Bus Comparator Module Halt Status Uint16 HWBP8:1; // 7 Bus Comparator Module Halt Status Uint16 CTM1:1; // 8 Counter Module Halt Status Uint16 CTM2:1; // 9 Counter Module Halt Status Uint16 CTM3:1; // 10 Counter Module Halt Status Uint16 CTM4:1; // 11 Counter Module Halt Status Uint16 rsvd1:4; // 15:12 Reserved }; union GLBL_HALT_STAT_REG { Uint16 all; struct GLBL_HALT_STAT_BITS bit; }; struct GLBL_ENABLE_BITS { // bits description Uint16 HWBP1:1; // 0 Bus Comparator Module Global Enable Uint16 HWBP2:1; // 1 Bus Comparator Module Global Enable Uint16 HWBP3:1; // 2 Bus Comparator Module Global Enable Uint16 HWBP4:1; // 3 Bus Comparator Module Global Enable Uint16 HWBP5:1; // 4 Bus Comparator Module Global Enable Uint16 HWBP6:1; // 5 Bus Comparator Module Global Enable Uint16 HWBP7:1; // 6 Bus Comparator Module Global Enable Uint16 HWBP8:1; // 7 Bus Comparator Module Global Enable Uint16 CTM1:1; // 8 Counter Module Global Enable Uint16 CTM2:1; // 9 Counter Module Global Enable Uint16 CTM3:1; // 10 Counter Module Global Enable Uint16 CTM4:1; // 11 Counter Module Global Enable Uint16 rsvd1:4; // 15:12 Reserved }; union GLBL_ENABLE_REG { Uint16 all; struct GLBL_ENABLE_BITS bit; }; struct GLBL_CTM_RESET_BITS { // bits description Uint16 CTM1:1; // 0 Global Reset for the counters Uint16 CTM2:1; // 1 Global Reset for the counters Uint16 CTM3:1; // 2 Global Reset for the counters Uint16 CTM4:1; // 3 Global Reset for the counters Uint16 rsvd1:12; // 15:4 Reserved }; union GLBL_CTM_RESET_REG { Uint16 all; struct GLBL_CTM_RESET_BITS bit; }; struct GLBL_NMI_CTL_BITS { // bits description Uint16 HWBP1:1; // 0 Bus Comparator non-maskable interrupt enable Uint16 HWBP2:1; // 1 Bus Comparator non-maskable interrupt enable Uint16 HWBP3:1; // 2 Bus Comparator non-maskable interrupt enable Uint16 HWBP4:1; // 3 Bus Comparator non-maskable interrupt enable Uint16 HWBP5:1; // 4 Bus Comparator non-maskable interrupt enable Uint16 HWBP6:1; // 5 Bus Comparator non-maskable interrupt enable Uint16 HWBP7:1; // 6 Bus Comparator non-maskable interrupt enable Uint16 HWBP8:1; // 7 Bus Comparator non-maskable interrupt enable Uint16 CTM1:1; // 8 Counter non-maskable interrupt enable Uint16 CTM2:1; // 9 Counter non-maskable interrupt enable Uint16 CTM3:1; // 10 Counter non-maskable interrupt enable Uint16 CTM4:1; // 11 Counter non-maskable interrupt enable Uint16 rsvd1:4; // 15:12 Reserved }; union GLBL_NMI_CTL_REG { Uint16 all; struct GLBL_NMI_CTL_BITS bit; }; struct GLBL_OWNER_BITS { // bits description Uint16 OWNER:2; // 1:0 Global Ownership Bits Uint16 rsvd1:14; // 15:2 Reserved }; union GLBL_OWNER_REG { Uint16 all; struct GLBL_OWNER_BITS bit; }; struct GLBL_EVENT_AND_MASK_BITS { // bits description Uint16 MASK1_HWBP1:1; // 0 Bus Comparator AND Event Mask1 Uint16 MASK1_HWBP2:1; // 1 Bus Comparator AND Event Mask1 Uint16 MASK1_HWBP3:1; // 2 Bus Comparator AND Event Mask1 Uint16 MASK1_HWBP4:1; // 3 Bus Comparator AND Event Mask1 Uint16 MASK1_HWBP5:1; // 4 Bus Comparator AND Event Mask1 Uint16 MASK1_HWBP6:1; // 5 Bus Comparator AND Event Mask1 Uint16 MASK1_HWBP7:1; // 6 Bus Comparator AND Event Mask1 Uint16 MASK1_HWBP8:1; // 7 Bus Comparator AND Event Mask1 Uint16 MASK2_HWBP1:1; // 8 Bus Comparator AND Event Mask2 Uint16 MASK2_HWBP2:1; // 9 Bus Comparator AND Event Mask2 Uint16 MASK2_HWBP3:1; // 10 Bus Comparator AND Event Mask2 Uint16 MASK2_HWBP4:1; // 11 Bus Comparator AND Event Mask2 Uint16 MASK2_HWBP5:1; // 12 Bus Comparator AND Event Mask2 Uint16 MASK2_HWBP6:1; // 13 Bus Comparator AND Event Mask2 Uint16 MASK2_HWBP7:1; // 14 Bus Comparator AND Event Mask2 Uint16 MASK2_HWBP8:1; // 15 Bus Comparator AND Event Mask2 Uint16 MASK3_HWBP1:1; // 16 Bus Comparator AND Event Mask3 Uint16 MASK3_HWBP2:1; // 17 Bus Comparator AND Event Mask3 Uint16 MASK3_HWBP3:1; // 18 Bus Comparator AND Event Mask3 Uint16 MASK3_HWBP4:1; // 19 Bus Comparator AND Event Mask3 Uint16 MASK3_HWBP5:1; // 20 Bus Comparator AND Event Mask3 Uint16 MASK3_HWBP6:1; // 21 Bus Comparator AND Event Mask3 Uint16 MASK3_HWBP7:1; // 22 Bus Comparator AND Event Mask3 Uint16 MASK3_HWBP8:1; // 23 Bus Comparator AND Event Mask3 Uint16 MASK4_HWBP1:1; // 24 Bus Comparator AND Event Mask4 Uint16 MASK4_HWBP2:1; // 25 Bus Comparator AND Event Mask4 Uint16 MASK4_HWBP3:1; // 26 Bus Comparator AND Event Mask4 Uint16 MASK4_HWBP4:1; // 27 Bus Comparator AND Event Mask4 Uint16 MASK4_HWBP5:1; // 28 Bus Comparator AND Event Mask4 Uint16 MASK4_HWBP6:1; // 29 Bus Comparator AND Event Mask4 Uint16 MASK4_HWBP7:1; // 30 Bus Comparator AND Event Mask4 Uint16 MASK4_HWBP8:1; // 31 Bus Comparator AND Event Mask4 }; union GLBL_EVENT_AND_MASK_REG { Uint32 all; struct GLBL_EVENT_AND_MASK_BITS bit; }; struct GLBL_EVENT_OR_MASK_BITS { // bits description Uint16 MASK1_HWBP1:1; // 0 Bus Comparator OR Event Mask1 Uint16 MASK1_HWBP2:1; // 1 Bus Comparator OR Event Mask1 Uint16 MASK1_HWBP3:1; // 2 Bus Comparator OR Event Mask1 Uint16 MASK1_HWBP4:1; // 3 Bus Comparator OR Event Mask1 Uint16 MASK1_HWBP5:1; // 4 Bus Comparator OR Event Mask1 Uint16 MASK1_HWBP6:1; // 5 Bus Comparator OR Event Mask1 Uint16 MASK1_HWBP7:1; // 6 Bus Comparator OR Event Mask1 Uint16 MASK1_HWBP8:1; // 7 Bus Comparator OR Event Mask1 Uint16 MASK2_HWBP1:1; // 8 Bus Comparator OR Event Mask2 Uint16 MASK2_HWBP2:1; // 9 Bus Comparator OR Event Mask2 Uint16 MASK2_HWBP3:1; // 10 Bus Comparator OR Event Mask2 Uint16 MASK2_HWBP4:1; // 11 Bus Comparator OR Event Mask2 Uint16 MASK2_HWBP5:1; // 12 Bus Comparator OR Event Mask2 Uint16 MASK2_HWBP6:1; // 13 Bus Comparator OR Event Mask2 Uint16 MASK2_HWBP7:1; // 14 Bus Comparator OR Event Mask2 Uint16 MASK2_HWBP8:1; // 15 Bus Comparator OR Event Mask2 Uint16 MASK3_HWBP1:1; // 16 Bus Comparator OR Event Mask3 Uint16 MASK3_HWBP2:1; // 17 Bus Comparator OR Event Mask3 Uint16 MASK3_HWBP3:1; // 18 Bus Comparator OR Event Mask3 Uint16 MASK3_HWBP4:1; // 19 Bus Comparator OR Event Mask3 Uint16 MASK3_HWBP5:1; // 20 Bus Comparator OR Event Mask3 Uint16 MASK3_HWBP6:1; // 21 Bus Comparator OR Event Mask3 Uint16 MASK3_HWBP7:1; // 22 Bus Comparator OR Event Mask3 Uint16 MASK3_HWBP8:1; // 23 Bus Comparator OR Event Mask3 Uint16 MASK4_HWBP1:1; // 24 Bus Comparator OR Event Mask4 Uint16 MASK4_HWBP2:1; // 25 Bus Comparator OR Event Mask4 Uint16 MASK4_HWBP3:1; // 26 Bus Comparator OR Event Mask4 Uint16 MASK4_HWBP4:1; // 27 Bus Comparator OR Event Mask4 Uint16 MASK4_HWBP5:1; // 28 Bus Comparator OR Event Mask4 Uint16 MASK4_HWBP6:1; // 29 Bus Comparator OR Event Mask4 Uint16 MASK4_HWBP7:1; // 30 Bus Comparator OR Event Mask4 Uint16 MASK4_HWBP8:1; // 31 Bus Comparator OR Event Mask4 }; union GLBL_EVENT_OR_MASK_REG { Uint32 all; struct GLBL_EVENT_OR_MASK_BITS bit; }; struct GLBL_AND_EVENT_INT_MASK_BITS { // bits description Uint16 RTOSINT_MASK1:1; // 0 RTOSINT generation mask for global AND events Uint16 RTOSINT_MASK2:1; // 1 RTOSINT generation mask for global AND events Uint16 RTOSINT_MASK3:1; // 2 RTOSINT generation mask for global AND events Uint16 RTOSINT_MASK4:1; // 3 RTOSINT generation mask for global AND events Uint16 rsvd1:12; // 15:4 Reserved }; union GLBL_AND_EVENT_INT_MASK_REG { Uint16 all; struct GLBL_AND_EVENT_INT_MASK_BITS bit; }; struct GLBL_OR_EVENT_INT_MASK_BITS { // bits description Uint16 RTOSINT_MASK1:1; // 0 RTOSINT generation mask for global OR events Uint16 RTOSINT_MASK2:1; // 1 RTOSINT generation mask for global OR events Uint16 RTOSINT_MASK3:1; // 2 RTOSINT generation mask for global OR events Uint16 RTOSINT_MASK4:1; // 3 RTOSINT generation mask for global OR events Uint16 rsvd1:12; // 15:4 Reserved }; union GLBL_OR_EVENT_INT_MASK_REG { Uint16 all; struct GLBL_OR_EVENT_INT_MASK_BITS bit; }; struct ERAD_GLOBAL_REGS { union GLBL_EVENT_STAT_REG GLBL_EVENT_STAT; // Global Event Status Register Uint16 rsvd1; // Reserved union GLBL_HALT_STAT_REG GLBL_HALT_STAT; // Global Halt Status Register Uint16 rsvd2; // Reserved union GLBL_ENABLE_REG GLBL_ENABLE; // Global Enable Register Uint16 rsvd3; // Reserved union GLBL_CTM_RESET_REG GLBL_CTM_RESET; // Global Counter Reset Uint16 rsvd4; // Reserved union GLBL_NMI_CTL_REG GLBL_NMI_CTL; // Global Debug NMI control Uint16 rsvd5; // Reserved union GLBL_OWNER_REG GLBL_OWNER; // Global Ownership Uint16 rsvd6; // Reserved union GLBL_EVENT_AND_MASK_REG GLBL_EVENT_AND_MASK; // Global Bus Comparator Event AND Mask Register union GLBL_EVENT_OR_MASK_REG GLBL_EVENT_OR_MASK; // Global Bus Comparator Event OR Mask Register union GLBL_AND_EVENT_INT_MASK_REG GLBL_AND_EVENT_INT_MASK; // Global AND Event Interrupt Mask Register Uint16 rsvd7; // Reserved union GLBL_OR_EVENT_INT_MASK_REG GLBL_OR_EVENT_INT_MASK; // Global OR Event Interrupt Mask Register }; struct HWBP_CLEAR_BITS { // bits description Uint16 EVENT_CLR:1; // 0 Event Clear register Uint16 rsvd1:15; // 15:1 Reserved }; union HWBP_CLEAR_REG { Uint16 all; struct HWBP_CLEAR_BITS bit; }; struct HWBP_CNTL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 BUS_SEL:4; // 4:1 Bus select bits Uint16 STOP:1; // 5 Stop bit (Halt/No Halt of CPU) Uint16 RTOSINT:1; // 6 RTOSINT bit Uint16 COMP_MODE:3; // 9:7 Compare mode Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:4; // 15:12 Reserved }; union HWBP_CNTL_REG { Uint16 all; struct HWBP_CNTL_BITS bit; }; struct HWBP_STATUS_BITS { // bits description Uint16 EVENT_FIRED:1; // 0 HWBP Event Fired bits Uint16 rsvd1:7; // 7:1 Reserved Uint16 MODULE_ID:6; // 13:8 Identification bits Uint16 STATUS:2; // 15:14 Status bits }; union HWBP_STATUS_REG { Uint16 all; struct HWBP_STATUS_BITS bit; }; struct ERAD_HWBP_REGS { Uint32 HWBP_MASK; // HWBP Mask Register Uint32 HWBP_REF; // HWBP Reference Register union HWBP_CLEAR_REG HWBP_CLEAR; // HWBP Clear Register Uint16 rsvd1; // Reserved union HWBP_CNTL_REG HWBP_CNTL; // HWBP Control Register union HWBP_STATUS_REG HWBP_STATUS; // HWBP Status Register }; struct CTM_CNTL_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 START_STOP_MODE:1; // 2 Start_stop mode bit Uint16 EVENT_MODE:1; // 3 Event mode bit Uint16 RST_ON_MATCH:1; // 4 Reset_on_match bit Uint16 rsvd2:1; // 5 Reserved Uint16 STOP:1; // 6 Stop bit (Halt/No Halt of CPU) Uint16 RTOSINT:1; // 7 RTOSINT bit Uint16 START_STOP_CUMULATIVE:1; // 8 Start stop cumulative bit Uint16 rsvd3:1; // 9 Reserved Uint16 RST_EN:1; // 10 Enable Reset Uint16 CNT_INP_SEL_EN:1; // 11 Counter Input Select Enable Uint16 rsvd4:4; // 15:12 Reserved }; union CTM_CNTL_REG { Uint16 all; struct CTM_CNTL_BITS bit; }; struct CTM_STATUS_BITS { // bits description Uint16 EVENT_FIRED:1; // 0 Counter Event Fired bits Uint16 OVERFLOW:1; // 1 Counter Overflowed Uint16 MODULE_ID:10; // 11:2 Identification bits Uint16 STATUS:4; // 15:12 Status bits }; union CTM_STATUS_REG { Uint16 all; struct CTM_STATUS_BITS bit; }; struct CTM_INPUT_SEL_BITS { // bits description Uint16 CNT_INP_SEL:7; // 6:0 Counter Input Select Uint16 rsvd1:1; // 7 Reserved Uint16 STA_INP_SEL:7; // 14:8 Counter Sart Input Select Uint16 rsvd2:1; // 15 Reserved }; union CTM_INPUT_SEL_REG { Uint16 all; struct CTM_INPUT_SEL_BITS bit; }; struct CTM_CLEAR_BITS { // bits description Uint16 EVENT_CLEAR:1; // 0 Clear EVENT_FIRED Uint16 OVERFLOW_CLEAR:1; // 1 Clear OVERFLOW Uint16 rsvd1:14; // 15:2 Reserved }; union CTM_CLEAR_REG { Uint16 all; struct CTM_CLEAR_BITS bit; }; struct CTM_INPUT_SEL_2_BITS { // bits description Uint16 STO_INP_SEL:7; // 6:0 Counter Stop Input Select Uint16 rsvd1:1; // 7 Reserved Uint16 RST_INP_SEL:7; // 14:8 Counter Reset input Select Uint16 rsvd2:1; // 15 Reserved }; union CTM_INPUT_SEL_2_REG { Uint16 all; struct CTM_INPUT_SEL_2_BITS bit; }; struct CTM_INPUT_COND_BITS { // bits description Uint16 CTM_INP_INV:1; // 0 Counter Input Invert Uint16 CTM_INP_SYNCH:1; // 1 Counter input synchronizer enable Uint16 rsvd1:2; // 3:2 Reserved Uint16 STA_INP_INV:1; // 4 Start input Invert Uint16 STA_INP_SYNCH:1; // 5 Start input synchronizer enable Uint16 rsvd2:2; // 7:6 Reserved Uint16 STO_INP_INV:1; // 8 Stop input Invert Uint16 STO_INP_SYNCH:1; // 9 Stop input synchronizer enable Uint16 rsvd3:2; // 11:10 Reserved Uint16 RST_INP_INV:1; // 12 Reset input Invert Uint16 RST_INP_SYNCH:1; // 13 Reset input synchronizer enable Uint16 rsvd4:2; // 15:14 Reserved }; union CTM_INPUT_COND_REG { Uint16 all; struct CTM_INPUT_COND_BITS bit; }; struct ERAD_COUNTER_REGS { union CTM_CNTL_REG CTM_CNTL; // Counter Control Register union CTM_STATUS_REG CTM_STATUS; // Counter Status Register Uint32 CTM_REF; // Counter Reference Register Uint32 CTM_COUNT; // Counter Current Value Register Uint32 CTM_MAX_COUNT; // Counter Max Count Value Register union CTM_INPUT_SEL_REG CTM_INPUT_SEL; // Counter Input Select Register union CTM_CLEAR_REG CTM_CLEAR; // Counter Clear Register union CTM_INPUT_SEL_2_REG CTM_INPUT_SEL_2; // Counter Input Select Extension Register union CTM_INPUT_COND_REG CTM_INPUT_COND; // Counter Input Conditioning Register }; struct CRC_GLOBAL_CTRL_BITS { // bits description Uint16 CRC1_INIT:1; // 0 Initialize CRC Module 1 Uint16 CRC2_INIT:1; // 1 Initialize CRC Module 2 Uint16 CRC3_INIT:1; // 2 Initialize CRC Module 3 Uint16 CRC4_INIT:1; // 3 Initialize CRC Module 4 Uint16 CRC5_INIT:1; // 4 Initialize CRC Module 5 Uint16 CRC6_INIT:1; // 5 Initialize CRC Module 6 Uint16 CRC7_INIT:1; // 6 Initialize CRC Module 7 Uint16 CRC8_INIT:1; // 7 Initialize CRC Module 8 Uint16 CRC1_EN:1; // 8 Enable CRC Module 1 Uint16 CRC2_EN:1; // 9 Enable CRC Module 2 Uint16 CRC3_EN:1; // 10 Enable CRC Module 3 Uint16 CRC4_EN:1; // 11 Enable CRC Module 4 Uint16 CRC5_EN:1; // 12 Enable CRC Module 5 Uint16 CRC6_EN:1; // 13 Enable CRC Module 6 Uint16 CRC7_EN:1; // 14 Enable CRC Module 7 Uint16 CRC8_EN:1; // 15 Enable CRC Module 8 }; union CRC_GLOBAL_CTRL_REG { Uint16 all; struct CRC_GLOBAL_CTRL_BITS bit; }; struct ERAD_CRC_GLOBAL_REGS{ union CRC_GLOBAL_CTRL_REG CRC_GLOBAL_CTRL; // CRC_GLOBAL_CRTL }; struct CRC_QUALIFIER_BITS { // bits description Uint16 CRC_QUALIFIER:5; // 4:0 CRC Qualifier Register Uint16 rsvd1:11; // 15:5 Reserved }; union CRC_QUALIFIER_REG { Uint16 all; struct CRC_QUALIFIER_BITS bit; }; struct ERAD_CRC_REGS { Uint32 CRC_CURRENT; // CRC_CURRENT Uint32 CRC_SEED; // CRC_SEED union CRC_QUALIFIER_REG CRC_QUALIFIER; // CRC_QUALIFIER }; //--------------------------------------------------------------------------- // ERAD External References & Function Declarations: // extern volatile struct ERAD_GLOBAL_REGS EradGlobalRegs; extern volatile struct ERAD_HWBP_REGS EradHWBP1Regs; extern volatile struct ERAD_HWBP_REGS EradHWBP2Regs; extern volatile struct ERAD_HWBP_REGS EradHWBP3Regs; extern volatile struct ERAD_HWBP_REGS EradHWBP4Regs; extern volatile struct ERAD_HWBP_REGS EradHWBP5Regs; extern volatile struct ERAD_HWBP_REGS EradHWBP6Regs; extern volatile struct ERAD_HWBP_REGS EradHWBP7Regs; extern volatile struct ERAD_HWBP_REGS EradHWBP8Regs; extern volatile struct ERAD_COUNTER_REGS EradCounter1Regs; extern volatile struct ERAD_COUNTER_REGS EradCounter2Regs; extern volatile struct ERAD_COUNTER_REGS EradCounter3Regs; extern volatile struct ERAD_COUNTER_REGS EradCounter4Regs; extern volatile struct ERAD_CRC_GLOBAL_REGS EradCRCGlobalRegs; extern volatile struct ERAD_CRC_REGS EradCRC1Regs; extern volatile struct ERAD_CRC_REGS EradCRC2Regs; extern volatile struct ERAD_CRC_REGS EradCRC3Regs; extern volatile struct ERAD_CRC_REGS EradCRC4Regs; extern volatile struct ERAD_CRC_REGS EradCRC5Regs; extern volatile struct ERAD_CRC_REGS EradCRC6Regs; extern volatile struct ERAD_CRC_REGS EradCRC7Regs; extern volatile struct ERAD_CRC_REGS EradCRC8Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_flash.h // // TITLE: Definitions for the FLASH registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // FLASH Individual Register Bit Definitions: struct FRDCNTL_BITS { // bits description Uint16 rsvd1:8; // 7:0 Reserved Uint16 RWAIT:4; // 11:8 Random Read Waitstate Uint16 rsvd2:4; // 15:12 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union FRDCNTL_REG { Uint32 all; struct FRDCNTL_BITS bit; }; struct FBAC_BITS { // bits description Uint16 rsvd1:8; // 7:0 Reserved Uint16 BAGP:8; // 15:8 Bank Active Grace Period Uint16 rsvd2:16; // 31:16 Reserved }; union FBAC_REG { Uint32 all; struct FBAC_BITS bit; }; struct FBFALLBACK_BITS { // bits description Uint16 BNKPWR0:2; // 1:0 Bank Power Mode of BANK0 Uint16 rsvd1:2; // 3:2 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union FBFALLBACK_REG { Uint32 all; struct FBFALLBACK_BITS bit; }; struct FBPRDY_BITS { // bits description Uint16 BANKRDY:1; // 0 Flash Bank Active Power State Uint16 rsvd1:14; // 14:1 Reserved Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode Uint16 rsvd2:16; // 31:16 Reserved }; union FBPRDY_REG { Uint32 all; struct FBPRDY_BITS bit; }; struct FPAC1_BITS { // bits description Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode Uint16 rsvd1:15; // 15:1 Reserved Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count Uint16 rsvd2:4; // 31:28 Reserved }; union FPAC1_REG { Uint32 all; struct FPAC1_BITS bit; }; struct FMSTAT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 VOLTSTAT:1; // 3 Core Voltage Status. Uint16 CSTAT:1; // 4 Command Status. Uint16 INVDAT:1; // 5 Invalid Data. Uint16 PGM:1; // 6 Program Active. Uint16 ERS:1; // 7 Erase Active. Uint16 Busy:1; // 8 Busy Bit. Uint16 rsvd4:1; // 9 Reserved Uint16 EV:1; // 10 Erase verify Uint16 rsvd5:1; // 11 Reserved Uint16 PGV:1; // 12 Program verify Uint16 rsvd6:1; // 13 Reserved Uint16 ILA:1; // 14 Illegal Address Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:14; // 31:18 Reserved }; union FMSTAT_REG { Uint32 all; struct FMSTAT_BITS bit; }; struct FRD_INTF_CTRL_BITS { // bits description Uint16 PREFETCH_EN:1; // 0 Prefetch Enable Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FRD_INTF_CTRL_REG { Uint32 all; struct FRD_INTF_CTRL_BITS bit; }; struct FLASH_CTRL_REGS { union FRDCNTL_REG FRDCNTL; // Flash Read Control Register Uint16 rsvd1[28]; // Reserved union FBAC_REG FBAC; // Flash Bank Access Control Register union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 Uint16 rsvd2[4]; // Reserved union FMSTAT_REG FMSTAT; // Flash Module Status Register Uint16 rsvd3[340]; // Reserved union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register }; struct ECC_ENABLE_BITS { // bits description Uint16 ENABLE:4; // 3:0 Enable ECC Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECC_ENABLE_REG { Uint32 all; struct ECC_ENABLE_BITS bit; }; struct ERR_STATUS_BITS { // bits description Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred Uint16 rsvd1:13; // 15:3 Reserved Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred Uint16 rsvd2:13; // 31:19 Reserved }; union ERR_STATUS_REG { Uint32 all; struct ERR_STATUS_BITS bit; }; struct ERR_POS_BITS { // bits description Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits Uint16 rsvd1:2; // 7:6 Reserved Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits Uint16 rsvd2:7; // 15:9 Reserved Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits Uint16 rsvd3:2; // 23:22 Reserved Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits Uint16 rsvd4:7; // 31:25 Reserved }; union ERR_POS_REG { Uint32 all; struct ERR_POS_BITS bit; }; struct ERR_STATUS_CLR_BITS { // bits description Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear Uint16 rsvd1:13; // 15:3 Reserved Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear Uint16 rsvd2:13; // 31:19 Reserved }; union ERR_STATUS_CLR_REG { Uint32 all; struct ERR_STATUS_CLR_BITS bit; }; struct ERR_CNT_BITS { // bits description Uint16 ERR_CNT:16; // 15:0 Error counter Uint16 rsvd1:16; // 31:16 Reserved }; union ERR_CNT_REG { Uint32 all; struct ERR_CNT_BITS bit; }; struct ERR_THRESHOLD_BITS { // bits description Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold Uint16 rsvd1:16; // 31:16 Reserved }; union ERR_THRESHOLD_REG { Uint32 all; struct ERR_THRESHOLD_BITS bit; }; struct ERR_INTFLG_BITS { // bits description Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ERR_INTFLG_REG { Uint32 all; struct ERR_INTFLG_BITS bit; }; struct ERR_INTCLR_BITS { // bits description Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ERR_INTCLR_REG { Uint32 all; struct ERR_INTCLR_BITS bit; }; struct FADDR_TEST_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 ADDRL:13; // 15:3 ECC Address Low Uint16 ADDRH:6; // 21:16 ECC Address High Uint16 rsvd2:10; // 31:22 Reserved }; union FADDR_TEST_REG { Uint32 all; struct FADDR_TEST_BITS bit; }; struct FECC_TEST_BITS { // bits description Uint16 ECC:8; // 7:0 ECC Control Bits Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_TEST_REG { Uint32 all; struct FECC_TEST_BITS bit; }; struct FECC_CTRL_BITS { // bits description Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic Uint16 ECC_SELECT:1; // 1 ECC Bit Select Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_CTRL_REG { Uint32 all; struct FECC_CTRL_BITS bit; }; struct FECC_STATUS_BITS { // bits description Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error Uint16 rsvd1:7; // 15:9 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FECC_STATUS_REG { Uint32 all; struct FECC_STATUS_BITS bit; }; struct FLASH_ECC_REGS { union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High union ERR_STATUS_REG ERR_STATUS; // Error Status union ERR_POS_REG ERR_POS; // Error Position union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear union ERR_CNT_REG ERR_CNT; // Error Control union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear Uint32 FDATAH_TEST; // Data High Test Uint32 FDATAL_TEST; // Data Low Test union FADDR_TEST_REG FADDR_TEST; // ECC Test Address union FECC_TEST_REG FECC_TEST; // ECC Test Address union FECC_CTRL_REG FECC_CTRL; // ECC Control Uint32 FOUTH_TEST; // Test Data Out High Uint32 FOUTL_TEST; // Test Data Out Low union FECC_STATUS_REG FECC_STATUS; // ECC Status }; //--------------------------------------------------------------------------- // FLASH External References & Function Declarations: // extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; extern volatile struct FLASH_ECC_REGS Flash0EccRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_fsi.h // // TITLE: Definitions for the FSI registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // FSI Individual Register Bit Definitions: struct TX_MASTER_CTRL_BITS { // bits description Uint16 CORE_RST:1; // 0 Transmitter Master Core Reset Uint16 FLUSH:1; // 1 Flush Operation Start Uint16 rsvd1:6; // 7:2 Reserved Uint16 KEY:8; // 15:8 Write Key }; union TX_MASTER_CTRL_REG { Uint16 all; struct TX_MASTER_CTRL_BITS bit; }; struct TX_CLK_CTRL_BITS { // bits description Uint16 CLK_RST:1; // 0 Soft Reset for the Clock Divider Uint16 CLK_EN:1; // 1 Clock Divider Enable Uint16 PRESCALE_VAL:8; // 9:2 Prescale value Uint16 rsvd1:6; // 15:10 Reserved }; union TX_CLK_CTRL_REG { Uint16 all; struct TX_CLK_CTRL_BITS bit; }; struct TX_OPER_CTRL_LO_BITS { // bits description Uint16 DATA_WIDTH:2; // 1:0 Transmit Data width Uint16 SPI_MODE:1; // 2 SPI Mode Select Uint16 START_MODE:3; // 5:3 Transmission Start Mode Select Uint16 SW_CRC:1; // 6 CRC Source Select Uint16 PING_TO_MODE:1; // 7 Ping Counter Reset Mode Select Uint16 SEL_PLLCLK:1; // 8 Input Clock Select Uint16 TDM_ENABLE:1; // 9 Transmit TDM Mode Enable Uint16 rsvd1:6; // 15:10 Reserved }; union TX_OPER_CTRL_LO_REG { Uint16 all; struct TX_OPER_CTRL_LO_BITS bit; }; struct TX_OPER_CTRL_HI_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 FORCE_ERR:1; // 5 Error Frame Force Uint16 ECC_SEL:1; // 6 ECC Data Width Select Uint16 EXT_TRIG_SEL:6; // 12:7 External Trigger Select Uint16 rsvd2:3; // 15:13 Reserved }; union TX_OPER_CTRL_HI_REG { Uint16 all; struct TX_OPER_CTRL_HI_BITS bit; }; struct TX_FRAME_CTRL_BITS { // bits description Uint16 FRAME_TYPE:4; // 3:0 Transmit Frame Type Uint16 N_WORDS:4; // 7:4 Number of Words to be Transmitted Uint16 rsvd1:7; // 14:8 Reserved Uint16 START:1; // 15 Start Transmission }; union TX_FRAME_CTRL_REG { Uint16 all; struct TX_FRAME_CTRL_BITS bit; }; struct TX_FRAME_TAG_UDATA_BITS { // bits description Uint16 FRAME_TAG:4; // 3:0 Frame Tag Uint16 rsvd1:4; // 7:4 Reserved Uint16 USER_DATA:8; // 15:8 User Data }; union TX_FRAME_TAG_UDATA_REG { Uint16 all; struct TX_FRAME_TAG_UDATA_BITS bit; }; struct TX_BUF_PTR_LOAD_BITS { // bits description Uint16 BUF_PTR_LOAD:4; // 3:0 Buffer Pointer Force Load Uint16 rsvd1:12; // 15:4 Reserved }; union TX_BUF_PTR_LOAD_REG { Uint16 all; struct TX_BUF_PTR_LOAD_BITS bit; }; struct TX_BUF_PTR_STS_BITS { // bits description Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index Uint16 rsvd1:4; // 7:4 Reserved Uint16 CURR_WORD_CNT:5; // 12:8 Remaining Words in Buffer Uint16 rsvd2:3; // 15:13 Reserved }; union TX_BUF_PTR_STS_REG { Uint16 all; struct TX_BUF_PTR_STS_BITS bit; }; struct TX_PING_CTRL_BITS { // bits description Uint16 CNT_RST:1; // 0 Ping Counter Reset Uint16 TIMER_EN:1; // 1 Ping Counter Enable Uint16 EXT_TRIG_EN:1; // 2 External Trigger Enable Uint16 EXT_TRIG_SEL:6; // 8:3 External Trigger Select Uint16 rsvd1:7; // 15:9 Reserved }; union TX_PING_CTRL_REG { Uint16 all; struct TX_PING_CTRL_BITS bit; }; struct TX_PING_TAG_BITS { // bits description Uint16 TAG:4; // 3:0 Ping Frame Tag Uint16 rsvd1:12; // 15:4 Reserved }; union TX_PING_TAG_REG { Uint16 all; struct TX_PING_TAG_BITS bit; }; struct TX_INT_CTRL_BITS { // bits description Uint16 INT1_EN_FRAME_DONE:1; // 0 Enable Frame Done Interrupt to INT1 Uint16 INT1_EN_BUF_UNDERRUN:1; // 1 Enable Buffer Underrun Interrupt to INT1 Uint16 INT1_EN_BUF_OVERRUN:1; // 2 Enable Buffer Overrun Interrupt to INT1 Uint16 INT1_EN_PING_TO:1; // 3 Enable Ping Timer Interrupt to INT1 Uint16 rsvd1:4; // 7:4 Reserved Uint16 INT2_EN_FRAME_DONE:1; // 8 Enable Frame Done Interrupt to INT2 Uint16 INT2_EN_BUF_UNDERRUN:1; // 9 Enable Buffer Underrun Interrupt to INT2 Uint16 INT2_EN_BUF_OVERRUN:1; // 10 Enable Buffer Overrun Interrupt to INT2 Uint16 INT2_EN_PING_TO:1; // 11 Enable Ping Timer Interrupt to INT2 Uint16 rsvd2:4; // 15:12 Reserved }; union TX_INT_CTRL_REG { Uint16 all; struct TX_INT_CTRL_BITS bit; }; struct TX_DMA_CTRL_BITS { // bits description Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable Uint16 rsvd1:15; // 15:1 Reserved }; union TX_DMA_CTRL_REG { Uint16 all; struct TX_DMA_CTRL_BITS bit; }; struct TX_LOCK_CTRL_BITS { // bits description Uint16 LOCK:1; // 0 Control Register Lock Enable Uint16 rsvd1:7; // 7:1 Reserved Uint16 KEY:8; // 15:8 Write Key }; union TX_LOCK_CTRL_REG { Uint16 all; struct TX_LOCK_CTRL_BITS bit; }; struct TX_EVT_STS_BITS { // bits description Uint16 FRAME_DONE:1; // 0 Frame Done Flag Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Uint16 rsvd1:12; // 15:4 Reserved }; union TX_EVT_STS_REG { Uint16 all; struct TX_EVT_STS_BITS bit; }; struct TX_EVT_CLR_BITS { // bits description Uint16 FRAME_DONE:1; // 0 Frame Done Flag Clear Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Clear Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Clear Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Clear Uint16 rsvd1:12; // 15:4 Reserved }; union TX_EVT_CLR_REG { Uint16 all; struct TX_EVT_CLR_BITS bit; }; struct TX_EVT_FRC_BITS { // bits description Uint16 FRAME_DONE:1; // 0 Frame Done Flag Force Uint16 BUF_UNDERRUN:1; // 1 Buffer Underrun Flag Force Uint16 BUF_OVERRUN:1; // 2 Buffer Overrun Flag Force Uint16 PING_TRIGGERED:1; // 3 Ping Frame Triggered Flag Force Uint16 rsvd1:12; // 15:4 Reserved }; union TX_EVT_FRC_REG { Uint16 all; struct TX_EVT_FRC_BITS bit; }; struct TX_USER_CRC_BITS { // bits description Uint16 USER_CRC:8; // 7:0 User-defined CRC Uint16 rsvd1:8; // 15:8 Reserved }; union TX_USER_CRC_REG { Uint16 all; struct TX_USER_CRC_BITS bit; }; struct TX_ECC_DATA_BITS { // bits description Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits }; union TX_ECC_DATA_REG { Uint32 all; struct TX_ECC_DATA_BITS bit; }; struct TX_ECC_VAL_BITS { // bits description Uint16 ECC_VAL:7; // 6:0 Computed ECC Value Uint16 rsvd1:9; // 15:7 Reserved }; union TX_ECC_VAL_REG { Uint16 all; struct TX_ECC_VAL_BITS bit; }; struct FSI_TX_REGS { union TX_MASTER_CTRL_REG TX_MASTER_CTRL; // Transmit master control register Uint16 rsvd1; // Reserved union TX_CLK_CTRL_REG TX_CLK_CTRL; // Transmit clock control register Uint16 rsvd2; // Reserved union TX_OPER_CTRL_LO_REG TX_OPER_CTRL_LO; // Transmit operation control register low union TX_OPER_CTRL_HI_REG TX_OPER_CTRL_HI; // Transmit operation control register high union TX_FRAME_CTRL_REG TX_FRAME_CTRL; // Transmit frame control register union TX_FRAME_TAG_UDATA_REG TX_FRAME_TAG_UDATA; // Transmit frame tag and user data register union TX_BUF_PTR_LOAD_REG TX_BUF_PTR_LOAD; // Transmit buffer pointer control load register union TX_BUF_PTR_STS_REG TX_BUF_PTR_STS; // Transmit buffer pointer control status register union TX_PING_CTRL_REG TX_PING_CTRL; // Transmit ping control register union TX_PING_TAG_REG TX_PING_TAG; // Transmit ping tag register Uint32 TX_PING_TO_REF; // Transmit ping timeout counter reference Uint32 TX_PING_TO_CNT; // Transmit ping timeout current count union TX_INT_CTRL_REG TX_INT_CTRL; // Transmit interrupt event control register union TX_DMA_CTRL_REG TX_DMA_CTRL; // Transmit DMA event control register union TX_LOCK_CTRL_REG TX_LOCK_CTRL; // Transmit lock control register Uint16 rsvd3; // Reserved union TX_EVT_STS_REG TX_EVT_STS; // Transmit event and error status flag register Uint16 rsvd4; // Reserved union TX_EVT_CLR_REG TX_EVT_CLR; // Transmit event and error clear register union TX_EVT_FRC_REG TX_EVT_FRC; // Transmit event and error flag force register union TX_USER_CRC_REG TX_USER_CRC; // Transmit user-defined CRC register Uint16 rsvd5[7]; // Reserved union TX_ECC_DATA_REG TX_ECC_DATA; // Transmit ECC data register union TX_ECC_VAL_REG TX_ECC_VAL; // Transmit ECC value register Uint16 rsvd6[29]; // Reserved Uint16 TX_BUF_BASE; // Base address for transmit buffer }; struct RX_MASTER_CTRL_BITS { // bits description Uint16 CORE_RST:1; // 0 Receiver Master Core Reset Uint16 INT_LOOPBACK:1; // 1 Internal Loopback Enable Uint16 SPI_PAIRING:1; // 2 Clock Pairing for SPI-like Behaviour Uint16 rsvd1:5; // 7:3 Reserved Uint16 KEY:8; // 15:8 Write Key }; union RX_MASTER_CTRL_REG { Uint16 all; struct RX_MASTER_CTRL_BITS bit; }; struct RX_OPER_CTRL_BITS { // bits description Uint16 DATA_WIDTH:2; // 1:0 Receive Data Width Select Uint16 SPI_MODE:1; // 2 SPI Mode Enable Uint16 N_WORDS:4; // 6:3 Number of Words to be Received Uint16 ECC_SEL:1; // 7 ECC Data Width Select Uint16 PING_WD_RST_MODE:1; // 8 Ping Watchdog Timeout Mode Select Uint16 rsvd1:7; // 15:9 Reserved }; union RX_OPER_CTRL_REG { Uint16 all; struct RX_OPER_CTRL_BITS bit; }; struct RX_FRAME_INFO_BITS { // bits description Uint16 FRAME_TYPE:4; // 3:0 Received Frame Type Uint16 rsvd1:12; // 15:4 Reserved }; union RX_FRAME_INFO_REG { Uint16 all; struct RX_FRAME_INFO_BITS bit; }; struct RX_FRAME_TAG_UDATA_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 FRAME_TAG:4; // 4:1 Received Frame Tag Uint16 rsvd2:3; // 7:5 Reserved Uint16 USER_DATA:8; // 15:8 Received User Data }; union RX_FRAME_TAG_UDATA_REG { Uint16 all; struct RX_FRAME_TAG_UDATA_BITS bit; }; struct RX_DMA_CTRL_BITS { // bits description Uint16 DMA_EVT_EN:1; // 0 DMA Event Enable Uint16 rsvd1:15; // 15:1 Reserved }; union RX_DMA_CTRL_REG { Uint16 all; struct RX_DMA_CTRL_BITS bit; }; struct RX_EVT_STS_BITS { // bits description Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag. Uint16 CRC_ERR:1; // 2 CRC Error Flag Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Uint16 FRAME_DONE:1; // 6 Frame Done Flag Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Uint16 PING_TAG_MATCH:1; // 12 Ping Tag Match Flag Uint16 DATA_TAG_MATCH:1; // 13 Data Tag Match Flag Uint16 ERROR_TAG_MATCH:1; // 14 Error Tag Match Flag Uint16 rsvd1:1; // 15 Reserved }; union RX_EVT_STS_REG { Uint16 all; struct RX_EVT_STS_BITS bit; }; struct RX_CRC_INFO_BITS { // bits description Uint16 RX_CRC:8; // 7:0 Received CRC Value Uint16 CALC_CRC:8; // 15:8 Hardware Calculated CRC }; union RX_CRC_INFO_REG { Uint16 all; struct RX_CRC_INFO_BITS bit; }; struct RX_EVT_CLR_BITS { // bits description Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Clear Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Clear Uint16 CRC_ERR:1; // 2 CRC Error Flag Clear Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Clear Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Clear Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Clear Uint16 FRAME_DONE:1; // 6 Frame Done Flag Clear Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Clear Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Clear Uint16 PING_FRAME:1; // 9 PING Frame Received Flag Clear Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Clear Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Clear Uint16 PING_TAG_MATCH:1; // 12 Ping Tag Match Flag Clear Uint16 DATA_TAG_MATCH:1; // 13 Data Tag Match Flag Clear Uint16 ERROR_TAG_MATCH:1; // 14 Error Tag Match Flag Clear Uint16 rsvd1:1; // 15 Reserved }; union RX_EVT_CLR_REG { Uint16 all; struct RX_EVT_CLR_BITS bit; }; struct RX_EVT_FRC_BITS { // bits description Uint16 PING_WD_TO:1; // 0 Ping Watchdog Timeout Flag Force Uint16 FRAME_WD_TO:1; // 1 Frame Watchdog Timeout Flag Force Uint16 CRC_ERR:1; // 2 CRC Error Flag Force Uint16 TYPE_ERR:1; // 3 Frame Type Error Flag Force Uint16 EOF_ERR:1; // 4 End-of-Frame Error Flag Force Uint16 BUF_OVERRUN:1; // 5 Receive Buffer Overrun Flag Force Uint16 FRAME_DONE:1; // 6 Frame Done Flag Force Uint16 BUF_UNDERRUN:1; // 7 Receive Buffer Underrun Flag Force Uint16 ERR_FRAME:1; // 8 Error Frame Received Flag Force Uint16 PING_FRAME:1; // 9 Ping Frame Received Flag Force Uint16 FRAME_OVERRUN:1; // 10 Frame Overrun Flag Force Uint16 DATA_FRAME:1; // 11 Data Frame Received Flag Force Uint16 PING_TAG_MATCH:1; // 12 Ping Tag Match Flag Force Uint16 DATA_TAG_MATCH:1; // 13 Data Tag Match Flag Force Uint16 ERROR_TAG_MATCH:1; // 14 Error Tag Match Flag Force Uint16 rsvd1:1; // 15 Reserved }; union RX_EVT_FRC_REG { Uint16 all; struct RX_EVT_FRC_BITS bit; }; struct RX_BUF_PTR_LOAD_BITS { // bits description Uint16 BUF_PTR_LOAD:4; // 3:0 Load value for receive buffer pointer Uint16 rsvd1:12; // 15:4 Reserved }; union RX_BUF_PTR_LOAD_REG { Uint16 all; struct RX_BUF_PTR_LOAD_BITS bit; }; struct RX_BUF_PTR_STS_BITS { // bits description Uint16 CURR_BUF_PTR:4; // 3:0 Current Buffer Pointer Index Uint16 rsvd1:4; // 7:4 Reserved Uint16 CURR_WORD_CNT:5; // 12:8 Available Words in Buffer Uint16 rsvd2:3; // 15:13 Reserved }; union RX_BUF_PTR_STS_REG { Uint16 all; struct RX_BUF_PTR_STS_BITS bit; }; struct RX_FRAME_WD_CTRL_BITS { // bits description Uint16 FRAME_WD_CNT_RST:1; // 0 Frame Watchdog Counter Reset Uint16 FRAME_WD_EN:1; // 1 Frame Watchdog Counter Enable Uint16 rsvd1:14; // 15:2 Reserved }; union RX_FRAME_WD_CTRL_REG { Uint16 all; struct RX_FRAME_WD_CTRL_BITS bit; }; struct RX_PING_WD_CTRL_BITS { // bits description Uint16 PING_WD_RST:1; // 0 Ping Watchdog Counter Reset Uint16 PING_WD_EN:1; // 1 Ping Watchdog Counter Enable Uint16 rsvd1:14; // 15:2 Reserved }; union RX_PING_WD_CTRL_REG { Uint16 all; struct RX_PING_WD_CTRL_BITS bit; }; struct RX_PING_TAG_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 PING_TAG:4; // 4:1 Ping Frame Tag Uint16 rsvd2:11; // 15:5 Reserved }; union RX_PING_TAG_REG { Uint16 all; struct RX_PING_TAG_BITS bit; }; struct RX_INT1_CTRL_BITS { // bits description Uint16 INT1_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT1 Uint16 INT1_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT1 Uint16 INT1_EN_CRC_ERR:1; // 2 Enable CRC Error Interrupt to INT1 Uint16 INT1_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT1 Uint16 INT1_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT1 Uint16 INT1_EN_OVERRUN:1; // 5 Enable Receive Buffer Overrun Interrupt to INT1 Uint16 INT1_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT1 Uint16 INT1_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT1 Uint16 INT1_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT1 Uint16 INT1_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT1 Uint16 INT1_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT1 Uint16 INT1_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT1 Uint16 INT1_EN_PING_TAG_MATCH:1; // 12 Enable Ping Frame Tag Matched Interrupt to INT1 Uint16 INT1_EN_DATA_TAG_MATCH:1; // 13 Enable Data Frame Tag Matched Interrupt to INT1 Uint16 INT1_EN_ERROR_TAG_MATCH:1; // 14 Enable Error Frame Tag Matched Interrupt to INT1 Uint16 rsvd1:1; // 15 Reserved }; union RX_INT1_CTRL_REG { Uint16 all; struct RX_INT1_CTRL_BITS bit; }; struct RX_INT2_CTRL_BITS { // bits description Uint16 INT2_EN_PING_WD_TO:1; // 0 Enable Ping Watchdog Timeout Interrupt to INT2 Uint16 INT2_EN_FRAME_WD_TO:1; // 1 Enable Frame Watchdog Timeout Interrupt to INT2 Uint16 INT2_EN_CRC_ERR:1; // 2 Enable CRC Errror Interrupt to INT2 Uint16 INT2_EN_TYPE_ERR:1; // 3 Enable Frame Type Error Interrupt to INT2 Uint16 INT2_EN_EOF_ERR:1; // 4 Enable End-of-Frame Error Interrupt to INT2 Uint16 INT2_EN_OVERRUN:1; // 5 Enable Buffer Overrun Interrupt to INT2 Uint16 INT2_EN_FRAME_DONE:1; // 6 Enable Frame Done Interrupt to INT2 Uint16 INT2_EN_UNDERRUN:1; // 7 Enable Buffer Underrun Interrupt to INT2 Uint16 INT2_EN_ERR_FRAME:1; // 8 Enable Error Frame Received Interrupt to INT2 Uint16 INT2_EN_PING_FRAME:1; // 9 Enable Ping Frame Received Interrupt to INT2 Uint16 INT2_EN_FRAME_OVERRUN:1; // 10 Enable Frame Overrun Interrupt to INT2 Uint16 INT2_EN_DATA_FRAME:1; // 11 Enable Data Frame Received Interrupt to INT2 Uint16 INT2_EN_PING_TAG_MATCH:1; // 12 Enable Ping Frame Tag Matched Interrupt to INT2 Uint16 INT2_EN_DATA_TAG_MATCH:1; // 13 Enable Data Frame Tag Matched Interrupt to INT2 Uint16 INT2_EN_ERROR_TAG_MATCH:1; // 14 Enable Error Frame Tag Matched Interrupt to INT2 Uint16 rsvd1:1; // 15 Reserved }; union RX_INT2_CTRL_REG { Uint16 all; struct RX_INT2_CTRL_BITS bit; }; struct RX_LOCK_CTRL_BITS { // bits description Uint16 LOCK:1; // 0 Control Register Lock Enable Uint16 rsvd1:7; // 7:1 Reserved Uint16 KEY:8; // 15:8 Write Key }; union RX_LOCK_CTRL_REG { Uint16 all; struct RX_LOCK_CTRL_BITS bit; }; struct RX_ECC_DATA_BITS { // bits description Uint16 DATA_LOW:16; // 15:0 ECC Data Lower 16 Bits Uint16 DATA_HIGH:16; // 31:16 ECC Data Upper 16 Bits }; union RX_ECC_DATA_REG { Uint32 all; struct RX_ECC_DATA_BITS bit; }; struct RX_ECC_VAL_BITS { // bits description Uint16 ECC_VAL:7; // 6:0 Computed ECC Value Uint16 rsvd1:9; // 15:7 Reserved }; union RX_ECC_VAL_REG { Uint16 all; struct RX_ECC_VAL_BITS bit; }; struct RX_ECC_LOG_BITS { // bits description Uint16 SBE:1; // 0 Single Bit Error Detected Uint16 MBE:1; // 1 Multiple Bit Errors Detected Uint16 rsvd1:14; // 15:2 Reserved }; union RX_ECC_LOG_REG { Uint16 all; struct RX_ECC_LOG_BITS bit; }; struct RX_FRAME_TAG_CMP_BITS { // bits description Uint16 TAG_REF:4; // 3:0 Frame Tag Reference Uint16 TAG_MASK:4; // 7:4 Frame Tag Mask Uint16 CMP_EN:1; // 8 Frame Tag Compare Enable Uint16 BROADCAST_EN:1; // 9 Broadcast Enable Uint16 rsvd1:6; // 15:10 Reserved }; union RX_FRAME_TAG_CMP_REG { Uint16 all; struct RX_FRAME_TAG_CMP_BITS bit; }; struct RX_PING_TAG_CMP_BITS { // bits description Uint16 TAG_REF:4; // 3:0 Ping Tag Reference Uint16 TAG_MASK:4; // 7:4 Ping Tag Mask Uint16 CMP_EN:1; // 8 Ping Tag Compare Enable Uint16 BROADCAST_EN:1; // 9 Broadcast Enable Uint16 rsvd1:6; // 15:10 Reserved }; union RX_PING_TAG_CMP_REG { Uint16 all; struct RX_PING_TAG_CMP_BITS bit; }; struct RX_DLYLINE_CTRL_BITS { // bits description Uint16 RXCLK_DLY:5; // 4:0 Delay Line Tap Select for RXCLK Uint16 RXD0_DLY:5; // 9:5 Delay Line Tap Select for RXD0 Uint16 RXD1_DLY:5; // 14:10 Delay Line Tap Select for RXD1 Uint16 rsvd1:1; // 15 Reserved }; union RX_DLYLINE_CTRL_REG { Uint16 all; struct RX_DLYLINE_CTRL_BITS bit; }; struct RX_VIS_1_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 RX_CORE_STS:1; // 3 Receiver Core Status Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union RX_VIS_1_REG { Uint32 all; struct RX_VIS_1_BITS bit; }; struct FSI_RX_REGS { union RX_MASTER_CTRL_REG RX_MASTER_CTRL; // Receive master control register Uint16 rsvd1[3]; // Reserved union RX_OPER_CTRL_REG RX_OPER_CTRL; // Receive operation control register Uint16 rsvd2; // Reserved union RX_FRAME_INFO_REG RX_FRAME_INFO; // Receive frame control register union RX_FRAME_TAG_UDATA_REG RX_FRAME_TAG_UDATA; // Receive frame tag and user data register union RX_DMA_CTRL_REG RX_DMA_CTRL; // Receive DMA event control register Uint16 rsvd3; // Reserved union RX_EVT_STS_REG RX_EVT_STS; // Receive event and error status flag register union RX_CRC_INFO_REG RX_CRC_INFO; // Receive CRC info of received and computed CRC union RX_EVT_CLR_REG RX_EVT_CLR; // Receive event and error clear register union RX_EVT_FRC_REG RX_EVT_FRC; // Receive event and error flag force register union RX_BUF_PTR_LOAD_REG RX_BUF_PTR_LOAD; // Receive buffer pointer load register union RX_BUF_PTR_STS_REG RX_BUF_PTR_STS; // Receive buffer pointer status register union RX_FRAME_WD_CTRL_REG RX_FRAME_WD_CTRL; // Receive frame watchdog control register Uint16 rsvd4; // Reserved Uint32 RX_FRAME_WD_REF; // Receive frame watchdog counter reference Uint32 RX_FRAME_WD_CNT; // Receive frame watchdog current count union RX_PING_WD_CTRL_REG RX_PING_WD_CTRL; // Receive ping watchdog control register union RX_PING_TAG_REG RX_PING_TAG; // Receive ping tag register Uint32 RX_PING_WD_REF; // Receive ping watchdog counter reference Uint32 RX_PING_WD_CNT; // Receive pingwatchdog current count union RX_INT1_CTRL_REG RX_INT1_CTRL; // Receive interrupt control register for RX_INT1 union RX_INT2_CTRL_REG RX_INT2_CTRL; // Receive interrupt control register for RX_INT2 union RX_LOCK_CTRL_REG RX_LOCK_CTRL; // Receive lock control register Uint16 rsvd5; // Reserved union RX_ECC_DATA_REG RX_ECC_DATA; // Receive ECC data register union RX_ECC_VAL_REG RX_ECC_VAL; // Receive ECC value register Uint16 rsvd6; // Reserved Uint32 RX_ECC_SEC_DATA; // Receive ECC corrected data register union RX_ECC_LOG_REG RX_ECC_LOG; // Receive ECC log and status register Uint16 rsvd7; // Reserved union RX_FRAME_TAG_CMP_REG RX_FRAME_TAG_CMP; // Receive frame tag compare register union RX_PING_TAG_CMP_REG RX_PING_TAG_CMP; // Receive ping tag compare register Uint16 rsvd8[6]; // Reserved union RX_DLYLINE_CTRL_REG RX_DLYLINE_CTRL; // Receive delay line control register Uint16 rsvd9[7]; // Reserved union RX_VIS_1_REG RX_VIS_1; // Receive debug visibility register 1 Uint16 rsvd10[6]; // Reserved Uint16 RX_BUF_BASE; // Base address for receive data buffer }; //--------------------------------------------------------------------------- // FSI External References & Function Declarations: // extern volatile struct FSI_TX_REGS FsiTxaRegs; extern volatile struct FSI_TX_REGS FsiTxbRegs; extern volatile struct FSI_RX_REGS FsiRxaRegs; extern volatile struct FSI_RX_REGS FsiRxbRegs; extern volatile struct FSI_RX_REGS FsiRxcRegs; extern volatile struct FSI_RX_REGS FsiRxdRegs; extern volatile struct FSI_RX_REGS FsiRxeRegs; extern volatile struct FSI_RX_REGS FsiRxfRegs; extern volatile struct FSI_RX_REGS FsiRxgRegs; extern volatile struct FSI_RX_REGS FsiRxhRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_gpio.h // // TITLE: Definitions for the GPIO registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // GPIO Individual Register Bit Definitions: struct GPACTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 }; union GPACTRL_REG { Uint32 all; struct GPACTRL_BITS bit; }; struct GPAQSEL1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 }; union GPAQSEL1_REG { Uint32 all; struct GPAQSEL1_BITS bit; }; struct GPAQSEL2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 }; union GPAQSEL2_REG { Uint32 all; struct GPAQSEL2_BITS bit; }; struct GPAMUX1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 }; union GPAMUX1_REG { Uint32 all; struct GPAMUX1_BITS bit; }; struct GPAMUX2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 }; union GPAMUX2_REG { Uint32 all; struct GPAMUX2_BITS bit; }; struct GPADIR_BITS { // bits description Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode }; union GPADIR_REG { Uint32 all; struct GPADIR_BITS bit; }; struct GPAPUD_BITS { // bits description Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin }; union GPAPUD_REG { Uint32 all; struct GPAPUD_BITS bit; }; struct GPAINV_BITS { // bits description Uint16 GPIO0:1; // 0 Input inversion control for this pin Uint16 GPIO1:1; // 1 Input inversion control for this pin Uint16 GPIO2:1; // 2 Input inversion control for this pin Uint16 GPIO3:1; // 3 Input inversion control for this pin Uint16 GPIO4:1; // 4 Input inversion control for this pin Uint16 GPIO5:1; // 5 Input inversion control for this pin Uint16 GPIO6:1; // 6 Input inversion control for this pin Uint16 GPIO7:1; // 7 Input inversion control for this pin Uint16 GPIO8:1; // 8 Input inversion control for this pin Uint16 GPIO9:1; // 9 Input inversion control for this pin Uint16 GPIO10:1; // 10 Input inversion control for this pin Uint16 GPIO11:1; // 11 Input inversion control for this pin Uint16 GPIO12:1; // 12 Input inversion control for this pin Uint16 GPIO13:1; // 13 Input inversion control for this pin Uint16 GPIO14:1; // 14 Input inversion control for this pin Uint16 GPIO15:1; // 15 Input inversion control for this pin Uint16 GPIO16:1; // 16 Input inversion control for this pin Uint16 GPIO17:1; // 17 Input inversion control for this pin Uint16 GPIO18:1; // 18 Input inversion control for this pin Uint16 GPIO19:1; // 19 Input inversion control for this pin Uint16 GPIO20:1; // 20 Input inversion control for this pin Uint16 GPIO21:1; // 21 Input inversion control for this pin Uint16 GPIO22:1; // 22 Input inversion control for this pin Uint16 GPIO23:1; // 23 Input inversion control for this pin Uint16 GPIO24:1; // 24 Input inversion control for this pin Uint16 GPIO25:1; // 25 Input inversion control for this pin Uint16 GPIO26:1; // 26 Input inversion control for this pin Uint16 GPIO27:1; // 27 Input inversion control for this pin Uint16 GPIO28:1; // 28 Input inversion control for this pin Uint16 GPIO29:1; // 29 Input inversion control for this pin Uint16 GPIO30:1; // 30 Input inversion control for this pin Uint16 GPIO31:1; // 31 Input inversion control for this pin }; union GPAINV_REG { Uint32 all; struct GPAINV_BITS bit; }; struct GPAODR_BITS { // bits description Uint16 GPIO0:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO1:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO2:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO3:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO4:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO5:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO6:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO7:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO8:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO9:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO10:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO11:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO12:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO13:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO14:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO15:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO16:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO17:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO18:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO19:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO20:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO21:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO22:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO23:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO24:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO25:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO26:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO27:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO28:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO29:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO30:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO31:1; // 31 Outpout Open-Drain control for this pin }; union GPAODR_REG { Uint32 all; struct GPAODR_BITS bit; }; struct GPAGMUX1_BITS { // bits description Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 }; union GPAGMUX1_REG { Uint32 all; struct GPAGMUX1_BITS bit; }; struct GPAGMUX2_BITS { // bits description Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 }; union GPAGMUX2_REG { Uint32 all; struct GPAGMUX2_BITS bit; }; struct GPACSEL1_BITS { // bits description Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select }; union GPACSEL1_REG { Uint32 all; struct GPACSEL1_BITS bit; }; struct GPACSEL2_BITS { // bits description Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select }; union GPACSEL2_REG { Uint32 all; struct GPACSEL2_BITS bit; }; struct GPACSEL3_BITS { // bits description Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select }; union GPACSEL3_REG { Uint32 all; struct GPACSEL3_BITS bit; }; struct GPACSEL4_BITS { // bits description Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select }; union GPACSEL4_REG { Uint32 all; struct GPACSEL4_BITS bit; }; struct GPALOCK_BITS { // bits description Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin }; union GPALOCK_REG { Uint32 all; struct GPALOCK_BITS bit; }; struct GPACR_BITS { // bits description Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin }; union GPACR_REG { Uint32 all; struct GPACR_BITS bit; }; struct GPBCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 }; union GPBCTRL_REG { Uint32 all; struct GPBCTRL_BITS bit; }; struct GPBQSEL1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 Uint16 GPIO36:2; // 9:8 Select input qualification type for GPIO36 Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 Uint16 GPIO38:2; // 13:12 Select input qualification type for GPIO38 Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 }; union GPBQSEL1_REG { Uint32 all; struct GPBQSEL1_BITS bit; }; struct GPBQSEL2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 Uint16 GPIO60:2; // 25:24 Select input qualification type for GPIO60 Uint16 GPIO61:2; // 27:26 Select input qualification type for GPIO61 Uint16 GPIO62:2; // 29:28 Select input qualification type for GPIO62 Uint16 GPIO63:2; // 31:30 Select input qualification type for GPIO63 }; union GPBQSEL2_REG { Uint32 all; struct GPBQSEL2_BITS bit; }; struct GPBMUX1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 }; union GPBMUX1_REG { Uint32 all; struct GPBMUX1_BITS bit; }; struct GPBMUX2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 }; union GPBMUX2_REG { Uint32 all; struct GPBMUX2_BITS bit; }; struct GPBDIR_BITS { // bits description Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO36:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO38:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO60:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO61:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO62:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO63:1; // 31 Defines direction for this pin in GPIO mode }; union GPBDIR_REG { Uint32 all; struct GPBDIR_BITS bit; }; struct GPBPUD_BITS { // bits description Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO36:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO38:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO60:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO61:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO62:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO63:1; // 31 Pull-Up Disable control for this pin }; union GPBPUD_REG { Uint32 all; struct GPBPUD_BITS bit; }; struct GPBINV_BITS { // bits description Uint16 GPIO32:1; // 0 Input inversion control for this pin Uint16 GPIO33:1; // 1 Input inversion control for this pin Uint16 GPIO34:1; // 2 Input inversion control for this pin Uint16 GPIO35:1; // 3 Input inversion control for this pin Uint16 GPIO36:1; // 4 Input inversion control for this pin Uint16 GPIO37:1; // 5 Input inversion control for this pin Uint16 GPIO38:1; // 6 Input inversion control for this pin Uint16 GPIO39:1; // 7 Input inversion control for this pin Uint16 GPIO40:1; // 8 Input inversion control for this pin Uint16 GPIO41:1; // 9 Input inversion control for this pin Uint16 GPIO42:1; // 10 Input inversion control for this pin Uint16 GPIO43:1; // 11 Input inversion control for this pin Uint16 GPIO44:1; // 12 Input inversion control for this pin Uint16 GPIO45:1; // 13 Input inversion control for this pin Uint16 GPIO46:1; // 14 Input inversion control for this pin Uint16 GPIO47:1; // 15 Input inversion control for this pin Uint16 GPIO48:1; // 16 Input inversion control for this pin Uint16 GPIO49:1; // 17 Input inversion control for this pin Uint16 GPIO50:1; // 18 Input inversion control for this pin Uint16 GPIO51:1; // 19 Input inversion control for this pin Uint16 GPIO52:1; // 20 Input inversion control for this pin Uint16 GPIO53:1; // 21 Input inversion control for this pin Uint16 GPIO54:1; // 22 Input inversion control for this pin Uint16 GPIO55:1; // 23 Input inversion control for this pin Uint16 GPIO56:1; // 24 Input inversion control for this pin Uint16 GPIO57:1; // 25 Input inversion control for this pin Uint16 GPIO58:1; // 26 Input inversion control for this pin Uint16 GPIO59:1; // 27 Input inversion control for this pin Uint16 GPIO60:1; // 28 Input inversion control for this pin Uint16 GPIO61:1; // 29 Input inversion control for this pin Uint16 GPIO62:1; // 30 Input inversion control for this pin Uint16 GPIO63:1; // 31 Input inversion control for this pin }; union GPBINV_REG { Uint32 all; struct GPBINV_BITS bit; }; struct GPBODR_BITS { // bits description Uint16 GPIO32:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO33:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO34:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO35:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO36:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO37:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO38:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO39:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO40:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO41:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO42:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO43:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO44:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO45:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO46:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO47:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO48:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO49:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO50:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO51:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO52:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO53:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO54:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO55:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO56:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO57:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO58:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO59:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO60:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO61:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO62:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO63:1; // 31 Outpout Open-Drain control for this pin }; union GPBODR_REG { Uint32 all; struct GPBODR_BITS bit; }; struct GPBAMSEL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 rsvd5:1; // 4 Reserved Uint16 rsvd6:1; // 5 Reserved Uint16 rsvd7:1; // 6 Reserved Uint16 rsvd8:1; // 7 Reserved Uint16 rsvd9:1; // 8 Reserved Uint16 rsvd10:1; // 9 Reserved Uint16 GPIO42:1; // 10 Analog Mode select for this pin Uint16 GPIO43:1; // 11 Analog Mode select for this pin Uint16 rsvd11:1; // 12 Reserved Uint16 rsvd12:1; // 13 Reserved Uint16 rsvd13:1; // 14 Reserved Uint16 rsvd14:1; // 15 Reserved Uint16 rsvd15:1; // 16 Reserved Uint16 rsvd16:1; // 17 Reserved Uint16 rsvd17:1; // 18 Reserved Uint16 rsvd18:1; // 19 Reserved Uint16 rsvd19:1; // 20 Reserved Uint16 rsvd20:1; // 21 Reserved Uint16 rsvd21:1; // 22 Reserved Uint16 rsvd22:1; // 23 Reserved Uint16 rsvd23:1; // 24 Reserved Uint16 rsvd24:1; // 25 Reserved Uint16 rsvd25:1; // 26 Reserved Uint16 rsvd26:1; // 27 Reserved Uint16 rsvd27:1; // 28 Reserved Uint16 rsvd28:1; // 29 Reserved Uint16 rsvd29:1; // 30 Reserved Uint16 rsvd30:1; // 31 Reserved }; union GPBAMSEL_REG { Uint32 all; struct GPBAMSEL_BITS bit; }; struct GPBGMUX1_BITS { // bits description Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 }; union GPBGMUX1_REG { Uint32 all; struct GPBGMUX1_BITS bit; }; struct GPBGMUX2_BITS { // bits description Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 }; union GPBGMUX2_REG { Uint32 all; struct GPBGMUX2_BITS bit; }; struct GPBCSEL1_BITS { // bits description Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select Uint16 GPIO36:4; // 19:16 GPIO36 Master CPU Select Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select Uint16 GPIO38:4; // 27:24 GPIO38 Master CPU Select Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select }; union GPBCSEL1_REG { Uint32 all; struct GPBCSEL1_BITS bit; }; struct GPBCSEL2_BITS { // bits description Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select }; union GPBCSEL2_REG { Uint32 all; struct GPBCSEL2_BITS bit; }; struct GPBCSEL3_BITS { // bits description Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select }; union GPBCSEL3_REG { Uint32 all; struct GPBCSEL3_BITS bit; }; struct GPBCSEL4_BITS { // bits description Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select Uint16 GPIO60:4; // 19:16 GPIO60 Master CPU Select Uint16 GPIO61:4; // 23:20 GPIO61 Master CPU Select Uint16 GPIO62:4; // 27:24 GPIO62 Master CPU Select Uint16 GPIO63:4; // 31:28 GPIO63 Master CPU Select }; union GPBCSEL4_REG { Uint32 all; struct GPBCSEL4_BITS bit; }; struct GPBLOCK_BITS { // bits description Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin Uint16 GPIO36:1; // 4 Configuration Lock bit for this pin Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin Uint16 GPIO38:1; // 6 Configuration Lock bit for this pin Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin Uint16 GPIO60:1; // 28 Configuration Lock bit for this pin Uint16 GPIO61:1; // 29 Configuration Lock bit for this pin Uint16 GPIO62:1; // 30 Configuration Lock bit for this pin Uint16 GPIO63:1; // 31 Configuration Lock bit for this pin }; union GPBLOCK_REG { Uint32 all; struct GPBLOCK_BITS bit; }; struct GPBCR_BITS { // bits description Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO36:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO38:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO60:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO61:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO62:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO63:1; // 31 Configuration lock commit bit for this pin }; union GPBCR_REG { Uint32 all; struct GPBCR_BITS bit; }; struct GPCCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO64 to GPIO71 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO72 to GPIO79 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO80 to GPIO87 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO88 to GPIO95 }; union GPCCTRL_REG { Uint32 all; struct GPCCTRL_BITS bit; }; struct GPCQSEL1_BITS { // bits description Uint16 GPIO64:2; // 1:0 Select input qualification type for GPIO64 Uint16 GPIO65:2; // 3:2 Select input qualification type for GPIO65 Uint16 GPIO66:2; // 5:4 Select input qualification type for GPIO66 Uint16 GPIO67:2; // 7:6 Select input qualification type for GPIO67 Uint16 GPIO68:2; // 9:8 Select input qualification type for GPIO68 Uint16 GPIO69:2; // 11:10 Select input qualification type for GPIO69 Uint16 GPIO70:2; // 13:12 Select input qualification type for GPIO70 Uint16 GPIO71:2; // 15:14 Select input qualification type for GPIO71 Uint16 GPIO72:2; // 17:16 Select input qualification type for GPIO72 Uint16 GPIO73:2; // 19:18 Select input qualification type for GPIO73 Uint16 GPIO74:2; // 21:20 Select input qualification type for GPIO74 Uint16 GPIO75:2; // 23:22 Select input qualification type for GPIO75 Uint16 GPIO76:2; // 25:24 Select input qualification type for GPIO76 Uint16 GPIO77:2; // 27:26 Select input qualification type for GPIO77 Uint16 GPIO78:2; // 29:28 Select input qualification type for GPIO78 Uint16 GPIO79:2; // 31:30 Select input qualification type for GPIO79 }; union GPCQSEL1_REG { Uint32 all; struct GPCQSEL1_BITS bit; }; struct GPCQSEL2_BITS { // bits description Uint16 GPIO80:2; // 1:0 Select input qualification type for GPIO80 Uint16 GPIO81:2; // 3:2 Select input qualification type for GPIO81 Uint16 GPIO82:2; // 5:4 Select input qualification type for GPIO82 Uint16 GPIO83:2; // 7:6 Select input qualification type for GPIO83 Uint16 GPIO84:2; // 9:8 Select input qualification type for GPIO84 Uint16 GPIO85:2; // 11:10 Select input qualification type for GPIO85 Uint16 GPIO86:2; // 13:12 Select input qualification type for GPIO86 Uint16 GPIO87:2; // 15:14 Select input qualification type for GPIO87 Uint16 GPIO88:2; // 17:16 Select input qualification type for GPIO88 Uint16 GPIO89:2; // 19:18 Select input qualification type for GPIO89 Uint16 GPIO90:2; // 21:20 Select input qualification type for GPIO90 Uint16 GPIO91:2; // 23:22 Select input qualification type for GPIO91 Uint16 GPIO92:2; // 25:24 Select input qualification type for GPIO92 Uint16 GPIO93:2; // 27:26 Select input qualification type for GPIO93 Uint16 GPIO94:2; // 29:28 Select input qualification type for GPIO94 Uint16 GPIO95:2; // 31:30 Select input qualification type for GPIO95 }; union GPCQSEL2_REG { Uint32 all; struct GPCQSEL2_BITS bit; }; struct GPCMUX1_BITS { // bits description Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 }; union GPCMUX1_REG { Uint32 all; struct GPCMUX1_BITS bit; }; struct GPCMUX2_BITS { // bits description Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 }; union GPCMUX2_REG { Uint32 all; struct GPCMUX2_BITS bit; }; struct GPCDIR_BITS { // bits description Uint16 GPIO64:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO65:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO66:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO67:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO68:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO69:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO70:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO71:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO72:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO73:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO74:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO75:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO76:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO77:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO78:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO79:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO80:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO81:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO82:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO83:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO84:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO85:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO86:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO87:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO88:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO89:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO90:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO91:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO92:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO93:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO94:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO95:1; // 31 Defines direction for this pin in GPIO mode }; union GPCDIR_REG { Uint32 all; struct GPCDIR_BITS bit; }; struct GPCPUD_BITS { // bits description Uint16 GPIO64:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO65:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO66:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO67:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO68:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO69:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO70:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO71:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO72:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO73:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO74:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO75:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO76:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO77:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO78:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO79:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO80:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO81:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO82:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO83:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO84:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO85:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO86:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO87:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO88:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO89:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO90:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO91:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO92:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO93:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO94:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO95:1; // 31 Pull-Up Disable control for this pin }; union GPCPUD_REG { Uint32 all; struct GPCPUD_BITS bit; }; struct GPCINV_BITS { // bits description Uint16 GPIO64:1; // 0 Input inversion control for this pin Uint16 GPIO65:1; // 1 Input inversion control for this pin Uint16 GPIO66:1; // 2 Input inversion control for this pin Uint16 GPIO67:1; // 3 Input inversion control for this pin Uint16 GPIO68:1; // 4 Input inversion control for this pin Uint16 GPIO69:1; // 5 Input inversion control for this pin Uint16 GPIO70:1; // 6 Input inversion control for this pin Uint16 GPIO71:1; // 7 Input inversion control for this pin Uint16 GPIO72:1; // 8 Input inversion control for this pin Uint16 GPIO73:1; // 9 Input inversion control for this pin Uint16 GPIO74:1; // 10 Input inversion control for this pin Uint16 GPIO75:1; // 11 Input inversion control for this pin Uint16 GPIO76:1; // 12 Input inversion control for this pin Uint16 GPIO77:1; // 13 Input inversion control for this pin Uint16 GPIO78:1; // 14 Input inversion control for this pin Uint16 GPIO79:1; // 15 Input inversion control for this pin Uint16 GPIO80:1; // 16 Input inversion control for this pin Uint16 GPIO81:1; // 17 Input inversion control for this pin Uint16 GPIO82:1; // 18 Input inversion control for this pin Uint16 GPIO83:1; // 19 Input inversion control for this pin Uint16 GPIO84:1; // 20 Input inversion control for this pin Uint16 GPIO85:1; // 21 Input inversion control for this pin Uint16 GPIO86:1; // 22 Input inversion control for this pin Uint16 GPIO87:1; // 23 Input inversion control for this pin Uint16 GPIO88:1; // 24 Input inversion control for this pin Uint16 GPIO89:1; // 25 Input inversion control for this pin Uint16 GPIO90:1; // 26 Input inversion control for this pin Uint16 GPIO91:1; // 27 Input inversion control for this pin Uint16 GPIO92:1; // 28 Input inversion control for this pin Uint16 GPIO93:1; // 29 Input inversion control for this pin Uint16 GPIO94:1; // 30 Input inversion control for this pin Uint16 GPIO95:1; // 31 Input inversion control for this pin }; union GPCINV_REG { Uint32 all; struct GPCINV_BITS bit; }; struct GPCODR_BITS { // bits description Uint16 GPIO64:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO65:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO66:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO67:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO68:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO69:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO70:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO71:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO72:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO73:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO74:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO75:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO76:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO77:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO78:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO79:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO80:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO81:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO82:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO83:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO84:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO85:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO86:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO87:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO88:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO89:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO90:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO91:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO92:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO93:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO94:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO95:1; // 31 Outpout Open-Drain control for this pin }; union GPCODR_REG { Uint32 all; struct GPCODR_BITS bit; }; struct GPCGMUX1_BITS { // bits description Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 }; union GPCGMUX1_REG { Uint32 all; struct GPCGMUX1_BITS bit; }; struct GPCGMUX2_BITS { // bits description Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 }; union GPCGMUX2_REG { Uint32 all; struct GPCGMUX2_BITS bit; }; struct GPCCSEL1_BITS { // bits description Uint16 GPIO64:4; // 3:0 GPIO64 Master CPU Select Uint16 GPIO65:4; // 7:4 GPIO65 Master CPU Select Uint16 GPIO66:4; // 11:8 GPIO66 Master CPU Select Uint16 GPIO67:4; // 15:12 GPIO67 Master CPU Select Uint16 GPIO68:4; // 19:16 GPIO68 Master CPU Select Uint16 GPIO69:4; // 23:20 GPIO69 Master CPU Select Uint16 GPIO70:4; // 27:24 GPIO70 Master CPU Select Uint16 GPIO71:4; // 31:28 GPIO71 Master CPU Select }; union GPCCSEL1_REG { Uint32 all; struct GPCCSEL1_BITS bit; }; struct GPCCSEL2_BITS { // bits description Uint16 GPIO72:4; // 3:0 GPIO72 Master CPU Select Uint16 GPIO73:4; // 7:4 GPIO73 Master CPU Select Uint16 GPIO74:4; // 11:8 GPIO74 Master CPU Select Uint16 GPIO75:4; // 15:12 GPIO75 Master CPU Select Uint16 GPIO76:4; // 19:16 GPIO76 Master CPU Select Uint16 GPIO77:4; // 23:20 GPIO77 Master CPU Select Uint16 GPIO78:4; // 27:24 GPIO78 Master CPU Select Uint16 GPIO79:4; // 31:28 GPIO79 Master CPU Select }; union GPCCSEL2_REG { Uint32 all; struct GPCCSEL2_BITS bit; }; struct GPCCSEL3_BITS { // bits description Uint16 GPIO80:4; // 3:0 GPIO80 Master CPU Select Uint16 GPIO81:4; // 7:4 GPIO81 Master CPU Select Uint16 GPIO82:4; // 11:8 GPIO82 Master CPU Select Uint16 GPIO83:4; // 15:12 GPIO83 Master CPU Select Uint16 GPIO84:4; // 19:16 GPIO84 Master CPU Select Uint16 GPIO85:4; // 23:20 GPIO85 Master CPU Select Uint16 GPIO86:4; // 27:24 GPIO86 Master CPU Select Uint16 GPIO87:4; // 31:28 GPIO87 Master CPU Select }; union GPCCSEL3_REG { Uint32 all; struct GPCCSEL3_BITS bit; }; struct GPCCSEL4_BITS { // bits description Uint16 GPIO88:4; // 3:0 GPIO88 Master CPU Select Uint16 GPIO89:4; // 7:4 GPIO89 Master CPU Select Uint16 GPIO90:4; // 11:8 GPIO90 Master CPU Select Uint16 GPIO91:4; // 15:12 GPIO91 Master CPU Select Uint16 GPIO92:4; // 19:16 GPIO92 Master CPU Select Uint16 GPIO93:4; // 23:20 GPIO93 Master CPU Select Uint16 GPIO94:4; // 27:24 GPIO94 Master CPU Select Uint16 GPIO95:4; // 31:28 GPIO95 Master CPU Select }; union GPCCSEL4_REG { Uint32 all; struct GPCCSEL4_BITS bit; }; struct GPCLOCK_BITS { // bits description Uint16 GPIO64:1; // 0 Configuration Lock bit for this pin Uint16 GPIO65:1; // 1 Configuration Lock bit for this pin Uint16 GPIO66:1; // 2 Configuration Lock bit for this pin Uint16 GPIO67:1; // 3 Configuration Lock bit for this pin Uint16 GPIO68:1; // 4 Configuration Lock bit for this pin Uint16 GPIO69:1; // 5 Configuration Lock bit for this pin Uint16 GPIO70:1; // 6 Configuration Lock bit for this pin Uint16 GPIO71:1; // 7 Configuration Lock bit for this pin Uint16 GPIO72:1; // 8 Configuration Lock bit for this pin Uint16 GPIO73:1; // 9 Configuration Lock bit for this pin Uint16 GPIO74:1; // 10 Configuration Lock bit for this pin Uint16 GPIO75:1; // 11 Configuration Lock bit for this pin Uint16 GPIO76:1; // 12 Configuration Lock bit for this pin Uint16 GPIO77:1; // 13 Configuration Lock bit for this pin Uint16 GPIO78:1; // 14 Configuration Lock bit for this pin Uint16 GPIO79:1; // 15 Configuration Lock bit for this pin Uint16 GPIO80:1; // 16 Configuration Lock bit for this pin Uint16 GPIO81:1; // 17 Configuration Lock bit for this pin Uint16 GPIO82:1; // 18 Configuration Lock bit for this pin Uint16 GPIO83:1; // 19 Configuration Lock bit for this pin Uint16 GPIO84:1; // 20 Configuration Lock bit for this pin Uint16 GPIO85:1; // 21 Configuration Lock bit for this pin Uint16 GPIO86:1; // 22 Configuration Lock bit for this pin Uint16 GPIO87:1; // 23 Configuration Lock bit for this pin Uint16 GPIO88:1; // 24 Configuration Lock bit for this pin Uint16 GPIO89:1; // 25 Configuration Lock bit for this pin Uint16 GPIO90:1; // 26 Configuration Lock bit for this pin Uint16 GPIO91:1; // 27 Configuration Lock bit for this pin Uint16 GPIO92:1; // 28 Configuration Lock bit for this pin Uint16 GPIO93:1; // 29 Configuration Lock bit for this pin Uint16 GPIO94:1; // 30 Configuration Lock bit for this pin Uint16 GPIO95:1; // 31 Configuration Lock bit for this pin }; union GPCLOCK_REG { Uint32 all; struct GPCLOCK_BITS bit; }; struct GPCCR_BITS { // bits description Uint16 GPIO64:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO65:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO66:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO67:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO68:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO69:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO70:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO71:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO72:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO73:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO74:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO75:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO76:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO77:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO78:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO79:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO80:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO81:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO82:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO83:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO84:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO85:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO86:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO87:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO88:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO89:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO90:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO91:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO92:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO93:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO94:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO95:1; // 31 Configuration lock commit bit for this pin }; union GPCCR_REG { Uint32 all; struct GPCCR_BITS bit; }; struct GPDCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO96 to GPIO103 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO104 to GPIO111 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO112 to GPIO119 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO120 to GPIO127 }; union GPDCTRL_REG { Uint32 all; struct GPDCTRL_BITS bit; }; struct GPDQSEL1_BITS { // bits description Uint16 GPIO96:2; // 1:0 Select input qualification type for GPIO96 Uint16 GPIO97:2; // 3:2 Select input qualification type for GPIO97 Uint16 GPIO98:2; // 5:4 Select input qualification type for GPIO98 Uint16 GPIO99:2; // 7:6 Select input qualification type for GPIO99 Uint16 GPIO100:2; // 9:8 Select input qualification type for GPIO100 Uint16 GPIO101:2; // 11:10 Select input qualification type for GPIO101 Uint16 GPIO102:2; // 13:12 Select input qualification type for GPIO102 Uint16 GPIO103:2; // 15:14 Select input qualification type for GPIO103 Uint16 GPIO104:2; // 17:16 Select input qualification type for GPIO104 Uint16 GPIO105:2; // 19:18 Select input qualification type for GPIO105 Uint16 GPIO106:2; // 21:20 Select input qualification type for GPIO106 Uint16 GPIO107:2; // 23:22 Select input qualification type for GPIO107 Uint16 GPIO108:2; // 25:24 Select input qualification type for GPIO108 Uint16 GPIO109:2; // 27:26 Select input qualification type for GPIO109 Uint16 GPIO110:2; // 29:28 Select input qualification type for GPIO110 Uint16 GPIO111:2; // 31:30 Select input qualification type for GPIO111 }; union GPDQSEL1_REG { Uint32 all; struct GPDQSEL1_BITS bit; }; struct GPDQSEL2_BITS { // bits description Uint16 GPIO112:2; // 1:0 Select input qualification type for GPIO112 Uint16 GPIO113:2; // 3:2 Select input qualification type for GPIO113 Uint16 GPIO114:2; // 5:4 Select input qualification type for GPIO114 Uint16 GPIO115:2; // 7:6 Select input qualification type for GPIO115 Uint16 GPIO116:2; // 9:8 Select input qualification type for GPIO116 Uint16 GPIO117:2; // 11:10 Select input qualification type for GPIO117 Uint16 GPIO118:2; // 13:12 Select input qualification type for GPIO118 Uint16 GPIO119:2; // 15:14 Select input qualification type for GPIO119 Uint16 GPIO120:2; // 17:16 Select input qualification type for GPIO120 Uint16 GPIO121:2; // 19:18 Select input qualification type for GPIO121 Uint16 GPIO122:2; // 21:20 Select input qualification type for GPIO122 Uint16 GPIO123:2; // 23:22 Select input qualification type for GPIO123 Uint16 GPIO124:2; // 25:24 Select input qualification type for GPIO124 Uint16 GPIO125:2; // 27:26 Select input qualification type for GPIO125 Uint16 GPIO126:2; // 29:28 Select input qualification type for GPIO126 Uint16 GPIO127:2; // 31:30 Select input qualification type for GPIO127 }; union GPDQSEL2_REG { Uint32 all; struct GPDQSEL2_BITS bit; }; struct GPDMUX1_BITS { // bits description Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 }; union GPDMUX1_REG { Uint32 all; struct GPDMUX1_BITS bit; }; struct GPDMUX2_BITS { // bits description Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 }; union GPDMUX2_REG { Uint32 all; struct GPDMUX2_BITS bit; }; struct GPDDIR_BITS { // bits description Uint16 GPIO96:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO97:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO98:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO99:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO100:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO101:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO102:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO103:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO104:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO105:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO106:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO107:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO108:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO109:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO110:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO111:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO112:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO113:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO114:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO115:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO116:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO117:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO118:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO119:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO120:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO121:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO122:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO123:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO124:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO125:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO126:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO127:1; // 31 Defines direction for this pin in GPIO mode }; union GPDDIR_REG { Uint32 all; struct GPDDIR_BITS bit; }; struct GPDPUD_BITS { // bits description Uint16 GPIO96:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO97:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO98:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO99:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO100:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO101:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO102:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO103:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO104:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO105:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO106:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO107:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO108:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO109:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO110:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO111:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO112:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO113:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO114:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO115:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO116:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO117:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO118:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO119:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO120:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO121:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO122:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO123:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO124:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO125:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO126:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO127:1; // 31 Pull-Up Disable control for this pin }; union GPDPUD_REG { Uint32 all; struct GPDPUD_BITS bit; }; struct GPDINV_BITS { // bits description Uint16 GPIO96:1; // 0 Input inversion control for this pin Uint16 GPIO97:1; // 1 Input inversion control for this pin Uint16 GPIO98:1; // 2 Input inversion control for this pin Uint16 GPIO99:1; // 3 Input inversion control for this pin Uint16 GPIO100:1; // 4 Input inversion control for this pin Uint16 GPIO101:1; // 5 Input inversion control for this pin Uint16 GPIO102:1; // 6 Input inversion control for this pin Uint16 GPIO103:1; // 7 Input inversion control for this pin Uint16 GPIO104:1; // 8 Input inversion control for this pin Uint16 GPIO105:1; // 9 Input inversion control for this pin Uint16 GPIO106:1; // 10 Input inversion control for this pin Uint16 GPIO107:1; // 11 Input inversion control for this pin Uint16 GPIO108:1; // 12 Input inversion control for this pin Uint16 GPIO109:1; // 13 Input inversion control for this pin Uint16 GPIO110:1; // 14 Input inversion control for this pin Uint16 GPIO111:1; // 15 Input inversion control for this pin Uint16 GPIO112:1; // 16 Input inversion control for this pin Uint16 GPIO113:1; // 17 Input inversion control for this pin Uint16 GPIO114:1; // 18 Input inversion control for this pin Uint16 GPIO115:1; // 19 Input inversion control for this pin Uint16 GPIO116:1; // 20 Input inversion control for this pin Uint16 GPIO117:1; // 21 Input inversion control for this pin Uint16 GPIO118:1; // 22 Input inversion control for this pin Uint16 GPIO119:1; // 23 Input inversion control for this pin Uint16 GPIO120:1; // 24 Input inversion control for this pin Uint16 GPIO121:1; // 25 Input inversion control for this pin Uint16 GPIO122:1; // 26 Input inversion control for this pin Uint16 GPIO123:1; // 27 Input inversion control for this pin Uint16 GPIO124:1; // 28 Input inversion control for this pin Uint16 GPIO125:1; // 29 Input inversion control for this pin Uint16 GPIO126:1; // 30 Input inversion control for this pin Uint16 GPIO127:1; // 31 Input inversion control for this pin }; union GPDINV_REG { Uint32 all; struct GPDINV_BITS bit; }; struct GPDODR_BITS { // bits description Uint16 GPIO96:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO97:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO98:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO99:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO100:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO101:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO102:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO103:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO104:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO105:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO106:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO107:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO108:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO109:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO110:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO111:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO112:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO113:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO114:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO115:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO116:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO117:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO118:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO119:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO120:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO121:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO122:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO123:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO124:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO125:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO126:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO127:1; // 31 Outpout Open-Drain control for this pin }; union GPDODR_REG { Uint32 all; struct GPDODR_BITS bit; }; struct GPDGMUX1_BITS { // bits description Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 }; union GPDGMUX1_REG { Uint32 all; struct GPDGMUX1_BITS bit; }; struct GPDGMUX2_BITS { // bits description Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 }; union GPDGMUX2_REG { Uint32 all; struct GPDGMUX2_BITS bit; }; struct GPDCSEL1_BITS { // bits description Uint16 GPIO96:4; // 3:0 GPIO96 Master CPU Select Uint16 GPIO97:4; // 7:4 GPIO97 Master CPU Select Uint16 GPIO98:4; // 11:8 GPIO98 Master CPU Select Uint16 GPIO99:4; // 15:12 GPIO99 Master CPU Select Uint16 GPIO100:4; // 19:16 GPIO100 Master CPU Select Uint16 GPIO101:4; // 23:20 GPIO101 Master CPU Select Uint16 GPIO102:4; // 27:24 GPIO102 Master CPU Select Uint16 GPIO103:4; // 31:28 GPIO103 Master CPU Select }; union GPDCSEL1_REG { Uint32 all; struct GPDCSEL1_BITS bit; }; struct GPDCSEL2_BITS { // bits description Uint16 GPIO104:4; // 3:0 GPIO104 Master CPU Select Uint16 GPIO105:4; // 7:4 GPIO105 Master CPU Select Uint16 GPIO106:4; // 11:8 GPIO106 Master CPU Select Uint16 GPIO107:4; // 15:12 GPIO107 Master CPU Select Uint16 GPIO108:4; // 19:16 GPIO108 Master CPU Select Uint16 GPIO109:4; // 23:20 GPIO109 Master CPU Select Uint16 GPIO110:4; // 27:24 GPIO110 Master CPU Select Uint16 GPIO111:4; // 31:28 GPIO111 Master CPU Select }; union GPDCSEL2_REG { Uint32 all; struct GPDCSEL2_BITS bit; }; struct GPDCSEL3_BITS { // bits description Uint16 GPIO112:4; // 3:0 GPIO112 Master CPU Select Uint16 GPIO113:4; // 7:4 GPIO113 Master CPU Select Uint16 GPIO114:4; // 11:8 GPIO114 Master CPU Select Uint16 GPIO115:4; // 15:12 GPIO115 Master CPU Select Uint16 GPIO116:4; // 19:16 GPIO116 Master CPU Select Uint16 GPIO117:4; // 23:20 GPIO117 Master CPU Select Uint16 GPIO118:4; // 27:24 GPIO118 Master CPU Select Uint16 GPIO119:4; // 31:28 GPIO119 Master CPU Select }; union GPDCSEL3_REG { Uint32 all; struct GPDCSEL3_BITS bit; }; struct GPDCSEL4_BITS { // bits description Uint16 GPIO120:4; // 3:0 GPIO120 Master CPU Select Uint16 GPIO121:4; // 7:4 GPIO121 Master CPU Select Uint16 GPIO122:4; // 11:8 GPIO122 Master CPU Select Uint16 GPIO123:4; // 15:12 GPIO123 Master CPU Select Uint16 GPIO124:4; // 19:16 GPIO124 Master CPU Select Uint16 GPIO125:4; // 23:20 GPIO125 Master CPU Select Uint16 GPIO126:4; // 27:24 GPIO126 Master CPU Select Uint16 GPIO127:4; // 31:28 GPIO127 Master CPU Select }; union GPDCSEL4_REG { Uint32 all; struct GPDCSEL4_BITS bit; }; struct GPDLOCK_BITS { // bits description Uint16 GPIO96:1; // 0 Configuration Lock bit for this pin Uint16 GPIO97:1; // 1 Configuration Lock bit for this pin Uint16 GPIO98:1; // 2 Configuration Lock bit for this pin Uint16 GPIO99:1; // 3 Configuration Lock bit for this pin Uint16 GPIO100:1; // 4 Configuration Lock bit for this pin Uint16 GPIO101:1; // 5 Configuration Lock bit for this pin Uint16 GPIO102:1; // 6 Configuration Lock bit for this pin Uint16 GPIO103:1; // 7 Configuration Lock bit for this pin Uint16 GPIO104:1; // 8 Configuration Lock bit for this pin Uint16 GPIO105:1; // 9 Configuration Lock bit for this pin Uint16 GPIO106:1; // 10 Configuration Lock bit for this pin Uint16 GPIO107:1; // 11 Configuration Lock bit for this pin Uint16 GPIO108:1; // 12 Configuration Lock bit for this pin Uint16 GPIO109:1; // 13 Configuration Lock bit for this pin Uint16 GPIO110:1; // 14 Configuration Lock bit for this pin Uint16 GPIO111:1; // 15 Configuration Lock bit for this pin Uint16 GPIO112:1; // 16 Configuration Lock bit for this pin Uint16 GPIO113:1; // 17 Configuration Lock bit for this pin Uint16 GPIO114:1; // 18 Configuration Lock bit for this pin Uint16 GPIO115:1; // 19 Configuration Lock bit for this pin Uint16 GPIO116:1; // 20 Configuration Lock bit for this pin Uint16 GPIO117:1; // 21 Configuration Lock bit for this pin Uint16 GPIO118:1; // 22 Configuration Lock bit for this pin Uint16 GPIO119:1; // 23 Configuration Lock bit for this pin Uint16 GPIO120:1; // 24 Configuration Lock bit for this pin Uint16 GPIO121:1; // 25 Configuration Lock bit for this pin Uint16 GPIO122:1; // 26 Configuration Lock bit for this pin Uint16 GPIO123:1; // 27 Configuration Lock bit for this pin Uint16 GPIO124:1; // 28 Configuration Lock bit for this pin Uint16 GPIO125:1; // 29 Configuration Lock bit for this pin Uint16 GPIO126:1; // 30 Configuration Lock bit for this pin Uint16 GPIO127:1; // 31 Configuration Lock bit for this pin }; union GPDLOCK_REG { Uint32 all; struct GPDLOCK_BITS bit; }; struct GPDCR_BITS { // bits description Uint16 GPIO96:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO97:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO98:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO99:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO100:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO101:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO102:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO103:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO104:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO105:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO106:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO107:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO108:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO109:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO110:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO111:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO112:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO113:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO114:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO115:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO116:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO117:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO118:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO119:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO120:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO121:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO122:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO123:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO124:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO125:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO126:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO127:1; // 31 Configuration lock commit bit for this pin }; union GPDCR_REG { Uint32 all; struct GPDCR_BITS bit; }; struct GPECTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO128 to GPIO135 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO136 to GPIO143 Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO144 to GPIO151 Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO152 to GPIO159 }; union GPECTRL_REG { Uint32 all; struct GPECTRL_BITS bit; }; struct GPEQSEL1_BITS { // bits description Uint16 GPIO128:2; // 1:0 Select input qualification type for GPIO128 Uint16 GPIO129:2; // 3:2 Select input qualification type for GPIO129 Uint16 GPIO130:2; // 5:4 Select input qualification type for GPIO130 Uint16 GPIO131:2; // 7:6 Select input qualification type for GPIO131 Uint16 GPIO132:2; // 9:8 Select input qualification type for GPIO132 Uint16 GPIO133:2; // 11:10 Select input qualification type for GPIO133 Uint16 GPIO134:2; // 13:12 Select input qualification type for GPIO134 Uint16 GPIO135:2; // 15:14 Select input qualification type for GPIO135 Uint16 GPIO136:2; // 17:16 Select input qualification type for GPIO136 Uint16 GPIO137:2; // 19:18 Select input qualification type for GPIO137 Uint16 GPIO138:2; // 21:20 Select input qualification type for GPIO138 Uint16 GPIO139:2; // 23:22 Select input qualification type for GPIO139 Uint16 GPIO140:2; // 25:24 Select input qualification type for GPIO140 Uint16 GPIO141:2; // 27:26 Select input qualification type for GPIO141 Uint16 GPIO142:2; // 29:28 Select input qualification type for GPIO142 Uint16 GPIO143:2; // 31:30 Select input qualification type for GPIO143 }; union GPEQSEL1_REG { Uint32 all; struct GPEQSEL1_BITS bit; }; struct GPEQSEL2_BITS { // bits description Uint16 GPIO144:2; // 1:0 Select input qualification type for GPIO144 Uint16 GPIO145:2; // 3:2 Select input qualification type for GPIO145 Uint16 GPIO146:2; // 5:4 Select input qualification type for GPIO146 Uint16 GPIO147:2; // 7:6 Select input qualification type for GPIO147 Uint16 GPIO148:2; // 9:8 Select input qualification type for GPIO148 Uint16 GPIO149:2; // 11:10 Select input qualification type for GPIO149 Uint16 GPIO150:2; // 13:12 Select input qualification type for GPIO150 Uint16 GPIO151:2; // 15:14 Select input qualification type for GPIO151 Uint16 GPIO152:2; // 17:16 Select input qualification type for GPIO152 Uint16 GPIO153:2; // 19:18 Select input qualification type for GPIO153 Uint16 GPIO154:2; // 21:20 Select input qualification type for GPIO154 Uint16 GPIO155:2; // 23:22 Select input qualification type for GPIO155 Uint16 GPIO156:2; // 25:24 Select input qualification type for GPIO156 Uint16 GPIO157:2; // 27:26 Select input qualification type for GPIO157 Uint16 GPIO158:2; // 29:28 Select input qualification type for GPIO158 Uint16 GPIO159:2; // 31:30 Select input qualification type for GPIO159 }; union GPEQSEL2_REG { Uint32 all; struct GPEQSEL2_BITS bit; }; struct GPEMUX1_BITS { // bits description Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 }; union GPEMUX1_REG { Uint32 all; struct GPEMUX1_BITS bit; }; struct GPEMUX2_BITS { // bits description Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 }; union GPEMUX2_REG { Uint32 all; struct GPEMUX2_BITS bit; }; struct GPEDIR_BITS { // bits description Uint16 GPIO128:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO129:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO130:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO131:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO132:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO133:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO134:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO135:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO136:1; // 8 Defines direction for this pin in GPIO mode Uint16 GPIO137:1; // 9 Defines direction for this pin in GPIO mode Uint16 GPIO138:1; // 10 Defines direction for this pin in GPIO mode Uint16 GPIO139:1; // 11 Defines direction for this pin in GPIO mode Uint16 GPIO140:1; // 12 Defines direction for this pin in GPIO mode Uint16 GPIO141:1; // 13 Defines direction for this pin in GPIO mode Uint16 GPIO142:1; // 14 Defines direction for this pin in GPIO mode Uint16 GPIO143:1; // 15 Defines direction for this pin in GPIO mode Uint16 GPIO144:1; // 16 Defines direction for this pin in GPIO mode Uint16 GPIO145:1; // 17 Defines direction for this pin in GPIO mode Uint16 GPIO146:1; // 18 Defines direction for this pin in GPIO mode Uint16 GPIO147:1; // 19 Defines direction for this pin in GPIO mode Uint16 GPIO148:1; // 20 Defines direction for this pin in GPIO mode Uint16 GPIO149:1; // 21 Defines direction for this pin in GPIO mode Uint16 GPIO150:1; // 22 Defines direction for this pin in GPIO mode Uint16 GPIO151:1; // 23 Defines direction for this pin in GPIO mode Uint16 GPIO152:1; // 24 Defines direction for this pin in GPIO mode Uint16 GPIO153:1; // 25 Defines direction for this pin in GPIO mode Uint16 GPIO154:1; // 26 Defines direction for this pin in GPIO mode Uint16 GPIO155:1; // 27 Defines direction for this pin in GPIO mode Uint16 GPIO156:1; // 28 Defines direction for this pin in GPIO mode Uint16 GPIO157:1; // 29 Defines direction for this pin in GPIO mode Uint16 GPIO158:1; // 30 Defines direction for this pin in GPIO mode Uint16 GPIO159:1; // 31 Defines direction for this pin in GPIO mode }; union GPEDIR_REG { Uint32 all; struct GPEDIR_BITS bit; }; struct GPEPUD_BITS { // bits description Uint16 GPIO128:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO129:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO130:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO131:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO132:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO133:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO134:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO135:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO136:1; // 8 Pull-Up Disable control for this pin Uint16 GPIO137:1; // 9 Pull-Up Disable control for this pin Uint16 GPIO138:1; // 10 Pull-Up Disable control for this pin Uint16 GPIO139:1; // 11 Pull-Up Disable control for this pin Uint16 GPIO140:1; // 12 Pull-Up Disable control for this pin Uint16 GPIO141:1; // 13 Pull-Up Disable control for this pin Uint16 GPIO142:1; // 14 Pull-Up Disable control for this pin Uint16 GPIO143:1; // 15 Pull-Up Disable control for this pin Uint16 GPIO144:1; // 16 Pull-Up Disable control for this pin Uint16 GPIO145:1; // 17 Pull-Up Disable control for this pin Uint16 GPIO146:1; // 18 Pull-Up Disable control for this pin Uint16 GPIO147:1; // 19 Pull-Up Disable control for this pin Uint16 GPIO148:1; // 20 Pull-Up Disable control for this pin Uint16 GPIO149:1; // 21 Pull-Up Disable control for this pin Uint16 GPIO150:1; // 22 Pull-Up Disable control for this pin Uint16 GPIO151:1; // 23 Pull-Up Disable control for this pin Uint16 GPIO152:1; // 24 Pull-Up Disable control for this pin Uint16 GPIO153:1; // 25 Pull-Up Disable control for this pin Uint16 GPIO154:1; // 26 Pull-Up Disable control for this pin Uint16 GPIO155:1; // 27 Pull-Up Disable control for this pin Uint16 GPIO156:1; // 28 Pull-Up Disable control for this pin Uint16 GPIO157:1; // 29 Pull-Up Disable control for this pin Uint16 GPIO158:1; // 30 Pull-Up Disable control for this pin Uint16 GPIO159:1; // 31 Pull-Up Disable control for this pin }; union GPEPUD_REG { Uint32 all; struct GPEPUD_BITS bit; }; struct GPEINV_BITS { // bits description Uint16 GPIO128:1; // 0 Input inversion control for this pin Uint16 GPIO129:1; // 1 Input inversion control for this pin Uint16 GPIO130:1; // 2 Input inversion control for this pin Uint16 GPIO131:1; // 3 Input inversion control for this pin Uint16 GPIO132:1; // 4 Input inversion control for this pin Uint16 GPIO133:1; // 5 Input inversion control for this pin Uint16 GPIO134:1; // 6 Input inversion control for this pin Uint16 GPIO135:1; // 7 Input inversion control for this pin Uint16 GPIO136:1; // 8 Input inversion control for this pin Uint16 GPIO137:1; // 9 Input inversion control for this pin Uint16 GPIO138:1; // 10 Input inversion control for this pin Uint16 GPIO139:1; // 11 Input inversion control for this pin Uint16 GPIO140:1; // 12 Input inversion control for this pin Uint16 GPIO141:1; // 13 Input inversion control for this pin Uint16 GPIO142:1; // 14 Input inversion control for this pin Uint16 GPIO143:1; // 15 Input inversion control for this pin Uint16 GPIO144:1; // 16 Input inversion control for this pin Uint16 GPIO145:1; // 17 Input inversion control for this pin Uint16 GPIO146:1; // 18 Input inversion control for this pin Uint16 GPIO147:1; // 19 Input inversion control for this pin Uint16 GPIO148:1; // 20 Input inversion control for this pin Uint16 GPIO149:1; // 21 Input inversion control for this pin Uint16 GPIO150:1; // 22 Input inversion control for this pin Uint16 GPIO151:1; // 23 Input inversion control for this pin Uint16 GPIO152:1; // 24 Input inversion control for this pin Uint16 GPIO153:1; // 25 Input inversion control for this pin Uint16 GPIO154:1; // 26 Input inversion control for this pin Uint16 GPIO155:1; // 27 Input inversion control for this pin Uint16 GPIO156:1; // 28 Input inversion control for this pin Uint16 GPIO157:1; // 29 Input inversion control for this pin Uint16 GPIO158:1; // 30 Input inversion control for this pin Uint16 GPIO159:1; // 31 Input inversion control for this pin }; union GPEINV_REG { Uint32 all; struct GPEINV_BITS bit; }; struct GPEODR_BITS { // bits description Uint16 GPIO128:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO129:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO130:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO131:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO132:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO133:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO134:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO135:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO136:1; // 8 Outpout Open-Drain control for this pin Uint16 GPIO137:1; // 9 Outpout Open-Drain control for this pin Uint16 GPIO138:1; // 10 Outpout Open-Drain control for this pin Uint16 GPIO139:1; // 11 Outpout Open-Drain control for this pin Uint16 GPIO140:1; // 12 Outpout Open-Drain control for this pin Uint16 GPIO141:1; // 13 Outpout Open-Drain control for this pin Uint16 GPIO142:1; // 14 Outpout Open-Drain control for this pin Uint16 GPIO143:1; // 15 Outpout Open-Drain control for this pin Uint16 GPIO144:1; // 16 Outpout Open-Drain control for this pin Uint16 GPIO145:1; // 17 Outpout Open-Drain control for this pin Uint16 GPIO146:1; // 18 Outpout Open-Drain control for this pin Uint16 GPIO147:1; // 19 Outpout Open-Drain control for this pin Uint16 GPIO148:1; // 20 Outpout Open-Drain control for this pin Uint16 GPIO149:1; // 21 Outpout Open-Drain control for this pin Uint16 GPIO150:1; // 22 Outpout Open-Drain control for this pin Uint16 GPIO151:1; // 23 Outpout Open-Drain control for this pin Uint16 GPIO152:1; // 24 Outpout Open-Drain control for this pin Uint16 GPIO153:1; // 25 Outpout Open-Drain control for this pin Uint16 GPIO154:1; // 26 Outpout Open-Drain control for this pin Uint16 GPIO155:1; // 27 Outpout Open-Drain control for this pin Uint16 GPIO156:1; // 28 Outpout Open-Drain control for this pin Uint16 GPIO157:1; // 29 Outpout Open-Drain control for this pin Uint16 GPIO158:1; // 30 Outpout Open-Drain control for this pin Uint16 GPIO159:1; // 31 Outpout Open-Drain control for this pin }; union GPEODR_REG { Uint32 all; struct GPEODR_BITS bit; }; struct GPEGMUX1_BITS { // bits description Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 }; union GPEGMUX1_REG { Uint32 all; struct GPEGMUX1_BITS bit; }; struct GPEGMUX2_BITS { // bits description Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 }; union GPEGMUX2_REG { Uint32 all; struct GPEGMUX2_BITS bit; }; struct GPECSEL1_BITS { // bits description Uint16 GPIO128:4; // 3:0 GPIO128 Master CPU Select Uint16 GPIO129:4; // 7:4 GPIO129 Master CPU Select Uint16 GPIO130:4; // 11:8 GPIO130 Master CPU Select Uint16 GPIO131:4; // 15:12 GPIO131 Master CPU Select Uint16 GPIO132:4; // 19:16 GPIO132 Master CPU Select Uint16 GPIO133:4; // 23:20 GPIO133 Master CPU Select Uint16 GPIO134:4; // 27:24 GPIO134 Master CPU Select Uint16 GPIO135:4; // 31:28 GPIO135 Master CPU Select }; union GPECSEL1_REG { Uint32 all; struct GPECSEL1_BITS bit; }; struct GPECSEL2_BITS { // bits description Uint16 GPIO136:4; // 3:0 GPIO136 Master CPU Select Uint16 GPIO137:4; // 7:4 GPIO137 Master CPU Select Uint16 GPIO138:4; // 11:8 GPIO138 Master CPU Select Uint16 GPIO139:4; // 15:12 GPIO139 Master CPU Select Uint16 GPIO140:4; // 19:16 GPIO140 Master CPU Select Uint16 GPIO141:4; // 23:20 GPIO141 Master CPU Select Uint16 GPIO142:4; // 27:24 GPIO142 Master CPU Select Uint16 GPIO143:4; // 31:28 GPIO143 Master CPU Select }; union GPECSEL2_REG { Uint32 all; struct GPECSEL2_BITS bit; }; struct GPECSEL3_BITS { // bits description Uint16 GPIO144:4; // 3:0 GPIO144 Master CPU Select Uint16 GPIO145:4; // 7:4 GPIO145 Master CPU Select Uint16 GPIO146:4; // 11:8 GPIO146 Master CPU Select Uint16 GPIO147:4; // 15:12 GPIO147 Master CPU Select Uint16 GPIO148:4; // 19:16 GPIO148 Master CPU Select Uint16 GPIO149:4; // 23:20 GPIO149 Master CPU Select Uint16 GPIO150:4; // 27:24 GPIO150 Master CPU Select Uint16 GPIO151:4; // 31:28 GPIO151 Master CPU Select }; union GPECSEL3_REG { Uint32 all; struct GPECSEL3_BITS bit; }; struct GPECSEL4_BITS { // bits description Uint16 GPIO152:4; // 3:0 GPIO152 Master CPU Select Uint16 GPIO153:4; // 7:4 GPIO153 Master CPU Select Uint16 GPIO154:4; // 11:8 GPIO154 Master CPU Select Uint16 GPIO155:4; // 15:12 GPIO155 Master CPU Select Uint16 GPIO156:4; // 19:16 GPIO156 Master CPU Select Uint16 GPIO157:4; // 23:20 GPIO157 Master CPU Select Uint16 GPIO158:4; // 27:24 GPIO158 Master CPU Select Uint16 GPIO159:4; // 31:28 GPIO159 Master CPU Select }; union GPECSEL4_REG { Uint32 all; struct GPECSEL4_BITS bit; }; struct GPELOCK_BITS { // bits description Uint16 GPIO128:1; // 0 Configuration Lock bit for this pin Uint16 GPIO129:1; // 1 Configuration Lock bit for this pin Uint16 GPIO130:1; // 2 Configuration Lock bit for this pin Uint16 GPIO131:1; // 3 Configuration Lock bit for this pin Uint16 GPIO132:1; // 4 Configuration Lock bit for this pin Uint16 GPIO133:1; // 5 Configuration Lock bit for this pin Uint16 GPIO134:1; // 6 Configuration Lock bit for this pin Uint16 GPIO135:1; // 7 Configuration Lock bit for this pin Uint16 GPIO136:1; // 8 Configuration Lock bit for this pin Uint16 GPIO137:1; // 9 Configuration Lock bit for this pin Uint16 GPIO138:1; // 10 Configuration Lock bit for this pin Uint16 GPIO139:1; // 11 Configuration Lock bit for this pin Uint16 GPIO140:1; // 12 Configuration Lock bit for this pin Uint16 GPIO141:1; // 13 Configuration Lock bit for this pin Uint16 GPIO142:1; // 14 Configuration Lock bit for this pin Uint16 GPIO143:1; // 15 Configuration Lock bit for this pin Uint16 GPIO144:1; // 16 Configuration Lock bit for this pin Uint16 GPIO145:1; // 17 Configuration Lock bit for this pin Uint16 GPIO146:1; // 18 Configuration Lock bit for this pin Uint16 GPIO147:1; // 19 Configuration Lock bit for this pin Uint16 GPIO148:1; // 20 Configuration Lock bit for this pin Uint16 GPIO149:1; // 21 Configuration Lock bit for this pin Uint16 GPIO150:1; // 22 Configuration Lock bit for this pin Uint16 GPIO151:1; // 23 Configuration Lock bit for this pin Uint16 GPIO152:1; // 24 Configuration Lock bit for this pin Uint16 GPIO153:1; // 25 Configuration Lock bit for this pin Uint16 GPIO154:1; // 26 Configuration Lock bit for this pin Uint16 GPIO155:1; // 27 Configuration Lock bit for this pin Uint16 GPIO156:1; // 28 Configuration Lock bit for this pin Uint16 GPIO157:1; // 29 Configuration Lock bit for this pin Uint16 GPIO158:1; // 30 Configuration Lock bit for this pin Uint16 GPIO159:1; // 31 Configuration Lock bit for this pin }; union GPELOCK_REG { Uint32 all; struct GPELOCK_BITS bit; }; struct GPECR_BITS { // bits description Uint16 GPIO128:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO129:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO130:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO131:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO132:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO133:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO134:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO135:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO136:1; // 8 Configuration lock commit bit for this pin Uint16 GPIO137:1; // 9 Configuration lock commit bit for this pin Uint16 GPIO138:1; // 10 Configuration lock commit bit for this pin Uint16 GPIO139:1; // 11 Configuration lock commit bit for this pin Uint16 GPIO140:1; // 12 Configuration lock commit bit for this pin Uint16 GPIO141:1; // 13 Configuration lock commit bit for this pin Uint16 GPIO142:1; // 14 Configuration lock commit bit for this pin Uint16 GPIO143:1; // 15 Configuration lock commit bit for this pin Uint16 GPIO144:1; // 16 Configuration lock commit bit for this pin Uint16 GPIO145:1; // 17 Configuration lock commit bit for this pin Uint16 GPIO146:1; // 18 Configuration lock commit bit for this pin Uint16 GPIO147:1; // 19 Configuration lock commit bit for this pin Uint16 GPIO148:1; // 20 Configuration lock commit bit for this pin Uint16 GPIO149:1; // 21 Configuration lock commit bit for this pin Uint16 GPIO150:1; // 22 Configuration lock commit bit for this pin Uint16 GPIO151:1; // 23 Configuration lock commit bit for this pin Uint16 GPIO152:1; // 24 Configuration lock commit bit for this pin Uint16 GPIO153:1; // 25 Configuration lock commit bit for this pin Uint16 GPIO154:1; // 26 Configuration lock commit bit for this pin Uint16 GPIO155:1; // 27 Configuration lock commit bit for this pin Uint16 GPIO156:1; // 28 Configuration lock commit bit for this pin Uint16 GPIO157:1; // 29 Configuration lock commit bit for this pin Uint16 GPIO158:1; // 30 Configuration lock commit bit for this pin Uint16 GPIO159:1; // 31 Configuration lock commit bit for this pin }; union GPECR_REG { Uint32 all; struct GPECR_BITS bit; }; struct GPFCTRL_BITS { // bits description Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO160 to GPIO167 Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO168 Uint16 rsvd1:8; // 23:16 Reserved Uint16 rsvd2:8; // 31:24 Reserved }; union GPFCTRL_REG { Uint32 all; struct GPFCTRL_BITS bit; }; struct GPFQSEL1_BITS { // bits description Uint16 GPIO160:2; // 1:0 Select input qualification type for GPIO160 Uint16 GPIO161:2; // 3:2 Select input qualification type for GPIO161 Uint16 GPIO162:2; // 5:4 Select input qualification type for GPIO162 Uint16 GPIO163:2; // 7:6 Select input qualification type for GPIO163 Uint16 GPIO164:2; // 9:8 Select input qualification type for GPIO164 Uint16 GPIO165:2; // 11:10 Select input qualification type for GPIO165 Uint16 GPIO166:2; // 13:12 Select input qualification type for GPIO166 Uint16 GPIO167:2; // 15:14 Select input qualification type for GPIO167 Uint16 GPIO168:2; // 17:16 Select input qualification type for GPIO168 Uint16 rsvd1:2; // 19:18 Reserved Uint16 rsvd2:2; // 21:20 Reserved Uint16 rsvd3:2; // 23:22 Reserved Uint16 rsvd4:2; // 25:24 Reserved Uint16 rsvd5:2; // 27:26 Reserved Uint16 rsvd6:2; // 29:28 Reserved Uint16 rsvd7:2; // 31:30 Reserved }; union GPFQSEL1_REG { Uint32 all; struct GPFQSEL1_BITS bit; }; struct GPFMUX1_BITS { // bits description Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 Uint16 rsvd1:2; // 19:18 Reserved Uint16 rsvd2:2; // 21:20 Reserved Uint16 rsvd3:2; // 23:22 Reserved Uint16 rsvd4:2; // 25:24 Reserved Uint16 rsvd5:2; // 27:26 Reserved Uint16 rsvd6:2; // 29:28 Reserved Uint16 rsvd7:2; // 31:30 Reserved }; union GPFMUX1_REG { Uint32 all; struct GPFMUX1_BITS bit; }; struct GPFDIR_BITS { // bits description Uint16 GPIO160:1; // 0 Defines direction for this pin in GPIO mode Uint16 GPIO161:1; // 1 Defines direction for this pin in GPIO mode Uint16 GPIO162:1; // 2 Defines direction for this pin in GPIO mode Uint16 GPIO163:1; // 3 Defines direction for this pin in GPIO mode Uint16 GPIO164:1; // 4 Defines direction for this pin in GPIO mode Uint16 GPIO165:1; // 5 Defines direction for this pin in GPIO mode Uint16 GPIO166:1; // 6 Defines direction for this pin in GPIO mode Uint16 GPIO167:1; // 7 Defines direction for this pin in GPIO mode Uint16 GPIO168:1; // 8 Defines direction for this pin in GPIO mode Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFDIR_REG { Uint32 all; struct GPFDIR_BITS bit; }; struct GPFPUD_BITS { // bits description Uint16 GPIO160:1; // 0 Pull-Up Disable control for this pin Uint16 GPIO161:1; // 1 Pull-Up Disable control for this pin Uint16 GPIO162:1; // 2 Pull-Up Disable control for this pin Uint16 GPIO163:1; // 3 Pull-Up Disable control for this pin Uint16 GPIO164:1; // 4 Pull-Up Disable control for this pin Uint16 GPIO165:1; // 5 Pull-Up Disable control for this pin Uint16 GPIO166:1; // 6 Pull-Up Disable control for this pin Uint16 GPIO167:1; // 7 Pull-Up Disable control for this pin Uint16 GPIO168:1; // 8 Pull-Up Disable control for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFPUD_REG { Uint32 all; struct GPFPUD_BITS bit; }; struct GPFINV_BITS { // bits description Uint16 GPIO160:1; // 0 Input inversion control for this pin Uint16 GPIO161:1; // 1 Input inversion control for this pin Uint16 GPIO162:1; // 2 Input inversion control for this pin Uint16 GPIO163:1; // 3 Input inversion control for this pin Uint16 GPIO164:1; // 4 Input inversion control for this pin Uint16 GPIO165:1; // 5 Input inversion control for this pin Uint16 GPIO166:1; // 6 Input inversion control for this pin Uint16 GPIO167:1; // 7 Input inversion control for this pin Uint16 GPIO168:1; // 8 Input inversion control for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFINV_REG { Uint32 all; struct GPFINV_BITS bit; }; struct GPFODR_BITS { // bits description Uint16 GPIO160:1; // 0 Outpout Open-Drain control for this pin Uint16 GPIO161:1; // 1 Outpout Open-Drain control for this pin Uint16 GPIO162:1; // 2 Outpout Open-Drain control for this pin Uint16 GPIO163:1; // 3 Outpout Open-Drain control for this pin Uint16 GPIO164:1; // 4 Outpout Open-Drain control for this pin Uint16 GPIO165:1; // 5 Outpout Open-Drain control for this pin Uint16 GPIO166:1; // 6 Outpout Open-Drain control for this pin Uint16 GPIO167:1; // 7 Outpout Open-Drain control for this pin Uint16 GPIO168:1; // 8 Outpout Open-Drain control for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFODR_REG { Uint32 all; struct GPFODR_BITS bit; }; struct GPFGMUX1_BITS { // bits description Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 Uint16 rsvd1:2; // 19:18 Reserved Uint16 rsvd2:2; // 21:20 Reserved Uint16 rsvd3:2; // 23:22 Reserved Uint16 rsvd4:2; // 25:24 Reserved Uint16 rsvd5:2; // 27:26 Reserved Uint16 rsvd6:2; // 29:28 Reserved Uint16 rsvd7:2; // 31:30 Reserved }; union GPFGMUX1_REG { Uint32 all; struct GPFGMUX1_BITS bit; }; struct GPFCSEL1_BITS { // bits description Uint16 GPIO160:4; // 3:0 GPIO160 Master CPU Select Uint16 GPIO161:4; // 7:4 GPIO161 Master CPU Select Uint16 GPIO162:4; // 11:8 GPIO162 Master CPU Select Uint16 GPIO163:4; // 15:12 GPIO163 Master CPU Select Uint16 GPIO164:4; // 19:16 GPIO164 Master CPU Select Uint16 GPIO165:4; // 23:20 GPIO165 Master CPU Select Uint16 GPIO166:4; // 27:24 GPIO166 Master CPU Select Uint16 GPIO167:4; // 31:28 GPIO167 Master CPU Select }; union GPFCSEL1_REG { Uint32 all; struct GPFCSEL1_BITS bit; }; struct GPFCSEL2_BITS { // bits description Uint16 GPIO168:4; // 3:0 GPIO168 Master CPU Select Uint16 rsvd1:4; // 7:4 Reserved Uint16 rsvd2:4; // 11:8 Reserved Uint16 rsvd3:4; // 15:12 Reserved Uint16 rsvd4:4; // 19:16 Reserved Uint16 rsvd5:4; // 23:20 Reserved Uint16 rsvd6:4; // 27:24 Reserved Uint16 rsvd7:4; // 31:28 Reserved }; union GPFCSEL2_REG { Uint32 all; struct GPFCSEL2_BITS bit; }; struct GPFLOCK_BITS { // bits description Uint16 GPIO160:1; // 0 Configuration Lock bit for this pin Uint16 GPIO161:1; // 1 Configuration Lock bit for this pin Uint16 GPIO162:1; // 2 Configuration Lock bit for this pin Uint16 GPIO163:1; // 3 Configuration Lock bit for this pin Uint16 GPIO164:1; // 4 Configuration Lock bit for this pin Uint16 GPIO165:1; // 5 Configuration Lock bit for this pin Uint16 GPIO166:1; // 6 Configuration Lock bit for this pin Uint16 GPIO167:1; // 7 Configuration Lock bit for this pin Uint16 GPIO168:1; // 8 Configuration Lock bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFLOCK_REG { Uint32 all; struct GPFLOCK_BITS bit; }; struct GPFCR_BITS { // bits description Uint16 GPIO160:1; // 0 Configuration lock commit bit for this pin Uint16 GPIO161:1; // 1 Configuration lock commit bit for this pin Uint16 GPIO162:1; // 2 Configuration lock commit bit for this pin Uint16 GPIO163:1; // 3 Configuration lock commit bit for this pin Uint16 GPIO164:1; // 4 Configuration lock commit bit for this pin Uint16 GPIO165:1; // 5 Configuration lock commit bit for this pin Uint16 GPIO166:1; // 6 Configuration lock commit bit for this pin Uint16 GPIO167:1; // 7 Configuration lock commit bit for this pin Uint16 GPIO168:1; // 8 Configuration lock commit bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFCR_REG { Uint32 all; struct GPFCR_BITS bit; }; struct GPIO_CTRL_REGS { union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period Control (GPIO0 to 31) union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) union GPAMUX1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) union GPAMUX2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) union GPADIR_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) union GPAPUD_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) Uint16 rsvd1[2]; // Reserved union GPAINV_REG GPAINV; // GPIO A Input Polarity Invert Registers (GPIO0 to 31) union GPAODR_REG GPAODR; // GPIO A Open Drain Output Register (GPIO0 to GPIO31) Uint16 rsvd2[12]; // Reserved union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to 15) union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to 31) Uint16 rsvd3[4]; // Reserved union GPACSEL1_REG GPACSEL1; // GPIO A Core Select Register (GPIO0 to 7) union GPACSEL2_REG GPACSEL2; // GPIO A Core Select Register (GPIO8 to 15) union GPACSEL3_REG GPACSEL3; // GPIO A Core Select Register (GPIO16 to 23) union GPACSEL4_REG GPACSEL4; // GPIO A Core Select Register (GPIO24 to 31) Uint16 rsvd4[12]; // Reserved union GPALOCK_REG GPALOCK; // GPIO A Lock Configuration Register (GPIO0 to 31) union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to 31) union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period Control (GPIO32 to 63) union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) union GPBMUX1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) union GPBMUX2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) union GPBDIR_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) Uint16 rsvd5[2]; // Reserved union GPBINV_REG GPBINV; // GPIO B Input Polarity Invert Registers (GPIO32 to 63) union GPBODR_REG GPBODR; // GPIO B Open Drain Output Register (GPIO32 to GPIO63) union GPBAMSEL_REG GPBAMSEL; // GPIO B Analog Mode Select register (GPIO32 to GPIO63) Uint16 rsvd6[10]; // Reserved union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to 47) union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to 63) Uint16 rsvd7[4]; // Reserved union GPBCSEL1_REG GPBCSEL1; // GPIO B Core Select Register (GPIO32 to 39) union GPBCSEL2_REG GPBCSEL2; // GPIO B Core Select Register (GPIO40 to 47) union GPBCSEL3_REG GPBCSEL3; // GPIO B Core Select Register (GPIO48 to 55) union GPBCSEL4_REG GPBCSEL4; // GPIO B Core Select Register (GPIO56 to 63) Uint16 rsvd8[12]; // Reserved union GPBLOCK_REG GPBLOCK; // GPIO B Lock Configuration Register (GPIO32 to 63) union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to 63) union GPCCTRL_REG GPCCTRL; // GPIO C Qualification Sampling Period Control (GPIO64 to 95) union GPCQSEL1_REG GPCQSEL1; // GPIO C Qualifier Select 1 Register (GPIO64 to 79) union GPCQSEL2_REG GPCQSEL2; // GPIO C Qualifier Select 2 Register (GPIO80 to 95) union GPCMUX1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) union GPCMUX2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) union GPCDIR_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) union GPCPUD_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) Uint16 rsvd9[2]; // Reserved union GPCINV_REG GPCINV; // GPIO C Input Polarity Invert Registers (GPIO64 to 95) union GPCODR_REG GPCODR; // GPIO C Open Drain Output Register (GPIO64 to GPIO95) Uint16 rsvd10[12]; // Reserved union GPCGMUX1_REG GPCGMUX1; // GPIO C Peripheral Group Mux (GPIO64 to 79) union GPCGMUX2_REG GPCGMUX2; // GPIO C Peripheral Group Mux (GPIO80 to 95) Uint16 rsvd11[4]; // Reserved union GPCCSEL1_REG GPCCSEL1; // GPIO C Core Select Register (GPIO64 to 71) union GPCCSEL2_REG GPCCSEL2; // GPIO C Core Select Register (GPIO72 to 79) union GPCCSEL3_REG GPCCSEL3; // GPIO C Core Select Register (GPIO80 to 87) union GPCCSEL4_REG GPCCSEL4; // GPIO C Core Select Register (GPIO88 to 95) Uint16 rsvd12[12]; // Reserved union GPCLOCK_REG GPCLOCK; // GPIO C Lock Configuration Register (GPIO64 to 95) union GPCCR_REG GPCCR; // GPIO C Lock Commit Register (GPIO64 to 95) union GPDCTRL_REG GPDCTRL; // GPIO D Qualification Sampling Period Control (GPIO96 to 127) union GPDQSEL1_REG GPDQSEL1; // GPIO D Qualifier Select 1 Register (GPIO96 to 111) union GPDQSEL2_REG GPDQSEL2; // GPIO D Qualifier Select 2 Register (GPIO112 to 127) union GPDMUX1_REG GPDMUX1; // GPIO D Mux 1 Register (GPIO96 to 111) union GPDMUX2_REG GPDMUX2; // GPIO D Mux 2 Register (GPIO112 to 127) union GPDDIR_REG GPDDIR; // GPIO D Direction Register (GPIO96 to 127) union GPDPUD_REG GPDPUD; // GPIO D Pull Up Disable Register (GPIO96 to 127) Uint16 rsvd13[2]; // Reserved union GPDINV_REG GPDINV; // GPIO D Input Polarity Invert Registers (GPIO96 to 127) union GPDODR_REG GPDODR; // GPIO D Open Drain Output Register (GPIO96 to GPIO127) Uint16 rsvd14[12]; // Reserved union GPDGMUX1_REG GPDGMUX1; // GPIO D Peripheral Group Mux (GPIO96 to 111) union GPDGMUX2_REG GPDGMUX2; // GPIO D Peripheral Group Mux (GPIO112 to 127) Uint16 rsvd15[4]; // Reserved union GPDCSEL1_REG GPDCSEL1; // GPIO D Core Select Register (GPIO96 to 103) union GPDCSEL2_REG GPDCSEL2; // GPIO D Core Select Register (GPIO104 to 111) union GPDCSEL3_REG GPDCSEL3; // GPIO D Core Select Register (GPIO112 to 119) union GPDCSEL4_REG GPDCSEL4; // GPIO D Core Select Register (GPIO120 to 127) Uint16 rsvd16[12]; // Reserved union GPDLOCK_REG GPDLOCK; // GPIO D Lock Configuration Register (GPIO96 to 127) union GPDCR_REG GPDCR; // GPIO D Lock Commit Register (GPIO96 to 127) union GPECTRL_REG GPECTRL; // GPIO E Qualification Sampling Period Control (GPIO128 to 159) union GPEQSEL1_REG GPEQSEL1; // GPIO E Qualifier Select 1 Register (GPIO128 to 143) union GPEQSEL2_REG GPEQSEL2; // GPIO E Qualifier Select 2 Register (GPIO144 to 159) union GPEMUX1_REG GPEMUX1; // GPIO E Mux 1 Register (GPIO128 to 143) union GPEMUX2_REG GPEMUX2; // GPIO E Mux 2 Register (GPIO144 to 159) union GPEDIR_REG GPEDIR; // GPIO E Direction Register (GPIO128 to 159) union GPEPUD_REG GPEPUD; // GPIO E Pull Up Disable Register (GPIO128 to 159) Uint16 rsvd17[2]; // Reserved union GPEINV_REG GPEINV; // GPIO E Input Polarity Invert Registers (GPIO128 to 159) union GPEODR_REG GPEODR; // GPIO E Open Drain Output Register (GPIO128 to GPIO159) Uint16 rsvd18[12]; // Reserved union GPEGMUX1_REG GPEGMUX1; // GPIO E Peripheral Group Mux (GPIO128 to 143) union GPEGMUX2_REG GPEGMUX2; // GPIO E Peripheral Group Mux (GPIO144 to 159) Uint16 rsvd19[4]; // Reserved union GPECSEL1_REG GPECSEL1; // GPIO E Core Select Register (GPIO128 to 135) union GPECSEL2_REG GPECSEL2; // GPIO E Core Select Register (GPIO136 to 143) union GPECSEL3_REG GPECSEL3; // GPIO E Core Select Register (GPIO144 to 151) union GPECSEL4_REG GPECSEL4; // GPIO E Core Select Register (GPIO152 to 159) Uint16 rsvd20[12]; // Reserved union GPELOCK_REG GPELOCK; // GPIO E Lock Configuration Register (GPIO128 to 159) union GPECR_REG GPECR; // GPIO E Lock Commit Register (GPIO128 to 159) union GPFCTRL_REG GPFCTRL; // GPIO F Qualification Sampling Period Control (GPIO160 to 168) union GPFQSEL1_REG GPFQSEL1; // GPIO F Qualifier Select 1 Register (GPIO160 to 168) Uint16 rsvd21[2]; // Reserved union GPFMUX1_REG GPFMUX1; // GPIO F Mux 1 Register (GPIO160 to 168) Uint16 rsvd22[2]; // Reserved union GPFDIR_REG GPFDIR; // GPIO F Direction Register (GPIO160 to 168) union GPFPUD_REG GPFPUD; // GPIO F Pull Up Disable Register (GPIO160 to 168) Uint16 rsvd23[2]; // Reserved union GPFINV_REG GPFINV; // GPIO F Input Polarity Invert Registers (GPIO160 to 168) union GPFODR_REG GPFODR; // GPIO F Open Drain Output Register (GPIO160 to GPIO168) Uint16 rsvd24[12]; // Reserved union GPFGMUX1_REG GPFGMUX1; // GPIO F Peripheral Group Mux (GPIO160 to 168) Uint16 rsvd25[6]; // Reserved union GPFCSEL1_REG GPFCSEL1; // GPIO F Core Select Register (GPIO160 to 167) union GPFCSEL2_REG GPFCSEL2; // GPIO F Core Select Register (GPIO168) Uint16 rsvd26[16]; // Reserved union GPFLOCK_REG GPFLOCK; // GPIO F Lock Configuration Register (GPIO160 to 168) union GPFCR_REG GPFCR; // GPIO F Lock Commit Register (GPIO160 to 168) }; struct GPADAT_BITS { // bits description Uint16 GPIO0:1; // 0 Data Register for this pin Uint16 GPIO1:1; // 1 Data Register for this pin Uint16 GPIO2:1; // 2 Data Register for this pin Uint16 GPIO3:1; // 3 Data Register for this pin Uint16 GPIO4:1; // 4 Data Register for this pin Uint16 GPIO5:1; // 5 Data Register for this pin Uint16 GPIO6:1; // 6 Data Register for this pin Uint16 GPIO7:1; // 7 Data Register for this pin Uint16 GPIO8:1; // 8 Data Register for this pin Uint16 GPIO9:1; // 9 Data Register for this pin Uint16 GPIO10:1; // 10 Data Register for this pin Uint16 GPIO11:1; // 11 Data Register for this pin Uint16 GPIO12:1; // 12 Data Register for this pin Uint16 GPIO13:1; // 13 Data Register for this pin Uint16 GPIO14:1; // 14 Data Register for this pin Uint16 GPIO15:1; // 15 Data Register for this pin Uint16 GPIO16:1; // 16 Data Register for this pin Uint16 GPIO17:1; // 17 Data Register for this pin Uint16 GPIO18:1; // 18 Data Register for this pin Uint16 GPIO19:1; // 19 Data Register for this pin Uint16 GPIO20:1; // 20 Data Register for this pin Uint16 GPIO21:1; // 21 Data Register for this pin Uint16 GPIO22:1; // 22 Data Register for this pin Uint16 GPIO23:1; // 23 Data Register for this pin Uint16 GPIO24:1; // 24 Data Register for this pin Uint16 GPIO25:1; // 25 Data Register for this pin Uint16 GPIO26:1; // 26 Data Register for this pin Uint16 GPIO27:1; // 27 Data Register for this pin Uint16 GPIO28:1; // 28 Data Register for this pin Uint16 GPIO29:1; // 29 Data Register for this pin Uint16 GPIO30:1; // 30 Data Register for this pin Uint16 GPIO31:1; // 31 Data Register for this pin }; union GPADAT_REG { Uint32 all; struct GPADAT_BITS bit; }; struct GPASET_BITS { // bits description Uint16 GPIO0:1; // 0 Output Set bit for this pin Uint16 GPIO1:1; // 1 Output Set bit for this pin Uint16 GPIO2:1; // 2 Output Set bit for this pin Uint16 GPIO3:1; // 3 Output Set bit for this pin Uint16 GPIO4:1; // 4 Output Set bit for this pin Uint16 GPIO5:1; // 5 Output Set bit for this pin Uint16 GPIO6:1; // 6 Output Set bit for this pin Uint16 GPIO7:1; // 7 Output Set bit for this pin Uint16 GPIO8:1; // 8 Output Set bit for this pin Uint16 GPIO9:1; // 9 Output Set bit for this pin Uint16 GPIO10:1; // 10 Output Set bit for this pin Uint16 GPIO11:1; // 11 Output Set bit for this pin Uint16 GPIO12:1; // 12 Output Set bit for this pin Uint16 GPIO13:1; // 13 Output Set bit for this pin Uint16 GPIO14:1; // 14 Output Set bit for this pin Uint16 GPIO15:1; // 15 Output Set bit for this pin Uint16 GPIO16:1; // 16 Output Set bit for this pin Uint16 GPIO17:1; // 17 Output Set bit for this pin Uint16 GPIO18:1; // 18 Output Set bit for this pin Uint16 GPIO19:1; // 19 Output Set bit for this pin Uint16 GPIO20:1; // 20 Output Set bit for this pin Uint16 GPIO21:1; // 21 Output Set bit for this pin Uint16 GPIO22:1; // 22 Output Set bit for this pin Uint16 GPIO23:1; // 23 Output Set bit for this pin Uint16 GPIO24:1; // 24 Output Set bit for this pin Uint16 GPIO25:1; // 25 Output Set bit for this pin Uint16 GPIO26:1; // 26 Output Set bit for this pin Uint16 GPIO27:1; // 27 Output Set bit for this pin Uint16 GPIO28:1; // 28 Output Set bit for this pin Uint16 GPIO29:1; // 29 Output Set bit for this pin Uint16 GPIO30:1; // 30 Output Set bit for this pin Uint16 GPIO31:1; // 31 Output Set bit for this pin }; union GPASET_REG { Uint32 all; struct GPASET_BITS bit; }; struct GPACLEAR_BITS { // bits description Uint16 GPIO0:1; // 0 Output Clear bit for this pin Uint16 GPIO1:1; // 1 Output Clear bit for this pin Uint16 GPIO2:1; // 2 Output Clear bit for this pin Uint16 GPIO3:1; // 3 Output Clear bit for this pin Uint16 GPIO4:1; // 4 Output Clear bit for this pin Uint16 GPIO5:1; // 5 Output Clear bit for this pin Uint16 GPIO6:1; // 6 Output Clear bit for this pin Uint16 GPIO7:1; // 7 Output Clear bit for this pin Uint16 GPIO8:1; // 8 Output Clear bit for this pin Uint16 GPIO9:1; // 9 Output Clear bit for this pin Uint16 GPIO10:1; // 10 Output Clear bit for this pin Uint16 GPIO11:1; // 11 Output Clear bit for this pin Uint16 GPIO12:1; // 12 Output Clear bit for this pin Uint16 GPIO13:1; // 13 Output Clear bit for this pin Uint16 GPIO14:1; // 14 Output Clear bit for this pin Uint16 GPIO15:1; // 15 Output Clear bit for this pin Uint16 GPIO16:1; // 16 Output Clear bit for this pin Uint16 GPIO17:1; // 17 Output Clear bit for this pin Uint16 GPIO18:1; // 18 Output Clear bit for this pin Uint16 GPIO19:1; // 19 Output Clear bit for this pin Uint16 GPIO20:1; // 20 Output Clear bit for this pin Uint16 GPIO21:1; // 21 Output Clear bit for this pin Uint16 GPIO22:1; // 22 Output Clear bit for this pin Uint16 GPIO23:1; // 23 Output Clear bit for this pin Uint16 GPIO24:1; // 24 Output Clear bit for this pin Uint16 GPIO25:1; // 25 Output Clear bit for this pin Uint16 GPIO26:1; // 26 Output Clear bit for this pin Uint16 GPIO27:1; // 27 Output Clear bit for this pin Uint16 GPIO28:1; // 28 Output Clear bit for this pin Uint16 GPIO29:1; // 29 Output Clear bit for this pin Uint16 GPIO30:1; // 30 Output Clear bit for this pin Uint16 GPIO31:1; // 31 Output Clear bit for this pin }; union GPACLEAR_REG { Uint32 all; struct GPACLEAR_BITS bit; }; struct GPATOGGLE_BITS { // bits description Uint16 GPIO0:1; // 0 Output Toggle bit for this pin Uint16 GPIO1:1; // 1 Output Toggle bit for this pin Uint16 GPIO2:1; // 2 Output Toggle bit for this pin Uint16 GPIO3:1; // 3 Output Toggle bit for this pin Uint16 GPIO4:1; // 4 Output Toggle bit for this pin Uint16 GPIO5:1; // 5 Output Toggle bit for this pin Uint16 GPIO6:1; // 6 Output Toggle bit for this pin Uint16 GPIO7:1; // 7 Output Toggle bit for this pin Uint16 GPIO8:1; // 8 Output Toggle bit for this pin Uint16 GPIO9:1; // 9 Output Toggle bit for this pin Uint16 GPIO10:1; // 10 Output Toggle bit for this pin Uint16 GPIO11:1; // 11 Output Toggle bit for this pin Uint16 GPIO12:1; // 12 Output Toggle bit for this pin Uint16 GPIO13:1; // 13 Output Toggle bit for this pin Uint16 GPIO14:1; // 14 Output Toggle bit for this pin Uint16 GPIO15:1; // 15 Output Toggle bit for this pin Uint16 GPIO16:1; // 16 Output Toggle bit for this pin Uint16 GPIO17:1; // 17 Output Toggle bit for this pin Uint16 GPIO18:1; // 18 Output Toggle bit for this pin Uint16 GPIO19:1; // 19 Output Toggle bit for this pin Uint16 GPIO20:1; // 20 Output Toggle bit for this pin Uint16 GPIO21:1; // 21 Output Toggle bit for this pin Uint16 GPIO22:1; // 22 Output Toggle bit for this pin Uint16 GPIO23:1; // 23 Output Toggle bit for this pin Uint16 GPIO24:1; // 24 Output Toggle bit for this pin Uint16 GPIO25:1; // 25 Output Toggle bit for this pin Uint16 GPIO26:1; // 26 Output Toggle bit for this pin Uint16 GPIO27:1; // 27 Output Toggle bit for this pin Uint16 GPIO28:1; // 28 Output Toggle bit for this pin Uint16 GPIO29:1; // 29 Output Toggle bit for this pin Uint16 GPIO30:1; // 30 Output Toggle bit for this pin Uint16 GPIO31:1; // 31 Output Toggle bit for this pin }; union GPATOGGLE_REG { Uint32 all; struct GPATOGGLE_BITS bit; }; struct GPBDAT_BITS { // bits description Uint16 GPIO32:1; // 0 Data Register for this pin Uint16 GPIO33:1; // 1 Data Register for this pin Uint16 GPIO34:1; // 2 Data Register for this pin Uint16 GPIO35:1; // 3 Data Register for this pin Uint16 GPIO36:1; // 4 Data Register for this pin Uint16 GPIO37:1; // 5 Data Register for this pin Uint16 GPIO38:1; // 6 Data Register for this pin Uint16 GPIO39:1; // 7 Data Register for this pin Uint16 GPIO40:1; // 8 Data Register for this pin Uint16 GPIO41:1; // 9 Data Register for this pin Uint16 GPIO42:1; // 10 Data Register for this pin Uint16 GPIO43:1; // 11 Data Register for this pin Uint16 GPIO44:1; // 12 Data Register for this pin Uint16 GPIO45:1; // 13 Data Register for this pin Uint16 GPIO46:1; // 14 Data Register for this pin Uint16 GPIO47:1; // 15 Data Register for this pin Uint16 GPIO48:1; // 16 Data Register for this pin Uint16 GPIO49:1; // 17 Data Register for this pin Uint16 GPIO50:1; // 18 Data Register for this pin Uint16 GPIO51:1; // 19 Data Register for this pin Uint16 GPIO52:1; // 20 Data Register for this pin Uint16 GPIO53:1; // 21 Data Register for this pin Uint16 GPIO54:1; // 22 Data Register for this pin Uint16 GPIO55:1; // 23 Data Register for this pin Uint16 GPIO56:1; // 24 Data Register for this pin Uint16 GPIO57:1; // 25 Data Register for this pin Uint16 GPIO58:1; // 26 Data Register for this pin Uint16 GPIO59:1; // 27 Data Register for this pin Uint16 GPIO60:1; // 28 Data Register for this pin Uint16 GPIO61:1; // 29 Data Register for this pin Uint16 GPIO62:1; // 30 Data Register for this pin Uint16 GPIO63:1; // 31 Data Register for this pin }; union GPBDAT_REG { Uint32 all; struct GPBDAT_BITS bit; }; struct GPBSET_BITS { // bits description Uint16 GPIO32:1; // 0 Output Set bit for this pin Uint16 GPIO33:1; // 1 Output Set bit for this pin Uint16 GPIO34:1; // 2 Output Set bit for this pin Uint16 GPIO35:1; // 3 Output Set bit for this pin Uint16 GPIO36:1; // 4 Output Set bit for this pin Uint16 GPIO37:1; // 5 Output Set bit for this pin Uint16 GPIO38:1; // 6 Output Set bit for this pin Uint16 GPIO39:1; // 7 Output Set bit for this pin Uint16 GPIO40:1; // 8 Output Set bit for this pin Uint16 GPIO41:1; // 9 Output Set bit for this pin Uint16 GPIO42:1; // 10 Output Set bit for this pin Uint16 GPIO43:1; // 11 Output Set bit for this pin Uint16 GPIO44:1; // 12 Output Set bit for this pin Uint16 GPIO45:1; // 13 Output Set bit for this pin Uint16 GPIO46:1; // 14 Output Set bit for this pin Uint16 GPIO47:1; // 15 Output Set bit for this pin Uint16 GPIO48:1; // 16 Output Set bit for this pin Uint16 GPIO49:1; // 17 Output Set bit for this pin Uint16 GPIO50:1; // 18 Output Set bit for this pin Uint16 GPIO51:1; // 19 Output Set bit for this pin Uint16 GPIO52:1; // 20 Output Set bit for this pin Uint16 GPIO53:1; // 21 Output Set bit for this pin Uint16 GPIO54:1; // 22 Output Set bit for this pin Uint16 GPIO55:1; // 23 Output Set bit for this pin Uint16 GPIO56:1; // 24 Output Set bit for this pin Uint16 GPIO57:1; // 25 Output Set bit for this pin Uint16 GPIO58:1; // 26 Output Set bit for this pin Uint16 GPIO59:1; // 27 Output Set bit for this pin Uint16 GPIO60:1; // 28 Output Set bit for this pin Uint16 GPIO61:1; // 29 Output Set bit for this pin Uint16 GPIO62:1; // 30 Output Set bit for this pin Uint16 GPIO63:1; // 31 Output Set bit for this pin }; union GPBSET_REG { Uint32 all; struct GPBSET_BITS bit; }; struct GPBCLEAR_BITS { // bits description Uint16 GPIO32:1; // 0 Output Clear bit for this pin Uint16 GPIO33:1; // 1 Output Clear bit for this pin Uint16 GPIO34:1; // 2 Output Clear bit for this pin Uint16 GPIO35:1; // 3 Output Clear bit for this pin Uint16 GPIO36:1; // 4 Output Clear bit for this pin Uint16 GPIO37:1; // 5 Output Clear bit for this pin Uint16 GPIO38:1; // 6 Output Clear bit for this pin Uint16 GPIO39:1; // 7 Output Clear bit for this pin Uint16 GPIO40:1; // 8 Output Clear bit for this pin Uint16 GPIO41:1; // 9 Output Clear bit for this pin Uint16 GPIO42:1; // 10 Output Clear bit for this pin Uint16 GPIO43:1; // 11 Output Clear bit for this pin Uint16 GPIO44:1; // 12 Output Clear bit for this pin Uint16 GPIO45:1; // 13 Output Clear bit for this pin Uint16 GPIO46:1; // 14 Output Clear bit for this pin Uint16 GPIO47:1; // 15 Output Clear bit for this pin Uint16 GPIO48:1; // 16 Output Clear bit for this pin Uint16 GPIO49:1; // 17 Output Clear bit for this pin Uint16 GPIO50:1; // 18 Output Clear bit for this pin Uint16 GPIO51:1; // 19 Output Clear bit for this pin Uint16 GPIO52:1; // 20 Output Clear bit for this pin Uint16 GPIO53:1; // 21 Output Clear bit for this pin Uint16 GPIO54:1; // 22 Output Clear bit for this pin Uint16 GPIO55:1; // 23 Output Clear bit for this pin Uint16 GPIO56:1; // 24 Output Clear bit for this pin Uint16 GPIO57:1; // 25 Output Clear bit for this pin Uint16 GPIO58:1; // 26 Output Clear bit for this pin Uint16 GPIO59:1; // 27 Output Clear bit for this pin Uint16 GPIO60:1; // 28 Output Clear bit for this pin Uint16 GPIO61:1; // 29 Output Clear bit for this pin Uint16 GPIO62:1; // 30 Output Clear bit for this pin Uint16 GPIO63:1; // 31 Output Clear bit for this pin }; union GPBCLEAR_REG { Uint32 all; struct GPBCLEAR_BITS bit; }; struct GPBTOGGLE_BITS { // bits description Uint16 GPIO32:1; // 0 Output Toggle bit for this pin Uint16 GPIO33:1; // 1 Output Toggle bit for this pin Uint16 GPIO34:1; // 2 Output Toggle bit for this pin Uint16 GPIO35:1; // 3 Output Toggle bit for this pin Uint16 GPIO36:1; // 4 Output Toggle bit for this pin Uint16 GPIO37:1; // 5 Output Toggle bit for this pin Uint16 GPIO38:1; // 6 Output Toggle bit for this pin Uint16 GPIO39:1; // 7 Output Toggle bit for this pin Uint16 GPIO40:1; // 8 Output Toggle bit for this pin Uint16 GPIO41:1; // 9 Output Toggle bit for this pin Uint16 GPIO42:1; // 10 Output Toggle bit for this pin Uint16 GPIO43:1; // 11 Output Toggle bit for this pin Uint16 GPIO44:1; // 12 Output Toggle bit for this pin Uint16 GPIO45:1; // 13 Output Toggle bit for this pin Uint16 GPIO46:1; // 14 Output Toggle bit for this pin Uint16 GPIO47:1; // 15 Output Toggle bit for this pin Uint16 GPIO48:1; // 16 Output Toggle bit for this pin Uint16 GPIO49:1; // 17 Output Toggle bit for this pin Uint16 GPIO50:1; // 18 Output Toggle bit for this pin Uint16 GPIO51:1; // 19 Output Toggle bit for this pin Uint16 GPIO52:1; // 20 Output Toggle bit for this pin Uint16 GPIO53:1; // 21 Output Toggle bit for this pin Uint16 GPIO54:1; // 22 Output Toggle bit for this pin Uint16 GPIO55:1; // 23 Output Toggle bit for this pin Uint16 GPIO56:1; // 24 Output Toggle bit for this pin Uint16 GPIO57:1; // 25 Output Toggle bit for this pin Uint16 GPIO58:1; // 26 Output Toggle bit for this pin Uint16 GPIO59:1; // 27 Output Toggle bit for this pin Uint16 GPIO60:1; // 28 Output Toggle bit for this pin Uint16 GPIO61:1; // 29 Output Toggle bit for this pin Uint16 GPIO62:1; // 30 Output Toggle bit for this pin Uint16 GPIO63:1; // 31 Output Toggle bit for this pin }; union GPBTOGGLE_REG { Uint32 all; struct GPBTOGGLE_BITS bit; }; struct GPCDAT_BITS { // bits description Uint16 GPIO64:1; // 0 Data Register for this pin Uint16 GPIO65:1; // 1 Data Register for this pin Uint16 GPIO66:1; // 2 Data Register for this pin Uint16 GPIO67:1; // 3 Data Register for this pin Uint16 GPIO68:1; // 4 Data Register for this pin Uint16 GPIO69:1; // 5 Data Register for this pin Uint16 GPIO70:1; // 6 Data Register for this pin Uint16 GPIO71:1; // 7 Data Register for this pin Uint16 GPIO72:1; // 8 Data Register for this pin Uint16 GPIO73:1; // 9 Data Register for this pin Uint16 GPIO74:1; // 10 Data Register for this pin Uint16 GPIO75:1; // 11 Data Register for this pin Uint16 GPIO76:1; // 12 Data Register for this pin Uint16 GPIO77:1; // 13 Data Register for this pin Uint16 GPIO78:1; // 14 Data Register for this pin Uint16 GPIO79:1; // 15 Data Register for this pin Uint16 GPIO80:1; // 16 Data Register for this pin Uint16 GPIO81:1; // 17 Data Register for this pin Uint16 GPIO82:1; // 18 Data Register for this pin Uint16 GPIO83:1; // 19 Data Register for this pin Uint16 GPIO84:1; // 20 Data Register for this pin Uint16 GPIO85:1; // 21 Data Register for this pin Uint16 GPIO86:1; // 22 Data Register for this pin Uint16 GPIO87:1; // 23 Data Register for this pin Uint16 GPIO88:1; // 24 Data Register for this pin Uint16 GPIO89:1; // 25 Data Register for this pin Uint16 GPIO90:1; // 26 Data Register for this pin Uint16 GPIO91:1; // 27 Data Register for this pin Uint16 GPIO92:1; // 28 Data Register for this pin Uint16 GPIO93:1; // 29 Data Register for this pin Uint16 GPIO94:1; // 30 Data Register for this pin Uint16 GPIO95:1; // 31 Data Register for this pin }; union GPCDAT_REG { Uint32 all; struct GPCDAT_BITS bit; }; struct GPCSET_BITS { // bits description Uint16 GPIO64:1; // 0 Output Set bit for this pin Uint16 GPIO65:1; // 1 Output Set bit for this pin Uint16 GPIO66:1; // 2 Output Set bit for this pin Uint16 GPIO67:1; // 3 Output Set bit for this pin Uint16 GPIO68:1; // 4 Output Set bit for this pin Uint16 GPIO69:1; // 5 Output Set bit for this pin Uint16 GPIO70:1; // 6 Output Set bit for this pin Uint16 GPIO71:1; // 7 Output Set bit for this pin Uint16 GPIO72:1; // 8 Output Set bit for this pin Uint16 GPIO73:1; // 9 Output Set bit for this pin Uint16 GPIO74:1; // 10 Output Set bit for this pin Uint16 GPIO75:1; // 11 Output Set bit for this pin Uint16 GPIO76:1; // 12 Output Set bit for this pin Uint16 GPIO77:1; // 13 Output Set bit for this pin Uint16 GPIO78:1; // 14 Output Set bit for this pin Uint16 GPIO79:1; // 15 Output Set bit for this pin Uint16 GPIO80:1; // 16 Output Set bit for this pin Uint16 GPIO81:1; // 17 Output Set bit for this pin Uint16 GPIO82:1; // 18 Output Set bit for this pin Uint16 GPIO83:1; // 19 Output Set bit for this pin Uint16 GPIO84:1; // 20 Output Set bit for this pin Uint16 GPIO85:1; // 21 Output Set bit for this pin Uint16 GPIO86:1; // 22 Output Set bit for this pin Uint16 GPIO87:1; // 23 Output Set bit for this pin Uint16 GPIO88:1; // 24 Output Set bit for this pin Uint16 GPIO89:1; // 25 Output Set bit for this pin Uint16 GPIO90:1; // 26 Output Set bit for this pin Uint16 GPIO91:1; // 27 Output Set bit for this pin Uint16 GPIO92:1; // 28 Output Set bit for this pin Uint16 GPIO93:1; // 29 Output Set bit for this pin Uint16 GPIO94:1; // 30 Output Set bit for this pin Uint16 GPIO95:1; // 31 Output Set bit for this pin }; union GPCSET_REG { Uint32 all; struct GPCSET_BITS bit; }; struct GPCCLEAR_BITS { // bits description Uint16 GPIO64:1; // 0 Output Clear bit for this pin Uint16 GPIO65:1; // 1 Output Clear bit for this pin Uint16 GPIO66:1; // 2 Output Clear bit for this pin Uint16 GPIO67:1; // 3 Output Clear bit for this pin Uint16 GPIO68:1; // 4 Output Clear bit for this pin Uint16 GPIO69:1; // 5 Output Clear bit for this pin Uint16 GPIO70:1; // 6 Output Clear bit for this pin Uint16 GPIO71:1; // 7 Output Clear bit for this pin Uint16 GPIO72:1; // 8 Output Clear bit for this pin Uint16 GPIO73:1; // 9 Output Clear bit for this pin Uint16 GPIO74:1; // 10 Output Clear bit for this pin Uint16 GPIO75:1; // 11 Output Clear bit for this pin Uint16 GPIO76:1; // 12 Output Clear bit for this pin Uint16 GPIO77:1; // 13 Output Clear bit for this pin Uint16 GPIO78:1; // 14 Output Clear bit for this pin Uint16 GPIO79:1; // 15 Output Clear bit for this pin Uint16 GPIO80:1; // 16 Output Clear bit for this pin Uint16 GPIO81:1; // 17 Output Clear bit for this pin Uint16 GPIO82:1; // 18 Output Clear bit for this pin Uint16 GPIO83:1; // 19 Output Clear bit for this pin Uint16 GPIO84:1; // 20 Output Clear bit for this pin Uint16 GPIO85:1; // 21 Output Clear bit for this pin Uint16 GPIO86:1; // 22 Output Clear bit for this pin Uint16 GPIO87:1; // 23 Output Clear bit for this pin Uint16 GPIO88:1; // 24 Output Clear bit for this pin Uint16 GPIO89:1; // 25 Output Clear bit for this pin Uint16 GPIO90:1; // 26 Output Clear bit for this pin Uint16 GPIO91:1; // 27 Output Clear bit for this pin Uint16 GPIO92:1; // 28 Output Clear bit for this pin Uint16 GPIO93:1; // 29 Output Clear bit for this pin Uint16 GPIO94:1; // 30 Output Clear bit for this pin Uint16 GPIO95:1; // 31 Output Clear bit for this pin }; union GPCCLEAR_REG { Uint32 all; struct GPCCLEAR_BITS bit; }; struct GPCTOGGLE_BITS { // bits description Uint16 GPIO64:1; // 0 Output Toggle bit for this pin Uint16 GPIO65:1; // 1 Output Toggle bit for this pin Uint16 GPIO66:1; // 2 Output Toggle bit for this pin Uint16 GPIO67:1; // 3 Output Toggle bit for this pin Uint16 GPIO68:1; // 4 Output Toggle bit for this pin Uint16 GPIO69:1; // 5 Output Toggle bit for this pin Uint16 GPIO70:1; // 6 Output Toggle bit for this pin Uint16 GPIO71:1; // 7 Output Toggle bit for this pin Uint16 GPIO72:1; // 8 Output Toggle bit for this pin Uint16 GPIO73:1; // 9 Output Toggle bit for this pin Uint16 GPIO74:1; // 10 Output Toggle bit for this pin Uint16 GPIO75:1; // 11 Output Toggle bit for this pin Uint16 GPIO76:1; // 12 Output Toggle bit for this pin Uint16 GPIO77:1; // 13 Output Toggle bit for this pin Uint16 GPIO78:1; // 14 Output Toggle bit for this pin Uint16 GPIO79:1; // 15 Output Toggle bit for this pin Uint16 GPIO80:1; // 16 Output Toggle bit for this pin Uint16 GPIO81:1; // 17 Output Toggle bit for this pin Uint16 GPIO82:1; // 18 Output Toggle bit for this pin Uint16 GPIO83:1; // 19 Output Toggle bit for this pin Uint16 GPIO84:1; // 20 Output Toggle bit for this pin Uint16 GPIO85:1; // 21 Output Toggle bit for this pin Uint16 GPIO86:1; // 22 Output Toggle bit for this pin Uint16 GPIO87:1; // 23 Output Toggle bit for this pin Uint16 GPIO88:1; // 24 Output Toggle bit for this pin Uint16 GPIO89:1; // 25 Output Toggle bit for this pin Uint16 GPIO90:1; // 26 Output Toggle bit for this pin Uint16 GPIO91:1; // 27 Output Toggle bit for this pin Uint16 GPIO92:1; // 28 Output Toggle bit for this pin Uint16 GPIO93:1; // 29 Output Toggle bit for this pin Uint16 GPIO94:1; // 30 Output Toggle bit for this pin Uint16 GPIO95:1; // 31 Output Toggle bit for this pin }; union GPCTOGGLE_REG { Uint32 all; struct GPCTOGGLE_BITS bit; }; struct GPDDAT_BITS { // bits description Uint16 GPIO96:1; // 0 Data Register for this pin Uint16 GPIO97:1; // 1 Data Register for this pin Uint16 GPIO98:1; // 2 Data Register for this pin Uint16 GPIO99:1; // 3 Data Register for this pin Uint16 GPIO100:1; // 4 Data Register for this pin Uint16 GPIO101:1; // 5 Data Register for this pin Uint16 GPIO102:1; // 6 Data Register for this pin Uint16 GPIO103:1; // 7 Data Register for this pin Uint16 GPIO104:1; // 8 Data Register for this pin Uint16 GPIO105:1; // 9 Data Register for this pin Uint16 GPIO106:1; // 10 Data Register for this pin Uint16 GPIO107:1; // 11 Data Register for this pin Uint16 GPIO108:1; // 12 Data Register for this pin Uint16 GPIO109:1; // 13 Data Register for this pin Uint16 GPIO110:1; // 14 Data Register for this pin Uint16 GPIO111:1; // 15 Data Register for this pin Uint16 GPIO112:1; // 16 Data Register for this pin Uint16 GPIO113:1; // 17 Data Register for this pin Uint16 GPIO114:1; // 18 Data Register for this pin Uint16 GPIO115:1; // 19 Data Register for this pin Uint16 GPIO116:1; // 20 Data Register for this pin Uint16 GPIO117:1; // 21 Data Register for this pin Uint16 GPIO118:1; // 22 Data Register for this pin Uint16 GPIO119:1; // 23 Data Register for this pin Uint16 GPIO120:1; // 24 Data Register for this pin Uint16 GPIO121:1; // 25 Data Register for this pin Uint16 GPIO122:1; // 26 Data Register for this pin Uint16 GPIO123:1; // 27 Data Register for this pin Uint16 GPIO124:1; // 28 Data Register for this pin Uint16 GPIO125:1; // 29 Data Register for this pin Uint16 GPIO126:1; // 30 Data Register for this pin Uint16 GPIO127:1; // 31 Data Register for this pin }; union GPDDAT_REG { Uint32 all; struct GPDDAT_BITS bit; }; struct GPDSET_BITS { // bits description Uint16 GPIO96:1; // 0 Output Set bit for this pin Uint16 GPIO97:1; // 1 Output Set bit for this pin Uint16 GPIO98:1; // 2 Output Set bit for this pin Uint16 GPIO99:1; // 3 Output Set bit for this pin Uint16 GPIO100:1; // 4 Output Set bit for this pin Uint16 GPIO101:1; // 5 Output Set bit for this pin Uint16 GPIO102:1; // 6 Output Set bit for this pin Uint16 GPIO103:1; // 7 Output Set bit for this pin Uint16 GPIO104:1; // 8 Output Set bit for this pin Uint16 GPIO105:1; // 9 Output Set bit for this pin Uint16 GPIO106:1; // 10 Output Set bit for this pin Uint16 GPIO107:1; // 11 Output Set bit for this pin Uint16 GPIO108:1; // 12 Output Set bit for this pin Uint16 GPIO109:1; // 13 Output Set bit for this pin Uint16 GPIO110:1; // 14 Output Set bit for this pin Uint16 GPIO111:1; // 15 Output Set bit for this pin Uint16 GPIO112:1; // 16 Output Set bit for this pin Uint16 GPIO113:1; // 17 Output Set bit for this pin Uint16 GPIO114:1; // 18 Output Set bit for this pin Uint16 GPIO115:1; // 19 Output Set bit for this pin Uint16 GPIO116:1; // 20 Output Set bit for this pin Uint16 GPIO117:1; // 21 Output Set bit for this pin Uint16 GPIO118:1; // 22 Output Set bit for this pin Uint16 GPIO119:1; // 23 Output Set bit for this pin Uint16 GPIO120:1; // 24 Output Set bit for this pin Uint16 GPIO121:1; // 25 Output Set bit for this pin Uint16 GPIO122:1; // 26 Output Set bit for this pin Uint16 GPIO123:1; // 27 Output Set bit for this pin Uint16 GPIO124:1; // 28 Output Set bit for this pin Uint16 GPIO125:1; // 29 Output Set bit for this pin Uint16 GPIO126:1; // 30 Output Set bit for this pin Uint16 GPIO127:1; // 31 Output Set bit for this pin }; union GPDSET_REG { Uint32 all; struct GPDSET_BITS bit; }; struct GPDCLEAR_BITS { // bits description Uint16 GPIO96:1; // 0 Output Clear bit for this pin Uint16 GPIO97:1; // 1 Output Clear bit for this pin Uint16 GPIO98:1; // 2 Output Clear bit for this pin Uint16 GPIO99:1; // 3 Output Clear bit for this pin Uint16 GPIO100:1; // 4 Output Clear bit for this pin Uint16 GPIO101:1; // 5 Output Clear bit for this pin Uint16 GPIO102:1; // 6 Output Clear bit for this pin Uint16 GPIO103:1; // 7 Output Clear bit for this pin Uint16 GPIO104:1; // 8 Output Clear bit for this pin Uint16 GPIO105:1; // 9 Output Clear bit for this pin Uint16 GPIO106:1; // 10 Output Clear bit for this pin Uint16 GPIO107:1; // 11 Output Clear bit for this pin Uint16 GPIO108:1; // 12 Output Clear bit for this pin Uint16 GPIO109:1; // 13 Output Clear bit for this pin Uint16 GPIO110:1; // 14 Output Clear bit for this pin Uint16 GPIO111:1; // 15 Output Clear bit for this pin Uint16 GPIO112:1; // 16 Output Clear bit for this pin Uint16 GPIO113:1; // 17 Output Clear bit for this pin Uint16 GPIO114:1; // 18 Output Clear bit for this pin Uint16 GPIO115:1; // 19 Output Clear bit for this pin Uint16 GPIO116:1; // 20 Output Clear bit for this pin Uint16 GPIO117:1; // 21 Output Clear bit for this pin Uint16 GPIO118:1; // 22 Output Clear bit for this pin Uint16 GPIO119:1; // 23 Output Clear bit for this pin Uint16 GPIO120:1; // 24 Output Clear bit for this pin Uint16 GPIO121:1; // 25 Output Clear bit for this pin Uint16 GPIO122:1; // 26 Output Clear bit for this pin Uint16 GPIO123:1; // 27 Output Clear bit for this pin Uint16 GPIO124:1; // 28 Output Clear bit for this pin Uint16 GPIO125:1; // 29 Output Clear bit for this pin Uint16 GPIO126:1; // 30 Output Clear bit for this pin Uint16 GPIO127:1; // 31 Output Clear bit for this pin }; union GPDCLEAR_REG { Uint32 all; struct GPDCLEAR_BITS bit; }; struct GPDTOGGLE_BITS { // bits description Uint16 GPIO96:1; // 0 Output Toggle bit for this pin Uint16 GPIO97:1; // 1 Output Toggle bit for this pin Uint16 GPIO98:1; // 2 Output Toggle bit for this pin Uint16 GPIO99:1; // 3 Output Toggle bit for this pin Uint16 GPIO100:1; // 4 Output Toggle bit for this pin Uint16 GPIO101:1; // 5 Output Toggle bit for this pin Uint16 GPIO102:1; // 6 Output Toggle bit for this pin Uint16 GPIO103:1; // 7 Output Toggle bit for this pin Uint16 GPIO104:1; // 8 Output Toggle bit for this pin Uint16 GPIO105:1; // 9 Output Toggle bit for this pin Uint16 GPIO106:1; // 10 Output Toggle bit for this pin Uint16 GPIO107:1; // 11 Output Toggle bit for this pin Uint16 GPIO108:1; // 12 Output Toggle bit for this pin Uint16 GPIO109:1; // 13 Output Toggle bit for this pin Uint16 GPIO110:1; // 14 Output Toggle bit for this pin Uint16 GPIO111:1; // 15 Output Toggle bit for this pin Uint16 GPIO112:1; // 16 Output Toggle bit for this pin Uint16 GPIO113:1; // 17 Output Toggle bit for this pin Uint16 GPIO114:1; // 18 Output Toggle bit for this pin Uint16 GPIO115:1; // 19 Output Toggle bit for this pin Uint16 GPIO116:1; // 20 Output Toggle bit for this pin Uint16 GPIO117:1; // 21 Output Toggle bit for this pin Uint16 GPIO118:1; // 22 Output Toggle bit for this pin Uint16 GPIO119:1; // 23 Output Toggle bit for this pin Uint16 GPIO120:1; // 24 Output Toggle bit for this pin Uint16 GPIO121:1; // 25 Output Toggle bit for this pin Uint16 GPIO122:1; // 26 Output Toggle bit for this pin Uint16 GPIO123:1; // 27 Output Toggle bit for this pin Uint16 GPIO124:1; // 28 Output Toggle bit for this pin Uint16 GPIO125:1; // 29 Output Toggle bit for this pin Uint16 GPIO126:1; // 30 Output Toggle bit for this pin Uint16 GPIO127:1; // 31 Output Toggle bit for this pin }; union GPDTOGGLE_REG { Uint32 all; struct GPDTOGGLE_BITS bit; }; struct GPEDAT_BITS { // bits description Uint16 GPIO128:1; // 0 Data Register for this pin Uint16 GPIO129:1; // 1 Data Register for this pin Uint16 GPIO130:1; // 2 Data Register for this pin Uint16 GPIO131:1; // 3 Data Register for this pin Uint16 GPIO132:1; // 4 Data Register for this pin Uint16 GPIO133:1; // 5 Data Register for this pin Uint16 GPIO134:1; // 6 Data Register for this pin Uint16 GPIO135:1; // 7 Data Register for this pin Uint16 GPIO136:1; // 8 Data Register for this pin Uint16 GPIO137:1; // 9 Data Register for this pin Uint16 GPIO138:1; // 10 Data Register for this pin Uint16 GPIO139:1; // 11 Data Register for this pin Uint16 GPIO140:1; // 12 Data Register for this pin Uint16 GPIO141:1; // 13 Data Register for this pin Uint16 GPIO142:1; // 14 Data Register for this pin Uint16 GPIO143:1; // 15 Data Register for this pin Uint16 GPIO144:1; // 16 Data Register for this pin Uint16 GPIO145:1; // 17 Data Register for this pin Uint16 GPIO146:1; // 18 Data Register for this pin Uint16 GPIO147:1; // 19 Data Register for this pin Uint16 GPIO148:1; // 20 Data Register for this pin Uint16 GPIO149:1; // 21 Data Register for this pin Uint16 GPIO150:1; // 22 Data Register for this pin Uint16 GPIO151:1; // 23 Data Register for this pin Uint16 GPIO152:1; // 24 Data Register for this pin Uint16 GPIO153:1; // 25 Data Register for this pin Uint16 GPIO154:1; // 26 Data Register for this pin Uint16 GPIO155:1; // 27 Data Register for this pin Uint16 GPIO156:1; // 28 Data Register for this pin Uint16 GPIO157:1; // 29 Data Register for this pin Uint16 GPIO158:1; // 30 Data Register for this pin Uint16 GPIO159:1; // 31 Data Register for this pin }; union GPEDAT_REG { Uint32 all; struct GPEDAT_BITS bit; }; struct GPESET_BITS { // bits description Uint16 GPIO128:1; // 0 Output Set bit for this pin Uint16 GPIO129:1; // 1 Output Set bit for this pin Uint16 GPIO130:1; // 2 Output Set bit for this pin Uint16 GPIO131:1; // 3 Output Set bit for this pin Uint16 GPIO132:1; // 4 Output Set bit for this pin Uint16 GPIO133:1; // 5 Output Set bit for this pin Uint16 GPIO134:1; // 6 Output Set bit for this pin Uint16 GPIO135:1; // 7 Output Set bit for this pin Uint16 GPIO136:1; // 8 Output Set bit for this pin Uint16 GPIO137:1; // 9 Output Set bit for this pin Uint16 GPIO138:1; // 10 Output Set bit for this pin Uint16 GPIO139:1; // 11 Output Set bit for this pin Uint16 GPIO140:1; // 12 Output Set bit for this pin Uint16 GPIO141:1; // 13 Output Set bit for this pin Uint16 GPIO142:1; // 14 Output Set bit for this pin Uint16 GPIO143:1; // 15 Output Set bit for this pin Uint16 GPIO144:1; // 16 Output Set bit for this pin Uint16 GPIO145:1; // 17 Output Set bit for this pin Uint16 GPIO146:1; // 18 Output Set bit for this pin Uint16 GPIO147:1; // 19 Output Set bit for this pin Uint16 GPIO148:1; // 20 Output Set bit for this pin Uint16 GPIO149:1; // 21 Output Set bit for this pin Uint16 GPIO150:1; // 22 Output Set bit for this pin Uint16 GPIO151:1; // 23 Output Set bit for this pin Uint16 GPIO152:1; // 24 Output Set bit for this pin Uint16 GPIO153:1; // 25 Output Set bit for this pin Uint16 GPIO154:1; // 26 Output Set bit for this pin Uint16 GPIO155:1; // 27 Output Set bit for this pin Uint16 GPIO156:1; // 28 Output Set bit for this pin Uint16 GPIO157:1; // 29 Output Set bit for this pin Uint16 GPIO158:1; // 30 Output Set bit for this pin Uint16 GPIO159:1; // 31 Output Set bit for this pin }; union GPESET_REG { Uint32 all; struct GPESET_BITS bit; }; struct GPECLEAR_BITS { // bits description Uint16 GPIO128:1; // 0 Output Clear bit for this pin Uint16 GPIO129:1; // 1 Output Clear bit for this pin Uint16 GPIO130:1; // 2 Output Clear bit for this pin Uint16 GPIO131:1; // 3 Output Clear bit for this pin Uint16 GPIO132:1; // 4 Output Clear bit for this pin Uint16 GPIO133:1; // 5 Output Clear bit for this pin Uint16 GPIO134:1; // 6 Output Clear bit for this pin Uint16 GPIO135:1; // 7 Output Clear bit for this pin Uint16 GPIO136:1; // 8 Output Clear bit for this pin Uint16 GPIO137:1; // 9 Output Clear bit for this pin Uint16 GPIO138:1; // 10 Output Clear bit for this pin Uint16 GPIO139:1; // 11 Output Clear bit for this pin Uint16 GPIO140:1; // 12 Output Clear bit for this pin Uint16 GPIO141:1; // 13 Output Clear bit for this pin Uint16 GPIO142:1; // 14 Output Clear bit for this pin Uint16 GPIO143:1; // 15 Output Clear bit for this pin Uint16 GPIO144:1; // 16 Output Clear bit for this pin Uint16 GPIO145:1; // 17 Output Clear bit for this pin Uint16 GPIO146:1; // 18 Output Clear bit for this pin Uint16 GPIO147:1; // 19 Output Clear bit for this pin Uint16 GPIO148:1; // 20 Output Clear bit for this pin Uint16 GPIO149:1; // 21 Output Clear bit for this pin Uint16 GPIO150:1; // 22 Output Clear bit for this pin Uint16 GPIO151:1; // 23 Output Clear bit for this pin Uint16 GPIO152:1; // 24 Output Clear bit for this pin Uint16 GPIO153:1; // 25 Output Clear bit for this pin Uint16 GPIO154:1; // 26 Output Clear bit for this pin Uint16 GPIO155:1; // 27 Output Clear bit for this pin Uint16 GPIO156:1; // 28 Output Clear bit for this pin Uint16 GPIO157:1; // 29 Output Clear bit for this pin Uint16 GPIO158:1; // 30 Output Clear bit for this pin Uint16 GPIO159:1; // 31 Output Clear bit for this pin }; union GPECLEAR_REG { Uint32 all; struct GPECLEAR_BITS bit; }; struct GPETOGGLE_BITS { // bits description Uint16 GPIO128:1; // 0 Output Toggle bit for this pin Uint16 GPIO129:1; // 1 Output Toggle bit for this pin Uint16 GPIO130:1; // 2 Output Toggle bit for this pin Uint16 GPIO131:1; // 3 Output Toggle bit for this pin Uint16 GPIO132:1; // 4 Output Toggle bit for this pin Uint16 GPIO133:1; // 5 Output Toggle bit for this pin Uint16 GPIO134:1; // 6 Output Toggle bit for this pin Uint16 GPIO135:1; // 7 Output Toggle bit for this pin Uint16 GPIO136:1; // 8 Output Toggle bit for this pin Uint16 GPIO137:1; // 9 Output Toggle bit for this pin Uint16 GPIO138:1; // 10 Output Toggle bit for this pin Uint16 GPIO139:1; // 11 Output Toggle bit for this pin Uint16 GPIO140:1; // 12 Output Toggle bit for this pin Uint16 GPIO141:1; // 13 Output Toggle bit for this pin Uint16 GPIO142:1; // 14 Output Toggle bit for this pin Uint16 GPIO143:1; // 15 Output Toggle bit for this pin Uint16 GPIO144:1; // 16 Output Toggle bit for this pin Uint16 GPIO145:1; // 17 Output Toggle bit for this pin Uint16 GPIO146:1; // 18 Output Toggle bit for this pin Uint16 GPIO147:1; // 19 Output Toggle bit for this pin Uint16 GPIO148:1; // 20 Output Toggle bit for this pin Uint16 GPIO149:1; // 21 Output Toggle bit for this pin Uint16 GPIO150:1; // 22 Output Toggle bit for this pin Uint16 GPIO151:1; // 23 Output Toggle bit for this pin Uint16 GPIO152:1; // 24 Output Toggle bit for this pin Uint16 GPIO153:1; // 25 Output Toggle bit for this pin Uint16 GPIO154:1; // 26 Output Toggle bit for this pin Uint16 GPIO155:1; // 27 Output Toggle bit for this pin Uint16 GPIO156:1; // 28 Output Toggle bit for this pin Uint16 GPIO157:1; // 29 Output Toggle bit for this pin Uint16 GPIO158:1; // 30 Output Toggle bit for this pin Uint16 GPIO159:1; // 31 Output Toggle bit for this pin }; union GPETOGGLE_REG { Uint32 all; struct GPETOGGLE_BITS bit; }; struct GPFDAT_BITS { // bits description Uint16 GPIO160:1; // 0 Data Register for this pin Uint16 GPIO161:1; // 1 Data Register for this pin Uint16 GPIO162:1; // 2 Data Register for this pin Uint16 GPIO163:1; // 3 Data Register for this pin Uint16 GPIO164:1; // 4 Data Register for this pin Uint16 GPIO165:1; // 5 Data Register for this pin Uint16 GPIO166:1; // 6 Data Register for this pin Uint16 GPIO167:1; // 7 Data Register for this pin Uint16 GPIO168:1; // 8 Data Register for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFDAT_REG { Uint32 all; struct GPFDAT_BITS bit; }; struct GPFSET_BITS { // bits description Uint16 GPIO160:1; // 0 Output Set bit for this pin Uint16 GPIO161:1; // 1 Output Set bit for this pin Uint16 GPIO162:1; // 2 Output Set bit for this pin Uint16 GPIO163:1; // 3 Output Set bit for this pin Uint16 GPIO164:1; // 4 Output Set bit for this pin Uint16 GPIO165:1; // 5 Output Set bit for this pin Uint16 GPIO166:1; // 6 Output Set bit for this pin Uint16 GPIO167:1; // 7 Output Set bit for this pin Uint16 GPIO168:1; // 8 Output Set bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFSET_REG { Uint32 all; struct GPFSET_BITS bit; }; struct GPFCLEAR_BITS { // bits description Uint16 GPIO160:1; // 0 Output Clear bit for this pin Uint16 GPIO161:1; // 1 Output Clear bit for this pin Uint16 GPIO162:1; // 2 Output Clear bit for this pin Uint16 GPIO163:1; // 3 Output Clear bit for this pin Uint16 GPIO164:1; // 4 Output Clear bit for this pin Uint16 GPIO165:1; // 5 Output Clear bit for this pin Uint16 GPIO166:1; // 6 Output Clear bit for this pin Uint16 GPIO167:1; // 7 Output Clear bit for this pin Uint16 GPIO168:1; // 8 Output Clear bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFCLEAR_REG { Uint32 all; struct GPFCLEAR_BITS bit; }; struct GPFTOGGLE_BITS { // bits description Uint16 GPIO160:1; // 0 Output Toggle bit for this pin Uint16 GPIO161:1; // 1 Output Toggle bit for this pin Uint16 GPIO162:1; // 2 Output Toggle bit for this pin Uint16 GPIO163:1; // 3 Output Toggle bit for this pin Uint16 GPIO164:1; // 4 Output Toggle bit for this pin Uint16 GPIO165:1; // 5 Output Toggle bit for this pin Uint16 GPIO166:1; // 6 Output Toggle bit for this pin Uint16 GPIO167:1; // 7 Output Toggle bit for this pin Uint16 GPIO168:1; // 8 Output Toggle bit for this pin Uint16 rsvd1:1; // 9 Reserved Uint16 rsvd2:1; // 10 Reserved Uint16 rsvd3:1; // 11 Reserved Uint16 rsvd4:1; // 12 Reserved Uint16 rsvd5:1; // 13 Reserved Uint16 rsvd6:1; // 14 Reserved Uint16 rsvd7:1; // 15 Reserved Uint16 rsvd8:1; // 16 Reserved Uint16 rsvd9:1; // 17 Reserved Uint16 rsvd10:1; // 18 Reserved Uint16 rsvd11:1; // 19 Reserved Uint16 rsvd12:1; // 20 Reserved Uint16 rsvd13:1; // 21 Reserved Uint16 rsvd14:1; // 22 Reserved Uint16 rsvd15:1; // 23 Reserved Uint16 rsvd16:1; // 24 Reserved Uint16 rsvd17:1; // 25 Reserved Uint16 rsvd18:1; // 26 Reserved Uint16 rsvd19:1; // 27 Reserved Uint16 rsvd20:1; // 28 Reserved Uint16 rsvd21:1; // 29 Reserved Uint16 rsvd22:1; // 30 Reserved Uint16 rsvd23:1; // 31 Reserved }; union GPFTOGGLE_REG { Uint32 all; struct GPFTOGGLE_BITS bit; }; struct GPIO_DATA_REGS { union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to 31) union GPASET_REG GPASET; // GPIO A Data Set Register (GPIO0 to 31) union GPACLEAR_REG GPACLEAR; // GPIO A Data Clear Register (GPIO0 to 31) union GPATOGGLE_REG GPATOGGLE; // GPIO A Data Toggle Register (GPIO0 to 31) union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to 63) union GPBSET_REG GPBSET; // GPIO B Data Set Register (GPIO32 to 63) union GPBCLEAR_REG GPBCLEAR; // GPIO B Data Clear Register (GPIO32 to 63) union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Data Toggle Register (GPIO32 to 63) union GPCDAT_REG GPCDAT; // GPIO C Data Register (GPIO64 to 95) union GPCSET_REG GPCSET; // GPIO C Data Set Register (GPIO64 to 95) union GPCCLEAR_REG GPCCLEAR; // GPIO C Data Clear Register (GPIO64 to 95) union GPCTOGGLE_REG GPCTOGGLE; // GPIO C Data Toggle Register (GPIO64 to 95) union GPDDAT_REG GPDDAT; // GPIO D Data Register (GPIO96 to 127) union GPDSET_REG GPDSET; // GPIO D Data Set Register (GPIO96 to 127) union GPDCLEAR_REG GPDCLEAR; // GPIO D Data Clear Register (GPIO96 to 127) union GPDTOGGLE_REG GPDTOGGLE; // GPIO D Data Toggle Register (GPIO96 to 127) union GPEDAT_REG GPEDAT; // GPIO E Data Register (GPIO128 to 159) union GPESET_REG GPESET; // GPIO E Data Set Register (GPIO128 to 159) union GPECLEAR_REG GPECLEAR; // GPIO E Data Clear Register (GPIO128 to 159) union GPETOGGLE_REG GPETOGGLE; // GPIO E Data Toggle Register (GPIO128 to 159) union GPFDAT_REG GPFDAT; // GPIO F Data Register (GPIO160 to 168) union GPFSET_REG GPFSET; // GPIO F Data Set Register (GPIO160 to 168) union GPFCLEAR_REG GPFCLEAR; // GPIO F Data Clear Register (GPIO160 to 168) union GPFTOGGLE_REG GPFTOGGLE; // GPIO F Data Toggle Register (GPIO160 to 168) }; struct GPIO_DATA_READ_REGS { Uint32 GPADAT_R; // GPIO A Data Read Register Uint32 GPBDAT_R; // GPIO B Data Read Register Uint32 GPCDAT_R; // GPIO C Data Read Register Uint32 GPDDAT_R; // GPIO D Data Read Register Uint32 GPEDAT_R; // GPIO E Data Read Register Uint32 GPFDAT_R; // GPIO F Data Read Register }; //--------------------------------------------------------------------------- // GPIO External References & Function Declarations: // extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; extern volatile struct GPIO_DATA_REGS GpioDataRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_hwbist.h // // TITLE: Definitions for the HWBIST registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // HWBIST Individual Register Bit Definitions: struct CSTCGCR3_BITS { // bits description Uint16 ILS:4; // 3:0 Interrupt Logging Start Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CSTCGCR3_REG { Uint32 all; struct CSTCGCR3_BITS bit; }; struct CSTCGCR4_BITS { // bits description Uint16 BISTGO:4; // 3:0 BIST Start Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CSTCGCR4_REG { Uint32 all; struct CSTCGCR4_BITS bit; }; struct CSTCGCR5_BITS { // bits description Uint16 RESTART:4; // 3:0 Restart Enable Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:15; // 30:16 Reserved Uint16 SOFT_RESET:1; // 31 Soft reset to BIST controller }; union CSTCGCR5_REG { Uint32 all; struct CSTCGCR5_BITS bit; }; struct CSTCGCR6_BITS { // bits description Uint16 COV:2; // 1:0 COVERAGE Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CSTCGCR6_REG { Uint32 all; struct CSTCGCR6_BITS bit; }; struct CSTCGCR7_BITS { // bits description Uint16 MCL:8; // 7:0 MAX CHAIN LENGTH Uint16 DC:4; // 11:8 DEAD CYCLES Uint16 NP:4; // 15:12 NUM OF PIPELINE STAGES Uint16 PST:2; // 17:16 PATTERN SET TYPE Uint16 SCD:2; // 19:18 SHIFT_CLOCK_DIVISION Uint16 rsvd1:12; // 31:20 Reserved }; union CSTCGCR7_REG { Uint32 all; struct CSTCGCR7_BITS bit; }; struct CSTCGCR8_BITS { // bits description Uint16 CPC:16; // 15:0 COMPARE PATTERN CNT Uint16 rsvd1:16; // 31:16 Reserved }; union CSTCGCR8_REG { Uint32 all; struct CSTCGCR8_BITS bit; }; struct CSTCPCNT_BITS { // bits description Uint16 PCNT_95:16; // 15:0 PATTERNS FOR 95% COVERAGE Uint16 PCNT_99:16; // 31:16 PATTERNS FOR 99% COVERAGE }; union CSTCPCNT_REG { Uint32 all; struct CSTCPCNT_BITS bit; }; struct CSTCCONFIG_BITS { // bits description Uint16 CFGDONE:4; // 3:0 Configuration done Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CSTCCONFIG_REG { Uint32 all; struct CSTCCONFIG_BITS bit; }; struct CSTCSADDR_BITS { // bits description Uint16 SAPAT:16; // 15:0 PATTERN ROM Start Address Uint16 SAMISR:16; // 31:16 MISR ROM Start Address }; union CSTCSADDR_REG { Uint32 all; struct CSTCSADDR_BITS bit; }; struct CSTCTEST_BITS { // bits description Uint16 TEST_TO:4; // 3:0 Test_ Time_Out Uint16 TEST_CMP_FAIL:4; // 7:4 Test MISR compare fail Uint16 TEST_NMI:4; // 11:8 Test_NMI Uint32 TEST:20; // 31:12 TEST Bits }; union CSTCTEST_REG { Uint32 all; struct CSTCTEST_BITS bit; }; struct CSTCCRD_BITS { // bits description Uint16 Restore_Done:4; // 3:0 Context Restone Done Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CSTCCRD_REG { Uint32 all; struct CSTCCRD_BITS bit; }; struct CSTCGSTAT_BITS { // bits description Uint16 BISTDONE:1; // 0 HW BIST Complete Uint16 MACRODONE:1; // 1 Macro test slot Complete Uint16 NMI:1; // 2 Exit due to NMI Uint16 BISTFAIL:1; // 3 HW BIST Failure Uint16 INTCMPF:1; // 4 Intermediate Comparison Failure Uint16 TOFAIL:1; // 5 Time Out Failure Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CSTCGSTAT_REG { Uint32 all; struct CSTCGSTAT_BITS bit; }; struct CSTCCPCR_BITS { // bits description Uint16 PATCNT:16; // 15:0 Current Pattern Count Uint16 rsvd1:16; // 31:16 Reserved }; union CSTCCPCR_REG { Uint32 all; struct CSTCCPCR_BITS bit; }; struct CSTCCADDR_BITS { // bits description Uint16 PATADDR:16; // 15:0 Current Pattern ROM Address Uint16 MISRADDR:16; // 31:16 Current MISR ROM Address }; union CSTCCADDR_REG { Uint32 all; struct CSTCCADDR_BITS bit; }; struct HWBIST_REGS { Uint16 rsvd1[4]; // Reserved Uint32 CSTCGCR1; // STC Global Control Register1 Uint16 rsvd2[6]; // Reserved union CSTCGCR3_REG CSTCGCR3; // STC Global Control Register3 Uint16 rsvd3[2]; // Reserved union CSTCGCR4_REG CSTCGCR4; // STC Global Control Register4 Uint16 rsvd4[2]; // Reserved union CSTCGCR5_REG CSTCGCR5; // STC Global Control Register5 Uint16 rsvd5[2]; // Reserved union CSTCGCR6_REG CSTCGCR6; // STC Global Control Register6 Uint16 rsvd6[2]; // Reserved union CSTCGCR7_REG CSTCGCR7; // STC Global Control Register7 Uint16 rsvd7[2]; // Reserved union CSTCGCR8_REG CSTCGCR8; // STC Global Control Register8 Uint16 rsvd8[2]; // Reserved union CSTCPCNT_REG CSTCPCNT; // STC Pattern Count Register Uint16 rsvd9[2]; // Reserved union CSTCCONFIG_REG CSTCCONFIG; // STC Registers Configuration Status Uint16 rsvd10[2]; // Reserved union CSTCSADDR_REG CSTCSADDR; // STC ROM Start Address Uint16 rsvd11[2]; // Reserved union CSTCTEST_REG CSTCTEST; // C28 HW BIST Test Register Uint16 rsvd12[2]; // Reserved Uint32 CSTCRET; // C28 Return PC Address Uint16 rsvd13[2]; // Reserved union CSTCCRD_REG CSTCCRD; // C28 Context Restore Done Register Uint16 rsvd14[6]; // Reserved union CSTCGSTAT_REG CSTCGSTAT; // STC Global Status Register Uint16 rsvd15[6]; // Reserved union CSTCCPCR_REG CSTCCPCR; // STC Current Pattern Count Register Uint16 rsvd16[2]; // Reserved union CSTCCADDR_REG CSTCCADDR; // STC Current ROM Address Register Uint16 rsvd17[2]; // Reserved Uint32 CSTCMISR0; // MISR Result Register 0 Uint16 rsvd18[2]; // Reserved Uint32 CSTCMISR1; // MISR Result Register 1 Uint16 rsvd19[2]; // Reserved Uint32 CSTCMISR2; // MISR Result Register 2 Uint16 rsvd20[2]; // Reserved Uint32 CSTCMISR3; // MISR Result Register 3 Uint16 rsvd21[2]; // Reserved Uint32 CSTCMISR4; // MISR Result Register 4 Uint16 rsvd22[2]; // Reserved Uint32 CSTCMISR5; // MISR Result Register 5 Uint16 rsvd23[2]; // Reserved Uint32 CSTCMISR6; // MISR Result Register 6 Uint16 rsvd24[2]; // Reserved Uint32 CSTCMISR7; // MISR Result Register 7 Uint16 rsvd25[2]; // Reserved Uint32 CSTCMISR8; // MISR Result Register 8 Uint16 rsvd26[2]; // Reserved Uint32 CSTCMISR9; // MISR Result Register 9 Uint16 rsvd27[2]; // Reserved Uint32 CSTCMISR10; // MISR Result Register 10 Uint16 rsvd28[2]; // Reserved Uint32 CSTCMISR11; // MISR Result Register 11 Uint16 rsvd29[2]; // Reserved Uint32 CSTCMISR12; // MISR Result Register 12 Uint16 rsvd30[2]; // Reserved Uint32 CSTCMISR13; // MISR Result Register 13 Uint16 rsvd31[2]; // Reserved Uint32 CSTCMISR14; // MISR Result Register 14 Uint16 rsvd32[2]; // Reserved Uint32 CSTCMISR15; // MISR Result Register 15 }; //--------------------------------------------------------------------------- // HWBIST External References & Function Declarations: // extern volatile struct HWBIST_REGS HwbistRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_i2c.h // // TITLE: Definitions for the I2C registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // I2C Individual Register Bit Definitions: struct I2COAR_BITS { // bits description Uint16 OAR:10; // 9:0 I2C Own address Uint16 rsvd1:6; // 15:10 Reserved }; union I2COAR_REG { Uint16 all; struct I2COAR_BITS bit; }; struct I2CIER_BITS { // bits description Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable Uint16 NACK:1; // 1 No-acknowledgment interrupt enable Uint16 ARDY:1; // 2 Register-access-ready interrupt enable Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable Uint16 SCD:1; // 5 Stop condition detected interrupt enable Uint16 AAS:1; // 6 Addressed as slave interrupt enable Uint16 rsvd1:9; // 15:7 Reserved }; union I2CIER_REG { Uint16 all; struct I2CIER_BITS bit; }; struct I2CSTR_BITS { // bits description Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. Uint16 SCD:1; // 5 Stop condition detected bit. Uint16 BYTESENT:1; // 6 Byte transmit over indication Uint16 rsvd1:1; // 7 Reserved Uint16 AD0:1; // 8 Address 0 bits Uint16 AAS:1; // 9 Addressed-as-slave bit Uint16 XSMT:1; // 10 Transmit shift register empty bit. Uint16 RSFULL:1; // 11 Receive shift register full bit. Uint16 BB:1; // 12 Bus busy bit. Uint16 NACKSNT:1; // 13 NACK sent bit. Uint16 SDIR:1; // 14 Slave direction bit Uint16 rsvd2:1; // 15 Reserved }; union I2CSTR_REG { Uint16 all; struct I2CSTR_BITS bit; }; struct I2CDRR_BITS { // bits description Uint16 DATA:8; // 7:0 Receive data Uint16 rsvd1:8; // 15:8 Reserved }; union I2CDRR_REG { Uint16 all; struct I2CDRR_BITS bit; }; struct I2CSAR_BITS { // bits description Uint16 SAR:10; // 9:0 Slave Address Uint16 rsvd1:6; // 15:10 Reserved }; union I2CSAR_REG { Uint16 all; struct I2CSAR_BITS bit; }; struct I2CDXR_BITS { // bits description Uint16 DATA:8; // 7:0 Transmit data Uint16 rsvd1:8; // 15:8 Reserved }; union I2CDXR_REG { Uint16 all; struct I2CDXR_BITS bit; }; struct I2CMDR_BITS { // bits description Uint16 BC:3; // 2:0 Bit count bits. Uint16 FDF:1; // 3 Free Data Format Uint16 STB:1; // 4 START Byte Mode Uint16 IRS:1; // 5 I2C Module Reset Uint16 DLB:1; // 6 Digital Loopback Mode Uint16 RM:1; // 7 Repeat Mode Uint16 XA:1; // 8 Expanded Address Mode Uint16 TRX:1; // 9 Transmitter Mode Uint16 MST:1; // 10 Master Mode Uint16 STP:1; // 11 STOP Condition Uint16 rsvd1:1; // 12 Reserved Uint16 STT:1; // 13 START condition bit Uint16 FREE:1; // 14 Debug Action Uint16 NACKMOD:1; // 15 NACK mode bit }; union I2CMDR_REG { Uint16 all; struct I2CMDR_BITS bit; }; struct I2CISRC_BITS { // bits description Uint16 INTCODE:3; // 2:0 Interrupt code bits. Uint16 rsvd1:5; // 7:3 Reserved Uint16 WRITE_ZEROS:4; // 11:8 Always write all 0s to this field Uint16 rsvd2:4; // 15:12 Reserved }; union I2CISRC_REG { Uint16 all; struct I2CISRC_BITS bit; }; struct I2CEMDR_BITS { // bits description Uint16 BC:1; // 0 Backwards compatibility mode Uint16 FCM:1; // 1 Forward Compatibility for Tx behav in Type1 Uint16 rsvd1:14; // 15:2 Reserved }; union I2CEMDR_REG { Uint16 all; struct I2CEMDR_BITS bit; }; struct I2CPSC_BITS { // bits description Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down Uint16 rsvd1:8; // 15:8 Reserved }; union I2CPSC_REG { Uint16 all; struct I2CPSC_BITS bit; }; struct I2CFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag Uint16 TXFFST:5; // 12:8 Transmit FIFO Status Uint16 TXFFRST:1; // 13 Transmit FIFO Reset Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable Uint16 rsvd1:1; // 15 Reserved }; union I2CFFTX_REG { Uint16 all; struct I2CFFTX_BITS bit; }; struct I2CFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag Uint16 RXFFST:5; // 12:8 Receive FIFO Status Uint16 RXFFRST:1; // 13 Receive FIFO Reset Uint16 rsvd1:2; // 15:14 Reserved }; union I2CFFRX_REG { Uint16 all; struct I2CFFRX_BITS bit; }; struct I2C_REGS { union I2COAR_REG I2COAR; // I2C Own address union I2CIER_REG I2CIER; // I2C Interrupt Enable union I2CSTR_REG I2CSTR; // I2C Status Uint16 I2CCLKL; // I2C Clock low-time divider Uint16 I2CCLKH; // I2C Clock high-time divider Uint16 I2CCNT; // I2C Data count union I2CDRR_REG I2CDRR; // I2C Data receive union I2CSAR_REG I2CSAR; // I2C Slave address union I2CDXR_REG I2CDXR; // I2C Data Transmit union I2CMDR_REG I2CMDR; // I2C Mode union I2CISRC_REG I2CISRC; // I2C Interrupt Source union I2CEMDR_REG I2CEMDR; // I2C Extended Mode union I2CPSC_REG I2CPSC; // I2C Prescaler Uint16 rsvd1[19]; // Reserved union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive }; //--------------------------------------------------------------------------- // I2C External References & Function Declarations: // extern volatile struct I2C_REGS I2caRegs; extern volatile struct I2C_REGS I2cbRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_inputxbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XBAR Individual Register Bit Definitions: struct INPUTSELECTLOCK_BITS { // bits description Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SELECT Register Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SELECT Register Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SELECT Register Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SELECT Register Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SELECT Register Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT6SELECT Register Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT7SELECT Register Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT8SELECT Register Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT9SELECT Register Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT10SELECT Register Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SELECT Register Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SELECT Register Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SELECT Register Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SELECT Register Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SELECT Register Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SELECT Register Uint16 rsvd1:16; // 31:16 Reserved }; union INPUTSELECTLOCK_REG { Uint32 all; struct INPUTSELECTLOCK_BITS bit; }; struct INPUT_XBAR_REGS { Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) Uint16 INPUT15SELECT; // INPUT15 Input Select Register (GPIO0 to x) Uint16 INPUT16SELECT; // INPUT16 Input Select Register (GPIO0 to x) Uint16 rsvd1[14]; // Reserved union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register. }; //--------------------------------------------------------------------------- // INPUT_XBAR External References & Function Declarations: // extern volatile struct INPUT_XBAR_REGS InputXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_ipc.h // // TITLE: Definitions for the IPC registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // IPC Individual Register Bit Definitions: struct CPU1TOCMIPCACK_BITS { // bits description Uint16 IPC0:1; // 0 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC0 bit Uint16 IPC1:1; // 1 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC1 bit Uint16 IPC2:1; // 2 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC2 bit Uint16 IPC3:1; // 3 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC3 bit Uint16 IPC4:1; // 4 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC4 bit Uint16 IPC5:1; // 5 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC5 bit Uint16 IPC6:1; // 6 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC6 bit Uint16 IPC7:1; // 7 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC7 bit Uint16 IPC8:1; // 8 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC8 bit Uint16 IPC9:1; // 9 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC9 bit Uint16 IPC10:1; // 10 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC10 bit Uint16 IPC11:1; // 11 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC11 bit Uint16 IPC12:1; // 12 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC12 bit Uint16 IPC13:1; // 13 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC13 bit Uint16 IPC14:1; // 14 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC14 bit Uint16 IPC15:1; // 15 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC15 bit Uint16 IPC16:1; // 16 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC16 bit Uint16 IPC17:1; // 17 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC17 bit Uint16 IPC18:1; // 18 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC18 bit Uint16 IPC19:1; // 19 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC19 bit Uint16 IPC20:1; // 20 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC20 bit Uint16 IPC21:1; // 21 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC21 bit Uint16 IPC22:1; // 22 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC22 bit Uint16 IPC23:1; // 23 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC23 bit Uint16 IPC24:1; // 24 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC24 bit Uint16 IPC25:1; // 25 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC25 bit Uint16 IPC26:1; // 26 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC26 bit Uint16 IPC27:1; // 27 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC27 bit Uint16 IPC28:1; // 28 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC28 bit Uint16 IPC29:1; // 29 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC29 bit Uint16 IPC30:1; // 30 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC30 bit Uint16 IPC31:1; // 31 Acknowledgement from CPU1 to CMTOCPU1IPCFLG.IPC31 bit }; union CPU1TOCMIPCACK_REG { Uint32 all; struct CPU1TOCMIPCACK_BITS bit; }; struct CMTOCPU1IPCSTS_BITS { // bits description Uint16 IPC0:1; // 0 IPC0 Request from CM to CPU1 Uint16 IPC1:1; // 1 IPC1 Request from CM to CPU1 Uint16 IPC2:1; // 2 IPC2 Request from CM to CPU1 Uint16 IPC3:1; // 3 IPC3 Request from CM to CPU1 Uint16 IPC4:1; // 4 IPC4 Request from CM to CPU1 Uint16 IPC5:1; // 5 IPC5 Request from CM to CPU1 Uint16 IPC6:1; // 6 IPC6 Request from CM to CPU1 Uint16 IPC7:1; // 7 IPC7 Request from CM to CPU1 Uint16 IPC8:1; // 8 IPC8 Request from CM to CPU1 Uint16 IPC9:1; // 9 IPC9 Request from CM to CPU1 Uint16 IPC10:1; // 10 IPC10 Request from CM to CPU1 Uint16 IPC11:1; // 11 IPC11 Request from CM to CPU1 Uint16 IPC12:1; // 12 IPC12 Request from CM to CPU1 Uint16 IPC13:1; // 13 IPC13 Request from CM to CPU1 Uint16 IPC14:1; // 14 IPC14 Request from CM to CPU1 Uint16 IPC15:1; // 15 IPC15 Request from CM to CPU1 Uint16 IPC16:1; // 16 IPC16 Request from CM to CPU1 Uint16 IPC17:1; // 17 IPC17 Request from CM to CPU1 Uint16 IPC18:1; // 18 IPC18 Request from CM to CPU1 Uint16 IPC19:1; // 19 IPC19 Request from CM to CPU1 Uint16 IPC20:1; // 20 IPC20 Request from CM to CPU1 Uint16 IPC21:1; // 21 IPC21 Request from CM to CPU1 Uint16 IPC22:1; // 22 IPC22 Request from CM to CPU1 Uint16 IPC23:1; // 23 IPC23 Request from CM to CPU1 Uint16 IPC24:1; // 24 IPC24 Request from CM to CPU1 Uint16 IPC25:1; // 25 IPC25 Request from CM to CPU1 Uint16 IPC26:1; // 26 IPC26 Request from CM to CPU1 Uint16 IPC27:1; // 27 IPC27 Request from CM to CPU1 Uint16 IPC28:1; // 28 IPC28 Request from CM to CPU1 Uint16 IPC29:1; // 29 IPC29 Request from CM to CPU1 Uint16 IPC30:1; // 30 IPC30 Request from CM to CPU1 Uint16 IPC31:1; // 31 IPC31 Request from CM to CPU1 }; union CMTOCPU1IPCSTS_REG { Uint32 all; struct CMTOCPU1IPCSTS_BITS bit; }; struct CPU1TOCMIPCSET_BITS { // bits description Uint16 IPC0:1; // 0 Set CPU1TOCMIPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Set CPU1TOCMIPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Set CPU1TOCMIPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Set CPU1TOCMIPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Set CPU1TOCMIPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Set CPU1TOCMIPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Set CPU1TOCMIPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Set CPU1TOCMIPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Set CPU1TOCMIPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Set CPU1TOCMIPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Set CPU1TOCMIPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Set CPU1TOCMIPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Set CPU1TOCMIPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Set CPU1TOCMIPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Set CPU1TOCMIPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Set CPU1TOCMIPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Set CPU1TOCMIPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Set CPU1TOCMIPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Set CPU1TOCMIPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Set CPU1TOCMIPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Set CPU1TOCMIPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Set CPU1TOCMIPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Set CPU1TOCMIPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Set CPU1TOCMIPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Set CPU1TOCMIPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Set CPU1TOCMIPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Set CPU1TOCMIPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Set CPU1TOCMIPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Set CPU1TOCMIPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Set CPU1TOCMIPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Set CPU1TOCMIPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Set CPU1TOCMIPCFLG.IPC31 Flag }; union CPU1TOCMIPCSET_REG { Uint32 all; struct CPU1TOCMIPCSET_BITS bit; }; struct CPU1TOCMIPCCLR_BITS { // bits description Uint16 IPC0:1; // 0 Clear CPU1TOCMIPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Clear CPU1TOCMIPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Clear CPU1TOCMIPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Clear CPU1TOCMIPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Clear CPU1TOCMIPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Clear CPU1TOCMIPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Clear CPU1TOCMIPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Clear CPU1TOCMIPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Clear CPU1TOCMIPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Clear CPU1TOCMIPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Clear CPU1TOCMIPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Clear CPU1TOCMIPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Clear CPU1TOCMIPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Clear CPU1TOCMIPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Clear CPU1TOCMIPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Clear CPU1TOCMIPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Clear CPU1TOCMIPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Clear CPU1TOCMIPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Clear CPU1TOCMIPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Clear CPU1TOCMIPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Clear CPU1TOCMIPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Clear CPU1TOCMIPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Clear CPU1TOCMIPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Clear CPU1TOCMIPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Clear CPU1TOCMIPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Clear CPU1TOCMIPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Clear CPU1TOCMIPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Clear CPU1TOCMIPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Clear CPU1TOCMIPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Clear CPU1TOCMIPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Clear CPU1TOCMIPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Clear CPU1TOCMIPCFLG.IPC31 Flag }; union CPU1TOCMIPCCLR_REG { Uint32 all; struct CPU1TOCMIPCCLR_BITS bit; }; struct CPU1TOCMIPCFLG_BITS { // bits description Uint16 IPC0:1; // 0 CPU1 to CM IPC0 Flag Status Uint16 IPC1:1; // 1 CPU1 to CM IPC1 Flag Status Uint16 IPC2:1; // 2 CPU1 to CM IPC2 Flag Status Uint16 IPC3:1; // 3 CPU1 to CM IPC3 Flag Status Uint16 IPC4:1; // 4 CPU1 to CM IPC4 Flag Status Uint16 IPC5:1; // 5 CPU1 to CM IPC5 Flag Status Uint16 IPC6:1; // 6 CPU1 to CM IPC6 Flag Status Uint16 IPC7:1; // 7 CPU1 to CM IPC7 Flag Status Uint16 IPC8:1; // 8 CPU1 to CM IPC8 Flag Status Uint16 IPC9:1; // 9 CPU1 to CM IPC9 Flag Status Uint16 IPC10:1; // 10 CPU1 to CM IPC10 Flag Status Uint16 IPC11:1; // 11 CPU1 to CM IPC11 Flag Status Uint16 IPC12:1; // 12 CPU1 to CM IPC12 Flag Status Uint16 IPC13:1; // 13 CPU1 to CM IPC13 Flag Status Uint16 IPC14:1; // 14 CPU1 to CM IPC14 Flag Status Uint16 IPC15:1; // 15 CPU1 to CM IPC15 Flag Status Uint16 IPC16:1; // 16 CPU1 to CM IPC16 Flag Status Uint16 IPC17:1; // 17 CPU1 to CM IPC17 Flag Status Uint16 IPC18:1; // 18 CPU1 to CM IPC18 Flag Status Uint16 IPC19:1; // 19 CPU1 to CM IPC19 Flag Status Uint16 IPC20:1; // 20 CPU1 to CM IPC20 Flag Status Uint16 IPC21:1; // 21 CPU1 to CM IPC21 Flag Status Uint16 IPC22:1; // 22 CPU1 to CM IPC22 Flag Status Uint16 IPC23:1; // 23 CPU1 to CM IPC23 Flag Status Uint16 IPC24:1; // 24 CPU1 to CM IPC24 Flag Status Uint16 IPC25:1; // 25 CPU1 to CM IPC25 Flag Status Uint16 IPC26:1; // 26 CPU1 to CM IPC26 Flag Status Uint16 IPC27:1; // 27 CPU1 to CM IPC27 Flag Status Uint16 IPC28:1; // 28 CPU1 to CM IPC28 Flag Status Uint16 IPC29:1; // 29 CPU1 to CM IPC29 Flag Status Uint16 IPC30:1; // 30 CPU1 to CM IPC30 Flag Status Uint16 IPC31:1; // 31 CPU1 to CM IPC31 Flag Status }; union CPU1TOCMIPCFLG_REG { Uint32 all; struct CPU1TOCMIPCFLG_BITS bit; }; struct CPU1TOCM_IPC_REGS_CPU1VIEW { union CPU1TOCMIPCACK_REG CPU1TOCMIPCACK; // CPU1TOCMIPCACK Register union CMTOCPU1IPCSTS_REG CMTOCPU1IPCSTS; // CMTOCPU1IPCSTS Register union CPU1TOCMIPCSET_REG CPU1TOCMIPCSET; // CPU1TOCMIPCSET Register union CPU1TOCMIPCCLR_REG CPU1TOCMIPCCLR; // CPU1TOCMIPCCLR Register union CPU1TOCMIPCFLG_REG CPU1TOCMIPCFLG; // CPU1TOCMIPCFLG Register Uint16 rsvd1[2]; // Reserved Uint32 IPCCOUNTERL; // IPCCOUNTERL Register Uint32 IPCCOUNTERH; // IPCCOUNTERH Register Uint32 CPU1TOCMIPCSENDCOM; // CPU1TOCMIPCSENDCOM Register Uint32 CPU1TOCMIPCSENDADDR; // CPU1TOCMIPCSENDADDR Register Uint32 CPU1TOCMIPCSENDDATA; // CPU1TOCMIPCSENDDATA Register Uint32 CMTOCPU1IPCREPLY; // CMTOCPU1IPCREPLY Register Uint32 CMTOCPU1IPCRECVCOM; // CMTOCPU1IPCRECVCOM Register Uint32 CMTOCPU1IPCRECVADDR; // CMTOCPU1IPCRECVADDR Register Uint32 CMTOCPU1IPCRECVDATA; // CMTOCPU1IPCRECVDATA Register Uint32 CPU1TOCMIPCREPLY; // CPU1TOCMIPCREPLY Register Uint32 CMTOCPU1IPCBOOTSTS; // CMTOCPU1IPCBOOTSTS Register Uint32 CPU1TOCMIPCBOOTMODE; // CPU1TOCMIPCBOOTMODE Register }; struct CMTOCPU1IPCACK_BITS { // bits description Uint16 IPC0:1; // 0 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC0 bit Uint16 IPC1:1; // 1 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC1 bit Uint16 IPC2:1; // 2 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC2 bit Uint16 IPC3:1; // 3 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC3 bit Uint16 IPC4:1; // 4 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC4 bit Uint16 IPC5:1; // 5 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC5 bit Uint16 IPC6:1; // 6 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC6 bit Uint16 IPC7:1; // 7 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC7 bit Uint16 IPC8:1; // 8 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC8 bit Uint16 IPC9:1; // 9 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC9 bit Uint16 IPC10:1; // 10 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC10 bit Uint16 IPC11:1; // 11 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC11 bit Uint16 IPC12:1; // 12 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC12 bit Uint16 IPC13:1; // 13 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC13 bit Uint16 IPC14:1; // 14 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC14 bit Uint16 IPC15:1; // 15 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC15 bit Uint16 IPC16:1; // 16 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC16 bit Uint16 IPC17:1; // 17 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC17 bit Uint16 IPC18:1; // 18 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC18 bit Uint16 IPC19:1; // 19 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC19 bit Uint16 IPC20:1; // 20 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC20 bit Uint16 IPC21:1; // 21 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC21 bit Uint16 IPC22:1; // 22 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC22 bit Uint16 IPC23:1; // 23 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC23 bit Uint16 IPC24:1; // 24 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC24 bit Uint16 IPC25:1; // 25 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC25 bit Uint16 IPC26:1; // 26 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC26 bit Uint16 IPC27:1; // 27 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC27 bit Uint16 IPC28:1; // 28 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC28 bit Uint16 IPC29:1; // 29 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC29 bit Uint16 IPC30:1; // 30 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC30 bit Uint16 IPC31:1; // 31 Acknowledgement from CM to CPU1TOCMIPCFLG.IPC31 bit }; struct PUMPREQUEST_BITS { // bits description Uint16 SEM:2; // 1:0 Flash Pump Request Semaphore between CPU1, CPU2 and CM Uint16 rsvd1:14; // 15:2 Reserved Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register }; union PUMPREQUEST_REG { Uint32 all; struct PUMPREQUEST_BITS bit; }; struct CPU2TOCMIPCACK_BITS { // bits description Uint16 IPC0:1; // 0 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC0 bit Uint16 IPC1:1; // 1 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC1 bit Uint16 IPC2:1; // 2 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC2 bit Uint16 IPC3:1; // 3 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC3 bit Uint16 IPC4:1; // 4 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC4 bit Uint16 IPC5:1; // 5 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC5 bit Uint16 IPC6:1; // 6 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC6 bit Uint16 IPC7:1; // 7 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC7 bit Uint16 IPC8:1; // 8 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC8 bit Uint16 IPC9:1; // 9 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC9 bit Uint16 IPC10:1; // 10 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC10 bit Uint16 IPC11:1; // 11 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC11 bit Uint16 IPC12:1; // 12 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC12 bit Uint16 IPC13:1; // 13 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC13 bit Uint16 IPC14:1; // 14 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC14 bit Uint16 IPC15:1; // 15 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC15 bit Uint16 IPC16:1; // 16 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC16 bit Uint16 IPC17:1; // 17 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC17 bit Uint16 IPC18:1; // 18 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC18 bit Uint16 IPC19:1; // 19 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC19 bit Uint16 IPC20:1; // 20 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC20 bit Uint16 IPC21:1; // 21 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC21 bit Uint16 IPC22:1; // 22 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC22 bit Uint16 IPC23:1; // 23 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC23 bit Uint16 IPC24:1; // 24 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC24 bit Uint16 IPC25:1; // 25 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC25 bit Uint16 IPC26:1; // 26 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC26 bit Uint16 IPC27:1; // 27 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC27 bit Uint16 IPC28:1; // 28 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC28 bit Uint16 IPC29:1; // 29 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC29 bit Uint16 IPC30:1; // 30 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC30 bit Uint16 IPC31:1; // 31 Acknowledgement from CPU2 to CMTOCPU2IPCFLG.IPC31 bit }; union CPU2TOCMIPCACK_REG { Uint32 all; struct CPU2TOCMIPCACK_BITS bit; }; struct CMTOCPU2IPCSTS_BITS { // bits description Uint16 IPC0:1; // 0 IPC0 Request from CM to CPU2 Uint16 IPC1:1; // 1 IPC1 Request from CM to CPU2 Uint16 IPC2:1; // 2 IPC2 Request from CM to CPU2 Uint16 IPC3:1; // 3 IPC3 Request from CM to CPU2 Uint16 IPC4:1; // 4 IPC4 Request from CM to CPU2 Uint16 IPC5:1; // 5 IPC5 Request from CM to CPU2 Uint16 IPC6:1; // 6 IPC6 Request from CM to CPU2 Uint16 IPC7:1; // 7 IPC7 Request from CM to CPU2 Uint16 IPC8:1; // 8 IPC8 Request from CM to CPU2 Uint16 IPC9:1; // 9 IPC9 Request from CM to CPU2 Uint16 IPC10:1; // 10 IPC10 Request from CM to CPU2 Uint16 IPC11:1; // 11 IPC11 Request from CM to CPU2 Uint16 IPC12:1; // 12 IPC12 Request from CM to CPU2 Uint16 IPC13:1; // 13 IPC13 Request from CM to CPU2 Uint16 IPC14:1; // 14 IPC14 Request from CM to CPU2 Uint16 IPC15:1; // 15 IPC15 Request from CM to CPU2 Uint16 IPC16:1; // 16 IPC16 Request from CM to CPU2 Uint16 IPC17:1; // 17 IPC17 Request from CM to CPU2 Uint16 IPC18:1; // 18 IPC18 Request from CM to CPU2 Uint16 IPC19:1; // 19 IPC19 Request from CM to CPU2 Uint16 IPC20:1; // 20 IPC20 Request from CM to CPU2 Uint16 IPC21:1; // 21 IPC21 Request from CM to CPU2 Uint16 IPC22:1; // 22 IPC22 Request from CM to CPU2 Uint16 IPC23:1; // 23 IPC23 Request from CM to CPU2 Uint16 IPC24:1; // 24 IPC24 Request from CM to CPU2 Uint16 IPC25:1; // 25 IPC25 Request from CM to CPU2 Uint16 IPC26:1; // 26 IPC26 Request from CM to CPU2 Uint16 IPC27:1; // 27 IPC27 Request from CM to CPU2 Uint16 IPC28:1; // 28 IPC28 Request from CM to CPU2 Uint16 IPC29:1; // 29 IPC29 Request from CM to CPU2 Uint16 IPC30:1; // 30 IPC30 Request from CM to CPU2 Uint16 IPC31:1; // 31 IPC31 Request from CM to CPU2 }; union CMTOCPU2IPCSTS_REG { Uint32 all; struct CMTOCPU2IPCSTS_BITS bit; }; struct CPU2TOCMIPCSET_BITS { // bits description Uint16 IPC0:1; // 0 Set CPU2TOCMIPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Set CPU2TOCMIPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Set CPU2TOCMIPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Set CPU2TOCMIPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Set CPU2TOCMIPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Set CPU2TOCMIPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Set CPU2TOCMIPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Set CPU2TOCMIPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Set CPU2TOCMIPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Set CPU2TOCMIPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Set CPU2TOCMIPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Set CPU2TOCMIPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Set CPU2TOCMIPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Set CPU2TOCMIPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Set CPU2TOCMIPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Set CPU2TOCMIPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Set CPU2TOCMIPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Set CPU2TOCMIPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Set CPU2TOCMIPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Set CPU2TOCMIPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Set CPU2TOCMIPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Set CPU2TOCMIPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Set CPU2TOCMIPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Set CPU2TOCMIPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Set CPU2TOCMIPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Set CPU2TOCMIPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Set CPU2TOCMIPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Set CPU2TOCMIPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Set CPU2TOCMIPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Set CPU2TOCMIPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Set CPU2TOCMIPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Set CPU2TOCMIPCFLG.IPC31 Flag }; union CPU2TOCMIPCSET_REG { Uint32 all; struct CPU2TOCMIPCSET_BITS bit; }; struct CPU2TOCMIPCCLR_BITS { // bits description Uint16 IPC0:1; // 0 Clear CPU2TOCMIPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Clear CPU2TOCMIPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Clear CPU2TOCMIPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Clear CPU2TOCMIPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Clear CPU2TOCMIPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Clear CPU2TOCMIPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Clear CPU2TOCMIPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Clear CPU2TOCMIPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Clear CPU2TOCMIPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Clear CPU2TOCMIPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Clear CPU2TOCMIPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Clear CPU2TOCMIPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Clear CPU2TOCMIPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Clear CPU2TOCMIPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Clear CPU2TOCMIPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Clear CPU2TOCMIPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Clear CPU2TOCMIPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Clear CPU2TOCMIPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Clear CPU2TOCMIPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Clear CPU2TOCMIPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Clear CPU2TOCMIPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Clear CPU2TOCMIPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Clear CPU2TOCMIPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Clear CPU2TOCMIPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Clear CPU2TOCMIPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Clear CPU2TOCMIPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Clear CPU2TOCMIPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Clear CPU2TOCMIPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Clear CPU2TOCMIPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Clear CPU2TOCMIPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Clear CPU2TOCMIPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Clear CPU2TOCMIPCFLG.IPC31 Flag }; union CPU2TOCMIPCCLR_REG { Uint32 all; struct CPU2TOCMIPCCLR_BITS bit; }; struct CPU2TOCMIPCFLG_BITS { // bits description Uint16 IPC0:1; // 0 CPU2 to CM IPC0 Flag Status Uint16 IPC1:1; // 1 CPU2 to CM IPC1 Flag Status Uint16 IPC2:1; // 2 CPU2 to CM IPC2 Flag Status Uint16 IPC3:1; // 3 CPU2 to CM IPC3 Flag Status Uint16 IPC4:1; // 4 CPU2 to CM IPC4 Flag Status Uint16 IPC5:1; // 5 CPU2 to CM IPC5 Flag Status Uint16 IPC6:1; // 6 CPU2 to CM IPC6 Flag Status Uint16 IPC7:1; // 7 CPU2 to CM IPC7 Flag Status Uint16 IPC8:1; // 8 CPU2 to CM IPC8 Flag Status Uint16 IPC9:1; // 9 CPU2 to CM IPC9 Flag Status Uint16 IPC10:1; // 10 CPU2 to CM IPC10 Flag Status Uint16 IPC11:1; // 11 CPU2 to CM IPC11 Flag Status Uint16 IPC12:1; // 12 CPU2 to CM IPC12 Flag Status Uint16 IPC13:1; // 13 CPU2 to CM IPC13 Flag Status Uint16 IPC14:1; // 14 CPU2 to CM IPC14 Flag Status Uint16 IPC15:1; // 15 CPU2 to CM IPC15 Flag Status Uint16 IPC16:1; // 16 CPU2 to CM IPC16 Flag Status Uint16 IPC17:1; // 17 CPU2 to CM IPC17 Flag Status Uint16 IPC18:1; // 18 CPU2 to CM IPC18 Flag Status Uint16 IPC19:1; // 19 CPU2 to CM IPC19 Flag Status Uint16 IPC20:1; // 20 CPU2 to CM IPC20 Flag Status Uint16 IPC21:1; // 21 CPU2 to CM IPC21 Flag Status Uint16 IPC22:1; // 22 CPU2 to CM IPC22 Flag Status Uint16 IPC23:1; // 23 CPU2 to CM IPC23 Flag Status Uint16 IPC24:1; // 24 CPU2 to CM IPC24 Flag Status Uint16 IPC25:1; // 25 CPU2 to CM IPC25 Flag Status Uint16 IPC26:1; // 26 CPU2 to CM IPC26 Flag Status Uint16 IPC27:1; // 27 CPU2 to CM IPC27 Flag Status Uint16 IPC28:1; // 28 CPU2 to CM IPC28 Flag Status Uint16 IPC29:1; // 29 CPU2 to CM IPC29 Flag Status Uint16 IPC30:1; // 30 CPU2 to CM IPC30 Flag Status Uint16 IPC31:1; // 31 CPU2 to CM IPC31 Flag Status }; union CPU2TOCMIPCFLG_REG { Uint32 all; struct CPU2TOCMIPCFLG_BITS bit; }; struct CPU2TOCM_IPC_REGS_CPU2VIEW { union CPU2TOCMIPCACK_REG CPU2TOCMIPCACK; // CPU2TOCMIPCACK Register union CMTOCPU2IPCSTS_REG CMTOCPU2IPCSTS; // CMTOCPU2IPCSTS Register union CPU2TOCMIPCSET_REG CPU2TOCMIPCSET; // CPU2TOCMIPCSET Register union CPU2TOCMIPCCLR_REG CPU2TOCMIPCCLR; // CPU2TOCMIPCCLR Register union CPU2TOCMIPCFLG_REG CPU2TOCMIPCFLG; // CPU2TOCMIPCFLG Register Uint16 rsvd1[2]; // Reserved Uint32 IPCCOUNTERL; // IPCCOUNTERL Register Uint32 IPCCOUNTERH; // IPCCOUNTERH Register Uint32 CPU2TOCMIPCSENDCOM; // CPU2TOCMIPCSENDCOM Register Uint32 CPU2TOCMIPCSENDADDR; // CPU2TOCMIPCSENDADDR Register Uint32 CPU2TOCMIPCSENDDATA; // CPU2TOCMIPCSENDDATA Register Uint32 CMTOCPU2IPCREPLY; // CMTOCPU2IPCREPLY Register Uint32 CMTOCPU2IPCRECVCOM; // CMTOCPU2IPCRECVCOM Register Uint32 CMTOCPU2IPCRECVADDR; // CMTOCPU2IPCRECVADDR Register Uint32 CMTOCPU2IPCRECVDATA; // CMTOCPU2IPCRECVDATA Register Uint32 CPU2TOCMIPCREPLY; // CPU2TOCMIPCREPLY Register }; struct CMTOCPU2IPCACK_BITS { // bits description Uint16 IPC0:1; // 0 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC0 bit Uint16 IPC1:1; // 1 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC1 bit Uint16 IPC2:1; // 2 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC2 bit Uint16 IPC3:1; // 3 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC3 bit Uint16 IPC4:1; // 4 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC4 bit Uint16 IPC5:1; // 5 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC5 bit Uint16 IPC6:1; // 6 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC6 bit Uint16 IPC7:1; // 7 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC7 bit Uint16 IPC8:1; // 8 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC8 bit Uint16 IPC9:1; // 9 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC9 bit Uint16 IPC10:1; // 10 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC10 bit Uint16 IPC11:1; // 11 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC11 bit Uint16 IPC12:1; // 12 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC12 bit Uint16 IPC13:1; // 13 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC13 bit Uint16 IPC14:1; // 14 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC14 bit Uint16 IPC15:1; // 15 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC15 bit Uint16 IPC16:1; // 16 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC16 bit Uint16 IPC17:1; // 17 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC17 bit Uint16 IPC18:1; // 18 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC18 bit Uint16 IPC19:1; // 19 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC19 bit Uint16 IPC20:1; // 20 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC20 bit Uint16 IPC21:1; // 21 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC21 bit Uint16 IPC22:1; // 22 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC22 bit Uint16 IPC23:1; // 23 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC23 bit Uint16 IPC24:1; // 24 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC24 bit Uint16 IPC25:1; // 25 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC25 bit Uint16 IPC26:1; // 26 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC26 bit Uint16 IPC27:1; // 27 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC27 bit Uint16 IPC28:1; // 28 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC28 bit Uint16 IPC29:1; // 29 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC29 bit Uint16 IPC30:1; // 30 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC30 bit Uint16 IPC31:1; // 31 Acknowledgement from CM to CPU2TOCMIPCFLG.IPC31 bit }; struct CPU1TOCPU2IPCACK_BITS { // bits description Uint16 IPC0:1; // 0 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC0 bit Uint16 IPC1:1; // 1 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC1 bit Uint16 IPC2:1; // 2 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC2 bit Uint16 IPC3:1; // 3 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC3 bit Uint16 IPC4:1; // 4 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC4 bit Uint16 IPC5:1; // 5 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC5 bit Uint16 IPC6:1; // 6 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC6 bit Uint16 IPC7:1; // 7 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC7 bit Uint16 IPC8:1; // 8 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC8 bit Uint16 IPC9:1; // 9 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC9 bit Uint16 IPC10:1; // 10 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC10 bit Uint16 IPC11:1; // 11 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC11 bit Uint16 IPC12:1; // 12 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC12 bit Uint16 IPC13:1; // 13 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC13 bit Uint16 IPC14:1; // 14 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC14 bit Uint16 IPC15:1; // 15 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC15 bit Uint16 IPC16:1; // 16 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC16 bit Uint16 IPC17:1; // 17 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC17 bit Uint16 IPC18:1; // 18 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC18 bit Uint16 IPC19:1; // 19 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC19 bit Uint16 IPC20:1; // 20 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC20 bit Uint16 IPC21:1; // 21 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC21 bit Uint16 IPC22:1; // 22 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC22 bit Uint16 IPC23:1; // 23 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC23 bit Uint16 IPC24:1; // 24 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC24 bit Uint16 IPC25:1; // 25 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC25 bit Uint16 IPC26:1; // 26 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC26 bit Uint16 IPC27:1; // 27 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC27 bit Uint16 IPC28:1; // 28 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC28 bit Uint16 IPC29:1; // 29 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC29 bit Uint16 IPC30:1; // 30 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC30 bit Uint16 IPC31:1; // 31 Acknowledgement from CPU1 to CPU2TOCPU1IPCFLG.IPC31 bit }; union CPU1TOCPU2IPCACK_REG { Uint32 all; struct CPU1TOCPU2IPCACK_BITS bit; }; struct CPU2TOCPU1IPCSTS_BITS { // bits description Uint16 IPC0:1; // 0 IPC0 Request from CPU2 to CPU1 Uint16 IPC1:1; // 1 IPC1 Request from CPU2 to CPU1 Uint16 IPC2:1; // 2 IPC2 Request from CPU2 to CPU1 Uint16 IPC3:1; // 3 IPC3 Request from CPU2 to CPU1 Uint16 IPC4:1; // 4 IPC4 Request from CPU2 to CPU1 Uint16 IPC5:1; // 5 IPC5 Request from CPU2 to CPU1 Uint16 IPC6:1; // 6 IPC6 Request from CPU2 to CPU1 Uint16 IPC7:1; // 7 IPC7 Request from CPU2 to CPU1 Uint16 IPC8:1; // 8 IPC8 Request from CPU2 to CPU1 Uint16 IPC9:1; // 9 IPC9 Request from CPU2 to CPU1 Uint16 IPC10:1; // 10 IPC10 Request from CPU2 to CPU1 Uint16 IPC11:1; // 11 IPC11 Request from CPU2 to CPU1 Uint16 IPC12:1; // 12 IPC12 Request from CPU2 to CPU1 Uint16 IPC13:1; // 13 IPC13 Request from CPU2 to CPU1 Uint16 IPC14:1; // 14 IPC14 Request from CPU2 to CPU1 Uint16 IPC15:1; // 15 IPC15 Request from CPU2 to CPU1 Uint16 IPC16:1; // 16 IPC16 Request from CPU2 to CPU1 Uint16 IPC17:1; // 17 IPC17 Request from CPU2 to CPU1 Uint16 IPC18:1; // 18 IPC18 Request from CPU2 to CPU1 Uint16 IPC19:1; // 19 IPC19 Request from CPU2 to CPU1 Uint16 IPC20:1; // 20 IPC20 Request from CPU2 to CPU1 Uint16 IPC21:1; // 21 IPC21 Request from CPU2 to CPU1 Uint16 IPC22:1; // 22 IPC22 Request from CPU2 to CPU1 Uint16 IPC23:1; // 23 IPC23 Request from CPU2 to CPU1 Uint16 IPC24:1; // 24 IPC24 Request from CPU2 to CPU1 Uint16 IPC25:1; // 25 IPC25 Request from CPU2 to CPU1 Uint16 IPC26:1; // 26 IPC26 Request from CPU2 to CPU1 Uint16 IPC27:1; // 27 IPC27 Request from CPU2 to CPU1 Uint16 IPC28:1; // 28 IPC28 Request from CPU2 to CPU1 Uint16 IPC29:1; // 29 IPC29 Request from CPU2 to CPU1 Uint16 IPC30:1; // 30 IPC30 Request from CPU2 to CPU1 Uint16 IPC31:1; // 31 IPC31 Request from CPU2 to CPU1 }; union CPU2TOCPU1IPCSTS_REG { Uint32 all; struct CPU2TOCPU1IPCSTS_BITS bit; }; struct CPU1TOCPU2IPCSET_BITS { // bits description Uint16 IPC0:1; // 0 Set CPU1TOCPU2IPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Set CPU1TOCPU2IPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Set CPU1TOCPU2IPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Set CPU1TOCPU2IPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Set CPU1TOCPU2IPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Set CPU1TOCPU2IPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Set CPU1TOCPU2IPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Set CPU1TOCPU2IPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Set CPU1TOCPU2IPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Set CPU1TOCPU2IPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Set CPU1TOCPU2IPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Set CPU1TOCPU2IPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Set CPU1TOCPU2IPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Set CPU1TOCPU2IPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Set CPU1TOCPU2IPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Set CPU1TOCPU2IPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Set CPU1TOCPU2IPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Set CPU1TOCPU2IPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Set CPU1TOCPU2IPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Set CPU1TOCPU2IPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Set CPU1TOCPU2IPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Set CPU1TOCPU2IPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Set CPU1TOCPU2IPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Set CPU1TOCPU2IPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Set CPU1TOCPU2IPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Set CPU1TOCPU2IPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Set CPU1TOCPU2IPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Set CPU1TOCPU2IPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Set CPU1TOCPU2IPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Set CPU1TOCPU2IPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Set CPU1TOCPU2IPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Set CPU1TOCPU2IPCFLG.IPC31 Flag }; union CPU1TOCPU2IPCSET_REG { Uint32 all; struct CPU1TOCPU2IPCSET_BITS bit; }; struct CPU1TOCPU2IPCCLR_BITS { // bits description Uint16 IPC0:1; // 0 Clear CPU1TOCPU2IPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Clear CPU1TOCPU2IPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Clear CPU1TOCPU2IPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Clear CPU1TOCPU2IPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Clear CPU1TOCPU2IPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Clear CPU1TOCPU2IPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Clear CPU1TOCPU2IPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Clear CPU1TOCPU2IPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Clear CPU1TOCPU2IPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Clear CPU1TOCPU2IPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Clear CPU1TOCPU2IPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Clear CPU1TOCPU2IPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Clear CPU1TOCPU2IPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Clear CPU1TOCPU2IPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Clear CPU1TOCPU2IPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Clear CPU1TOCPU2IPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Clear CPU1TOCPU2IPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Clear CPU1TOCPU2IPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Clear CPU1TOCPU2IPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Clear CPU1TOCPU2IPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Clear CPU1TOCPU2IPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Clear CPU1TOCPU2IPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Clear CPU1TOCPU2IPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Clear CPU1TOCPU2IPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Clear CPU1TOCPU2IPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Clear CPU1TOCPU2IPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Clear CPU1TOCPU2IPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Clear CPU1TOCPU2IPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Clear CPU1TOCPU2IPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Clear CPU1TOCPU2IPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Clear CPU1TOCPU2IPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Clear CPU1TOCPU2IPCFLG.IPC31 Flag }; union CPU1TOCPU2IPCCLR_REG { Uint32 all; struct CPU1TOCPU2IPCCLR_BITS bit; }; struct CPU1TOCPU2IPCFLG_BITS { // bits description Uint16 IPC0:1; // 0 CPU1 to CPU2 IPC0 Flag Status Uint16 IPC1:1; // 1 CPU1 to CPU2 IPC1 Flag Status Uint16 IPC2:1; // 2 CPU1 to CPU2 IPC2 Flag Status Uint16 IPC3:1; // 3 CPU1 to CPU2 IPC3 Flag Status Uint16 IPC4:1; // 4 CPU1 to CPU2 IPC4 Flag Status Uint16 IPC5:1; // 5 CPU1 to CPU2 IPC5 Flag Status Uint16 IPC6:1; // 6 CPU1 to CPU2 IPC6 Flag Status Uint16 IPC7:1; // 7 CPU1 to CPU2 IPC7 Flag Status Uint16 IPC8:1; // 8 CPU1 to CPU2 IPC8 Flag Status Uint16 IPC9:1; // 9 CPU1 to CPU2 IPC9 Flag Status Uint16 IPC10:1; // 10 CPU1 to CPU2 IPC10 Flag Status Uint16 IPC11:1; // 11 CPU1 to CPU2 IPC11 Flag Status Uint16 IPC12:1; // 12 CPU1 to CPU2 IPC12 Flag Status Uint16 IPC13:1; // 13 CPU1 to CPU2 IPC13 Flag Status Uint16 IPC14:1; // 14 CPU1 to CPU2 IPC14 Flag Status Uint16 IPC15:1; // 15 CPU1 to CPU2 IPC15 Flag Status Uint16 IPC16:1; // 16 CPU1 to CPU2 IPC16 Flag Status Uint16 IPC17:1; // 17 CPU1 to CPU2 IPC17 Flag Status Uint16 IPC18:1; // 18 CPU1 to CPU2 IPC18 Flag Status Uint16 IPC19:1; // 19 CPU1 to CPU2 IPC19 Flag Status Uint16 IPC20:1; // 20 CPU1 to CPU2 IPC20 Flag Status Uint16 IPC21:1; // 21 CPU1 to CPU2 IPC21 Flag Status Uint16 IPC22:1; // 22 CPU1 to CPU2 IPC22 Flag Status Uint16 IPC23:1; // 23 CPU1 to CPU2 IPC23 Flag Status Uint16 IPC24:1; // 24 CPU1 to CPU2 IPC24 Flag Status Uint16 IPC25:1; // 25 CPU1 to CPU2 IPC25 Flag Status Uint16 IPC26:1; // 26 CPU1 to CPU2 IPC26 Flag Status Uint16 IPC27:1; // 27 CPU1 to CPU2 IPC27 Flag Status Uint16 IPC28:1; // 28 CPU1 to CPU2 IPC28 Flag Status Uint16 IPC29:1; // 29 CPU1 to CPU2 IPC29 Flag Status Uint16 IPC30:1; // 30 CPU1 to CPU2 IPC30 Flag Status Uint16 IPC31:1; // 31 CPU1 to CPU2 IPC31 Flag Status }; union CPU1TOCPU2IPCFLG_REG { Uint32 all; struct CPU1TOCPU2IPCFLG_BITS bit; }; struct CPU1TOCPU2_IPC_REGS_CPU1VIEW { union CPU1TOCPU2IPCACK_REG CPU1TOCPU2IPCACK; // CPU1TOCPU2IPCACK Register union CPU2TOCPU1IPCSTS_REG CPU2TOCPU1IPCSTS; // CPU2TOCPU1IPCSTS Register union CPU1TOCPU2IPCSET_REG CPU1TOCPU2IPCSET; // CPU1TOCPU2IPCSET Register union CPU1TOCPU2IPCCLR_REG CPU1TOCPU2IPCCLR; // CPU1TOCPU2IPCCLR Register union CPU1TOCPU2IPCFLG_REG CPU1TOCPU2IPCFLG; // CPU1TOCPU2IPCFLG Register Uint16 rsvd1[2]; // Reserved Uint32 IPCCOUNTERL; // IPCCOUNTERL Register Uint32 IPCCOUNTERH; // IPCCOUNTERH Register Uint32 CPU1TOCPU2IPCSENDCOM; // CPU1TOCPU2IPCSENDCOM Register Uint32 CPU1TOCPU2IPCSENDADDR; // CPU1TOCPU2IPCSENDADDR Register Uint32 CPU1TOCPU2IPCSENDDATA; // CPU1TOCPU2IPCSENDDATA Register Uint32 CPU2TOCPU1IPCREPLY; // CPU2TOCPU1IPCREPLY Register Uint32 CPU2TOCPU1IPCRECVCOM; // CPU2TOCPU1IPCRECVCOM Register Uint32 CPU2TOCPU1IPCRECVADDR; // CPU2TOCPU1IPCRECVADDR Register Uint32 CPU2TOCPU1IPCRECVDATA; // CPU2TOCPU1IPCRECVDATA Register Uint32 CPU1TOCPU2IPCREPLY; // CPU1TOCPU2IPCREPLY Register Uint32 CPU2TOCPU1IPCBOOTSTS; // CPU2TOCPU1IPCBOOTSTS Register Uint32 CPU1TOCPU2IPCBOOTMODE; // CPU1TOCPU2IPCBOOTMODE Register union PUMPREQUEST_REG PUMPREQUEST; // PUMPREQUEST Register }; struct CPU2TOCPU1IPCACK_BITS { // bits description Uint16 IPC0:1; // 0 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC0 bit Uint16 IPC1:1; // 1 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC1 bit Uint16 IPC2:1; // 2 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC2 bit Uint16 IPC3:1; // 3 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC3 bit Uint16 IPC4:1; // 4 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC4 bit Uint16 IPC5:1; // 5 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC5 bit Uint16 IPC6:1; // 6 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC6 bit Uint16 IPC7:1; // 7 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC7 bit Uint16 IPC8:1; // 8 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC8 bit Uint16 IPC9:1; // 9 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC9 bit Uint16 IPC10:1; // 10 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC10 bit Uint16 IPC11:1; // 11 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC11 bit Uint16 IPC12:1; // 12 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC12 bit Uint16 IPC13:1; // 13 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC13 bit Uint16 IPC14:1; // 14 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC14 bit Uint16 IPC15:1; // 15 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC15 bit Uint16 IPC16:1; // 16 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC16 bit Uint16 IPC17:1; // 17 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC17 bit Uint16 IPC18:1; // 18 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC18 bit Uint16 IPC19:1; // 19 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC19 bit Uint16 IPC20:1; // 20 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC20 bit Uint16 IPC21:1; // 21 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC21 bit Uint16 IPC22:1; // 22 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC22 bit Uint16 IPC23:1; // 23 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC23 bit Uint16 IPC24:1; // 24 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC24 bit Uint16 IPC25:1; // 25 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC25 bit Uint16 IPC26:1; // 26 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC26 bit Uint16 IPC27:1; // 27 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC27 bit Uint16 IPC28:1; // 28 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC28 bit Uint16 IPC29:1; // 29 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC29 bit Uint16 IPC30:1; // 30 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC30 bit Uint16 IPC31:1; // 31 Acknowledgement from CPU2 to CPU1TOCPU2IPCFLG.IPC31 bit }; union CPU2TOCPU1IPCACK_REG { Uint32 all; struct CPU2TOCPU1IPCACK_BITS bit; }; struct CPU1TOCPU2IPCSTS_BITS { // bits description Uint16 IPC0:1; // 0 IPC0 Request from CPU1 to CPU2 Uint16 IPC1:1; // 1 IPC1 Request from CPU1 to CPU2 Uint16 IPC2:1; // 2 IPC2 Request from CPU1 to CPU2 Uint16 IPC3:1; // 3 IPC3 Request from CPU1 to CPU2 Uint16 IPC4:1; // 4 IPC4 Request from CPU1 to CPU2 Uint16 IPC5:1; // 5 IPC5 Request from CPU1 to CPU2 Uint16 IPC6:1; // 6 IPC6 Request from CPU1 to CPU2 Uint16 IPC7:1; // 7 IPC7 Request from CPU1 to CPU2 Uint16 IPC8:1; // 8 IPC8 Request from CPU1 to CPU2 Uint16 IPC9:1; // 9 IPC9 Request from CPU1 to CPU2 Uint16 IPC10:1; // 10 IPC10 Request from CPU1 to CPU2 Uint16 IPC11:1; // 11 IPC11 Request from CPU1 to CPU2 Uint16 IPC12:1; // 12 IPC12 Request from CPU1 to CPU2 Uint16 IPC13:1; // 13 IPC13 Request from CPU1 to CPU2 Uint16 IPC14:1; // 14 IPC14 Request from CPU1 to CPU2 Uint16 IPC15:1; // 15 IPC15 Request from CPU1 to CPU2 Uint16 IPC16:1; // 16 IPC16 Request from CPU1 to CPU2 Uint16 IPC17:1; // 17 IPC17 Request from CPU1 to CPU2 Uint16 IPC18:1; // 18 IPC18 Request from CPU1 to CPU2 Uint16 IPC19:1; // 19 IPC19 Request from CPU1 to CPU2 Uint16 IPC20:1; // 20 IPC20 Request from CPU1 to CPU2 Uint16 IPC21:1; // 21 IPC21 Request from CPU1 to CPU2 Uint16 IPC22:1; // 22 IPC22 Request from CPU1 to CPU2 Uint16 IPC23:1; // 23 IPC23 Request from CPU1 to CPU2 Uint16 IPC24:1; // 24 IPC24 Request from CPU1 to CPU2 Uint16 IPC25:1; // 25 IPC25 Request from CPU1 to CPU2 Uint16 IPC26:1; // 26 IPC26 Request from CPU1 to CPU2 Uint16 IPC27:1; // 27 IPC27 Request from CPU1 to CPU2 Uint16 IPC28:1; // 28 IPC28 Request from CPU1 to CPU2 Uint16 IPC29:1; // 29 IPC29 Request from CPU1 to CPU2 Uint16 IPC30:1; // 30 IPC30 Request from CPU1 to CPU2 Uint16 IPC31:1; // 31 IPC31 Request from CPU1 to CPU2 }; union CPU1TOCPU2IPCSTS_REG { Uint32 all; struct CPU1TOCPU2IPCSTS_BITS bit; }; struct CPU2TOCPU1IPCSET_BITS { // bits description Uint16 IPC0:1; // 0 Set CPU2TOCPU1IPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Set CPU2TOCPU1IPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Set CPU2TOCPU1IPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Set CPU2TOCPU1IPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Set CPU2TOCPU1IPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Set CPU2TOCPU1IPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Set CPU2TOCPU1IPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Set CPU2TOCPU1IPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Set CPU2TOCPU1IPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Set CPU2TOCPU1IPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Set CPU2TOCPU1IPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Set CPU2TOCPU1IPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Set CPU2TOCPU1IPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Set CPU2TOCPU1IPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Set CPU2TOCPU1IPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Set CPU2TOCPU1IPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Set CPU2TOCPU1IPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Set CPU2TOCPU1IPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Set CPU2TOCPU1IPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Set CPU2TOCPU1IPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Set CPU2TOCPU1IPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Set CPU2TOCPU1IPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Set CPU2TOCPU1IPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Set CPU2TOCPU1IPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Set CPU2TOCPU1IPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Set CPU2TOCPU1IPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Set CPU2TOCPU1IPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Set CPU2TOCPU1IPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Set CPU2TOCPU1IPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Set CPU2TOCPU1IPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Set CPU2TOCPU1IPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Set CPU2TOCPU1IPCFLG.IPC31 Flag }; union CPU2TOCPU1IPCSET_REG { Uint32 all; struct CPU2TOCPU1IPCSET_BITS bit; }; struct CPU2TOCPU1IPCCLR_BITS { // bits description Uint16 IPC0:1; // 0 Clear CPU2TOCPU1IPCFLG.IPC0 Flag Uint16 IPC1:1; // 1 Clear CPU2TOCPU1IPCFLG.IPC1 Flag Uint16 IPC2:1; // 2 Clear CPU2TOCPU1IPCFLG.IPC2 Flag Uint16 IPC3:1; // 3 Clear CPU2TOCPU1IPCFLG.IPC3 Flag Uint16 IPC4:1; // 4 Clear CPU2TOCPU1IPCFLG.IPC4 Flag Uint16 IPC5:1; // 5 Clear CPU2TOCPU1IPCFLG.IPC5 Flag Uint16 IPC6:1; // 6 Clear CPU2TOCPU1IPCFLG.IPC6 Flag Uint16 IPC7:1; // 7 Clear CPU2TOCPU1IPCFLG.IPC7 Flag Uint16 IPC8:1; // 8 Clear CPU2TOCPU1IPCFLG.IPC8 Flag Uint16 IPC9:1; // 9 Clear CPU2TOCPU1IPCFLG.IPC9 Flag Uint16 IPC10:1; // 10 Clear CPU2TOCPU1IPCFLG.IPC10 Flag Uint16 IPC11:1; // 11 Clear CPU2TOCPU1IPCFLG.IPC11 Flag Uint16 IPC12:1; // 12 Clear CPU2TOCPU1IPCFLG.IPC12 Flag Uint16 IPC13:1; // 13 Clear CPU2TOCPU1IPCFLG.IPC13 Flag Uint16 IPC14:1; // 14 Clear CPU2TOCPU1IPCFLG.IPC14 Flag Uint16 IPC15:1; // 15 Clear CPU2TOCPU1IPCFLG.IPC15 Flag Uint16 IPC16:1; // 16 Clear CPU2TOCPU1IPCFLG.IPC16 Flag Uint16 IPC17:1; // 17 Clear CPU2TOCPU1IPCFLG.IPC17 Flag Uint16 IPC18:1; // 18 Clear CPU2TOCPU1IPCFLG.IPC18 Flag Uint16 IPC19:1; // 19 Clear CPU2TOCPU1IPCFLG.IPC19 Flag Uint16 IPC20:1; // 20 Clear CPU2TOCPU1IPCFLG.IPC20 Flag Uint16 IPC21:1; // 21 Clear CPU2TOCPU1IPCFLG.IPC21 Flag Uint16 IPC22:1; // 22 Clear CPU2TOCPU1IPCFLG.IPC22 Flag Uint16 IPC23:1; // 23 Clear CPU2TOCPU1IPCFLG.IPC23 Flag Uint16 IPC24:1; // 24 Clear CPU2TOCPU1IPCFLG.IPC24 Flag Uint16 IPC25:1; // 25 Clear CPU2TOCPU1IPCFLG.IPC25 Flag Uint16 IPC26:1; // 26 Clear CPU2TOCPU1IPCFLG.IPC26 Flag Uint16 IPC27:1; // 27 Clear CPU2TOCPU1IPCFLG.IPC27 Flag Uint16 IPC28:1; // 28 Clear CPU2TOCPU1IPCFLG.IPC28 Flag Uint16 IPC29:1; // 29 Clear CPU2TOCPU1IPCFLG.IPC29 Flag Uint16 IPC30:1; // 30 Clear CPU2TOCPU1IPCFLG.IPC30 Flag Uint16 IPC31:1; // 31 Clear CPU2TOCPU1IPCFLG.IPC31 Flag }; union CPU2TOCPU1IPCCLR_REG { Uint32 all; struct CPU2TOCPU1IPCCLR_BITS bit; }; struct CPU2TOCPU1IPCFLG_BITS { // bits description Uint16 IPC0:1; // 0 CPU2 to CPU1 IPC0 Flag Status Uint16 IPC1:1; // 1 CPU2 to CPU1 IPC1 Flag Status Uint16 IPC2:1; // 2 CPU2 to CPU1 IPC2 Flag Status Uint16 IPC3:1; // 3 CPU2 to CPU1 IPC3 Flag Status Uint16 IPC4:1; // 4 CPU2 to CPU1 IPC4 Flag Status Uint16 IPC5:1; // 5 CPU2 to CPU1 IPC5 Flag Status Uint16 IPC6:1; // 6 CPU2 to CPU1 IPC6 Flag Status Uint16 IPC7:1; // 7 CPU2 to CPU1 IPC7 Flag Status Uint16 IPC8:1; // 8 CPU2 to CPU1 IPC8 Flag Status Uint16 IPC9:1; // 9 CPU2 to CPU1 IPC9 Flag Status Uint16 IPC10:1; // 10 CPU2 to CPU1 IPC10 Flag Status Uint16 IPC11:1; // 11 CPU2 to CPU1 IPC11 Flag Status Uint16 IPC12:1; // 12 CPU2 to CPU1 IPC12 Flag Status Uint16 IPC13:1; // 13 CPU2 to CPU1 IPC13 Flag Status Uint16 IPC14:1; // 14 CPU2 to CPU1 IPC14 Flag Status Uint16 IPC15:1; // 15 CPU2 to CPU1 IPC15 Flag Status Uint16 IPC16:1; // 16 CPU2 to CPU1 IPC16 Flag Status Uint16 IPC17:1; // 17 CPU2 to CPU1 IPC17 Flag Status Uint16 IPC18:1; // 18 CPU2 to CPU1 IPC18 Flag Status Uint16 IPC19:1; // 19 CPU2 to CPU1 IPC19 Flag Status Uint16 IPC20:1; // 20 CPU2 to CPU1 IPC20 Flag Status Uint16 IPC21:1; // 21 CPU2 to CPU1 IPC21 Flag Status Uint16 IPC22:1; // 22 CPU2 to CPU1 IPC22 Flag Status Uint16 IPC23:1; // 23 CPU2 to CPU1 IPC23 Flag Status Uint16 IPC24:1; // 24 CPU2 to CPU1 IPC24 Flag Status Uint16 IPC25:1; // 25 CPU2 to CPU1 IPC25 Flag Status Uint16 IPC26:1; // 26 CPU2 to CPU1 IPC26 Flag Status Uint16 IPC27:1; // 27 CPU2 to CPU1 IPC27 Flag Status Uint16 IPC28:1; // 28 CPU2 to CPU1 IPC28 Flag Status Uint16 IPC29:1; // 29 CPU2 to CPU1 IPC29 Flag Status Uint16 IPC30:1; // 30 CPU2 to CPU1 IPC30 Flag Status Uint16 IPC31:1; // 31 CPU2 to CPU1 IPC31 Flag Status }; union CPU2TOCPU1IPCFLG_REG { Uint32 all; struct CPU2TOCPU1IPCFLG_BITS bit; }; struct CPU1TOCPU2_IPC_REGS_CPU2VIEW { union CPU2TOCPU1IPCACK_REG CPU2TOCPU1IPCACK; // CPU2TOCPU1IPCACK Register union CPU1TOCPU2IPCSTS_REG CPU1TOCPU2IPCSTS; // CPU1TOCPU2IPCSTS Register union CPU2TOCPU1IPCSET_REG CPU2TOCPU1IPCSET; // CPU2TOCPU1IPCSET Register union CPU2TOCPU1IPCCLR_REG CPU2TOCPU1IPCCLR; // CPU2TOCPU1IPCCLR Register union CPU2TOCPU1IPCFLG_REG CPU2TOCPU1IPCFLG; // CPU2TOCPU1IPCFLG Register Uint16 rsvd1[2]; // Reserved Uint32 IPCCOUNTERL; // IPCCOUNTERL Register Uint32 IPCCOUNTERH; // IPCCOUNTERH Register Uint32 CPU1TOCPU2IPCRECVCOM; // CPU1TOCPU2IPCRECVCOM Register Uint32 CPU1TOCPU2IPCRECVADDR; // CPU1TOCPU2IPCRECVADDR Register Uint32 CPU1TOCPU2IPCRECVDATA; // CPU1TOCPU2IPCRECVDATA Register Uint32 CPU2TOCPU1IPCREPLY; // CPU2TOCPU1IPCREPLY Register Uint32 CPU2TOCPU1IPCSENDCOM; // CPU2TOCPU1IPCSENDCOM Register Uint32 CPU2TOCPU1IPCSENDADDR; // CPU2TOCPU1IPCSENDADDR Register Uint32 CPU2TOCPU1IPCSENDDATA; // CPU2TOCPU1IPCSENDDATA Register Uint32 CPU1TOCPU2IPCREPLY; // CPU1TOCPU2IPCREPLY Register Uint32 CPU2TOCPU1IPCBOOTSTS; // CPU2TOCPU1IPCBOOTSTS Register Uint32 CPU1TOCPU2IPCBOOTMODE; // CPU1TOCPU2IPCBOOTMODE Register union PUMPREQUEST_REG PUMPREQUEST; // PUMPREQUEST Register }; extern volatile struct CPU1TOCPU2_IPC_REGS_CPU1VIEW Cpu1toCpu2IpcRegs; extern volatile struct CPU1TOCM_IPC_REGS_CPU1VIEW Cpu1toCmIpcRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_mcan.h // // TITLE: Definitions for the MCAN registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // MCAN Individual Register Bit Definitions: struct MCANSS_PID_BITS { // bits description Uint16 MINOR:6; // 5:0 Minor Revision Uint16 rsvd1:2; // 7:6 Reserved Uint16 MAJOR:3; // 10:8 Major Revision Uint16 rsvd2:5; // 15:11 Reserved Uint16 MODULE_ID:12; // 27:16 Module Identification Number Uint16 rsvd3:2; // 29:28 Reserved Uint16 SCHEME:2; // 31:30 PID Register Scheme }; union MCANSS_PID_REG { Uint32 all; struct MCANSS_PID_BITS bit; }; struct MCANSS_CTRL_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 DBGSUSP_FREE:1; // 3 Debug Suspend Free Uint16 WAKEUPREQEN:1; // 4 Wakeup Request Enable Uint16 AUTOWAKEUP:1; // 5 Automatic Wakeup Enable Uint16 EXT_TS_CNTR_EN:1; // 6 External Timestamp Counter Enable Uint16 rsvd2:9; // 15:7 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANSS_CTRL_REG { Uint32 all; struct MCANSS_CTRL_BITS bit; }; struct MCANSS_STAT_BITS { // bits description Uint16 RESET:1; // 0 Soft Reset Status Uint16 MEM_INIT_DONE:1; // 1 Memory Initialization Done Uint16 ENABLE_FDOE:1; // 2 Flexible Datarate Operation Enable Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_STAT_REG { Uint32 all; struct MCANSS_STAT_BITS bit; }; struct MCANSS_ICS_BITS { // bits description Uint16 EXT_TS_CNTR_OVFL:1; // 0 External Timestamp Counter Overflow Interrupt Status Clear Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_ICS_REG { Uint32 all; struct MCANSS_ICS_BITS bit; }; struct MCANSS_IRS_BITS { // bits description Uint16 EXT_TS_CNTR_OVFL:1; // 0 External Timestamp Counter Overflow Interrupt Status Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_IRS_REG { Uint32 all; struct MCANSS_IRS_BITS bit; }; struct MCANSS_IECS_BITS { // bits description Uint16 EXT_TS_CNTR_OVFL:1; // 0 External Timestamp Counter Overflow Interrupt Enable Clear Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_IECS_REG { Uint32 all; struct MCANSS_IECS_BITS bit; }; struct MCANSS_IE_BITS { // bits description Uint16 EXT_TS_CNTR_OVFL:1; // 0 External Timestamp Counter Overflow Interrupt Enable Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_IE_REG { Uint32 all; struct MCANSS_IE_BITS bit; }; struct MCANSS_IES_BITS { // bits description Uint16 EXT_TS_CNTR_OVFL:1; // 0 External Timestamp Counter Overflow Interrupt Enable Status Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_IES_REG { Uint32 all; struct MCANSS_IES_BITS bit; }; struct MCANSS_EOI_BITS { // bits description Uint16 EOI:8; // 7:0 External Timestamp Counter Overflow End of Interrupt Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_EOI_REG { Uint32 all; struct MCANSS_EOI_BITS bit; }; struct MCANSS_EXT_TS_PRESCALER_BITS { // bits description Uint32 PRESCALER:24; // 23:0 External Timestamp Prescaler Uint16 rsvd1:8; // 31:24 Reserved }; union MCANSS_EXT_TS_PRESCALER_REG { Uint32 all; struct MCANSS_EXT_TS_PRESCALER_BITS bit; }; struct MCANSS_EXT_TS_UNSERVICED_INTR_CNTR_BITS {// bits description Uint16 EXT_TS_INTR_CNTR:5; // 4:0 External Timestamp Counter Unserviced Rollover Interrupts Uint16 rsvd1:11; // 15:5 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANSS_EXT_TS_UNSERVICED_INTR_CNTR_REG { Uint32 all; struct MCANSS_EXT_TS_UNSERVICED_INTR_CNTR_BITS bit; }; struct MCANSS_REGS { union MCANSS_PID_REG MCANSS_PID; // MCAN Subsystem Revision Register union MCANSS_CTRL_REG MCANSS_CTRL; // MCAN Subsystem Control Register union MCANSS_STAT_REG MCANSS_STAT; // MCAN Subsystem Status Register union MCANSS_ICS_REG MCANSS_ICS; // MCAN Subsystem Interrupt Clear Shadow Register union MCANSS_IRS_REG MCANSS_IRS; // MCAN Subsystem Interrupt Raw Satus Register union MCANSS_IECS_REG MCANSS_IECS; // MCAN Subsystem Interrupt Enable Clear Shadow Register union MCANSS_IE_REG MCANSS_IE; // MCAN Subsystem Interrupt Enable Register union MCANSS_IES_REG MCANSS_IES; // MCAN Subsystem Interrupt Enable Status union MCANSS_EOI_REG MCANSS_EOI; // MCAN Subsystem End of Interrupt union MCANSS_EXT_TS_PRESCALER_REG MCANSS_EXT_TS_PRESCALER; // MCAN Subsystem External Timestamp Prescaler 0 union MCANSS_EXT_TS_UNSERVICED_INTR_CNTR_REG MCANSS_EXT_TS_UNSERVICED_INTR_CNTR;// MCAN Subsystem External Timestamp Unserviced Interrupts Counter }; struct MCAN_CREL_BITS { // bits description Uint16 DAY:8; // 7:0 Time Stamp Day Uint16 MON:8; // 15:8 Time Stamp Month Uint16 YEAR:4; // 19:16 Time Stamp Year Uint16 SUBSTEP:4; // 23:20 Sub-Step of Core Release Uint16 STEP:4; // 27:24 Step of Core Release Uint16 REL:4; // 31:28 Core Release }; union MCAN_CREL_REG { Uint32 all; struct MCAN_CREL_BITS bit; }; struct MCAN_DBTP_BITS { // bits description Uint16 DSJW:4; // 3:0 Data Resynchronization Jump Width Uint16 DTSEG2:4; // 7:4 Data Time Segment After Sample Point Uint16 DTSEG1:5; // 12:8 Data Time Segment Before Sample Point Uint16 rsvd1:3; // 15:13 Reserved Uint16 DBRP:5; // 20:16 Data Bit Rate Prescaler Uint16 rsvd2:2; // 22:21 Reserved Uint16 TDC:1; // 23 Transmitter Delay Compensation Uint16 rsvd3:8; // 31:24 Reserved }; union MCAN_DBTP_REG { Uint32 all; struct MCAN_DBTP_BITS bit; }; struct MCAN_TEST_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 LBCK:1; // 4 Loop Back Mode Uint16 TX:2; // 6:5 Control of Transmit Pin Uint16 RX:1; // 7 Receive Pin Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCAN_TEST_REG { Uint32 all; struct MCAN_TEST_BITS bit; }; struct MCAN_RWD_BITS { // bits description Uint16 WDC:8; // 7:0 Watchdog Configuration Uint16 WDV:8; // 15:8 Watchdog Value Uint16 rsvd1:16; // 31:16 Reserved }; union MCAN_RWD_REG { Uint32 all; struct MCAN_RWD_BITS bit; }; struct MCAN_CCCR_BITS { // bits description Uint16 INIT:1; // 0 Initialization Uint16 CCE:1; // 1 Configuration Change Enable Uint16 ASM:1; // 2 Restricted Operation Mode Uint16 CSA:1; // 3 Clock Stop Acknowledge Uint16 CSR:1; // 4 Clock Stop Request Uint16 MON:1; // 5 Bus Monitoring Mode Uint16 DAR:1; // 6 Disable Automatic Retransmission Uint16 TEST:1; // 7 Test Mode Enable Uint16 FDOE:1; // 8 Flexible Datarate Operation Enable Uint16 BRSE:1; // 9 Bit Rate Switch Enable Uint16 rsvd1:2; // 11:10 Reserved Uint16 PXHD:1; // 12 Protocol Exception Handling Disable Uint16 EFBI:1; // 13 Edge Filtering During Bus Integration Uint16 TXP:1; // 14 Transmit Pause Uint16 NISO:1; // 15 Non-ISO Operation Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_CCCR_REG { Uint32 all; struct MCAN_CCCR_BITS bit; }; struct MCAN_NBTP_BITS { // bits description Uint16 NTSEG2:7; // 6:0 Nominal Time Segment After Sample Point Uint16 rsvd1:1; // 7 Reserved Uint16 NTSEG1:8; // 15:8 Nominal Time Segment Before Sample Point Uint16 NBRP:9; // 24:16 Nominal Bit Rate Prescaler Uint16 NSJW:7; // 31:25 Nominal (Re)Synchronization Jump Width }; union MCAN_NBTP_REG { Uint32 all; struct MCAN_NBTP_BITS bit; }; struct MCAN_TSCC_BITS { // bits description Uint16 TSS:2; // 1:0 Timestamp Select Uint16 rsvd1:14; // 15:2 Reserved Uint16 TCP:4; // 19:16 Timestamp Counter Prescaler Uint16 rsvd2:12; // 31:20 Reserved }; union MCAN_TSCC_REG { Uint32 all; struct MCAN_TSCC_BITS bit; }; struct MCAN_TSCV_BITS { // bits description Uint16 TSC:16; // 15:0 Timestamp Counter Uint16 rsvd1:16; // 31:16 Reserved }; union MCAN_TSCV_REG { Uint32 all; struct MCAN_TSCV_BITS bit; }; struct MCAN_TOCC_BITS { // bits description Uint16 ETOC:1; // 0 Enable Timeout Counter Uint16 TOS:2; // 2:1 Timeout Select Uint16 rsvd1:13; // 15:3 Reserved Uint16 TOP:16; // 31:16 Timeout Period }; union MCAN_TOCC_REG { Uint32 all; struct MCAN_TOCC_BITS bit; }; struct MCAN_TOCV_BITS { // bits description Uint16 TOC:16; // 15:0 Timeout Counter Uint16 rsvd1:16; // 31:16 Reserved }; union MCAN_TOCV_REG { Uint32 all; struct MCAN_TOCV_BITS bit; }; struct MCAN_ECR_BITS { // bits description Uint16 TEC:8; // 7:0 Transmit Error Counter Uint16 REC:7; // 14:8 Receive Error Counter Uint16 RP:1; // 15 Receive Error Passive Uint16 CEL:8; // 23:16 CAN Error Logging Uint16 rsvd1:8; // 31:24 Reserved }; union MCAN_ECR_REG { Uint32 all; struct MCAN_ECR_BITS bit; }; struct MCAN_PSR_BITS { // bits description Uint16 LEC:3; // 2:0 Last Error Code Uint16 ACT:2; // 4:3 Node Activity Uint16 EP:1; // 5 Error Passive Uint16 EW:1; // 6 Warning Status Uint16 BO:1; // 7 Bus_Off Status Uint16 DLEC:3; // 10:8 Data Phase Last Error Code Uint16 RESI:1; // 11 ESI Flag of Last Received CAN FD Message Uint16 RBRS:1; // 12 BRS Flag of Last Received CAN FD Message Uint16 RFDF:1; // 13 Received a CAN FD Message Uint16 PXE:1; // 14 Protocol Exception Event Uint16 rsvd1:1; // 15 Reserved Uint16 TDCV:7; // 22:16 Transmitter Delay Compensation Value Uint16 rsvd2:9; // 31:23 Reserved }; union MCAN_PSR_REG { Uint32 all; struct MCAN_PSR_BITS bit; }; struct MCAN_TDCR_BITS { // bits description Uint16 TDCF:7; // 6:0 Transmitter Delay Compensation Filter Window Length Uint16 rsvd1:1; // 7 Reserved Uint16 TDCO:7; // 14:8 Transmitter Delay Compensation Offset Uint16 rsvd2:1; // 15 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCAN_TDCR_REG { Uint32 all; struct MCAN_TDCR_BITS bit; }; struct MCAN_IR_BITS { // bits description Uint16 RF0N:1; // 0 Rx FIFO 0 New Message Uint16 RF0W:1; // 1 Rx FIFO 0 Watermark Reached Uint16 RF0F:1; // 2 Rx FIFO 0 Full Uint16 RF0L:1; // 3 Rx FIFO 0 Message Lost Uint16 RF1N:1; // 4 Rx FIFO 1 New Message Uint16 RF1W:1; // 5 Rx FIFO 1 Watermark Reached Uint16 RF1F:1; // 6 Rx FIFO 1 Full Uint16 RF1L:1; // 7 Rx FIFO 1 Message Lost Uint16 HPM:1; // 8 High Priority Message Uint16 TC:1; // 9 Transmission Completed Uint16 TCF:1; // 10 Transmission Cancellation Finished Uint16 TFE:1; // 11 Tx FIFO Empty Uint16 TEFN:1; // 12 Tx Event FIFO New Entry Uint16 TEFW:1; // 13 Tx Event FIFO Watermark Reached Uint16 TEFF:1; // 14 Tx Event FIFO Full Uint16 TEFL:1; // 15 Tx Event FIFO Element Lost Uint16 TSW:1; // 16 Timestamp Wraparound Uint16 MRAF:1; // 17 Message RAM Access Failure Uint16 TOO:1; // 18 Timeout Occurred Uint16 DRX:1; // 19 Message Stored to Dedicated Rx Buffer Uint16 rsvd1:1; // 20 Reserved Uint16 BEU:1; // 21 Bit Error Uncorrected Uint16 ELO:1; // 22 Error Logging Overflow Uint16 EP:1; // 23 Error Passive Uint16 EW:1; // 24 Warning Status Uint16 BO:1; // 25 Bus_Off Status Uint16 WDI:1; // 26 Watchdog Interrupt Uint16 PEA:1; // 27 Protocol Error in Arbitration Phase Uint16 PED:1; // 28 Protocol Error in Data Phase Uint16 ARA:1; // 29 Access to Reserved Address Uint16 rsvd2:1; // 30 Reserved Uint16 rsvd3:1; // 31 Reserved }; union MCAN_IR_REG { Uint32 all; struct MCAN_IR_BITS bit; }; struct MCAN_IE_BITS { // bits description Uint16 RF0NE:1; // 0 Rx FIFO 0 New Message Enable Uint16 RF0WE:1; // 1 Rx FIFO 0 Watermark Reached Enable Uint16 RF0FE:1; // 2 Rx FIFO 0 Full Enable Uint16 RF0LE:1; // 3 Rx FIFO 0 Message Lost Enable Uint16 RF1NE:1; // 4 Rx FIFO 1 New Message Enable Uint16 RF1WE:1; // 5 Rx FIFO 1 Watermark Reached Enable Uint16 RF1FE:1; // 6 Rx FIFO 1 Full Enable Uint16 RF1LE:1; // 7 Rx FIFO 1 Message Lost Enable Uint16 HPME:1; // 8 High Priority Message Enable Uint16 TCE:1; // 9 Transmission Completed Enable Uint16 TCFE:1; // 10 Transmission Cancellation Finished Enable Uint16 TFEE:1; // 11 Tx FIFO Empty Enable Uint16 TEFNE:1; // 12 Tx Event FIFO New Entry Enable Uint16 TEFWE:1; // 13 Tx Event FIFO Watermark Reached Enable Uint16 TEFFE:1; // 14 Tx Event FIFO Full Enable Uint16 TEFLE:1; // 15 Tx Event FIFO Element Lost Enable Uint16 TSWE:1; // 16 Timestamp Wraparound Enable Uint16 MRAFE:1; // 17 Message RAM Access Failure Enable Uint16 TOOE:1; // 18 Timeout Occurred Enable Uint16 DRXE:1; // 19 Message Stored to Dedicated Rx Buffer Enable Uint16 BECE:1; // 20 Bit Error Corrected Enable Uint16 BEUE:1; // 21 Bit Error Uncorrected Enable Uint16 ELOE:1; // 22 Error Logging Overflow Enable Uint16 EPE:1; // 23 Error Passive Enable Uint16 EWE:1; // 24 Warning Status Enable Uint16 BOE:1; // 25 Bus_Off Status Enable Uint16 WDIE:1; // 26 Watchdog Interrupt Enable Uint16 PEAE:1; // 27 Protocol Error in Arbitration Phase Enable Uint16 PEDE:1; // 28 Protocol Error in Data Phase Enable Uint16 ARAE:1; // 29 Access to Reserved Address Enable Uint16 rsvd1:2; // 31:30 Reserved }; union MCAN_IE_REG { Uint32 all; struct MCAN_IE_BITS bit; }; struct MCAN_ILS_BITS { // bits description Uint16 RF0NL:1; // 0 Rx FIFO 0 New Message Line Uint16 RF0WL:1; // 1 Rx FIFO 0 Watermark Reached Line Uint16 RF0FL:1; // 2 Rx FIFO 0 Full Line Uint16 RF0LL:1; // 3 Rx FIFO 0 Message Lost Line Uint16 RF1NL:1; // 4 Rx FIFO 1 New Message Line Uint16 RF1WL:1; // 5 Rx FIFO 1 Watermark Reached Line Uint16 RF1FL:1; // 6 Rx FIFO 1 Full Line Uint16 RF1LL:1; // 7 Rx FIFO 1 Message Lost Line Uint16 HPML:1; // 8 High Priority Message Line Uint16 TCL:1; // 9 Transmission Completed Line Uint16 TCFL:1; // 10 Transmission Cancellation Finished Line Uint16 TFEL:1; // 11 Tx FIFO Empty Line Uint16 TEFNL:1; // 12 Tx Event FIFO New Entry Line Uint16 TEFWL:1; // 13 Tx Event FIFO Watermark Reached Line Uint16 TEFFL:1; // 14 Tx Event FIFO Full Line Uint16 TEFLL:1; // 15 Tx Event FIFO Element Lost Line Uint16 TSWL:1; // 16 Timestamp Wraparound Line Uint16 MRAFL:1; // 17 Message RAM Access Failure Line Uint16 TOOL:1; // 18 Timeout Occurred Line Uint16 DRXL:1; // 19 Message Stored to Dedicated Rx Buffer Line Uint16 BECL:1; // 20 Bit Error Corrected Line Uint16 BEUL:1; // 21 Bit Error Uncorrected Line Uint16 ELOL:1; // 22 Error Logging Overflow Line Uint16 EPL:1; // 23 Error Passive Line Uint16 EWL:1; // 24 Warning Status Line Uint16 BOL:1; // 25 Bus_Off Status Line Uint16 WDIL:1; // 26 Watchdog Interrupt Line Uint16 PEAL:1; // 27 Protocol Error in Arbitration Phase Line Uint16 PEDL:1; // 28 Protocol Error in Data Phase Line Uint16 ARAL:1; // 29 Access to Reserved Address Line Uint16 rsvd1:2; // 31:30 Reserved }; union MCAN_ILS_REG { Uint32 all; struct MCAN_ILS_BITS bit; }; struct MCAN_ILE_BITS { // bits description Uint16 EINT0:1; // 0 Enable Interrupt Line 0 Uint16 EINT1:1; // 1 Enable Interrupt Line 1 Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_ILE_REG { Uint32 all; struct MCAN_ILE_BITS bit; }; struct MCAN_GFC_BITS { // bits description Uint16 RRFE:1; // 0 Reject Remote Frames Extended Uint16 RRFS:1; // 1 Reject Remote Frames Standard Uint16 ANFE:2; // 3:2 Accept Non-matching Frames Extended Uint16 ANFS:2; // 5:4 Accept Non-matching Frames Standard Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_GFC_REG { Uint32 all; struct MCAN_GFC_BITS bit; }; struct MCAN_SIDFC_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 FLSSA:14; // 15:2 Filter List Standard Start Address Uint16 LSS:8; // 23:16 List Size Standard Uint16 rsvd2:8; // 31:24 Reserved }; union MCAN_SIDFC_REG { Uint32 all; struct MCAN_SIDFC_BITS bit; }; struct MCAN_XIDFC_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 FLESA:14; // 15:2 Filter List Extended Start Address Uint16 LSE:7; // 22:16 List Size Extended Uint16 rsvd2:9; // 31:23 Reserved }; union MCAN_XIDFC_REG { Uint32 all; struct MCAN_XIDFC_BITS bit; }; struct MCAN_XIDAM_BITS { // bits description Uint32 EIDM:29; // 28:0 Extended ID Mask Uint16 rsvd1:3; // 31:29 Reserved }; union MCAN_XIDAM_REG { Uint32 all; struct MCAN_XIDAM_BITS bit; }; struct MCAN_HPMS_BITS { // bits description Uint16 BIDX:6; // 5:0 Buffer Index Uint16 MSI:2; // 7:6 Message Storage Indicator Uint16 FIDX:7; // 14:8 Filter Index Uint16 FLST:1; // 15 Filter List Uint16 rsvd1:16; // 31:16 Reserved }; union MCAN_HPMS_REG { Uint32 all; struct MCAN_HPMS_BITS bit; }; struct MCAN_NDAT1_BITS { // bits description Uint16 ND0:1; // 0 New Data RX Buffer 0 Uint16 ND1:1; // 1 New Data RX Buffer 1 Uint16 ND2:1; // 2 New Data RX Buffer 2 Uint16 ND3:1; // 3 New Data RX Buffer 3 Uint16 ND4:1; // 4 New Data RX Buffer 4 Uint16 ND5:1; // 5 New Data RX Buffer 5 Uint16 ND6:1; // 6 New Data RX Buffer 6 Uint16 ND7:1; // 7 New Data RX Buffer 7 Uint16 ND8:1; // 8 New Data RX Buffer 8 Uint16 ND9:1; // 9 New Data RX Buffer 9 Uint16 ND10:1; // 10 New Data RX Buffer 10 Uint16 ND11:1; // 11 New Data RX Buffer 11 Uint16 ND12:1; // 12 New Data RX Buffer 12 Uint16 ND13:1; // 13 New Data RX Buffer 13 Uint16 ND14:1; // 14 New Data RX Buffer 14 Uint16 ND15:1; // 15 New Data RX Buffer 15 Uint16 ND16:1; // 16 New Data RX Buffer 16 Uint16 ND17:1; // 17 New Data RX Buffer 17 Uint16 ND18:1; // 18 New Data RX Buffer 18 Uint16 ND19:1; // 19 New Data RX Buffer 19 Uint16 ND20:1; // 20 New Data RX Buffer 20 Uint16 ND21:1; // 21 New Data RX Buffer 21 Uint16 ND22:1; // 22 New Data RX Buffer 22 Uint16 ND23:1; // 23 New Data RX Buffer 23 Uint16 ND24:1; // 24 New Data RX Buffer 24 Uint16 ND25:1; // 25 New Data RX Buffer 25 Uint16 ND26:1; // 26 New Data RX Buffer 26 Uint16 ND27:1; // 27 New Data RX Buffer 27 Uint16 ND28:1; // 28 New Data RX Buffer 28 Uint16 ND29:1; // 29 New Data RX Buffer 29 Uint16 ND30:1; // 30 New Data RX Buffer 30 Uint16 ND31:1; // 31 New Data RX Buffer 31 }; union MCAN_NDAT1_REG { Uint32 all; struct MCAN_NDAT1_BITS bit; }; struct MCAN_NDAT2_BITS { // bits description Uint16 ND32:1; // 0 New Data RX Buffer 32 Uint16 ND33:1; // 1 New Data RX Buffer 33 Uint16 ND34:1; // 2 New Data RX Buffer 34 Uint16 ND35:1; // 3 New Data RX Buffer 35 Uint16 ND36:1; // 4 New Data RX Buffer 36 Uint16 ND37:1; // 5 New Data RX Buffer 37 Uint16 ND38:1; // 6 New Data RX Buffer 38 Uint16 ND39:1; // 7 New Data RX Buffer 39 Uint16 ND40:1; // 8 New Data RX Buffer 40 Uint16 ND41:1; // 9 New Data RX Buffer 41 Uint16 ND42:1; // 10 New Data RX Buffer 42 Uint16 ND43:1; // 11 New Data RX Buffer 43 Uint16 ND44:1; // 12 New Data RX Buffer 44 Uint16 ND45:1; // 13 New Data RX Buffer 45 Uint16 ND46:1; // 14 New Data RX Buffer 46 Uint16 ND47:1; // 15 New Data RX Buffer 47 Uint16 ND48:1; // 16 New Data RX Buffer 48 Uint16 ND49:1; // 17 New Data RX Buffer 49 Uint16 ND50:1; // 18 New Data RX Buffer 50 Uint16 ND51:1; // 19 New Data RX Buffer 51 Uint16 ND52:1; // 20 New Data RX Buffer 52 Uint16 ND53:1; // 21 New Data RX Buffer 53 Uint16 ND54:1; // 22 New Data RX Buffer 54 Uint16 ND55:1; // 23 New Data RX Buffer 55 Uint16 ND56:1; // 24 New Data RX Buffer 56 Uint16 ND57:1; // 25 New Data RX Buffer 57 Uint16 ND58:1; // 26 New Data RX Buffer 58 Uint16 ND59:1; // 27 New Data RX Buffer 59 Uint16 ND60:1; // 28 New Data RX Buffer 60 Uint16 ND61:1; // 29 New Data RX Buffer 61 Uint16 ND62:1; // 30 New Data RX Buffer 62 Uint16 ND63:1; // 31 New Data RX Buffer 63 }; union MCAN_NDAT2_REG { Uint32 all; struct MCAN_NDAT2_BITS bit; }; struct MCAN_RXF0C_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 F0SA:14; // 15:2 Rx FIFO 0 Start Address Uint16 F0S:7; // 22:16 Rx FIFO 0 Size Uint16 rsvd2:1; // 23 Reserved Uint16 F0WM:7; // 30:24 Rx FIFO 0 Watermark Uint16 F0OM:1; // 31 FIFO 0 Operation Mode }; union MCAN_RXF0C_REG { Uint32 all; struct MCAN_RXF0C_BITS bit; }; struct MCAN_RXF0S_BITS { // bits description Uint16 F0FL:7; // 6:0 Rx FIFO 0 Fill Level Uint16 rsvd1:1; // 7 Reserved Uint16 F0GI:6; // 13:8 Rx FIFO 0 Get Index Uint16 rsvd2:2; // 15:14 Reserved Uint16 F0PI:6; // 21:16 Rx FIFO 0 Put Index Uint16 rsvd3:2; // 23:22 Reserved Uint16 F0F:1; // 24 Rx FIFO 0 Full Uint16 RF0L:1; // 25 Rx FIFO 0 Message Lost Uint16 rsvd4:6; // 31:26 Reserved }; union MCAN_RXF0S_REG { Uint32 all; struct MCAN_RXF0S_BITS bit; }; struct MCAN_RXF0A_BITS { // bits description Uint16 F0AI:6; // 5:0 Rx FIFO 0 Acknowledge Index Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_RXF0A_REG { Uint32 all; struct MCAN_RXF0A_BITS bit; }; struct MCAN_RXBC_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 RBSA:14; // 15:2 Rx Buffer Start Address Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_RXBC_REG { Uint32 all; struct MCAN_RXBC_BITS bit; }; struct MCAN_RXF1C_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 F1SA:14; // 15:2 Rx FIFO 1 Start Address Uint16 F1S:7; // 22:16 Rx FIFO 1 Size Uint16 rsvd2:1; // 23 Reserved Uint16 F1WM:7; // 30:24 Rx FIFO 1 Watermark Uint16 F1OM:1; // 31 FIFO 1 Operation Mode }; union MCAN_RXF1C_REG { Uint32 all; struct MCAN_RXF1C_BITS bit; }; struct MCAN_RXF1S_BITS { // bits description Uint16 F1FL:7; // 6:0 Rx FIFO 1 Fill Level Uint16 rsvd1:1; // 7 Reserved Uint16 F1GI:6; // 13:8 Rx FIFO 1 Get Index Uint16 rsvd2:2; // 15:14 Reserved Uint16 F1PI:6; // 21:16 Rx FIFO 1 Put Index Uint16 rsvd3:2; // 23:22 Reserved Uint16 F1F:1; // 24 Rx FIFO 1 Full Uint16 RF1L:1; // 25 Rx FIFO 1 Message Lost Uint16 rsvd4:4; // 29:26 Reserved Uint16 DMS:2; // 31:30 Debug Message Status }; union MCAN_RXF1S_REG { Uint32 all; struct MCAN_RXF1S_BITS bit; }; struct MCAN_RXF1A_BITS { // bits description Uint16 F1AI:6; // 5:0 Rx FIFO 1 Acknowledge Index Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_RXF1A_REG { Uint32 all; struct MCAN_RXF1A_BITS bit; }; struct MCAN_RXESC_BITS { // bits description Uint16 F0DS:3; // 2:0 Rx FIFO 0 Data Field Size Uint16 rsvd1:1; // 3 Reserved Uint16 F1DS:3; // 6:4 Rx FIFO 1 Data Field Size Uint16 rsvd2:1; // 7 Reserved Uint16 RBDS:3; // 10:8 Rx Buffer Data Field Size Uint16 rsvd3:5; // 15:11 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union MCAN_RXESC_REG { Uint32 all; struct MCAN_RXESC_BITS bit; }; struct MCAN_TXBC_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 TBSA:14; // 15:2 Tx Buffers Start Address Uint16 NDTB:6; // 21:16 Number of Dedicated Transmit Buffers Uint16 rsvd2:2; // 23:22 Reserved Uint16 TFQS:6; // 29:24 Transmit FIFO/Queue Size Uint16 TFQM:1; // 30 Tx FIFO/Queue Mode Uint16 rsvd3:1; // 31 Reserved }; union MCAN_TXBC_REG { Uint32 all; struct MCAN_TXBC_BITS bit; }; struct MCAN_TXFQS_BITS { // bits description Uint16 TFFL:6; // 5:0 Tx FIFO Free Level Uint16 rsvd1:2; // 7:6 Reserved Uint16 TFGI:5; // 12:8 Tx FIFO Get Index Uint16 rsvd2:3; // 15:13 Reserved Uint16 TFQP:5; // 20:16 Tx FIFO/Queue Put Index Uint16 TFQF:1; // 21 Tx FIFO/Queue Full Uint16 rsvd3:10; // 31:22 Reserved }; union MCAN_TXFQS_REG { Uint32 all; struct MCAN_TXFQS_BITS bit; }; struct MCAN_TXESC_BITS { // bits description Uint16 TBDS:3; // 2:0 Tx Buffer Data Field Size Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_TXESC_REG { Uint32 all; struct MCAN_TXESC_BITS bit; }; struct MCAN_TXBRP_BITS { // bits description Uint16 TRP0:1; // 0 Transmission Request Pending 0 Uint16 TRP1:1; // 1 Transmission Request Pending 1 Uint16 TRP2:1; // 2 Transmission Request Pending 2 Uint16 TRP3:1; // 3 Transmission Request Pending 3 Uint16 TRP4:1; // 4 Transmission Request Pending 4 Uint16 TRP5:1; // 5 Transmission Request Pending 5 Uint16 TRP6:1; // 6 Transmission Request Pending 6 Uint16 TRP7:1; // 7 Transmission Request Pending 7 Uint16 TRP8:1; // 8 Transmission Request Pending 8 Uint16 TRP9:1; // 9 Transmission Request Pending 9 Uint16 TRP10:1; // 10 Transmission Request Pending 10 Uint16 TRP11:1; // 11 Transmission Request Pending 11 Uint16 TRP12:1; // 12 Transmission Request Pending 12 Uint16 TRP13:1; // 13 Transmission Request Pending 13 Uint16 TRP14:1; // 14 Transmission Request Pending 14 Uint16 TRP15:1; // 15 Transmission Request Pending 15 Uint16 TRP16:1; // 16 Transmission Request Pending 16 Uint16 TRP17:1; // 17 Transmission Request Pending 17 Uint16 TRP18:1; // 18 Transmission Request Pending 18 Uint16 TRP19:1; // 19 Transmission Request Pending 19 Uint16 TRP20:1; // 20 Transmission Request Pending 20 Uint16 TRP21:1; // 21 Transmission Request Pending 21 Uint16 TRP22:1; // 22 Transmission Request Pending 22 Uint16 TRP23:1; // 23 Transmission Request Pending 23 Uint16 TRP24:1; // 24 Transmission Request Pending 24 Uint16 TRP25:1; // 25 Transmission Request Pending 25 Uint16 TRP26:1; // 26 Transmission Request Pending 26 Uint16 TRP27:1; // 27 Transmission Request Pending 27 Uint16 TRP28:1; // 28 Transmission Request Pending 28 Uint16 TRP29:1; // 29 Transmission Request Pending 29 Uint16 TRP30:1; // 30 Transmission Request Pending 30 Uint16 TRP31:1; // 31 Transmission Request Pending 31 }; union MCAN_TXBRP_REG { Uint32 all; struct MCAN_TXBRP_BITS bit; }; struct MCAN_TXBAR_BITS { // bits description Uint16 _AR0:1; // 0 Add Request 0 Uint16 _AR1:1; // 1 Add Request 1 Uint16 _AR2:1; // 2 Add Request 2 Uint16 _AR3:1; // 3 Add Request 3 Uint16 _AR4:1; // 4 Add Request 4 Uint16 _AR5:1; // 5 Add Request 5 Uint16 _AR6:1; // 6 Add Request 6 Uint16 _AR7:1; // 7 Add Request 7 Uint16 _AR8:1; // 8 Add Request 8 Uint16 _AR9:1; // 9 Add Request 9 Uint16 _AR10:1; // 10 Add Request 10 Uint16 _AR11:1; // 11 Add Request 11 Uint16 _AR12:1; // 12 Add Request 12 Uint16 _AR13:1; // 13 Add Request 13 Uint16 _AR14:1; // 14 Add Request 14 Uint16 _AR15:1; // 15 Add Request 15 Uint16 _AR16:1; // 16 Add Request 16 Uint16 _AR17:1; // 17 Add Request 17 Uint16 _AR18:1; // 18 Add Request 18 Uint16 _AR19:1; // 19 Add Request 19 Uint16 _AR20:1; // 20 Add Request 20 Uint16 _AR21:1; // 21 Add Request 21 Uint16 _AR22:1; // 22 Add Request 22 Uint16 _AR23:1; // 23 Add Request 23 Uint16 _AR24:1; // 24 Add Request 24 Uint16 _AR25:1; // 25 Add Request 25 Uint16 _AR26:1; // 26 Add Request 26 Uint16 _AR27:1; // 27 Add Request 27 Uint16 _AR28:1; // 28 Add Request 28 Uint16 _AR29:1; // 29 Add Request 29 Uint16 _AR30:1; // 30 Add Request 30 Uint16 _AR31:1; // 31 Add Request 31 }; union MCAN_TXBAR_REG { Uint32 all; struct MCAN_TXBAR_BITS bit; }; struct MCAN_TXBCR_BITS { // bits description Uint16 CR0:1; // 0 Cancellation Request 0 Uint16 CR1:1; // 1 Cancellation Request 1 Uint16 CR2:1; // 2 Cancellation Request 2 Uint16 CR3:1; // 3 Cancellation Request 3 Uint16 CR4:1; // 4 Cancellation Request 4 Uint16 CR5:1; // 5 Cancellation Request 5 Uint16 CR6:1; // 6 Cancellation Request 6 Uint16 CR7:1; // 7 Cancellation Request 7 Uint16 CR8:1; // 8 Cancellation Request 8 Uint16 CR9:1; // 9 Cancellation Request 9 Uint16 CR10:1; // 10 Cancellation Request 10 Uint16 CR11:1; // 11 Cancellation Request 11 Uint16 CR12:1; // 12 Cancellation Request 12 Uint16 CR13:1; // 13 Cancellation Request 13 Uint16 CR14:1; // 14 Cancellation Request 14 Uint16 CR15:1; // 15 Cancellation Request 15 Uint16 CR16:1; // 16 Cancellation Request 16 Uint16 CR17:1; // 17 Cancellation Request 17 Uint16 CR18:1; // 18 Cancellation Request 18 Uint16 CR19:1; // 19 Cancellation Request 19 Uint16 CR20:1; // 20 Cancellation Request 20 Uint16 CR21:1; // 21 Cancellation Request 21 Uint16 CR22:1; // 22 Cancellation Request 22 Uint16 CR23:1; // 23 Cancellation Request 23 Uint16 CR24:1; // 24 Cancellation Request 24 Uint16 CR25:1; // 25 Cancellation Request 25 Uint16 CR26:1; // 26 Cancellation Request 26 Uint16 CR27:1; // 27 Cancellation Request 27 Uint16 CR28:1; // 28 Cancellation Request 28 Uint16 CR29:1; // 29 Cancellation Request 29 Uint16 CR30:1; // 30 Cancellation Request 30 Uint16 CR31:1; // 31 Cancellation Request 31 }; union MCAN_TXBCR_REG { Uint32 all; struct MCAN_TXBCR_BITS bit; }; struct MCAN_TXBTO_BITS { // bits description Uint16 TO0:1; // 0 Transmission Occurred 0 Uint16 TO1:1; // 1 Transmission Occurred 1 Uint16 TO2:1; // 2 Transmission Occurred 2 Uint16 TO3:1; // 3 Transmission Occurred 3 Uint16 TO4:1; // 4 Transmission Occurred 4 Uint16 TO5:1; // 5 Transmission Occurred 5 Uint16 TO6:1; // 6 Transmission Occurred 6 Uint16 TO7:1; // 7 Transmission Occurred 7 Uint16 TO8:1; // 8 Transmission Occurred 8 Uint16 TO9:1; // 9 Transmission Occurred 9 Uint16 TO10:1; // 10 Transmission Occurred 10 Uint16 TO11:1; // 11 Transmission Occurred 11 Uint16 TO12:1; // 12 Transmission Occurred 12 Uint16 TO13:1; // 13 Transmission Occurred 13 Uint16 TO14:1; // 14 Transmission Occurred 14 Uint16 TO15:1; // 15 Transmission Occurred 15 Uint16 TO16:1; // 16 Transmission Occurred 16 Uint16 TO17:1; // 17 Transmission Occurred 17 Uint16 TO18:1; // 18 Transmission Occurred 18 Uint16 TO19:1; // 19 Transmission Occurred 19 Uint16 TO20:1; // 20 Transmission Occurred 20 Uint16 TO21:1; // 21 Transmission Occurred 21 Uint16 TO22:1; // 22 Transmission Occurred 22 Uint16 TO23:1; // 23 Transmission Occurred 23 Uint16 TO24:1; // 24 Transmission Occurred 24 Uint16 TO25:1; // 25 Transmission Occurred 25 Uint16 TO26:1; // 26 Transmission Occurred 26 Uint16 TO27:1; // 27 Transmission Occurred 27 Uint16 TO28:1; // 28 Transmission Occurred 28 Uint16 TO29:1; // 29 Transmission Occurred 29 Uint16 TO30:1; // 30 Transmission Occurred 30 Uint16 TO31:1; // 31 Transmission Occurred 31 }; union MCAN_TXBTO_REG { Uint32 all; struct MCAN_TXBTO_BITS bit; }; struct MCAN_TXBCF_BITS { // bits description Uint16 CF0:1; // 0 Cancellation Finished 0 Uint16 CF1:1; // 1 Cancellation Finished 1 Uint16 CF2:1; // 2 Cancellation Finished 2 Uint16 CF3:1; // 3 Cancellation Finished 3 Uint16 CF4:1; // 4 Cancellation Finished 4 Uint16 CF5:1; // 5 Cancellation Finished 5 Uint16 CF6:1; // 6 Cancellation Finished 6 Uint16 CF7:1; // 7 Cancellation Finished 7 Uint16 CF8:1; // 8 Cancellation Finished 8 Uint16 CF9:1; // 9 Cancellation Finished 9 Uint16 CF10:1; // 10 Cancellation Finished 10 Uint16 CF11:1; // 11 Cancellation Finished 11 Uint16 CF12:1; // 12 Cancellation Finished 12 Uint16 CF13:1; // 13 Cancellation Finished 13 Uint16 CF14:1; // 14 Cancellation Finished 14 Uint16 CF15:1; // 15 Cancellation Finished 15 Uint16 CF16:1; // 16 Cancellation Finished 16 Uint16 CF17:1; // 17 Cancellation Finished 17 Uint16 CF18:1; // 18 Cancellation Finished 18 Uint16 CF19:1; // 19 Cancellation Finished 19 Uint16 CF20:1; // 20 Cancellation Finished 20 Uint16 CF21:1; // 21 Cancellation Finished 21 Uint16 CF22:1; // 22 Cancellation Finished 22 Uint16 CF23:1; // 23 Cancellation Finished 23 Uint16 CF24:1; // 24 Cancellation Finished 24 Uint16 CF25:1; // 25 Cancellation Finished 25 Uint16 CF26:1; // 26 Cancellation Finished 26 Uint16 CF27:1; // 27 Cancellation Finished 27 Uint16 CF28:1; // 28 Cancellation Finished 28 Uint16 CF29:1; // 29 Cancellation Finished 29 Uint16 CF30:1; // 30 Cancellation Finished 30 Uint16 CF31:1; // 31 Cancellation Finished 31 }; union MCAN_TXBCF_REG { Uint32 all; struct MCAN_TXBCF_BITS bit; }; struct MCAN_TXBTIE_BITS { // bits description Uint16 TIE0:1; // 0 Transmission Interrupt Enable 0 Uint16 TIE1:1; // 1 Transmission Interrupt Enable 1 Uint16 TIE2:1; // 2 Transmission Interrupt Enable 2 Uint16 TIE3:1; // 3 Transmission Interrupt Enable 3 Uint16 TIE4:1; // 4 Transmission Interrupt Enable 4 Uint16 TIE5:1; // 5 Transmission Interrupt Enable 5 Uint16 TIE6:1; // 6 Transmission Interrupt Enable 6 Uint16 TIE7:1; // 7 Transmission Interrupt Enable 7 Uint16 TIE8:1; // 8 Transmission Interrupt Enable 8 Uint16 TIE9:1; // 9 Transmission Interrupt Enable 9 Uint16 TIE10:1; // 10 Transmission Interrupt Enable 10 Uint16 TIE11:1; // 11 Transmission Interrupt Enable 11 Uint16 TIE12:1; // 12 Transmission Interrupt Enable 12 Uint16 TIE13:1; // 13 Transmission Interrupt Enable 13 Uint16 TIE14:1; // 14 Transmission Interrupt Enable 14 Uint16 TIE15:1; // 15 Transmission Interrupt Enable 15 Uint16 TIE16:1; // 16 Transmission Interrupt Enable 16 Uint16 TIE17:1; // 17 Transmission Interrupt Enable 17 Uint16 TIE18:1; // 18 Transmission Interrupt Enable 18 Uint16 TIE19:1; // 19 Transmission Interrupt Enable 19 Uint16 TIE20:1; // 20 Transmission Interrupt Enable 20 Uint16 TIE21:1; // 21 Transmission Interrupt Enable 21 Uint16 TIE22:1; // 22 Transmission Interrupt Enable 22 Uint16 TIE23:1; // 23 Transmission Interrupt Enable 23 Uint16 TIE24:1; // 24 Transmission Interrupt Enable 24 Uint16 TIE25:1; // 25 Transmission Interrupt Enable 25 Uint16 TIE26:1; // 26 Transmission Interrupt Enable 26 Uint16 TIE27:1; // 27 Transmission Interrupt Enable 27 Uint16 TIE28:1; // 28 Transmission Interrupt Enable 28 Uint16 TIE29:1; // 29 Transmission Interrupt Enable 29 Uint16 TIE30:1; // 30 Transmission Interrupt Enable 30 Uint16 TIE31:1; // 31 Transmission Interrupt Enable 31 }; union MCAN_TXBTIE_REG { Uint32 all; struct MCAN_TXBTIE_BITS bit; }; struct MCAN_TXBCIE_BITS { // bits description Uint16 CFIE0:1; // 0 Cancellation Finished Interrupt Enable 0 Uint16 CFIE1:1; // 1 Cancellation Finished Interrupt Enable 1 Uint16 CFIE2:1; // 2 Cancellation Finished Interrupt Enable 2 Uint16 CFIE3:1; // 3 Cancellation Finished Interrupt Enable 3 Uint16 CFIE4:1; // 4 Cancellation Finished Interrupt Enable 4 Uint16 CFIE5:1; // 5 Cancellation Finished Interrupt Enable 5 Uint16 CFIE6:1; // 6 Cancellation Finished Interrupt Enable 6 Uint16 CFIE7:1; // 7 Cancellation Finished Interrupt Enable 7 Uint16 CFIE8:1; // 8 Cancellation Finished Interrupt Enable 8 Uint16 CFIE9:1; // 9 Cancellation Finished Interrupt Enable 9 Uint16 CFIE10:1; // 10 Cancellation Finished Interrupt Enable 10 Uint16 CFIE11:1; // 11 Cancellation Finished Interrupt Enable 11 Uint16 CFIE12:1; // 12 Cancellation Finished Interrupt Enable 12 Uint16 CFIE13:1; // 13 Cancellation Finished Interrupt Enable 13 Uint16 CFIE14:1; // 14 Cancellation Finished Interrupt Enable 14 Uint16 CFIE15:1; // 15 Cancellation Finished Interrupt Enable 15 Uint16 CFIE16:1; // 16 Cancellation Finished Interrupt Enable 16 Uint16 CFIE17:1; // 17 Cancellation Finished Interrupt Enable 17 Uint16 CFIE18:1; // 18 Cancellation Finished Interrupt Enable 18 Uint16 CFIE19:1; // 19 Cancellation Finished Interrupt Enable 19 Uint16 CFIE20:1; // 20 Cancellation Finished Interrupt Enable 20 Uint16 CFIE21:1; // 21 Cancellation Finished Interrupt Enable 21 Uint16 CFIE22:1; // 22 Cancellation Finished Interrupt Enable 22 Uint16 CFIE23:1; // 23 Cancellation Finished Interrupt Enable 23 Uint16 CFIE24:1; // 24 Cancellation Finished Interrupt Enable 24 Uint16 CFIE25:1; // 25 Cancellation Finished Interrupt Enable 25 Uint16 CFIE26:1; // 26 Cancellation Finished Interrupt Enable 26 Uint16 CFIE27:1; // 27 Cancellation Finished Interrupt Enable 27 Uint16 CFIE28:1; // 28 Cancellation Finished Interrupt Enable 28 Uint16 CFIE29:1; // 29 Cancellation Finished Interrupt Enable 29 Uint16 CFIE30:1; // 30 Cancellation Finished Interrupt Enable 30 Uint16 CFIE31:1; // 31 Cancellation Finished Interrupt Enable 31 }; union MCAN_TXBCIE_REG { Uint32 all; struct MCAN_TXBCIE_BITS bit; }; struct MCAN_TXEFC_BITS { // bits description Uint16 rsvd1:2; // 1:0 Reserved Uint16 EFSA:14; // 15:2 Event FIFO Start Address Uint16 EFS:6; // 21:16 Event FIFO Size Uint16 rsvd2:2; // 23:22 Reserved Uint16 EFWM:6; // 29:24 Event FIFO Watermark Uint16 rsvd3:2; // 31:30 Reserved }; union MCAN_TXEFC_REG { Uint32 all; struct MCAN_TXEFC_BITS bit; }; struct MCAN_TXEFS_BITS { // bits description Uint16 EFFL:6; // 5:0 Event FIFO Fill Level Uint16 rsvd1:2; // 7:6 Reserved Uint16 EFGI:5; // 12:8 Event FIFO Get Index Uint16 rsvd2:3; // 15:13 Reserved Uint16 EFPI:5; // 20:16 Event FIFO Put Index Uint16 rsvd3:3; // 23:21 Reserved Uint16 EFF:1; // 24 Event FIFO Full Uint16 TEFL:1; // 25 Tx Event FIFO Element Lost Uint16 rsvd4:6; // 31:26 Reserved }; union MCAN_TXEFS_REG { Uint32 all; struct MCAN_TXEFS_BITS bit; }; struct MCAN_TXEFA_BITS { // bits description Uint16 EFAI:5; // 4:0 Event FIFO Acknowledge Index Uint16 rsvd1:11; // 15:5 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCAN_TXEFA_REG { Uint32 all; struct MCAN_TXEFA_BITS bit; }; struct MCAN_REGS { union MCAN_CREL_REG MCAN_CREL; // MCAN Core Release Register Uint32 MCAN_ENDN; // MCAN Endian Register Uint16 rsvd1[2]; // Reserved union MCAN_DBTP_REG MCAN_DBTP; // MCAN Data Bit Timing and Prescaler Register union MCAN_TEST_REG MCAN_TEST; // MCAN Test Register union MCAN_RWD_REG MCAN_RWD; // MCAN RAM Watchdog union MCAN_CCCR_REG MCAN_CCCR; // MCAN CC Control Register union MCAN_NBTP_REG MCAN_NBTP; // MCAN Nominal Bit Timing and Prescaler Register union MCAN_TSCC_REG MCAN_TSCC; // MCAN Timestamp Counter Configuration union MCAN_TSCV_REG MCAN_TSCV; // MCAN Timestamp Counter Value union MCAN_TOCC_REG MCAN_TOCC; // MCAN Timeout Counter Configuration union MCAN_TOCV_REG MCAN_TOCV; // MCAN Timeout Counter Value Uint16 rsvd2[8]; // Reserved union MCAN_ECR_REG MCAN_ECR; // MCAN Error Counter Register union MCAN_PSR_REG MCAN_PSR; // MCAN Protocol Status Register union MCAN_TDCR_REG MCAN_TDCR; // MCAN Transmitter Delay Compensation Register Uint16 rsvd3[2]; // Reserved union MCAN_IR_REG MCAN_IR; // MCAN Interrupt Register union MCAN_IE_REG MCAN_IE; // MCAN Interrupt Enable union MCAN_ILS_REG MCAN_ILS; // MCAN Interrupt Line Select union MCAN_ILE_REG MCAN_ILE; // MCAN Interrupt Line Enable Uint16 rsvd4[16]; // Reserved union MCAN_GFC_REG MCAN_GFC; // MCAN Global Filter Configuration union MCAN_SIDFC_REG MCAN_SIDFC; // MCAN Standard ID Filter Configuration union MCAN_XIDFC_REG MCAN_XIDFC; // MCAN Extended ID Filter Configuration Uint16 rsvd5[2]; // Reserved union MCAN_XIDAM_REG MCAN_XIDAM; // MCAN Extended ID and Mask union MCAN_HPMS_REG MCAN_HPMS; // MCAN High Priority Message Status union MCAN_NDAT1_REG MCAN_NDAT1; // MCAN New Data 1 union MCAN_NDAT2_REG MCAN_NDAT2; // MCAN New Data 2 union MCAN_RXF0C_REG MCAN_RXF0C; // MCAN Rx FIFO 0 Configuration union MCAN_RXF0S_REG MCAN_RXF0S; // MCAN Rx FIFO 0 Status union MCAN_RXF0A_REG MCAN_RXF0A; // MCAN Rx FIFO 0 Acknowledge union MCAN_RXBC_REG MCAN_RXBC; // MCAN Rx Buffer Configuration union MCAN_RXF1C_REG MCAN_RXF1C; // MCAN Rx FIFO 1 Configuration union MCAN_RXF1S_REG MCAN_RXF1S; // MCAN Rx FIFO 1 Status union MCAN_RXF1A_REG MCAN_RXF1A; // MCAN Rx FIFO 1 Acknowledge union MCAN_RXESC_REG MCAN_RXESC; // MCAN Rx Buffer / FIFO Element Size Configuration union MCAN_TXBC_REG MCAN_TXBC; // MCAN Tx Buffer Configuration union MCAN_TXFQS_REG MCAN_TXFQS; // MCAN Tx FIFO / Queue Status union MCAN_TXESC_REG MCAN_TXESC; // MCAN Tx Buffer Element Size Configuration union MCAN_TXBRP_REG MCAN_TXBRP; // MCAN Tx Buffer Request Pending union MCAN_TXBAR_REG MCAN_TXBAR; // MCAN Tx Buffer Add Request union MCAN_TXBCR_REG MCAN_TXBCR; // MCAN Tx Buffer Cancellation Request union MCAN_TXBTO_REG MCAN_TXBTO; // MCAN Tx Buffer Transmission Occurred union MCAN_TXBCF_REG MCAN_TXBCF; // MCAN Tx Buffer Cancellation Finished union MCAN_TXBTIE_REG MCAN_TXBTIE; // MCAN Tx Buffer Transmission Interrupt Enable union MCAN_TXBCIE_REG MCAN_TXBCIE; // MCAN Tx Buffer Cancellation Finished Interrupt Enable Uint16 rsvd6[4]; // Reserved union MCAN_TXEFC_REG MCAN_TXEFC; // MCAN Tx Event FIFO Configuration union MCAN_TXEFS_REG MCAN_TXEFS; // MCAN Tx Event FIFO Status union MCAN_TXEFA_REG MCAN_TXEFA; // MCAN Tx Event FIFO Acknowledge }; struct MCANERR_REV_BITS { // bits description Uint16 REVMIN:6; // 5:0 Minor Revision Uint16 rsvd1:2; // 7:6 Reserved Uint16 REVMAJ:3; // 10:8 Major Revision Uint16 rsvd2:5; // 15:11 Reserved Uint16 MODULE_ID:12; // 27:16 Module Identification Number Uint16 rsvd3:2; // 29:28 Reserved Uint16 SCHEME:2; // 31:30 PID Register Scheme }; union MCANERR_REV_REG { Uint32 all; struct MCANERR_REV_BITS bit; }; struct MCANERR_VECTOR_BITS { // bits description Uint16 ECC_VECTOR:11; // 10:0 ECC RAM ID Uint16 rsvd1:4; // 14:11 Reserved Uint16 RD_SVBUS:1; // 15 Read Trigger Uint16 RD_SVBUS_ADDRESS:8; // 23:16 Read Address Offset Uint16 RD_SVBUS_DONE:1; // 24 Read Completion Flag Uint16 rsvd2:7; // 31:25 Reserved }; union MCANERR_VECTOR_REG { Uint32 all; struct MCANERR_VECTOR_BITS bit; }; struct MCANERR_STAT_BITS { // bits description Uint16 NUM_RAMS:11; // 10:0 Number of RAMs Uint16 rsvd1:5; // 15:11 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANERR_STAT_REG { Uint32 all; struct MCANERR_STAT_BITS bit; }; struct MCANERR_WRAP_REV_BITS { // bits description Uint16 REVMIN:6; // 5:0 Minor Revision Uint16 rsvd1:2; // 7:6 Reserved Uint16 REVMAJ:3; // 10:8 Major Revision Uint16 rsvd2:5; // 15:11 Reserved Uint16 MODULE_ID:12; // 27:16 Module Identification Number Uint16 rsvd3:2; // 29:28 Reserved Uint16 SCHEME:2; // 31:30 PID Register Scheme }; union MCANERR_WRAP_REV_REG { Uint32 all; struct MCANERR_WRAP_REV_BITS bit; }; struct MCANERR_CTRL_BITS { // bits description Uint16 ECC_ENABLE:1; // 0 Enable ECC Generation Uint16 ECC_CHECK:1; // 1 Enable ECC Check Uint16 ENABLE_RMW:1; // 2 Enable Read-Modify-Write Uint16 FORCE_SEC:1; // 3 Force Single Bit Error Corrected Error Uint16 FORCE_DED:1; // 4 Force Double Bit Error Detected Error Uint16 FORCE_N_ROW:1; // 5 Force Next Single/Double Bit Error Uint16 ERROR_ONCE:1; // 6 Force Error Only Once Enable Uint16 rsvd1:1; // 7 Reserved Uint16 CHECK_SVBUS_TIMEOUT:1; // 8 SVBUS Timeout Enable Uint16 rsvd2:7; // 15:9 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_CTRL_REG { Uint32 all; struct MCANERR_CTRL_BITS bit; }; struct MCANERR_ERR_CTRL2_BITS { // bits description Uint16 ECC_BIT1:16; // 15:0 Force Error Bit1 Column Index Uint16 ECC_BIT2:16; // 31:16 Force Error Bit2 Column Index }; union MCANERR_ERR_CTRL2_REG { Uint32 all; struct MCANERR_ERR_CTRL2_BITS bit; }; struct MCANERR_ERR_STAT1_BITS { // bits description Uint16 ECC_SEC:2; // 1:0 Single Bit Error Corrected Status Uint16 ECC_DED:2; // 3:2 Double Bit Error Detected Status Uint16 ECC_OTHER:1; // 4 SEC While Writeback Error Status Uint16 rsvd1:2; // 6:5 Reserved Uint16 CTRL_REG_ERROR:1; // 7 Control Register Error Uint16 CLR_ECC_SEC:2; // 9:8 Clear ECC_SEC Uint16 CLR_ECC_DED:2; // 11:10 Clear ECC_DED Uint16 CLR_ECC_OTHER:1; // 12 Clear ECC_OTHER Uint16 rsvd2:2; // 14:13 Reserved Uint16 CLR_CTRL_REG_ERROR:1; // 15 Clear Control Register Error Uint16 ECC_BIT1:16; // 31:16 ECC Error Bit Position }; union MCANERR_ERR_STAT1_REG { Uint32 all; struct MCANERR_ERR_STAT1_BITS bit; }; struct MCANERR_ERR_STAT3_BITS { // bits description Uint16 WB_PEND:1; // 0 Delayed Write Back Pending Status Uint16 SVBUS_TIMEOUT:1; // 1 Serial VBUS Timeout Flag Uint16 rsvd1:7; // 8:2 Reserved Uint16 CLR_SVBUS_TIMEOUT:1; // 9 Clear Serial VBUS Timeout Uint16 rsvd2:6; // 15:10 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_ERR_STAT3_REG { Uint32 all; struct MCANERR_ERR_STAT3_BITS bit; }; struct MCANERR_SEC_EOI_BITS { // bits description Uint16 EOI_WR:1; // 0 End of Interrupt Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANERR_SEC_EOI_REG { Uint32 all; struct MCANERR_SEC_EOI_BITS bit; }; struct MCANERR_SEC_STATUS_BITS { // bits description Uint16 MSGMEM_PEND:1; // 0 Message RAM SEC Interrupt Pending Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_SEC_STATUS_REG { Uint32 all; struct MCANERR_SEC_STATUS_BITS bit; }; struct MCANERR_SEC_ENABLE_SET_BITS { // bits description Uint16 MSGMEM_ENABLE_SET:1; // 0 Message RAM SEC Interrupt Pending Enable Set Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_SEC_ENABLE_SET_REG { Uint32 all; struct MCANERR_SEC_ENABLE_SET_BITS bit; }; struct MCANERR_SEC_ENABLE_CLR_BITS { // bits description Uint16 MSGMEM_ENABLE_CLR:1; // 0 Message RAM SEC Interrupt Pending Enable Clear Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_SEC_ENABLE_CLR_REG { Uint32 all; struct MCANERR_SEC_ENABLE_CLR_BITS bit; }; struct MCANERR_DED_EOI_BITS { // bits description Uint16 EOI_WR:1; // 0 End of Interrupt Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANERR_DED_EOI_REG { Uint32 all; struct MCANERR_DED_EOI_BITS bit; }; struct MCANERR_DED_STATUS_BITS { // bits description Uint16 MSGMEM_PEND:1; // 0 Message RAM DED Interrupt Pending Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_DED_STATUS_REG { Uint32 all; struct MCANERR_DED_STATUS_BITS bit; }; struct MCANERR_DED_ENABLE_SET_BITS { // bits description Uint16 MSGMEM_ENABLE_SET:1; // 0 Message RAM DED Interrupt Pending Enable Set Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_DED_ENABLE_SET_REG { Uint32 all; struct MCANERR_DED_ENABLE_SET_BITS bit; }; struct MCANERR_DED_ENABLE_CLR_BITS { // bits description Uint16 MSGMEM_ENABLE_CLR:1; // 0 Message RAM DED Interrupt Pending Enable Clear Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union MCANERR_DED_ENABLE_CLR_REG { Uint32 all; struct MCANERR_DED_ENABLE_CLR_BITS bit; }; struct MCANERR_AGGR_ENABLE_SET_BITS { // bits description Uint16 ENABLE_PARITY_SET:1; // 0 Enable Parity Errors Set Uint16 ENABLE_TIMEOUT_SET:1; // 1 Enable Timeout Errors Set Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANERR_AGGR_ENABLE_SET_REG { Uint32 all; struct MCANERR_AGGR_ENABLE_SET_BITS bit; }; struct MCANERR_AGGR_ENABLE_CLR_BITS { // bits description Uint16 ENABLE_PARITY_CLR:1; // 0 Enable Parity Errors Clear Uint16 ENABLE_TIMEOUT_CLR:1; // 1 Enable Timeout Errors Clear Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANERR_AGGR_ENABLE_CLR_REG { Uint32 all; struct MCANERR_AGGR_ENABLE_CLR_BITS bit; }; struct MCANERR_AGGR_STATUS_SET_BITS { // bits description Uint16 AGGR_PARITY_ERR:2; // 1:0 Aggregator Parity Error Status Uint16 SVBUS_TIMEOUT:2; // 3:2 Aggregator Serial VBUS Timeout Error Status Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANERR_AGGR_STATUS_SET_REG { Uint32 all; struct MCANERR_AGGR_STATUS_SET_BITS bit; }; struct MCANERR_AGGR_STATUS_CLR_BITS { // bits description Uint16 AGGR_PARITY_ERR:2; // 1:0 Aggregator Parity Error Status Uint16 SVBUS_TIMEOUT:2; // 3:2 Aggregator Serial VBUS Timeout Error Status Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCANERR_AGGR_STATUS_CLR_REG { Uint32 all; struct MCANERR_AGGR_STATUS_CLR_BITS bit; }; struct MCAN_ERROR_REGS { union MCANERR_REV_REG MCANERR_REV; // MCAN Error Aggregator Revision Register Uint16 rsvd1[2]; // Reserved union MCANERR_VECTOR_REG MCANERR_VECTOR; // MCAN ECC Vector Register union MCANERR_STAT_REG MCANERR_STAT; // MCAN Error Misc Status union MCANERR_WRAP_REV_REG MCANERR_WRAP_REV; // MCAN ECC Wrapper Revision Register union MCANERR_CTRL_REG MCANERR_CTRL; // MCAN ECC Control Uint32 MCANERR_ERR_CTRL1; // MCAN ECC Error Control 1 Register union MCANERR_ERR_CTRL2_REG MCANERR_ERR_CTRL2; // MCAN ECC Error Control 2 Register union MCANERR_ERR_STAT1_REG MCANERR_ERR_STAT1; // MCAN ECC Error Status 1 Register Uint32 MCANERR_ERR_STAT2; // MCAN ECC Error Status 2 Register union MCANERR_ERR_STAT3_REG MCANERR_ERR_STAT3; // MCAN ECC Error Status 3 Register Uint16 rsvd2[8]; // Reserved union MCANERR_SEC_EOI_REG MCANERR_SEC_EOI; // MCAN Single Error Corrected End of Interrupt Register union MCANERR_SEC_STATUS_REG MCANERR_SEC_STATUS; // MCAN Single Error Corrected Interrupt Status Register Uint16 rsvd3[30]; // Reserved union MCANERR_SEC_ENABLE_SET_REG MCANERR_SEC_ENABLE_SET; // MCAN Single Error Corrected Interrupt Enable Set Register Uint16 rsvd4[30]; // Reserved union MCANERR_SEC_ENABLE_CLR_REG MCANERR_SEC_ENABLE_CLR; // MCAN Single Error Corrected Interrupt Enable Clear Register Uint16 rsvd5[60]; // Reserved union MCANERR_DED_EOI_REG MCANERR_DED_EOI; // MCAN Double Error Detected End of Interrupt Register union MCANERR_DED_STATUS_REG MCANERR_DED_STATUS; // MCAN Double Error Detected Interrupt Status Register Uint16 rsvd6[30]; // Reserved union MCANERR_DED_ENABLE_SET_REG MCANERR_DED_ENABLE_SET; // MCAN Double Error Detected Interrupt Enable Set Register Uint16 rsvd7[30]; // Reserved union MCANERR_DED_ENABLE_CLR_REG MCANERR_DED_ENABLE_CLR; // MCAN Double Error Detected Interrupt Enable Clear Register Uint16 rsvd8[30]; // Reserved union MCANERR_AGGR_ENABLE_SET_REG MCANERR_AGGR_ENABLE_SET; // MCAN Error Aggregator Enable Set Register union MCANERR_AGGR_ENABLE_CLR_REG MCANERR_AGGR_ENABLE_CLR; // MCAN Error Aggregator Enable Clear Register union MCANERR_AGGR_STATUS_SET_REG MCANERR_AGGR_STATUS_SET; // MCAN Error Aggregator Status Set Register union MCANERR_AGGR_STATUS_CLR_REG MCANERR_AGGR_STATUS_CLR; // MCAN Error Aggregator Status Clear Register }; //--------------------------------------------------------------------------- // MCAN External References & Function Declarations: // extern volatile struct MCAN_ERROR_REGS McanErrorRegs; extern volatile struct MCAN_REGS McanRegs; extern volatile struct MCANSS_REGS McanssRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_mcbsp.h // // TITLE: Definitions for the MCBSP registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // MCBSP Individual Register Bit Definitions: struct DRR2_BITS { // bits description Uint16 HWLB:8; // 7:0 High word low byte Uint16 HWHB:8; // 15:8 High word high byte }; union DRR2_REG { Uint16 all; struct DRR2_BITS bit; }; struct DRR1_BITS { // bits description Uint16 LWLB:8; // 7:0 Low word low byte Uint16 LWHB:8; // 15:8 Low word high byte }; union DRR1_REG { Uint16 all; struct DRR1_BITS bit; }; struct DXR2_BITS { // bits description Uint16 HWLB:8; // 7:0 High word low byte Uint16 HWHB:8; // 15:8 High word high byte }; union DXR2_REG { Uint16 all; struct DXR2_BITS bit; }; struct DXR1_BITS { // bits description Uint16 LWLB:8; // 7:0 Low word low byte Uint16 LWHB:8; // 15:8 Low word high byte }; union DXR1_REG { Uint16 all; struct DXR1_BITS bit; }; struct SPCR2_BITS { // bits description Uint16 XRST:1; // 0 Transmitter reset Uint16 XRDY:1; // 1 Transmitter ready Uint16 XEMPTY:1; // 2 Transmitter empty Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits Uint16 GRST:1; // 6 Sample rate generator reset Uint16 FRST:1; // 7 Frame sync logic reset Uint16 SOFT:1; // 8 SOFT bit Uint16 FREE:1; // 9 FREE bit Uint16 rsvd1:6; // 15:10 Reserved }; union SPCR2_REG { Uint16 all; struct SPCR2_BITS bit; }; struct SPCR1_BITS { // bits description Uint16 RRST:1; // 0 Receiver reset Uint16 RRDY:1; // 1 Receiver ready Uint16 RFULL:1; // 2 Receiver full Uint16 RSYNCERR:1; // 3 Receive sync error INT flag Uint16 RINTM:2; // 5:4 Receive Interupt mode bits Uint16 rsvd1:1; // 6 Reserved Uint16 DXENA:1; // 7 DX delay enable Uint16 rsvd2:3; // 10:8 Reserved Uint16 CLKSTP:2; // 12:11 Clock stop mode Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode Uint16 DLB:1; // 15 Digital loopback }; union SPCR1_REG { Uint16 all; struct SPCR1_BITS bit; }; struct RCR2_BITS { // bits description Uint16 RDATDLY:2; // 1:0 Receive data delay Uint16 RFIG:1; // 2 Receive frame sync ignore Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects Uint16 RWDLEN2:3; // 7:5 Receive word length 2 Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2 Uint16 RPHASE:1; // 15 Receive Phase }; union RCR2_REG { Uint16 all; struct RCR2_BITS bit; }; struct RCR1_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 RWDLEN1:3; // 7:5 Receive word length 1 Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1 Uint16 rsvd2:1; // 15 Reserved }; union RCR1_REG { Uint16 all; struct RCR1_BITS bit; }; struct XCR2_BITS { // bits description Uint16 XDATDLY:2; // 1:0 Transmit data delay Uint16 XFIG:1; // 2 Transmit frame sync ignore Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects Uint16 XWDLEN2:3; // 7:5 Transmit word length 2 Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2 Uint16 XPHASE:1; // 15 Transmit Phase }; union XCR2_REG { Uint16 all; struct XCR2_BITS bit; }; struct XCR1_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 XWDLEN1:3; // 7:5 Transmit word length 1 Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1 Uint16 rsvd2:1; // 15 Reserved }; union XCR1_REG { Uint16 all; struct XCR1_BITS bit; }; struct SRGR2_BITS { // bits description Uint16 FPER:12; // 11:0 Frame-sync period Uint16 FSGM:1; // 12 Frame sync generator mode Uint16 CLKSM:1; // 13 Sample rate generator mode Uint16 rsvd1:1; // 14 Reserved Uint16 GSYNC:1; // 15 CLKG sync }; union SRGR2_REG { Uint16 all; struct SRGR2_BITS bit; }; struct SRGR1_BITS { // bits description Uint16 CLKGDV:8; // 7:0 CLKG divider Uint16 FWID:8; // 15:8 Frame width }; union SRGR1_REG { Uint16 all; struct SRGR1_BITS bit; }; struct MCR2_BITS { // bits description Uint16 XMCM:2; // 1:0 Transmit data delay Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects Uint16 XPBBLK:2; // 8:7 Transmit word length 2 Uint16 XMCME:1; // 9 Transmit Frame length 2 Uint16 rsvd1:6; // 15:10 Reserved }; union MCR2_REG { Uint16 all; struct MCR2_BITS bit; }; struct MCR1_BITS { // bits description Uint16 RMCM:1; // 0 Receive multichannel mode Uint16 rsvd1:1; // 1 Reserved Uint16 RCBLK:3; // 4:2 eceive current block Uint16 RPABLK:2; // 6:5 Receive partition A Block Uint16 RPBBLK:2; // 8:7 Receive partition B Block Uint16 RMCME:1; // 9 Receive multi-channel enhance mode Uint16 rsvd2:6; // 15:10 Reserved }; union MCR1_REG { Uint16 all; struct MCR1_BITS bit; }; struct PCR_BITS { // bits description Uint16 CLKRP:1; // 0 Receive Clock polarity Uint16 CLKXP:1; // 1 Transmit clock polarity Uint16 FSRP:1; // 2 Receive Frame synchronization polarity Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 SCLKME:1; // 7 Sample clock mode selection Uint16 CLKRM:1; // 8 Receiver Clock Mode Uint16 CLKXM:1; // 9 Transmit Clock Mode. Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode Uint16 rsvd4:4; // 15:12 Reserved }; union PCR_REG { Uint16 all; struct PCR_BITS bit; }; struct MFFINT_BITS { // bits description Uint16 XINT:1; // 0 Enable for Receive Interrupt Uint16 rsvd1:1; // 1 Reserved Uint16 RINT:1; // 2 Enable for transmit Interrupt Uint16 rsvd2:13; // 15:3 Reserved }; union MFFINT_REG { Uint16 all; struct MFFINT_BITS bit; }; struct McBSP_REGS { union DRR2_REG DRR2; // Data receive register bits 31-16 union DRR1_REG DRR1; // Data receive register bits 15-0 union DXR2_REG DXR2; // Data transmit register bits 31-16 union DXR1_REG DXR1; // Data transmit register bits 15-0 union SPCR2_REG SPCR2; // Serial port control register 2 union SPCR1_REG SPCR1; // Serial port control register 1 union RCR2_REG RCR2; // Receive Control register 2 union RCR1_REG RCR1; // Receive Control register 1 union XCR2_REG XCR2; // Transmit Control register 2 union XCR1_REG XCR1; // Transmit Control register 1 union SRGR2_REG SRGR2; // Sample rate generator register 2 union SRGR1_REG SRGR1; // Sample rate generator register 1 union MCR2_REG MCR2; // Multi-channel control register 2 union MCR1_REG MCR1; // Multi-channel control register 1 Uint16 RCERA; // Receive channel enable partition A Uint16 RCERB; // Receive channel enable partition B Uint16 XCERA; // Transmit channel enable partition A Uint16 XCERB; // Transmit channel enable partition B union PCR_REG PCR; // Pin Control register Uint16 RCERC; // Receive channel enable partition C Uint16 RCERD; // Receive channel enable partition D Uint16 XCERC; // Transmit channel enable partition C Uint16 XCERD; // Transmit channel enable partition D Uint16 RCERE; // Receive channel enable partition E Uint16 RCERF; // Receive channel enable partition F Uint16 XCERE; // Transmit channel enable partition E Uint16 XCERF; // Transmit channel enable partition F Uint16 RCERG; // Receive channel enable partition G Uint16 RCERH; // Receive channel enable partition H Uint16 XCERG; // Transmit channel enable partition G Uint16 XCERH; // Transmit channel enable partition H Uint16 rsvd1[4]; // Reserved union MFFINT_REG MFFINT; // Interrupt enable }; //--------------------------------------------------------------------------- // MCBSP External References & Function Declarations: // extern volatile struct McBSP_REGS McbspaRegs; extern volatile struct McBSP_REGS McbspbRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_memconfig.h // // TITLE: Definitions for the MEMCONFIG registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // MEMCONFIG Individual Register Bit Definitions: struct DxLOCK_BITS { // bits description Uint16 LOCK_M0:1; // 0 M0 RAM Lock bits Uint16 LOCK_M1:1; // 1 M1 RAM Lock bits Uint16 LOCK_D0:1; // 2 D0 RAM Lock bits Uint16 LOCK_D1:1; // 3 D1 RAM Lock bits Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxLOCK_REG { Uint32 all; struct DxLOCK_BITS bit; }; struct DxCOMMIT_BITS { // bits description Uint16 COMMIT_M0:1; // 0 M0 RAM Permanent Lock bits Uint16 COMMIT_M1:1; // 1 M1 RAM Permanent Lock bits Uint16 COMMIT_D0:1; // 2 D0 RAM Permanent Lock bits Uint16 COMMIT_D1:1; // 3 D1 RAM Permanent Lock bits Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxCOMMIT_REG { Uint32 all; struct DxCOMMIT_BITS bit; }; struct DxACCPROT0_BITS { // bits description Uint16 FETCHPROT_M0:1; // 0 Fetch Protection For M0 RAM Uint16 CPUWRPROT_M0:1; // 1 CPU WR Protection For M0 RAM Uint16 rsvd1:6; // 7:2 Reserved Uint16 FETCHPROT_M1:1; // 8 Fetch Protection For M1 RAM Uint16 CPUWRPROT_M1:1; // 9 CPU WR Protection For M1 RAM Uint16 rsvd2:6; // 15:10 Reserved Uint16 FETCHPROT_D0:1; // 16 Fetch Protection For D0 RAM Uint16 CPUWRPROT_D0:1; // 17 CPU WR Protection For D0 RAM Uint16 rsvd3:6; // 23:18 Reserved Uint16 FETCHPROT_D1:1; // 24 Fetch Protection For D1 RAM Uint16 CPUWRPROT_D1:1; // 25 CPU WR Protection For D1 RAM Uint16 rsvd4:6; // 31:26 Reserved }; union DxACCPROT0_REG { Uint32 all; struct DxACCPROT0_BITS bit; }; struct DxTEST_BITS { // bits description Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM Uint16 TEST_D0:2; // 5:4 Selects the different modes for D0 RAM Uint16 TEST_D1:2; // 7:6 Selects the different modes for D1 RAM Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxTEST_REG { Uint32 all; struct DxTEST_BITS bit; }; struct DxINIT_BITS { // bits description Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. Uint16 INIT_D0:1; // 2 RAM Initialization control for D0 RAM. Uint16 INIT_D1:1; // 3 RAM Initialization control for D1 RAM. Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxINIT_REG { Uint32 all; struct DxINIT_BITS bit; }; struct DxINITDONE_BITS { // bits description Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. Uint16 INITDONE_D0:1; // 2 RAM Initialization status for D0 RAM. Uint16 INITDONE_D1:1; // 3 RAM Initialization status for D1 RAM. Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DxINITDONE_REG { Uint32 all; struct DxINITDONE_BITS bit; }; struct DxRAMTEST_LOCK_BITS { // bits description Uint16 M0:1; // 0 DxTEST.TEST_M0 LOCK Uint16 M1:1; // 1 DxTEST.TEST_M1 LOCK Uint16 D0:1; // 2 DxTEST.TEST_D0 LOCK Uint16 D1:1; // 3 DxTEST.TEST_D1 LOCK Uint16 rsvd1:12; // 15:4 Reserved Uint16 KEY:16; // 31:16 KEY field }; union DxRAMTEST_LOCK_REG { Uint32 all; struct DxRAMTEST_LOCK_BITS bit; }; struct LSxLOCK_BITS { // bits description Uint16 LOCK_LS0:1; // 0 LS0 RAM Lock bits Uint16 LOCK_LS1:1; // 1 LS1 RAM Lock bits Uint16 LOCK_LS2:1; // 2 LS2 RAM Lock bits Uint16 LOCK_LS3:1; // 3 LS3 RAM Lock bits Uint16 LOCK_LS4:1; // 4 LS4 RAM Lock bits Uint16 LOCK_LS5:1; // 5 LS5 RAM Lock bits Uint16 LOCK_LS6:1; // 6 LS6 RAM Lock bits Uint16 LOCK_LS7:1; // 7 LS7 RAM Lock bits Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxLOCK_REG { Uint32 all; struct LSxLOCK_BITS bit; }; struct LSxCOMMIT_BITS { // bits description Uint16 COMMIT_LS0:1; // 0 LS0 RAM Permanent Lock bits Uint16 COMMIT_LS1:1; // 1 LS1 RAM Permanent Lock bits Uint16 COMMIT_LS2:1; // 2 LS2 RAM Permanent Lock bits Uint16 COMMIT_LS3:1; // 3 LS3 RAM Permanent Lock bits Uint16 COMMIT_LS4:1; // 4 LS4 RAM Permanent Lock bits Uint16 COMMIT_LS5:1; // 5 LS5 RAM Permanent Lock bits Uint16 COMMIT_LS6:1; // 6 LS6 RAM Permanent Lock bits Uint16 COMMIT_LS7:1; // 7 LS7 RAM Permanent Lock bits Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxCOMMIT_REG { Uint32 all; struct LSxCOMMIT_BITS bit; }; struct LSxMSEL_BITS { // bits description Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM Uint16 MSEL_LS6:2; // 13:12 Master Select for LS6 RAM Uint16 MSEL_LS7:2; // 15:14 Master Select for LS7 RAM Uint16 rsvd1:16; // 31:16 Reserved }; union LSxMSEL_REG { Uint32 all; struct LSxMSEL_BITS bit; }; struct LSxCLAPGM_BITS { // bits description Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA Uint16 CLAPGM_LS6:1; // 6 Selects LS6 RAM as program vs data memory for CLA Uint16 CLAPGM_LS7:1; // 7 Selects LS7 RAM as program vs data memory for CLA Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxCLAPGM_REG { Uint32 all; struct LSxCLAPGM_BITS bit; }; struct LSxACCPROT0_BITS { // bits description Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM Uint16 rsvd1:6; // 7:2 Reserved Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM Uint16 rsvd2:6; // 15:10 Reserved Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM Uint16 rsvd3:6; // 23:18 Reserved Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM Uint16 rsvd4:6; // 31:26 Reserved }; union LSxACCPROT0_REG { Uint32 all; struct LSxACCPROT0_BITS bit; }; struct LSxACCPROT1_BITS { // bits description Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM Uint16 rsvd1:6; // 7:2 Reserved Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM Uint16 rsvd2:6; // 15:10 Reserved Uint16 FETCHPROT_LS6:1; // 16 Fetch Protection For LS6 RAM Uint16 CPUWRPROT_LS6:1; // 17 CPU WR Protection For LS6 RAM Uint16 rsvd3:6; // 23:18 Reserved Uint16 FETCHPROT_LS7:1; // 24 Fetch Protection For LS7 RAM Uint16 CPUWRPROT_LS7:1; // 25 CPU WR Protection For LS7 RAM Uint16 rsvd4:6; // 31:26 Reserved }; union LSxACCPROT1_REG { Uint32 all; struct LSxACCPROT1_BITS bit; }; struct LSxTEST_BITS { // bits description Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM Uint16 TEST_LS6:2; // 13:12 Selects the different modes for LS6 RAM Uint16 TEST_LS7:2; // 15:14 Selects the different modes for LS7 RAM Uint16 rsvd1:16; // 31:16 Reserved }; union LSxTEST_REG { Uint32 all; struct LSxTEST_BITS bit; }; struct LSxINIT_BITS { // bits description Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. Uint16 INIT_LS6:1; // 6 RAM Initialization control for LS6 RAM. Uint16 INIT_LS7:1; // 7 RAM Initialization control for LS7 RAM. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxINIT_REG { Uint32 all; struct LSxINIT_BITS bit; }; struct LSxINITDONE_BITS { // bits description Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. Uint16 INITDONE_LS6:1; // 6 RAM Initialization status for LS6 RAM. Uint16 INITDONE_LS7:1; // 7 RAM Initialization status for LS7 RAM. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LSxINITDONE_REG { Uint32 all; struct LSxINITDONE_BITS bit; }; struct LSxRAMTEST_LOCK_BITS { // bits description Uint16 LS0:1; // 0 LSxTEST.TEST_LS0 LOCK Uint16 LS1:1; // 1 LSxTEST.TEST_LS1 LOCK Uint16 LS2:1; // 2 LSxTEST.TEST_LS2 LOCK Uint16 LS3:1; // 3 LSxTEST.TEST_LS3 LOCK Uint16 LS4:1; // 4 LSxTEST.TEST_LS4 LOCK Uint16 LS5:1; // 5 LSxTEST.TEST_LS5 LOCK Uint16 LS6:1; // 6 LSxTEST.TEST_LS6 LOCK Uint16 LS7:1; // 7 LSxTEST.TEST_LS7 LOCK Uint16 rsvd1:8; // 15:8 Reserved Uint16 KEY:16; // 31:16 KEY field }; union LSxRAMTEST_LOCK_REG { Uint32 all; struct LSxRAMTEST_LOCK_BITS bit; }; struct GSxLOCK_BITS { // bits description Uint16 LOCK_GS0:1; // 0 GS0 RAM Lock bits Uint16 LOCK_GS1:1; // 1 GS1 RAM Lock bits Uint16 LOCK_GS2:1; // 2 GS2 RAM Lock bits Uint16 LOCK_GS3:1; // 3 GS3 RAM Lock bits Uint16 LOCK_GS4:1; // 4 GS4 RAM Lock bits Uint16 LOCK_GS5:1; // 5 GS5 RAM Lock bits Uint16 LOCK_GS6:1; // 6 GS6 RAM Lock bits Uint16 LOCK_GS7:1; // 7 GS7 RAM Lock bits Uint16 LOCK_GS8:1; // 8 GS8 RAM Lock bits Uint16 LOCK_GS9:1; // 9 GS9 RAM Lock bits Uint16 LOCK_GS10:1; // 10 GS10 RAM Lock bits Uint16 LOCK_GS11:1; // 11 GS11 RAM Lock bits Uint16 LOCK_GS12:1; // 12 GS12 RAM Lock bits Uint16 LOCK_GS13:1; // 13 GS13 RAM Lock bits Uint16 LOCK_GS14:1; // 14 GS14 RAM Lock bits Uint16 LOCK_GS15:1; // 15 GS15 RAM Lock bits Uint16 rsvd1:16; // 31:16 Reserved }; union GSxLOCK_REG { Uint32 all; struct GSxLOCK_BITS bit; }; struct GSxCOMMIT_BITS { // bits description Uint16 COMMIT_GS0:1; // 0 GS0 RAM Permanent Lock bits Uint16 COMMIT_GS1:1; // 1 GS1 RAM Permanent Lock bits Uint16 COMMIT_GS2:1; // 2 GS2 RAM Permanent Lock bits Uint16 COMMIT_GS3:1; // 3 GS3 RAM Permanent Lock bits Uint16 COMMIT_GS4:1; // 4 GS4 RAM Permanent Lock bits Uint16 COMMIT_GS5:1; // 5 GS5 RAM Permanent Lock bits Uint16 COMMIT_GS6:1; // 6 GS6 RAM Permanent Lock bits Uint16 COMMIT_GS7:1; // 7 GS7 RAM Permanent Lock bits Uint16 COMMIT_GS8:1; // 8 GS8 RAM Permanent Lock bits Uint16 COMMIT_GS9:1; // 9 GS9 RAM Permanent Lock bits Uint16 COMMIT_GS10:1; // 10 GS10 RAM Permanent Lock bits Uint16 COMMIT_GS11:1; // 11 GS11 RAM Permanent Lock bits Uint16 COMMIT_GS12:1; // 12 GS12 RAM Permanent Lock bits Uint16 COMMIT_GS13:1; // 13 GS13 RAM Permanent Lock bits Uint16 COMMIT_GS14:1; // 14 GS14 RAM Permanent Lock bits Uint16 COMMIT_GS15:1; // 15 GS15 RAM Permanent Lock bits Uint16 rsvd1:16; // 31:16 Reserved }; union GSxCOMMIT_REG { Uint32 all; struct GSxCOMMIT_BITS bit; }; struct GSxMSEL_BITS { // bits description Uint16 MSEL_GS0:1; // 0 Master Select for GS0 RAM Uint16 MSEL_GS1:1; // 1 Master Select for GS1 RAM Uint16 MSEL_GS2:1; // 2 Master Select for GS2 RAM Uint16 MSEL_GS3:1; // 3 Master Select for GS3 RAM Uint16 MSEL_GS4:1; // 4 Master Select for GS4 RAM Uint16 MSEL_GS5:1; // 5 Master Select for GS5 RAM Uint16 MSEL_GS6:1; // 6 Master Select for GS6 RAM Uint16 MSEL_GS7:1; // 7 Master Select for GS7 RAM Uint16 MSEL_GS8:1; // 8 Master Select for GS8 RAM Uint16 MSEL_GS9:1; // 9 Master Select for GS9 RAM Uint16 MSEL_GS10:1; // 10 Master Select for GS10 RAM Uint16 MSEL_GS11:1; // 11 Master Select for GS11 RAM Uint16 MSEL_GS12:1; // 12 Master Select for GS12 RAM Uint16 MSEL_GS13:1; // 13 Master Select for GS13 RAM Uint16 MSEL_GS14:1; // 14 Master Select for GS14 RAM Uint16 MSEL_GS15:1; // 15 Master Select for GS15 RAM Uint16 rsvd1:16; // 31:16 Reserved }; union GSxMSEL_REG { Uint32 all; struct GSxMSEL_BITS bit; }; struct GSxACCPROT0_BITS { // bits description Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT0_REG { Uint32 all; struct GSxACCPROT0_BITS bit; }; struct GSxACCPROT1_BITS { // bits description Uint16 FETCHPROT_GS4:1; // 0 Fetch Protection For GS4 RAM Uint16 CPUWRPROT_GS4:1; // 1 CPU WR Protection For GS4 RAM Uint16 DMAWRPROT_GS4:1; // 2 DMA WR Protection For GS4 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS5:1; // 8 Fetch Protection For GS5 RAM Uint16 CPUWRPROT_GS5:1; // 9 CPU WR Protection For GS5 RAM Uint16 DMAWRPROT_GS5:1; // 10 DMA WR Protection For GS5RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS6:1; // 16 Fetch Protection For GS6 RAM Uint16 CPUWRPROT_GS6:1; // 17 CPU WR Protection For GS6 RAM Uint16 DMAWRPROT_GS6:1; // 18 DMA WR Protection For GS6RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS7:1; // 24 Fetch Protection For GS7 RAM Uint16 CPUWRPROT_GS7:1; // 25 CPU WR Protection For GS7 RAM Uint16 DMAWRPROT_GS7:1; // 26 DMA WR Protection For GS7RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT1_REG { Uint32 all; struct GSxACCPROT1_BITS bit; }; struct GSxACCPROT2_BITS { // bits description Uint16 FETCHPROT_GS8:1; // 0 Fetch Protection For GS8 RAM Uint16 CPUWRPROT_GS8:1; // 1 CPU WR Protection For GS8 RAM Uint16 DMAWRPROT_GS8:1; // 2 DMA WR Protection For GS8 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS9:1; // 8 Fetch Protection For GS9 RAM Uint16 CPUWRPROT_GS9:1; // 9 CPU WR Protection For GS9 RAM Uint16 DMAWRPROT_GS9:1; // 10 DMA WR Protection For GS9RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS10:1; // 16 Fetch Protection For GS10 RAM Uint16 CPUWRPROT_GS10:1; // 17 CPU WR Protection For GS10 RAM Uint16 DMAWRPROT_GS10:1; // 18 DMA WR Protection For GS10RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS11:1; // 24 Fetch Protection For GS11 RAM Uint16 CPUWRPROT_GS11:1; // 25 CPU WR Protection For GS11 RAM Uint16 DMAWRPROT_GS11:1; // 26 DMA WR Protection For GS11RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT2_REG { Uint32 all; struct GSxACCPROT2_BITS bit; }; struct GSxACCPROT3_BITS { // bits description Uint16 FETCHPROT_GS12:1; // 0 Fetch Protection For GS12 RAM Uint16 CPUWRPROT_GS12:1; // 1 CPU WR Protection For GS12 RAM Uint16 DMAWRPROT_GS12:1; // 2 DMA WR Protection For GS12 RAM Uint16 rsvd1:5; // 7:3 Reserved Uint16 FETCHPROT_GS13:1; // 8 Fetch Protection For GS13 RAM Uint16 CPUWRPROT_GS13:1; // 9 CPU WR Protection For GS13 RAM Uint16 DMAWRPROT_GS13:1; // 10 DMA WR Protection For GS13RAM Uint16 rsvd2:5; // 15:11 Reserved Uint16 FETCHPROT_GS14:1; // 16 Fetch Protection For GS14 RAM Uint16 CPUWRPROT_GS14:1; // 17 CPU WR Protection For GS14 RAM Uint16 DMAWRPROT_GS14:1; // 18 DMA WR Protection For GS14RAM Uint16 rsvd3:5; // 23:19 Reserved Uint16 FETCHPROT_GS15:1; // 24 Fetch Protection For GS15 RAM Uint16 CPUWRPROT_GS15:1; // 25 CPU WR Protection For GS15 RAM Uint16 DMAWRPROT_GS15:1; // 26 DMA WR Protection For GS15RAM Uint16 rsvd4:5; // 31:27 Reserved }; union GSxACCPROT3_REG { Uint32 all; struct GSxACCPROT3_BITS bit; }; struct GSxTEST_BITS { // bits description Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM Uint16 TEST_GS4:2; // 9:8 Selects the different modes for GS4 RAM Uint16 TEST_GS5:2; // 11:10 Selects the different modes for GS5 RAM Uint16 TEST_GS6:2; // 13:12 Selects the different modes for GS6 RAM Uint16 TEST_GS7:2; // 15:14 Selects the different modes for GS7 RAM Uint16 TEST_GS8:2; // 17:16 Selects the different modes for GS8 RAM Uint16 TEST_GS9:2; // 19:18 Selects the different modes for GS9 RAM Uint16 TEST_GS10:2; // 21:20 Selects the different modes for GS10 RAM Uint16 TEST_GS11:2; // 23:22 Selects the different modes for GS11 RAM Uint16 TEST_GS12:2; // 25:24 Selects the different modes for GS12 RAM Uint16 TEST_GS13:2; // 27:26 Selects the different modes for GS13 RAM Uint16 TEST_GS14:2; // 29:28 Selects the different modes for GS14 RAM Uint16 TEST_GS15:2; // 31:30 Selects the different modes for GS15 RAM }; union GSxTEST_REG { Uint32 all; struct GSxTEST_BITS bit; }; struct GSxINIT_BITS { // bits description Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. Uint16 INIT_GS4:1; // 4 RAM Initialization control for GS4 RAM. Uint16 INIT_GS5:1; // 5 RAM Initialization control for GS5 RAM. Uint16 INIT_GS6:1; // 6 RAM Initialization control for GS6 RAM. Uint16 INIT_GS7:1; // 7 RAM Initialization control for GS7 RAM. Uint16 INIT_GS8:1; // 8 RAM Initialization control for GS8 RAM. Uint16 INIT_GS9:1; // 9 RAM Initialization control for GS9 RAM. Uint16 INIT_GS10:1; // 10 RAM Initialization control for GS10 RAM. Uint16 INIT_GS11:1; // 11 RAM Initialization control for GS11 RAM. Uint16 INIT_GS12:1; // 12 RAM Initialization control for GS12 RAM. Uint16 INIT_GS13:1; // 13 RAM Initialization control for GS13 RAM. Uint16 INIT_GS14:1; // 14 RAM Initialization control for GS14 RAM. Uint16 INIT_GS15:1; // 15 RAM Initialization control for GS15 RAM. Uint16 rsvd1:16; // 31:16 Reserved }; union GSxINIT_REG { Uint32 all; struct GSxINIT_BITS bit; }; struct GSxINITDONE_BITS { // bits description Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. Uint16 INITDONE_GS4:1; // 4 RAM Initialization status for GS4 RAM. Uint16 INITDONE_GS5:1; // 5 RAM Initialization status for GS5 RAM. Uint16 INITDONE_GS6:1; // 6 RAM Initialization status for GS6 RAM. Uint16 INITDONE_GS7:1; // 7 RAM Initialization status for GS7 RAM. Uint16 INITDONE_GS8:1; // 8 RAM Initialization status for GS8 RAM. Uint16 INITDONE_GS9:1; // 9 RAM Initialization status for GS9 RAM. Uint16 INITDONE_GS10:1; // 10 RAM Initialization status for GS10 RAM. Uint16 INITDONE_GS11:1; // 11 RAM Initialization status for GS11 RAM. Uint16 INITDONE_GS12:1; // 12 RAM Initialization status for GS12 RAM. Uint16 INITDONE_GS13:1; // 13 RAM Initialization status for GS13 RAM. Uint16 INITDONE_GS14:1; // 14 RAM Initialization status for GS14 RAM. Uint16 INITDONE_GS15:1; // 15 RAM Initialization status for GS15 RAM. Uint16 rsvd1:16; // 31:16 Reserved }; union GSxINITDONE_REG { Uint32 all; struct GSxINITDONE_BITS bit; }; struct GSxRAMTEST_LOCK_BITS { // bits description Uint16 GS0:1; // 0 GSxTEST.TEST_GS0 LOCK Uint16 GS1:1; // 1 GSxTEST.TEST_GS1 LOCK Uint16 GS2:1; // 2 GSxTEST.TEST_GS2 LOCK Uint16 GS3:1; // 3 GSxTEST.TEST_GS3 LOCK Uint16 GS4:1; // 4 GSxTEST.TEST_GS4 LOCK Uint16 GS5:1; // 5 GSxTEST.TEST_GS5 LOCK Uint16 GS6:1; // 6 GSxTEST.TEST_GS6 LOCK Uint16 GS7:1; // 7 GSxTEST.TEST_GS7 LOCK Uint16 GS8:1; // 8 GSxTEST.TEST_GS8 LOCK Uint16 GS9:1; // 9 GSxTEST.TEST_GS9 LOCK Uint16 GS10:1; // 10 GSxTEST.TEST_GS10 LOCK Uint16 GS11:1; // 11 GSxTEST.TEST_GS11 LOCK Uint16 GS12:1; // 12 GSxTEST.TEST_GS12 LOCK Uint16 GS13:1; // 13 GSxTEST.TEST_GS13 LOCK Uint16 GS14:1; // 14 GSxTEST.TEST_GS14 LOCK Uint16 GS15:1; // 15 GSxTEST.TEST_GS15 LOCK Uint16 KEY:16; // 31:16 KEY field }; union GSxRAMTEST_LOCK_REG { Uint32 all; struct GSxRAMTEST_LOCK_BITS bit; }; struct MSGxLOCK_BITS { // bits description Uint16 LOCK_CPUTOCPU_MSGRAM0:1; // 0 CPUTOCPU RAM Lock bits Uint16 LOCK_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM Lock bits Uint16 LOCK_CLA1TOCPU:1; // 2 CLA1TOCPU RAM Lock bits Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 LOCK_CLA1TODMA:1; // 5 CLA1TODMA RAM control fields lock bit Uint16 LOCK_DMATOCLA1:1; // 6 DMATOCLA1 RAM control fields lock bit Uint16 LOCK_CPUTOCPU_MSGRAM1:1; // 7 Lock bit of CPU to CPU MSG RAM1 control fields Uint16 LOCK_CPUTOCM_MSGRAM0:1; // 8 Lock bit of CPU to CM MSG RAM0 control fields Uint16 LOCK_CPUTOCM_MSGRAM1:1; // 9 Lock bit of CPU to CM MSG RAM1 control fields Uint16 LOCK_CLA2TODMA:1; // 10 Lock bit of CLA to DMA MSG RAM control fields Uint16 LOCK_DMATOCLA2:1; // 11 Lock bit of DMA to CLA MSG RAM control fields Uint16 rsvd3:4; // 15:12 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union MSGxLOCK_REG { Uint32 all; struct MSGxLOCK_BITS bit; }; struct MSGxCOMMIT_BITS { // bits description Uint16 COMMIT_CPUTOCPU_MSGRAM0:1; // 0 CPUTOCPU RAM control fields COMMIT bit Uint16 COMMIT_CPUTOCLA1:1; // 1 CPUTOCLA1 RAM control fields COMMIT bit Uint16 COMMIT_CLA1TOCPU:1; // 2 CLA1TOCPU RAM control fields COMMIT bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 COMMIT_CLA1TODMA:1; // 5 CLA1TODMA RAM control fields COMMIT bit Uint16 COMMIT_DMATOCLA1:1; // 6 DMATOCLA1 RAM control fields COMMIT bit Uint16 COMMIT_CPUTOCPU_MSGRAM1:1; // 7 Commint bit of CPU to CPU MSG RAM1 control fields Uint16 COMMIT_CPUTOCM_MSGRAM0:1; // 8 Commint bit of CPU to CM MSG RAM0 control fields Uint16 COMMIT_CPUTOCM_MSGRAM1:1; // 9 Commint bit of CPU to CM MSG RAM1 control fields Uint16 COMMIT_CLATODMA_MSGRAM0:1; // 10 Commint bit of CLA to DMA MSG RAM control fields Uint16 COMMIT_DMATOCLA_MSGRAM1:1; // 11 Commint bit of DMA to CLA MSG RAM control fields Uint16 rsvd3:4; // 15:12 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union MSGxCOMMIT_REG { Uint32 all; struct MSGxCOMMIT_BITS bit; }; struct MSGxACCPROT0_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CPUWRPROT_CPUTOCPU_MSGRAM0:1; // 1 CPU WR Protection For CPUTOCPU_MSGRAM0 RAM Uint16 DMAWRPROT_CPUTOCPU_MSGRAM0:1; // 2 DMA WR Protection For CPUTOCPU_MSGRAM0 RAM Uint16 rsvd2:5; // 7:3 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 rsvd5:1; // 10 Reserved Uint16 rsvd6:5; // 15:11 Reserved Uint16 rsvd7:1; // 16 Reserved Uint16 rsvd8:1; // 17 Reserved Uint16 rsvd9:1; // 18 Reserved Uint16 rsvd10:5; // 23:19 Reserved Uint16 rsvd11:1; // 24 Reserved Uint16 rsvd12:1; // 25 Reserved Uint16 rsvd13:1; // 26 Reserved Uint16 rsvd14:5; // 31:27 Reserved }; union MSGxACCPROT0_REG { Uint32 all; struct MSGxACCPROT0_BITS bit; }; struct MSGxACCPROT1_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:5; // 7:3 Reserved Uint16 rsvd5:1; // 8 Reserved Uint16 rsvd6:1; // 9 Reserved Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:5; // 15:11 Reserved Uint16 rsvd9:1; // 16 Reserved Uint16 rsvd10:1; // 17 Reserved Uint16 rsvd11:1; // 18 Reserved Uint16 rsvd12:5; // 23:19 Reserved Uint16 rsvd13:1; // 24 Reserved Uint16 CPUWRPROT_CPUTOCPU_MSGRAM1:1; // 25 CPU WR Protection For CPUTOCPU_MSGRAM1 RAM Uint16 DMAWRPROT_CPUTOCPU_MSGRAM1:1; // 26 DMA WR Protection For CPUTOCPU_MSGRAM1RAM Uint16 rsvd14:5; // 31:27 Reserved }; union MSGxACCPROT1_REG { Uint32 all; struct MSGxACCPROT1_BITS bit; }; struct MSGxACCPROT2_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CPUWRPROT_CPUTOCM_MSGRAM0:1; // 1 CPU WR Protection For CPUTOCM_MSGRAM0 RAM Uint16 DMAWRPROT_CPUTOCM_MSGRAM0:1; // 2 DMA WR Protection For CPUTOCM_MSGRAM0 RAM Uint16 rsvd2:5; // 7:3 Reserved Uint16 rsvd3:1; // 8 Reserved Uint16 CPUWRPROT_CPUTOCM_MSGRAM1:1; // 9 CPU WR Protection For CPUTOCM_MSGRAM1 RAM Uint16 DMAWRPROT_CPUTOCM_MSGRAM1:1; // 10 DMA WR Protection For CPUTOCM_MSGRAM1RAM Uint16 rsvd4:5; // 15:11 Reserved Uint16 rsvd5:1; // 16 Reserved Uint16 rsvd6:1; // 17 Reserved Uint16 rsvd7:1; // 18 Reserved Uint16 rsvd8:5; // 23:19 Reserved Uint16 rsvd9:1; // 24 Reserved Uint16 rsvd10:1; // 25 Reserved Uint16 rsvd11:1; // 26 Reserved Uint16 rsvd12:5; // 31:27 Reserved }; union MSGxACCPROT2_REG { Uint32 all; struct MSGxACCPROT2_BITS bit; }; struct MSGxTEST_BITS { // bits description Uint16 TEST_CPUTOCPU_MSGRAM0:2; // 1:0 CPU to CPU Mode Select Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select Uint16 rsvd1:2; // 7:6 Reserved Uint16 rsvd2:2; // 9:8 Reserved Uint16 TEST_CLA1TODMA:2; // 11:10 CLA1 to DMA MSG RAM Mode Select Uint16 TEST_DMATOCLA1:2; // 13:12 DMA to CLA1 MSG RAM Mode Select Uint16 TEST_CPUTOCPU_MSGRAM1:2; // 15:14 CPU to CPU Mode Select Uint16 TEST_CPUTOCM_MSGRAM0:2; // 17:16 CPU to CM Mode Select Uint16 TEST_CPUTOCM_MSGRAM1:2; // 19:18 CPU to CM Mode Select Uint16 rsvd3:2; // 21:20 Reserved Uint16 rsvd4:2; // 23:22 Reserved Uint16 rsvd5:8; // 31:24 Reserved }; union MSGxTEST_REG { Uint32 all; struct MSGxTEST_BITS bit; }; struct MSGxINIT_BITS { // bits description Uint16 INIT_CPUTOCPU_MSGRAM0:1; // 0 Initialization control for CPU to CPU MSG RAM0 Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 INIT_CLA1TODMA:1; // 5 Initialization control for CLA1 to DMA MSG RAM Uint16 INIT_DMATOCLA1:1; // 6 Initialization control for DMA to CLA1 MSG RAM Uint16 INIT_CPUTOCPU_MSGRAM1:1; // 7 Initialization control for CPU to CPU MSG RAM1 Uint16 INIT_CPUTOCM_MSGRAM0:1; // 8 Initialization control for CPU to CM MSG RAM0 Uint16 INIT_CPUTOCM_MSGRAM1:1; // 9 Initialization control for CPU to CM MSG RAM1 Uint16 rsvd3:1; // 10 Reserved Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:4; // 15:12 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union MSGxINIT_REG { Uint32 all; struct MSGxINIT_BITS bit; }; struct MSGxINITDONE_BITS { // bits description Uint16 INITDONE_CPUTOCPU_MSGRAM0:1; // 0 Initialization status for CPU to CPU MSG RAM Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:1; // 4 Reserved Uint16 INITDONE_CLA1TODMA:1; // 5 Initialization status for CLA1 to DMA MSG RAM Uint16 INITDONE_DMATOCLA1:1; // 6 Initialization status for DMA to CLA1 MSG RAM Uint16 INITDONE_CPUTOCPU_MSGRAM1:1; // 7 Initialization status for CPU to CPU MSG RAM1 Uint16 INITDONE_CPUTOCM_MSGRAM0:1; // 8 Initialization status for CPU to CM MSG RAM0 Uint16 INITDONE_CPUTOCM_MSGRAM1:1; // 9 Initialization status for CPU to CM MSG RAM1 Uint16 rsvd3:1; // 10 Reserved Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:4; // 15:12 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union MSGxINITDONE_REG { Uint32 all; struct MSGxINITDONE_BITS bit; }; struct MSGxRAMTEST_LOCK_BITS { // bits description Uint16 CPUTOCPU_MSGRAM0:1; // 0 MSGxTEST.TEST_CPUTOCPU_MSGRAM0 LOCK Uint16 CPUTOCLA1:1; // 1 MSGxTEST.TEST_CPUTOCLA1 LOCK Uint16 CLA1TOCPU:1; // 2 MSGxTEST.TEST_CLA1TOCPU LOCK Uint16 CPUTOCLA2:1; // 3 MSGxTEST.TEST_CPUTOCLA2 LOCK Uint16 CLA2TOCPU:1; // 4 MSGxTEST.TEST_CLA2TOCPU LOCK Uint16 CLA1TODMA:1; // 5 MSGxTEST.TEST_CLA1TODMA LOCK Uint16 DMATOCLA1:1; // 6 MSGxTEST.TEST_DMATOCLA1 LOCK Uint16 CPUTOCPU_MSGRAM1:1; // 7 MSGxTEST.TEST_CPUTOCPU_MSGRAM1 LOCK Uint16 CPUTOCM_MSGRAM0:1; // 8 MSGxTEST.TEST_CPUTOCM_MSGRAM0 LOCK Uint16 CPUTOCM_MSGRAM1:1; // 9 MSGxTEST.TEST_CPUTOCM_MSGRAM1 LOCK Uint16 CLA2TODMA:1; // 10 MSGxTEST.TEST_CLA2TODMA LOCK Uint16 DMATOCLA2:1; // 11 MSGxTEST.TEST_DMATOCLA2 LOCK Uint16 rsvd1:4; // 15:12 Reserved Uint16 KEY:16; // 31:16 KEY field }; union MSGxRAMTEST_LOCK_REG { Uint32 all; struct MSGxRAMTEST_LOCK_BITS bit; }; struct ROM_LOCK_BITS { // bits description Uint16 LOCK_BOOTROM:1; // 0 BOOTROM Lock bits Uint16 LOCK_SECUREROM:1; // 1 SECUREROM Lock bits Uint16 LOCK_CLADATAROM:1; // 2 CLADATAROM Lock bits Uint16 rsvd1:13; // 15:3 Reserved Uint16 KEY:16; // 31:16 KEY field }; union ROM_LOCK_REG { Uint32 all; struct ROM_LOCK_BITS bit; }; struct ROM_TEST_BITS { // bits description Uint16 TEST_BOOTROM:2; // 1:0 Selects the different modes for BOOTROM Uint16 TEST_SECUREROM:2; // 3:2 Selects the different modes for SECUREROM Uint16 TEST_CLADATAROM:2; // 5:4 Selects the different modes for CLADATAROM Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ROM_TEST_REG { Uint32 all; struct ROM_TEST_BITS bit; }; struct ROM_FORCE_ERROR_BITS { // bits description Uint16 FORCE_BOOTROM_ERROR:1; // 0 Force Bootrom Parity Error Uint16 FORCE_SECUREROM_ERROR:1; // 1 Force SECUREROM Parity Error Uint16 FORCE_CLADATAROM_ERROR:1; // 2 Force CLADATAROM Parity Error Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ROM_FORCE_ERROR_REG { Uint32 all; struct ROM_FORCE_ERROR_BITS bit; }; struct PERI_MEM_TEST_LOCK_BITS { // bits description Uint16 LOCK_PERI_MEM_TEST_CONTROL:1; // 0 PERI_MEM_TEST_CONTROL Lock bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 KEY field }; union PERI_MEM_TEST_LOCK_REG { Uint32 all; struct PERI_MEM_TEST_LOCK_BITS bit; }; struct PERI_MEM_TEST_CONTROL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 rsvd3:1; // 2 Reserved Uint16 rsvd4:1; // 3 Reserved Uint16 EtherCAT_TEST_ENABLE:1; // 4 EtherCAT Test mode enable Uint16 EtherCAT_MEM_FORCE_ERROR:1; // 5 Force Parity Error on EtherCAT RAM Uint16 rsvd5:10; // 15:6 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union PERI_MEM_TEST_CONTROL_REG { Uint32 all; struct PERI_MEM_TEST_CONTROL_BITS bit; }; struct MEM_CFG_REGS { union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register Uint16 rsvd1[4]; // Reserved union DxACCPROT0_REG DxACCPROT0; // Dedicated RAM Config Register Uint16 rsvd2[6]; // Reserved union DxTEST_REG DxTEST; // Dedicated RAM TEST Register union DxINIT_REG DxINIT; // Dedicated RAM Init Register union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register union DxRAMTEST_LOCK_REG DxRAMTEST_LOCK; // Lock register to Dx RAM TEST registers Uint16 rsvd3[8]; // Reserved union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 Uint16 rsvd4[4]; // Reserved union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register union LSxRAMTEST_LOCK_REG LSxRAMTEST_LOCK; // Lock register to LSx RAM TEST registers Uint16 rsvd5[8]; // Reserved union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register union GSxMSEL_REG GSxMSEL; // Global Shared RAM Master Sel Register Uint16 rsvd6[2]; // Reserved union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Access Protection Register 0 union GSxACCPROT1_REG GSxACCPROT1; // Global Shared RAM Access Protection Register 1 union GSxACCPROT2_REG GSxACCPROT2; // Global Shared RAM Access Protection Register 2 union GSxACCPROT3_REG GSxACCPROT3; // Global Shared RAM Access Protection Register 3 union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register union GSxRAMTEST_LOCK_REG GSxRAMTEST_LOCK; // Lock register to GSx RAM TEST registers Uint16 rsvd7[8]; // Reserved union MSGxLOCK_REG MSGxLOCK; // Message RAM Config Lock Register union MSGxCOMMIT_REG MSGxCOMMIT; // Message RAM Config Lock Commit Register Uint16 rsvd8[4]; // Reserved union MSGxACCPROT0_REG MSGxACCPROT0; // Message RAM Access Protection Register 0 union MSGxACCPROT1_REG MSGxACCPROT1; // Message RAM Access Protection Register 1 union MSGxACCPROT2_REG MSGxACCPROT2; // Message RAM Access Protection Register 2 Uint16 rsvd9[2]; // Reserved union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register union MSGxINIT_REG MSGxINIT; // Message RAM Init Register union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register union MSGxRAMTEST_LOCK_REG MSGxRAMTEST_LOCK; // Lock register to MSGx RAM TEST registers Uint16 rsvd10[40]; // Reserved union ROM_LOCK_REG ROM_LOCK; // ROM Config Lock Register union ROM_TEST_REG ROM_TEST; // ROM TEST Register union ROM_FORCE_ERROR_REG ROM_FORCE_ERROR; // ROM Force Error register Uint16 rsvd11[4]; // Reserved union PERI_MEM_TEST_LOCK_REG PERI_MEM_TEST_LOCK; // Peripheral Memory Test Lock Register union PERI_MEM_TEST_CONTROL_REG PERI_MEM_TEST_CONTROL; // Peripheral Memory Test control Register }; struct EMIF1LOCK_BITS { // bits description Uint16 LOCK_EMIF1:1; // 0 EMIF1 access protection and master select fields lock bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF1LOCK_REG { Uint32 all; struct EMIF1LOCK_BITS bit; }; struct EMIF1COMMIT_BITS { // bits description Uint16 COMMIT_EMIF1:1; // 0 EMIF1 access protection and master select permanent lock Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF1COMMIT_REG { Uint32 all; struct EMIF1COMMIT_BITS bit; }; struct EMIF1MSEL_BITS { // bits description Uint16 MSEL_EMIF1:2; // 1:0 Master Select for EMIF1. Uint16 rsvd1:2; // 3:2 Reserved Uint32 KEY:28; // 31:4 KEY to enable the write into MSEL_EMIF1 bits }; union EMIF1MSEL_REG { Uint32 all; struct EMIF1MSEL_BITS bit; }; struct EMIF1ACCPROT0_BITS { // bits description Uint16 FETCHPROT_EMIF1:1; // 0 Fetch Protection For EMIF1 Uint16 CPUWRPROT_EMIF1:1; // 1 CPU WR Protection For EMIF1 Uint16 DMAWRPROT_EMIF1:1; // 2 DMA WR Protection For EMIF1 Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF1ACCPROT0_REG { Uint32 all; struct EMIF1ACCPROT0_BITS bit; }; struct EMIF1_CONFIG_REGS { union EMIF1LOCK_REG EMIF1LOCK; // EMIF1 Config Lock Register union EMIF1COMMIT_REG EMIF1COMMIT; // EMIF1 Config Lock Commit Register union EMIF1MSEL_REG EMIF1MSEL; // EMIF1 Master Sel Register Uint16 rsvd1[2]; // Reserved union EMIF1ACCPROT0_REG EMIF1ACCPROT0; // EMIF1 Config Register 0 }; struct EMIF2LOCK_BITS { // bits description Uint16 LOCK_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF2LOCK_REG { Uint32 all; struct EMIF2LOCK_BITS bit; }; struct EMIF2COMMIT_BITS { // bits description Uint16 COMMIT_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF2COMMIT_REG { Uint32 all; struct EMIF2COMMIT_BITS bit; }; struct EMIF2ACCPROT0_BITS { // bits description Uint16 FETCHPROT_EMIF2:1; // 0 Fetch Protection For EMIF2 Uint16 CPUWRPROT_EMIF2:1; // 1 CPU WR Protection For EMIF2 Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EMIF2ACCPROT0_REG { Uint32 all; struct EMIF2ACCPROT0_BITS bit; }; struct EMIF2_CONFIG_REGS { union EMIF2LOCK_REG EMIF2LOCK; // EMIF2 Config Lock Register union EMIF2COMMIT_REG EMIF2COMMIT; // EMIF2 Config Lock Commit Register Uint16 rsvd1[4]; // Reserved union EMIF2ACCPROT0_REG EMIF2ACCPROT0; // EMIF2 Config Register 0 }; struct NMAVFLG_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 DMAREAD:1; // 10 Non Master DMA read Access Violation Flag Uint16 rsvd4:5; // 15:11 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVFLG_REG { Uint32 all; struct NMAVFLG_BITS bit; }; struct NMAVSET_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 DMAREAD:1; // 10 Non Master DMA read Access Violation Flag Set Uint16 rsvd4:5; // 15:11 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVSET_REG { Uint32 all; struct NMAVSET_BITS bit; }; struct NMAVCLR_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 DMAREAD:1; // 10 Non Master DMA read Access Violation Flag Clear Uint16 rsvd4:5; // 15:11 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVCLR_REG { Uint32 all; struct NMAVCLR_BITS bit; }; struct NMAVINTEN_BITS { // bits description Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Interrupt Enable Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 DMAREAD:1; // 10 Non Master DMA Read Access Violation Interrupt Enable Uint16 rsvd4:5; // 15:11 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union NMAVINTEN_REG { Uint32 all; struct NMAVINTEN_BITS bit; }; struct MAVFLG_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVFLG_REG { Uint32 all; struct MAVFLG_BITS bit; }; struct MAVSET_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVSET_REG { Uint32 all; struct MAVSET_BITS bit; }; struct MAVCLR_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVCLR_REG { Uint32 all; struct MAVCLR_BITS bit; }; struct MAVINTEN_BITS { // bits description Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MAVINTEN_REG { Uint32 all; struct MAVINTEN_BITS bit; }; struct ACCESS_PROTECTION_REGS { union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address Uint32 NMDMAWRAVADDR; // Non-Master DMA Write Access Violation Address Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address Uint16 rsvd1[6]; // Reserved Uint32 NMDMARDAVADDR; // Non-Master DMA Read Access Violation Address Uint16 rsvd2[2]; // Reserved union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address }; struct UCERRFLG_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Uint16 rsvd1:1; // 3 Reserved Uint16 ECATRAMRDERR:1; // 4 ECAT RAM Read Error Flag Uint16 rsvd2:11; // 15:5 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRFLG_REG { Uint32 all; struct UCERRFLG_BITS bit; }; struct UCERRSET_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set Uint16 rsvd1:1; // 3 Reserved Uint16 ECATRAMRDERR:1; // 4 ECAT RAM Read Error Flag Set Uint16 rsvd2:11; // 15:5 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRSET_REG { Uint32 all; struct UCERRSET_BITS bit; }; struct UCERRCLR_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear Uint16 rsvd1:1; // 3 Reserved Uint16 ECATRAMRDERR:1; // 4 ECAT RAM Read Error Flag Clear Uint16 rsvd2:11; // 15:5 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union UCERRCLR_REG { Uint32 all; struct UCERRCLR_BITS bit; }; struct CERRFLG_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRFLG_REG { Uint32 all; struct CERRFLG_BITS bit; }; struct CERRSET_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRSET_REG { Uint32 all; struct CERRSET_BITS bit; }; struct CERRCLR_BITS { // bits description Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CERRCLR_REG { Uint32 all; struct CERRCLR_BITS bit; }; struct CERRCNT_BITS { // bits description Uint16 CERRCNT:16; // 15:0 Correctable error count. Uint16 rsvd1:16; // 31:16 Reserved }; union CERRCNT_REG { Uint32 all; struct CERRCNT_BITS bit; }; struct CERRTHRES_BITS { // bits description Uint16 CERRTHRES:16; // 15:0 Correctable error threshold. Uint16 rsvd1:16; // 31:16 Reserved }; union CERRTHRES_REG { Uint32 all; struct CERRTHRES_BITS bit; }; struct CEINTFLG_BITS { // bits description Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTFLG_REG { Uint32 all; struct CEINTFLG_BITS bit; }; struct CEINTCLR_BITS { // bits description Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTCLR_REG { Uint32 all; struct CEINTCLR_BITS bit; }; struct CEINTSET_BITS { // bits description Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTSET_REG { Uint32 all; struct CEINTSET_BITS bit; }; struct CEINTEN_BITS { // bits description Uint16 CEINTEN:1; // 0 CPU/DMA/CLA Correctable Error Interrupt Enable. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CEINTEN_REG { Uint32 all; struct CEINTEN_BITS bit; }; struct MEMORY_ERROR_REGS { union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address Uint16 rsvd1[2]; // Reserved Uint32 UCECATRAMADDR; // Uncorrectable etherCAT RAM Read Error Address Uint16 rsvd2[16]; // Reserved union CERRFLG_REG CERRFLG; // Correctable Error Flag Register union CERRSET_REG CERRSET; // Correctable Error Flag Set Register union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register Uint32 CCPUREADDR; // Correctable CPU Read Error Address Uint16 rsvd3[2]; // Reserved Uint32 CCLA1READDR; // Correctable CLA1 Read Error Address Uint16 rsvd4[2]; // Reserved union CERRCNT_REG CERRCNT; // Correctable Error Count Register union CERRTHRES_REG CERRTHRES; // Correctable Error Threshold Value Register union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register }; struct ROMWAITSTATE_BITS { // bits description Uint16 WSDISABLE:1; // 0 ROM Wait State Enable/Disable Control Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ROMWAITSTATE_REG { Uint32 all; struct ROMWAITSTATE_BITS bit; }; struct ROM_WAIT_STATE_REGS { union ROMWAITSTATE_REG ROMWAITSTATE; // ROM Wait State Configuration Register }; struct ROMPREFETCH_BITS { // bits description Uint16 PFENABLE:1; // 0 ROM Prefetch Enable/Disable Control Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ROMPREFETCH_REG { Uint32 all; struct ROMPREFETCH_BITS bit; }; struct ROM_PREFETCH_REGS { union ROMPREFETCH_REG ROMPREFETCH; // ROM Prefetch Configuration Register }; struct CPU_RAM_TEST_ERROR_STS_BITS { // bits description Uint16 COR_ERROR:1; // 0 COR_ERROR flag Uint16 UNC_ERROR:1; // 1 UNC_ERROR flag Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPU_RAM_TEST_ERROR_STS_REG { Uint32 all; struct CPU_RAM_TEST_ERROR_STS_BITS bit; }; struct CPU_RAM_TEST_ERROR_STS_CLR_BITS {// bits description Uint16 COR_ERROR:1; // 0 COR_ERROR flag clear bit Uint16 UNC_ERROR:1; // 1 UNC_ERROR flag clear bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPU_RAM_TEST_ERROR_STS_CLR_REG { Uint32 all; struct CPU_RAM_TEST_ERROR_STS_CLR_BITS bit; }; struct TEST_ERROR_REGS { union CPU_RAM_TEST_ERROR_STS_REG CPU_RAM_TEST_ERROR_STS; // Ram Test: Error Status Register union CPU_RAM_TEST_ERROR_STS_CLR_REG CPU_RAM_TEST_ERROR_STS_CLR; // Ram Test: Error Status Clear Register Uint32 CPU_RAM_TEST_ERROR_ADDR; // Ram Test: Error address register }; //--------------------------------------------------------------------------- // MEMCONFIG External References & Function Declarations: // extern volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; extern volatile struct MEM_CFG_REGS MemCfgRegs; extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; extern volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; extern volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; extern volatile struct TEST_ERROR_REGS TestErrorRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_nmiintrupt.h // // TITLE: Definitions for the NMI registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // NMI Individual Register Bit Definitions: struct NMICFG_BITS { // bits description Uint16 NMIE:1; // 0 Global NMI Enable Uint16 rsvd1:15; // 15:1 Reserved }; union NMICFG_REG { Uint16 all; struct NMICFG_BITS bit; }; struct NMIFLG_BITS { // bits description Uint16 NMIINT:1; // 0 NMI Interrupt Flag Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag Uint16 ERADNMI:1; // 7 ERAD Module NMI Flag Uint16 CLBNMI:1; // 8 Configurable Logic Block NMI Flag Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag Uint16 rsvd1:1; // 11 Reserved Uint16 CMNMIWDRSn:1; // 12 CM NMI watch dog has timed out. Uint16 ECATNMIn:1; // 13 NMI from EtherCAT reset out Uint16 CRC_FAIL:1; // 14 CRC calculation failed. Uint16 rsvd2:1; // 15 Reserved }; union NMIFLG_REG { Uint16 all; struct NMIFLG_BITS bit; }; struct NMIFLGCLR_BITS { // bits description Uint16 NMIINT:1; // 0 NMIINT Flag Clear Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear Uint16 ERADNMI:1; // 7 ERADNMI Flag Clear Uint16 CLBNMI:1; // 8 CLBNMI Flag Clear Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear Uint16 rsvd1:1; // 11 Reserved Uint16 CMNMIWDRSn:1; // 12 DCDCOLF Flag Clear Uint16 ECATNMIn:1; // 13 ECATNMIn flag clear Uint16 CRC_FAIL:1; // 14 CRC_FAIL flag clear Uint16 rsvd2:1; // 15 Reserved }; union NMIFLGCLR_REG { Uint16 all; struct NMIFLGCLR_BITS bit; }; struct NMIFLGFRC_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force Uint16 ERADNMI:1; // 7 ERADNMI Flag Force Uint16 CLBNMI:1; // 8 CLBNMI Flag Force Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force Uint16 rsvd2:1; // 11 Reserved Uint16 CMNMIWDRSn:1; // 12 DCDCOLF Flag Force Uint16 ECATNMIn:1; // 13 ECATNMIn flag force Uint16 CRC_FAIL:1; // 14 CRC_FAIL flag force Uint16 rsvd3:1; // 15 Reserved }; union NMIFLGFRC_REG { Uint16 all; struct NMIFLGFRC_BITS bit; }; struct NMISHDFLG_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag Uint16 ERADNMI:1; // 7 Shadow ERADNMI Flag Uint16 CLBNMI:1; // 8 Shadow CLBNMI Flag Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag Uint16 rsvd2:1; // 11 Reserved Uint16 CMNMIWDRSn:1; // 12 Shadow DCDCOLF Flag Uint16 ECATNMIn:1; // 13 ECATNMIn flag Uint16 CRC_FAIL:1; // 14 CRC_FAIL flag Uint16 rsvd3:1; // 15 Reserved }; union NMISHDFLG_REG { Uint16 all; struct NMISHDFLG_BITS bit; }; struct ERRORSTS_BITS { // bits description Uint16 ERROR:1; // 0 Error flag. Uint16 PINSTS:1; // 1 Error pin status. Uint16 rsvd1:14; // 15:2 Reserved }; union ERRORSTS_REG { Uint16 all; struct ERRORSTS_BITS bit; }; struct ERRORSTSCLR_BITS { // bits description Uint16 ERROR:1; // 0 ERRORFLG.ERROR clear bit Uint16 rsvd1:15; // 15:1 Reserved }; union ERRORSTSCLR_REG { Uint16 all; struct ERRORSTSCLR_BITS bit; }; struct ERRORSTSFRC_BITS { // bits description Uint16 ERROR:1; // 0 ERRORSTS.ERROR pin force. Uint16 rsvd1:15; // 15:1 Reserved }; union ERRORSTSFRC_REG { Uint16 all; struct ERRORSTSFRC_BITS bit; }; struct ERRORCTL_BITS { // bits description Uint16 ERRORPOLSEL:1; // 0 ERROR pin polarity select Uint16 rsvd1:15; // 15:1 Reserved }; union ERRORCTL_REG { Uint16 all; struct ERRORCTL_BITS bit; }; struct ERRORLOCK_BITS { // bits description Uint16 ERRORCTL:1; // 0 ERRORCTL Lock bit Uint16 rsvd1:15; // 15:1 Reserved }; union ERRORLOCK_REG { Uint16 all; struct ERRORLOCK_BITS bit; }; struct NMI_INTRUPT_REGS { union NMICFG_REG NMICFG; // NMI Configuration Register union NMIFLG_REG NMIFLG; // NMI Flag Register (SYSRsn Clear) union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register Uint16 NMIWDCNT; // NMI Watchdog Counter Register Uint16 NMIWDPRD; // NMI Watchdog Period Register union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register union ERRORSTS_REG ERRORSTS; // Error pin status union ERRORSTSCLR_REG ERRORSTSCLR; // ERRORSTS clear register union ERRORSTSFRC_REG ERRORSTSFRC; // ERRORSTS force register union ERRORCTL_REG ERRORCTL; // Error pin control register union ERRORLOCK_REG ERRORLOCK; // Lock register to Error pin registers. }; //--------------------------------------------------------------------------- // NMIINTRUPT External References & Function Declarations: // extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_outputxbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XBAR Individual Register Bit Definitions: struct OUTPUT1MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUX0TO15CFG_REG { Uint32 all; struct OUTPUT1MUX0TO15CFG_BITS bit; }; struct OUTPUT1MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUX16TO31CFG_REG { Uint32 all; struct OUTPUT1MUX16TO31CFG_BITS bit; }; struct OUTPUT2MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUX0TO15CFG_REG { Uint32 all; struct OUTPUT2MUX0TO15CFG_BITS bit; }; struct OUTPUT2MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUX16TO31CFG_REG { Uint32 all; struct OUTPUT2MUX16TO31CFG_BITS bit; }; struct OUTPUT3MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUX0TO15CFG_REG { Uint32 all; struct OUTPUT3MUX0TO15CFG_BITS bit; }; struct OUTPUT3MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUX16TO31CFG_REG { Uint32 all; struct OUTPUT3MUX16TO31CFG_BITS bit; }; struct OUTPUT4MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUX0TO15CFG_REG { Uint32 all; struct OUTPUT4MUX0TO15CFG_BITS bit; }; struct OUTPUT4MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUX16TO31CFG_REG { Uint32 all; struct OUTPUT4MUX16TO31CFG_BITS bit; }; struct OUTPUT5MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUX0TO15CFG_REG { Uint32 all; struct OUTPUT5MUX0TO15CFG_BITS bit; }; struct OUTPUT5MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUX16TO31CFG_REG { Uint32 all; struct OUTPUT5MUX16TO31CFG_BITS bit; }; struct OUTPUT6MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUX0TO15CFG_REG { Uint32 all; struct OUTPUT6MUX0TO15CFG_BITS bit; }; struct OUTPUT6MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUX16TO31CFG_REG { Uint32 all; struct OUTPUT6MUX16TO31CFG_BITS bit; }; struct OUTPUT7MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUX0TO15CFG_REG { Uint32 all; struct OUTPUT7MUX0TO15CFG_BITS bit; }; struct OUTPUT7MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUX16TO31CFG_REG { Uint32 all; struct OUTPUT7MUX16TO31CFG_BITS bit; }; struct OUTPUT8MUX0TO15CFG_BITS { // bits description Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUX0TO15CFG_REG { Uint32 all; struct OUTPUT8MUX0TO15CFG_BITS bit; }; struct OUTPUT8MUX16TO31CFG_BITS { // bits description Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUX16TO31CFG_REG { Uint32 all; struct OUTPUT8MUX16TO31CFG_BITS bit; }; struct OUTPUT1MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR }; union OUTPUT1MUXENABLE_REG { Uint32 all; struct OUTPUT1MUXENABLE_BITS bit; }; struct OUTPUT2MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR }; union OUTPUT2MUXENABLE_REG { Uint32 all; struct OUTPUT2MUXENABLE_BITS bit; }; struct OUTPUT3MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR }; union OUTPUT3MUXENABLE_REG { Uint32 all; struct OUTPUT3MUXENABLE_BITS bit; }; struct OUTPUT4MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR }; union OUTPUT4MUXENABLE_REG { Uint32 all; struct OUTPUT4MUXENABLE_BITS bit; }; struct OUTPUT5MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR }; union OUTPUT5MUXENABLE_REG { Uint32 all; struct OUTPUT5MUXENABLE_BITS bit; }; struct OUTPUT6MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR }; union OUTPUT6MUXENABLE_REG { Uint32 all; struct OUTPUT6MUXENABLE_BITS bit; }; struct OUTPUT7MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR }; union OUTPUT7MUXENABLE_REG { Uint32 all; struct OUTPUT7MUXENABLE_BITS bit; }; struct OUTPUT8MUXENABLE_BITS { // bits description Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR }; union OUTPUT8MUXENABLE_REG { Uint32 all; struct OUTPUT8MUXENABLE_BITS bit; }; struct OUTPUTLATCH_BITS { // bits description Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCH_REG { Uint32 all; struct OUTPUTLATCH_BITS bit; }; struct OUTPUTLATCHCLR_BITS { // bits description Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHCLR_REG { Uint32 all; struct OUTPUTLATCHCLR_BITS bit; }; struct OUTPUTLATCHFRC_BITS { // bits description Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHFRC_REG { Uint32 all; struct OUTPUTLATCHFRC_BITS bit; }; struct OUTPUTLATCHENABLE_BITS { // bits description Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTLATCHENABLE_REG { Uint32 all; struct OUTPUTLATCHENABLE_BITS bit; }; struct OUTPUTINV_BITS { // bits description Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union OUTPUTINV_REG { Uint32 all; struct OUTPUTINV_BITS bit; }; struct OUTPUTLOCK_BITS { // bits description Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Write Protection KEY }; union OUTPUTLOCK_REG { Uint32 all; struct OUTPUTLOCK_BITS bit; }; struct OUTPUT_XBAR_REGS { union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion Uint16 rsvd1[4]; // Reserved union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register }; //--------------------------------------------------------------------------- // OUTPUT_XBAR External References & Function Declarations: // extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_pbist.h // // TITLE: Definitions for the PBIST registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PBIST Individual Register Bit Definitions: struct RAMT_BITS { // bits description Uint16 rsvd1:16; // 15:0 Reserved Uint16 RDS:8; // 23:16 Return Data Select Uint16 RGS:8; // 31:24 RAM Group Select }; union RAMT_REG { Uint32 all; struct RAMT_BITS bit; }; struct DLRT_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 ROM_TEST:1; // 2 ROM-based testing Uint16 TCK_GATED:1; // 3 TCK gated Uint16 CONFIG_ACC:1; // 4 Config Access Uint16 rsvd3:1; // 5 Reserved Uint16 rsvd4:1; // 6 Reserved Uint16 rsvd5:1; // 7 Reserved Uint16 rsvd6:1; // 8 Reserved Uint16 GO_NOGO_TEST:1; // 9 GO/ NO-GO Testing Uint16 rsvd7:1; // 10 Reserved Uint16 rsvd8:5; // 15:11 Reserved Uint16 rsvd9:16; // 31:16 Reserved }; union DLRT_REG { Uint32 all; struct DLRT_BITS bit; }; struct STR_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 RESUME:1; // 1 Resume / Emulation Read Uint16 STOP:1; // 2 Stops PBIST testing Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:2; // 6:5 Reserved Uint16 rsvd5:1; // 7 Reserved Uint16 rsvd6:1; // 8 Reserved Uint16 rsvd7:7; // 15:9 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union STR_REG { Uint32 all; struct STR_BITS bit; }; struct PACT_BITS { // bits description Uint16 ENABLE:1; // 0 Enable clocks to PBIST Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PACT_REG { Uint32 all; struct PACT_BITS bit; }; struct OVERRIDE_BITS { // bits description Uint16 RINFO_MEM_OVER:1; // 0 ROM Memory Information Override Uint16 rsvd1:2; // 2:1 Reserved Uint16 ALGO_OVER:1; // 3 ROM Algorithm Override Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union OVERRIDE_REG { Uint32 all; struct OVERRIDE_BITS bit; }; struct PBIST_REGS { Uint16 rsvd1[352]; // Reserved union RAMT_REG RAMT; // RAM Configuration Register Uint16 rsvd2[2]; // Reserved union DLRT_REG DLRT; // PBIST Data Logger Register Uint16 rsvd3[6]; // Reserved union STR_REG STR; // Program Control Register Uint16 rsvd4[18]; // Reserved union PACT_REG PACT; // PBIST Activate Register Uint16 rsvd5[6]; // Reserved union OVERRIDE_REG OVERRIDE; // PBIST Override Register Uint16 rsvd6[6]; // Reserved Uint32 FSRF0; // Fail Status - Port 0 Uint16 rsvd7[2]; // Reserved Uint32 FSRF1; // Fail Status - Port 1 Uint16 rsvd8[2]; // Reserved Uint32 FSRC0; // Fail Status Count - Port 0 Uint16 rsvd9[2]; // Reserved Uint32 FSRC1; // Fail Status Count - Port 1 Uint16 rsvd10[38]; // Reserved Uint32 ALGO; // PBIST Algorithm Uint16 rsvd11[2]; // Reserved Uint32 RINFOL; // RAM Info Mask Register Lower Uint16 rsvd12[2]; // Reserved Uint32 RINFOU; // RAM Info Mask Register Higher }; //--------------------------------------------------------------------------- // PBIST External References & Function Declarations: // extern volatile struct PBIST_REGS PbistRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_piectrl.h // // TITLE: Definitions for the PIE registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PIE Individual Register Bit Definitions: struct PIECTRL_BITS { // bits description Uint16 ENPIE:1; // 0 PIE Enable Uint16 PIEVECT:15; // 15:1 PIE Vector Address }; union PIECTRL_REG { Uint16 all; struct PIECTRL_BITS bit; }; struct PIEACK_BITS { // bits description Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 Uint16 rsvd1:4; // 15:12 Reserved }; union PIEACK_REG { Uint16 all; struct PIEACK_BITS bit; }; struct PIEIER1_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 }; union PIEIER1_REG { Uint16 all; struct PIEIER1_BITS bit; }; struct PIEIFR1_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 }; union PIEIFR1_REG { Uint16 all; struct PIEIFR1_BITS bit; }; struct PIEIER2_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 }; union PIEIER2_REG { Uint16 all; struct PIEIER2_BITS bit; }; struct PIEIFR2_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 }; union PIEIFR2_REG { Uint16 all; struct PIEIFR2_BITS bit; }; struct PIEIER3_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 }; union PIEIER3_REG { Uint16 all; struct PIEIER3_BITS bit; }; struct PIEIFR3_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 }; union PIEIFR3_REG { Uint16 all; struct PIEIFR3_BITS bit; }; struct PIEIER4_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 }; union PIEIER4_REG { Uint16 all; struct PIEIER4_BITS bit; }; struct PIEIFR4_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 }; union PIEIFR4_REG { Uint16 all; struct PIEIFR4_BITS bit; }; struct PIEIER5_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 }; union PIEIER5_REG { Uint16 all; struct PIEIER5_BITS bit; }; struct PIEIFR5_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 }; union PIEIFR5_REG { Uint16 all; struct PIEIFR5_BITS bit; }; struct PIEIER6_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 }; union PIEIER6_REG { Uint16 all; struct PIEIER6_BITS bit; }; struct PIEIFR6_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 }; union PIEIFR6_REG { Uint16 all; struct PIEIFR6_BITS bit; }; struct PIEIER7_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 }; union PIEIER7_REG { Uint16 all; struct PIEIER7_BITS bit; }; struct PIEIFR7_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 }; union PIEIFR7_REG { Uint16 all; struct PIEIFR7_BITS bit; }; struct PIEIER8_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 }; union PIEIER8_REG { Uint16 all; struct PIEIER8_BITS bit; }; struct PIEIFR8_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 }; union PIEIFR8_REG { Uint16 all; struct PIEIFR8_BITS bit; }; struct PIEIER9_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 }; union PIEIER9_REG { Uint16 all; struct PIEIER9_BITS bit; }; struct PIEIFR9_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 }; union PIEIFR9_REG { Uint16 all; struct PIEIFR9_BITS bit; }; struct PIEIER10_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 }; union PIEIER10_REG { Uint16 all; struct PIEIER10_BITS bit; }; struct PIEIFR10_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 }; union PIEIFR10_REG { Uint16 all; struct PIEIFR10_BITS bit; }; struct PIEIER11_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 }; union PIEIER11_REG { Uint16 all; struct PIEIER11_BITS bit; }; struct PIEIFR11_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 }; union PIEIFR11_REG { Uint16 all; struct PIEIFR11_BITS bit; }; struct PIEIER12_BITS { // bits description Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 }; union PIEIER12_REG { Uint16 all; struct PIEIER12_BITS bit; }; struct PIEIFR12_BITS { // bits description Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 }; union PIEIFR12_REG { Uint16 all; struct PIEIFR12_BITS bit; }; struct PIE_CTRL_REGS { union PIECTRL_REG PIECTRL; // ePIE Control Register union PIEACK_REG PIEACK; // Interrupt Acknowledge Register union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register }; //--------------------------------------------------------------------------- // PIECTRL External References & Function Declarations: // extern volatile struct PIE_CTRL_REGS PieCtrlRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_pievect.h // // TITLE: Definitions for the PIE Vector Table. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PIE Interrupt Vector Table Definition: // Create a user type called PINT (pointer to interrupt): typedef __interrupt void (*PINT)(void); // Define Vector Table: struct PIE_VECT_TABLE { PINT PIE1_RESERVED_INT; // Reserved PINT PIE2_RESERVED_INT; // Reserved PINT PIE3_RESERVED_INT; // Reserved PINT PIE4_RESERVED_INT; // Reserved PINT PIE5_RESERVED_INT; // Reserved PINT PIE6_RESERVED_INT; // Reserved PINT PIE7_RESERVED_INT; // Reserved PINT PIE8_RESERVED_INT; // Reserved PINT PIE9_RESERVED_INT; // Reserved PINT PIE10_RESERVED_INT; // Reserved PINT PIE11_RESERVED_INT; // Reserved PINT PIE12_RESERVED_INT; // Reserved PINT PIE13_RESERVED_INT; // Reserved PINT TIMER1_INT; // CPU Timer 1 Interrupt PINT TIMER2_INT; // CPU Timer 2 Interrupt PINT DATALOG_INT; // Datalogging Interrupt PINT RTOS_INT; // RTOS Interrupt PINT EMU_INT; // Emulation Interrupt PINT NMI_INT; // Non-Maskable Interrupt PINT ILLEGAL_INT; // Illegal Operation Trap PINT USER1_INT; // User Defined Trap 1 PINT USER2_INT; // User Defined Trap 2 PINT USER3_INT; // User Defined Trap 3 PINT USER4_INT; // User Defined Trap 4 PINT USER5_INT; // User Defined Trap 5 PINT USER6_INT; // User Defined Trap 6 PINT USER7_INT; // User Defined Trap 7 PINT USER8_INT; // User Defined Trap 8 PINT USER9_INT; // User Defined Trap 9 PINT USER10_INT; // User Defined Trap 10 PINT USER11_INT; // User Defined Trap 11 PINT USER12_INT; // User Defined Trap 12 PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 PINT XINT1_INT; // 1.4 - XINT1 Interrupt PINT XINT2_INT; // 1.5 - XINT2 Interrupt PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1 PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt PINT ECAP7_INT; // 4.7 - eCAP7 Interrupt PINT PIE14_RESERVED_INT; // 4.8 - Reserved PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt PINT PIE15_RESERVED_INT; // 5.4 - Reserved PINT CLB1_INT; // 5.5 - CLB1 (Reconfigurable Logic) Interrupt PINT CLB2_INT; // 5.6 - CLB2 (Reconfigurable Logic) Interrupt PINT CLB3_INT; // 5.7 - CLB3 (Reconfigurable Logic) Interrupt PINT CLB4_INT; // 5.8 - CLB4 (Reconfigurable Logic) Interrupt PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt PINT PIE16_RESERVED_INT; // 7.7 - Reserved PINT PIE17_RESERVED_INT; // 7.8 - Reserved PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 PINT I2CB_INT; // 8.3 - I2CB Interrupt 1 PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2 PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt PINT CANA0_INT; // 9.5 - CANA Interrupt 0 PINT CANA1_INT; // 9.6 - CANA Interrupt 1 PINT CANB0_INT; // 9.7 - CANB Interrupt 0 PINT CANB1_INT; // 9.8 - CANB Interrupt 1 PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 PINT XINT3_INT; // 12.1 - XINT3 Interrupt PINT XINT4_INT; // 12.2 - XINT4 Interrupt PINT XINT5_INT; // 12.3 - XINT5 Interrupt PINT PBIST_INT; // 12.4 - PBIST Interrupt PINT FMC_INT; // 12.5 - Flash Wrapper Operation Done Interrupt PINT PIE18_RESERVED_INT; // 12.6 - Reserved PINT FPU_OFLOW_INT; // 12.7 - FPU Overflow Interrupt PINT FPU_UFLOW_INT; // 12.8 - FPU Underflow Interrupt PINT I2CA_HIGH_INT; // 1.9 - I2CA Interrupt high priority PINT SYS_ERR_INT; // 1.10 - System error interrupt PINT ECATSYNC0_INT; // 1.11 - ETHERCAT SYNC0 interrupt PINT ECAT_INT; // 1.12 - ETHERCAT main interrupt PINT CIPC0_INT; // 1.13 - C28x CPU IPC interrupt 0 PINT CIPC1_INT; // 1.14 - C28x CPU IPC interrupt 1 PINT CIPC2_INT; // 1.15 - C28x CPU IPC interrupt 2 PINT CIPC3_INT; // 1.16 - C28x CPU IPC interrupt 3 PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt PINT EPWM13_TZ_INT; // 2.13 - ePWM13 Trip Zone Interrupt PINT EPWM14_TZ_INT; // 2.14 - ePWM14 Trip Zone Interrupt PINT EPWM15_TZ_INT; // 2.15 - ePWM15 Trip Zone Interrupt PINT EPWM16_TZ_INT; // 2.16 - ePWM16 Trip Zone Interrupt PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt PINT EPWM13_INT; // 3.13 - ePWM13 Interrupt PINT EPWM14_INT; // 3.14 - ePWM14 Interrupt PINT EPWM15_INT; // 3.15 - ePWM15 Interrupt PINT EPWM16_INT; // 3.16 - ePWM16 Interrupt PINT FSITXA1_INT; // 4.9 - FSIA Transmit interrupt 1 PINT FSITXA2_INT; // 4.10 - FSIA Transmit interrupt 2 PINT FSITXB1_INT; // 4.11 - FSIB Transmit interrupt 1 PINT FSITXB2_INT; // 4.12 - FSIB Transmit interrupt 2 PINT FSIRXA1_INT; // 4.13 - FSIA Receive interrupt 1 PINT FSIRXA2_INT; // 4.14 - FSIA Receive interrupt 2 PINT FSIRXB1_INT; // 4.15 - FSIB Receive interrupt 1 PINT FSIRXB2_INT; // 4.16 - FSIB Receive interrupt 2 PINT SDFM1_INT; // 5.9 - Sigma Delta Filter Module1 Interrupt PINT SDFM2_INT; // 5.10 - Sigma Delta Filter Module2 Interrupt PINT ECATRST_INT; // 5.11 - ETHERCAT Resetout Interrupt PINT ECATSYNC1_INT; // 5.12 - ETHERCAT SYNC1 interrupt PINT SDFM1DR1_INT; // 5.13 - Sigma Delta Filter Module1 Filter 1 Interrupt PINT SDFM1DR2_INT; // 5.14 - Sigma Delta Filter Module1 Filter 2 Interrupt PINT SDFM1DR3_INT; // 5.15 - Sigma Delta Filter Module1 Filter 3 Interrupt PINT SDFM1DR4_INT; // 5.16 - Sigma Delta Filter Module1 Filter 4 Interrupt PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt PINT SPID_RX_INT; // 6.11 - SPID Receive Interrupt PINT SPID_TX_INT; // 6.12 - SPID Transmit Interrupt PINT SDFM2DR1_INT; // 6.13 - Sigma Delta Filter Module2 Filter 1 Interrupt PINT SDFM2DR2_INT; // 6.14 - Sigma Delta Filter Module2 Filter 2 Interrupt PINT SDFM2DR3_INT; // 6.15 - Sigma Delta Filter Module2 Filter 3 Interrupt PINT SDFM2DR4_INT; // 6.16 - Sigma Delta Filter Module2 Filter 4 Interrupt PINT FSIRXC1_INT; // 7.9 - FSIC Receive interrupt 1 PINT FSIRXC2_INT; // 7.10 - FSIC Receive interrupt 2 PINT FSIRXD1_INT; // 7.11 - FSID Receive interrupt 1 PINT FSIRXD2_INT; // 7.12 - FSID Receive interrupt 2 PINT FSIRXE1_INT; // 7.13 - FSIE Receive interrupt 1 PINT FSIRXE2_INT; // 7.14 - FSIE Receive interrupt 2 PINT FSIRXF1_INT; // 7.15 - FSIF Receive interrupt 1 PINT FSIRXF2_INT; // 7.16 - FSIF Receive interrupt 2 PINT FSIRXG1_INT; // 8.9 - FSIG Receive interrupt 1 PINT FSIRXG2_INT; // 8.10 - FSIG Receive interrupt 2 PINT FSIRXH1_INT; // 8.11 - FSIH Receive interrupt 1 PINT FSIRXH2_INT; // 8.12 - FSIH Receive interrupt 2 PINT PIE22_RESERVED_INT; // 8.13 - CLB5 Interrupt PINT PIE23_RESERVED_INT; // 8.14 - CLB6 Interrupt PINT PIE24_RESERVED_INT; // 8.15 - CLB7 Interrupt PINT PIE25_RESERVED_INT; // 8.16 - CLB8 Interrupt PINT MCANSS0_INT; // 9.9 - MCAN Sub-System Interrupt 0 PINT MCANSS1_INT; // 9.10 - MCAN Sub-System Interrupt 1 PINT MCANSS_ECC_CORR_PLS_INT; // 9.11 - MCAN Sub-System ECC error Interrupt PINT MCANSS_WAKE_AND_TS_PLS_INT; // 9.12 - MCAN Sub-System wakeup Interrupt PINT PMBUSA_INT; // 9.13 - PMBUSA Interrupt PINT CM_STATUS_INT; // 9.14 - CM Reset Status Interrupt PINT USBA_INT; // 9.15 - USBA Interrupt PINT PIE19_RESERVED_INT; // 9.16 - Reserved PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2 PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3 PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4 PINT CMTOCPUXIPC0_INT; // 11.9 - CM to CPU IPC Interrupt 0 PINT CMTOCPUXIPC1_INT; // 11.10 - CM to CPU IPC Interrupt 1 PINT CMTOCPUXIPC2_INT; // 11.11 - CM to CPU IPC Interrupt 2 PINT CMTOCPUXIPC3_INT; // 11.12 - CM to CPU IPC Interrupt 3 PINT CMTOCPUXIPC4_INT; // 11.13 - CM to CPU IPC Interrupt 4 PINT CMTOCPUXIPC5_INT; // 11.14 - CM to CPU IPC Interrupt 5 PINT CMTOCPUXIPC6_INT; // 11.15 - CM to CPU IPC Interrupt 6 PINT CMTOCPUXIPC7_INT; // 11.16 - CM to CPU IPC Interrupt 7 PINT PIE20_RESERVED_INT; // 12.9 - Reserved PINT ECAP6_2_INT; // 12.10 - eCAP6 Interrupt 2 PINT ECAP7_2_INT; // 12.11 - eCAP7 Interrupt 2 PINT PIE21_RESERVED_INT; // 12.12 - Reserved PINT CPUCRC_INT; // 12.13 - CPU BGCRC module interrupt PINT CLA1CRC_INT; // 12.14 - CLA1 BGCRC module interrupt PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt }; //--------------------------------------------------------------------------- // PieVect External References & Function Declarations: // extern volatile struct PIE_VECT_TABLE PieVectTable; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_pmbus.h // // TITLE: Definitions for the PMBUS registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // PMBUS Individual Register Bit Definitions: struct PMBMC_BITS { // bits description Uint16 RW:1; // 0 RnW bit of the Message Uint16 SLAVE_ADDR:7; // 7:1 Slave Address Uint16 BYTE_COUNT:8; // 15:8 Number of Bytes Transmitted Uint16 CMD_ENA:1; // 16 Master Command Code Enable Uint16 EXT_CMD:1; // 17 Master Extended Command Code Enable Uint16 PEC_ENA:1; // 18 Master PEC Processing Enable Uint16 GRP_CMD:1; // 19 Master Group Command Message Enable Uint16 PRC_CALL:1; // 20 Master Process Call Message Enable Uint16 rsvd1:11; // 31:21 Reserved }; union PMBMC_REG { Uint32 all; struct PMBMC_BITS bit; }; struct PMBACK_BITS { // bits description Uint16 ACK:1; // 0 Allows firmware to ack/nack received data Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBACK_REG { Uint32 all; struct PMBACK_BITS bit; }; struct PMBSTS_BITS { // bits description Uint16 RD_BYTE_COUNT:3; // 2:0 Number of Data Bytes available in Receive Data Register Uint16 DATA_READY:1; // 3 Data Ready Flag Uint16 DATA_REQUEST:1; // 4 Data Request Flag Uint16 EOM:1; // 5 End of Message Indicator Uint16 NACK:1; // 6 Not Acknowledge Flag Status Uint16 PEC_VALID:1; // 7 PEC Valid Indicator Uint16 CLK_LOW_TIMEOUT:1; // 8 Clock Low Timeout Status Uint16 CLK_HIGH_DETECTED:1; // 9 Clock High Detection Status Uint16 SLAVE_ADDR_READY:1; // 10 Slave Address Ready Uint16 RPT_START:1; // 11 Repeated Start Flag Uint16 UNIT_BUSY:1; // 12 PMBus Busy Indicator Uint16 BUS_FREE:1; // 13 PMBus Free Indicator Uint16 LOST_ARB:1; // 14 Lost Arbitration Flag Uint16 MASTER:1; // 15 Master Indicator Uint16 ALERT_EDGE:1; // 16 Alert Edge Detection Status Uint16 CONTROL_EDGE:1; // 17 Control Edge Detection Status Uint16 ALERT_RAW:1; // 18 Alert Pin Real Time Status Uint16 CONTROL_RAW:1; // 19 Control Pin Real Time Status Uint16 SDA_RAW:1; // 20 PMBus Data Pin Real Time Status Uint16 SCL_RAW:1; // 21 PMBus Clock Pin Real Time Status Uint16 rsvd1:10; // 31:22 Reserved }; union PMBSTS_REG { Uint32 all; struct PMBSTS_BITS bit; }; struct PMBINTM_BITS { // bits description Uint16 BUS_FREE:1; // 0 Bus Free Interrupt Mask Uint16 BUS_LOW_TIMEOUT:1; // 1 Clock Low Timeout Interrupt Mask Uint16 DATA_READY:1; // 2 Data Ready Interrupt Mask Uint16 DATA_REQUEST:1; // 3 Data Request Interrupt Mask Uint16 SLAVE_ADDR_READY:1; // 4 Slave Address Ready Interrupt Mask Uint16 EOM:1; // 5 End of Message Interrupt Mask Uint16 ALERT:1; // 6 Alert Detection Interrupt Mask Uint16 CONTROL:1; // 7 Control Detection Interrupt Mask Uint16 LOST_ARB:1; // 8 Lost Arbitration Interrupt Mask Uint16 CLK_HIGH_DETECT:1; // 9 Clock High Detection Interrupt Mask Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBINTM_REG { Uint32 all; struct PMBINTM_BITS bit; }; struct PMBSC_BITS { // bits description Uint16 SLAVE_ADDR:7; // 6:0 Configures the current device address of the slave. Uint16 MAN_SLAVE_ACK:1; // 7 Manual Slave Address Acknowledgement Mode Uint16 SLAVE_MASK:7; // 14:8 Slave address mask Uint16 PEC_ENA:1; // 15 PEC Processing Enable Uint16 TX_COUNT:3; // 18:16 Number of valid bytes in Transmit Data Register Uint16 TX_PEC:1; // 19 send a PEC byte at end of message Uint16 MAN_CMD:1; // 20 Manual Command Acknowledgement Mode Uint16 RX_BYTE_ACK_CNT:2; // 22:21 Number of data bytes to automatically acknowledge Uint16 rsvd1:9; // 31:23 Reserved }; union PMBSC_REG { Uint32 all; struct PMBSC_BITS bit; }; struct PMBHSA_BITS { // bits description Uint16 SLAVE_RW:1; // 0 Stored R/W bit Uint16 SLAVE_ADDR:7; // 7:1 Stored device address Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBHSA_REG { Uint32 all; struct PMBHSA_BITS bit; }; struct PMBCTRL_BITS { // bits description Uint16 RESET:1; // 0 PMBus Interface Synchronous Reset Uint16 ALERT_EN:1; // 1 Slave Alert Enable Uint16 BUS_LO_INT_EDGE:1; // 2 Clock Low Timeout Interrupt Edge Select Uint16 FAST_MODE:1; // 3 Fast Mode Enable Uint16 rsvd1:1; // 4 Reserved Uint16 CNTL_INT_EDGE:1; // 5 Control Interrupt Edge Select Uint16 ALERT_MODE:1; // 6 Configures mode of Alert pin Uint16 ALERT_VALUE:1; // 7 Configures output value of Alert pin in GPIO Mode Uint16 ALERT_DIR:1; // 8 Configures direction of Alert pin in GPIO mode Uint16 CNTL_MODE:1; // 9 Configures mode of Control pin Uint16 CNTL_VALUE:1; // 10 Configures output value of Control pin in GPIO Mode Uint16 CNTL_DIR:1; // 11 Configures direction of Control pin in GPIO mode Uint16 SDA_MODE:1; // 12 Configures mode of PMBus Data pin Uint16 SDA_VALUE:1; // 13 Configures output value of PMBus data pin in GPIO Mode Uint16 SDA_DIR:1; // 14 Configures direction of PMBus data pin in GPIO mode Uint16 SCL_MODE:1; // 15 Configures mode of PMBus Clock pin Uint16 SCL_VALUE:1; // 16 Configures output value of PMBus clock pin in GPIO Mode Uint16 SCL_DIR:1; // 17 Configures direction of PMBus clock pin in GPIO mode Uint16 IBIAS_A_EN:1; // 18 PMBus Current Source A Control Uint16 IBIAS_B_EN:1; // 19 PMBus Current Source B Control Uint16 CLK_LO_DIS:1; // 20 Clock Low Timeout Disable Uint16 SLAVE_EN:1; // 21 PMBus Slave Enable Uint16 MASTER_EN:1; // 22 PMBus Master Enable Uint16 CLKDIV:5; // 27:23 PMBUS Clock Divide Value Uint16 rsvd2:3; // 30:28 Reserved Uint16 I2CMODE:1; // 31 Bit to enable I2C mode }; union PMBCTRL_REG { Uint32 all; struct PMBCTRL_BITS bit; }; struct PMBTIMCTL_BITS { // bits description Uint16 TIM_OVERRIDE:1; // 0 Overide the default settings of the timing parameters. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMCTL_REG { Uint32 all; struct PMBTIMCTL_BITS bit; }; struct PMBTIMCLK_BITS { // bits description Uint16 CLK_HIGH_LIMIT:8; // 7:0 Determines the PMBUS master clock high pulse width. Uint16 rsvd1:8; // 15:8 Reserved Uint16 CLK_FREQ:8; // 23:16 Determines the PMBUS master clock frequency. Uint16 rsvd2:8; // 31:24 Reserved }; union PMBTIMCLK_REG { Uint32 all; struct PMBTIMCLK_BITS bit; }; struct PMBTIMSTSETUP_BITS { // bits description Uint16 TSU_STA:8; // 7:0 Setup time, rise edge of PMBUS master clock to start edge. Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMSTSETUP_REG { Uint32 all; struct PMBTIMSTSETUP_BITS bit; }; struct PMBTIMBIDLE_BITS { // bits description Uint16 BUSIDLE:10; // 9:0 Determines the Bus Idle Limit Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMBIDLE_REG { Uint32 all; struct PMBTIMBIDLE_BITS bit; }; struct PMBTIMLOWTIMOUT_BITS { // bits description Uint32 CLKLOWTIMOUT:20; // 19:0 Determines the clock low timeout value Uint16 rsvd1:12; // 31:20 Reserved }; union PMBTIMLOWTIMOUT_REG { Uint32 all; struct PMBTIMLOWTIMOUT_BITS bit; }; struct PMBTIMHIGHTIMOUT_BITS { // bits description Uint16 CLKHIGHTIMOUT:10; // 9:0 Determines the clock high timeout value Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBTIMHIGHTIMOUT_REG { Uint32 all; struct PMBTIMHIGHTIMOUT_BITS bit; }; struct PMBUS_REGS { union PMBMC_REG PMBMC; // PMBUS Master Mode Control Register Uint32 PMBTXBUF; // PMBUS Transmit Buffer Uint32 PMBRXBUF; // PMBUS Receive buffer union PMBACK_REG PMBACK; // PMBUS Acknowledge Register union PMBSTS_REG PMBSTS; // PMBUS Status Register union PMBINTM_REG PMBINTM; // PMBUS Interrupt Mask Register union PMBSC_REG PMBSC; // PMBUS Slave Mode Configuration Register union PMBHSA_REG PMBHSA; // PMBUS Hold Slave Address Register union PMBCTRL_REG PMBCTRL; // PMBUS Control Register union PMBTIMCTL_REG PMBTIMCTL; // PMBUS Timing Control Register union PMBTIMCLK_REG PMBTIMCLK; // PMBUS Clock Timing Register union PMBTIMSTSETUP_REG PMBTIMSTSETUP; // PMBUS Start Setup Time Register union PMBTIMBIDLE_REG PMBTIMBIDLE; // PMBUS Bus Idle Time Register union PMBTIMLOWTIMOUT_REG PMBTIMLOWTIMOUT; // PMBUS Clock Low Timeout Value Register union PMBTIMHIGHTIMOUT_REG PMBTIMHIGHTIMOUT; // PMBUS Clock High Timeout Value Register }; //--------------------------------------------------------------------------- // PMBUS External References & Function Declarations: // extern volatile struct PMBUS_REGS PmbusaRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_sci.h // // TITLE: Definitions for the SCI registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SCI Individual Register Bit Definitions: struct SCICCR_BITS { // bits description Uint16 SCICHAR:3; // 2:0 Character length control Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control Uint16 LOOPBKENA:1; // 4 Loop Back enable Uint16 PARITYENA:1; // 5 Parity enable Uint16 PARITY:1; // 6 Even or Odd Parity Uint16 STOPBITS:1; // 7 Number of Stop Bits Uint16 rsvd1:8; // 15:8 Reserved }; union SCICCR_REG { Uint16 all; struct SCICCR_BITS bit; }; struct SCICTL1_BITS { // bits description Uint16 RXENA:1; // 0 SCI receiver enable Uint16 TXENA:1; // 1 SCI transmitter enable Uint16 SLEEP:1; // 2 SCI sleep Uint16 TXWAKE:1; // 3 Transmitter wakeup method Uint16 rsvd1:1; // 4 Reserved Uint16 SWRESET:1; // 5 Software reset Uint16 RXERRINTENA:1; // 6 Receive error interrupt enable Uint16 rsvd2:9; // 15:7 Reserved }; union SCICTL1_REG { Uint16 all; struct SCICTL1_BITS bit; }; struct SCIHBAUD_BITS { // bits description Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD Uint16 rsvd1:8; // 15:8 Reserved }; union SCIHBAUD_REG { Uint16 all; struct SCIHBAUD_BITS bit; }; struct SCILBAUD_BITS { // bits description Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD Uint16 rsvd1:8; // 15:8 Reserved }; union SCILBAUD_REG { Uint16 all; struct SCILBAUD_BITS bit; }; struct SCICTL2_BITS { // bits description Uint16 TXINTENA:1; // 0 Transmit __interrupt enable Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable Uint16 rsvd1:4; // 5:2 Reserved Uint16 TXEMPTY:1; // 6 Transmitter empty flag Uint16 TXRDY:1; // 7 Transmitter ready flag Uint16 rsvd2:8; // 15:8 Reserved }; union SCICTL2_REG { Uint16 all; struct SCICTL2_BITS bit; }; struct SCIRXST_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag Uint16 PE:1; // 2 Parity error flag Uint16 OE:1; // 3 Overrun error flag Uint16 FE:1; // 4 Framing error flag Uint16 BRKDT:1; // 5 Break-detect flag Uint16 RXRDY:1; // 6 Receiver ready flag Uint16 RXERROR:1; // 7 Receiver error flag Uint16 rsvd2:8; // 15:8 Reserved }; union SCIRXST_REG { Uint16 all; struct SCIRXST_BITS bit; }; struct SCIRXEMU_BITS { // bits description Uint16 ERXDT:8; // 7:0 Receive emulation buffer data Uint16 rsvd1:8; // 15:8 Reserved }; union SCIRXEMU_REG { Uint16 all; struct SCIRXEMU_BITS bit; }; struct SCIRXBUF_BITS { // bits description Uint16 SAR:8; // 7:0 Receive Character bits Uint16 rsvd1:6; // 13:8 Reserved Uint16 SCIFFPE:1; // 14 Receiver error flag Uint16 SCIFFFE:1; // 15 Receiver error flag }; union SCIRXBUF_REG { Uint16 all; struct SCIRXBUF_BITS bit; }; struct SCITXBUF_BITS { // bits description Uint16 TXDT:8; // 7:0 Transmit data buffer Uint16 rsvd1:8; // 15:8 Reserved }; union SCITXBUF_REG { Uint16 all; struct SCITXBUF_BITS bit; }; struct SCIFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 Interrupt level Uint16 TXFFIENA:1; // 5 Interrupt enable Uint16 TXFFINTCLR:1; // 6 Clear INT flag Uint16 TXFFINT:1; // 7 INT flag Uint16 TXFFST:5; // 12:8 FIFO status Uint16 TXFIFORESET:1; // 13 FIFO reset Uint16 SCIFFENA:1; // 14 Enhancement enable Uint16 SCIRST:1; // 15 SCI reset rx/tx channels }; union SCIFFTX_REG { Uint16 all; struct SCIFFTX_BITS bit; }; struct SCIFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 Interrupt level Uint16 RXFFIENA:1; // 5 Interrupt enable Uint16 RXFFINTCLR:1; // 6 Clear INT flag Uint16 RXFFINT:1; // 7 INT flag Uint16 RXFFST:5; // 12:8 FIFO status Uint16 RXFIFORESET:1; // 13 FIFO reset Uint16 RXFFOVRCLR:1; // 14 Clear overflow Uint16 RXFFOVF:1; // 15 FIFO overflow }; union SCIFFRX_REG { Uint16 all; struct SCIFFRX_BITS bit; }; struct SCIFFCT_BITS { // bits description Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay Uint16 rsvd1:5; // 12:8 Reserved Uint16 CDC:1; // 13 Auto baud mode enable Uint16 ABDCLR:1; // 14 Auto baud clear Uint16 ABD:1; // 15 Auto baud detect }; union SCIFFCT_REG { Uint16 all; struct SCIFFCT_BITS bit; }; struct SCIPRI_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 FREESOFT:2; // 4:3 Emulation modes Uint16 rsvd2:3; // 7:5 Reserved Uint16 rsvd3:8; // 15:8 Reserved }; union SCIPRI_REG { Uint16 all; struct SCIPRI_BITS bit; }; struct SCI_REGS { union SCICCR_REG SCICCR; // Communications control register union SCICTL1_REG SCICTL1; // Control register 1 union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register union SCILBAUD_REG SCILBAUD; // Baud rate (low) register union SCICTL2_REG SCICTL2; // Control register 2 union SCIRXST_REG SCIRXST; // Receive status register union SCIRXEMU_REG SCIRXEMU; // Receive emulation buffer register union SCIRXBUF_REG SCIRXBUF; // Receive data buffer Uint16 rsvd1; // Reserved union SCITXBUF_REG SCITXBUF; // Transmit data buffer union SCIFFTX_REG SCIFFTX; // FIFO transmit register union SCIFFRX_REG SCIFFRX; // FIFO receive register union SCIFFCT_REG SCIFFCT; // FIFO control register Uint16 rsvd2[2]; // Reserved union SCIPRI_REG SCIPRI; // SCI priority control }; //--------------------------------------------------------------------------- // SCI External References & Function Declarations: // extern volatile struct SCI_REGS SciaRegs; extern volatile struct SCI_REGS ScibRegs; extern volatile struct SCI_REGS ScicRegs; extern volatile struct SCI_REGS ScidRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_sdfm.h // // TITLE: Definitions for the SDFM registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SDFM Individual Register Bit Definitions: struct SDIFLG_BITS { // bits description Uint16 FLT1_FLG_CEVT1:1; // 0 High-level Interrupt flag for Ch1 Uint16 FLT1_FLG_CEVT2:1; // 1 Low-level Interrupt flag for Ch1 Uint16 FLT2_FLG_CEVT1:1; // 2 High-level Interrupt flag for Ch2 Uint16 FLT2_FLG_CEVT2:1; // 3 Low-level Interrupt flag for Ch2 Uint16 FLT3_FLG_CEVT1:1; // 4 High-level Interrupt flag for Ch3 Uint16 FLT3_FLG_CEVT2:1; // 5 Low-level Interrupt flag for Ch3 Uint16 FLT4_FLG_CEVT1:1; // 6 High-level Interrupt flag for Ch4 Uint16 FLT4_FLG_CEVT2:1; // 7 Low-level Interrupt flag for Ch4 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 Uint16 SDFFOVF1:1; // 16 FIFO Overflow Flag for Ch1. Uint16 SDFFOVF2:1; // 17 FIFO Overflow Flag for Ch2 Uint16 SDFFOVF3:1; // 18 FIFO Overflow Flag for Ch3 Uint16 SDFFOVF4:1; // 19 FIFO Overflow Flag for Ch4 Uint16 SDFFINT1:1; // 20 SDFIFO interrupt for Ch1 Uint16 SDFFINT2:1; // 21 SDFIFO interrupt for Ch2 Uint16 SDFFINT3:1; // 22 SDFIFO interrupt for Ch3 Uint16 SDFFINT4:1; // 23 SDFIFO interrupt for Ch4 Uint16 rsvd1:7; // 30:24 Reserved Uint16 MIF:1; // 31 Master Interrupt Flag }; union SDIFLG_REG { Uint32 all; struct SDIFLG_BITS bit; }; struct SDIFLGCLR_BITS { // bits description Uint16 FLT1_FLG_CEVT1:1; // 0 High-level Interrupt flag for Ch1 Uint16 FLT1_FLG_CEVT2:1; // 1 Low-level Interrupt flag for Ch1 Uint16 FLT2_FLG_CEVT1:1; // 2 High-level Interrupt flag for Ch2 Uint16 FLT2_FLG_CEVT2:1; // 3 Low-level Interrupt flag for Ch2 Uint16 FLT3_FLG_CEVT1:1; // 4 High-level Interrupt flag for Ch3 Uint16 FLT3_FLG_CEVT2:1; // 5 Low-level Interrupt flag for Ch3 Uint16 FLT4_FLG_CEVT1:1; // 6 High-level Interrupt flag for Ch4 Uint16 FLT4_FLG_CEVT2:1; // 7 Low-level Interrupt flag for Ch4 Uint16 MF1:1; // 8 Modulator Failure for Filter 1 Uint16 MF2:1; // 9 Modulator Failure for Filter 2 Uint16 MF3:1; // 10 Modulator Failure for Filter 3 Uint16 MF4:1; // 11 Modulator Failure for Filter 4 Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 Uint16 SDFFOVF1:1; // 16 SDFIFO overflow clear Ch1 Uint16 SDFFOVF2:1; // 17 SDFIFO overflow clear Ch2 Uint16 SDFFOVF3:1; // 18 SDFIFO overflow clear Ch3 Uint16 SDFFOVF4:1; // 19 SDFIFO overflow clear Ch4 Uint16 SDFFINT1:1; // 20 SDFIFO Interrupt flag-clear bit for Ch1 Uint16 SDFFINT2:1; // 21 SDFIFO Interrupt flag-clear bit for Ch2 Uint16 SDFFINT3:1; // 22 SDFIFO Interrupt flag-clear bit for Ch3 Uint16 SDFFINT4:1; // 23 SDFIFO Interrupt flag-clear bit for Ch4 Uint16 rsvd1:7; // 30:24 Reserved Uint16 MIF:1; // 31 Master Interrupt Flag }; union SDIFLGCLR_REG { Uint32 all; struct SDIFLGCLR_BITS bit; }; struct SDCTL_BITS { // bits description Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 Uint16 rsvd1:9; // 12:4 Reserved Uint16 MIE:1; // 13 Master SDy_ERR Interrupt enable Uint16 rsvd2:1; // 14 Reserved Uint16 rsvd3:1; // 15 Reserved }; union SDCTL_REG { Uint16 all; struct SDCTL_BITS bit; }; struct SDMFILEN_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 rsvd2:3; // 6:4 Reserved Uint16 rsvd3:2; // 8:7 Reserved Uint16 rsvd4:1; // 9 Reserved Uint16 rsvd5:1; // 10 Reserved Uint16 MFE:1; // 11 Master Filter Enable. Uint16 rsvd6:1; // 12 Reserved Uint16 rsvd7:3; // 15:13 Reserved }; union SDMFILEN_REG { Uint16 all; struct SDMFILEN_BITS bit; }; struct SDSTATUS_BITS { // bits description Uint16 HZ1:1; // 0 High-level Threshold crossing (Z) flag Ch1 Uint16 HZ2:1; // 1 High-level Threshold crossing (Z) flag Ch2 Uint16 HZ3:1; // 2 High-level Threshold crossing (Z) flag Ch3 Uint16 HZ4:1; // 3 High-level Threshold crossing (Z) flag Ch4 Uint16 rsvd1:4; // 7:4 Reserved Uint16 rsvd2:1; // 8 Reserved Uint16 rsvd3:1; // 9 Reserved Uint16 rsvd4:1; // 10 Reserved Uint16 rsvd5:1; // 11 Reserved Uint16 rsvd6:1; // 12 Reserved Uint16 rsvd7:1; // 13 Reserved Uint16 rsvd8:1; // 14 Reserved Uint16 rsvd9:1; // 15 Reserved }; union SDSTATUS_REG { Uint16 all; struct SDSTATUS_BITS bit; }; struct SDCTLPARM1_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 SDCLKSEL:1; // 3 SD1 Clock source select. Uint16 SDCLKSYNC:1; // 4 Enable Synchronizer on SD clock Uint16 rsvd2:1; // 5 Reserved Uint16 SDDATASYNC:1; // 6 Enable Synchronizer on SD data Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:8; // 15:8 Reserved }; union SDCTLPARM1_REG { Uint16 all; struct SDCTLPARM1_BITS bit; }; struct SDDFPARM1_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM1_REG { Uint16 all; struct SDDFPARM1_BITS bit; }; struct SDDPARM1_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM1_REG { Uint16 all; struct SDDPARM1_BITS bit; }; struct SDFLT1CMPH1_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT1CMPH1_REG { Uint16 all; struct SDFLT1CMPH1_BITS bit; }; struct SDFLT1CMPL1_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT1CMPL1_REG { Uint16 all; struct SDFLT1CMPL1_BITS bit; }; struct SDCPARM1_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 EN_CEVT1:1; // 5 CEVT1 Interrupt enable. Uint16 EN_CEVT2:1; // 6 CEVT2 Interrupt enable. Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 CEVT1SEL:2; // 12:11 Comparator Event1 select Uint16 CEN:1; // 13 Comparator Enable Uint16 CEVT2SEL:2; // 15:14 Comparator Event2 select }; union SDCPARM1_REG { Uint16 all; struct SDCPARM1_BITS bit; }; struct SDDATA1_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA1_REG { Uint32 all; struct SDDATA1_BITS bit; }; struct SDDATFIFO1_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO1_REG { Uint32 all; struct SDDATFIFO1_BITS bit; }; struct SDFLT1CMPH2_BITS { // bits description Uint16 HLT2:15; // 14:0 Second High level threshold. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT1CMPH2_REG { Uint16 all; struct SDFLT1CMPH2_BITS bit; }; struct SDFLT1CMPHZ_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT1CMPHZ_REG { Uint16 all; struct SDFLT1CMPHZ_BITS bit; }; struct SDFIFOCTL1_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL1_REG { Uint16 all; struct SDFIFOCTL1_BITS bit; }; struct SDSYNC1_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC1_REG { Uint16 all; struct SDSYNC1_BITS bit; }; struct SDFLT1CMPL2_BITS { // bits description Uint16 LLT2:15; // 14:0 Second low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT1CMPL2_REG { Uint16 all; struct SDFLT1CMPL2_BITS bit; }; struct SDCTLPARM2_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 SDCLKSEL:1; // 3 SD2 Clock source select. Uint16 SDCLKSYNC:1; // 4 Enable Synchronizer on SD clock Uint16 rsvd2:1; // 5 Reserved Uint16 SDDATASYNC:1; // 6 Enable Synchronizer on SD data Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:8; // 15:8 Reserved }; union SDCTLPARM2_REG { Uint16 all; struct SDCTLPARM2_BITS bit; }; struct SDDFPARM2_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM2_REG { Uint16 all; struct SDDFPARM2_BITS bit; }; struct SDDPARM2_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM2_REG { Uint16 all; struct SDDPARM2_BITS bit; }; struct SDFLT2CMPH1_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT2CMPH1_REG { Uint16 all; struct SDFLT2CMPH1_BITS bit; }; struct SDFLT2CMPL1_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT2CMPL1_REG { Uint16 all; struct SDFLT2CMPL1_BITS bit; }; struct SDCPARM2_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 EN_CEVT1:1; // 5 CEVT1 Interrupt enable. Uint16 EN_CEVT2:1; // 6 CEVT2 Interrupt enable. Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 CEVT1SEL:2; // 12:11 Comparator Event1 select Uint16 CEN:1; // 13 Comparator Enable Uint16 CEVT2SEL:2; // 15:14 Comparator Event2 select }; union SDCPARM2_REG { Uint16 all; struct SDCPARM2_BITS bit; }; struct SDDATA2_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA2_REG { Uint32 all; struct SDDATA2_BITS bit; }; struct SDDATFIFO2_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO2_REG { Uint32 all; struct SDDATFIFO2_BITS bit; }; struct SDFLT2CMPH2_BITS { // bits description Uint16 HLT2:15; // 14:0 Second High level threshold. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT2CMPH2_REG { Uint16 all; struct SDFLT2CMPH2_BITS bit; }; struct SDFLT2CMPHZ_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT2CMPHZ_REG { Uint16 all; struct SDFLT2CMPHZ_BITS bit; }; struct SDFIFOCTL2_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL2_REG { Uint16 all; struct SDFIFOCTL2_BITS bit; }; struct SDSYNC2_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC2_REG { Uint16 all; struct SDSYNC2_BITS bit; }; struct SDFLT2CMPL2_BITS { // bits description Uint16 LLT2:15; // 14:0 Second low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT2CMPL2_REG { Uint16 all; struct SDFLT2CMPL2_BITS bit; }; struct SDCTLPARM3_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 SDCLKSEL:1; // 3 SD3 Clock source select. Uint16 SDCLKSYNC:1; // 4 Enable Synchronizer on SD clock Uint16 rsvd2:1; // 5 Reserved Uint16 SDDATASYNC:1; // 6 Enable Synchronizer on SD data Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:8; // 15:8 Reserved }; union SDCTLPARM3_REG { Uint16 all; struct SDCTLPARM3_BITS bit; }; struct SDDFPARM3_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM3_REG { Uint16 all; struct SDDFPARM3_BITS bit; }; struct SDDPARM3_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM3_REG { Uint16 all; struct SDDPARM3_BITS bit; }; struct SDFLT3CMPH1_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT3CMPH1_REG { Uint16 all; struct SDFLT3CMPH1_BITS bit; }; struct SDFLT3CMPL1_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT3CMPL1_REG { Uint16 all; struct SDFLT3CMPL1_BITS bit; }; struct SDCPARM3_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 EN_CEVT1:1; // 5 CEVT1 Interrupt enable. Uint16 EN_CEVT2:1; // 6 CEVT2 Interrupt enable. Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 CEVT1SEL:2; // 12:11 Comparator Event1 select Uint16 CEN:1; // 13 Comparator Enable Uint16 CEVT2SEL:2; // 15:14 Comparator Event2 select }; union SDCPARM3_REG { Uint16 all; struct SDCPARM3_BITS bit; }; struct SDDATA3_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA3_REG { Uint32 all; struct SDDATA3_BITS bit; }; struct SDDATFIFO3_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO3_REG { Uint32 all; struct SDDATFIFO3_BITS bit; }; struct SDFLT3CMPH2_BITS { // bits description Uint16 HLT2:15; // 14:0 Second High level threshold. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT3CMPH2_REG { Uint16 all; struct SDFLT3CMPH2_BITS bit; }; struct SDFLT3CMPHZ_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT3CMPHZ_REG { Uint16 all; struct SDFLT3CMPHZ_BITS bit; }; struct SDFIFOCTL3_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL3_REG { Uint16 all; struct SDFIFOCTL3_BITS bit; }; struct SDSYNC3_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC3_REG { Uint16 all; struct SDSYNC3_BITS bit; }; struct SDFLT3CMPL2_BITS { // bits description Uint16 LLT2:15; // 14:0 Second low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT3CMPL2_REG { Uint16 all; struct SDFLT3CMPL2_BITS bit; }; struct SDCTLPARM4_BITS { // bits description Uint16 MOD:2; // 1:0 Modulator clocking modes Uint16 rsvd1:1; // 2 Reserved Uint16 SDCLKSEL:1; // 3 SD4 Clock source select. Uint16 SDCLKSYNC:1; // 4 Enable Synchronizer on SD clock Uint16 rsvd2:1; // 5 Reserved Uint16 SDDATASYNC:1; // 6 Enable Synchronizer on SD data Uint16 rsvd3:1; // 7 Reserved Uint16 rsvd4:8; // 15:8 Reserved }; union SDCTLPARM4_REG { Uint16 all; struct SDCTLPARM4_BITS bit; }; struct SDDFPARM4_BITS { // bits description Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 Uint16 FEN:1; // 8 Filter Enable Uint16 AE:1; // 9 Ack Enable Uint16 SST:2; // 11:10 Data filter Structure (SincFast/1/2/3) Uint16 SDSYNCEN:1; // 12 Data Filter Reset Enable Uint16 rsvd1:3; // 15:13 Reserved }; union SDDFPARM4_REG { Uint16 all; struct SDDFPARM4_BITS bit; }; struct SDDPARM4_BITS { // bits description Uint16 rsvd1:10; // 9:0 Reserved Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) }; union SDDPARM4_REG { Uint16 all; struct SDDPARM4_BITS bit; }; struct SDFLT4CMPH1_BITS { // bits description Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT4CMPH1_REG { Uint16 all; struct SDFLT4CMPH1_BITS bit; }; struct SDFLT4CMPL1_BITS { // bits description Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT4CMPL1_REG { Uint16 all; struct SDFLT4CMPL1_BITS bit; }; struct SDCPARM4_BITS { // bits description Uint16 COSR:5; // 4:0 Comparator Oversample Ratio. Actual rate COSR+1 Uint16 EN_CEVT1:1; // 5 CEVT1 Interrupt enable. Uint16 EN_CEVT2:1; // 6 CEVT2 Interrupt enable. Uint16 CS1_CS0:2; // 8:7 Comparator Filter Structure (SincFast/1/2/3) Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable Uint16 HZEN:1; // 10 High level (Z) Threshold crossing output enable Uint16 CEVT1SEL:2; // 12:11 Comparator Event1 select Uint16 CEN:1; // 13 Comparator Enable Uint16 CEVT2SEL:2; // 15:14 Comparator Event2 select }; union SDCPARM4_REG { Uint16 all; struct SDCPARM4_BITS bit; }; struct SDDATA4_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATA4_REG { Uint32 all; struct SDDATA4_BITS bit; }; struct SDDATFIFO4_BITS { // bits description Uint16 DATA16:16; // 15:0 Lo-order 16b in 32b mode Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode, 16-bit Data in 16b mode }; union SDDATFIFO4_REG { Uint32 all; struct SDDATFIFO4_BITS bit; }; struct SDFLT4CMPH2_BITS { // bits description Uint16 HLT2:15; // 14:0 Second High level threshold. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT4CMPH2_REG { Uint16 all; struct SDFLT4CMPH2_BITS bit; }; struct SDFLT4CMPHZ_BITS { // bits description Uint16 HLTZ:15; // 14:0 High-level threshold (Z) for the comparator filter output Uint16 rsvd1:1; // 15 Reserved }; union SDFLT4CMPHZ_REG { Uint16 all; struct SDFLT4CMPHZ_BITS bit; }; struct SDFIFOCTL4_BITS { // bits description Uint16 SDFFIL:5; // 4:0 SDFIFO Interrupt Level Uint16 rsvd1:1; // 5 Reserved Uint16 SDFFST:5; // 10:6 SDFIFO Status Uint16 rsvd2:1; // 11 Reserved Uint16 FFIEN:1; // 12 SDFIFO data ready Interrupt Enable Uint16 FFEN:1; // 13 SDFIFO Enable Uint16 DRINTSEL:1; // 14 Data-Ready Interrupt Source Select Uint16 OVFIEN:1; // 15 SDFIFO Overflow interrupt enable }; union SDFIFOCTL4_REG { Uint16 all; struct SDFIFOCTL4_BITS bit; }; struct SDSYNC4_BITS { // bits description Uint16 SYNCSEL:6; // 5:0 SDSYNC Source Select Uint16 WTSYNCEN:1; // 6 Wait-for-Sync Enable Uint16 WTSYNFLG:1; // 7 Wait-for-Sync Flag Uint16 WTSYNCLR:1; // 8 Wait-for-Sync Flag Clear Uint16 FFSYNCCLREN:1; // 9 FIFO Clear-on-SDSYNC Enable Uint16 WTSCLREN:1; // 10 WTSYNFLG Clear-on-FIFOINT Enable Uint16 rsvd1:5; // 15:11 Reserved }; union SDSYNC4_REG { Uint16 all; struct SDSYNC4_BITS bit; }; struct SDFLT4CMPL2_BITS { // bits description Uint16 LLT2:15; // 14:0 Second low-level threshold for the comparator filter output. Uint16 rsvd1:1; // 15 Reserved }; union SDFLT4CMPL2_REG { Uint16 all; struct SDFLT4CMPL2_BITS bit; }; struct SDCOMP1CTL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CEVT1DIGFILTSEL:2; // 3:2 High Comparator Trip Select Uint16 rsvd3:2; // 5:4 Reserved Uint16 rsvd4:1; // 6 Reserved Uint16 rsvd5:1; // 7 Reserved Uint16 rsvd6:1; // 8 Reserved Uint16 rsvd7:1; // 9 Reserved Uint16 CEVT2DIGFILTSEL:2; // 11:10 Low Comparator Trip Select Uint16 rsvd8:2; // 13:12 Reserved Uint16 rsvd9:1; // 14 Reserved Uint16 rsvd10:1; // 15 Reserved }; union SDCOMP1CTL_REG { Uint16 all; struct SDCOMP1CTL_BITS bit; }; struct SDCOMP1EVT2FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP1EVT2FLTCTL_REG { Uint16 all; struct SDCOMP1EVT2FLTCTL_BITS bit; }; struct SDCOMP1EVT2FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP1EVT2FLTCLKCTL_REG { Uint16 all; struct SDCOMP1EVT2FLTCLKCTL_BITS bit; }; struct SDCOMP1EVT1FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP1EVT1FLTCTL_REG { Uint16 all; struct SDCOMP1EVT1FLTCTL_BITS bit; }; struct SDCOMP1EVT1FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP1EVT1FLTCLKCTL_REG { Uint16 all; struct SDCOMP1EVT1FLTCLKCTL_BITS bit; }; struct SDCOMP1LOCK_BITS { // bits description Uint16 SDCOMP1CTL:1; // 0 COMPCTL Lock Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 COMP:1; // 3 COMPevent filter registers Lock Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCOMP1LOCK_REG { Uint16 all; struct SDCOMP1LOCK_BITS bit; }; struct SDCOMP2CTL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CEVT1DIGFILTSEL:2; // 3:2 High Comparator Trip Select Uint16 rsvd3:2; // 5:4 Reserved Uint16 rsvd4:1; // 6 Reserved Uint16 rsvd5:1; // 7 Reserved Uint16 rsvd6:1; // 8 Reserved Uint16 rsvd7:1; // 9 Reserved Uint16 CEVT2DIGFILTSEL:2; // 11:10 Low Comparator Trip Select Uint16 rsvd8:2; // 13:12 Reserved Uint16 rsvd9:1; // 14 Reserved Uint16 rsvd10:1; // 15 Reserved }; union SDCOMP2CTL_REG { Uint16 all; struct SDCOMP2CTL_BITS bit; }; struct SDCOMP2EVT2FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP2EVT2FLTCTL_REG { Uint16 all; struct SDCOMP2EVT2FLTCTL_BITS bit; }; struct SDCOMP2EVT2FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP2EVT2FLTCLKCTL_REG { Uint16 all; struct SDCOMP2EVT2FLTCLKCTL_BITS bit; }; struct SDCOMP2EVT1FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP2EVT1FLTCTL_REG { Uint16 all; struct SDCOMP2EVT1FLTCTL_BITS bit; }; struct SDCOMP2EVT1FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP2EVT1FLTCLKCTL_REG { Uint16 all; struct SDCOMP2EVT1FLTCLKCTL_BITS bit; }; struct SDCOMP2LOCK_BITS { // bits description Uint16 SDCOMP2CTL:1; // 0 COMPCTL Lock Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 COMP:1; // 3 COMPevent filter registers Lock Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCOMP2LOCK_REG { Uint16 all; struct SDCOMP2LOCK_BITS bit; }; struct SDCOMP3CTL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CEVT1DIGFILTSEL:2; // 3:2 High Comparator Trip Select Uint16 rsvd3:2; // 5:4 Reserved Uint16 rsvd4:1; // 6 Reserved Uint16 rsvd5:1; // 7 Reserved Uint16 rsvd6:1; // 8 Reserved Uint16 rsvd7:1; // 9 Reserved Uint16 CEVT2DIGFILTSEL:2; // 11:10 Low Comparator Trip Select Uint16 rsvd8:2; // 13:12 Reserved Uint16 rsvd9:1; // 14 Reserved Uint16 rsvd10:1; // 15 Reserved }; union SDCOMP3CTL_REG { Uint16 all; struct SDCOMP3CTL_BITS bit; }; struct SDCOMP3EVT2FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP3EVT2FLTCTL_REG { Uint16 all; struct SDCOMP3EVT2FLTCTL_BITS bit; }; struct SDCOMP3EVT2FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP3EVT2FLTCLKCTL_REG { Uint16 all; struct SDCOMP3EVT2FLTCLKCTL_BITS bit; }; struct SDCOMP3EVT1FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP3EVT1FLTCTL_REG { Uint16 all; struct SDCOMP3EVT1FLTCTL_BITS bit; }; struct SDCOMP3EVT1FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP3EVT1FLTCLKCTL_REG { Uint16 all; struct SDCOMP3EVT1FLTCLKCTL_BITS bit; }; struct SDCOMP3LOCK_BITS { // bits description Uint16 SDCOMP3CTL:1; // 0 COMPCTL Lock Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 COMP:1; // 3 COMPevent filter registers Lock Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCOMP3LOCK_REG { Uint16 all; struct SDCOMP3LOCK_BITS bit; }; struct SDCOMP4CTL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CEVT1DIGFILTSEL:2; // 3:2 High Comparator Trip Select Uint16 rsvd3:2; // 5:4 Reserved Uint16 rsvd4:1; // 6 Reserved Uint16 rsvd5:1; // 7 Reserved Uint16 rsvd6:1; // 8 Reserved Uint16 rsvd7:1; // 9 Reserved Uint16 CEVT2DIGFILTSEL:2; // 11:10 Low Comparator Trip Select Uint16 rsvd8:2; // 13:12 Reserved Uint16 rsvd9:1; // 14 Reserved Uint16 rsvd10:1; // 15 Reserved }; union SDCOMP4CTL_REG { Uint16 all; struct SDCOMP4CTL_BITS bit; }; struct SDCOMP4EVT2FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP4EVT2FLTCTL_REG { Uint16 all; struct SDCOMP4EVT2FLTCTL_BITS bit; }; struct SDCOMP4EVT2FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP4EVT2FLTCLKCTL_REG { Uint16 all; struct SDCOMP4EVT2FLTCLKCTL_BITS bit; }; struct SDCOMP4EVT1FLTCTL_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 SAMPWIN:5; // 8:4 Sample Window Uint16 THRESH:5; // 13:9 Majority Voting Threshold Uint16 rsvd2:1; // 14 Reserved Uint16 FILINIT:1; // 15 Filter Initialization Bit }; union SDCOMP4EVT1FLTCTL_REG { Uint16 all; struct SDCOMP4EVT1FLTCTL_BITS bit; }; struct SDCOMP4EVT1FLTCLKCTL_BITS { // bits description Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale Uint16 rsvd1:6; // 15:10 Reserved }; union SDCOMP4EVT1FLTCLKCTL_REG { Uint16 all; struct SDCOMP4EVT1FLTCLKCTL_BITS bit; }; struct SDCOMP4LOCK_BITS { // bits description Uint16 SDCOMP4CTL:1; // 0 COMPCTL Lock Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:1; // 2 Reserved Uint16 COMP:1; // 3 COMPevent filter registers Lock Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved }; union SDCOMP4LOCK_REG { Uint16 all; struct SDCOMP4LOCK_BITS bit; }; struct SDFM_REGS { union SDIFLG_REG SDIFLG; // SD Interrupt Flag Register union SDIFLGCLR_REG SDIFLGCLR; // SD Interrupt Flag Clear Register union SDCTL_REG SDCTL; // SD Control Register Uint16 rsvd1; // Reserved union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable union SDSTATUS_REG SDSTATUS; // SD Status Register Uint16 rsvd2[8]; // Reserved union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 union SDDPARM1_REG SDDPARM1; // Data Parameter Register for Ch1 union SDFLT1CMPH1_REG SDFLT1CMPH1; // High-level Threshold Register for Ch1 union SDFLT1CMPL1_REG SDFLT1CMPL1; // Low-level Threshold Register for Ch1 union SDCPARM1_REG SDCPARM1; // Comparator Filter Parameter Register for Ch1 union SDDATA1_REG SDDATA1; // Data Filter Data Register (16 or 32bit) for Ch1 union SDDATFIFO1_REG SDDATFIFO1; // Filter Data FIFO Output(32b) for Ch1 Uint16 SDCDATA1; // Comparator Filter Data Register (16b) for Ch1 union SDFLT1CMPH2_REG SDFLT1CMPH2; // Second high level threhold for CH1 union SDFLT1CMPHZ_REG SDFLT1CMPHZ; // High-level (Z) Threshold Register for Ch1 union SDFIFOCTL1_REG SDFIFOCTL1; // FIFO Control Register for Ch1 union SDSYNC1_REG SDSYNC1; // SD Filter Sync control for Ch1 union SDFLT1CMPL2_REG SDFLT1CMPL2; // Second low level threhold for CH1 union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 union SDDPARM2_REG SDDPARM2; // Data Parameter Register for Ch2 union SDFLT2CMPH1_REG SDFLT2CMPH1; // High-level Threshold Register for Ch2 union SDFLT2CMPL1_REG SDFLT2CMPL1; // Low-level Threshold Register for Ch2 union SDCPARM2_REG SDCPARM2; // Comparator Filter Parameter Register for Ch2 union SDDATA2_REG SDDATA2; // Data Filter Data Register (16 or 32bit) for Ch2 union SDDATFIFO2_REG SDDATFIFO2; // Filter Data FIFO Output(32b) for Ch2 Uint16 SDCDATA2; // Comparator Filter Data Register (16b) for Ch2 union SDFLT2CMPH2_REG SDFLT2CMPH2; // Second high level threhold for CH2 union SDFLT2CMPHZ_REG SDFLT2CMPHZ; // High-level (Z) Threshold Register for Ch2 union SDFIFOCTL2_REG SDFIFOCTL2; // FIFO Control Register for Ch2 union SDSYNC2_REG SDSYNC2; // SD Filter Sync control for Ch2 union SDFLT2CMPL2_REG SDFLT2CMPL2; // Second low level threhold for CH2 union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 union SDDPARM3_REG SDDPARM3; // Data Parameter Register for Ch3 union SDFLT3CMPH1_REG SDFLT3CMPH1; // High-level Threshold Register for Ch3 union SDFLT3CMPL1_REG SDFLT3CMPL1; // Low-level Threshold Register for Ch3 union SDCPARM3_REG SDCPARM3; // Comparator Filter Parameter Register for Ch3 union SDDATA3_REG SDDATA3; // Data Filter Data Register (16 or 32bit) for Ch3 union SDDATFIFO3_REG SDDATFIFO3; // Filter Data FIFO Output(32b) for Ch3 Uint16 SDCDATA3; // Comparator Filter Data Register (16b) for Ch3 union SDFLT3CMPH2_REG SDFLT3CMPH2; // Second high level threhold for CH3 union SDFLT3CMPHZ_REG SDFLT3CMPHZ; // High-level (Z) Threshold Register for Ch3 union SDFIFOCTL3_REG SDFIFOCTL3; // FIFO Control Register for Ch3 union SDSYNC3_REG SDSYNC3; // SD Filter Sync control for Ch3 union SDFLT3CMPL2_REG SDFLT3CMPL2; // Second low level threhold for CH3 union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 union SDDPARM4_REG SDDPARM4; // Data Parameter Register for Ch4 union SDFLT4CMPH1_REG SDFLT4CMPH1; // High-level Threshold Register for Ch4 union SDFLT4CMPL1_REG SDFLT4CMPL1; // Low-level Threshold Register for Ch4 union SDCPARM4_REG SDCPARM4; // Comparator Filter Parameter Register for Ch4 union SDDATA4_REG SDDATA4; // Data Filter Data Register (16 or 32bit) for Ch4 union SDDATFIFO4_REG SDDATFIFO4; // Filter Data FIFO Output(32b) for Ch4 Uint16 SDCDATA4; // Comparator Filter Data Register (16b) for Ch4 union SDFLT4CMPH2_REG SDFLT4CMPH2; // Second high level threhold for CH4 union SDFLT4CMPHZ_REG SDFLT4CMPHZ; // High-level (Z) Threshold Register for Ch4 union SDFIFOCTL4_REG SDFIFOCTL4; // FIFO Control Register for Ch4 union SDSYNC4_REG SDSYNC4; // SD Filter Sync control for Ch4 union SDFLT4CMPL2_REG SDFLT4CMPL2; // Second low level threhold for CH4 Uint16 rsvd3[16]; // Reserved union SDCOMP1CTL_REG SDCOMP1CTL; // SD Comparator event filter1 Control Register union SDCOMP1EVT2FLTCTL_REG SDCOMP1EVT2FLTCTL; // COMPL/CEVT2 Digital filter1 Control Register union SDCOMP1EVT2FLTCLKCTL_REG SDCOMP1EVT2FLTCLKCTL; // COMPL/CEVT2 Digital filter1 Clock Control Register union SDCOMP1EVT1FLTCTL_REG SDCOMP1EVT1FLTCTL; // COMPH/CEVT1 Digital filter1 Control Register union SDCOMP1EVT1FLTCLKCTL_REG SDCOMP1EVT1FLTCLKCTL; // COMPH/CEVT1 Digital filter1 Clock Control Register Uint16 rsvd4[2]; // Reserved union SDCOMP1LOCK_REG SDCOMP1LOCK; // SD compartor event filter1 Lock Register union SDCOMP2CTL_REG SDCOMP2CTL; // SD Comparator event filter2 Control Register union SDCOMP2EVT2FLTCTL_REG SDCOMP2EVT2FLTCTL; // COMPL/CEVT2 Digital filter2 Control Register union SDCOMP2EVT2FLTCLKCTL_REG SDCOMP2EVT2FLTCLKCTL; // COMPL/CEVT2 Digital filter2 Clock Control Register union SDCOMP2EVT1FLTCTL_REG SDCOMP2EVT1FLTCTL; // COMPH/CEVT1 Digital filter2 Control Register union SDCOMP2EVT1FLTCLKCTL_REG SDCOMP2EVT1FLTCLKCTL; // COMPH/CEVT1 Digital filter2 Clock Control Register Uint16 rsvd5[2]; // Reserved union SDCOMP2LOCK_REG SDCOMP2LOCK; // SD compartor event filter2 Lock Register union SDCOMP3CTL_REG SDCOMP3CTL; // SD Comparator event filter3 Control Register union SDCOMP3EVT2FLTCTL_REG SDCOMP3EVT2FLTCTL; // COMPL/CEVT2 Digital filter3 Control Register union SDCOMP3EVT2FLTCLKCTL_REG SDCOMP3EVT2FLTCLKCTL; // COMPL/CEVT2 Digital filter3 Clock Control Register union SDCOMP3EVT1FLTCTL_REG SDCOMP3EVT1FLTCTL; // COMPH/CEVT1 Digital filter3 Control Register union SDCOMP3EVT1FLTCLKCTL_REG SDCOMP3EVT1FLTCLKCTL; // COMPH/CEVT1 Digital filter3 Clock Control Register Uint16 rsvd6[2]; // Reserved union SDCOMP3LOCK_REG SDCOMP3LOCK; // SD compartor event filter3 Lock Register union SDCOMP4CTL_REG SDCOMP4CTL; // SD Comparator event filter4 Control Register union SDCOMP4EVT2FLTCTL_REG SDCOMP4EVT2FLTCTL; // COMPL/CEVT2 Digital filter4 Control Register union SDCOMP4EVT2FLTCLKCTL_REG SDCOMP4EVT2FLTCLKCTL; // COMPL/CEVT2 Digital filter4 Clock Control Register union SDCOMP4EVT1FLTCTL_REG SDCOMP4EVT1FLTCTL; // COMPH/CEVT1 Digital filter4 Control Register union SDCOMP4EVT1FLTCLKCTL_REG SDCOMP4EVT1FLTCLKCTL; // COMPH/CEVT1 Digital filter4 Clock Control Register Uint16 rsvd7[2]; // Reserved union SDCOMP4LOCK_REG SDCOMP4LOCK; // SD compartor event filter4 Lock Register }; //--------------------------------------------------------------------------- // SDFM External References & Function Declarations: // extern volatile struct SDFM_REGS Sdfm1Regs; extern volatile struct SDFM_REGS Sdfm2Regs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_spi.h // // TITLE: Definitions for the SPI registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SPI Individual Register Bit Definitions: struct SPICCR_BITS { // bits description Uint16 SPICHAR:4; // 3:0 Character Length Control Uint16 SPILBK:1; // 4 SPI Loopback Uint16 HS_MODE:1; // 5 High Speed mode control Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity Uint16 SPISWRESET:1; // 7 SPI Software Reset Uint16 rsvd1:8; // 15:8 Reserved }; union SPICCR_REG { Uint16 all; struct SPICCR_BITS bit; }; struct SPICTL_BITS { // bits description Uint16 SPIINTENA:1; // 0 SPI Interupt Enable Uint16 TALK:1; // 1 Master/Slave Transmit Enable Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control Uint16 CLK_PHASE:1; // 3 SPI Clock Phase Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable Uint16 rsvd1:11; // 15:5 Reserved }; union SPICTL_REG { Uint16 all; struct SPICTL_BITS bit; }; struct SPISTS_BITS { // bits description Uint16 rsvd1:5; // 4:0 Reserved Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag Uint16 rsvd2:8; // 15:8 Reserved }; union SPISTS_REG { Uint16 all; struct SPISTS_BITS bit; }; struct SPIBRR_BITS { // bits description Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control Uint16 rsvd1:9; // 15:7 Reserved }; union SPIBRR_REG { Uint16 all; struct SPIBRR_BITS bit; }; struct SPIFFTX_BITS { // bits description Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag Uint16 TXFFST:5; // 12:8 Transmit FIFO Status Uint16 TXFIFO:1; // 13 TXFIFO Reset Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable Uint16 SPIRST:1; // 15 SPI Reset }; union SPIFFTX_REG { Uint16 all; struct SPIFFTX_BITS bit; }; struct SPIFFRX_BITS { // bits description Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag Uint16 RXFFST:5; // 12:8 Receive FIFO Status Uint16 RXFIFORESET:1; // 13 RXFIFO Reset Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag }; union SPIFFRX_REG { Uint16 all; struct SPIFFRX_BITS bit; }; struct SPIFFCT_BITS { // bits description Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits Uint16 rsvd1:8; // 15:8 Reserved }; union SPIFFCT_REG { Uint16 all; struct SPIFFCT_BITS bit; }; struct SPIPRI_BITS { // bits description Uint16 TRIWIRE:1; // 0 3-wire mode select bit Uint16 STEINV:1; // 1 SPISTE inversion bit Uint16 rsvd1:2; // 3:2 Reserved Uint16 FREE:1; // 4 Free emulation mode Uint16 SOFT:1; // 5 Soft emulation mode Uint16 rsvd2:1; // 6 Reserved Uint16 rsvd3:9; // 15:7 Reserved }; union SPIPRI_REG { Uint16 all; struct SPIPRI_BITS bit; }; struct SPI_REGS { union SPICCR_REG SPICCR; // SPI Configuration Control Register union SPICTL_REG SPICTL; // SPI Operation Control Register union SPISTS_REG SPISTS; // SPI Status Register Uint16 rsvd1; // Reserved union SPIBRR_REG SPIBRR; // SPI Baud Rate Register Uint16 rsvd2; // Reserved Uint16 SPIRXEMU; // SPI Emulation Buffer Register Uint16 SPIRXBUF; // SPI Serial Input Buffer Register Uint16 SPITXBUF; // SPI Serial Output Buffer Register Uint16 SPIDAT; // SPI Serial Data Register union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register Uint16 rsvd3[2]; // Reserved union SPIPRI_REG SPIPRI; // SPI Priority Control Register }; //--------------------------------------------------------------------------- // SPI External References & Function Declarations: // extern volatile struct SPI_REGS SpiaRegs; extern volatile struct SPI_REGS SpibRegs; extern volatile struct SPI_REGS SpicRegs; extern volatile struct SPI_REGS SpidRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_sysctrl.h // // TITLE: Definitions for the SYSCTRL registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SYSCTL Individual Register Bit Definitions: struct CLKSEM_BITS { // bits description Uint16 SEM:2; // 1:0 Semaphore for CLKCFG Ownership by CPU1 or CPU2 Uint16 rsvd1:14; // 15:2 Reserved Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register }; union CLKSEM_REG { Uint32 all; struct CLKSEM_BITS bit; }; struct CLKCFGLOCK1_BITS { // bits description Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register Uint16 SYSPLLCTL2:1; // 4 Lock bit for SYSPLLCTL2 register Uint16 SYSPLLCTL3:1; // 5 Lock bit for SYSPLLCTL3 register Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register Uint16 AUXPLLCTL1:1; // 7 Lock bit for AUXPLLCTL1 register Uint16 rsvd1:1; // 8 Reserved Uint16 rsvd2:1; // 9 Reserved Uint16 AUXPLLMULT:1; // 10 Lock bit for AUXPLLMULT register Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register Uint16 AUXCLKDIVSEL:1; // 12 Lock bit for AUXCLKDIVSEL register Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register Uint16 CLBCLKCTL:1; // 14 Lock bit for CLBCLKCTL register Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register Uint16 XTALCR:1; // 16 Lock bit for XTALCR register Uint16 ETHERCATCLKCTL:1; // 17 Lock bit for ETHERCATCLKCTL register Uint16 CMCLKCTL:1; // 18 Lock bit for CMCLKCTL register Uint16 rsvd3:13; // 31:19 Reserved }; union CLKCFGLOCK1_REG { Uint32 all; struct CLKCFGLOCK1_BITS bit; }; struct CLKSRCCTL1_BITS { // bits description Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit Uint16 rsvd1:1; // 2 Reserved Uint16 INTOSC2OFF_NOTSUPPORTED:1; // 3 Internal Oscillator 2 Off Bit Uint16 XTALOFF:1; // 4 Crystal (External) Oscillator Off Bit Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:10; // 15:6 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union CLKSRCCTL1_REG { Uint32 all; struct CLKSRCCTL1_BITS bit; }; struct CLKSRCCTL2_BITS { // bits description Uint16 AUXOSCCLKSRCSEL:2; // 1:0 AUXOSCCLK Source Select Bit Uint16 CANABCLKSEL:2; // 3:2 CANA Clock Source Select Bit Uint16 CANBBCLKSEL:2; // 5:4 CANB Clock Source Select Bit Uint16 rsvd1:2; // 7:6 Reserved Uint16 rsvd2:2; // 9:8 Reserved Uint16 MCANABITCLKSEL:2; // 11:10 MCAN (global) Bit-Clock Source Select Bit Uint16 rsvd3:4; // 15:12 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union CLKSRCCTL2_REG { Uint32 all; struct CLKSRCCTL2_BITS bit; }; struct CLKSRCCTL3_BITS { // bits description Uint16 XCLKOUTSEL:4; // 3:0 XCLKOUT Source Select Bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLKSRCCTL3_REG { Uint32 all; struct CLKSRCCTL3_BITS bit; }; struct SYSPLLCTL1_BITS { // bits description Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union SYSPLLCTL1_REG { Uint32 all; struct SYSPLLCTL1_BITS bit; }; struct SYSPLLMULT_BITS { // bits description Uint16 IMULT:8; // 7:0 SYSPLL Integer Multiplier Uint16 rsvd1:2; // 9:8 Reserved Uint16 rsvd2:2; // 11:10 Reserved Uint16 rsvd3:2; // 13:12 Reserved Uint16 rsvd4:2; // 15:14 Reserved Uint16 ODIV:5; // 20:16 Output Clock Divider Uint16 rsvd5:3; // 23:21 Reserved Uint16 REFDIV:5; // 28:24 Reference Clock Divider Uint16 rsvd6:3; // 31:29 Reserved }; union SYSPLLMULT_REG { Uint32 all; struct SYSPLLMULT_BITS bit; }; struct SYSPLLSTS_BITS { // bits description Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit Uint16 SLIPS_NOTSUPPORTED:1; // 1 SYSPLL Slip Status Bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union SYSPLLSTS_REG { Uint32 all; struct SYSPLLSTS_BITS bit; }; struct AUXPLLCTL1_BITS { // bits description Uint16 PLLEN:1; // 0 AUXPLL enable/disable bit Uint16 PLLCLKEN:1; // 1 AUXPLL bypassed or included in the AUXPLLCLK path Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union AUXPLLCTL1_REG { Uint32 all; struct AUXPLLCTL1_BITS bit; }; struct AUXPLLMULT_BITS { // bits description Uint16 IMULT:8; // 7:0 AUXPLL Integer Multiplier Uint16 rsvd1:2; // 9:8 Reserved Uint16 rsvd2:2; // 11:10 Reserved Uint16 rsvd3:2; // 13:12 Reserved Uint16 rsvd4:2; // 15:14 Reserved Uint16 ODIV:5; // 20:16 Output Clock Divider Uint16 rsvd5:3; // 23:21 Reserved Uint16 REFDIV:5; // 28:24 Reference Clock Divider Uint16 rsvd6:3; // 31:29 Reserved }; union AUXPLLMULT_REG { Uint32 all; struct AUXPLLMULT_BITS bit; }; struct AUXPLLSTS_BITS { // bits description Uint16 LOCKS:1; // 0 AUXPLL Lock Status Bit Uint16 SLIPS_NOTSUPPORTED:1; // 1 AUXPLL Slip Status Bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:12; // 15:4 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union AUXPLLSTS_REG { Uint32 all; struct AUXPLLSTS_BITS bit; }; struct SYSCLKDIVSEL_BITS { // bits description Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYSCLKDIVSEL_REG { Uint32 all; struct SYSCLKDIVSEL_BITS bit; }; struct AUXCLKDIVSEL_BITS { // bits description Uint16 AUXPLLDIV:3; // 2:0 AUXPLLCLK Divide Select Uint16 rsvd1:5; // 7:3 Reserved Uint16 MCANCLKDIV:5; // 12:8 Divider between CANFD Source Clock and CANFD Bit CLK Uint16 rsvd2:3; // 15:13 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union AUXCLKDIVSEL_REG { Uint32 all; struct AUXCLKDIVSEL_BITS bit; }; struct PERCLKDIVSEL_BITS { // bits description Uint16 EPWMCLKDIV:2; // 1:0 EPWM Clock Divide Select Uint16 rsvd1:2; // 3:2 Reserved Uint16 EMIF1CLKDIV:1; // 4 EMIF1 Clock Divide Select Uint16 rsvd2:1; // 5 Reserved Uint16 EMIF2CLKDIV:1; // 6 EMIF2 Clock Divide Select Uint16 rsvd3:9; // 15:7 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union PERCLKDIVSEL_REG { Uint32 all; struct PERCLKDIVSEL_BITS bit; }; struct XCLKOUTDIVSEL_BITS { // bits description Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union XCLKOUTDIVSEL_REG { Uint32 all; struct XCLKOUTDIVSEL_BITS bit; }; struct CLBCLKCTL_BITS { // bits description Uint16 CLBCLKDIV:3; // 2:0 CLB clock divider configuration. Uint16 rsvd1:1; // 3 Reserved Uint16 TILECLKDIV:1; // 4 CLB Tile clock divider configuration. Uint16 rsvd2:11; // 15:5 Reserved Uint16 CLKMODECLB1:1; // 16 Clock mode of CLB1 Uint16 CLKMODECLB2:1; // 17 Clock mode of CLB2 Uint16 CLKMODECLB3:1; // 18 Clock mode of CLB3 Uint16 CLKMODECLB4:1; // 19 Clock mode of CLB4 Uint16 rsvd4:1; // 20 Clock mode of CLB5 Uint16 rsvd5:1; // 21 Clock mode of CLB6 Uint16 rsvd6:1; // 22 Clock mode of CLB7 Uint16 rsvd7:1; // 23 Clock mode of CLB8 Uint16 rsvd3:8; // 31:24 Reserved }; union CLBCLKCTL_REG { Uint32 all; struct CLBCLKCTL_BITS bit; }; struct LOSPCP_BITS { // bits description Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union LOSPCP_REG { Uint32 all; struct LOSPCP_BITS bit; }; struct MCDCR_BITS { // bits description Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCDCR_REG { Uint32 all; struct MCDCR_BITS bit; }; struct X1CNT_BITS { // bits description Uint16 X1CNT:10; // 9:0 X1 Counter Uint16 rsvd1:6; // 15:10 Reserved Uint16 CLR:1; // 16 X1 Counter Clear Uint16 rsvd2:15; // 31:17 Reserved }; union X1CNT_REG { Uint32 all; struct X1CNT_BITS bit; }; struct XTALCR_BITS { // bits description Uint16 OSCOFF:1; // 0 XTAL Oscillator powered-down Uint16 SE:1; // 1 XTAL Oscilator in Single-Ended mode Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:13; // 15:3 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union XTALCR_REG { Uint32 all; struct XTALCR_BITS bit; }; struct ETHERCATCLKCTL_BITS { // bits description Uint16 DIVSRCSEL:1; // 0 Clock source select for the etherCAT clock divider. Uint16 ECATDIV:3; // 3:1 etherCAT clock divider configuration. Uint16 rsvd1:4; // 7:4 Reserved Uint16 PHYCLKEN:1; // 8 etherCAT PHY clock enable Uint16 rsvd2:7; // 15:9 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union ETHERCATCLKCTL_REG { Uint32 all; struct ETHERCATCLKCTL_BITS bit; }; struct CMCLKCTL_BITS { // bits description Uint16 CMDIVSRCSEL:1; // 0 Clock source select for the CM clock divider. Uint16 CMCLKDIV:3; // 3:1 CM clock divider configuration. Uint16 ETHDIVSRCSEL:1; // 4 Clock source select for the etherNET clock divider. Uint16 ETHDIV:3; // 7:5 Ethernet clock divider configuration Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMCLKCTL_REG { Uint32 all; struct CMCLKCTL_BITS bit; }; struct CLK_CFG_REGS { union CLKSEM_REG CLKSEM; // Clock Control Semaphore Register union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers Uint16 rsvd1[4]; // Reserved union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 Uint16 rsvd2[4]; // Reserved union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register union AUXPLLCTL1_REG AUXPLLCTL1; // AUXPLL Control register-1 Uint16 rsvd3[4]; // Reserved union AUXPLLMULT_REG AUXPLLMULT; // AUXPLL Multiplier register union AUXPLLSTS_REG AUXPLLSTS; // AUXPLL Status register union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register union AUXCLKDIVSEL_REG AUXCLKDIVSEL; // Auxillary Clock Divider Select register union PERCLKDIVSEL_REG PERCLKDIVSEL; // Peripheral Clock Divider Selet register union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register union CLBCLKCTL_REG CLBCLKCTL; // CLB Clocking Control Register union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar union MCDCR_REG MCDCR; // Missing Clock Detect Control Register union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock union XTALCR_REG XTALCR; // XTAL Control Register Uint16 rsvd4[2]; // Reserved union ETHERCATCLKCTL_REG ETHERCATCLKCTL; // ETHERCATCLKCTL union CMCLKCTL_REG CMCLKCTL; // CMCLKCTL }; struct CPUSYSLOCK1_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register Uint16 PCLKCR1:1; // 4 Lock bit for PCLKCR1 Register Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register Uint16 rsvd3:1; // 8 Reserved Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register Uint16 PCLKCR11:1; // 14 Lock bit for PCLKCR11 Register Uint16 rsvd4:1; // 15 Reserved Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register Uint16 rsvd5:1; // 18 Reserved Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register Uint16 rsvd6:1; // 20 Reserved Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register Uint16 PCLKCR17:1; // 24 Lock bit for PCLKCR17 Register Uint16 PCLKCR18:1; // 25 Lock bit for PCLKCR18 Register Uint16 rsvd7:1; // 26 Reserved Uint16 PCLKCR20:1; // 27 Lock bit for PCLKCR20 Register Uint16 PCLKCR21:1; // 28 Lock bit for PCLKCR21 Register Uint16 PCLKCR22:1; // 29 Lock bit for PCLKCR22 Register Uint16 PCLKCR23:1; // 30 Lock bit for PCLKCR23 Register Uint16 rsvd8:1; // 31 Reserved }; union CPUSYSLOCK1_REG { Uint32 all; struct CPUSYSLOCK1_BITS bit; }; struct CPUSYSLOCK2_BITS { // bits description Uint16 ETHERCATCTL:1; // 0 Lock bit for ETHERCATCTL register Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSYSLOCK2_REG { Uint32 all; struct CPUSYSLOCK2_BITS bit; }; struct PIEVERRADDR_BITS { // bits description Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address Uint16 rsvd1:10; // 31:22 Reserved }; union PIEVERRADDR_REG { Uint32 all; struct PIEVERRADDR_BITS bit; }; struct ETHERCATCTL_BITS { // bits description Uint16 I2CLOOPBACK:1; // 0 Loopback I2C port of etherCAT IP to I2C_A. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ETHERCATCTL_REG { Uint32 all; struct ETHERCATCTL_BITS bit; }; struct PCLKCR0_BITS { // bits description Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit Uint16 rsvd1:1; // 1 Reserved Uint16 DMA:1; // 2 DMA Clock Enable bit Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit Uint16 rsvd2:7; // 12:6 Reserved Uint16 CPUBGCRC:1; // 13 CPUBGCRC Clock Enable Bit Uint16 CLA1BGCRC:1; // 14 CLA1BGCRC Clock Enable Bit Uint16 rsvd3:1; // 15 Reserved Uint16 HRCAL:1; // 16 HRCAL Clock Enable Bit Uint16 rsvd4:1; // 17 Reserved Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync Uint16 GTBCLKSYNC:1; // 19 EPWM Time Base Clock Global sync Uint16 rsvd5:4; // 23:20 Reserved Uint16 ERAD:1; // 24 ERAD module clock enable Uint16 rsvd6:7; // 31:25 Reserved }; union PCLKCR0_REG { Uint32 all; struct PCLKCR0_BITS bit; }; struct PCLKCR1_BITS { // bits description Uint16 EMIF1:1; // 0 EMIF1 Clock Enable bit Uint16 EMIF2:1; // 1 EMIF2 Clock Enable bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR1_REG { Uint32 all; struct PCLKCR1_BITS bit; }; struct PCLKCR2_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit Uint16 EPWM9:1; // 8 EPWM9 Clock Enable bit Uint16 EPWM10:1; // 9 EPWM10 Clock Enable bit Uint16 EPWM11:1; // 10 EPWM11 Clock Enable bit Uint16 EPWM12:1; // 11 EPWM12 Clock Enable bit Uint16 EPWM13:1; // 12 EPWM13 Clock Enable bit Uint16 EPWM14:1; // 13 EPWM14 Clock Enable bit Uint16 EPWM15:1; // 14 EPWM15 Clock Enable bit Uint16 EPWM16:1; // 15 EPWM16 Clock Enable bit Uint16 rsvd1:16; // 31:16 Reserved }; union PCLKCR2_REG { Uint32 all; struct PCLKCR2_BITS bit; }; struct PCLKCR3_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit Uint16 ECAP7:1; // 6 ECAP7 Clock Enable bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR3_REG { Uint32 all; struct PCLKCR3_BITS bit; }; struct PCLKCR4_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit Uint16 EQEP3:1; // 2 EQEP3 Clock Enable bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR4_REG { Uint32 all; struct PCLKCR4_BITS bit; }; struct PCLKCR6_BITS { // bits description Uint16 SD1:1; // 0 SD1 Clock Enable bit Uint16 SD2:1; // 1 SD2 Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union PCLKCR6_REG { Uint32 all; struct PCLKCR6_BITS bit; }; struct PCLKCR7_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit Uint16 SCI_C:1; // 2 SCI_C Clock Enable bit Uint16 SCI_D:1; // 3 SCI_D Clock Enable bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR7_REG { Uint32 all; struct PCLKCR7_BITS bit; }; struct PCLKCR8_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit Uint16 SPI_C:1; // 2 SPI_C Clock Enable bit Uint16 SPI_D:1; // 3 SPI_D Clock Enable bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:1; // 16 Reserved Uint16 rsvd3:1; // 17 Reserved Uint16 rsvd4:14; // 31:18 Reserved }; union PCLKCR8_REG { Uint32 all; struct PCLKCR8_BITS bit; }; struct PCLKCR9_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit Uint16 I2C_B:1; // 1 I2C_B Clock Enable bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR9_REG { Uint32 all; struct PCLKCR9_BITS bit; }; struct PCLKCR10_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union PCLKCR10_REG { Uint32 all; struct PCLKCR10_BITS bit; }; struct PCLKCR11_BITS { // bits description Uint16 McBSP_A:1; // 0 McBSP_A Clock Enable bit Uint16 McBSP_B:1; // 1 McBSP_B Clock Enable bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 USB_A:1; // 16 USB_A Clock Enable bit Uint16 rsvd2:1; // 17 Reserved Uint16 rsvd3:14; // 31:18 Reserved }; union PCLKCR11_REG { Uint32 all; struct PCLKCR11_BITS bit; }; struct PCLKCR13_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit Uint16 ADC_D:1; // 3 ADC_D Clock Enable bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR13_REG { Uint32 all; struct PCLKCR13_BITS bit; }; struct PCLKCR14_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit Uint16 CMPSS8:1; // 7 CMPSS8 Clock Enable bit Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR14_REG { Uint32 all; struct PCLKCR14_BITS bit; }; struct PCLKCR16_BITS { // bits description Uint16 rsvd1:16; // 15:0 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC12_1 Clock Enable Bit Uint16 DAC_B:1; // 17 Buffered_DAC12_2 Clock Enable Bit Uint16 DAC_C:1; // 18 Buffered_DAC12_3 Clock Enable Bit Uint16 rsvd2:1; // 19 Reserved Uint16 rsvd3:12; // 31:20 Reserved }; union PCLKCR16_REG { Uint32 all; struct PCLKCR16_BITS bit; }; struct PCLKCR17_BITS { // bits description Uint16 CLB1:1; // 0 CLB1 Clock Enable bit Uint16 CLB2:1; // 1 CLB2 Clock Enable bit Uint16 CLB3:1; // 2 CLB3 Clock Enable bit Uint16 CLB4:1; // 3 CLB4 Clock Enable bit Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:8; // 15:8 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union PCLKCR17_REG { Uint32 all; struct PCLKCR17_BITS bit; }; struct PCLKCR18_BITS { // bits description Uint16 FSITX_A:1; // 0 FSITX_A Clock Enable bit Uint16 FSITX_B:1; // 1 FSITX_B Clock Enable bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 FSIRX_A:1; // 16 FSIRX_A Clock Enable bit Uint16 FSIRX_B:1; // 17 FSIRX_B Clock Enable bit Uint16 FSIRX_C:1; // 18 FSIRX_C Clock Enable bit Uint16 FSIRX_D:1; // 19 FSIRX_D Clock Enable bit Uint16 FSIRX_E:1; // 20 FSIRX_E Clock Enable bit Uint16 FSIRX_F:1; // 21 FSIRX_F Clock Enable bit Uint16 FSIRX_G:1; // 22 FSIRX_G Clock Enable bit Uint16 FSIRX_H:1; // 23 FSIRX_H Clock Enable bit Uint16 rsvd8:8; // 31:24 Reserved }; union PCLKCR18_REG { Uint32 all; struct PCLKCR18_BITS bit; }; struct PCLKCR20_BITS { // bits description Uint16 PMBUS_A:1; // 0 PMBUS_A Clock Enable bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PCLKCR20_REG { Uint32 all; struct PCLKCR20_BITS bit; }; struct PCLKCR21_BITS { // bits description Uint16 DCC0:1; // 0 DCC0 Clock Enable Bit Uint16 DCC1:1; // 1 DCC1 Clock Enable Bit Uint16 DCC2:1; // 2 DCC2 Clock Enable Bit Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR21_REG { Uint32 all; struct PCLKCR21_BITS bit; }; struct PCLKCR22_BITS { // bits description Uint16 PBISTCLK:1; // 0 PBISTCLK Clock Enable Bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR22_REG { Uint32 all; struct PCLKCR22_BITS bit; }; struct PCLKCR23_BITS { // bits description Uint16 ETHERCAT:1; // 0 ETHERCAT Clock Enable Bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PCLKCR23_REG { Uint32 all; struct PCLKCR23_BITS bit; }; struct SIMRESET_BITS { // bits description Uint16 CPU1RSn:1; // 0 Generates a reset to CPU Uint16 XRSn:1; // 1 Generates a simulated XRSn Uint16 rsvd1:14; // 15:2 Reserved Uint16 KEY:16; // 31:16 Key value }; union SIMRESET_REG { Uint32 all; struct SIMRESET_BITS bit; }; struct LPMCR_BITS { // bits description Uint16 LPM:2; // 1:0 Low Power Mode setting Uint16 QUALSTDBY:6; // 7:2 STANDBY Wakeup Pin Qualification Setting Uint16 rsvd1:7; // 14:8 Reserved Uint16 WDINTE:1; // 15 Enable for WDINT wakeup from STANDBY Uint16 rsvd2:2; // 17:16 Reserved Uint16 rsvd3:13; // 30:18 Reserved Uint16 rsvd4:1; // 31 Reserved }; union LPMCR_REG { Uint32 all; struct LPMCR_BITS bit; }; struct GPIOLPMSEL0_BITS { // bits description Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup }; union GPIOLPMSEL0_REG { Uint32 all; struct GPIOLPMSEL0_BITS bit; }; struct GPIOLPMSEL1_BITS { // bits description Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup }; union GPIOLPMSEL1_REG { Uint32 all; struct GPIOLPMSEL1_BITS bit; }; struct TMR2CLKCTL_BITS { // bits description Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union TMR2CLKCTL_REG { Uint32 all; struct TMR2CLKCTL_BITS bit; }; struct RESCCLR_BITS { // bits description Uint16 POR:1; // 0 POR Reset Cause Indication Bit Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit Uint16 rsvd1:1; // 4 Reserved Uint16 HWBISTn:1; // 5 HWBISTn Reset Cause Indication Bit Uint16 rsvd2:1; // 6 Reserved Uint16 rsvd3:1; // 7 Reserved Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit Uint16 ECAT_RESET_OUT:1; // 9 ECAT_RESET_OUT Reset Cause Indication Bit Uint16 SIMRESET_CPU1RSn:1; // 10 SIMRESET_CPU1RSn Reset Cause Indication Bit Uint16 SIMRESET_XRSn:1; // 11 SIMRESET_XRSn Reset Cause Indication Bit Uint16 rsvd4:4; // 15:12 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union RESCCLR_REG { Uint32 all; struct RESCCLR_BITS bit; }; struct RESC_BITS { // bits description Uint16 POR:1; // 0 POR Reset Cause Indication Bit Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit Uint16 rsvd1:1; // 4 Reserved Uint16 HWBISTn:1; // 5 HWBISTn Reset Cause Indication Bit Uint16 rsvd2:1; // 6 Reserved Uint16 rsvd3:1; // 7 Reserved Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit Uint16 ECAT_RESET_OUT:1; // 9 ECAT_RESET_OUT Reset Cause Indication Bit Uint16 SIMRESET_CPU1RSn:1; // 10 SIMRESET_CPU1RSn Reset Cause Indication Bit Uint16 SIMRESET_XRSn:1; // 11 SIMRESET_XRSn Reset Cause Indication Bit Uint16 rsvd4:4; // 15:12 Reserved Uint16 rsvd5:14; // 29:16 Reserved Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status Uint16 TRSTn_pin_status:1; // 31 TRSTn Status }; union RESC_REG { Uint32 all; struct RESC_BITS bit; }; struct CPU_SYS_REGS { union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers union CPUSYSLOCK2_REG CPUSYSLOCK2; // Lock bit for CPUSYS registers Uint16 rsvd1[6]; // Reserved union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register union ETHERCATCTL_REG ETHERCATCTL; // ETHERCAT control register. Uint16 rsvd2[20]; // Reserved union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers union PCLKCR1_REG PCLKCR1; // Peripheral Clock Gating Registers union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers Uint16 rsvd3[2]; // Reserved union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers union PCLKCR11_REG PCLKCR11; // Peripheral Clock Gating Registers Uint16 rsvd4[2]; // Reserved union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers Uint16 rsvd5[2]; // Reserved union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers union PCLKCR17_REG PCLKCR17; // Peripheral Clock Gating Registers union PCLKCR18_REG PCLKCR18; // Peripheral Clock Gating Registers Uint16 rsvd6[2]; // Reserved union PCLKCR20_REG PCLKCR20; // Peripheral Clock Gating Registers union PCLKCR21_REG PCLKCR21; // Peripheral Clock Gating Registers union PCLKCR22_REG PCLKCR22; // Peripheral Clock Gating Registers union PCLKCR23_REG PCLKCR23; // Peripheral Clock Gating Registers Uint16 rsvd7[30]; // Reserved union SIMRESET_REG SIMRESET; // Simulated Reset Register Uint16 rsvd8[4]; // Reserved union LPMCR_REG LPMCR; // LPM Control Register union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register union RESCCLR_REG RESCCLR; // Reset Cause Clear Register union RESC_REG RESC; // Reset Cause register }; struct CLA1TASKSRCSELLOCK_BITS { // bits description Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CLA1TASKSRCSELLOCK_REG { Uint32 all; struct CLA1TASKSRCSELLOCK_BITS bit; }; struct DMACHSRCSELLOCK_BITS { // bits description Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DMACHSRCSELLOCK_REG { Uint32 all; struct DMACHSRCSELLOCK_BITS bit; }; struct CLA1TASKSRCSEL1_BITS { // bits description Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 }; union CLA1TASKSRCSEL1_REG { Uint32 all; struct CLA1TASKSRCSEL1_BITS bit; }; struct CLA1TASKSRCSEL2_BITS { // bits description Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 }; union CLA1TASKSRCSEL2_REG { Uint32 all; struct CLA1TASKSRCSEL2_BITS bit; }; struct DMACHSRCSEL1_BITS { // bits description Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA }; union DMACHSRCSEL1_REG { Uint32 all; struct DMACHSRCSEL1_BITS bit; }; struct DMACHSRCSEL2_BITS { // bits description Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA Uint16 rsvd1:16; // 31:16 Reserved }; union DMACHSRCSEL2_REG { Uint32 all; struct DMACHSRCSEL2_BITS bit; }; struct DMA_CLA_SRC_SEL_REGS { union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register Uint16 rsvd1[2]; // Reserved union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 Uint16 rsvd2[12]; // Reserved union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 }; struct DEVCFGLOCK1_BITS { // bits description Uint16 CPUSEL0:1; // 0 Lock bit for CPUSEL0 register Uint16 CPUSEL1:1; // 1 Lock bit for CPUSEL1 register Uint16 CPUSEL2:1; // 2 Lock bit for CPUSEL2 register Uint16 rsvd1:1; // 3 Reserved Uint16 CPUSEL4:1; // 4 Lock bit for CPUSEL4 register Uint16 CPUSEL5:1; // 5 Lock bit for CPUSEL5 register Uint16 CPUSEL6:1; // 6 Lock bit for CPUSEL6 register Uint16 CPUSEL7:1; // 7 Lock bit for CPUSEL7 register Uint16 CPUSEL8:1; // 8 Lock bit for CPUSEL8 register Uint16 CPUSEL9:1; // 9 Lock bit for CPUSEL9 register Uint16 rsvd2:1; // 10 Reserved Uint16 CPUSEL11:1; // 11 Lock bit for CPUSEL11 register Uint16 CPUSEL12:1; // 12 Lock bit for CPUSEL12 register Uint16 rsvd3:1; // 13 Reserved Uint16 CPUSEL14:1; // 14 Lock bit for CPUSEL14 register Uint16 CPUSEL15:1; // 15 Lock bit for CPUSEL15 register Uint16 CPUSEL16:1; // 16 Lock bit for CPUSEL16 register Uint16 rsvd4:1; // 17 Reserved Uint16 CPUSEL18:1; // 18 Lock bit for CPUSEL18 register Uint16 rsvd5:6; // 24:19 Reserved Uint16 CPUSEL25:1; // 25 Lock bit for CPUSEL25 register Uint16 rsvd6:6; // 31:26 Reserved }; union DEVCFGLOCK1_REG { Uint32 all; struct DEVCFGLOCK1_BITS bit; }; struct PARTIDL_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 rsvd2:2; // 4:3 Reserved Uint16 rsvd3:1; // 5 Reserved Uint16 QUAL:2; // 7:6 Qualification Status Uint16 PIN_COUNT:3; // 10:8 Device Pin Count Uint16 rsvd4:1; // 11 Reserved Uint16 rsvd5:1; // 12 Reserved Uint16 INSTASPIN:2; // 14:13 Motorware feature set Uint16 rsvd6:1; // 15 Reserved Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB Uint16 rsvd7:4; // 27:24 Reserved Uint16 PARTID_FORMAT_REVISION:4; // 31:28 Revision of the PARTID format }; union PARTIDL_REG { Uint32 all; struct PARTIDL_BITS bit; }; struct PARTIDH_BITS { // bits description Uint16 rsvd1:4; // 3:0 Reserved Uint16 rsvd2:4; // 7:4 Reserved Uint16 FAMILY:8; // 15:8 Device family Uint16 PARTNO:8; // 23:16 Device part number Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID }; union PARTIDH_REG { Uint32 all; struct PARTIDH_BITS bit; }; struct REVID_BITS { // bits description Uint16 REVID:16; // 15:0 Device Revision ID. This is specific to the Device Uint16 rsvd1:16; // 31:16 Reserved }; union REVID_REG { Uint32 all; struct REVID_BITS bit; }; struct PERCNF1_BITS { // bits description Uint16 ADC_A_MODE:1; // 0 ADC Wrapper-1 mode setting bit Uint16 ADC_B_MODE:1; // 1 ADC Wrapper-2 mode setting bit Uint16 ADC_C_MODE:1; // 2 ADC Wrapper-3 mode setting bit Uint16 ADC_D_MODE:1; // 3 ADC Wrapper-4 mode setting bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 USB_A_PHY:1; // 16 USB_A_PHY enable/disable bit Uint16 rsvd2:1; // 17 Reserved Uint16 rsvd3:14; // 31:18 Reserved }; union PERCNF1_REG { Uint32 all; struct PERCNF1_BITS bit; }; struct FUSEERR_BITS { // bits description Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status Uint16 ERR:1; // 5 Efuse Self Test Error Status Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FUSEERR_REG { Uint32 all; struct FUSEERR_BITS bit; }; struct SOFTPRES0_BITS { // bits description Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 CPU2_CLA1:1; // 2 CPU2_CLA1 software reset bit Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:9; // 12:4 Reserved Uint16 CPU1_CPUBGCRC:1; // 13 CPUBGCRC Module reset bit Uint16 CPU1_CLA1BGCRC:1; // 14 CLA1BGCRC Module reset bit Uint16 rsvd4:1; // 15 Reserved Uint16 CPU2_CPUBGCRC:1; // 16 CPUBGCRC Module reset bit Uint16 CPU2_CLA1BGCRC:1; // 17 CLA1BGCRC Module reset bit Uint16 rsvd5:1; // 18 Reserved Uint16 rsvd6:5; // 23:19 Reserved Uint16 CPU1_ERAD:1; // 24 ERAD Module reset bit Uint16 CPU2_ERAD:1; // 25 ERAD Module reset bit Uint16 rsvd7:6; // 31:26 Reserved }; union SOFTPRES0_REG { Uint32 all; struct SOFTPRES0_BITS bit; }; struct SOFTPRES1_BITS { // bits description Uint16 EMIF1:1; // 0 EMIF1 software reset bit Uint16 EMIF2:1; // 1 EMIF2 software reset bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES1_REG { Uint32 all; struct SOFTPRES1_BITS bit; }; struct SOFTPRES2_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 software reset bit Uint16 EPWM2:1; // 1 EPWM2 software reset bit Uint16 EPWM3:1; // 2 EPWM3 software reset bit Uint16 EPWM4:1; // 3 EPWM4 software reset bit Uint16 EPWM5:1; // 4 EPWM5 software reset bit Uint16 EPWM6:1; // 5 EPWM6 software reset bit Uint16 EPWM7:1; // 6 EPWM7 software reset bit Uint16 EPWM8:1; // 7 EPWM8 software reset bit Uint16 EPWM9:1; // 8 EPWM9 software reset bit Uint16 EPWM10:1; // 9 EPWM10 software reset bit Uint16 EPWM11:1; // 10 EPWM11 software reset bit Uint16 EPWM12:1; // 11 EPWM12 software reset bit Uint16 EPWM13:1; // 12 EPWM13 software reset bit Uint16 EPWM14:1; // 13 EPWM14 software reset bit Uint16 EPWM15:1; // 14 EPWM15 software reset bit Uint16 EPWM16:1; // 15 EPWM16 software reset bit Uint16 rsvd1:16; // 31:16 Reserved }; union SOFTPRES2_REG { Uint32 all; struct SOFTPRES2_BITS bit; }; struct SOFTPRES3_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 software reset bit Uint16 ECAP2:1; // 1 ECAP2 software reset bit Uint16 ECAP3:1; // 2 ECAP3 software reset bit Uint16 ECAP4:1; // 3 ECAP4 software reset bit Uint16 ECAP5:1; // 4 ECAP5 software reset bit Uint16 ECAP6:1; // 5 ECAP6 software reset bit Uint16 ECAP7:1; // 6 ECAP7 software reset bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES3_REG { Uint32 all; struct SOFTPRES3_BITS bit; }; struct SOFTPRES4_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 software reset bit Uint16 EQEP2:1; // 1 EQEP2 software reset bit Uint16 EQEP3:1; // 2 EQEP3 software reset bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES4_REG { Uint32 all; struct SOFTPRES4_BITS bit; }; struct SOFTPRES6_BITS { // bits description Uint16 SD1:1; // 0 SD1 software reset bit Uint16 SD2:1; // 1 SD2 software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union SOFTPRES6_REG { Uint32 all; struct SOFTPRES6_BITS bit; }; struct SOFTPRES7_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A software reset bit Uint16 SCI_B:1; // 1 SCI_B software reset bit Uint16 SCI_C:1; // 2 SCI_C software reset bit Uint16 SCI_D:1; // 3 SCI_D software reset bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES7_REG { Uint32 all; struct SOFTPRES7_BITS bit; }; struct SOFTPRES8_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A software reset bit Uint16 SPI_B:1; // 1 SPI_B software reset bit Uint16 SPI_C:1; // 2 SPI_C software reset bit Uint16 SPI_D:1; // 3 SPI_D software reset bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:1; // 16 Reserved Uint16 rsvd3:1; // 17 Reserved Uint16 rsvd4:14; // 31:18 Reserved }; union SOFTPRES8_REG { Uint32 all; struct SOFTPRES8_BITS bit; }; struct SOFTPRES9_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A software reset bit Uint16 I2C_B:1; // 1 I2C_B software reset bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES9_REG { Uint32 all; struct SOFTPRES9_BITS bit; }; struct SOFTPRES10_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A software reset bit Uint16 CAN_B:1; // 1 CAN_B software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union SOFTPRES10_REG { Uint32 all; struct SOFTPRES10_BITS bit; }; struct SOFTPRES11_BITS { // bits description Uint16 McBSP_A:1; // 0 McBSP_A software reset bit Uint16 McBSP_B:1; // 1 McBSP_B software reset bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 USB_A:1; // 16 USB_A software reset bit Uint16 rsvd2:1; // 17 Reserved Uint16 rsvd3:14; // 31:18 Reserved }; union SOFTPRES11_REG { Uint32 all; struct SOFTPRES11_BITS bit; }; struct SOFTPRES13_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A software reset bit Uint16 ADC_B:1; // 1 ADC_B software reset bit Uint16 ADC_C:1; // 2 ADC_C software reset bit Uint16 ADC_D:1; // 3 ADC_D software reset bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES13_REG { Uint32 all; struct SOFTPRES13_BITS bit; }; struct SOFTPRES14_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit Uint16 CMPSS8:1; // 7 CMPSS8 software reset bit Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES14_REG { Uint32 all; struct SOFTPRES14_BITS bit; }; struct SOFTPRES16_BITS { // bits description Uint16 rsvd1:16; // 15:0 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC12_1 software reset bit Uint16 DAC_B:1; // 17 Buffered_DAC12_2 software reset bit Uint16 DAC_C:1; // 18 Buffered_DAC12_3 software reset bit Uint16 rsvd2:1; // 19 Reserved Uint16 rsvd3:12; // 31:20 Reserved }; union SOFTPRES16_REG { Uint32 all; struct SOFTPRES16_BITS bit; }; struct SOFTPRES17_BITS { // bits description Uint16 CLB1:1; // 0 CLB1 software reset bit Uint16 CLB2:1; // 1 CLB2 software reset bit Uint16 CLB3:1; // 2 CLB3 software reset bit Uint16 CLB4:1; // 3 CLB4 software reset bit Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:8; // 15:8 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union SOFTPRES17_REG { Uint32 all; struct SOFTPRES17_BITS bit; }; struct SOFTPRES18_BITS { // bits description Uint16 FSITX_A:1; // 0 FSITX_A software reset bit Uint16 FSITX_B:1; // 1 FSITX_B software reset bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 FSIRX_A:1; // 16 FSIRX_A software reset bit Uint16 FSIRX_B:1; // 17 FSIRX_B software reset bit Uint16 FSIRX_C:1; // 18 FSIRX_C software reset bit Uint16 FSIRX_D:1; // 19 FSIRX_D software reset bit Uint16 FSIRX_E:1; // 20 FSIRX_E software reset bit Uint16 FSIRX_F:1; // 21 FSIRX_F software reset bit Uint16 FSIRX_G:1; // 22 FSIRX_G software reset bit Uint16 FSIRX_H:1; // 23 FSIRX_H software reset bit Uint16 rsvd8:8; // 31:24 Reserved }; union SOFTPRES18_REG { Uint32 all; struct SOFTPRES18_BITS bit; }; struct SOFTPRES20_BITS { // bits description Uint16 PMBUS_A:1; // 0 PMBUS_A software reset bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union SOFTPRES20_REG { Uint32 all; struct SOFTPRES20_BITS bit; }; struct SOFTPRES21_BITS { // bits description Uint16 DCC0:1; // 0 DCC0 Module reset bit Uint16 DCC1:1; // 1 DCC1 Module reset bit Uint16 DCC2:1; // 2 DCC2 Module reset bit Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES21_REG { Uint32 all; struct SOFTPRES21_BITS bit; }; struct SOFTPRES23_BITS { // bits description Uint16 ETHERCAT:1; // 0 ETHERCAT Module reset bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SOFTPRES23_REG { Uint32 all; struct SOFTPRES23_BITS bit; }; struct CPUSEL0_BITS { // bits description Uint16 EPWM1:1; // 0 EPWM1 CPU select bit Uint16 EPWM2:1; // 1 EPWM2 CPU select bit Uint16 EPWM3:1; // 2 EPWM3 CPU select bit Uint16 EPWM4:1; // 3 EPWM4 CPU select bit Uint16 EPWM5:1; // 4 EPWM5 CPU select bit Uint16 EPWM6:1; // 5 EPWM6 CPU select bit Uint16 EPWM7:1; // 6 EPWM7 CPU select bit Uint16 EPWM8:1; // 7 EPWM8 CPU select bit Uint16 EPWM9:1; // 8 EPWM9 CPU select bit Uint16 EPWM10:1; // 9 EPWM10 CPU select bit Uint16 EPWM11:1; // 10 EPWM11 CPU select bit Uint16 EPWM12:1; // 11 EPWM12 CPU select bit Uint16 EPWM13:1; // 12 EPWM13 CPU select bit Uint16 EPWM14:1; // 13 EPWM14 CPU select bit Uint16 EPWM15:1; // 14 EPWM15 CPU select bit Uint16 EPWM16:1; // 15 EPWM16 CPU select bit Uint16 rsvd1:16; // 31:16 Reserved }; union CPUSEL0_REG { Uint32 all; struct CPUSEL0_BITS bit; }; struct CPUSEL1_BITS { // bits description Uint16 ECAP1:1; // 0 ECAP1 CPU select bit Uint16 ECAP2:1; // 1 ECAP2 CPU select bit Uint16 ECAP3:1; // 2 ECAP3 CPU select bit Uint16 ECAP4:1; // 3 ECAP4 CPU select bit Uint16 ECAP5:1; // 4 ECAP5 CPU select bit Uint16 ECAP6:1; // 5 ECAP6 CPU select bit Uint16 ECAP7:1; // 6 ECAP7 CPU select bit Uint16 rsvd1:1; // 7 Reserved Uint16 rsvd2:8; // 15:8 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CPUSEL1_REG { Uint32 all; struct CPUSEL1_BITS bit; }; struct CPUSEL2_BITS { // bits description Uint16 EQEP1:1; // 0 EQEP1 CPU select bit Uint16 EQEP2:1; // 1 EQEP2 CPU select bit Uint16 EQEP3:1; // 2 EQEP3 CPU select bit Uint16 rsvd1:1; // 3 Reserved Uint16 rsvd2:12; // 15:4 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CPUSEL2_REG { Uint32 all; struct CPUSEL2_BITS bit; }; struct CPUSEL4_BITS { // bits description Uint16 SD1:1; // 0 SD1 CPU select bit Uint16 SD2:1; // 1 SD2 CPU select bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 rsvd8:16; // 31:16 Reserved }; union CPUSEL4_REG { Uint32 all; struct CPUSEL4_BITS bit; }; struct CPUSEL5_BITS { // bits description Uint16 SCI_A:1; // 0 SCI_A CPU select bit Uint16 SCI_B:1; // 1 SCI_B CPU select bit Uint16 SCI_C:1; // 2 SCI_C CPU select bit Uint16 SCI_D:1; // 3 SCI_D CPU select bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL5_REG { Uint32 all; struct CPUSEL5_BITS bit; }; struct CPUSEL6_BITS { // bits description Uint16 SPI_A:1; // 0 SPI_A CPU select bit Uint16 SPI_B:1; // 1 SPI_B CPU select bit Uint16 SPI_C:1; // 2 SPI_C CPU select bit Uint16 SPI_D:1; // 3 SPI_D CPU select bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:1; // 16 Reserved Uint16 rsvd3:1; // 17 Reserved Uint16 rsvd4:14; // 31:18 Reserved }; union CPUSEL6_REG { Uint32 all; struct CPUSEL6_BITS bit; }; struct CPUSEL7_BITS { // bits description Uint16 I2C_A:1; // 0 I2C_A CPU select bit Uint16 I2C_B:1; // 1 I2C_B CPU select bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL7_REG { Uint32 all; struct CPUSEL7_BITS bit; }; struct CPUSEL8_BITS { // bits description Uint16 CAN_A:1; // 0 CAN_A CPU select bit Uint16 CAN_B:1; // 1 CAN_B CPU select bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:11; // 15:5 Reserved Uint16 rsvd5:16; // 31:16 Reserved }; union CPUSEL8_REG { Uint32 all; struct CPUSEL8_BITS bit; }; struct CPUSEL9_BITS { // bits description Uint16 McBSP_A:1; // 0 McBSP_A CPU select bit Uint16 McBSP_B:1; // 1 McBSP_B CPU select bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL9_REG { Uint32 all; struct CPUSEL9_BITS bit; }; struct CPUSEL11_BITS { // bits description Uint16 ADC_A:1; // 0 ADC_A CPU select bit Uint16 ADC_B:1; // 1 ADC_B CPU select bit Uint16 ADC_C:1; // 2 ADC_C CPU select bit Uint16 ADC_D:1; // 3 ADC_D CPU select bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL11_REG { Uint32 all; struct CPUSEL11_BITS bit; }; struct CPUSEL12_BITS { // bits description Uint16 CMPSS1:1; // 0 CMPSS1 CPU select bit Uint16 CMPSS2:1; // 1 CMPSS2 CPU select bit Uint16 CMPSS3:1; // 2 CMPSS3 CPU select bit Uint16 CMPSS4:1; // 3 CMPSS4 CPU select bit Uint16 CMPSS5:1; // 4 CMPSS5 CPU select bit Uint16 CMPSS6:1; // 5 CMPSS6 CPU select bit Uint16 CMPSS7:1; // 6 CMPSS7 CPU select bit Uint16 CMPSS8:1; // 7 CMPSS8 CPU select bit Uint16 rsvd1:8; // 15:8 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL12_REG { Uint32 all; struct CPUSEL12_BITS bit; }; struct CPUSEL14_BITS { // bits description Uint16 rsvd1:16; // 15:0 Reserved Uint16 DAC_A:1; // 16 Buffered_DAC12_1 CPU select bit Uint16 DAC_B:1; // 17 Buffered_DAC12_2 CPU select bit Uint16 DAC_C:1; // 18 Buffered_DAC12_3 CPU select bit Uint16 rsvd2:1; // 19 Reserved Uint16 rsvd3:12; // 31:20 Reserved }; union CPUSEL14_REG { Uint32 all; struct CPUSEL14_BITS bit; }; struct CPUSEL15_BITS { // bits description Uint16 CLB1:1; // 0 CLB1 CPU select bit Uint16 CLB2:1; // 1 CLB2 CPU select bit Uint16 CLB3:1; // 2 CLB3 CPU select bit Uint16 CLB4:1; // 3 CLB4 CPU select bit Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:1; // 5 Reserved Uint16 rsvd3:1; // 6 Reserved Uint16 rsvd4:1; // 7 Reserved Uint16 rsvd5:8; // 15:8 Reserved Uint16 rsvd6:16; // 31:16 Reserved }; union CPUSEL15_REG { Uint32 all; struct CPUSEL15_BITS bit; }; struct CPUSEL16_BITS { // bits description Uint16 FSITX_A:1; // 0 FSITX_A CPU select bit Uint16 FSITX_B:1; // 1 FSITX_B CPU select bit Uint16 rsvd1:1; // 2 Reserved Uint16 rsvd2:1; // 3 Reserved Uint16 rsvd3:1; // 4 Reserved Uint16 rsvd4:1; // 5 Reserved Uint16 rsvd5:1; // 6 Reserved Uint16 rsvd6:1; // 7 Reserved Uint16 rsvd7:8; // 15:8 Reserved Uint16 FSIRX_A:1; // 16 FSIRX_A CPU select bit Uint16 FSIRX_B:1; // 17 FSIRX_B CPU select bit Uint16 FSIRX_C:1; // 18 FSIRX_C CPU select bit Uint16 FSIRX_D:1; // 19 FSIRX_D CPU select bit Uint16 FSIRX_E:1; // 20 FSIRX_E CPU select bit Uint16 FSIRX_F:1; // 21 FSIRX_F CPU select bit Uint16 FSIRX_G:1; // 22 FSIRX_G CPU select bit Uint16 FSIRX_H:1; // 23 FSIRX_H CPU select bit Uint16 rsvd8:8; // 31:24 Reserved }; union CPUSEL16_REG { Uint32 all; struct CPUSEL16_BITS bit; }; struct CPUSEL18_BITS { // bits description Uint16 PMBUS_A:1; // 0 PMBUS_A CPU select bit Uint16 rsvd1:1; // 1 Reserved Uint16 rsvd2:14; // 15:2 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CPUSEL18_REG { Uint32 all; struct CPUSEL18_BITS bit; }; struct CPUSEL25_BITS { // bits description Uint16 HRCAL_A:1; // 0 HRCAL CPU select bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CPUSEL25_REG { Uint32 all; struct CPUSEL25_BITS bit; }; struct CPU2RESCTL_BITS { // bits description Uint16 RESET:1; // 0 CPU2 Reset Control bit Uint16 rsvd1:15; // 15:1 Reserved Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register }; union CPU2RESCTL_REG { Uint32 all; struct CPU2RESCTL_BITS bit; }; struct RSTSTAT_BITS { // bits description Uint16 CPU2RES:1; // 0 CPU2 Reset Status bit Uint16 CPU2NMIWDRST:1; // 1 Tells whether a CPU2.NMIWD reset was issued to CPU2 or not Uint16 CPU2HWBISTRST:2; // 3:2 Tells whether a HWBIST reset was issued to CPU2 or not Uint16 rsvd1:12; // 15:4 Reserved }; union RSTSTAT_REG { Uint16 all; struct RSTSTAT_BITS bit; }; struct LPMSTAT_BITS { // bits description Uint16 CPU2LPMSTAT:2; // 1:0 CPU2 LPM Status Uint16 rsvd1:14; // 15:2 Reserved }; union LPMSTAT_REG { Uint16 all; struct LPMSTAT_BITS bit; }; struct BANKSEL_BITS { // bits description Uint16 SEL:2; // 1:0 Selects the BANK to be programmed by CPU1 FMC. Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union BANKSEL_REG { Uint32 all; struct BANKSEL_BITS bit; }; struct USBTYPE_BITS { // bits description Uint16 TYPE:2; // 1:0 Configure USB type Uint16 rsvd1:13; // 14:2 Reserved Uint16 LOCK:1; // 15 Lock bit }; union USBTYPE_REG { Uint16 all; struct USBTYPE_BITS bit; }; struct ECAPTYPE_BITS { // bits description Uint16 TYPE:2; // 1:0 Configure ECAP type Uint16 rsvd1:13; // 14:2 Reserved Uint16 LOCK:1; // 15 Lock bit }; union ECAPTYPE_REG { Uint16 all; struct ECAPTYPE_BITS bit; }; struct SDFMTYPE_BITS { // bits description Uint16 TYPE:2; // 1:0 Configure SDFM type Uint16 rsvd1:13; // 14:2 Reserved Uint16 LOCK:1; // 15 Lock bit }; union SDFMTYPE_REG { Uint16 all; struct SDFMTYPE_BITS bit; }; struct MEMMAPTYPE_BITS { // bits description Uint16 TYPE:2; // 1:0 Configures system specific features related to memory map. Uint16 rsvd1:13; // 14:2 Reserved Uint16 LOCK:1; // 15 Lock bit }; union MEMMAPTYPE_REG { Uint16 all; struct MEMMAPTYPE_BITS bit; }; struct DEV_CFG_REGS { union DEVCFGLOCK1_REG DEVCFGLOCK1; // Lock bit for DEVCFG registers Uint16 rsvd1[6]; // Reserved union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number union REVID_REG REVID; // Device Revision Number Uint16 rsvd2[82]; // Reserved union PERCNF1_REG PERCNF1; // Peripheral Configuration register Uint16 rsvd3[18]; // Reserved union FUSEERR_REG FUSEERR; // e-Fuse error Status register Uint16 rsvd4[12]; // Reserved union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register union SOFTPRES1_REG SOFTPRES1; // EMIF Software Reset register union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register Uint16 rsvd5[2]; // Reserved union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register union SOFTPRES10_REG SOFTPRES10; // Peripheral Software Reset register union SOFTPRES11_REG SOFTPRES11; // Peripheral Software Reset register Uint16 rsvd6[2]; // Reserved union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register Uint16 rsvd7[2]; // Reserved union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register union SOFTPRES17_REG SOFTPRES17; // Reserved Peripheral Software Reset register union SOFTPRES18_REG SOFTPRES18; // Reserved Peripheral Software Reset register Uint16 rsvd8[2]; // Reserved union SOFTPRES20_REG SOFTPRES20; // Peripheral Software Reset register union SOFTPRES21_REG SOFTPRES21; // Peripheral Software Reset register Uint16 rsvd9[2]; // Reserved union SOFTPRES23_REG SOFTPRES23; // Peripheral Software Reset register Uint16 rsvd10[36]; // Reserved union CPUSEL0_REG CPUSEL0; // CPU Select register for common peripherals union CPUSEL1_REG CPUSEL1; // CPU Select register for common peripherals union CPUSEL2_REG CPUSEL2; // CPU Select register for common peripherals Uint16 rsvd11[2]; // Reserved union CPUSEL4_REG CPUSEL4; // CPU Select register for common peripherals union CPUSEL5_REG CPUSEL5; // CPU Select register for common peripherals union CPUSEL6_REG CPUSEL6; // CPU Select register for common peripherals union CPUSEL7_REG CPUSEL7; // CPU Select register for common peripherals union CPUSEL8_REG CPUSEL8; // CPU Select register for common peripherals union CPUSEL9_REG CPUSEL9; // CPU Select register for common peripherals Uint16 rsvd12[2]; // Reserved union CPUSEL11_REG CPUSEL11; // CPU Select register for common peripherals union CPUSEL12_REG CPUSEL12; // CPU Select register for common peripherals Uint16 rsvd13[2]; // Reserved union CPUSEL14_REG CPUSEL14; // CPU Select register for common peripherals union CPUSEL15_REG CPUSEL15; // CPU Select register for common peripherals union CPUSEL16_REG CPUSEL16; // CPU Select register for common peripherals Uint16 rsvd14[2]; // Reserved union CPUSEL18_REG CPUSEL18; // CPU Select register for common peripherals Uint16 rsvd15[12]; // Reserved union CPUSEL25_REG CPUSEL25; // CPU Select register for common peripherals Uint16 rsvd16[24]; // Reserved union CPU2RESCTL_REG CPU2RESCTL; // CPU2 Reset Control Register union RSTSTAT_REG RSTSTAT; // Reset Status register for secondary C28x CPUs union LPMSTAT_REG LPMSTAT; // LPM Status Register for secondary C28x CPUs Uint16 rsvd17[94]; // Reserved union BANKSEL_REG BANKSEL; // Configures the bank to programmed by CPU1. Uint16 rsvd18[20]; // Reserved union USBTYPE_REG USBTYPE; // Configures USB Type for the device union ECAPTYPE_REG ECAPTYPE; // Configures ECAP Type for the device union SDFMTYPE_REG SDFMTYPE; // Configures SDFM Type for the device Uint16 rsvd19; // Reserved union MEMMAPTYPE_REG MEMMAPTYPE; // Configures Memory Map Type for the device }; struct ADCA_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ADCA_AC_REG { Uint32 all; struct ADCA_AC_BITS bit; }; struct ADCB_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ADCB_AC_REG { Uint32 all; struct ADCB_AC_BITS bit; }; struct ADCC_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ADCC_AC_REG { Uint32 all; struct ADCC_AC_BITS bit; }; struct ADCD_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ADCD_AC_REG { Uint32 all; struct ADCD_AC_BITS bit; }; struct CMPSS1_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS1_AC_REG { Uint32 all; struct CMPSS1_AC_BITS bit; }; struct CMPSS2_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS2_AC_REG { Uint32 all; struct CMPSS2_AC_BITS bit; }; struct CMPSS3_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS3_AC_REG { Uint32 all; struct CMPSS3_AC_BITS bit; }; struct CMPSS4_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS4_AC_REG { Uint32 all; struct CMPSS4_AC_BITS bit; }; struct CMPSS5_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS5_AC_REG { Uint32 all; struct CMPSS5_AC_BITS bit; }; struct CMPSS6_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS6_AC_REG { Uint32 all; struct CMPSS6_AC_BITS bit; }; struct CMPSS7_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS7_AC_REG { Uint32 all; struct CMPSS7_AC_BITS bit; }; struct CMPSS8_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMPSS8_AC_REG { Uint32 all; struct CMPSS8_AC_BITS bit; }; struct DACA_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DACA_AC_REG { Uint32 all; struct DACA_AC_BITS bit; }; struct DACB_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DACB_AC_REG { Uint32 all; struct DACB_AC_BITS bit; }; struct DACC_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union DACC_AC_REG { Uint32 all; struct DACC_AC_BITS bit; }; struct EPWM1_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM1_AC_REG { Uint32 all; struct EPWM1_AC_BITS bit; }; struct EPWM2_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM2_AC_REG { Uint32 all; struct EPWM2_AC_BITS bit; }; struct EPWM3_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM3_AC_REG { Uint32 all; struct EPWM3_AC_BITS bit; }; struct EPWM4_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM4_AC_REG { Uint32 all; struct EPWM4_AC_BITS bit; }; struct EPWM5_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM5_AC_REG { Uint32 all; struct EPWM5_AC_BITS bit; }; struct EPWM6_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM6_AC_REG { Uint32 all; struct EPWM6_AC_BITS bit; }; struct EPWM7_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM7_AC_REG { Uint32 all; struct EPWM7_AC_BITS bit; }; struct EPWM8_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM8_AC_REG { Uint32 all; struct EPWM8_AC_BITS bit; }; struct EPWM9_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM9_AC_REG { Uint32 all; struct EPWM9_AC_BITS bit; }; struct EPWM10_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM10_AC_REG { Uint32 all; struct EPWM10_AC_BITS bit; }; struct EPWM11_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM11_AC_REG { Uint32 all; struct EPWM11_AC_BITS bit; }; struct EPWM12_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM12_AC_REG { Uint32 all; struct EPWM12_AC_BITS bit; }; struct EPWM13_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM13_AC_REG { Uint32 all; struct EPWM13_AC_BITS bit; }; struct EPWM14_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM14_AC_REG { Uint32 all; struct EPWM14_AC_BITS bit; }; struct EPWM15_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM15_AC_REG { Uint32 all; struct EPWM15_AC_BITS bit; }; struct EPWM16_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EPWM16_AC_REG { Uint32 all; struct EPWM16_AC_BITS bit; }; struct EQEP1_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EQEP1_AC_REG { Uint32 all; struct EQEP1_AC_BITS bit; }; struct EQEP2_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EQEP2_AC_REG { Uint32 all; struct EQEP2_AC_BITS bit; }; struct EQEP3_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union EQEP3_AC_REG { Uint32 all; struct EQEP3_AC_BITS bit; }; struct ECAP1_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP1_AC_REG { Uint32 all; struct ECAP1_AC_BITS bit; }; struct ECAP2_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP2_AC_REG { Uint32 all; struct ECAP2_AC_BITS bit; }; struct ECAP3_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP3_AC_REG { Uint32 all; struct ECAP3_AC_BITS bit; }; struct ECAP4_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP4_AC_REG { Uint32 all; struct ECAP4_AC_BITS bit; }; struct ECAP5_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP5_AC_REG { Uint32 all; struct ECAP5_AC_BITS bit; }; struct ECAP6_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP6_AC_REG { Uint32 all; struct ECAP6_AC_BITS bit; }; struct ECAP7_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union ECAP7_AC_REG { Uint32 all; struct ECAP7_AC_BITS bit; }; struct SDFM1_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SDFM1_AC_REG { Uint32 all; struct SDFM1_AC_BITS bit; }; struct SDFM2_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SDFM2_AC_REG { Uint32 all; struct SDFM2_AC_BITS bit; }; struct CLB1_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB1_AC_REG { Uint32 all; struct CLB1_AC_BITS bit; }; struct CLB2_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB2_AC_REG { Uint32 all; struct CLB2_AC_BITS bit; }; struct CLB3_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB3_AC_REG { Uint32 all; struct CLB3_AC_BITS bit; }; struct CLB4_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 rsvd1:2; // 5:4 Reserved Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CLB4_AC_REG { Uint32 all; struct CLB4_AC_BITS bit; }; struct SPIA_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SPIA_AC_REG { Uint32 all; struct SPIA_AC_BITS bit; }; struct SPIB_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SPIB_AC_REG { Uint32 all; struct SPIB_AC_BITS bit; }; struct SPIC_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SPIC_AC_REG { Uint32 all; struct SPIC_AC_BITS bit; }; struct SPID_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SPID_AC_REG { Uint32 all; struct SPID_AC_BITS bit; }; struct PMBUS_A_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PMBUS_A_AC_REG { Uint32 all; struct PMBUS_A_AC_BITS bit; }; struct CAN_A_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 rsvd1:2; // 3:2 Reserved Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CAN_A_AC_REG { Uint32 all; struct CAN_A_AC_BITS bit; }; struct CAN_B_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 rsvd1:2; // 3:2 Reserved Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union CAN_B_AC_REG { Uint32 all; struct CAN_B_AC_BITS bit; }; struct MCBSPA_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCBSPA_AC_REG { Uint32 all; struct MCBSPA_AC_BITS bit; }; struct MCBSPB_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union MCBSPB_AC_REG { Uint32 all; struct MCBSPB_AC_BITS bit; }; struct USBA_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 rsvd1:2; // 3:2 Reserved Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union USBA_AC_REG { Uint32 all; struct USBA_AC_BITS bit; }; struct HRPWM_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union HRPWM_AC_REG { Uint32 all; struct HRPWM_AC_BITS bit; }; struct ETHERCAT_AC_BITS { // bits description Uint16 CPU1_ACC:2; // 1:0 CPU1 Access conditions to peripheral Uint16 rsvd1:2; // 3:2 Reserved Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd2:10; // 15:6 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union ETHERCAT_AC_REG { Uint32 all; struct ETHERCAT_AC_BITS bit; }; struct FSIATX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIATX_AC_REG { Uint32 all; struct FSIATX_AC_BITS bit; }; struct FSIARX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIARX_AC_REG { Uint32 all; struct FSIARX_AC_BITS bit; }; struct FSIBTX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIBTX_AC_REG { Uint32 all; struct FSIBTX_AC_BITS bit; }; struct FSIBRX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIBRX_AC_REG { Uint32 all; struct FSIBRX_AC_BITS bit; }; struct FSICRX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSICRX_AC_REG { Uint32 all; struct FSICRX_AC_BITS bit; }; struct FSIDRX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIDRX_AC_REG { Uint32 all; struct FSIDRX_AC_BITS bit; }; struct FSIERX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIERX_AC_REG { Uint32 all; struct FSIERX_AC_BITS bit; }; struct FSIFRX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIFRX_AC_REG { Uint32 all; struct FSIFRX_AC_BITS bit; }; struct FSIGRX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIGRX_AC_REG { Uint32 all; struct FSIGRX_AC_BITS bit; }; struct FSIHRX_AC_BITS { // bits description Uint16 CPUx_ACC:2; // 1:0 CPUx Access conditions to peripheral Uint16 CLA1_ACC:2; // 3:2 CLA1 Access Conditions to Peripheral Uint16 DMA1_ACC:2; // 5:4 DMA1 Access Conditions to Peripheral Uint16 rsvd1:10; // 15:6 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union FSIHRX_AC_REG { Uint32 all; struct FSIHRX_AC_BITS bit; }; struct PERIPH_AC_LOCK_BITS { // bits description Uint16 LOCK_AC_WR:1; // 0 Lock control for Access control registers write. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union PERIPH_AC_LOCK_REG { Uint32 all; struct PERIPH_AC_LOCK_BITS bit; }; struct CPU1_PERIPH_AC_REGS { union ADCA_AC_REG ADCA_AC; // ADCA Master Access Control Register union ADCB_AC_REG ADCB_AC; // ADCB Master Access Control Register union ADCC_AC_REG ADCC_AC; // ADCC Master Access Control Register union ADCD_AC_REG ADCD_AC; // ADCD Master Access Control Register Uint16 rsvd1[8]; // Reserved union CMPSS1_AC_REG CMPSS1_AC; // CMPSS1 Master Access Control Register union CMPSS2_AC_REG CMPSS2_AC; // CMPSS2 Master Access Control Register union CMPSS3_AC_REG CMPSS3_AC; // CMPSS3 Master Access Control Register union CMPSS4_AC_REG CMPSS4_AC; // CMPSS4 Master Access Control Register union CMPSS5_AC_REG CMPSS5_AC; // CMPSS5 Master Access Control Register union CMPSS6_AC_REG CMPSS6_AC; // CMPSS6 Master Access Control Register union CMPSS7_AC_REG CMPSS7_AC; // CMPSS7 Master Access Control Register union CMPSS8_AC_REG CMPSS8_AC; // CMPSS8 Master Access Control Register Uint16 rsvd2[8]; // Reserved union DACA_AC_REG DACA_AC; // DACA Master Access Control Register union DACB_AC_REG DACB_AC; // DACB Master Access Control Register union DACC_AC_REG DACC_AC; // DACC Master Access Control Register Uint16 rsvd3[26]; // Reserved union EPWM1_AC_REG EPWM1_AC; // EPWM1 Master Access Control Register union EPWM2_AC_REG EPWM2_AC; // EPWM2 Master Access Control Register union EPWM3_AC_REG EPWM3_AC; // EPWM3 Master Access Control Register union EPWM4_AC_REG EPWM4_AC; // EPWM4 Master Access Control Register union EPWM5_AC_REG EPWM5_AC; // EPWM5 Master Access Control Register union EPWM6_AC_REG EPWM6_AC; // EPWM6 Master Access Control Register union EPWM7_AC_REG EPWM7_AC; // EPWM7 Master Access Control Register union EPWM8_AC_REG EPWM8_AC; // EPWM8 Master Access Control Register union EPWM9_AC_REG EPWM9_AC; // EPWM9 Master Access Control Register union EPWM10_AC_REG EPWM10_AC; // EPWM10 Master Access Control Register union EPWM11_AC_REG EPWM11_AC; // EPWM11 Master Access Control Register union EPWM12_AC_REG EPWM12_AC; // EPWM12 Master Access Control Register union EPWM13_AC_REG EPWM13_AC; // EPWM13 Master Access Control Register union EPWM14_AC_REG EPWM14_AC; // EPWM14 Master Access Control Register union EPWM15_AC_REG EPWM15_AC; // EPWM15 Master Access Control Register union EPWM16_AC_REG EPWM16_AC; // EPWM16 Master Access Control Register Uint16 rsvd4[8]; // Reserved union EQEP1_AC_REG EQEP1_AC; // EQEP1 Master Access Control Register union EQEP2_AC_REG EQEP2_AC; // EQEP2 Master Access Control Register union EQEP3_AC_REG EQEP3_AC; // EQEP3 Master Access Control Register Uint16 rsvd5[10]; // Reserved union ECAP1_AC_REG ECAP1_AC; // ECAP1 Master Access Control Register union ECAP2_AC_REG ECAP2_AC; // ECAP2 Master Access Control Register union ECAP3_AC_REG ECAP3_AC; // ECAP3 Master Access Control Register union ECAP4_AC_REG ECAP4_AC; // ECAP4 Master Access Control Register union ECAP5_AC_REG ECAP5_AC; // ECAP5 Master Access Control Register union ECAP6_AC_REG ECAP6_AC; // ECAP6 Master Access Control Register union ECAP7_AC_REG ECAP7_AC; // ECAP7 Master Access Control Register Uint16 rsvd6[26]; // Reserved union SDFM1_AC_REG SDFM1_AC; // SDFM1 Master Access Control Register union SDFM2_AC_REG SDFM2_AC; // SDFM2 Master Access Control Register Uint16 rsvd7[4]; // Reserved union CLB1_AC_REG CLB1_AC; // CLB1 Master Access Control Register union CLB2_AC_REG CLB2_AC; // CLB2 Master Access Control Register union CLB3_AC_REG CLB3_AC; // CLB3 Master Access Control Register union CLB4_AC_REG CLB4_AC; // CLB4 Master Access Control Register Uint16 rsvd8[88]; // Reserved union SPIA_AC_REG SPIA_AC; // SPIA Master Access Control Register union SPIB_AC_REG SPIB_AC; // SPIB Master Access Control Register union SPIC_AC_REG SPIC_AC; // SPIC Master Access Control Register union SPID_AC_REG SPID_AC; // SPID Master Access Control Register Uint16 rsvd9[24]; // Reserved union PMBUS_A_AC_REG PMBUS_A_AC; // PMBUSA Master Access Control Register Uint16 rsvd10[14]; // Reserved union CAN_A_AC_REG CAN_A_AC; // CAN_A Master Access Control Register union CAN_B_AC_REG CAN_B_AC; // CAN_B Master Access Control Register Uint16 rsvd11[12]; // Reserved union MCBSPA_AC_REG MCBSPA_AC; // MCBSPA Master Access Control Register union MCBSPB_AC_REG MCBSPB_AC; // MCBSPB Master Access Control Register Uint16 rsvd12[44]; // Reserved union USBA_AC_REG USBA_AC; // USBA Master Access Control Register Uint16 rsvd13[38]; // Reserved union HRPWM_AC_REG HRPWM_AC; // HRPWM Master Access Control Register union ETHERCAT_AC_REG ETHERCAT_AC; // ETHERCAT Master Access Control Register Uint16 rsvd14[4]; // Reserved union FSIATX_AC_REG FSIATX_AC; // FSIATX Master Access Control Register union FSIARX_AC_REG FSIARX_AC; // FSIARX Master Access Control Register union FSIBTX_AC_REG FSIBTX_AC; // FSIBTX Master Access Control Register union FSIBRX_AC_REG FSIBRX_AC; // FSIBRX Master Access Control Register Uint16 rsvd15[2]; // Reserved union FSICRX_AC_REG FSICRX_AC; // FSICRX Master Access Control Register Uint16 rsvd16[2]; // Reserved union FSIDRX_AC_REG FSIDRX_AC; // FSIDRX Master Access Control Register Uint16 rsvd17[2]; // Reserved union FSIERX_AC_REG FSIERX_AC; // FSIERX Master Access Control Register Uint16 rsvd18[2]; // Reserved union FSIFRX_AC_REG FSIFRX_AC; // FSIFRX Master Access Control Register Uint16 rsvd19[2]; // Reserved union FSIGRX_AC_REG FSIGRX_AC; // FSIGRX Master Access Control Register Uint16 rsvd20[2]; // Reserved union FSIHRX_AC_REG FSIHRX_AC; // FSIHRX Master Access Control Register Uint16 rsvd21[46]; // Reserved union PERIPH_AC_LOCK_REG PERIPH_AC_LOCK; // Lock Register to stop Write access to peripheral Access register. }; struct CPU2_PERIPH_AC_REGS { union ADCA_AC_REG ADCA_AC; // ADCA Master Access Control Register union ADCB_AC_REG ADCB_AC; // ADCB Master Access Control Register union ADCC_AC_REG ADCC_AC; // ADCC Master Access Control Register union ADCD_AC_REG ADCD_AC; // ADCD Master Access Control Register Uint16 rsvd1[8]; // Reserved union CMPSS1_AC_REG CMPSS1_AC; // CMPSS1 Master Access Control Register union CMPSS2_AC_REG CMPSS2_AC; // CMPSS2 Master Access Control Register union CMPSS3_AC_REG CMPSS3_AC; // CMPSS3 Master Access Control Register union CMPSS4_AC_REG CMPSS4_AC; // CMPSS4 Master Access Control Register union CMPSS5_AC_REG CMPSS5_AC; // CMPSS5 Master Access Control Register union CMPSS6_AC_REG CMPSS6_AC; // CMPSS6 Master Access Control Register union CMPSS7_AC_REG CMPSS7_AC; // CMPSS7 Master Access Control Register union CMPSS8_AC_REG CMPSS8_AC; // CMPSS8 Master Access Control Register Uint16 rsvd2[8]; // Reserved union DACA_AC_REG DACA_AC; // DACA Master Access Control Register union DACB_AC_REG DACB_AC; // DACB Master Access Control Register union DACC_AC_REG DACC_AC; // DACC Master Access Control Register Uint16 rsvd3[26]; // Reserved union EPWM1_AC_REG EPWM1_AC; // EPWM1 Master Access Control Register union EPWM2_AC_REG EPWM2_AC; // EPWM2 Master Access Control Register union EPWM3_AC_REG EPWM3_AC; // EPWM3 Master Access Control Register union EPWM4_AC_REG EPWM4_AC; // EPWM4 Master Access Control Register union EPWM5_AC_REG EPWM5_AC; // EPWM5 Master Access Control Register union EPWM6_AC_REG EPWM6_AC; // EPWM6 Master Access Control Register union EPWM7_AC_REG EPWM7_AC; // EPWM7 Master Access Control Register union EPWM8_AC_REG EPWM8_AC; // EPWM8 Master Access Control Register union EPWM9_AC_REG EPWM9_AC; // EPWM9 Master Access Control Register union EPWM10_AC_REG EPWM10_AC; // EPWM10 Master Access Control Register union EPWM11_AC_REG EPWM11_AC; // EPWM11 Master Access Control Register union EPWM12_AC_REG EPWM12_AC; // EPWM12 Master Access Control Register union EPWM13_AC_REG EPWM13_AC; // EPWM13 Master Access Control Register union EPWM14_AC_REG EPWM14_AC; // EPWM14 Master Access Control Register union EPWM15_AC_REG EPWM15_AC; // EPWM15 Master Access Control Register union EPWM16_AC_REG EPWM16_AC; // EPWM16 Master Access Control Register Uint16 rsvd4[8]; // Reserved union EQEP1_AC_REG EQEP1_AC; // EQEP1 Master Access Control Register union EQEP2_AC_REG EQEP2_AC; // EQEP2 Master Access Control Register union EQEP3_AC_REG EQEP3_AC; // EQEP3 Master Access Control Register Uint16 rsvd5[10]; // Reserved union ECAP1_AC_REG ECAP1_AC; // ECAP1 Master Access Control Register union ECAP2_AC_REG ECAP2_AC; // ECAP2 Master Access Control Register union ECAP3_AC_REG ECAP3_AC; // ECAP3 Master Access Control Register union ECAP4_AC_REG ECAP4_AC; // ECAP4 Master Access Control Register union ECAP5_AC_REG ECAP5_AC; // ECAP5 Master Access Control Register union ECAP6_AC_REG ECAP6_AC; // ECAP6 Master Access Control Register union ECAP7_AC_REG ECAP7_AC; // ECAP7 Master Access Control Register Uint16 rsvd6[26]; // Reserved union SDFM1_AC_REG SDFM1_AC; // SDFM1 Master Access Control Register union SDFM2_AC_REG SDFM2_AC; // SDFM2 Master Access Control Register Uint16 rsvd7[100]; // Reserved union SPIA_AC_REG SPIA_AC; // SPIA Master Access Control Register union SPIB_AC_REG SPIB_AC; // SPIB Master Access Control Register union SPIC_AC_REG SPIC_AC; // SPIC Master Access Control Register union SPID_AC_REG SPID_AC; // SPID Master Access Control Register Uint16 rsvd8[24]; // Reserved union PMBUS_A_AC_REG PMBUS_A_AC; // PMBUSA Master Access Control Register Uint16 rsvd9[14]; // Reserved union CAN_A_AC_REG CAN_A_AC; // CAN_A Master Access Control Register union CAN_B_AC_REG CAN_B_AC; // CAN_B Master Access Control Register Uint16 rsvd10[12]; // Reserved union MCBSPA_AC_REG MCBSPA_AC; // MCBSPA Master Access Control Register union MCBSPB_AC_REG MCBSPB_AC; // MCBSPB Master Access Control Register Uint16 rsvd11[44]; // Reserved union USBA_AC_REG USBA_AC; // USBA Master Access Control Register Uint16 rsvd12[38]; // Reserved union HRPWM_AC_REG HRPWM_AC; // HRPWM Master Access Control Register Uint16 rsvd13[6]; // Reserved union FSIATX_AC_REG FSIATX_AC; // FSIATX Master Access Control Register union FSIARX_AC_REG FSIARX_AC; // FSIARX Master Access Control Register union FSIBTX_AC_REG FSIBTX_AC; // FSIBTX Master Access Control Register union FSIBRX_AC_REG FSIBRX_AC; // FSIBRX Master Access Control Register Uint16 rsvd14[2]; // Reserved union FSICRX_AC_REG FSICRX_AC; // FSICRX Master Access Control Register Uint16 rsvd15[2]; // Reserved union FSIDRX_AC_REG FSIDRX_AC; // FSIDRX Master Access Control Register Uint16 rsvd16[2]; // Reserved union FSIERX_AC_REG FSIERX_AC; // FSIERX Master Access Control Register Uint16 rsvd17[2]; // Reserved union FSIFRX_AC_REG FSIFRX_AC; // FSIFRX Master Access Control Register Uint16 rsvd18[2]; // Reserved union FSIGRX_AC_REG FSIGRX_AC; // FSIGRX Master Access Control Register Uint16 rsvd19[2]; // Reserved union FSIHRX_AC_REG FSIHRX_AC; // FSIHRX Master Access Control Register Uint16 rsvd20[46]; // Reserved union PERIPH_AC_LOCK_REG PERIPH_AC_LOCK; // Lock Register to stop Write access to peripheral Access register. }; struct CMRESCTL_BITS { // bits description Uint16 RESET:1; // 0 Software reset to CM Uint16 RESETSTS:1; // 1 CM Reset status Uint16 rsvd1:14; // 15:2 Reserved Uint16 KEY:16; // 31:16 Key value }; union CMRESCTL_REG { Uint32 all; struct CMRESCTL_BITS bit; }; struct CMTOCPU1NMICTL_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 rsvd2:1; // 1 Reserved Uint16 CMNMIWDRST:1; // 2 CMNMIWDRST NMI enable bit, enables nmi generation to C28x Uint16 rsvd3:13; // 15:3 Reserved Uint16 rsvd4:16; // 31:16 Reserved }; union CMTOCPU1NMICTL_REG { Uint32 all; struct CMTOCPU1NMICTL_BITS bit; }; struct CMTOCPU1INTCTL_BITS { // bits description Uint16 VECTRESET:1; // 0 VECTRESET Interrupt enable bit, enables interrupt to C28x Uint16 SYSRESETREQ:1; // 1 SYSRESETREQ Interrupt enable bit, enables interrupt to C28x Uint16 CMNMIWDRST:1; // 2 CMNMIWDRST Interrupt enable bit, enables interrupt to C28x Uint16 rsvd1:13; // 15:3 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CMTOCPU1INTCTL_REG { Uint32 all; struct CMTOCPU1INTCTL_BITS bit; }; struct PALLOCATE0_BITS { // bits description Uint16 USB_A:1; // 0 Allocate USB_A to CM Uint16 ETHERCAT:1; // 1 Allocate ETHERCAT to CM Uint16 CAN_A:1; // 2 Allocate CANA to CM Uint16 CAN_B:1; // 3 Allocate CANB to CM Uint16 rsvd1:1; // 4 Reserved Uint16 rsvd2:11; // 15:5 Reserved Uint16 rsvd3:16; // 31:16 Reserved }; union PALLOCATE0_REG { Uint32 all; struct PALLOCATE0_BITS bit; }; struct CM_CONF_REGS_LOCK_BITS { // bits description Uint16 LOCK:1; // 0 Lock one time CM configuration registers. Uint16 rsvd1:15; // 15:1 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CM_CONF_REGS_LOCK_REG { Uint32 all; struct CM_CONF_REGS_LOCK_BITS bit; }; struct CM_CONF_REGS { union CMRESCTL_REG CMRESCTL; // CM Reset Control Register union CMTOCPU1NMICTL_REG CMTOCPU1NMICTL; // CM To CPU1 NMI Control register union CMTOCPU1INTCTL_REG CMTOCPU1INTCTL; // CM To CPU1 interrupt Control register Uint16 rsvd1[26]; // Reserved union PALLOCATE0_REG PALLOCATE0; // CM Peripheral Allocation Register. Uint16 rsvd2[988]; // Reserved union CM_CONF_REGS_LOCK_REG CM_CONF_REGS_LOCK; // CM Configuration Registers Lock }; struct CM_STATUS_INT_FLG_BITS { // bits description Uint16 GINT:1; // 0 Global Interrupt flag Uint16 CMNMIWDRST:1; // 1 CMNMIWDRST caused a reset of CM Uint16 CMSYSRESETREQ:1; // 2 CMSYSRESETREQ caused a reset of CM Uint16 CMVECTRESET:1; // 3 CMVECTRESET caused a reset of CM Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CM_STATUS_INT_FLG_REG { Uint32 all; struct CM_STATUS_INT_FLG_BITS bit; }; struct CM_STATUS_INT_CLR_BITS { // bits description Uint16 GINT:1; // 0 Global Interrupt flag Clear bit Uint16 CMNMIWDRST:1; // 1 CMNMIWDRST interrupt flag clear bit Uint16 CMSYSRESETREQ:1; // 2 CMSYSRESETREQ interrupt flag clear bit Uint16 CMVECTRESET:1; // 3 CMVECTRESET interrupt flag clear bit Uint16 rsvd1:12; // 15:4 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union CM_STATUS_INT_CLR_REG { Uint32 all; struct CM_STATUS_INT_CLR_BITS bit; }; struct CM_STATUS_INT_SET_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CMNMIWDRST:1; // 1 CMNMIWDRST interrupt flag set bit Uint16 CMSYSRESETREQ:1; // 2 CMSYSRESETREQ interrupt flag set bit Uint16 CMVECTRESET:1; // 3 CMVECTRESET interrupt flag set bit Uint16 rsvd2:12; // 15:4 Reserved Uint16 KEY:16; // 31:16 KEY field }; union CM_STATUS_INT_SET_REG { Uint32 all; struct CM_STATUS_INT_SET_BITS bit; }; struct CM_STATUS_MASK_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 CMNMIWDRST:1; // 1 CMNMIWDRST flag mask bit Uint16 CMSYSRESETREQ:1; // 2 CMSYSRESETREQ interrupt flag set bit Uint16 CMVECTRESET:1; // 3 CMVECTRESET interrupt flag set bit Uint16 rsvd2:12; // 15:4 Reserved Uint16 KEY:16; // 31:16 KEY field }; union CM_STATUS_MASK_REG { Uint32 all; struct CM_STATUS_MASK_BITS bit; }; struct SYS_ERR_INT_FLG_BITS { // bits description Uint16 GINT:1; // 0 Global Interrupt flag Uint16 EMIF_ERR:1; // 1 EMIF error event flag Uint16 RAM_CORRECTABLE_ERR:1; // 2 RAM correctable error flag Uint16 FLASH_CORRECTABLE_ERR:1; // 3 FLASH correctable error flag Uint16 RAM_ACC_VIOL:1; // 4 A RAM access vioation flag. Uint16 SYS_PLL_SLIP_NOTSUPPORTED:1; // 5 System PLL Slip event flag. Uint16 AUX_PLL_SLIP_NOTSUPPORTED:1; // 6 Auxillary PLL Slip event flag. Uint16 DCC0:1; // 7 DCC0 Interrupt flag. Uint16 DCC1:1; // 8 DCC1 Interrupt flag. Uint16 DCC2:1; // 9 DCC2 Interrupt flag. Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYS_ERR_INT_FLG_REG { Uint32 all; struct SYS_ERR_INT_FLG_BITS bit; }; struct SYS_ERR_INT_CLR_BITS { // bits description Uint16 GINT:1; // 0 Global Interrupt flag Clear bit Uint16 EMIF_ERR:1; // 1 EMIF_ERR interrupt flag clear bit Uint16 RAM_CORRECTABLE_ERR:1; // 2 RAM_CORRECTABLE_ERR interrupt flag clear bit Uint16 FLASH_CORRECTABLE_ERR:1; // 3 FLASH_CORRECTABLE_ERR interrupt flag clear bit Uint16 RAM_ACC_VIOL:1; // 4 RAM_ACC_VIOL interrupt flag clear bit Uint16 SYS_PLL_SLIP_NOTSUPPORTED:1; // 5 SYS_PLL_SLIP interrupt flag clear bit Uint16 AUX_PLL_SLIP_NOTSUPPORTED:1; // 6 AUX_PLL_SLIP interrupt flag clear bit Uint16 DCC0:1; // 7 DCC0 interrupt flag clear bit Uint16 DCC1:1; // 8 DCC1 interrupt flag clear bit Uint16 DCC2:1; // 9 DCC2 interrupt flag clear bit Uint16 rsvd1:6; // 15:10 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYS_ERR_INT_CLR_REG { Uint32 all; struct SYS_ERR_INT_CLR_BITS bit; }; struct SYS_ERR_INT_SET_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 EMIF_ERR:1; // 1 Reserved Uint16 RAM_CORRECTABLE_ERR:1; // 2 RAM_CORRECTABLE_ERR interrupt flag set bit Uint16 FLASH_CORRECTABLE_ERR:1; // 3 FLASH_CORRECTABLE_ERR interrupt flag set bit Uint16 RAM_ACC_VIOL:1; // 4 RAM_ACC_VIOL interrupt flag set bit Uint16 SYS_PLL_SLIP_NOTSUPPORTED:1; // 5 SYS_PLL_SLIP interrupt flag set bit Uint16 AUX_PLL_SLIP_NOTSUPPORTED:1; // 6 AUX_PLL_SLIP interrupt flag set bit Uint16 DCC0:1; // 7 DCC0 interrupt flag set bit Uint16 DCC1:1; // 8 DCC1 interrupt flag set bit Uint16 DCC2:1; // 9 DCC2 interrupt flag set bit Uint16 rsvd2:6; // 15:10 Reserved Uint16 KEY:16; // 31:16 KEY field }; union SYS_ERR_INT_SET_REG { Uint32 all; struct SYS_ERR_INT_SET_BITS bit; }; struct SYS_ERR_MASK_BITS { // bits description Uint16 rsvd1:1; // 0 Reserved Uint16 EMIF_ERR:1; // 1 Reserved Uint16 RAM_CORRECTABLE_ERR:1; // 2 RAM_CORRECTABLE_ERR flag mask bit Uint16 FLASH_CORRECTABLE_ERR:1; // 3 FLASH_CORRECTABLE_ERR flag mask bit Uint16 RAM_ACC_VIOL:1; // 4 RAM_ACC_VIOL flag mask bit Uint16 SYS_PLL_SLIP:1; // 5 SYS_PLL_SLIP flag mask bit Uint16 AUX_PLL_SLIP:1; // 6 AUX_PLL_SLIP flag mask bit Uint16 DCC0:1; // 7 DCC0 flag mask bit Uint16 DCC1:1; // 8 DCC1 flag mask bit Uint16 DCC2:1; // 9 DCC2 flag mask bit Uint16 rsvd2:6; // 15:10 Reserved Uint16 KEY:16; // 31:16 KEY field }; union SYS_ERR_MASK_REG { Uint32 all; struct SYS_ERR_MASK_BITS bit; }; struct SYS_STATUS_REGS { union CM_STATUS_INT_FLG_REG CM_STATUS_INT_FLG; // Status of interrupts due to multiple sources of Cortex-M4 reset. union CM_STATUS_INT_CLR_REG CM_STATUS_INT_CLR; // CM_STATUS_INT_FLG clear register union CM_STATUS_INT_SET_REG CM_STATUS_INT_SET; // CM_STATUS_INT_FLG set register union CM_STATUS_MASK_REG CM_STATUS_MASK; // CM_STATUS_MASK register Uint16 rsvd1[8]; // Reserved union SYS_ERR_INT_FLG_REG SYS_ERR_INT_FLG; // Status of interrupts due to multiple different errors in the system. union SYS_ERR_INT_CLR_REG SYS_ERR_INT_CLR; // SYS_ERR_INT_FLG clear register union SYS_ERR_INT_SET_REG SYS_ERR_INT_SET; // SYS_ERR_INT_FLG set register union SYS_ERR_MASK_REG SYS_ERR_MASK; // SYS_ERR_MASK register }; struct VMT_SPARE_MMR_REGS { }; struct SYNCSELECT_BITS { // bits description Uint16 rsvd1:3; // 2:0 Reserved Uint16 rsvd2:3; // 5:3 Reserved Uint16 rsvd3:3; // 8:6 Reserved Uint16 rsvd4:3; // 11:9 Reserved Uint16 rsvd5:3; // 14:12 Reserved Uint16 rsvd6:1; // 15 Reserved Uint16 rsvd7:4; // 19:16 Reserved Uint16 rsvd8:4; // 23:20 Reserved Uint16 SYNCOUT:5; // 28:24 Select Syncout Source Uint16 rsvd9:3; // 31:29 Reserved }; union SYNCSELECT_REG { Uint32 all; struct SYNCSELECT_BITS bit; }; struct ADCSOCOUTSELECT_BITS { // bits description Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAOn Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAOn Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAOn Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAOn Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAOn Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAOn Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAOn Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAOn Uint16 PWM9SOCAEN:1; // 8 PWM9SOCAEN Enable for ADCSOCAOn Uint16 PWM10SOCAEN:1; // 9 PWM10SOCAEN Enable for ADCSOCAOn Uint16 PWM11SOCAEN:1; // 10 PWM11SOCAEN Enable for ADCSOCAOn Uint16 PWM12SOCAEN:1; // 11 PWM12SOCAEN Enable for ADCSOCAOn Uint16 PWM13SOCAEN:1; // 12 PWM13SOCAEN Enable for ADCSOCAOn Uint16 PWM14SOCAEN:1; // 13 PWM14SOCAEN Enable for ADCSOCAOn Uint16 PWM15SOCAEN:1; // 14 PWM15SOCAEN Enable for ADCSOCAOn Uint16 PWM16SOCAEN:1; // 15 PWM16SOCAEN Enable for ADCSOCAOn Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBOn Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBOn Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBOn Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBOn Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBOn Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBOn Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBOn Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBOn Uint16 PWM9SOCBEN:1; // 24 PWM9SOCBEN Enable for ADCSOCBOn Uint16 PWM10SOCBEN:1; // 25 PWM10SOCBEN Enable for ADCSOCBOn Uint16 PWM11SOCBEN:1; // 26 PWM11SOCBEN Enable for ADCSOCBOn Uint16 PWM12SOCBEN:1; // 27 PWM12SOCBEN Enable for ADCSOCBOn Uint16 PWM13SOCBEN:1; // 28 PWM13SOCBEN Enable for ADCSOCBOn Uint16 PWM14SOCBEN:1; // 29 PWM14SOCBEN Enable for ADCSOCBOn Uint16 PWM15SOCBEN:1; // 30 PWM15SOCBEN Enable for ADCSOCBOn Uint16 PWM16SOCBEN:1; // 31 PWM16SOCBEN Enable for ADCSOCBOn }; union ADCSOCOUTSELECT_REG { Uint32 all; struct ADCSOCOUTSELECT_BITS bit; }; struct SYNCSOCLOCK_BITS { // bits description Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit Uint16 rsvd1:14; // 15:2 Reserved Uint16 rsvd2:16; // 31:16 Reserved }; union SYNCSOCLOCK_REG { Uint32 all; struct SYNCSOCLOCK_BITS bit; }; struct SYNC_SOC_REGS { union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADC (Off Chip) SOC Select Register union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register }; //--------------------------------------------------------------------------- // SYSCTRL External References & Function Declarations: // extern volatile struct SYNC_SOC_REGS SyncSocRegs; extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; extern volatile struct DEV_CFG_REGS DevCfgRegs; extern volatile struct CLK_CFG_REGS ClkCfgRegs; extern volatile struct CPU_SYS_REGS CpuSysRegs; extern volatile struct CPU1_PERIPH_AC_REGS SysPeriphAcRegs; extern volatile struct CM_CONF_REGS CmConfRegs; extern volatile struct SYS_STATUS_REGS SysStatusRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_wwd.h // // TITLE: Definitions for the SYSCTL registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // SYSCTL Individual Register Bit Definitions: struct SCSR_BITS { // bits description Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit Uint16 WDENINT:1; // 1 WD Interrupt Enable Uint16 WDINTS:1; // 2 WD Interrupt Status Uint16 rsvd1:13; // 15:3 Reserved }; union SCSR_REG { Uint16 all; struct SCSR_BITS bit; }; struct WDCNTR_BITS { // bits description Uint16 WDCNTR:8; // 7:0 WD Counter Uint16 rsvd1:8; // 15:8 Reserved }; union WDCNTR_REG { Uint16 all; struct WDCNTR_BITS bit; }; struct WDKEY_BITS { // bits description Uint16 WDKEY:8; // 7:0 WD KEY Uint16 rsvd1:8; // 15:8 Reserved }; union WDKEY_REG { Uint16 all; struct WDKEY_BITS bit; }; struct WDCR_BITS { // bits description Uint16 WDPS:3; // 2:0 WD Clock Prescalar Uint16 WDCHK:3; // 5:3 WD Check Bits Uint16 WDDIS:1; // 6 WD Disable Uint16 WDFLG:1; // 7 WD Reset Status Flag Uint16 WDPRECLKDIV:4; // 11:8 WD Pre Clock Divider Uint16 rsvd1:4; // 15:12 Reserved }; union WDCR_REG { Uint16 all; struct WDCR_BITS bit; }; struct WDWCR_BITS { // bits description Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality Uint16 FIRSTKEY:1; // 8 First Key Detect Flag Uint16 rsvd1:7; // 15:9 Reserved }; union WDWCR_REG { Uint16 all; struct WDWCR_BITS bit; }; struct WD_REGS { Uint16 rsvd1[34]; // Reserved union SCSR_REG SCSR; // System Control & Status Register union WDCNTR_REG WDCNTR; // Watchdog Counter Register Uint16 rsvd2; // Reserved union WDKEY_REG WDKEY; // Watchdog Reset Key Register Uint16 rsvd3[3]; // Reserved union WDCR_REG WDCR; // Watchdog Control Register union WDWCR_REG WDWCR; // Watchdog Windowed Control Register }; //--------------------------------------------------------------------------- // WWD External References & Function Declarations: // extern volatile struct WD_REGS WdRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_xbar.h // // TITLE: Definitions for the XBAR registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XBAR Individual Register Bit Definitions: struct XBARFLG1_BITS { // bits description Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal }; union XBARFLG1_REG { Uint32 all; struct XBARFLG1_BITS bit; }; struct XBARFLG2_BITS { // bits description Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal Uint16 ADCSOCA:1; // 6 Input Flag for ADCSOCA Signal Uint16 ADCSOCB:1; // 7 Input Flag for ADCSOCB Signal Uint16 INPUT7:1; // 8 Input Flag for INPUT7 Signal Uint16 INPUT8:1; // 9 Input Flag for INPUT8 Signal Uint16 INPUT9:1; // 10 Input Flag for INPUT9 Signal Uint16 INPUT10:1; // 11 Input Flag for INPUT10\ Signal Uint16 INPUT11:1; // 12 Input Flag for INPUT11 Signal Uint16 INPUT12:1; // 13 Input Flag for INPUT12 Signal Uint16 INPUT13:1; // 14 Input Flag for INPUT13 Signal Uint16 INPUT14:1; // 15 Input Flag for INPUT14 Signal Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal }; union XBARFLG2_REG { Uint32 all; struct XBARFLG2_BITS bit; }; struct XBARFLG3_BITS { // bits description Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal Uint16 ECAP7_OUT:1; // 23 Input Flag for ECAP7.OUT Signal Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag for SD1FLT1.COMPZ Signal Uint16 SD1FLT1_DRINT:1; // 25 Input Flag for SD1FLT1.DRINT Signal Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag for SD1FLT2.COMPZ Signal Uint16 SD1FLT2_DRINT:1; // 27 Input Flag for SD1FLT2.DRINT Signal Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag for SD1FLT3.COMPZ Signal Uint16 SD1FLT3_DRINT:1; // 29 Input Flag for SD1FLT3.DRINT Signal Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag for SD1FLT4.COMPZ Signal Uint16 SD1FLT4_DRINT:1; // 31 Input Flag for SD1FLT4.DRINT Signal }; union XBARFLG3_REG { Uint32 all; struct XBARFLG3_BITS bit; }; struct XBARFLG4_BITS { // bits description Uint16 SD2FLT1_COMPZ:1; // 0 Input Flag for SD2FLT1.COMPZ Signal Uint16 SD2FLT1_DRINT:1; // 1 Input Flag for SD2FLT1.DRINT Signal Uint16 SD2FLT2_COMPZ:1; // 2 Input Flag for SD2FLT2.COMPZ Signal Uint16 SD2FLT2_DRINT:1; // 3 Input Flag for SD2FLT2.DRINT Signal Uint16 SD2FLT3_COMPZ:1; // 4 Input Flag for SD2FLT3.COMPZ Signal Uint16 SD2FLT3_DRINT:1; // 5 Input Flag for SD2FLT3.DRINT Signal Uint16 SD2FLT4_COMPZ:1; // 6 Input Flag for SD2FLT4.COMPZ Signal Uint16 SD2FLT4_DRINT:1; // 7 Input Flag for SD2FLT4.DRINT Signal Uint16 EMAC_PPS0:1; // 8 Input Flag for EMAC_PPS0 Signal Uint16 MCANA_FEVT0:1; // 9 Input Flag for MCANA_FEVT0 Signal Uint16 MCANA_FEVT1:1; // 10 Input Flag for MCANA_FEVT1 Signal Uint16 MCANA_FEVT2:1; // 11 Input Flag for MCANA_FEVT2 Signal Uint16 rsvd1:1; // 12 Input Flag for CLB7_4.1 Signal Uint16 rsvd2:1; // 13 Input Flag for CLB7_5.1 Signal Uint16 rsvd3:1; // 14 Input Flag for CLB8_4.1 Signal Uint16 rsvd4:1; // 15 Input Flag for CLB8_5.1 Signal Uint16 CLB1_OUT4:1; // 16 Input Flag for CLB1_4.1 Signal Uint16 CLB1_OUT5:1; // 17 Input Flag for CLB1_5.1 Signal Uint16 CLB2_OUT4:1; // 18 Input Flag for CLB2_4.1 Signal Uint16 CLB2_OUT5:1; // 19 Input Flag for CLB2_5.1 Signal Uint16 CLB3_OUT4:1; // 20 Input Flag for CLB3_4.1 Signal Uint16 CLB3_OUT5:1; // 21 Input Flag for CLB3_5.1 Signal Uint16 CLB4_OUT4:1; // 22 Input Flag for CLB4_4.1 Signal Uint16 CLB4_OUT5:1; // 23 Input Flag for CLB4_5.1 Signal Uint16 rsvd5:1; // 24 Input Latch for CLB5_OUT4 Signal Uint16 rsvd6:1; // 25 Input Latch for CLB5_OUT5 Signal Uint16 rsvd7:1; // 26 Input Latch for CLB6_OUT4 Signal Uint16 rsvd8:1; // 27 Input Latch for CLB6_OUT5 Signal Uint16 ERRORSTS_ERROR:1; // 28 Input Latch for ERRORSTS_ERROR Signal Uint16 ECATSYNC0:1; // 29 Input Latch for ECATSYNC0 Signal Uint16 ECATSYNC1:1; // 30 Input Latch for ECATSYNC1 Signal Uint16 CLAHALT:1; // 31 Input Latch for CLAHALT Signal }; union XBARFLG4_REG { Uint32 all; struct XBARFLG4_BITS bit; }; struct XBARCLR1_BITS { // bits description Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal }; union XBARCLR1_REG { Uint32 all; struct XBARCLR1_BITS bit; }; struct XBARCLR2_BITS { // bits description Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal Uint16 INPUT6:1; // 5 Input Flag Clear for INPUT6 Signal Uint16 ADCSOCA:1; // 6 Input Flag Clear for ADCSOCA Signal Uint16 ADCSOCB:1; // 7 Input Flag Clear for ADCSOCB Signal Uint16 INPUT7:1; // 8 Input Flag Clear for INPUT7 Signal Uint16 INPUT8:1; // 9 Input Flag Clear for INPUT8 Signal Uint16 INPUT9:1; // 10 Input Flag Clear for INPUT9 Signal Uint16 INPUT10:1; // 11 Input Flag Clear for INPUT10 Signal Uint16 INPUT11:1; // 12 Input Flag Clear for INPUT11 Signal Uint16 INPUT12:1; // 13 Input Flag Clear for INPUT12 Signal Uint16 INPUT13:1; // 14 Input Flag Clear for INPUT13 Signal Uint16 INPUT14:1; // 15 Input Flag Clear for INPUT14 Signal Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal }; union XBARCLR2_REG { Uint32 all; struct XBARCLR2_BITS bit; }; struct XBARCLR3_BITS { // bits description Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal Uint16 ECAP7_OUT:1; // 23 Input Flag clear for ECAP7.OUT Signal Uint16 SD1FLT1_COMPZ:1; // 24 Input Flag clear for SD1FLT1.COMPZ Signal Uint16 SD1FLT1_DRINT:1; // 25 Input Flag clear for SD1FLT1.DRINT Signal Uint16 SD1FLT2_COMPZ:1; // 26 Input Flag clear for SD1FLT2.COMPZ Signal Uint16 SD1FLT2_DRINT:1; // 27 Input Flag clear for SD1FLT2.DRINT Signal Uint16 SD1FLT3_COMPZ:1; // 28 Input Flag clear for SD1FLT3.COMPZ Signal Uint16 SD1FLT3_DRINT:1; // 29 Input Flag clear for SD1FLT3.DRINT Signal Uint16 SD1FLT4_COMPZ:1; // 30 Input Flag clear for SD1FLT4.COMPZ Signal Uint16 SD1FLT4_DRINT:1; // 31 Input Flag clear for SD1FLT4.DRINT Signal }; union XBARCLR3_REG { Uint32 all; struct XBARCLR3_BITS bit; }; struct XBARCLR4_BITS { // bits description Uint16 SD2FLT1_COMPZ:1; // 0 Input Flag clear for SD2FLT1.COMPZ Signal Uint16 SD2FLT1_DRINT:1; // 1 Input Flag clear for SD2FLT1.DRINT Signal Uint16 SD2FLT2_COMPZ:1; // 2 Input Flag clear for SD2FLT2.COMPZ Signal Uint16 SD2FLT2_DRINT:1; // 3 Input Flag clear for SD2FLT2.DRINT Signal Uint16 SD2FLT3_COMPZ:1; // 4 Input Flag clear for SD2FLT3.COMPZ Signal Uint16 SD2FLT3_DRINT:1; // 5 Input Flag clear for SD2FLT3.DRINT Signal Uint16 SD2FLT4_COMPZ:1; // 6 Input Flag clear for SD2FLT4.COMPZ Signal Uint16 SD2FLT4_DRINT:1; // 7 Input Flag clear for SD2FLT4.DRINT Signal Uint16 EMAC_PPS0:1; // 8 Input Flag clear for EMAC_PPS0 Signal Uint16 MCANA_FEVT0:1; // 9 Input Flag clear for MCANA_FEVT0 Signal Uint16 MCANA_FEVT1:1; // 10 Input Flag clear for MCANA_FEVT1 Signal Uint16 MCANA_FEVT2:1; // 11 Input Flag clear for MCANA_FEVT2 Signal Uint16 rsvd1:1; // 12 Input Flag clear for CLB7_OUT4 Signal Uint16 rsvd2:1; // 13 Input Flag clear for CLB7_OUT5 Signal Uint16 rsvd3:1; // 14 Input Flag clear for CLB8_OUT4 Signal Uint16 rsvd4:1; // 15 Input Flag clear for CLB8_OUT5 Signal Uint16 CLB1_OUT4:1; // 16 Input Flag clear for CLB1_4.1 Signal Uint16 CLB1_OUT5:1; // 17 Input Flag clear for CLB1_5.1 Signal Uint16 CLB2_OUT4:1; // 18 Input Flag clear for CLB2_4.1 Signal Uint16 CLB2_OUT5:1; // 19 Input Flag clear for CLB2_5.1 Signal Uint16 CLB3_OUT4:1; // 20 Input Flag clear for CLB3_4.1 Signal Uint16 CLB3_OUT5:1; // 21 Input Flag clear for CLB3_5.1 Signal Uint16 CLB4_OUT4:1; // 22 Input Flag clear for CLB4_4.1 Signal Uint16 CLB4_OUT5:1; // 23 Input Flag clear for CLB4_5.1 Signal Uint16 rsvd5:1; // 24 Input Latch clear for CLB5_OUT4 Signal Uint16 rsvd6:1; // 25 Input Latch clear for CLB5_OUT5 Signal Uint16 rsvd7:1; // 26 Input Latch clear for CLB6_OUT4 Signal Uint16 rsvd8:1; // 27 Input Latch clear for CLB6_OUT5 Signal Uint16 ERRORSTS_ERROR:1; // 28 Input Latch clear for ERRORSTS_ERROR Signal Uint16 ECATSYNC0:1; // 29 Input Latch clear for ECATSYNC0 Signal Uint16 ECATSYNC1:1; // 30 Input Latch clear for ECATSYNC1 Signal Uint16 CLAHALT:1; // 31 Input Flag clear for CLAHALT Signal }; union XBARCLR4_REG { Uint32 all; struct XBARCLR4_BITS bit; }; struct XBAR_REGS { union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 union XBARFLG4_REG XBARFLG4; // X-Bar Input Flag Register 4 union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 union XBARCLR4_REG XBARCLR4; // X-Bar Input Flag Clear Register 4 }; //--------------------------------------------------------------------------- // XBAR External References & Function Declarations: // extern volatile struct XBAR_REGS XbarRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_xint.h // // TITLE: Definitions for the XINT registers. // //########################################################################### // $TI Release: F2838x Support Library v3.02.00.00 $ // $Release Date: Tue May 26 17:21:56 IST 2020 $ // $Copyright: // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### //--------------------------------------------------------------------------- // XINT Individual Register Bit Definitions: struct XINT1CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT1 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT1 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT1CR_REG { Uint16 all; struct XINT1CR_BITS bit; }; struct XINT2CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT2 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT2 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT2CR_REG { Uint16 all; struct XINT2CR_BITS bit; }; struct XINT3CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT3 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT3 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT3CR_REG { Uint16 all; struct XINT3CR_BITS bit; }; struct XINT4CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT4 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT4 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT4CR_REG { Uint16 all; struct XINT4CR_BITS bit; }; struct XINT5CR_BITS { // bits description Uint16 ENABLE:1; // 0 XINT5 Enable Uint16 rsvd1:1; // 1 Reserved Uint16 POLARITY:2; // 3:2 XINT5 Polarity Uint16 rsvd2:12; // 15:4 Reserved }; union XINT5CR_REG { Uint16 all; struct XINT5CR_BITS bit; }; struct XINT_REGS { union XINT1CR_REG XINT1CR; // XINT1 configuration register union XINT2CR_REG XINT2CR; // XINT2 configuration register union XINT3CR_REG XINT3CR; // XINT3 configuration register union XINT4CR_REG XINT4CR; // XINT4 configuration register union XINT5CR_REG XINT5CR; // XINT5 configuration register Uint16 rsvd1[3]; // Reserved Uint16 XINT1CTR; // XINT1 counter register Uint16 XINT2CTR; // XINT2 counter register Uint16 XINT3CTR; // XINT3 counter register }; //--------------------------------------------------------------------------- // XINT External References & Function Declarations: // extern volatile struct XINT_REGS XintRegs; //=========================================================================== // End of file. //=========================================================================== //########################################################################### // // FILE: f2838x_FPGA.h // // TITLE: External Interface Register Definitions. (XZCS0) // //########################################################################### // FPGA Region // define FPGA support bit of encoder type typedef struct { Uint16 InputData[0x10]; // 0x1040 (LSB is I00) Uint16 Reserved0[0x10]; // 0x1050 ~ 0x105F Uint16 OutputData[0x10]; // 0x1060 (LSB is O00) Uint16 Reserved1[0x10]; // 0x1070 ~ 0x107F } FPGA_EXTENT_IO_CH; typedef struct { Uint16 EnablePWM1; // 0x0070 Uint16 PWM1ONCount; // 0x0071 Uint16 PWM1OFFCount; // 0x0072 } FPGA_LASER_PWM_CH; typedef struct { Uint16 DIO_InputNum : 4; Uint16 DIO_OutputNum : 4; Uint16 EncPortNum : 4; Uint16 Reserved : 4; } FPGA_ID1; typedef struct { Uint16 IsSupGeneralCmd : 2; Uint16 PowerStageMCUTypeRead : 2; Uint16 LaserPWM_ModuleNum : 2; Uint16 ExtModuleNum : 2; Uint16 IsSup_M3IP : 1; Uint16 IsSupSTOInterface : 1; Uint16 Reserved : 6; } FPGA_ID2; typedef struct { int16 EncoderType; // 0x0080 int16 EncoderSupportType; // 0x0081 int16 EncBaurateDivider; // 0x0082 int16 Reserved1; int16 EncTimeoutCount1; // 0x0084 int16 EncTimeoutCount2; // 0x0085 int16 EncWaitReqDelay; // 0x0086 int16 DelaySwitchTime; // 0x0087 int16 EncCRCPolynomial; // 0x0088 int16 EncCRCInitValue; // 0x0089 int16 RxCmdExtractMask; // 0x008A int16 EncCtrlWord; // 0x008B int16 DMAAddrMap1; // 0x008C int16 DMAAddrMap2; // 0x008D int16 TxCmdExtractMask; // 0x008E int16 Reserved2; } FPGA_EncAttribute; typedef struct { FPGA_EncAttribute EncAttribute; // 0x0080 ~ 0x008F int32 QEP_AbsCounter; // 0x0090 int32 QEP_IndexCounter; // 0x0092 int16 QEP_Count; // 0x0094 int16 QEP_Status; // 0x0095 Uint16 QEP_Timer; // 0x0096 Uint16 QEP_InpAB_Change; // 0x0097 Uint16 QEP_ABZ_RawData; // 0x0098 int16 QEP_Reserved1[7]; int16 Reserved1[0x10]; // 0x00A0 ~ 0x00AF int16 Reserved2[0x10]; // 0x00B0 ~ 0x00BF int16 SyncUniEnc_TxControl; // 0x00C0 int16 SyncUniEnc_ReqDataLen; // 0x00C1 int16 SyncUniEnc_ResDataLen; // 0x00C2 int16 SyncUniEnc_RecoveryTimeCount; // 0x00C3 int16 SyncUniEnc_ReqMainCmd[0x02]; // 0x00C4 ~ 0x00C5 int16 SyncUniEnc_ReqArgData[0x02]; // 0x00C6 ~ 0x00C7 int16 SyncUniEnc_Reserved1[0x08]; // 0x00C8 ~ 0x00CF int16 SyncUniEnc_RxStatus; // 0x00D0 int16 SyncUniEnc_Reserved2[0x03]; // 0x00D1 ~ 0x00D3 int16 SyncUniEnc_MainFrameData[0x04]; // 0x00D4 ~ 0x00D7 int16 SyncUniEnc_AddFrame1Data[0x02]; // 0x00D8 ~ 0x00D9 int16 SyncUniEnc_AddFrame2Data[0x02]; // 0x00DA ~ 0x00DB int16 SyncUniEnc_Reserved3[0x03]; // 0x00DC ~ 0x00DE int16 SyncUniEnc_CRCCounter; // 0x00DF int16 UniEnc_TxControl; // 0x00E0 int16 UniEnc_TxData[0x0E]; // 0x00E1 ~ 0x00EE int16 UniEnc_Reserved1; // 0x00EF int16 UniEnc_RxStatus; // 0x00F0 int16 UniEnc_RxData[0x0D]; // 0x00F1 ~ 0x00FD int16 UniEnc_ModStat; // 0x00FE int16 UniEnc_CRCCounter; // 0x00FF } FPGA_ENC_CH; struct FPGA_REGS { int16 WDTBaseTime; // 0x0000 set Basetime = 160 -> WDT working rate = 160MHz/160 = 1MHz (Period = 1us) int16 WDTTimeCount; // 0x0001 set TimeCount = 2000 -> if 2000 base time clock without refresh then time out int16 WDTRefresh; // 0x0002 set Refresh = 0 -> refresh watch dog counter int16 WDTStatusRegister; // 0x0003 D15 : Watchdog timeout indicator. int16 WDTSelectField; // 0x0004 D15 : Enable watch dog timer, D14 : OE flag (control this flag without enable WDT) int16 Reserved1[0x0b]; int16 DriverControlIO; // 0x0010 int16 DriverStatusIO; // 0x0011 int16 EncPwrCtrl; // 0x0012 D0 : Front stage, D1 : Add-on card, 0:turn off, 1:turn on int16 Reserved2[0x01]; // 0x0013 int16 TestValue; // 0x0014 FPGA_ID1 ID1; // 0x0015 FPGA_ID2 ID2; // 0x0016 int16 FPGA_ID3; // 0x0017 int16 Reserved3[0x02]; int16 PhaseFailInfo; // 0x001A int16 PWMFrequencyDouble; // 0x001B Uint16 DI_SampleFactor; // 0x001C int16 WatchdogCounter; // 0x001D int32 FPGA_SWVersion; // 0x001E FF.FF.FF.FF 24~31: Major, 16~23: Minor, 8~15: Patch, 0~7: RC number int16 Reserved5[0x10]; int16 HMI_DipSwitch; // 0x0030 int16 HMI_SevenSegment1; // 0x0031 int16 HMI_SevenSegment2; // 0x0032 int16 HMI_SevenSegment3; // 0x0033 int16 HMI_SevenSegment4; // 0x0034 int16 HMI_SevenSegment5; // 0x0035 int16 Reserved6[0x0a]; int32 QEP_CommandCounter; // 0x0040 int16 QEP_CommandRawData; // 0x0042 int16 Reserved7[0x0d]; int16 PowerStageRawData; // 0x0050 int16 PowerStageIDReady; // 0x0051 int16 InvVerAndType; // 0x0052 int16 InvStructAndAxisNum; // 0x0053 int16 PIM_CurNorm; // 0x0054 int16 Reserved8; // 0x0055 int16 ModuleType; // 0x0056 int16 ModuleStruct; // 0x0057 int16 CurrentSensorRange; // 0x0058 int16 PWM_DeadTime; // 0x0059 int16 Module_CurPeak; // 0x005A int16 Module_CurNorm; // 0x005B int16 Reserved9[0x14]; // 0x005C ~ 0x006F FPGA_LASER_PWM_CH laser; // 0x0070 ~ 0x0072 int16 Reserved10[0x0d]; FPGA_ENC_CH encoder[9]; // 0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380, 0x0400, 0x0480 int16 Reserved11[0x208]; // 0x0500 ~ 0x0707 int16 I0RiseTimeTick; // 0x0708 int16 I0FallTimeTick; // 0x0709 int16 I0RiseHappen; // 0x070A int16 I0FallHappen; // 0x070B int16 I1RiseTimeTick; // 0x070C int16 I1FallTimeTick; // 0x070D int16 I1RiseHappen; // 0x070E int16 I1FallHappen; // 0x070F int16 DMA_Encoder[0x20]; // 0x0710 ~ 0x072F int16 Reserved12[0x8d0]; // 0x0730 ~ 0x0FFF int16 SyncDivider; // 0x1000 int16 SyncStatus; // 0x1001 int16 OptionBoardStatus; // 0x1002 int16 Reserved13[0x0d]; // 0x1003 ~ 0x100F int16 SSI_Chip_Select; // 0x1010 int16 Reserved14[0x2f]; // 0x1011 ~ 0x103F FPGA_EXTENT_IO_CH io[2]; // 0x1040 ~ 0x10BF }; extern volatile struct FPGA_REGS FPGARegs; //=========================================================================== // No more. //=========================================================================== // Define maximum supported axis and encoder number and slot number //#define MAX_CMPNT_NUM_FRONTSTAGE 6 // No use. FrontStage sup max component number=6 but DeviceInfo only sup 4 //#define MAX_CMPNT_NUM_EXTBOARD 6 // No use. ExtBoard sup max component number=6 but DeviceInfo only sup 4 //#define MAX_CMPNT_NUM_ADDONCARD 6 // No use. AddonCard sup max component number=6 but DeviceInfo only sup 4 // Define for M3 extended IO // Define for extended monitor for each encoder (current spedification is related to the axis number) // Define M3 maximum supported extend slave number // Define for axis and encoder number in execution for each CPU // two axial axes run in CPU1 // one axial and one spindle axes(with dual-feedback) run in CPU2 // Timer loop frequency (Hz) // MCU revision ID // // End of file. // /* ============================================================================== File Name: CommonVariables.h Description: This file defines variables that are commonly used in CPU1 and CPU2. These variables are put in the GsRAM owned by CPU1, so they are read-only for CPU2. The common variables are instanced within both CPUs (assigned value in CPU 1), and they are mapped to the same memory zone (via pragma instruction). ================================================================================= */ /* ================================================================================= File name: DMCTYPE.H Originator: Digital Control Systems Group Texas Instruments Description: DMC data type definition file. ===================================================================================== History: ------------------------------------------------------------------------------------- 04-15-2005 Version 3.20 ------------------------------------------------------------------------------*/ //--------------------------------------------------------------------------- // For Portability, User Is Recommended To Use Following Data Type Size // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: // //#define PI 3.14159265358979L, if higher accuracy is necessary, suffix L should be added. //define TWOPI 6.28318530717958L, if higher accuracy is necessary, suffix L should be added. // Version Number Coding // X.XX.XXrcXXX for development pre-release // X.XX.XX for final release, which release candidate number is zero. typedef struct { Uint32 EncUpdateTimeTick; int32 LastAbsCounter; int32 AbsCounter; int32 LastAbsCounterOri_E1; int32 AbsCounterOri_E1; int32 LastAbsCounterOri_E2; int32 AbsCounterOri_E2; } EncDelayTable; typedef struct { int16 MotionDirPolarity; float32 EncUpdateFreq; // Constant value, delay table update frequency. Unit: period / us float32 EncDelayTime; int16 EncTableIndex; int16 EnEnc1DelayTable; int16 EnEnc2DelayTable; EncDelayTable DelayTable[2]; } HostEncDelayTableVar; // Define for variables in CPU1 which will be referenced in CM // must allocate to CPU1toCM message RAM typedef struct { Uint16 IPCStatus; int16 HostCommType; int16 IsMechIsrPeriodErr; float32 TransCycleTime; HostEncDelayTableVar EncDelayTableVar[2]; int16 AxisControlType[2]; } CPU1RefVariablesCM; //=========================================================================== // No more. //=========================================================================== #pragma DATA_SECTION(CPU1RefVarCM,"CPU1RefVariableCMFiles"); #pragma RETAIN(CPU1RefVarCM); #pragma DATA_SECTION(Host_ServoRspCH_MasterCPU,"Host_CPU1ServoRspFiles"); #pragma RETAIN(Host_ServoRspCH_MasterCPU); //#pragma CODE_SECTION(multi_slv_exchange_sync, "ramfuncs"); #pragma DATA_SECTION(lnk_sbuff,"MIII_LnkSbuffFiles"); #pragma RETAIN(lnk_sbuff); #pragma DATA_SECTION(lnk_rbuff,"MIII_LnkRbuffFiles"); #pragma RETAIN(lnk_rbuff); #pragma DATA_SECTION(MIIIReceiveError1,"MIII_ReceiveErrorFiles"); #pragma RETAIN(MIIIReceiveError1); /* globals */ /* Buffer */ volatile Uint32 lnk_sbuff[ 11 + 1 ][ ( 60 >> 2 ) ]; /* Send Buffer */ volatile Uint32 lnk_rbuff[ 11 + 1 ][ ( 60 >> 2 ) ]; /* Receive Buffer */ typedef struct{ Uint16 commstat_syntec; Uint32 asic_ests; Uint32 commdata_not_rcv; Uint32 comm_enabled_st; } MIIIReceiveError; /* Error Status */ MIIIReceiveError MIIIReceiveError1; Uint32 Host_ServoRspCH_MasterCPU[2 * 56] = {0L}; CPU1RefVariablesCM CPU1RefVarCM;