//###########################################################################
//
// FILE:    hw_flash.h
//
// TITLE:   Definitions for the FLASH registers.
//
//###########################################################################
// $TI Release:  $
// $Release Date:  $
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//###########################################################################

#ifndef HW_FLASH_H
#define HW_FLASH_H

//*************************************************************************************************
//
// The following are defines for the FLASH register offsets
//
//*************************************************************************************************
#define FLASH_O_FRDCNTL         0x0U     // Flash Read Control Register
#define FLASH_O_FLPROT          0x4U     // Flash program/erase protect register
#define FLASH_O_FLCLKCTL        0x40U    // Flash NW clock control register.
#define FLASH_O_FRD_INTF_CTRL   0x180U   // Flash Read Interface Control Register

#define FLASH_O_ECC_ENABLE   0x0U    // ECC Enable
#define FLASH_O_FECC_CTRL    0x20U   // ECC Control


//*************************************************************************************************
//
// The following are defines for the bit fields in the FRDCNTL register
//
//*************************************************************************************************
#define FLASH_FRDCNTL_RWAIT_S           8U
#define FLASH_FRDCNTL_RWAIT_M           0xF00U       // Random Read Waitstate
#define FLASH_FRDCNTL_TRIMENGRRWAIT_S   24U
#define FLASH_FRDCNTL_TRIMENGRRWAIT_M   0xF000000U   // Random Read Waitstate of Trim and ENGR
                                                     // sectors.

//*************************************************************************************************
//
// The following are defines for the bit fields in the FLPROT register
//
//*************************************************************************************************
#define FLASH_FLPROT_FLWEPROT   0x1U   // Flash write/erase protect bit.

//*************************************************************************************************
//
// The following are defines for the bit fields in the FLCLKCTL register
//
//*************************************************************************************************
#define FLASH_FLCLKCTL_KDIV_S   0U
#define FLASH_FLCLKCTL_KDIV_M   0xFU   // KDIV value of MCLK divider.

//*************************************************************************************************
//
// The following are defines for the bit fields in the FRD_INTF_CTRL register
//
//*************************************************************************************************
#define FLASH_FRD_INTF_CTRL_PREFETCH_EN     0x1U   // Prefetch Enable
#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN   0x2U   // Data Cache Enable


//*************************************************************************************************
//
// The following are defines for the bit fields in the ECC_ENABLE register
//
//*************************************************************************************************
#define FLASH_ECC_ENABLE_ENABLE_S   0U
#define FLASH_ECC_ENABLE_ENABLE_M   0xFU   // Enable ECC

//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_CTRL register
//
//*************************************************************************************************
#define FLASH_FECC_CTRL_ECC_TEST_EN_S   0U
#define FLASH_FECC_CTRL_ECC_TEST_EN_M   0x3U   // Enable ECC Test Logic



#endif
