# EPG Module

The Embedded Pattern Generator (EPG) module is a customizable pattern and clock generator which could serve many test and application scenarios that require a simple pattern generator or a periodic clock generator. The EPG module can also be used to capture and incoming serial stream of data. EPG driver provides functions for independent clock generation and clock division

group `epg_api`

  Defines

  `EPG_GCTL0_EPGOUTSEL_S` 8U
  `EPG_GCTL0_EPGOUTSEL_M` 0xFF00U
  `EPG_GCTL3_EPGOUT_SIGOUTSEL_BIT_L` 4U
  `EPG_GCTL2_EPGOUT_CLKOUTSEL_BIT_L` 4U
  `EPG_GCTL1_SIGGEN_CLKSEL_BIT_L` 4U
  `EPG_CLKDIV_REG_OFF` 12U
  `EPG_SIGGEN_REG_OFF` 32U
  `EPG_CLKDIV_CLKOFFSET_BIT_L` 8U
  `EPG_INT_GLOBAL_INT` 0x1U

    Global Interrupt Flag.

    Interrupt Flags that can be passed to EPG_enableInterruptFlag(), EPG_diableInterruptFlag, EPG_forceInterruptFlag, EPG_clearInterruptFlag as intFlags parameter.

  `EPG_INT_SIGGEN0_DONE` 0x2U

    Signal Generator 0 Operation Done.

  `EPG_INT_SIGGEN0_FILL` 0x4U

    Signal Generator 0 Data Fill.

  `EPG_LOCK_REG_GCTL0` 0x1U

    GCTL0 Register.

    Register Flags that can be passed to EPG_releaseLockReg, EPG_LockReg, EPG_commitRegLock as regFlags parameter.

  `EPG_LOCK_REG_GCTL1` 0x2U

    GCTL1 Register.

  `EPG_LOCK_REG_GCTL2` 0x4U

    GCTL2 Register.

  `EPG_LOCK_REG_GCTL3` 0x8U

    GCTL3 Register.

  `EPG_LOCK_REG_CLKDIV0_CTL0` 0x10U

    CLK divider 0 CTL0 Register.

  `EPG_LOCK_REG_CLKDIV1_CTL0` 0x20U

    CLK divider 1 CTL0 Register.

  `EPG_LOCK_REG_SIGGEN0_CTL0` 0x40U

    Signal gen 0 CTL0 Register.

  `EPG_LOCK_REG_SIGGEN0_CTL1` 0x80U

    Signal gen 0 CTL1 Register.

  `EPG_MX_SEL_LOCK_REG_MXSEL0` 0x1U

    Mux Select 0 Register.

    Register Flags that can be passed to EPG_releaseLockMXSelReg, EPG_lockMXSelReg, EPG_commitMXSelRegLock as regFlags parameter.

  Enums

  enum `EPG_OutputSelect`

    Values that can be passed to EPG_selectGlobalOutput() as the gPinOutSel parameter.

    Values:

    enumerator `EPG_OUT_SEL_SIG` = 0x0U

      Signal Generator mux output.

    enumerator `EPG_OUT_SEL_CLK` = 0x1U

      Clock Generator mux output.

  enum `EPG_SignalGenOut`

    Values that can be passed to EPG_selectSignalOutput() as the sigGenOutput parameter.

    Values:

    enumerator `EPG_SIGGEN0_DATATRANOUT0` = 0x0U

      Signal Generator 0 Data Transform out 0.

    enumerator `EPG_SIGGEN0_DATATRANOUT1` = 0x1U

      Signal Generator 0 Data Transform out 1.

    enumerator `EPG_SIGGEN0_DATATRANOUT2` = 0x2U

      Signal Generator 0 Data Transform out 2.

    enumerator `EPG_SIGGEN0_DATATRANOUT3` = 0x3U

      Signal Generator 0 Data Transform out 3.

    enumerator `EPG_SIGGEN0_DATATRANOUT4` = 0x4U

      Signal Generator 0 Data Transform out 4.

    enumerator `EPG_SIGGEN0_DATATRANOUT5` = 0x5U

      Signal Generator 0 Data Transform out 5.

    enumerator `EPG_SIGGEN0_DATATRANOUT6` = 0x6U

      Signal Generator 0 Data Transform out 6.

    enumerator `EPG_SIGGEN0_DATATRANOUT7` = 0x7U

      Signal Generator 0 Data Transform out 7.

  enum `EPG_ClockGenOut`

    Values that can be passed to EPG_selectClkOutput() as the clkGenOutput parameter.

    Values:

    enumerator `EPG_CLKGEN0_CLKOUT0_DCLK` = 0x0U

      Clock Generator 0 Clk output 0 DCLK.

    enumerator `EPG_CLKGEN0_CLKOUT1_DCLK` = 0x1U

      Clock Generator 0 Clk output 1 DCLK.

    enumerator `EPG_CLKGEN0_CLKOUT2_DCLK` = 0x2U

      Clock Generator 0 Clk output 2 DCLK.

    enumerator `EPG_CLKGEN0_CLKOUT3_DCLK` = 0x3U

      Clock Generator 0 Clk output 3 DCLK.

    enumerator `EPG_CLKGEN1_CLKOUT0_DCLK` = 0x4U

      Clock Generator 1 Clk output 0 DCLK.

    enumerator `EPG_CLKGEN1_CLKOUT1_DCLK` = 0x5U

      Clock Generator 1 Clk output 1 DCLK.

    enumerator `EPG_CLKGEN1_CLKOUT2_DCLK` = 0x6U

      Clock Generator 1 Clk output 2 DCLK.

    enumerator `EPG_CLKGEN1_CLKOUT3_DCLK` = 0x7U

      Clock Generator 1 Clk output 3 DCLK.

  enum `EPG_ClockGenGclkOut`

    Values that can be passed to EPG_selectSigGenClkSource() as the clkGenOutput parameter.

    Values:

    enumerator `EPG_CLKGEN0_CLKOUT0_GCLK` = 0x0U

      Clock Generator 0 Clk output 0 GCLK.

    enumerator `EPG_CLKGEN0_CLKOUT1_GCLK` = 0x1U

      Clock Generator 0 Clk output 1 GCLK.

    enumerator `EPG_CLKGEN0_CLKOUT2_GCLK` = 0x2U

      Clock Generator 0 Clk output 2 GCLK.

    enumerator `EPG_CLKGEN0_CLKOUT3_GCLK` = 0x3U

      Clock Generator 0 Clk output 3 GCLK.

    enumerator `EPG_CLKGEN1_CLKOUT0_GCLK` = 0x4U

      Clock Generator 1 Clk output 0 GCLK.

    enumerator `EPG_CLKGEN1_CLKOUT1_GCLK` = 0x5U

      Clock Generator 1 Clk output 1 GCLK.

    enumerator `EPG_CLKGEN1_CLKOUT2_GCLK` = 0x6U

      Clock Generator 1 Clk output 2 GCLK.

    enumerator `EPG_CLKGEN1_CLKOUT3_GCLK` = 0x7U

      Clock Generator 1 Clk output 3 GCLK.

  enum `EPG_ClockStopEdge`

    Values that can be passed to EPG_setClkGenStopEdge(), as the stopEdge parameter.

    Values:

    enumerator `EPG_CLK_STOP_EDGE_CLKOUT0` = 0x000U

      Stop on Clk output 0.

    enumerator `EPG_CLK_STOP_EDGE_CLKOUT1` = 0x010U

      Stop on Clk output 1.

    enumerator `EPG_CLK_STOP_EDGE_CLKOUT2` = 0x100U

      Stop on Clk output 2.

    enumerator `EPG_CLK_STOP_EDGE_CLKOUT3` = 0x110U

      Stop on Clk output 3.

  enum `EPG_SignalGenMode`

    Values that can be passed to EPG_setSignalGenMode(), as the sigGenMode parameter.

    Values:

    enumerator `EPG_SIGGEN_MODE_BIT_BANG` = 0x0U

      BIT BANG MODE.

    enumerator `EPG_SIGGEN_MODE_SHIFT_RIGHT_ONCE` = 0x1U

      SHIFT RIGHT ONCE MODE.

    enumerator `EPG_SIGGEN_MODE_ROTATE_RIGHT_ONCE` = 0x2U

      ROTATE RIGHT ONCE MODE.

    enumerator `EPG_SIGGEN_MODE_ROTATE_RIGHT_REPEAT` = 0x3U

      ROTATE RIGHT REPEAT MODE.

    enumerator `EPG_SIGGEN_MODE_SHIFT_LEFT_ONCE` = 0x4U

      SHIFT LEFT ONCE MODE.

    enumerator `EPG_SIGGEN_MODE_ROTATE_LEFT_ONCE` = 0x5U

      ROTATE LEFT ONCE MODE.

    enumerator `EPG_SIGGEN_MODE_ROTATE_LEFT_REPEAT` = 0x6U

      ROTATE LEFT REPEAT.

    enumerator `EPG_SIGGEN_MODE_SHIFT_RIGHT_REPEAT` = 0x7U

      SHIFT RIGHT REPEAT MODE.

    enumerator `EPG_SIGGEN_MODE_SHIFT_LEFT_REPEAT` = 0x8U

      SHIGT LEFT REPEAT MODE.

  enum `EPG_SignalGenData0In`

    Values that can be passed to EPG_setData0In(), as the data0Input parameter.

    Values:

    enumerator `EPG_SIGGEN_DATA0_DATA_NEXT0` = 0x0U

      DATA TRANSFORM NEXT[0].

    enumerator `EPG_SIGGEN_DATA0_EPGIN0` = 0x1U

      EPG Input 0.

    enumerator `EPG_SIGGEN_DATA0_EPGIN1` = 0x2U

      EPG Input 1.

    enumerator `EPG_SIGGEN_DATA0_EPGIN2` = 0x3U

      EPG Input 2.

    enumerator `EPG_SIGGEN_DATA0_EPGIN3` = 0x4U

      EPG Input 3.

    enumerator `EPG_SIGGEN_DATA0_EPGIN4` = 0x5U

      EPG Input 4.

    enumerator `EPG_SIGGEN_DATA0_EPGIN5` = 0x6U

      EPG Input 5.

    enumerator `EPG_SIGGEN_DATA0_EPGIN6` = 0x7U

      EPG Input 6.

    enumerator `EPG_SIGGEN_DATA0_EPGIN7` = 0x8U

      EPG Input 7.

  enum `EPG_SignalGenData63In`

    Values that can be passed to EPG_setData63In(), as the data63Input parameter.

    Values:

    enumerator `EPG_SIGGEN_DATA63_DATA_NEXT63` = 0x0U

      DATA TRANSFORM NEXT[63].

    enumerator `EPG_SIGGEN_DATA63_EPGIN0` = 0x1U

      EPG Input 0.

    enumerator `EPG_SIGGEN_DATA63_EPGIN1` = 0x2U

      EPG Input 1.

    enumerator `EPG_SIGGEN_DATA63_EPGIN2` = 0x3U

      EPG Input 2.

    enumerator `EPG_SIGGEN_DATA63_EPGIN3` = 0x4U

      EPG Input 3.

    enumerator `EPG_SIGGEN_DATA63_EPGIN4` = 0x5U

      EPG Input 4.

    enumerator `EPG_SIGGEN_DATA63_EPGIN5` = 0x6U

      EPG Input 5.

    enumerator `EPG_SIGGEN_DATA63_EPGIN6` = 0x7U

      EPG Input 6.

    enumerator `EPG_SIGGEN_DATA63_EPGIN7` = 0x8U

      EPG Input 7.

  enum `EPG_OUT`

    Values that can be passed to EPG_selectEPGOutput(), EPG_selectClkOutput, EPG_selectSignalOutput as the gPinNum parameter.

    Values:

    enumerator `EPG_OUT0` = 0x0U

      EPG Output 0.

    enumerator `EPG_OUT1` = 0x1U

      EPG Output 1.

    enumerator `EPG_OUT2` = 0x2U

      EPG Output 2.

    enumerator `EPG_OUT3` = 0x3U

      EPG Output 3.

    enumerator `EPG_OUT4` = 0x4U

      EPG Output 4.

    enumerator `EPG_OUT5` = 0x5U

      EPG Output 5.

    enumerator `EPG_OUT6` = 0x6U

      EPG Output 6.

  enum `EPG_SIGGEN`

    Values that can be used for sigGenNum parameter.

    Values:

    enumerator `EPG_SIGGEN0` = 0x0U

      Signal Generator 0.

    enumerator `EPG_SIGGEN1` = 0x1U

      Signal Generator 1.

  enum `EPG_CLKGEN`

    Values that can be used for clkGenNum parameter.

    Values:

    enumerator `EPG_CLKGEN0` = 0x0U

      Clock Generator 0.

    enumerator `EPG_CLKGEN1` = 0x1U
  enum `EPG_DataIn`

    Values that can be passed to EPG_selectEPGDataOut(), as the dataIn parameter.

    Values:

    enumerator `EPG_DATAIN_CANARX` = 0

      CANA Receive input (RX)

    enumerator `EPG_DATAIN_MCANARX` = 1

      MCANA Receive input (RX)

    enumerator `EPG_DATAIN_LINARX` = 2

      LINA Receive input (RX)

    enumerator `EPG_DATAIN_LINBRX` = 3

      LINB Receive input (RX)

    enumerator `EPG_DATAIN_FSIAD0RX` = 4

      FSIA D0 Receive Input (RX)

    enumerator `EPG_DATAIN_FSIAD1RX` = 5

      FSIA D1 Receive Input (RX)

    enumerator `EPG_DATAIN_FSIBD0RX` = 6

      FSIB D0 Receive Input (RX)

    enumerator `EPG_DATAIN_FSIBD1RX` = 7

      FSIB D1 Receive Input (RX)

    enumerator `EPG_DATAIN_FSIARX_CLK` = 8

      FSIA Receive Clock Input Signal.

    enumerator `EPG_DATAIN_SPIA_CLK` = 9

      SPIA Clock Signal.

    enumerator `EPG_DATAIN_SPIA_PICO` = 10

      SPIA Peripheral in Controller out Signal.

    enumerator `EPG_DATAIN_SPIA_POCI` = 11

      SPIA Peripheral out Controller in Signal.

    enumerator `EPG_DATAIN_SPIA_PTE` = 12

      SPIA Peripheral Transmit Enable Signal.

    enumerator `EPG_DATAIN_SPIB_CLK` = 13

      SPIB Clock Signal.

    enumerator `EPG_DATAIN_SPIB_PICO` = 14

      SPIB Peripheral in COntroller out Signal.

    enumerator `EPG_DATAIN_SPIB_POCI` = 15

      SPIB Peripheral out Controller in Signal.

    enumerator `EPG_DATAIN_SPIB_PTE` = 16

      SPIB Peripheral Transmit Enable Signal.

    enumerator `EPG_DATAIN_I2CA_SDA` = 17

      I2CA Serial Data Line.

    enumerator `EPG_DATAIN_I2CA_SCL` = 18

      I2CA Serial Clock Line.

    enumerator `EPG_DATAIN_I2CB_SDA` = 19

      I2CB Serial Data Line.

    enumerator `EPG_DATAIN_I2CB_SCL` = 20

      I2CB Serial Clock Line.

    enumerator `EPG_DATAIN_SDC1` = 21

      SDFM C1 Input.

    enumerator `EPG_DATAIN_SDC2` = 22

      SDFM C2 Input.

    enumerator `EPG_DATAIN_SDC3` = 23

      SDFM C3 Input.

    enumerator `EPG_DATAIN_SDC4` = 24

      SDFM C4 Input.

    enumerator `EPG_DATAIN_SDC5` = 25

      SDFM C5 Input.

    enumerator `EPG_DATAIN_SDC6` = 26

      SDFM C6 Input.

    enumerator `EPG_DATAIN_SDC7` = 27

      SDFM C7 Input.

    enumerator `EPG_DATAIN_SDC8` = 28

      SDFM C8 Input.

    enumerator `EPG_DATAIN_SDC9` = 29

      SDFM C9 Input.

    enumerator `EPG_DATAIN_SDC10` = 30

      SDFM C10 Input.

    enumerator `EPG_DATAIN_SDC11` = 31

      SDFM C11 Input.

    enumerator `EPG_DATAIN_SDC12` = 32

      SDFM C12 Input.

    enumerator `EPG_DATAIN_SDC13` = 33

      SDFM C13 Input.

    enumerator `EPG_DATAIN_SDC14` = 34

      SDFM C14 Input.

    enumerator `EPG_DATAIN_SDC15` = 35

      SDFM C15 Input.

    enumerator `EPG_DATAIN_SDC16` = 36

      SDFM C16 Input.

    enumerator `EPG_DATAIN_SCIARX` = 37

      SCIA Receive input (RX)

    enumerator `EPG_DATAIN_SCIBRX` = 38

      SCIB Receive input (RX)

    enumerator `EPG_DATAIN_EQEP1A` = 39

      EQEP1 Signal A.

    enumerator `EPG_DATAIN_EQEP1B` = 40

      EQEP1 Signal B.

    enumerator `EPG_DATAIN_EQEP1I` = 41

      EQEP1 Index signal.

    enumerator `EPG_DATAIN_EQEP1S` = 42

      EQEP1 Strobe input.

    enumerator `EPG_DATAIN_EQEP2A` = 43

      EQEP2 Signal A.

    enumerator `EPG_DATAIN_EQEP2B` = 44

      EQEP2 Signal B.

    enumerator `EPG_DATAIN_EQEP2I` = 45

      EQEP1 Index signal.

    enumerator `EPG_DATAIN_EQEP2S` = 46

      EQEP1 Strobe input.

    enumerator `EPG_DATAIN_FSICRX_CLK` = 47

      FSIC Receive Clock Input Signal.

    enumerator `EPG_DATAIN_FSICD0RX` = 48

      FSIC D0 Receive Input (RX)

    enumerator `EPG_DATAIN_FSICD1RX` = 49

      FSIC D1 Receive Input (RX)

    enumerator `EPG_DATAIN_FSIBRX_CLK` = 50

      FSIB Receive Clock Input Signal.

    enumerator `EPG_DATAIN_UART0RX` = 51

      UART0 Receive input (RX)

    enumerator `EPG_DATAIN_UART1RX` = 52

      UART1 Receive input (RX)

    enumerator `EPG_DATAIN_ECAP1` = 53

      ECAP 1 Input.

    enumerator `EPG_DATAIN_ECAP2` = 54

      ECAP 2 Input.

    enumerator `EPG_DATAIN_ECAP3` = 55

      ECAP 3 Input.

    enumerator `EPG_DATAIN_ECAP4` = 56

      ECAP 4 Input.

    enumerator `EPG_DATAIN_ECAP5` = 57

      ECAP 5 Input.

    enumerator `EPG_DATAIN_ECAP6` = 58

      ECAP 6 Input.

    enumerator `EPG_DATAIN_ECAP7` = 59

      ECAP 7 Input.

    enumerator `EPG_DATAIN_MCANBRX` = 63

      MCANB Receive input (RX)

  enum `EPG_DataOutSel`

    Values that can be passed to EPG_selectEPGDataOut(), as the dataOutSel parameter.

    Values:

    enumerator `EPG_DATAOUT_DATAIN` = 0x0U

      Input Data.

    enumerator `EPG_DATAOUT_EPGOUT` = 0x1U

      EPG output.

  Functions

  void `EPG_enableGlobal`(uint32_t base)

    Enable EPG and starts signal and clock generator

    This function enables the EPG module and starts signal and clock generator.

    Parameters

      - `base`: is the base address of the EPG module.

    Return

      None.

  void `EPG_disableGlobal`(uint32_t base)

    Disable EPG and stops signal and clock generator

    This function disables the EPG module and stops signal and clock generator.

    Parameters

      - `base`: is the base address of the EPG module.

    Return

      None.

  void `EPG_selectEPGOutput`(uint32_t base, EPG_OUT gPinNum, EPG_OutputSelect gPinOutSel)

    Select the EPG output source

    This function selects the global EPG output source to be clock or signal. This output can then be routed to any GPIO through xbar, mux sel.

    Parameters

      - `base`: is the base address of the EPG module.

      - `gPinNum`: is the global EPG Output number.

      - `gPinOutSel`: is the mux output of the gPinNum.

    The gPinNum can take any of EPG_OUTX. The gPinOutSel can take any of the EPG_OUT_SEL_CLK, EPG_OUT_SEL_SIG values.

    Return

      None.

  void `EPG_selectSignalOutput`(uint32_t base, EPG_OUT gPinNum, EPG_SignalGenOut sigGenOutput)

    Select the individual EPG pin signal data output

    This function selects the individual EPG pin’s signal generator data output. This output can then be routed to EPG global output by selecting signal generator as source for that pin.

    Parameters

      - `base`: is the base address of the EPG module.

      - `gPinNum`: is the global EPG Output number.

      - `sigGenOutput`: is the mux output of the gPinNum signal generators data output.

    The gPinNum can take any of EPG_OUTX. The sigGenOutput can take any of the EPG_SIG_GEN0_DATATRANX values where X is a number from 0 to 7 specifying which data ouput of sig gen to be used.

    Return

      None.

  void `EPG_selectClkOutput`(uint32_t base, EPG_OUT gPinNum, EPG_ClockGenOut clkGenOutput)

    Select the individual EPG pin clock data output

    This function selects the individual EPG pin’s clock generator data output. This output can then be routed to EPG global output by selecting clock generator as source for that pin.

    Parameters

      - `base`: is the base address of the EPG module.

      - `gPinNum`: is the global EPG Output number.

      - `clkGenOutput`: is the mux output of the gPinNum clock generator’s data output.

    The gPinNum can take any of EPG_OUTX. The clkGenOutput can take any of the EPG_CLK_GENY_CLKOUTX_DCLK values where X is a number from 0 to 3 specifying which data ouput of clock gen and Y can be 0 or 1 specifying which clock generator to be used to be used

    Return

      None.

  void `EPG_selectSigGenClkSource`(uint32_t base, EPG_SIGGEN sigGenNum, EPG_ClockGenGclkOut clkGenOutput)

    Select the signal generator’s clock source

    This function selects the signal generator’s clock source. This clock source is used to generate the periodic or aperiodic signals by the signal generator.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number whose clk source is being configured based on the availability.

      - `clkGenOutput`: is the mux output of the clock generator’s data output to be selected as source.

    The sigGenNum can take value of 0. The clkGenOutput can take any of the EPG_CLK_GENY_CLKOUTX_DCLK values where X is a number from 0 to 3 specifying which data ouput of clock gen to be used and Y can be 0 or 1 specifying which clock generator to be used

    Return

      None.

  void `EPG_setClkGenPeriod`(uint32_t base, EPG_CLKGEN clkGenNum, uint32_t periodValue)

    Set the clock generator period

    This function Sets the clock generator’s period Clock divider counter counts up to

    periodValue and snaps back to 0.
    Parameters

      - `base`: is the base address of the EPG module.

      - `clkGenNum`: is the clock generator number whose period is being set.

      - `periodValue`: is the period value in number of system clk cycles

    The clkGenNum can take values from 0 to 1 inclusive. The periodValue can take a maximum value of EPG_CLKDIV0_CTL0_PRD_M.

    Return

      None.

  void `EPG_setClkGenStopEdge`(uint32_t base, EPG_CLKGEN clkGenNum, EPG_ClockStopEdge stopEdge)

    Set the clock generator stop value

    This function Sets the clock generator’s stop value This Determines on which of the CLKOUTs edge clock generation is stopped following a clear of SIGGEN1_CTL0.EN.

    Parameters

      - `base`: is the base address of the EPG module.

      - `clkGenNum`: is the clock generator number which is being configured.

      - `stopEdge`: is the Edge signal at which clock stops.

    The clkGenNum can take values from 0 to 1 inclusive. The stopEdge can take any of EPG_CLK_STOP_EDGE_CLKOUTX value where X signifies the clock out number varying from 0 to 3 inclusive

    Return

      None.

  void `EPG_setClkGenOffset`(uint32_t base, EPG_CLKGEN clkGenNum, uint32_t clkGenOutputNum, uint32_t offsetValue)

    Set the clock generator clock offset

    This function Sets the clock generator output’s offset. This Determines number of source clock cycles by which the divided clock output is delayed.

    Parameters

      - `base`: is the base address of the EPG module.

      - `clkGenNum`: is the clock generator number which is being configured.

      - `clkGenOutputNum`: is the output number of particular clock generator whose offset is being set.

      - `offsetValue`: is the offset value in number of system clk cycles

    The clkGenNum can take values from 0 to 1 inclusive. The clkGenOutputNum can take values from 0 to 3 inclusive. The offsetValue can take a maximum value of EPG_CLKDIV0_CLKOFFSET_CLK0OFFSET_M.

    Return

      None.

  void `EPG_enableSignalGen`(uint32_t base, EPG_SIGGEN sigGenNum)

    Enable EPG signal generator

    This function enables the Signal generator after which the signal generator functions as per the mode definition.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is enabled.

    The sigGenNum can take value of 0.

    Return

      None.

  void `EPG_disableSignalGen`(uint32_t base, EPG_SIGGEN sigGenNum)

    Disable EPG signal generator

    This function Disables the Signal generator and stops its operation.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is disabled.

    The sigGenNum can take value of 0.

    Return

      None.

  void `EPG_setSignalGenMode`(uint32_t base, EPG_SIGGEN sigGenNum, EPG_SignalGenMode sigGenMode)

    Set EPG signal generator Mode

    This function Sets the EPG signal generator’s Mode. This mode effects the operation of the signal generator on the DATA input.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

      - `sigGenMode`: is the Signal generator mode being set.

    The sigGenNum can take value of 0. The sigGenMode can take any of the EPG_SIGGEN_MODE_BIT_BANG, EPG_SIGGEN_MODE_SHIFT_RIGHT_ONCE, EPG_SIGGEN_MODE_ROTATE_RIGHT_ONCE, EPG_SIGGEN_MODE_ROTATE_RIGHT_REPEAT, EPG_SIGGEN_MODE_SHIFT_LEFT_ONCE, EPG_SIGGEN_MODE_ROTATE_LEFT_ONCE, EPG_SIGGEN_MODE_ROTATE_LEFT_REPEAT, EPG_SIGGEN_MODE_SHIFT_RIGHT_REPEAT, EPG_SIGGEN_MODE_SHIFT_LEFT_REPEAT values.

    Return

      None.

  void `EPG_enableBitRevOnDataIn`(uint32_t base, EPG_SIGGEN sigGenNum)

    Perform bit reversal on input of signal generator

    This function set’s signal generator to Perform bit reversal on input. This results in bit reversal on data input of data transform block.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

    The sigGenNum can take value of 0.

    Return

      None.

  void `EPG_disableBitRevOnDataIn`(uint32_t base, EPG_SIGGEN sigGenNum)

    Disable bit reversal on input of signal generator

    This function set’s signal generator to disable bit reversal on input. This results in no bit reversal on data input of data transform block.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

    The sigGenNum can take value of 0.

    Return

      None.

  void `EPG_enableBitRevOnDataOut`(uint32_t base, EPG_SIGGEN sigGenNum)

    Perform bit reversal on output of signal generator

    This function set’s signal generator to Perform bit reversal on output. This results in bit reversal on data output of data transform block.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

    The sigGenNum can take value of 0.

    Return

      None.

  void `EPG_disableBitRevOnDataOut`(uint32_t base, EPG_SIGGEN sigGenNum)

    Disable bit reversal on output of signal generator

    This function set’s signal generator to disable bit reversal on output. This results in no bit reversal on data output of data transform block.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

    The sigGenNum can take value of 0.

    Return

      None.

  void `EPG_setDataBitLen`(uint32_t base, EPG_SIGGEN sigGenNum, uint32_t bitLength)

    Set EPG signal generators data bit length

    This function Sets EPG signal generators data bit length. This defines the number bits which participates in the shift rotate operations.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

      - `bitLength`: is the number of bits of the signal generator input data.

    The sigGenNum can take value of 0. The bitLength can have a maximum value of 64.

    Return

      None.

  void `EPG_setData0In`(uint32_t base, EPG_SIGGEN sigGenNum, EPG_SignalGenData0In data0Input)

    Set EPG signal generator data bit 0 input

    This function Sets EPG signal generator data bit 0 input. This provides the ability to capture the data.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

      - `data0Input`: is the source input of bit 0 of Data Register.

    The sigGenNum can take value of 0. The data0Input can take any of the EPG_SIGGEN_DATA0_DATA_NEXT0, EPG_SIGGEN_DATA0_EPGINX values where X can be from 0 to 7 which signifies signal input to the EPG.

    Return

      None.

  void `EPG_setData63In`(uint32_t base, EPG_SIGGEN sigGenNum, EPG_SignalGenData63In data63Input)

    Set EPG signal generator data bit 63 input

    This function Sets EPG signal generator data bit 63 input. This provides the ability to capture the data.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

      - `data0Input`: is the source input of bit 63 of Data Register.

    The sigGenNum can take value of 0. The data63Input can take any of the EPG_SIGGEN_DATA63_DATA_NEXT63, EPG_SIGGEN_DATA63_EPGINX values where X can be from 0 to 7 which signifies signal input to the EPG.

    Return

      None.

  void `EPG_setData0Word`(uint32_t base, EPG_SIGGEN sigGenNum, uint32_t data0)

    Write EPG signal generator data 0 [0:31] input

    This function Writes EPG signal generator data 0 [0:31] input. This is the Data used in signal bit stream.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

      - `data0`: is the first 32 bits of Data Register.

    The sigGenNum can take value of 0. The data0 can take any 32 bit value.

    Return

      None.

  void `EPG_setData1Word`(uint32_t base, EPG_SIGGEN sigGenNum, uint32_t data1)

    Write EPG signal generator data 1 [32:63] input

    This function Writes EPG signal generator data 1 [32:63] input. This is the Data used in signal bit stream.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

      - `data0`: is the last 32 bits of 63 bit Data Register.

    The sigGenNum can take value of 0. The data1 can take any 32 bit value.

    Return

      None.

  uint32_t `EPG_getData0ActiveReg`(uint32_t base, EPG_SIGGEN sigGenNum)

    Get EPG signal generator data 0 active register [0:31] value

    This function Reads EPG signal generator data 0 active [0:31] value which is the Data resulted from the transformation.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

    The sigGenNum can take value of 0.

    Return

      Returns the Data 0 Active register value.

  uint32_t `EPG_getData1ActiveReg`(uint32_t base, EPG_SIGGEN sigGenNum)

    Get EPG signal generator data 1 active register [32:64] value

    This function Reads EPG signal generator data 1 active [32:64] value which is the Data resulted from the transformation.

    Parameters

      - `base`: is the base address of the EPG module.

      - `sigGenNum`: is the Signal generator number which is beign configured.

    The sigGenNum can take value of 0.

    Return

      Returns the Data 1 Active register value.

  void `EPG_enableInterruptFlag`(uint32_t base, uint32_t intFlags)

    Enable the EPG interrupt sources

    This function enables the indicated EPG interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt. Disabled sources have no effect on the processor.

    Parameters

      - `base`: is the base address of the EPG module.

      - `intFlags`: is a bit mask of the interrupt sources to be enabled.

    The intFlags parameter can be any of the EPG_INT_GLOBAL_INT, EPG_INT_SIGGEN0_DONE, or EPG_INT_SIGGEN0_FILL values.

    Return

      None.

  void `EPG_disableInterruptFlag`(uint32_t base, uint32_t intFlags)

    Disables the EPG interrupt sources

    This function enables the indicated EPG interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt. Disabled sources have no effect on the processor.

    Parameters

      - `base`: is the base address of the EPG module.

      - `intFlags`: is a bit mask of the interrupt sources to be disabled.

    The intFlags parameter can be any of the EPG_INT_GLOBAL_INT, EPG_INT_SIGGEN0_DONE, or EPG_INT_SIGGEN0_FILL values.

    Return

      None.

  uint32_t `EPG_getInterruptStatus`(uint32_t base)

    Get the EPG interrupt sources

    This function returns the EPG interrupt sources that are active.

    Parameters

      - `base`: is the base address of the EPG module.

    Return

      Returns the bit mask of the interrupt sources which are currently triggered.

  void `EPG_clearInterruptFlag`(uint32_t base, uint32_t intFlags)

    Clear EPG Interrupt Sources

    This function clears the indicated EPG interrupt sources if pending.

    Parameters

      - `base`: is the base address of the EPG module.

      - `intFlags`: is a bit mask of the interrupt sources to be clear.

    The intFlags parameter can be any of the EPG_INT_GLOBAL_INT, EPG_INT_SIGGEN0_DONE, or EPG_INT_SIGGEN0_FILL values.

    Return

      None.

  void `EPG_forceInterruptFlag`(uint32_t base, uint32_t intFlags)

    Force EPG Interrupt Sources

    This function triggers the indicated EPG interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt. Disabled sources have no effect on the processor.

    Parameters

      - `base`: is the base address of the EPG module.

      - `intFlags`: is a bit mask of the interrupt sources to be trigger.

    The intFlags parameter can be any of the EPG_INT_GLOBAL_INT, EPG_INT_SIGGEN0_DONE, or EPG_INT_SIGGEN0_FILL values.

    Return

      None.

  void `EPG_lockReg`(uint32_t base, uint32_t regFlags)

    Lock EPG Register

    This function Locks EPG Register from being written further.

    Parameters

      - `base`: is the base address of the EPG module.

      - `regFlags`: is a bit mask of the EPG registers that need to locked.

    The regFlags parameter can be any of the EPG_LOCK_REG_GCTL0, EPG_LOCK_REG_GCTL1, EPG_LOCK_REG_GCTL2 EPG_LOCK_REG_GCTL3, EPG_LOCK_REG_CLKDIV0_CTL0, EPG_LOCK_REG_CLKDIV1_CTL0, EPG_LOCK_REG_SIGGEN0_CTL0, EPG_LOCK_REG_SIGGEN0_CTL1 values.

    Return

      None.

  void `EPG_releaseLockReg`(uint32_t base, uint32_t regFlags)

    Release Locks of EPG Register

    This function Releases Locks of EPG Register so they can be overwritten.

    Parameters

      - `base`: is the base address of the EPG module.

      - `regFlags`: is a bit mask of EPG registers whose lock to be released.

    The regFlags parameter can be any of the EPG_LOCK_REG_GCTL0, EPG_LOCK_REG_GCTL1, EPG_LOCK_REG_GCTL2 EPG_LOCK_REG_GCTL3, EPG_LOCK_REG_CLKDIV0_CTL0, EPG_LOCK_REG_CLKDIV1_CTL0, EPG_LOCK_REG_SIGGEN0_CTL0, EPG_LOCK_REG_SIGGEN0_CTL1 values.

    Return

      None.

  void `EPG_commitRegLock`(uint32_t base, uint32_t regFlags)

    Commit EPG registers Lock

    This function Commits Locks of EPG lock register so that the EPG locks cannot be removed.

    Parameters

      - `base`: is the base address of the EPG module.

      - `regFlags`: is a bit mask of EPG registers whose locks to be commited.

    The regFlags parameter can be any of the EPG_LOCK_REG_GCTL0, EPG_LOCK_REG_GCTL1, EPG_LOCK_REG_GCTL2 EPG_LOCK_REG_GCTL3, EPG_LOCK_REG_CLKDIV0_CTL0, EPG_LOCK_REG_CLKDIV1_CTL0, EPG_LOCK_REG_SIGGEN0_CTL0, EPG_LOCK_REG_SIGGEN0_CTL1 values.

    Return

      None.

  void `EPG_lockMXSelReg`(uint32_t muxbase, uint32_t regFlags)

    Lock EPG Mux Select Register

    This function Locks EPG Mux Select Register from being written further.

    Parameters

      - `muxbase`: is the base address of the EPG Mux module.

      - `regFlags`: is a bit mask of the EPG Mux Select registers.

    The regFlags parameter can be of the EPG_MX_SEL_LOCK_REG_MXSEL0

    Return

      None.

  void `EPG_releaseLockMXSelReg`(uint32_t muxbase, uint32_t regFlags)

    Release Locks of EPG Mux Select Register

    This function Releases Locks of EPG Mux Sel Registers to allow overwriting the registers.

    Parameters

      - `muxbase`: is the base address of the EPG Mux module.

      - `regFlags`: is a bit mask of the EPG Mux Select registers.

    The regFlags parameter can be of the EPG_MX_SEL_LOCK_REG_MXSEL0

    Return

      None.

  void `EPG_commitMXSelRegLock`(uint32_t muxbase, uint32_t regFlags)

    Commit EPG Mux Select Registers Lock

    This function Commits the Locks of EPG Mux Sel Registers so that the locks cannot be updated further.

    Parameters

      - `muxbase`: is the base address of the EPG Mux module.

      - `regFlags`: is a bit mask of the EPG Mux Select registers.

    The regFlags parameter can be of the EPG_MX_SEL_LOCK_REG_MXSEL0

    Return

      None.

  void `EPG_selectEPGDataOut`(uint32_t muxbase, EPG_DataIn dataIn, EPG_DataOutSel dataOutSel)

    Select EPG Data Output

    This function selects EPG Modules’s Final Data Output which can be used to feed EPG outputs to inputs of certain IPs or bypass the IP’s input as is.

    Parameters

      - `muxbase`: is the base address of the EPG MUX module.

      - `dataIn`: is the bit of EPG Data Input to be configured.

      - `dataOutSel`: is the source of dataOutBit to configure.

    The dataIn can take EPG_DATAIN. The dataOutSel can take any of the EPG_DATA_OUT_DATA_IN, EPG_DATA_OUT_EPG_OUT values.

    Return

      None.

The code for this module is contained in driverlib/epg.c, with driverlib/epg.h containing the API declarations for use by applications.