SYSCTL Module¶

System Control (SysCtl) determines the overall operation of the device. The API provides functions to configure the clocking of the device, the set of peripherals that are enabled, the windowed watchdog, the NMI watchdog, and low-power modes. It also provides functions to handle and obtain information about resets and missing clock detection failures.

group sysctl_api

Defines

SYSCTL_CLKSRCCTL_DELAY asm(" RPT #250 || NOP \n RPT #50 || NOP")¶

SYSCTL_REGWRITE_DELAY asm(" RPT #69 || NOP")¶

SYSCTL_WD_CHKBITS 0x0028U¶

SYSCTL_WD_ENRSTKEY 0x0055U¶

SYSCTL_WD_RSTKEY 0x00AAU¶

SYSCTL_PERIPH_REG_M 0x001FU¶

SYSCTL_PERIPH_REG_S 0x0000U¶

SYSCTL_PERIPH_BIT_M 0x1F00U¶

SYSCTL_PERIPH_BIT_S 0x0008U¶

SYSCTL_REG_KEY 0xA5A50000U¶

SYSCTL_PLL_KEY 0XCAFE0000U¶

SYSCTL_ETHERCATCLKCTL_DIVSRCSEL_S 0x0U¶

SYSCTL_ETHERCATCLKCTL_PHYCLKEN_S 0x8U¶

SYSCTL_CLBCLKCTL_TILECLKDIV_S 0x4U¶

SYSCTL_TYPE_LOCK_S 0xFU¶

SYSCTL_LPM_IDLE 0x0000U¶

SYSCTL_LPM_STANDBY 0x0001U¶

SYSCTL_LPM_HALT 0x0002U¶

SYSCTL_CPUSEL_DAC_S 0x10U¶

SYSCTL_DEFAULT_OSC_FREQ 10000000U¶

SYSCTL_BOOT_ROM_STATUS 0x0002U¶

SYSCTL_BOOT_ROM_POR 0x2000U¶

SYSCTL_BOOT_ROM_XRS 0x1000U¶

Device_cal ((void (*)(void))((uintptr_t)0x003faae3))¶

SYSCTL_SYSDIV_M 0x00007F00UL¶

SYSCTL_SYSDIV_S 8U¶

SYSCTL_REFDIV_M 0x007C0000UL¶

SYSCTL_REFDIV_S 18U¶

SYSCTL_ODIV_M 0x0F800000UL¶

SYSCTL_ODIV_S 23U¶

SYSCTL_REFDIV(x) ((((uint32_t)(x) - 1U) << SYSCTL_REFDIV_S ) & \ SYSCTL_REFDIV_M)¶: Macro to format Clock divider value. x is a number from 1 to 32.

SYSCTL_ODIV(x) ((((uint32_t)(x) - 1U) << SYSCTL_ODIV_S ) & \ SYSCTL_ODIV_M)¶: Macro to format Clock divider value. x is a number from 1 to 32.

SYSCTL_SYSDIV(x) ((x << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M)¶: Macro to format system clock divider value. x must be values from 1 to 126.

SYSCTL_IMULT_M 0x000000FFUL¶

SYSCTL_IMULT_S 0U¶

SYSCTL_IMULT(x) (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M)¶: Macro to format integer multiplier value. x is a number from 1 to 127.

SYSCTL_DCC_BASE_M 0x30000000UL¶

SYSCTL_DCC_BASE_S 28U¶

SYSCTL_DCC_BASE_0 0x00000000UL¶: DCC0 module.

SYSCTL_DCC_BASE_1 0x10000000UL¶: DCC1 module.

SYSCTL_DCC_BASE_2 0x20000000UL¶: DCC2 module.

SYSCTL_OSCSRC_M 0x00030000UL¶

SYSCTL_OSCSRC_S 16U¶

SYSCTL_OSCSRC_OSC2 0x00000000UL¶: Internal oscillator INTOSC2.

SYSCTL_OSCSRC_XTAL 0x00010000U¶: External oscillator (XTAL) in crystal mode.

SYSCTL_OSCSRC_XTAL_SE 0x00030000U¶: External oscillator (XTAL) in single-ended mode.

SYSCTL_OSCSRC_OSC1 0x00020000UL¶: Internal oscillator INTOSC1.

SYSCTL_PLL_ENABLE 0x80000000U¶: Enable PLL.

SYSCTL_PLL_DISABLE 0x00000000U¶: Disable PLL.

SYSCTL_PLL_BYPASS 0x40000000U¶: Bypass PLL.

SYSCTL_PLL_CONFIG_M 0xC0000000U¶

SYSCTL_PLL_RETRIES 100U¶

SYSCTL_PLLLOCK_TIMEOUT 2000U¶

SYSCTL_DCC_COUNTER0_TOLERANCE 1U¶

SYSCTL_DCC_COUNTER0_WINDOW 1000U¶

SYSCTL_AUXPLL_DIV_1 0x00000000U¶: Auxiliary PLL divide by 1.

SYSCTL_AUXPLL_DIV_2 0x00000100U¶: Auxiliary PLL divide by 2.

SYSCTL_AUXPLL_DIV_4 0x00000200U¶: Auxiliary PLL divide by 4.

SYSCTL_AUXPLL_DIV_8 0x00000300U¶: Auxiliary PLL divide by 8.

SYSCTL_AUXPLL_DIV_3 0x00000400U¶: Auxiliary PLL divide by 3.

SYSCTL_AUXPLL_DIV_5 0x00000500U¶: Auxiliary PLL divide by 5.

SYSCTL_AUXPLL_DIV_6 0x00000600U¶: Auxiliary PLL divide by 6.

SYSCTL_AUXPLL_DIV_7 0x00000700U¶: Auxiliary PLL divide by 7.

SYSCTL_AUXPLL_REFDIV(x) SYSCTL_REFDIV((x))¶: Macro to format Clock divider value. x is a number from 1 to 32.

SYSCTL_AUXPLL_ODIV(x) SYSCTL_ODIV((x))¶: Macro to format Clock divider value. x is a number from 1 to 32.

SYSCTL_AUXPLL_IMULT(x) SYSCTL_IMULT((x))¶: Macro to format integer multiplier value. x is a number from 1 to 127.

SYSCTL_AUXPLL_FMULT_NONE 0x00000000U¶: No fractional multiplier.

SYSCTL_AUXPLL_FMULT_0 0x00000000U¶: No fractional multiplier.

SYSCTL_AUXPLL_FMULT_1_4 0x00004000U¶: Fractional multiplier - 0.25.

SYSCTL_AUXPLL_FMULT_1_2 0x00008000U¶: Fractional multiplier - 0.50.

SYSCTL_AUXPLL_FMULT_3_4 0x0000C000U¶: Fractional multiplier - 0.75.

SYSCTL_AUXPLL_OSCSRC_OSC2 0x00000000UL¶: Internal oscillator INTOSC2 as auxiliary clock input.

SYSCTL_AUXPLL_OSCSRC_XTAL 0x00010000UL¶: External oscillator (XTAL) as auxiliary clock input.

SYSCTL_AUXPLL_OSCSRC_AUXCLKIN 0x00020000U¶: AUXCLKIN (from GPIO) as auxiliary clock input.

SYSCTL_AUXPLL_OSCSRC_XTAL_SE 0x00030000U¶: External oscillator (XTAL) in single-ended mode.

SYSCTL_AUXPLL_ENABLE 0x80000000U¶: Enable AUXPLL.

SYSCTL_AUXPLL_DISABLE 0x00000000U¶: Disable AUXPLL.

SYSCTL_AUXPLL_BYPASS 0x40000000U¶: Bypass AUXPLL.

SYSCTL_NMI_NMIINT 0x1U¶: NMI Interrupt Flag.

SYSCTL_NMI_CLOCKFAIL 0x2U¶: Clock Fail Interrupt Flag.

SYSCTL_NMI_UNCERR 0x4U¶: Flash/RAM/ROM Uncorrectable Error NMI Flag.

SYSCTL_NMI_REGPARITYERR 0x8U¶: Register parity error.

SYSCTL_NMI_CPU1HWBISTERR 0x10U¶: HW BIST Error NMI Flag.

SYSCTL_NMI_PIEVECTERR 0x40U¶: PIE Vector Fetch Error Flag.

SYSCTL_NMI_SYSDBGNMI 0x80U¶: System Debug Module NMI Flag.

SYSCTL_NMI_CLBNMI 0x100U¶: Reconfigurable Logic NMI Flag.

SYSCTL_NMI_CPU2WDRSN 0x200U¶: CPU2 WDRSn Reset Indication Flag.

SYSCTL_NMI_CPU2NMIWDRSN 0x400U¶: CPU2 NMIWDRSn Reset Indication Flag.

SYSCTL_NMI_LSCMPERR 0x1000U¶: Lockstep Compare Error.

SYSCTL_NMI_ECATNMIN 0x2000U¶: EtherCAT NMI Flag.

SYSCTL_NMI_CRC_FAIL 0x4000U¶: BGCRC calculation failed.

SYSCTL_NMI_SWERR 0x8000U¶: SW Error Force NMI Flag.

SYSCTL_STATUS_GINT 0x1U¶: Global Interrupt flag.

SYSCTL_STATUS_EMIF_ERR 0x2U¶: EMIF error event flag.

SYSCTL_STATUS_CORRECTABLE_ERR 0x4U¶: RAM/Flash correctable error flag.

SYSCTL_STATUS_RAM_ACC_VIOL 0x10U¶: A RAM access vioation flag.

SYSCTL_STATUS_SYS_PLL_SLIP 0x20U¶: System PLL Slip event flag.

SYSCTL_STATUS_AUX_PLL_SLIP 0x40U¶: Auxillary PLL Slip event flag.

SYSCTL_STATUS_DCC0 0x80U¶: DCC0 Interrupt flag.

SYSCTL_STATUS_DCC1 0x100U¶: DCC1 Interrupt flag.

SYSCTL_STATUS_DCC2 0x200U¶: DCC2 Interrupt flag.

SYSCTL_STATUS_AES_BUS_ERROR 0x400U¶: AES_BUS_ERROR Interrupt flag.

SYSCTL_STATUS_EPG1_INT 0x800U¶: EPG1_INT Interrupt flag.

SYSCTL_CAUSE_POR 0x00000001U¶: Power-on reset.

SYSCTL_CAUSE_XRS 0x00000002U¶: External reset pin.

SYSCTL_CAUSE_WDRS 0x00000004U¶: Watchdog reset.

SYSCTL_CAUSE_NMIWDRS 0x00000008U¶: NMI watchdog reset.

SYSCTL_CAUSE_SCCRESET 0x00000100U¶: SCCRESETn by DCSM.

SYSCTL_CAUSE_HWBISTN 0x00000020U¶: HWBISTn Reset.

SYSCTL_CAUSE_ECAT_RESET_OUT 0x00000200U¶: ECAT_RESET_OUT Reset.

SYSCTL_CAUSE_SIMRESET_CPU1RSN 0x00000400U¶: SIMRESET_CPU1RSn.

SYSCTL_CAUSE_SIMRESET_XRSN 0x00000800U¶: SIMRESET_XRSn.

SYSCTL_ADCSOC_SRC_PWM1SOCA 0x1U¶: ePWM1 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM2SOCA 0x2U¶: ePWM2 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM3SOCA 0x4U¶: ePWM3 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM4SOCA 0x8U¶: ePWM4 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM5SOCA 0x10U¶: ePWM5 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM6SOCA 0x20U¶: ePWM6 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM7SOCA 0x40U¶: ePWM7 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM8SOCA 0x80U¶: ePWM8 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM9SOCA 0x100U¶: ePWM9 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM10SOCA 0x200U¶: ePWM10 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM11SOCA 0x400U¶: ePWM11 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM12SOCA 0x800U¶: ePWM12 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM13SOCA 0x1000U¶: ePWM13 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM14SOCA 0x2000U¶: ePWM14 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM15SOCA 0x4000U¶: ePWM15 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM16SOCA 0x8000U¶: ePWM16 SOCA for ADCSOCAO

SYSCTL_ADCSOC_SRC_PWM1SOCB 0x10000U¶: ePWM1 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM2SOCB 0x20000U¶: ePWM2 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM3SOCB 0x40000U¶: ePWM3 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM4SOCB 0x80000U¶: ePWM4 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM5SOCB 0x100000U¶: ePWM5 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM6SOCB 0x200000U¶: ePWM6 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM7SOCB 0x400000U¶: ePWM7 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM8SOCB 0x800000U¶: ePWM8 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM9SOCB 0x1000000U¶: ePWM9 SOCB for ADCSOCBO

SYSCTL_ADCSOC_SRC_PWM13SOCB 0x10000000U¶: ePWM13 SOCB for ADCSOCBO

Enums

enum SysCtl_PeripheralPCLOCKCR¶

The following are values that can be passed to SysCtl_enablePeripheral() and SysCtl_disablePeripheral() as the peripheral parameter.

Values:

enumerator SYSCTL_PERIPH_CLK_CLA1 = 0x0000¶: CLA1 clock.

enumerator SYSCTL_PERIPH_CLK_DMA = 0x0200¶: DMA clock.

enumerator SYSCTL_PERIPH_CLK_TIMER0 = 0x0300¶: CPUTIMER0 clock.

enumerator SYSCTL_PERIPH_CLK_TIMER1 = 0x0400¶: CPUTIMER1 clock.

enumerator SYSCTL_PERIPH_CLK_TIMER2 = 0x0500¶: CPUTIMER2 clock.

enumerator SYSCTL_PERIPH_CLK_CPUBGCRC = 0x0D00¶: CPUBGCRC clock.

enumerator SYSCTL_PERIPH_CLK_CLA1BGCRC = 0x0E00¶: CLA1BGCRC clock.

enumerator SYSCTL_PERIPH_CLK_TBCLKSYNC = 0x1200¶: TBCLKSYNC clock.

enumerator SYSCTL_PERIPH_CLK_GTBCLKSYNC = 0x1300¶: GTBCLKSYNC clock.

enumerator SYSCTL_PERIPH_CLK_ERAD = 0x1800¶: ERAD clock.

enumerator SYSCTL_PERIPH_CLK_EMIF1 = 0x0001¶: EMIF1 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM1 = 0x0002¶: EPWM1 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM2 = 0x0102¶: EPWM2 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM3 = 0x0202¶: EPWM3 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM4 = 0x0302¶: EPWM4 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM5 = 0x0402¶: EPWM5 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM6 = 0x0502¶: EPWM6 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM7 = 0x0602¶: EPWM7 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM8 = 0x0702¶: EPWM8 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM9 = 0x0802¶: EPWM9 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM10 = 0x0902¶: EPWM10 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM11 = 0x0A02¶: EPWM11 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM12 = 0x0B02¶: EPWM12 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM13 = 0x0C02¶: EPWM13 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM14 = 0x0D02¶: EPWM14 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM15 = 0x0E02¶: EPWM15 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM16 = 0x0F02¶: EPWM16 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM17 = 0x1002¶: EPWM17 clock.

enumerator SYSCTL_PERIPH_CLK_EPWM18 = 0x1102¶: EPWM18 clock.

enumerator SYSCTL_PERIPH_CLK_ECAP1 = 0x0003¶: ECAP1 clock.

enumerator SYSCTL_PERIPH_CLK_ECAP2 = 0x0103¶: ECAP2 clock.

enumerator SYSCTL_PERIPH_CLK_ECAP3 = 0x0203¶: ECAP3 clock.

enumerator SYSCTL_PERIPH_CLK_ECAP4 = 0x0303¶: ECAP4 clock.

enumerator SYSCTL_PERIPH_CLK_ECAP5 = 0x0403¶: ECAP5 clock.

enumerator SYSCTL_PERIPH_CLK_ECAP6 = 0x0503¶: ECAP6 clock.

enumerator SYSCTL_PERIPH_CLK_ECAP7 = 0x0603¶: ECAP7 clock.

enumerator SYSCTL_PERIPH_CLK_EQEP1 = 0x0004¶: EQEP1 clock.

enumerator SYSCTL_PERIPH_CLK_EQEP2 = 0x0104¶: EQEP2 clock.

enumerator SYSCTL_PERIPH_CLK_EQEP3 = 0x0204¶: EQEP3 clock.

enumerator SYSCTL_PERIPH_CLK_EQEP4 = 0x0304¶: EQEP4 clock.

enumerator SYSCTL_PERIPH_CLK_EQEP5 = 0x0404¶: EQEP5 clock.

enumerator SYSCTL_PERIPH_CLK_EQEP6 = 0x0504¶: EQEP6 clock.

enumerator SYSCTL_PERIPH_CLK_SD1 = 0x0006¶: SD1 clock.

enumerator SYSCTL_PERIPH_CLK_SD2 = 0x0106¶: SD2 clock.

enumerator SYSCTL_PERIPH_CLK_SD3 = 0x0206¶: SD3 clock.

enumerator SYSCTL_PERIPH_CLK_SD4 = 0x0306¶: SD4 clock.

enumerator SYSCTL_PERIPH_CLK_SCIA = 0x0007¶: SCI_A clock.

enumerator SYSCTL_PERIPH_CLK_SCIB = 0x0107¶: SCI_B clock.

enumerator SYSCTL_PERIPH_CLK_UARTA = 0x1007¶: UART_A clock.

enumerator SYSCTL_PERIPH_CLK_UARTB = 0x1107¶: UART_B clock.

enumerator SYSCTL_PERIPH_CLK_SPIA = 0x0008¶: SPI_A clock.

enumerator SYSCTL_PERIPH_CLK_SPIB = 0x0108¶: SPI_B clock.

enumerator SYSCTL_PERIPH_CLK_SPIC = 0x0208¶: SPI_C clock.

enumerator SYSCTL_PERIPH_CLK_SPID = 0x0308¶: SPI_D clock.

enumerator SYSCTL_PERIPH_CLK_I2CA = 0x0009¶: I2C_A clock.

enumerator SYSCTL_PERIPH_CLK_I2CB = 0x0109¶: I2C_B clock.

enumerator SYSCTL_PERIPH_CLK_PMBUSA = 0x1009¶: PMBUS_A clock.

enumerator SYSCTL_PERIPH_CLK_CANA = 0x000A¶: CAN_A clock.

enumerator SYSCTL_PERIPH_CLK_MCANA = 0x040A¶: MCAN_A clock.

enumerator SYSCTL_PERIPH_CLK_MCANB = 0x050A¶: MCAN_B clock.

enumerator SYSCTL_PERIPH_CLK_USBA = 0x100B¶: USB_A clock.

enumerator SYSCTL_PERIPH_CLK_ADCA = 0x000D¶: ADC_A clock.

enumerator SYSCTL_PERIPH_CLK_ADCB = 0x010D¶: ADC_B clock.

enumerator SYSCTL_PERIPH_CLK_ADCC = 0x020D¶: ADC_C clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS1 = 0x000E¶: CMPSS1 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS2 = 0x010E¶: CMPSS2 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS3 = 0x020E¶: CMPSS3 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS4 = 0x030E¶: CMPSS4 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS5 = 0x040E¶: CMPSS5 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS6 = 0x050E¶: CMPSS6 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS7 = 0x060E¶: CMPSS7 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS8 = 0x070E¶: CMPSS8 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS9 = 0x080E¶: CMPSS9 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS10 = 0x090E¶: CMPSS10 clock.

enumerator SYSCTL_PERIPH_CLK_CMPSS11 = 0x0A0E¶: CMPSS11 clock.

enumerator SYSCTL_PERIPH_CLK_DACA = 0x1010¶: DAC_A clock.

enumerator SYSCTL_PERIPH_CLK_DACC = 0x1210¶: DAC_C clock.

enumerator SYSCTL_PERIPH_CLK_CLB1 = 0x0011¶: CLB1 clock.

enumerator SYSCTL_PERIPH_CLK_CLB2 = 0x0111¶: CLB2 clock.

enumerator SYSCTL_PERIPH_CLK_CLB3 = 0x0211¶: CLB3 clock.

enumerator SYSCTL_PERIPH_CLK_CLB4 = 0x0311¶: CLB4 clock.

enumerator SYSCTL_PERIPH_CLK_CLB5 = 0x0411¶: CLB5 clock.

enumerator SYSCTL_PERIPH_CLK_CLB6 = 0x0511¶: CLB6 clock.

enumerator SYSCTL_PERIPH_CLK_FSITXA = 0x0012¶: FSITX_A clock.

enumerator SYSCTL_PERIPH_CLK_FSITXB = 0x0112¶: FSITX_B clock.

enumerator SYSCTL_PERIPH_CLK_FSIRXA = 0x1012¶: FSIRX_A clock.

enumerator SYSCTL_PERIPH_CLK_FSIRXB = 0x1112¶: FSIRX_B clock.

enumerator SYSCTL_PERIPH_CLK_FSIRXC = 0x1212¶: FSIRX_C clock.

enumerator SYSCTL_PERIPH_CLK_FSIRXD = 0x1312¶: FSIRX_D clock.

enumerator SYSCTL_PERIPH_CLK_LINA = 0x0013¶: LIN_A clock.

enumerator SYSCTL_PERIPH_CLK_LINB = 0x0113¶: LIN_B clock.

enumerator SYSCTL_PERIPH_CLK_DCC0 = 0x0015¶: DCC0 clock.

enumerator SYSCTL_PERIPH_CLK_DCC1 = 0x0115¶: DCC1 clock.

enumerator SYSCTL_PERIPH_CLK_DCC2 = 0x0215¶: DCC2 clock.

enumerator SYSCTL_PERIPH_CLK_ECAT = 0x0017¶: ETHERCAT clock.

enumerator SYSCTL_PERIPH_CLK_HRCAL0 = 0x0019¶: HRCAL0 clock.

enumerator SYSCTL_PERIPH_CLK_HRCAL1 = 0x0119¶: HRCAL1 clock.

enumerator SYSCTL_PERIPH_CLK_HRCAL2 = 0x0219¶: HRCAL2 clock.

enumerator SYSCTL_PERIPH_CLK_AESA = 0x001A¶: AESA clock.

enumerator SYSCTL_PERIPH_CLK_EPG1 = 0x001B¶: EPG1 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER1 = 0x001C¶: ADCCHECKER1 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER2 = 0x011C¶: ADCCHECKER2 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER3 = 0x021C¶: ADCCHECKER3 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER4 = 0x031C¶: ADCCHECKER4 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER5 = 0x041C¶: ADCCHECKER5 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER6 = 0x051C¶: ADCCHECKER6 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER7 = 0x061C¶: ADCCHECKER7 clock.

enumerator SYSCTL_PERIPH_CLK_ADCCHECKER8 = 0x071C¶: ADCCHECKER8 clock.

enumerator SYSCTL_PERIPH_CLK_ADCSEAGGRCPU1 = 0x101C¶: ADCSEAGGRCPU1 clock.

enum SysCtl_PeripheralSOFTPRES¶

The following are values that can be passed to SysCtl_resetPeripheral() as the peripheral parameter.

Values:

enumerator SYSCTL_PERIPH_RES_CPU1CLA1 = 0x0000¶: Reset CPU1_CLA1 clock.

enumerator SYSCTL_PERIPH_RES_CPU1CPUBGCRC = 0x0D00¶: Reset CPU1_CPUBGCRC clock.

enumerator SYSCTL_PERIPH_RES_CPU1CLA1BGCRC = 0x0E00¶: Reset CPU1_CLA1BGCRC clock.

enumerator SYSCTL_PERIPH_RES_CPU2CPUBGCRC = 0x1000¶: Reset CPU2_CPUBGCRC clock.

enumerator SYSCTL_PERIPH_RES_CPU1ERAD = 0x1800¶: Reset CPU1_ERAD clock.

enumerator SYSCTL_PERIPH_RES_CPU2ERAD = 0x1900¶: Reset CPU2_ERAD clock.

enumerator SYSCTL_PERIPH_RES_EMIF1 = 0x0001¶: Reset EMIF1 clock.

enumerator SYSCTL_PERIPH_RES_EPWM1 = 0x0002¶: Reset EPWM1 clock.

enumerator SYSCTL_PERIPH_RES_EPWM2 = 0x0102¶: Reset EPWM2 clock.

enumerator SYSCTL_PERIPH_RES_EPWM3 = 0x0202¶: Reset EPWM3 clock.

enumerator SYSCTL_PERIPH_RES_EPWM4 = 0x0302¶: Reset EPWM4 clock.

enumerator SYSCTL_PERIPH_RES_EPWM5 = 0x0402¶: Reset EPWM5 clock.

enumerator SYSCTL_PERIPH_RES_EPWM6 = 0x0502¶: Reset EPWM6 clock.

enumerator SYSCTL_PERIPH_RES_EPWM7 = 0x0602¶: Reset EPWM7 clock.

enumerator SYSCTL_PERIPH_RES_EPWM8 = 0x0702¶: Reset EPWM8 clock.

enumerator SYSCTL_PERIPH_RES_EPWM9 = 0x0802¶: Reset EPWM9 clock.

enumerator SYSCTL_PERIPH_RES_EPWM10 = 0x0902¶: Reset EPWM10 clock.

enumerator SYSCTL_PERIPH_RES_EPWM11 = 0x0A02¶: Reset EPWM11 clock.

enumerator SYSCTL_PERIPH_RES_EPWM12 = 0x0B02¶: Reset EPWM12 clock.

enumerator SYSCTL_PERIPH_RES_EPWM13 = 0x0C02¶: Reset EPWM13 clock.

enumerator SYSCTL_PERIPH_RES_EPWM14 = 0x0D02¶: Reset EPWM14 clock.

enumerator SYSCTL_PERIPH_RES_EPWM15 = 0x0E02¶: Reset EPWM15 clock.

enumerator SYSCTL_PERIPH_RES_EPWM16 = 0x0F02¶: Reset EPWM16 clock.

enumerator SYSCTL_PERIPH_RES_EPWM17 = 0x1002¶: Reset EPWM17 clock.

enumerator SYSCTL_PERIPH_RES_EPWM18 = 0x1102¶: Reset EPWM18 clock.

enumerator SYSCTL_PERIPH_RES_ECAP1 = 0x0003¶: Reset ECAP1 clock.

enumerator SYSCTL_PERIPH_RES_ECAP2 = 0x0103¶: Reset ECAP2 clock.

enumerator SYSCTL_PERIPH_RES_ECAP3 = 0x0203¶: Reset ECAP3 clock.

enumerator SYSCTL_PERIPH_RES_ECAP4 = 0x0303¶: Reset ECAP4 clock.

enumerator SYSCTL_PERIPH_RES_ECAP5 = 0x0403¶: Reset ECAP5 clock.

enumerator SYSCTL_PERIPH_RES_ECAP6 = 0x0503¶: Reset ECAP6 clock.

enumerator SYSCTL_PERIPH_RES_ECAP7 = 0x0603¶: Reset ECAP7 clock.

enumerator SYSCTL_PERIPH_RES_EQEP1 = 0x0004¶: Reset EQEP1 clock.

enumerator SYSCTL_PERIPH_RES_EQEP2 = 0x0104¶: Reset EQEP2 clock.

enumerator SYSCTL_PERIPH_RES_EQEP3 = 0x0204¶: Reset EQEP3 clock.

enumerator SYSCTL_PERIPH_RES_EQEP4 = 0x0304¶: Reset EQEP4 clock.

enumerator SYSCTL_PERIPH_RES_EQEP5 = 0x0404¶: Reset EQEP5 clock.

enumerator SYSCTL_PERIPH_RES_EQEP6 = 0x0504¶: Reset EQEP6 clock.

enumerator SYSCTL_PERIPH_RES_SD1 = 0x0006¶: Reset SD1 clock.

enumerator SYSCTL_PERIPH_RES_SD2 = 0x0106¶: Reset SD2 clock.

enumerator SYSCTL_PERIPH_RES_SD3 = 0x0206¶: Reset SD3 clock.

enumerator SYSCTL_PERIPH_RES_SD4 = 0x0306¶: Reset SD4 clock.

enumerator SYSCTL_PERIPH_RES_SCIA = 0x0007¶: Reset SCI_A clock.

enumerator SYSCTL_PERIPH_RES_SCIB = 0x0107¶: Reset SCI_B clock.

enumerator SYSCTL_PERIPH_RES_UARTA = 0x1007¶: Reset UART_A clock.

enumerator SYSCTL_PERIPH_RES_UARTB = 0x1107¶: Reset UART_B clock.

enumerator SYSCTL_PERIPH_RES_SPIA = 0x0008¶: Reset SPI_A clock.

enumerator SYSCTL_PERIPH_RES_SPIB = 0x0108¶: Reset SPI_B clock.

enumerator SYSCTL_PERIPH_RES_SPIC = 0x0208¶: Reset SPI_C clock.

enumerator SYSCTL_PERIPH_RES_SPID = 0x0308¶: Reset SPI_D clock.

enumerator SYSCTL_PERIPH_RES_I2CA = 0x0009¶: Reset I2C_A clock.

enumerator SYSCTL_PERIPH_RES_I2CB = 0x0109¶: Reset I2C_B clock.

enumerator SYSCTL_PERIPH_RES_PMBUSA = 0x1009¶: Reset PMBUS_A clock.

enumerator SYSCTL_PERIPH_RES_CANA = 0x000A¶: Reset CAN_A clock.

enumerator SYSCTL_PERIPH_RES_MCANA = 0x040A¶: Reset MCAN_A clock.

enumerator SYSCTL_PERIPH_RES_MCANB = 0x050A¶: Reset MCAN_B clock.

enumerator SYSCTL_PERIPH_RES_USBA = 0x100B¶: Reset USB_A clock.

enumerator SYSCTL_PERIPH_RES_ADCA = 0x000D¶: Reset ADC_A clock.

enumerator SYSCTL_PERIPH_RES_ADCB = 0x010D¶: Reset ADC_B clock.

enumerator SYSCTL_PERIPH_RES_ADCC = 0x020D¶: Reset ADC_C clock.

enumerator SYSCTL_PERIPH_RES_CMPSS1 = 0x000E¶: Reset CMPSS1 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS2 = 0x010E¶: Reset CMPSS2 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS3 = 0x020E¶: Reset CMPSS3 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS4 = 0x030E¶: Reset CMPSS4 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS5 = 0x040E¶: Reset CMPSS5 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS6 = 0x050E¶: Reset CMPSS6 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS7 = 0x060E¶: Reset CMPSS7 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS8 = 0x070E¶: Reset CMPSS8 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS9 = 0x080E¶: Reset CMPSS9 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS10 = 0x090E¶: Reset CMPSS10 clock.

enumerator SYSCTL_PERIPH_RES_CMPSS11 = 0x0A0E¶: Reset CMPSS11 clock.

enumerator SYSCTL_PERIPH_RES_DACA = 0x1010¶: Reset DAC_A clock.

enumerator SYSCTL_PERIPH_RES_DACC = 0x1210¶: Reset DAC_C clock.

enumerator SYSCTL_PERIPH_RES_CLB1 = 0x0011¶: Reset CLB1 clock.

enumerator SYSCTL_PERIPH_RES_CLB2 = 0x0111¶: Reset CLB2 clock.

enumerator SYSCTL_PERIPH_RES_CLB3 = 0x0211¶: Reset CLB3 clock.

enumerator SYSCTL_PERIPH_RES_CLB4 = 0x0311¶: Reset CLB4 clock.

enumerator SYSCTL_PERIPH_RES_CLB5 = 0x0411¶: Reset CLB5 clock.

enumerator SYSCTL_PERIPH_RES_CLB6 = 0x0511¶: Reset CLB6 clock.

enumerator SYSCTL_PERIPH_RES_FSITXA = 0x0012¶: Reset FSITX_A clock.

enumerator SYSCTL_PERIPH_RES_FSITXB = 0x0112¶: Reset FSITX_B clock.

enumerator SYSCTL_PERIPH_RES_FSIRXA = 0x1012¶: Reset FSIRX_A clock.

enumerator SYSCTL_PERIPH_RES_FSIRXB = 0x1112¶: Reset FSIRX_B clock.

enumerator SYSCTL_PERIPH_RES_FSIRXC = 0x1212¶: Reset FSIRX_C clock.

enumerator SYSCTL_PERIPH_RES_FSIRXD = 0x1312¶: Reset FSIRX_D clock.

enumerator SYSCTL_PERIPH_RES_LINA = 0x0013¶: Reset LIN_A clock.

enumerator SYSCTL_PERIPH_RES_LINB = 0x0113¶: Reset LIN_B clock.

enumerator SYSCTL_PERIPH_RES_DCC0 = 0x0015¶: Reset DCC0 clock.

enumerator SYSCTL_PERIPH_RES_DCC1 = 0x0115¶: Reset DCC1 clock.

enumerator SYSCTL_PERIPH_RES_DCC2 = 0x0215¶: Reset DCC2 clock.

enumerator SYSCTL_PERIPH_RES_ECAT = 0x0017¶: Reset ETHERCAT clock.

enumerator SYSCTL_PERIPH_RES_AESA = 0x001A¶: Reset AESA clock.

enumerator SYSCTL_PERIPH_RES_EPG1 = 0x001B¶: Reset EPG1 clock.

enumerator SYSCTL_PERIPH_RES_FLASHA = 0x001C¶: Reset FLASHA clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER1 = 0x001D¶: Reset ADCCHECKER1 clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER2 = 0x011D¶: Reset ADCCHECKER2 clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER3 = 0x021D¶: Reset ADCCHECKER3 clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER4 = 0x031D¶: Reset ADCCHECKER4 clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER5 = 0x041D¶: Reset ADCCHECKER5 clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER6 = 0x051D¶: Reset ADCCHECKER6 clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER7 = 0x061D¶: Reset ADCCHECKER7 clock.

enumerator SYSCTL_PERIPH_RES_ADCCHECKER8 = 0x071D¶: Reset ADCCHECKER8 clock.

enumerator SYSCTL_PERIPH_RES_ADCSEAGGRCPU1 = 0x101D¶: Reset ADCSEAGGRCPU1 clock.

enumerator SYSCTL_PERIPH_RES_ADCSEAGGRCPU2 = 0x111D¶: Reset ADCSEAGGRCPU2 clock.

enum SysCtl_CPUSelPeripheral¶

The following are values that can be passed to SysCtl_lockCPUSelectRegs() as the peripheral parameter.

Values:

enumerator SYSCTL_CPUSEL0_EPWM = 0x0U¶: Configure CPU Select for EPWM.

enumerator SYSCTL_CPUSEL1_ECAP = 0x1U¶: Configure CPU Select for ECAP.

enumerator SYSCTL_CPUSEL2_EQEP = 0x2U¶: Configure CPU Select for EQEP.

enumerator SYSCTL_CPUSEL4_SD = 0x4U¶: Configure CPU Select for SD.

enumerator SYSCTL_CPUSEL5_SCI = 0x5U¶: Configure CPU Select for SCI.

enumerator SYSCTL_CPUSEL6_SPI = 0x6U¶: Configure CPU Select for SPI.

enumerator SYSCTL_CPUSEL7_I2C = 0x7U¶: Configure CPU Select for I2C.

enumerator SYSCTL_CPUSEL8_CAN = 0x8U¶: Configure CPU Select for CAN.

enumerator SYSCTL_CPUSEL11_ADC = 0xBU¶: Configure CPU Select for ADC.

enumerator SYSCTL_CPUSEL12_CMPSS = 0xCU¶: Configure CPU Select for CMPSS.

enumerator SYSCTL_CPUSEL13_DCC = 0xDU¶: Configure CPU Select for DCC.

enumerator SYSCTL_CPUSEL14_DAC = 0xEU¶: Configure CPU Select for DAC.

enumerator SYSCTL_CPUSEL15_CLB = 0xFU¶: Configure CPU Select for CLB.

enumerator SYSCTL_CPUSEL16_FSI = 0x10U¶: Configure CPU Select for FSI.

enumerator SYSCTL_CPUSEL17_LIN = 0x11U¶: Configure CPU Select for LIN.

enumerator SYSCTL_CPUSEL23_ECAT = 0x17U¶: Configure CPU Select for ETHERCAT.

enumerator SYSCTL_CPUSEL25_HRCAL = 0x19U¶: Configure CPU Select for HRCAL.

enumerator SYSCTL_CPUSEL26_AES = 0x1AU¶: Configure CPU Select for AES.

enumerator SYSCTL_CPUSEL27_EPG = 0x1BU¶: Configure CPU Select for EPG.

enum SysCtl_CPUSelPeriphInstance¶

The following are values that can be passed to SysCtl_selectCPUForPeripheralInstance() as the peripheral parameter.

Values:

enumerator SYSCTL_CPUSEL_EPWM1 = 0x0000¶

enumerator SYSCTL_CPUSEL_EPWM2 = 0x0100¶

enumerator SYSCTL_CPUSEL_EPWM3 = 0x0200¶

enumerator SYSCTL_CPUSEL_EPWM4 = 0x0300¶

enumerator SYSCTL_CPUSEL_EPWM5 = 0x0400¶

enumerator SYSCTL_CPUSEL_EPWM6 = 0x0500¶

enumerator SYSCTL_CPUSEL_EPWM7 = 0x0600¶

enumerator SYSCTL_CPUSEL_EPWM8 = 0x0700¶

enumerator SYSCTL_CPUSEL_EPWM9 = 0x0800¶

enumerator SYSCTL_CPUSEL_EPWM10 = 0x0900¶

enumerator SYSCTL_CPUSEL_EPWM11 = 0x0A00¶

enumerator SYSCTL_CPUSEL_EPWM12 = 0x0B00¶

enumerator SYSCTL_CPUSEL_EPWM13 = 0x0C00¶

enumerator SYSCTL_CPUSEL_EPWM14 = 0x0D00¶

enumerator SYSCTL_CPUSEL_EPWM15 = 0x0E00¶

enumerator SYSCTL_CPUSEL_EPWM16 = 0x0F00¶

enumerator SYSCTL_CPUSEL_EPWM17 = 0x1000¶

enumerator SYSCTL_CPUSEL_EPWM18 = 0x1100¶

enumerator SYSCTL_CPUSEL_ECAP1 = 0x0001¶

enumerator SYSCTL_CPUSEL_ECAP2 = 0x0101¶

enumerator SYSCTL_CPUSEL_ECAP3 = 0x0201¶

enumerator SYSCTL_CPUSEL_ECAP4 = 0x0301¶

enumerator SYSCTL_CPUSEL_ECAP5 = 0x0401¶

enumerator SYSCTL_CPUSEL_ECAP6 = 0x0501¶

enumerator SYSCTL_CPUSEL_ECAP7 = 0x0601¶

enumerator SYSCTL_CPUSEL_EQEP1 = 0x0002¶

enumerator SYSCTL_CPUSEL_EQEP2 = 0x0102¶

enumerator SYSCTL_CPUSEL_EQEP3 = 0x0202¶

enumerator SYSCTL_CPUSEL_EQEP4 = 0x0302¶

enumerator SYSCTL_CPUSEL_EQEP5 = 0x0402¶

enumerator SYSCTL_CPUSEL_EQEP6 = 0x0502¶

enumerator SYSCTL_CPUSEL_HRCAP6 = 0x0503¶

enumerator SYSCTL_CPUSEL_HRCAP7 = 0x0603¶

enumerator SYSCTL_CPUSEL_SD1 = 0x0004¶

enumerator SYSCTL_CPUSEL_SD2 = 0x0104¶

enumerator SYSCTL_CPUSEL_SD3 = 0x0204¶

enumerator SYSCTL_CPUSEL_SD4 = 0x0304¶

enumerator SYSCTL_CPUSEL_SCIA = 0x0005¶

enumerator SYSCTL_CPUSEL_SCIB = 0x0105¶

enumerator SYSCTL_CPUSEL_UARTA = 0x1005¶

enumerator SYSCTL_CPUSEL_UARTB = 0x1105¶

enumerator SYSCTL_CPUSEL_SPIA = 0x0006¶

enumerator SYSCTL_CPUSEL_SPIB = 0x0106¶

enumerator SYSCTL_CPUSEL_SPIC = 0x0206¶

enumerator SYSCTL_CPUSEL_SPID = 0x0306¶

enumerator SYSCTL_CPUSEL_I2CA = 0x0007¶

enumerator SYSCTL_CPUSEL_I2CB = 0x0107¶

enumerator SYSCTL_CPUSEL_PMBUSA = 0x1007¶

enumerator SYSCTL_CPUSEL_CANA = 0x0008¶

enumerator SYSCTL_CPUSEL_MCANA = 0x0408¶

enumerator SYSCTL_CPUSEL_MCANB = 0x0508¶

enumerator SYSCTL_CPUSEL_USBA = 0x1009¶

enumerator SYSCTL_CPUSEL_ADCA = 0x000B¶

enumerator SYSCTL_CPUSEL_ADCB = 0x010B¶

enumerator SYSCTL_CPUSEL_ADCC = 0x020B¶

enumerator SYSCTL_CPUSEL_CMPSS1 = 0x000C¶

enumerator SYSCTL_CPUSEL_CMPSS2 = 0x010C¶

enumerator SYSCTL_CPUSEL_CMPSS3 = 0x020C¶

enumerator SYSCTL_CPUSEL_CMPSS4 = 0x030C¶

enumerator SYSCTL_CPUSEL_CMPSS5 = 0x040C¶

enumerator SYSCTL_CPUSEL_CMPSS6 = 0x050C¶

enumerator SYSCTL_CPUSEL_CMPSS7 = 0x060C¶

enumerator SYSCTL_CPUSEL_CMPSS8 = 0x070C¶

enumerator SYSCTL_CPUSEL_CMPSS9 = 0x080C¶

enumerator SYSCTL_CPUSEL_CMPSS10 = 0x090C¶

enumerator SYSCTL_CPUSEL_CMPSS11 = 0x0A0C¶

enumerator SYSCTL_CPUSEL_DCC0 = 0x000D¶

enumerator SYSCTL_CPUSEL_DCC1 = 0x010D¶

enumerator SYSCTL_CPUSEL_DCC2 = 0x020D¶

enumerator SYSCTL_CPUSEL_DACA = 0x100E¶

enumerator SYSCTL_CPUSEL_DACC = 0x120E¶

enumerator SYSCTL_CPUSEL_CLB1 = 0x000F¶

enumerator SYSCTL_CPUSEL_CLB2 = 0x010F¶

enumerator SYSCTL_CPUSEL_CLB3 = 0x020F¶

enumerator SYSCTL_CPUSEL_CLB4 = 0x030F¶

enumerator SYSCTL_CPUSEL_CLB5 = 0x040F¶

enumerator SYSCTL_CPUSEL_CLB6 = 0x050F¶

enumerator SYSCTL_CPUSEL_FSITXA = 0x0010¶

enumerator SYSCTL_CPUSEL_FSITXB = 0x0110¶

enumerator SYSCTL_CPUSEL_FSIRXA = 0x1010¶

enumerator SYSCTL_CPUSEL_FSIRXB = 0x1110¶

enumerator SYSCTL_CPUSEL_FSIRXC = 0x1210¶

enumerator SYSCTL_CPUSEL_FSIRXD = 0x1310¶

enumerator SYSCTL_CPUSEL_LINA = 0x0011¶

enumerator SYSCTL_CPUSEL_LINB = 0x0111¶

enumerator SYSCTL_CPUSEL_ECAT = 0x0017¶

enumerator SYSCTL_CPUSEL_HRCAL0 = 0x0019¶

enumerator SYSCTL_CPUSEL_HRCAL1 = 0x0119¶

enumerator SYSCTL_CPUSEL_HRCAL2 = 0x0219¶

enumerator SYSCTL_CPUSEL_AESA = 0x001A¶

enumerator SYSCTL_CPUSEL_EPG1 = 0x001B¶

enumerator SYSCTL_CPUSEL_ADCCHECKER1 = 0x001C¶

enumerator SYSCTL_CPUSEL_ADCCHECKER2 = 0x011C¶

enumerator SYSCTL_CPUSEL_ADCCHECKER3 = 0x021C¶

enumerator SYSCTL_CPUSEL_ADCCHECKER4 = 0x031C¶

enumerator SYSCTL_CPUSEL_ADCCHECKER5 = 0x041C¶

enumerator SYSCTL_CPUSEL_ADCCHECKER6 = 0x051C¶

enumerator SYSCTL_CPUSEL_ADCCHECKER7 = 0x061C¶

enumerator SYSCTL_CPUSEL_ADCCHECKER8 = 0x071C¶

enum SysCtl_CPUSel¶

The following are values that can be passed to SysCtl_selectCPUForPeripheral() as cpuInst parameter.

Values:

enumerator SYSCTL_CPUSEL_CPU1 = 0x0U¶: Connect the peripheral (indicated by SysCtl_CPUSelPeripheral) to CPU1.

enumerator SYSCTL_CPUSEL_CPU2 = 0x1U¶: Connect the peripheral (indicated by SysCtl_CPUSelPeripheral) to CPU2.

enum SysCtl_FlashBank¶

Values:

enumerator SYSCTL_FLASH_BANK0 = 0U¶

enumerator SYSCTL_FLASH_BANK1 = 2U¶

enumerator SYSCTL_FLASH_BANK2 = 4U¶

enumerator SYSCTL_FLASH_BANK3 = 6U¶

enumerator SYSCTL_FLASH_BANK4 = 8U¶

enum SysCtl_SharedDxRAM¶

Values:

enumerator SYSCTL_D2RAM = 0x4U¶

enumerator SYSCTL_D3RAM = 0x8U¶

enumerator SYSCTL_D4RAM = 0x10U¶

enumerator SYSCTL_D5RAM = 0x20U¶

enum SysCtl_WDPredivider¶

The following are values that can be passed to SysCtl_setWatchdogPredivider() as the predivider parameter.

Values:

enumerator SYSCTL_WD_PREDIV_2 = 0x800¶: PREDIVCLK = INTOSC1 / 2.

enumerator SYSCTL_WD_PREDIV_4 = 0x900¶: PREDIVCLK = INTOSC1 / 4.

enumerator SYSCTL_WD_PREDIV_8 = 0xA00¶: PREDIVCLK = INTOSC1 / 8.

enumerator SYSCTL_WD_PREDIV_16 = 0xB00¶: PREDIVCLK = INTOSC1 / 16.

enumerator SYSCTL_WD_PREDIV_32 = 0xC00¶: PREDIVCLK = INTOSC1 / 32.

enumerator SYSCTL_WD_PREDIV_64 = 0xD00¶: PREDIVCLK = INTOSC1 / 64.

enumerator SYSCTL_WD_PREDIV_128 = 0xE00¶: PREDIVCLK = INTOSC1 / 128.

enumerator SYSCTL_WD_PREDIV_256 = 0xF00¶: PREDIVCLK = INTOSC1 / 256.

enumerator SYSCTL_WD_PREDIV_512 = 0x000¶: PREDIVCLK = INTOSC1 / 512.

enumerator SYSCTL_WD_PREDIV_1024 = 0x100¶: PREDIVCLK = INTOSC1 / 1024.

enumerator SYSCTL_WD_PREDIV_2048 = 0x200¶: PREDIVCLK = INTOSC1 / 2048.

enumerator SYSCTL_WD_PREDIV_4096 = 0x300¶: PREDIVCLK = INTOSC1 / 4096.

enum SysCtl_WDPrescaler¶

The following are values that can be passed to SysCtl_setWatchdogPrescaler() as the prescaler parameter.

Values:

enumerator SYSCTL_WD_PRESCALE_1 = 1¶: WDCLK = PREDIVCLK / 1.

enumerator SYSCTL_WD_PRESCALE_2 = 2¶: WDCLK = PREDIVCLK / 2.

enumerator SYSCTL_WD_PRESCALE_4 = 3¶: WDCLK = PREDIVCLK / 4.

enumerator SYSCTL_WD_PRESCALE_8 = 4¶: WDCLK = PREDIVCLK / 8.

enumerator SYSCTL_WD_PRESCALE_16 = 5¶: WDCLK = PREDIVCLK / 16.

enumerator SYSCTL_WD_PRESCALE_32 = 6¶: WDCLK = PREDIVCLK / 32.

enumerator SYSCTL_WD_PRESCALE_64 = 7¶: WDCLK = PREDIVCLK / 64.

enum SysCtl_WDMode¶

The following are values that can be passed to SysCtl_setWatchdogMode() as the prescaler parameter.

Values:

enumerator SYSCTL_WD_MODE_RESET¶: Watchdog can generate a reset signal.

enumerator SYSCTL_WD_MODE_INTERRUPT¶: Watchdog can generate an interrupt signal; reset signal is disabled.

enum SysCtl_LSPCLKPrescaler¶

The following are values that can be passed to SysCtl_setLowSpeedClock() as the prescaler parameter.

Values:

enumerator SYSCTL_LSPCLK_PRESCALE_1 = 0¶: LSPCLK = SYSCLK / 1.

enumerator SYSCTL_LSPCLK_PRESCALE_2 = 1¶: LSPCLK = SYSCLK / 2.

enumerator SYSCTL_LSPCLK_PRESCALE_4 = 2¶: LSPCLK = SYSCLK / 4 (default)

enumerator SYSCTL_LSPCLK_PRESCALE_6 = 3¶: LSPCLK = SYSCLK / 6.

enumerator SYSCTL_LSPCLK_PRESCALE_8 = 4¶: LSPCLK = SYSCLK / 8.

enumerator SYSCTL_LSPCLK_PRESCALE_10 = 5¶: LSPCLK = SYSCLK / 10.

enumerator SYSCTL_LSPCLK_PRESCALE_12 = 6¶: LSPCLK = SYSCLK / 12.

enumerator SYSCTL_LSPCLK_PRESCALE_14 = 7¶: LSPCLK = SYSCLK / 14.

enum SysCtl_EPWMCLKDivider¶

The following are values that can be passed to SysCtl_setEPWMClockDivider() as the divider parameter.

Values:

enumerator SYSCTL_EPWMCLK_DIV_1¶: EPWMCLK = PLLSYSCLK / 1.

enumerator SYSCTL_EPWMCLK_DIV_2¶: EPWMCLK = PLLSYSCLK / 2.

enum SysCtl_EMIF1CLKDivider¶

The following are values that can be passed to SysCtl_setEMIF1ClockDivider() as the divider parameter.

Values:

enumerator SYSCTL_EMIF1CLK_DIV_1¶: EMIF1CLK = PLLSYSCLK / 1.

enumerator SYSCTL_EMIF1CLK_DIV_2¶: EMIF1CLK = PLLSYSCLK / 2.

enum SysCtl_LINACLKDivider¶

The following are values that can be passed to SysCtl_setLINAClockDivider() as the divider parameter.

Values:

enumerator SYSCTL_LINACLK_DIV_1¶: LINACLK = PLLSYSCLK / 1.

enumerator SYSCTL_LINACLK_DIV_2¶: LINACLK = PLLSYSCLK / 2.

enumerator SYSCTL_LINACLK_DIV_4¶: LINACLK = PLLSYSCLK / 4.

enum SysCtl_LINBCLKDivider¶

The following are values that can be passed to SysCtl_setLINBClockDivider() as the divider parameter.

Values:

enumerator SYSCTL_LINBCLK_DIV_1¶: LINBCLK = PLLSYSCLK / 1.

enumerator SYSCTL_LINBCLK_DIV_2¶: LINBCLK = PLLSYSCLK / 2.

enumerator SYSCTL_LINBCLK_DIV_4¶: LINBCLK = PLLSYSCLK / 4.

enum SysCtl_AccessPeripheral¶

The following are values that can be passed to SysCtl_setPeripheralAccessControl() and SysCtl_getPeripheralAccessControl() as the peripheral parameter.

Values:

enumerator SYSCTL_ACCESS_ADCA = 0x0¶: ADCA access.

enumerator SYSCTL_ACCESS_ADCB = 0x2¶: ADCB access.

enumerator SYSCTL_ACCESS_ADCC = 0x4¶: ADCC access.

enumerator SYSCTL_ACCESS_CMPSS1 = 0x10¶: CMPSS1 access.

enumerator SYSCTL_ACCESS_CMPSS2 = 0x12¶: CMPSS2 access.

enumerator SYSCTL_ACCESS_CMPSS3 = 0x14¶: CMPSS3 access.

enumerator SYSCTL_ACCESS_CMPSS4 = 0x16¶: CMPSS4 access.

enumerator SYSCTL_ACCESS_CMPSS5 = 0x18¶: CMPSS5 access.

enumerator SYSCTL_ACCESS_CMPSS6 = 0x1A¶: CMPSS6 access.

enumerator SYSCTL_ACCESS_CMPSS7 = 0x1C¶: CMPSS7 access.

enumerator SYSCTL_ACCESS_CMPSS8 = 0x1E¶: CMPSS8 access.

enumerator SYSCTL_ACCESS_CMPSS9 = 0x20¶: CMPSS9 access.

enumerator SYSCTL_ACCESS_CMPSS10 = 0x22¶: CMPSS10 access.

enumerator SYSCTL_ACCESS_CMPSS11 = 0x24¶: CMPSS11 access.

enumerator SYSCTL_ACCESS_DACA = 0x28¶: DACA access.

enumerator SYSCTL_ACCESS_DACC = 0x2C¶: DACC access.

enumerator SYSCTL_ACCESS_EPWM1 = 0x48¶: EPWM1 access.

enumerator SYSCTL_ACCESS_EPWM2 = 0x4A¶: EPWM2 access.

enumerator SYSCTL_ACCESS_EPWM3 = 0x4C¶: EPWM3 access.

enumerator SYSCTL_ACCESS_EPWM4 = 0x4E¶: EPWM4 access.

enumerator SYSCTL_ACCESS_EPWM5 = 0x50¶: EPWM5 access.

enumerator SYSCTL_ACCESS_EPWM6 = 0x52¶: EPWM6 access.

enumerator SYSCTL_ACCESS_EPWM7 = 0x54¶: EPWM7 access.

enumerator SYSCTL_ACCESS_EPWM8 = 0x56¶: EPWM8 access.

enumerator SYSCTL_ACCESS_EPWM9 = 0x58¶: EPWM9 access.

enumerator SYSCTL_ACCESS_EPWM10 = 0x5A¶: EPWM10 access.

enumerator SYSCTL_ACCESS_EPWM11 = 0x5C¶: EPWM11 access.

enumerator SYSCTL_ACCESS_EPWM12 = 0x5E¶: EPWM12 access.

enumerator SYSCTL_ACCESS_EPWM13 = 0x60¶: EPWM13 access.

enumerator SYSCTL_ACCESS_EPWM14 = 0x62¶: EPWM14 access.

enumerator SYSCTL_ACCESS_EPWM15 = 0x64¶: EPWM15 access.

enumerator SYSCTL_ACCESS_EPWM16 = 0x66¶: EPWM16 access.

enumerator SYSCTL_ACCESS_EPWM17 = 0x68¶: EPWM17 access.

enumerator SYSCTL_ACCESS_EPWM18 = 0x6A¶: EPWM18 access.

enumerator SYSCTL_ACCESS_EQEP1 = 0x70¶: EQEP1 access.

enumerator SYSCTL_ACCESS_EQEP2 = 0x72¶: EQEP2 access.

enumerator SYSCTL_ACCESS_EQEP3 = 0x74¶: EQEP3 access.

enumerator SYSCTL_ACCESS_EQEP4 = 0x76¶: EQEP4 access.

enumerator SYSCTL_ACCESS_EQEP5 = 0x78¶: EQEP5 access.

enumerator SYSCTL_ACCESS_EQEP6 = 0x7A¶: EQEP6 access.

enumerator SYSCTL_ACCESS_ECAP1 = 0x80¶: ECAP1 access.

enumerator SYSCTL_ACCESS_ECAP2 = 0x82¶: ECAP2 access.

enumerator SYSCTL_ACCESS_ECAP3 = 0x84¶: ECAP3 access.

enumerator SYSCTL_ACCESS_ECAP4 = 0x86¶: ECAP4 access.

enumerator SYSCTL_ACCESS_ECAP5 = 0x88¶: ECAP5 access.

enumerator SYSCTL_ACCESS_ECAP6 = 0x8A¶: ECAP6 access.

enumerator SYSCTL_ACCESS_ECAP7 = 0x8C¶: ECAP7 access.

enumerator SYSCTL_ACCESS_SDFM1 = 0xA8¶: SDFM1 access.

enumerator SYSCTL_ACCESS_SDFM2 = 0xAA¶: SDFM2 access.

enumerator SYSCTL_ACCESS_SDFM3 = 0xAC¶: SDFM3 access.

enumerator SYSCTL_ACCESS_SDFM4 = 0xAE¶: SDFM4 access.

enumerator SYSCTL_ACCESS_CLB1 = 0xB0¶: CLB1 access.

enumerator SYSCTL_ACCESS_CLB2 = 0xB2¶: CLB2 access.

enumerator SYSCTL_ACCESS_CLB3 = 0xB4¶: CLB3 access.

enumerator SYSCTL_ACCESS_CLB4 = 0xB6¶: CLB4 access.

enumerator SYSCTL_ACCESS_CLB5 = 0xB8¶: CLB5 access.

enumerator SYSCTL_ACCESS_CLB6 = 0xBA¶: CLB6 access.

enumerator SYSCTL_ACCESS_SCIA = 0x100¶: SCIA access.

enumerator SYSCTL_ACCESS_SCIB = 0x102¶: SCIB access.

enumerator SYSCTL_ACCESS_SPIA = 0x110¶: SPIA access.

enumerator SYSCTL_ACCESS_SPIB = 0x112¶: SPIB access.

enumerator SYSCTL_ACCESS_SPIC = 0x114¶: SPIC access.

enumerator SYSCTL_ACCESS_SPID = 0x116¶: SPID access.

enumerator SYSCTL_ACCESS_I2CA = 0x120¶: I2CA access.

enumerator SYSCTL_ACCESS_I2CB = 0x122¶: I2CB access.

enumerator SYSCTL_ACCESS_PMBUSA = 0x130¶: PMBUS_A access.

enumerator SYSCTL_ACCESS_LINA = 0x138¶: LIN_A access.

enumerator SYSCTL_ACCESS_LINB = 0x13A¶: LIN_B access.

enumerator SYSCTL_ACCESS_CANA = 0x140¶: DCANA access.

enumerator SYSCTL_ACCESS_MCANA = 0x148¶: MCANA access.

enumerator SYSCTL_ACCESS_MCANB = 0x14A¶: MCANB access.

enumerator SYSCTL_ACCESS_FSIATX = 0x158¶: FSIATX access.

enumerator SYSCTL_ACCESS_FSIARX = 0x15A¶: FSIARX access.

enumerator SYSCTL_ACCESS_FSIBTX = 0x15C¶: FSIBTX access.

enumerator SYSCTL_ACCESS_FSIBRX = 0x15E¶: FSIBRX access.

enumerator SYSCTL_ACCESS_FSICRX = 0x162¶: FSICRX access.

enumerator SYSCTL_ACCESS_FSIDRX = 0x166¶: FSIDRX access.

enumerator SYSCTL_ACCESS_USBA = 0x18A¶: USBA access.

enumerator SYSCTL_ACCESS_HRPWM0 = 0x1B2¶: HRPWM0 access.

enumerator SYSCTL_ACCESS_HRPWM1 = 0x1B4¶: HRPWM1 access.

enumerator SYSCTL_ACCESS_HRPWM2 = 0x1B6¶: HRPWM2 access.

enumerator SYSCTL_ACCESS_ECAT = 0x1B8¶: ETHERCAT access.

enumerator SYSCTL_ACCESS_AESA = 0x1BC¶: AESA access.

enumerator SYSCTL_ACCESS_UARTA = 0x1BE¶: UARTA access.

enumerator SYSCTL_ACCESS_UARTB = 0x1C0¶: UARTB access.

enum SysCtl_AccessController¶

The following are values that can be passed to SysCtl_setPeripheralAccessControl() and SysCtl_getPeripheralAccessControl() as the controller parameter.

Values:

enumerator SYSCTL_ACCESS_CPUX = 0U¶: CPU access to the peripheral.

enumerator SYSCTL_ACCESS_CLA1 = 2U¶: CLA1 access to the peripheral.

enumerator SYSCTL_ACCESS_DMA1 = 4U¶: DMA access to the peripheral.

enum SysCtl_AccessPermission¶

The following are values that can be passed to SysCtl_setPeripheralAccessControl() as the permission parameter.

Values:

enumerator SYSCTL_ACCESS_FULL = 3U¶: Full Access for both read and write.

enumerator SYSCTL_ACCESS_PROTECTED = 2U¶: Protected RD access such that FIFOs. Clear on read, registers are not changed and no write access.

enumerator SYSCTL_ACCESS_NONE = 0U¶: No read or write access.

enum SysCtl_ClockOut¶

The following are values that can be passed to SysCtl_selectClockOutSource() as the source parameter.

Values:

enumerator SYSCTL_CLOCKOUT_PLLSYS = 0U¶: PLL System Clock post SYSCLKDIV.

enumerator SYSCTL_CLOCKOUT_PLLRAW = 1U¶: PLL Raw Clock.

enumerator SYSCTL_CLOCKOUT_SYSCLK = 2U¶: CPU System Clock.

enumerator SYSCTL_CLOCKOUT_SYSCLK2 = 3U¶: CPU 2 System Clock.

enumerator SYSCTL_CLOCKOUT_AUXPLLCLK = 4U¶: Aux PLL Clock.

enumerator SYSCTL_CLOCKOUT_INTOSC1 = 5U¶: Internal Oscillator 1.

enumerator SYSCTL_CLOCKOUT_INTOSC2 = 6U¶: Internal Oscillator 2.

enumerator SYSCTL_CLOCKOUT_XTALOSC = 7U¶: External Oscillator.

enum SysCtl_ExternalOscMode¶

The following are values that can be passed to SysCtl_setExternalOscMode() as the mode parameter.

Values:

enumerator SYSCTL_XTALMODE_CRYSTAL = 1U¶: XTAL Oscillator Crystal Mode.

enumerator SYSCTL_XTALMODE_SINGLE = 2U¶: XTAL Oscillator Single-Ended Mode.

enum SysCtl_SyncOutputSource¶

The following values define the syncSrc parameter for SysCtl_setSyncOutputConfig().

Values:

enumerator SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT = 0X0U¶: EPWM1SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM2SYNCOUT = 0X1U¶: EPWM2SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM3SYNCOUT = 0X2U¶: EPWM3SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT = 0X3U¶: EPWM4SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM5SYNCOUT = 0X4U¶: EPWM5SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM6SYNCOUT = 0X5U¶: EPWM6SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT = 0X6U¶: EPWM7SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM8SYNCOUT = 0X7U¶: EPWM8SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM9SYNCOUT = 0X8U¶: EPWM9SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT = 0X9U¶: EPWM10SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM11SYNCOUT = 0XAU¶: EPWM11SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM12SYNCOUT = 0XBU¶: EPWM12SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM13SYNCOUT = 0XCU¶: EPWM13SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM14SYNCOUT = 0XDU¶: EPWM14SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM15SYNCOUT = 0XEU¶: EPWM15SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM16SYNCOUT = 0XFU¶: EPWM16SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM17SYNCOUT = 0X10U¶: EPWM15SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_EPWM18SYNCOUT = 0X11U¶: EPWM16SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_ECAP1SYNCOUT = 0x18¶: ECAP1SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_ECAP2SYNCOUT = 0x19¶: ECAP2SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_ECAP3SYNCOUT = 0x20¶: ECAP3SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_ECAP4SYNCOUT = 0x21¶: ECAP4SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_ECAP5SYNCOUT = 0x22¶: ECAP5SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_ECAP6SYNCOUT = 0x23¶: ECAP6SYNCOUT –> EXTSYNCOUT.

enumerator SYSCTL_SYNC_OUT_SRC_ECAP7SYNCOUT = 0x24¶: ECAP7SYNCOUT –> EXTSYNCOUT.

enum SysCtl_DeviceParametric¶

The following values define the parametric parameter for SysCtl_getDeviceParametric().

Values:

enumerator SYSCTL_DEVICE_QUAL¶: Device Qualification Status.

enumerator SYSCTL_DEVICE_PINCOUNT¶: Device Pin Count.

enumerator SYSCTL_DEVICE_FLASH¶: Device Flash size (KB)

enumerator SYSCTL_DEVICE_FAMILY¶: Device Family.

enumerator SYSCTL_DEVICE_PARTNO¶: Device Part Number.

enumerator SYSCTL_DEVICE_CLASSID¶: Device Class ID.

enum SysCtl_DeviceConf¶

The following are values that can be passed to SysCtl_lockConfigRegs() as the regs parameter.

Values:

enumerator SYSCTL_DC_PERCNF_PARTID¶: Allows/Blocks write to Device config registers.

enumerator SYSCTL_BANKSEL¶: Allows/Blocks write to BANKSEL registers.

enum SysCtl_CoreReset¶

The following are values that can be passed to SysCtl_controlCPU2Reset() as the control parameter.

Values:

enumerator SYSCTL_CORE_DEACTIVE¶: Core reset is deactivated.

enumerator SYSCTL_CORE_ACTIVE¶: Core is held in reset.

enum SysCtl_SelType¶

The following are values that can be passed to SysCtl_configureType() as the peripheral parameter.

Values:

enumerator SYSCTL_USBTYPE = 0x0¶

Configure USB Type :

Type 0 : Disable Global interrupt feature
TYpe 1 : Enable Global interrupt feature

enumerator SYSCTL_ECAPTYPE = 0x1¶

Configure ECAP Type :

Type 0 : No EALLOW protection for ECAP registers
Type 1 : ECAP registers are EALLOW protected

enumerator SYSCTL_SDFMTYPE = 0x2¶

Configure SDFM Type :

Type 0 : Data Ready conditions combined with the fault conditions on the interrupt line. Data ready interrupts from individual filters are not generated.
Type 1 : Data Ready conditions do not generate the SDFMINT. Each filter generates a separate data ready interrupts.

enumerator SYSCTL_MEMMAPTYPE = 0x4¶

Configure MEMMAP Type :

Type 0 : Disables re-mapping SDRAM in lower 64kb of address space
Type 1 : Enables re-mapping SDRAM in lower 64kb of address space.

enum SysCtl_XClkDivider¶

The following are values that can be passed to SysCtl_setXClk() as divider parameter.

Values:

enumerator SYSCTL_XCLKOUT_DIV_1 = 0¶: XCLKOUT = XCLKOUT / 1.

enumerator SYSCTL_XCLKOUT_DIV_2 = 1¶: XCLKOUT = XCLKOUT / 2.

enumerator SYSCTL_XCLKOUT_DIV_4 = 2¶: XCLKOUT = XCLKOUT / 4.

enumerator SYSCTL_XCLKOUT_DIV_8 = 3¶: XCLKOUT = XCLKOUT / 8.

enum SysCtl_ECatClkDivider¶

The following are values that can be passed to SysCtl_setECatClk() as divider parameter.

Values:

enumerator SYSCTL_ECATCLKOUT_DIV_1¶: ECat clock = ECat clock / 1.

enumerator SYSCTL_ECATCLKOUT_DIV_2¶: ECat clock = ECat clock / 2.

enumerator SYSCTL_ECATCLKOUT_DIV_3¶: ECat clock = ECat clock / 3.

enumerator SYSCTL_ECATCLKOUT_DIV_4¶: ECat clock = ECat clock / 4.

enumerator SYSCTL_ECATCLKOUT_DIV_5¶: ECat clock = ECat clock / 5.

enumerator SYSCTL_ECATCLKOUT_DIV_6¶: ECat clock = ECat clock / 6.

enumerator SYSCTL_ECATCLKOUT_DIV_7¶: ECat clock = ECat clock / 7.

enumerator SYSCTL_ECATCLKOUT_DIV_8¶: ECat clock = ECat clock / 8.

enum SysCtl_PLLClockSource¶

The following are values that can be passed to SysCtl_setCMClk(), SysCtl_setECatClk() & SysCtl_isPLLValid() as source parameter.

Values:

enumerator SYSCTL_SOURCE_AUXPLL¶: Auxillary PLL.

enumerator SYSCTL_SOURCE_SYSPLL¶: System PLL.

enum SysCtl_MCANClkDivider¶

The following are values that can be passed to SysCtl_setMCANClk() as divider parameter.

Values:

enumerator SYSCTL_MCANCLK_DIV_1 = 0x0¶: MCAN clock = MCAN clock / 1.

enumerator SYSCTL_MCANCLK_DIV_2 = 0x1¶: MCAN clock = MCAN clock / 2.

enumerator SYSCTL_MCANCLK_DIV_3 = 0x2¶: MCAN clock = MCAN clock / 3.

enumerator SYSCTL_MCANCLK_DIV_4 = 0x3¶: MCAN clock = MCAN clock / 4.

enumerator SYSCTL_MCANCLK_DIV_5 = 0x4¶: MCAN clock = MCAN clock / 5.

enumerator SYSCTL_MCANCLK_DIV_6 = 0x5¶: MCAN clock = MCAN clock / 6.

enumerator SYSCTL_MCANCLK_DIV_7 = 0x6¶: MCAN clock = MCAN clock / 7.

enumerator SYSCTL_MCANCLK_DIV_8 = 0x7¶: MCAN clock = MCAN clock / 8.

enumerator SYSCTL_MCANCLK_DIV_9 = 0x8¶: MCAN clock = MCAN clock / 9.

enumerator SYSCTL_MCANCLK_DIV_10 = 0x9¶: MCAN clock = MCAN clock / 10.

enumerator SYSCTL_MCANCLK_DIV_11 = 0xA¶: MCAN clock = MCAN clock / 11.

enumerator SYSCTL_MCANCLK_DIV_12 = 0xB¶: MCAN clock = MCAN clock / 12.

enumerator SYSCTL_MCANCLK_DIV_13 = 0xC¶: MCAN clock = MCAN clock / 13.

enumerator SYSCTL_MCANCLK_DIV_14 = 0xD¶: MCAN clock = MCAN clock / 14.

enumerator SYSCTL_MCANCLK_DIV_15 = 0xE¶: MCAN clock = MCAN clock / 15.

enumerator SYSCTL_MCANCLK_DIV_16 = 0xF¶: MCAN clock = MCAN clock / 16.

enumerator SYSCTL_MCANCLK_DIV_17 = 0x10¶: MCAN clock = MCAN clock / 17.

enumerator SYSCTL_MCANCLK_DIV_18 = 0x11¶: MCAN clock = MCAN clock / 18.

enumerator SYSCTL_MCANCLK_DIV_19 = 0x12¶: MCAN clock = MCAN clock / 19.

enumerator SYSCTL_MCANCLK_DIV_20 = 0x13¶: MCAN clock = MCAN clock / 20.

enum SysCtl_MCANInstance¶

The following are values that can be passed to SysCtl_setMCANClk() as mcanInst parameter.

Values:

enumerator SYSCTL_MCANA = 1U¶

enumerator SYSCTL_MCANB = 2U¶

enum SysCtl_AuxPLLClkDivider¶

The following are values that can be passed to SysCtl_setAuxPLLClk() as divider parameter.

Values:

enumerator SYSCTL_AUXPLLCLK_DIV_1¶: AUXPLL clock = AUXPLL clock / 1.

enumerator SYSCTL_AUXPLLCLK_DIV_2¶: AUXPLL clock = AUXPLL clock / 2.

enumerator SYSCTL_AUXPLLCLK_DIV_4¶: AUXPLL clock = AUXPLL clock / 4.

enumerator SYSCTL_AUXPLLCLK_DIV_8¶: AUXPLL clock = AUXPLL clock / 8.

enumerator SYSCTL_AUXPLLCLK_DIV_3¶: AUXPLL clock = AUXPLL clock / 3.

enumerator SYSCTL_AUXPLLCLK_DIV_5¶: AUXPLL clock = AUXPLL clock / 5.

enumerator SYSCTL_AUXPLLCLK_DIV_6¶: AUXPLL clock = AUXPLL clock / 6.

enumerator SYSCTL_AUXPLLCLK_DIV_7¶: AUXPLL clock = AUXPLL clock / 7.

enum SysCtl_Cputimer2ClkDivider¶

The following are values that can be passed to SysCtl_setCputimer2Clk() as divider parameter.

Values:

enumerator SYSCTL_TMR2CLKPRESCALE_1¶: Cputimer2 clock = Cputimer2 clock / 1.

enumerator SYSCTL_TMR2CLKPRESCALE_2¶: Cputimer2 clock = Cputimer2 clock / 2.

enumerator SYSCTL_TMR2CLKPRESCALE_4¶: Cputimer2 clock = Cputimer2 clock / 4.

enumerator SYSCTL_TMR2CLKPRESCALE_8¶: Cputimer2 clock = Cputimer2 clock / 8.

enumerator SYSCTL_TMR2CLKPRESCALE_16¶: Cputimer2 clock = Cputimer2 clock / 16.

enum SysCtl_Cputimer2ClkSource¶

The following are values that can be passed to SysCtl_setCputimer2Clk() as source parameter.

Values:

enumerator SYSCTL_TMR2CLKSRCSEL_SYSCLK = 0U¶: System Clock.

enumerator SYSCTL_TMR2CLKSRCSEL_INTOSC1 = 1U¶: Internal Oscillator 1.

enumerator SYSCTL_TMR2CLKSRCSEL_INTOSC2 = 2U¶: Internal Oscillator 2.

enumerator SYSCTL_TMR2CLKSRCSEL_XTAL = 3U¶: Crystal oscillator.

enumerator SYSCTL_TMR2CLKSRCSEL_AUXPLLCLK = 6U¶: Aux PLL CLock.

enum SysCtl_ClkRegSel¶

The following are values that can be passed to SysCtl_lockClkConfig() as the peripheral parameter.

Values:

enumerator SYSCTL_REG_SEL_CLKSRCCTL1 = 0x0000¶: CLKSRCCTL1 lock.

enumerator SYSCTL_REG_SEL_CLKSRCCTL2 = 0x0100¶: CLKSRCCTL2 lock.

enumerator SYSCTL_REG_SEL_CLKSRCCTL3 = 0x0200¶: CLKSRCCTL3 lock.

enumerator SYSCTL_REG_SEL_SYSPLLCTL1 = 0x0300¶: SYSPLLCTL1 lock.

enumerator SYSCTL_REG_SEL_SYSPLLMULT = 0x0600¶: SYSPLLMULT lock.

enumerator SYSCTL_REG_SEL_AUXPLLCTL1 = 0x0700¶: AUXPLLCTL1 lock.

enumerator SYSCTL_REG_SEL_AUXPLLMULT = 0x0A00¶: AUXPLLMULT lock.

enumerator SYSCTL_REG_SEL_SYSCLKDIVSEL = 0x0B00¶: SYSCLKDIVSEL lock.

enumerator SYSCTL_REG_SEL_AUXCLKDIVSEL = 0x0C00¶: AUXCLKDIVSEL lock.

enumerator SYSCTL_REG_SEL_PERCLKDIVSEL = 0x0D00¶: PERCLKDIVSEL lock.

enumerator SYSCTL_REG_SEL_CLBCLKCTL = 0x0E00¶: CLBCLKCTL lock.

enumerator SYSCTL_REG_SEL_LOSPCP = 0x0F00¶: LOSPCP lock.

enumerator SYSCTL_REG_SEL_XTALCR = 0x1000¶: XTALCR lock.

enumerator SYSCTL_REG_SEL_EXTRFLTDET = 0x1100¶: EXTRFLTDET lock.

enumerator SYSCTL_REG_SEL_ETHERCATCLKCTL = 0x1200¶: ETHERCATCLKCTL lock.

enum SysCtl_CpuRegSel¶

The following are values that can be passed to SysCtl_lockSysConfig() as the peripheral parameter.

Values:

enumerator SYSCTL_REG_SEL_PIEVERRADDR = 0x0200¶: PIEVERRADDR lock.

enumerator SYSCTL_REG_SEL_PCLKCR0 = 0x0300¶: PCLKCR0 lock.

enumerator SYSCTL_REG_SEL_PCLKCR1 = 0x0400¶: PCLKCR1 lock.

enumerator SYSCTL_REG_SEL_PCLKCR2 = 0x0500¶: PCLKCR2 lock.

enumerator SYSCTL_REG_SEL_PCLKCR3 = 0x0600¶: PCLKCR3 lock.

enumerator SYSCTL_REG_SEL_PCLKCR4 = 0x0700¶: PCLKCR4 lock.

enumerator SYSCTL_REG_SEL_PCLKCR6 = 0x0900¶: PCLKCR6 lock.

enumerator SYSCTL_REG_SEL_PCLKCR7 = 0x0A00¶: PCLKCR7 lock.

enumerator SYSCTL_REG_SEL_PCLKCR8 = 0x0B00¶: PCLKCR8 lock.

enumerator SYSCTL_REG_SEL_PCLKCR9 = 0x0C00¶: PCLKCR9 lock.

enumerator SYSCTL_REG_SEL_PCLKCR10 = 0x0D00¶: PCLKCR10 lock.

enumerator SYSCTL_REG_SEL_PCLKCR11 = 0x0E00¶: PCLKCR11 lock.

enumerator SYSCTL_REG_SEL_PCLKCR13 = 0x1000¶: PCLKCR13 lock.

enumerator SYSCTL_REG_SEL_PCLKCR14 = 0x1100¶: PCLKCR14 lock.

enumerator SYSCTL_REG_SEL_PCLKCR16 = 0x1300¶: PCLKCR16 lock.

enumerator SYSCTL_REG_SEL_LPMCR = 0x1500¶: LPMCR lock.

enumerator SYSCTL_REG_SEL_GPIOLPMSEL0 = 0x1600¶: GPIOLPMSEL0 lock.

enumerator SYSCTL_REG_SEL_GPIOLPMSEL1 = 0x1700¶: GPIOLPMSEL1 lock.

enumerator SYSCTL_REG_SEL_PCLKCR17 = 0x1800¶: PCLKCR17 lock.

enumerator SYSCTL_REG_SEL_PCLKCR18 = 0x1900¶: PCLKCR18 lock.

enumerator SYSCTL_REG_SEL_PCLKCR19 = 0x1A00¶: PCLKCR19 lock.

enumerator SYSCTL_REG_SEL_PCLKCR21 = 0x1C00¶: PCLKCR21 lock.

enumerator SYSCTL_REG_SEL_PCLKCR22 = 0x1D00¶: PCLKCR22 lock.

enumerator SYSCTL_REG_SEL_PCLKCR23 = 0x1E00¶: PCLKCR23 lock.

enumerator SYSCTL_REG_SEL_ETHERCATCTL = 0x0001¶: ETHERCATCTL lock.

enumerator SYSCTL_REG_SEL_PCLKCR25 = 0x0101¶: PCLKCR25 lock.

enumerator SYSCTL_REG_SEL_PCLKCR26 = 0x0201¶: PCLKCR26 lock.

enumerator SYSCTL_REG_SEL_PCLKCR27 = 0x0301¶: PCLKCR27 lock.

enumerator SYSCTL_REG_SEL_LSEN = 0x0401¶: LSEN lock.

enumerator SYSCTL_REG_SEL_CMPSSLPMSEL = 0x0501¶: CMPSSLPMSEL lock.

enumerator SYSCTL_REG_SEL_PCLKCR28 = 0x0601¶: PCLKCR28 lock.

enumerator SYSCTL_REG_SEL_USER_REG1_SYSRSN = 0x1801¶: USER_REG1_SYSRSN lock.

enumerator SYSCTL_REG_SEL_USER_REG2_SYSRSN = 0x1901¶: USER_REG2_SYSRSN lock.

enumerator SYSCTL_REG_SEL_USER_REG1_XRSN = 0x1A01¶: USER_REG1_XRSN lock.

enumerator SYSCTL_REG_SEL_USER_REG2_XRSN = 0x1B01¶: USER_REG2_XRSN lock.

enumerator SYSCTL_REG_SEL_USER_REG1_PORESETN = 0x1C01¶: USER_REG1_PORESETN lock.

enumerator SYSCTL_REG_SEL_USER_REG2_PORESETN = 0x1D01¶: USER_REG2_PORESETN lock.

enumerator SYSCTL_REG_SEL_USER_REG3_PORESETN = 0x1E01¶: USER_REG3_PORESETN lock.

enumerator SYSCTL_REG_SEL_USER_REG4_PORESETN = 0x1F01¶: USER_REG4_PORESETN lock.

enum SysCtl_CLBClkDivider¶

The following are values that can be passed to SysCtl_setCLBClk() as cpuInst parameter.

Values:

enumerator SYSCTL_CLBCLKOUT_DIV_1¶: CLB clock = CLB clock / 1.

enumerator SYSCTL_CLBCLKOUT_DIV_2¶: CLB clock = CLB clock / 2.

enumerator SYSCTL_CLBCLKOUT_DIV_3¶: CLB clock = CLB clock / 3.

enumerator SYSCTL_CLBCLKOUT_DIV_4¶: CLB clock = CLB clock / 4.

enumerator SYSCTL_CLBCLKOUT_DIV_5¶: CLB clock = CLB clock / 5.

enumerator SYSCTL_CLBCLKOUT_DIV_6¶: CLB clock = CLB clock / 6.

enumerator SYSCTL_CLBCLKOUT_DIV_7¶: CLB clock = CLB clock / 7.

enumerator SYSCTL_CLBCLKOUT_DIV_8¶: CLB clock = CLB clock / 8.

enum SysCtl_CLBTClkDivider¶

Values:

enumerator SYSCTL_CLBTCLKOUT_DIV_1¶: CLBTCLKOUT = CLB clock / 1.

enumerator SYSCTL_CLBTCLKOUT_DIV_2¶: CLBTCLKOUT = CLB clock / 2.

enum SysCtl_CLBInst¶

Values:

enumerator SYSCTL_CLB1 = 0x10¶: CLB 1 instance.

enumerator SYSCTL_CLB2 = 0x11¶: CLB 2 instance.

enumerator SYSCTL_CLB3 = 0x12¶: CLB 3 instance.

enumerator SYSCTL_CLB4 = 0x13¶: CLB 4 instance.

enumerator SYSCTL_CLB5 = 0x14¶: CLB 5 instance.

enumerator SYSCTL_CLB6 = 0x15¶: CLB 6 instance.

enum SysCtl_CLBClkm¶

Values:

enumerator SYSCTL_CLBCLK_SYNC¶: CLB is synchronous to SYSCLK.

enumerator SYSCTL_CLBCLK_ASYNC¶: CLB runs of asynchronous clock.

enum SysCtl_UserRegister¶

The following are values that can be passed to SysCtl_setUserRegister() and SysCtl_getUserRegister() as the reg parameter.

Values:

enumerator SYSCTL_USER_REG1_SYSRSN = 0U¶: User register reset by SYSRSn.

enumerator SYSCTL_USER_REG2_SYSRSN = 1U¶: User register reset by SYSRSn.

enumerator SYSCTL_USER_REG1_XRSN = 2U¶: User register reset by XRSn.

enumerator SYSCTL_USER_REG2_XRSN = 3U¶: User register reset by XRSn.

enumerator SYSCTL_USER_REG1_PORESETN = 4U¶: User register reset by PORESETn.

enumerator SYSCTL_USER_REG2_PORESETN = 5U¶: User register reset by PORESETn.

enumerator SYSCTL_USER_REG3_PORESETN = 6U¶: User register reset by PORESETn.

enumerator SYSCTL_USER_REG4_PORESETN = 7U¶: User register reset by PORESETn.

enum SysCtl_LFUUserRegister¶

The following are values that can be passed to SysCtl_setLFUUserRegister() and SysCtl_getLFUUserRegister() as the reg parameter.

Values:

enumerator SYSCTL_LFU_USER_REG1_SYSRSN = 0U¶: User register reset by SYSRSn.

enumerator SYSCTL_LFU_USER_REG2_SYSRSN = 1U¶: User register reset by SYSRSn.

enumerator SYSCTL_LFU_USER_REG1_XRSN = 2U¶: User register reset by XRSn.

enumerator SYSCTL_LFU_USER_REG2_XRSN = 3U¶: User register reset by XRSn.

enumerator SYSCTL_LFU_USER_REG1_PORESETN = 4U¶: User register reset by PORESETn.

enumerator SYSCTL_LFU_USER_REG2_PORESETN = 5U¶: User register reset by PORESETn.

enum SysCtl_DevicePartNumber¶

The following are device part numbers that can be passed to SysCtl_emulateDevice() as the input parameter.

Values:

enumerator SYSCTL_EMULATE_F28P650DK9 = 0U¶

enumerator SYSCTL_EMULATE_F28P650DK7 = 1U¶

enumerator SYSCTL_EMULATE_F28P650DK8 = 2U¶

enumerator SYSCTL_EMULATE_F28P650SK7 = 3U¶

enumerator SYSCTL_EMULATE_F28P659DK8 = 4U¶

enumerator SYSCTL_EMULATE_F28P650DK6 = 5U¶

enumerator SYSCTL_EMULATE_F28P650SK6 = 6U¶

enumerator SYSCTL_EMULATE_F28P659DH8 = 7U¶

enumerator SYSCTL_EMULATE_F28P659SH6 = 8U¶

enumerator SYSCTL_EMULATE_F28P650DH6 = 9U¶

enumerator SYSCTL_EMULATE_F28P650SH6 = 10U¶

enum SysCtl_CMPSSLPMSel¶

Values that can be passed to SysCtl_disableCMPSSLPMWakeupPin() and SysCtl_enableCMPSSLPMWakeupPin() as the pin input parameter.

Values:

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_1H = 0x00¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_1L = 0x01¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_2H = 0x02¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_2L = 0x03¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_3H = 0x04¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_3L = 0x05¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_4H = 0x06¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_4L = 0x07¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_5H = 0x08¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_5L = 0x09¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_6H = 0x0A¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_6L = 0x0B¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_7H = 0x0C¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_7L = 0x0D¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_8H = 0x0E¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_8L = 0x0F¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_9H = 0x10¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_9L = 0x11¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_10H = 0x12¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_10L = 0x13¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_11H = 0x14¶

enumerator SYSCTL_CMPSSLPMSEL_CMPSS_11L = 0x15¶

Functions

void SysCtl_deviceCal(void)¶

Wrapper function for Device_cal function

Return

None.

Parameters

None: This is a wrapper function for the Device_cal function available in the OTP memory.

void SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral)¶

Resets a peripheral

This function uses the SOFTPRESx registers to reset a specified peripheral. Module registers will be returned to their reset states.

Parameters

peripheral: is the peripheral to reset.

Note: This includes registers containing trim values.The peripheral software reset needed by CPU2 can be communicated to CPU1 via IPC for all shared peripherals.
Return: None.

void SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral)¶

Enables a peripheral.

Peripherals are enabled with this function. At power-up, all peripherals are disabled; they must be enabled in order to operate or respond to register reads/writes.

Parameters

peripheral: is the peripheral to enable.

Note: Note that there should be atleast 5 cycles delay between enabling the peripheral clock and accessing the peripheral registers. The delay should be added by the user if the peripheral is accessed immediately after this function call. Use asm(” RPT #5 || NOP”); to add 5 cycle delay post this function call.
Return: None.

void SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral)¶

Disables a peripheral.

Peripherals are disabled with this function. Once disabled, they will not operate or respond to register reads/writes.

Parameters

peripheral: is the peripheral to disable.

Return: None.

void SysCtl_resetDevice(void)¶

Resets the device.

This function performs a watchdog reset of the device.

Return: This function does not return.

uint32_t SysCtl_getResetCause(void)¶

Gets the reason for a reset.

This function will return the reason(s) for a reset. Since the reset reasons are sticky until either cleared by software or an external reset, multiple reset reasons may be returned if multiple resets have occurred. The reset reason will be a logical OR of

SYSCTL_CAUSE_POR - Power-on reset
SYSCTL_CAUSE_XRS - External reset pin
SYSCTL_CAUSE_WDRS - Watchdog reset
SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset
SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM
SYSCTL_CAUSE_HWBISTN - HWBISTn Reset
SYSCTL_CAUSE_ECAT_RESET_OUT - ECAT_RESET_OUT Reset
SYSCTL_CAUSE_SIMRESET_CPU1RSN - SIMRESET_CPU1RSn
SYSCTL_CAUSE_SIMRESET_XRSN - SIMRESET_XRSn

Note: If you re-purpose the reserved boot ROM RAM, the POR and XRS reset statuses won’t be accurate.
Return: Returns the reason(s) for a reset.

void SysCtl_clearResetCause(uint32_t rstCauses)¶

Clears reset reasons.

This function clears the specified sticky reset reasons. Once cleared, another reset for the same reason can be detected, and a reset for a different reason can be distinguished (instead of having two reset causes set). If the reset reason is used by an application, all reset causes should be cleared after they are retrieved with

SysCtl_getResetCause().

Parameters

rstCauses: are the reset causes to be cleared; must be a logical OR of
- SYSCTL_CAUSE_POR - Power-on reset
- SYSCTL_CAUSE_XRS - External reset pin
- SYSCTL_CAUSE_WDRS - Watchdog reset
- SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset
- SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM
- SYSCTL_CAUSE_HWBISTN - HWBISTn Reset
- SYSCTL_CAUSE_ECAT_RESET_OUT - ECAT_RESET_OUT Reset
- SYSCTL_CAUSE_SIMRESET_CPU1RSN - SIMRESET_CPU1RSn
- SYSCTL_CAUSE_SIMRESET_XRSN - SIMRESET_XRSn

Note: Some reset causes are cleared by the boot ROM.
Return: None.

void SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler)¶

Sets the low speed peripheral clock rate prescaler.

This function configures the clock rate of the low speed peripherals. The

prescaler parameter is the value by which the SYSCLK rate is divided to get the LSPCLK rate. For example, a prescaler of SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter of the SYSCLK rate.

Parameters

prescaler: is the LSPCLK rate relative to SYSCLK

Return: None.

void SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider)¶

Sets the ePWM clock divider.

This function configures the clock rate of the EPWMCLK. The

divider parameter is the value by which the SYSCLK rate is divided to get the EPWMCLK rate. For example, SYSCTL_EPWMCLK_DIV_2 will select an EPWMCLK rate that is half the PLLSYSCLK rate.

Parameters

divider: is the value by which PLLSYSCLK is divided

Return: None.

void SysCtl_setEMIF1ClockDivider(SysCtl_EMIF1CLKDivider divider)¶

Sets the EMIF1 clock divider.

This function configures the clock rate of the EMIF1CLK. The

divider parameter is the value by which the SYSCLK rate is divided to get the EMIF1CLK rate. For example, SYSCTL_EMIF1CLK_DIV_2 will select an EMIF1CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual core device) rate.

Parameters

divider: is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual core device) is divided

Return: None.

void SysCtl_setLINAClockDivider(SysCtl_LINACLKDivider divider)¶

Sets the LINA clock divider.

This function configures the clock rate of the LINACLK. The

divider parameter is the value by which the SYSCLK rate is divided to get the LINACLK rate. For example, SYSCTL_LINACLK_DIV_2 will select an LINACLK rate that is half the PLLSYSCLK rate.

Parameters

divider: is the value by which PLLSYSCLK is divided

Return: None.

void SysCtl_setLINBClockDivider(SysCtl_LINBCLKDivider divider)¶

Sets the LINB clock divider.

This function configures the clock rate of the LINBCLK. The

divider parameter is the value by which the SYSCLK rate is divided to get the LINBCLK rate. For example, SYSCTL_LINBCLK_DIV_2 will select an LINBCLK rate that is half the PLLSYSCLK rate.

Parameters

divider: is the value by which PLLSYSCLK is divided

Return: None.

void SysCtl_selectClockOutSource(SysCtl_ClockOut source)¶

Selects a clock source to mux to an external GPIO pin (XCLKOUT).

This function configures the specified clock source to be muxed to an external clock out (XCLKOUT) GPIO pin. The

source parameter may take a value of one of the following values:

SYSCTL_CLOCKOUT_PLLSYS
SYSCTL_CLOCKOUT_PLLRAW
SYSCTL_CLOCKOUT_SYSCLK
SYSCTL_CLOCKOUT_SYSCLK2
SYSCTL_CLOCKOUT_AUXPLLCLK
SYSCTL_CLOCKOUT_INTOSC1
SYSCTL_CLOCKOUT_INTOSC2
SYSCTL_CLOCKOUT_XTALOSC

Parameters

source: is the internal clock source to be configured.

Return: None.

void SysCtl_setExternalOscMode(SysCtl_ExternalOscMode mode)¶

Set the external oscillator mode.

This function sets the external oscillator mode specified by the

mode parameter which may take one of two values:

SYSCTL_XTALMODE_CRYSTAL - Crystal Mode
SYSCTL_XTALMODE_SINGLE - Single-Ended Mode

Parameters

mode: is the external oscillator mode to be configured.

Note: The external oscillator must be powered off before this configuration can be performed.
Return: None.

uint16_t SysCtl_getExternalOscCounterValue(void)¶

Gets the external oscillator counter value.

This function returns the X1 clock counter value. When the return value reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external oscillator (XTAL), an application should call this function to make sure the counter is saturated.

Return: Returns the value of the 10-bit X1 clock counter.

void SysCtl_clearExternalOscCounterValue(void)¶

Clears the external oscillator counter value.

Return: None.

void SysCtl_turnOnOsc(uint32_t oscSource)¶

Turns on the specified oscillator sources.

This function turns on the oscillator specified by the

oscSource parameter which may take a value of SYSCTL_OSCSRC_XTAL

Parameters

oscSource: is the oscillator source to be configured.

Note: SYSCTL_OSCSRC_OSC1 is not a valid value for oscSource.
Return: None.

void SysCtl_turnOffOsc(uint32_t oscSource)¶

Turns off the specified oscillator sources.

This function turns off the oscillator specified by the

oscSource parameter which may take a value of SYSCTL_OSCSRC_XTAL

Parameters

oscSource: is the oscillator source to be configured.

Note: SYSCTL_OSCSRC_OSC1 is not a valid value for oscSource.
Return: None.

void SysCtl_enterIdleMode(void)¶

Enters IDLE mode.

This function puts the device into IDLE mode. The CPU clock is gated while all peripheral clocks are left running. Any enabled interrupt will wake the CPU up from IDLE mode.

Return: None.

void SysCtl_enterStandbyMode(void)¶

Enters STANDBY mode.

This function puts the device into STANDBY mode. This will gate both the CPU clock and any peripheral clocks derived from SYSCLK. The watchdog is left active, and an NMI or an optional watchdog interrupt will wake the CPU subsystem from STANDBY mode.

GPIOs may be configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin().

The CPU will receive an interrupt (WAKEINT) on wakeup.

Return: None.

void SysCtl_enterHaltMode(void)¶

Enters HALT mode.

This function puts the device into HALT mode. This will gate almost all systems and clocks and allows for the power-down of oscillators and analog blocks. The watchdog may be left clocked to produce a reset. See SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin().

Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first.

The CPU will receive an interrupt (WAKEINT) on wakeup.

Return: None.

void SysCtl_enableLPMWakeupPin(uint32_t pin)¶

Enables a pin to wake up the device from the following mode(s):

STANDBY
HALT

This function connects a pin to the LPM circuit, allowing an event on the pin to wake up the device when when it is in following mode(s):

STANDBY
HALT

Parameters

pin: is the identifying number of the pin.

The pin is specified by its numerical value. For example, GPIO34 is specified by passing 34 as pin. Only GPIOs 0 through 63 are capable of being connected to the LPM circuit.

Return: None.

void SysCtl_disableLPMWakeupPin(uint32_t pin)¶

Disables a pin to wake up the device from the following mode(s):

STANDBY
HALT

This function disconnects a pin to the LPM circuit, disallowing an event on the pin to wake up the device when when it is in following mode(s):

STANDBY
HALT

Parameters

pin: is the identifying number of the pin.

The pin is specified by its numerical value. For example, GPIO34 is specified by passing 34 as pin. Only GPIOs 0 through 63 are valid.

Return: None.

void SysCtl_enableCMPSSLPMWakeupPin(SysCtl_CMPSSLPMSel pin)¶

Connects the selected pin to LPM circuit

The

This function connects a pin to the LPM circuit

Parameters

pin: parameter can be a value from the enumeration SysCtl_CMPSSLPMSel

Return: None.

void SysCtl_disableCMPSSLPMWakeupPin(SysCtl_CMPSSLPMSel pin)¶

Disonnects the selected pin from LPM circuit

The

This function disconnects a pin from the LPM circuit

Parameters

pin: parameter can be a value from the enumeration SysCtl_CMPSSLPMSel

Return: None.

void SysCtl_setStandbyQualificationPeriod(uint16_t cycles)¶

Sets the number of cycles to qualify an input on waking from STANDBY mode.

This function sets the number of OSCCLK clock cycles used to qualify the selected inputs when waking from STANDBY mode. The

cycles parameter should be passed a cycle count between 2 and 65 cycles inclusive.

Parameters

cycles: is the number of OSCCLK cycles.

Return: None.

void SysCtl_enableWatchdogStandbyWakeup(void)¶

Enable the device to wake from STANDBY mode upon a watchdog interrupt.

Note: In order to use this option, you must configure the watchdog to generate an interrupt using SysCtl_setWatchdogMode().
Return: None.

void SysCtl_disableWatchdogStandbyWakeup(void)¶

Disable the device from waking from STANDBY mode upon a watchdog interrupt.

Return: None.

void SysCtl_enableWatchdogInHalt(void)¶

Enable the watchdog to run while in HALT mode.

This function configures the watchdog to continue to run while in HALT mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the system enters HALT mode. By default the watchdog is gated when the system enters HALT.

Return: None.

void SysCtl_disableWatchdogInHalt(void)¶

Disable the watchdog from running while in HALT mode.

This function gates the watchdog when the system enters HALT mode. INTOSC1 and INTOSC2 will be powered down. This is the default behavior of the device.

Return: None.

void SysCtl_setWatchdogMode(SysCtl_WDMode mode)¶

Configures whether the watchdog generates a reset or an interrupt signal.

This function configures the action taken when the watchdog counter reaches its maximum value. When the

mode parameter is SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog interrupt signal and disables the generation of a reset signal. This will allow the watchdog module to wake up the device from IDLE or STANDBY if desired (see SysCtl_enableWatchdogStandbyWakeup()).

Parameters

mode: is a flag to select the watchdog mode.

When the mode parameter is SYSCTL_WD_MODE_RESET, the watchdog will be put into reset mode and generation of a watchdog interrupt signal will be disabled. This is how the watchdog is configured by default.

Note: Check the status of the watchdog interrupt using SysCtl_isWatchdogInterruptActive() before calling this function. If the interrupt is still active, switching from interrupt mode to reset mode will immediately reset the device.
Return: None.

bool SysCtl_isWatchdogInterruptActive(void)¶

Gets the status of the watchdog interrupt signal.

This function returns the status of the watchdog interrupt signal. If the interrupt is active, this function will return true. If false, the interrupt is NOT active.

Note: Make sure to call this function to ensure that the interrupt is not active before making any changes to the configuration of the watchdog to prevent any unexpected behavior. For instance, switching from interrupt mode to reset mode while the interrupt is active will immediately reset the device.
Return: true if the interrupt is active and false if it is not.

void SysCtl_disableWatchdog(void)¶

Disables the watchdog.

This function disables the watchdog timer. Note that the watchdog timer is enabled on reset.

Return: None.

void SysCtl_enableWatchdog(void)¶

Enables the watchdog.

This function enables the watchdog timer. Note that the watchdog timer is enabled on reset.

Return: None.

bool SysCtl_isWatchdogEnabled(void)¶

Checks if the watchdog is enabled or not

This function returns the watchdog status whether it is enabled or disabled

Return: true if the watchdog is enabled & false if the watchdog is disabled

void SysCtl_serviceWatchdog(void)¶

Services the watchdog.

This function resets the watchdog.

Return: None.

void SysCtl_enableWatchdogReset(void)¶

Writes the first key to enter the watchdog reset.

This function writes the first key to enter the watchdog reset.

Return: None.

void SysCtl_resetWatchdog(void)¶

Writes the second key to reset the watchdog.

This function writes the second key to reset the watchdog.

Return: None.

void SysCtl_setWatchdogPredivider(SysCtl_WDPredivider predivider)¶

Sets up watchdog clock (WDCLK) pre-divider.

This function sets up the watchdog clock (WDCLK) pre-divider. There are two dividers that scale INTOSC1 to WDCLK. The

predivider parameter divides INTOSC1 down to PREDIVCLK and the prescaler (set by the SysCtl_setWatchdogPrescaler() function) divides PREDIVCLK down to WDCLK.

Parameters

predivider: is the value that configures the pre-divider.

Return: None.

void SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler)¶

Sets up watchdog clock (WDCLK) prescaler.

This function sets up the watchdog clock (WDCLK) prescaler. There are two dividers that scale INTOSC1 to WDCLK. The predivider (set with the

SysCtl_setWatchdogPredivider() function) divides INTOSC1 down to PREDIVCLK and the prescaler parameter divides PREDIVCLK down to WDCLK.

Parameters

prescaler: is the value that configures the watchdog clock relative to the value from the pre-divider.

Return: None.

uint16_t SysCtl_getWatchdogCounterValue(void)¶

Gets the watchdog counter value.

Return: Returns the current value of the 8-bit watchdog counter. If this count value overflows, a watchdog output pulse is generated.

bool SysCtl_getWatchdogResetStatus(void)¶

Gets the watchdog reset status.

This function returns the watchdog reset status. If this function returns true, that indicates that a watchdog reset generated the last reset condition. Otherwise, it was an external device or power-up reset condition.

Return: Returns true if the watchdog generated the last reset condition.

void SysCtl_clearWatchdogResetStatus(void)¶

Clears the watchdog reset status.

This function clears the watchdog reset status. To check if it was set first, see SysCtl_getWatchdogResetStatus().

Return: None.

void SysCtl_setWatchdogWindowValue(uint16_t value)¶

Set the minimum threshold value for windowed watchdog

This function sets the minimum threshold value used to define the lower limit of the windowed watchdog functionality.

Parameters

value: is the value to set the window threshold

Return: None.

void SysCtl_clearWatchdogOverride(void)¶

Clears the watchdog override.

This function clears the watchdog override and locks the watchdog timer module to remain in its prior state which could be either enable /disable. The watchdog timer will remain in this state until the next system reset.

Return: None.

void SysCtl_enableNMIGlobalInterrupt(void)¶

Enable the NMI Global interrupt bit

Note: This bit should be set after the device security related initialization is complete.

Return: None.

bool SysCtl_getNMIStatus(void)¶

Read NMI interrupts.

Read the current state of NMI interrupt.

Return: true if NMI interrupt is triggered, false if not.

uint16_t SysCtl_getNMIFlagStatus(void)¶

Read NMI Flags.

Read the current state of individual NMI interrupts

Return

Value of NMIFLG register. These defines are provided to decode the value:

SYSCTL_NMI_NMIINT - NMI Interrupt Flag
SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag
SYSCTL_NMI_UNCERR - Flash/RAM/ROM Uncorrectable Error NMI Flag
SYSCTL_NMI_REGPARITYERR - Register parity error
SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag
SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag
SYSCTL_NMI_SYSDBGNMI - System Debug Module NMI Flag
SYSCTL_NMI_CLBNMI - Reconfigurable Logic NMI Flag
SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag
SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag
SYSCTL_NMI_LSCMPERR - Lockstep Compare Error
SYSCTL_NMI_ECATNMIN - EtherCAT NMI Flag
SYSCTL_NMI_CRC_FAIL - BGCRC calculation failed.
SYSCTL_NMI_SWERR - SW Error Force NMI Flag

bool SysCtl_isNMIFlagSet(uint16_t nmiFlags)¶

Check if the individual NMI interrupts are set.

Check if interrupt flags corresponding to the passed in bit mask are asserted.

Parameters

nmiFlags: Bit mask of the NMI interrupts that user wants to clear. The bit format of this parameter is same as of the NMIFLG register. These defines are provided:
- SYSCTL_NMI_NMIINT - NMI Interrupt Flag
- SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag
- SYSCTL_NMI_UNCERR - Flash/RAM/ROM Uncorrectable Error NMI Flag
- SYSCTL_NMI_REGPARITYERR - Register parity error
- SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag
- SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag
- SYSCTL_NMI_SYSDBGNMI - System Debug Module NMI Flag
- SYSCTL_NMI_CLBNMI - Reconfigurable Logic NMI Flag
- SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag
- SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag
- SYSCTL_NMI_LSCMPERR - Lockstep Compare Error
- SYSCTL_NMI_ECATNMIN - EtherCAT NMI Flag
- SYSCTL_NMI_CRC_FAIL - BGCRC calculation failed.
- SYSCTL_NMI_SWERR - SW Error Force NMI Flag

Return: true if any of the NMI asked for in the parameter bit mask is set. false if none of the NMI requested in the parameter bit mask are set.

void SysCtl_clearNMIStatus(uint16_t nmiFlags)¶

Function to clear individual NMI interrupts.

Clear NMI interrupt flags that correspond with the passed in bit mask.

Parameters

nmiFlags: Bit mask of the NMI interrupts that user wants to clear. The bit format of this parameter is same as of the NMIFLG register. These defines are provided:
- SYSCTL_NMI_NMIINT - NMI Interrupt Flag
- SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag
- SYSCTL_NMI_UNCERR - Flash/RAM/ROM Uncorrectable Error NMI Flag
- SYSCTL_NMI_REGPARITYERR - Register parity error
- SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag
- SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag
- SYSCTL_NMI_SYSDBGNMI - System Debug Module NMI Flag
- SYSCTL_NMI_CLBNMI - Reconfigurable Logic NMI Flag
- SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag
- SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag
- SYSCTL_NMI_LSCMPERR - Lockstep Compare Error
- SYSCTL_NMI_ECATNMIN - EtherCAT NMI Flag
- SYSCTL_NMI_CRC_FAIL - BGCRC calculation failed.
- SYSCTL_NMI_SWERR - SW Error Force NMI Flag

Note: The NMI Interrupt flag is always cleared by default and therefore doesn’t have to be included in the bit mask.

Return: None.

void SysCtl_clearAllNMIFlags(void)¶

Clear all the NMI Flags that are currently set.

Return: None.

void SysCtl_forceNMIFlags(uint16_t nmiFlags)¶

Function to force individual NMI interrupt fail flags

Return

None.

Parameters

nmiFlags: Bit mask of the NMI interrupts that user wants to clear. The bit format of this parameter is same as of the NMIFLG register. These defines are provided:
- SYSCTL_NMI_NMIINT - NMI Interrupt Flag
- SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag
- SYSCTL_NMI_UNCERR - Flash/RAM/ROM Uncorrectable Error NMI Flag
- SYSCTL_NMI_REGPARITYERR - Register parity error
- SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag
- SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag
- SYSCTL_NMI_SYSDBGNMI - System Debug Module NMI Flag
- SYSCTL_NMI_CLBNMI - Reconfigurable Logic NMI Flag
- SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag
- SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag
- SYSCTL_NMI_LSCMPERR - Lockstep Compare Error
- SYSCTL_NMI_ECATNMIN - EtherCAT NMI Flag
- SYSCTL_NMI_CRC_FAIL - BGCRC calculation failed.
- SYSCTL_NMI_SWERR - SW Error Force NMI Flag

uint16_t SysCtl_getNMIWatchdogCounter(void)¶

Gets the NMI watchdog counter value.

Note: The counter is clocked at the SYSCLKOUT rate.

Return: Returns the NMI watchdog counter register’s current value.

void SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod)¶

Sets the NMI watchdog period value.

This function writes to the NMI watchdog period register that holds the value to which the NMI watchdog counter is compared. When the two registers match, a reset is generated. By default, the period is 0xFFFF.

Parameters

wdPeriod: is the 16-bit value at which a reset is generated.

Note: If a value smaller than the current counter value is passed into the wdPeriod parameter, a NMIRSn will be forced.
Return: None.

uint16_t SysCtl_getNMIWatchdogPeriod(void)¶

Gets the NMI watchdog period value.

Return: Returns the NMI watchdog period register’s current value.

uint32_t SysCtl_getNMIShadowFlagStatus(void)¶

Read NMI Shadow Flags.

Read the current state of individual NMI interrupts

Return

Value of NMISHDFLG register. These defines are provided to decode the value:

SYSCTL_NMI_NMIINT - NMI Interrupt Flag
SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag
SYSCTL_NMI_UNCERR - Flash/RAM/ROM Uncorrectable Error NMI Flag
SYSCTL_NMI_REGPARITYERR - Register parity error
SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag
SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag
SYSCTL_NMI_SYSDBGNMI - System Debug Module NMI Flag
SYSCTL_NMI_CLBNMI - Reconfigurable Logic NMI Flag
SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag
SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag
SYSCTL_NMI_LSCMPERR - Lockstep Compare Error
SYSCTL_NMI_ECATNMIN - EtherCAT NMI Flag
SYSCTL_NMI_CRC_FAIL - BGCRC calculation failed.
SYSCTL_NMI_SWERR - SW Error Force NMI Flag

bool SysCtl_isNMIShadowFlagSet(uint16_t nmiFlags)¶

Check if the individual NMI shadow flags are set.

Check if interrupt flags corresponding to the passed in bit mask are asserted.

Parameters

nmiFlags: Bit mask of the NMI interrupts that user wants to clear. The bit format of this parameter is same as of the NMIFLG register. These defines are provided:
- SYSCTL_NMI_NMIINT - NMI Interrupt Flag
- SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag
- SYSCTL_NMI_UNCERR - Flash/RAM/ROM Uncorrectable Error NMI Flag
- SYSCTL_NMI_REGPARITYERR - Register parity error
- SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag
- SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag
- SYSCTL_NMI_SYSDBGNMI - System Debug Module NMI Flag
- SYSCTL_NMI_CLBNMI - Reconfigurable Logic NMI Flag
- SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag
- SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag
- SYSCTL_NMI_LSCMPERR - Lockstep Compare Error
- SYSCTL_NMI_ECATNMIN - EtherCAT NMI Flag
- SYSCTL_NMI_CRC_FAIL - BGCRC calculation failed.
- SYSCTL_NMI_SWERR - SW Error Force NMI Flag

Return: true if any of the NMI asked for in the parameter bit mask is set. false if none of the NMI requested in the parameter bit mask are set.

void SysCtl_enableMCD(void)¶

Enable the missing clock detection (MCD) Logic

Return: None.

void SysCtl_disableMCD(void)¶

Disable the missing clock detection (MCD) Logic

Return: None.

bool SysCtl_isMCDClockFailureDetected(void)¶

Get the missing clock detection Failure Status

Note: A failure means the oscillator clock is missing
Return: Returns true if a failure is detected or false if a failure isn’t detected

void SysCtl_resetMCD(void)¶

Reset the missing clock detection logic after clock failure

Return: None.

void SysCtl_connectMCDClockSource(void)¶

Re-connect missing clock detection clock source to stop simulating clock failure

Return: None.

void SysCtl_disconnectMCDClockSource(void)¶

Disconnect missing clock detection clock source to simulate clock failure. This is for testing the MCD functionality.

Return: None.

void SysCtl_lockAccessControlRegs(void)¶

Lock the Access Control Registers

This function locks the access control registers and puts them in a read-only state.

Note: Only a reset can unlock the access control registers.
Return: None.

void SysCtl_setPeripheralAccessControl(SysCtl_AccessPeripheral peripheral, SysCtl_AccessController controller, SysCtl_AccessPermission permission)¶

Set the peripheral access control permissions

This function sets the specified peripheral access control permissions for the the specified controller

Parameters

peripheral: is the selected peripheral
controller: is the selected controller
permission: is the selected access permissions

The peripheral parameter can have one enumerated value in the format of SYSCTL_ACCESS_X where X is the name of the peripheral instance to be configured such as SYSCTL_ACCESS_ADCA.

The controller parameter can have one the following enumerated values:

SYSCTL_ACCESS_CPUX
SYSCTL_ACCESS_CLA1
SYSCTL_ACCESS_DMA1

The permission parameter can have one the following enumerated values:

SYSCTL_ACCESS_FULL - Full Access for both read and write
SYSCTL_ACCESS_PROTECTED - Protected read access such that FIFOs, clear on read registers are not changed, and no write access
SYSCTL_ACCESS_NONE - No read or write access

Return: None.

uint16_t SysCtl_getPeripheralAccessControl(SysCtl_AccessPeripheral peripheral, SysCtl_AccessController controller)¶

Get the peripheral access control permissions

This function gets the specified peripheral access control permissions for the the specified controller

Parameters

peripheral: is the selected peripheral
controller: is the selected controller

The peripheral parameter can have one enumerated value in the format of SYSCTL_ACCESS_X where X is the name of the peripheral instance to be configured such as SYSCTL_ACCESS_ADCA.

The controller parameter can have one the following enumerated values:

SYSCTL_ACCESS_CPUX
SYSCTL_ACCESS_CLA1
SYSCTL_ACCESS_DMA1

Return

Returns one of the following enumerated permission values:

SYSCTL_ACCESS_FULL - Full Access for both read and write
SYSCTL_ACCESS_PROTECTED - Protected read access such that FIFOs, clear on read registers are not changed, and no write access
SYSCTL_ACCESS_NONE - No read or write access

void SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc)¶

Configures the sync output source.

This function configures the sync output source from the ePWM modules. The

syncSrc parameter is a value SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT

Parameters

syncSrc: is sync output source selection.

Return: None.

void SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc)¶

Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal.

This function configures which ePWM SOC signals are enabled as a source for either ADCSOCAO or ADCSOCBO. The

adcsocSrc parameter takes a logical OR of SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different signals.

Parameters

adcsocSrc: is a bit field of the selected signals to be enabled

Return: None.

void SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc)¶

Disables ePWM SOC signals from driving an external ADCSOC signal.

This function configures which ePWM SOC signals are disabled as a source for either ADCSOCAO or ADCSOCBO. The

adcsocSrc parameter takes a logical OR of SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different signals.

Parameters

adcsocSrc: is a bit field of the selected signals to be disabled

Return: None.

void SysCtl_lockExtADCSOCSelect(void)¶

Locks the SOC Select of the Trig X-BAR.

This function locks the external ADC SOC select of the Trig X-BAR.

Return: None.

void SysCtl_lockSyncSelect(void)¶

Locks the Sync Select of the Trig X-BAR.

This function locks Sync Input and Output Select of the Trig X-BAR.

Return: None.

void SysCtl_selectCPUForPeripheralInstance(SysCtl_CPUSelPeriphInstance peripheral, SysCtl_CPUSel cpuInst)¶

Configures whether a peripheral is connected to CPU1 or CPU2.

The

peripheral parameter can have one enumerated value from SysCtl_CPUSelPeriphInstance

Parameters

peripheral: is the peripheral for which CPU needs to be configured.
cpuInst: is the CPU to which the peripheral instance need to be connected.

The cpuInst parameter can have one the following values:

SYSCTL_CPUSEL_CPU1 - to connect to CPU1
SYSCTL_CPUSEL_CPU2 - to connect to CPU2

Note: This API is applicable only for the CPU1 subsystem.
Return: None.

uint32_t SysCtl_getDeviceRevision(void)¶

Get the Device Silicon Revision ID

This function returns the silicon revision ID for the device.

Note: This API is applicable only for the CPU1 subsystem.
Return: Returns the silicon revision ID value.

void SysCtl_lockCPUSelectRegs(SysCtl_CPUSelPeripheral peripheral)¶

Locks the CPU select registers for the peripherals

The

peripheral parameter can have one enumerated value from SysCtl_CPUSelPeripheral

Parameters

peripheral: is the peripheral for which CPU needs to be selected.

Note: This API is applicable only for the CPU1 subsystem.
Return: None.

bool SysCtl_isCPU2Reset(void)¶

Check if the CPU2 is held in reset or not

Provides the reset status of CPU2 to CPU1

Note: This API is applicable only for the CPU1 subsystem.
Return: true if CPU2 core is in reset false if CPU2 core is out of reset

uint16_t SysCtl_getCPU2ResetStatus(void)¶

Gets the status/causes of the CPU2 reset.

The function provides causes of the CPU2 being in reset / not. This could be either of the following values or a combination of both:

SYSCTL_RSTSTAT_CPU2RES
SYSCTL_RSTSTAT_CPU2NMIWDRST
SYSCTL_RSTSTAT_CPU2HWBISTRST

Note: This API is applicable only for the CPU1 subsystem.
Return: Reset cause of CPU2.

void SysCtl_clearCPU2ResetStatus(uint16_t rstCauses)¶

Clears the CPU2 reset status.

This function clears the CPU2 reset status. This could be either of the following values or a combination of both:

Parameters

rstCauses: are the reset causes to be cleared

SYSCTL_RSTSTAT_CPU2NMIWDRST
SYSCTL_RSTSTAT_CPU2HWBISTRST.

To check if it was set first, see SysCtl_getCPU2ResetStatus().

Note: This API is applicable only for the CPU1 subsystem.
Return: None.

uint16_t SysCtl_getCPU2LPMStatus(void)¶

Gets the state of the CPU2.

The function indicates the power mode of the CPU2. It could be either in ACTIVE , IDLE or STANDBY mode.

Note: This API is applicable only for the CPU1 subsystem.
Return: Power mode of CPU2.

uint16_t SysCtl_getSemOwner(void)¶

Gets the Ownership details for clock configuration

A CPU can perform read/writes to any of the CLKCFG registers only if it owns the semaphore. Otherwise, writes are ignored and reads will return 0x0.

Note: Reads and writes of this ownership register are always allowed from both CPU1 and CPU2.
Return: Clock control Ownership details

void SysCtl_setXClk(SysCtl_XClkDivider divider)¶

Sets up XCLK divider.

This function sets up the XCLK divider. There is only one divider that scales INTOSC1 to XCLK.

Parameters

divider: is the value that configures the divider.

The divider parameter can have one enumerated value from SysCtl_XClkDivider

Return: None.

void SysCtl_setECatClk(SysCtl_ECatClkDivider divider, SysCtl_PLLClockSource source, uint16_t enable)¶

Sets up Ethercat CLK source, divider & PHY clock.

This function sets up the Ethercat CLK divider based on the source that is selected. There is only one divider that scales the “source” to Ethercat CLK. This also enables/disables the etherCAT PHY clock.

Parameters

divider: is the value that configures the divider.
source: is the source for the clock divider
enable: enables/disables the etherCAT PHY clock

The divider parameter can have one enumerated value from SysCtl_ECatClkDivider The source parameter can have one enumerated value from SysCtl_PLLClockSource The enable parameter can be either of these values: 0x0U: etherCAT PHY clock is disabled 0x1U: etherCAT PHY clock is enabled

Return: None.

void SysCtl_setPLLSysClk(uint16_t divider)¶

Sets up PLLSYSCLK divider.

This function sets up the PLLSYSCLK divider. There is only one divider that scales PLLSYSCLK to generate the system clock.

Parameters

divider: is the value that configures the divider.

The divider parameter can have any value (even/odd) from 1-126

Return: None.
Note: Please make sure to check if the PLL is locked and valid using the SysCtl_isPLLValid() before setting the divider.

void SysCtl_setAuxPLLClk(SysCtl_AuxPLLClkDivider divider)¶

Sets up AUXPLLCLK divider.

This function sets up the AUXPLLCLK divider. There is only one divider that scales AUXPLLCLK to generate the system clock.

Parameters

divider: is the value that configures the divider.

The divider parameter can have one enumerated value from SysCtl_AuxPLLClkDivider

Return: None.
Note: Please make sure to check if the PLL is locked and valid using the SysCtl_isPLLValid() before setting the divider.

void SysCtl_setMCANClk(SysCtl_MCANInstance mcanInst, SysCtl_MCANClkDivider divider)¶

Sets up MCAN Clk divider.

This function sets up the MCANCLK divider. There is only one divider that scales MCAN clock.

Parameters

mcanInst: is the MCAN instance
divider: is the value that configures the divider.

The mcanInst parameter can have one enumerated value from SysCtl_MCANInstance The divider parameter can have one enumerated value from SysCtl_MCANClkDivider

Return: None.

void SysCtl_setCputimer2Clk(SysCtl_Cputimer2ClkDivider divider, SysCtl_Cputimer2ClkSource source)¶

Sets up CPU Timer 2 CLK source & divider.

This function sets up the CPU Timer 2 CLK divider based on the source that is selected. There is only one divider that scales the “source” to CPU Timer 2 CLK.

Parameters

divider: is the value that configures the divider.
source: is the source for the clock divider

The divider parameter can have one enumerated value from SysCtl_Cputimer2ClkDivider The source parameter can have one enumerated value from SysCtl_Cputimer2ClkSource

Return: None.

void SysCtl_enableEthercatI2Cloopback(void)¶

Enables the Ethercat I2C loopback.

This function enables the Ethercat I2C loopback. Note that the Ethercat I2C loopback is disabled on reset.

Return: None.

void SysCtl_disableEthercatI2Cloopback(void)¶

Disables the Ethercat I2C loopback.

This function disables the Ethercat I2C loopback.Note that the Ethercat I2C loopback is enabled on reset.

Return: None.

uint32_t SysCtl_getPIEVErrAddr(void)¶

Gets the PIE Vector Fetch Error Handler Routine Address.

The function indicates the address of the PIE Vector Fetch Error handler routine.

Return: Error Handler Address.
Note: Its the responsibility of user to initialize this register. If this register is not initialized, a default error handler at address 0x3fffbe will get executed.

void SysCtl_simulateReset(uint32_t rstCauses)¶

Simulates a reset to the CPU1

The

rstCauses parameter can be one/ more of these values: SYSCTL_SIMRESET_CPU1RSN or SYSCTL_SIMRESET_XRSN

Parameters

rstCauses: is the cause for the reset.

Return: None.
Note: This API exists only on CPU1

uint32_t SysCtl_getInterruptStatus(void)¶

Gets the status of interrupts due to multiple different errors in the system.

Return

the Interrupt generated on the system. The values can be one/ more from:

SYSCTL_STATUS_EMIF_ERR
SYSCTL_STATUS_CORRECTABLE_ERR
SYSCTL_STATUS_RAM_ACC_VIOL
SYSCTL_STATUS_SYS_PLL_SLIP
SYSCTL_STATUS_AUX_PLL_SLIP
SYSCTL_STATUS_DCC0
SYSCTL_STATUS_DCC1
SYSCTL_STATUS_DCC2
SYSCTL_STATUS_AES_BUS_ERROR
SYSCTL_STATUS_EPG1_INT

void SysCtl_clearInterruptStatus(uint32_t intFlags)¶

Clears the interrupts due to multiple different errors in the system.

The

intFlags parameter are the Interrupts generated on errors in the system that need to be cleared. The values can be one or more from:

SYSCTL_STATUS_GINT
SYSCTL_STATUS_EMIF_ERR
SYSCTL_STATUS_CORRECTABLE_ERR
SYSCTL_STATUS_RAM_ACC_VIOL
SYSCTL_STATUS_SYS_PLL_SLIP
SYSCTL_STATUS_AUX_PLL_SLIP
SYSCTL_STATUS_DCC0
SYSCTL_STATUS_DCC1
SYSCTL_STATUS_DCC2
SYSCTL_STATUS_AES_BUS_ERROR
SYSCTL_STATUS_EPG1_INT

Parameters

intFlags: is the interrupt that needs to be cleared.

Return: None.

void SysCtl_setInterruptStatus(uint32_t intFlags)¶

Sets the interrupts for the multiple different errors in the system.

The

intFlags parameter are the Interrupts that can be set for the errors in the system. The values can be one/ more from:

SYSCTL_STATUS_EMIF_ERR
SYSCTL_STATUS_CORRECTABLE_ERR
SYSCTL_STATUS_RAM_ACC_VIOL
SYSCTL_STATUS_SYS_PLL_SLIP
SYSCTL_STATUS_AUX_PLL_SLIP
SYSCTL_STATUS_DCC0
SYSCTL_STATUS_DCC1
SYSCTL_STATUS_DCC2
SYSCTL_STATUS_AES_BUS_ERROR
SYSCTL_STATUS_EPG1_INT

Parameters

intFlags: is the interrupt that needs to be set.

Return: None.
Note: This API is present only on CPU1.

uint32_t SysCtl_getInterruptStatusMask(void)¶

Gets the masked interrupts due to multiple different errors in the system.

Return

the Interrupt generated on the system. The values can be one/ more from:

SYSCTL_STATUS_EMIF_ERR
SYSCTL_STATUS_CORRECTABLE_ERR
SYSCTL_STATUS_RAM_ACC_VIOL
SYSCTL_STATUS_SYS_PLL_SLIP
SYSCTL_STATUS_AUX_PLL_SLIP
SYSCTL_STATUS_DCC0
SYSCTL_STATUS_DCC1
SYSCTL_STATUS_DCC2
SYSCTL_STATUS_AES_BUS_ERROR
SYSCTL_STATUS_EPG1_INT

void SysCtl_setInterruptStatusMask(uint32_t intFlags)¶

Masks the interrupts for the multiple different errors in the system.

The

intFlags parameter are the Interrupts that can be masked for the errors in the system. The values can be one/ more from:

SYSCTL_STATUS_EMIF_ERR
SYSCTL_STATUS_CORRECTABLE_ERR
SYSCTL_STATUS_RAM_ACC_VIOL
SYSCTL_STATUS_SYS_PLL_SLIP
SYSCTL_STATUS_AUX_PLL_SLIP
SYSCTL_STATUS_DCC0
SYSCTL_STATUS_DCC1
SYSCTL_STATUS_DCC2
SYSCTL_STATUS_AES_BUS_ERROR
SYSCTL_STATUS_EPG1_INT

Parameters

intFlags: is the interrupt that needs to be set.

Return: None.
Note: This API is present only on CPU1.

void SysCtl_lockConfigRegs(SysCtl_DeviceConf regs)¶

Locks the Device configuration registers

This function locks the Device configuration registers.

Note: This API is applicable only for the CPU1 subsystem.
Return: None.

void SysCtl_CLBClkConfig(SysCtl_CLBInst inst, SysCtl_CLBClkm config)¶

Sets up CLB CLK configurations for a particuler CLB.

This function sets up the CLB CLK configurations based on the instance that is selected.

Parameters

inst: is the CLB instance that needs clock settings.
config: is the mode for the clock

The inst parameter can have one enumerated value from SysCtl_CLBInst The config parameter can have one enumerated value from SysCtl_CLBClkm

Return: None.

bool SysCtl_isErrorTriggered(void)¶

Check if One or more of the error sources triggered

Following are the events/triggers that can indicate an error:

nmi interrupt on C28x
Watchdog reset
Error on a Pie vector fetch
Efuse error
nmi interrupt on CM

Return
true if the error is triggered false if the error is not triggered

bool SysCtl_getErrorPinStatus(void)¶

Check if Error status pin is high or not

Return: true if the error status pin is high false if the error status pin is low

void SysCtl_forceError(void)¶

Forces an error flag to set to indicate an error being generated.

Return: None.

void SysCtl_clearError(void)¶

Clears any error flag set due to error generated.

Return: None.

void SysCtl_selectErrPinPolarity(uint16_t pol)¶

Selects the polarity of the error pin

The

pol parameter can take any of the below values: 0x0U: If an error is already triggered, Error pin will be driven with a value of 0, else 1. 0x1U: If an error is already triggered, Error pin will be driven with a value of 1, else 0.

Parameters

pol: is the ERROR pin polarity

Return: None.

void SysCtl_lockErrControl(void)¶

Locks the Error control registers

This function locks the Error configuration registers.

Return: None.
Note: The lock register is cleared only on a system reset.

bool SysCtl_isMCANWakeStatusSet(SysCtl_MCANInstance mcanInst)¶

Check if the MCAN wakeup event has occured.

The

mcanInst parameter can have one enumerated value from SysCtl_MCANInstance

Parameters

mcanInst: is the MCAN instance

Return: true if the MCAN wakeup event has occured. false if the MCAN wakeup event has not occured.

void SysCtl_clearMCANWakeStatus(SysCtl_MCANInstance mcanInst)¶

Clears the MCAN wakeup event status.

This function clears the MCAN wakeup event status. To check if it was set first, see

SysCtl_isMCANWakeStatusSet().

Parameters

mcanInst: is the MCAN instance

The mcanInst parameter can have one enumerated value from SysCtl_MCANInstance

Return: None.

void SysCtl_setUserRegister(SysCtl_UserRegister reg, uint32_t value)¶

Sets the user register.

This function sets sepcified user register. The

value parameter can have one enumerated value from SysCtl_UserRegister.

Parameters

reg: is the register to be set
value: is the value to be set

Return: None.

uint32_t SysCtl_getUserRegister(SysCtl_UserRegister reg)¶

Gets the user register.

This function sets sepcified user register. The

value parameter can have one enumerated value from SysCtl_UserRegister.

Parameters

reg: is the register to be set

Return: value of the specified register.

void SysCtl_setLFUCPU(uint16_t value)¶

Sets the LFU_CPU configuration

Note

This bit is used by compiler/application code for implementing CPU LFU

Return

None

Parameters

value: is the value to be set.
- 0 : No pending requests
- 1 : LFU Request in progress

uint16_t SysCtl_getLFUCPU(void)¶

Gets the LFU_CPU configuration

Note: This bit is used by compiler/application code for implementing CPU LFU
Return: 0 if No pending requests, 1 if LFU Request is in progress

void SysCtl_setLFUCLA1(uint16_t value)¶

Sets the LFU_CLA configuration

Note

This bit is used by compiler/application code for implementing CLA LFU

Return

None

Parameters

value: is the value to be set.
- 0 : No pending requests
- 1 : LFU Request in progress

uint16_t SysCtl_getLFUCLA1(void)¶

Gets the LFU_CLA configuration

Note: This bit is used by compiler/application code for implementing CLA LFU
Return: 0 if No pending requests, 1 if LFU Request is in progress

void SysCtl_swapPieVectorAndLS01(bool swap)¶

Swap PIE Vector Table to alternate location and swap LS0 and LS1

Return

None

Parameters

swap: Whether to enable or disable swap
- true : PIE Vector Table is swapped to alternate location. LS0 and LS1 is swapped
- false : PIE vector table is mapped to the original location LS0 and LS1 is mapped to original location

void SysCtl_swapPieVector(bool swap)¶

Swap PIE Vector Table to alternate location

Return

None

Parameters

swap: Whether to enable or disable swap
- true : PIE Vector Table is swapped to alternate location
- false : PIE vector table is mapped to the original location

bool SysCtl_isPieVectorSwap(void)¶

Checks if the PIE Vector Table is swapped or not

Return

true if the PIE Vector Table is mapped to original location, false if PIE Vector Table is swapped to alternate location

Parameters

reg: is the register to be set
value: is the value to be set

void SysCtl_swapLS01(bool swap)¶

Swap LS0 and LS1

Return

None

Parameters

swap: Whether to enable or disable swap
- true : LS0 and LS1 is swapped
- false : LS0 and LS1 is mapped to original location

bool SysCtl_isLS01Swap(void)¶

Checks if the LS0 and LS1 are swapped or not

Return

true if the LS0 and LS1 is mapped to original location, false if LS0 and LS1 is swapped

Parameters

reg: is the register to be set
value: is the value to be set

void SysCtl_setLFUUserRegister(SysCtl_LFUUserRegister reg, uint32_t value)¶

Sets the user register.

This function sets specified LFU user register. The

value parameter can have one enumerated value from SysCtl_LFUUserRegister.

Parameters

reg: is the register to be set
value: is the value to be set

Return: None.

uint32_t SysCtl_getLFUUserRegister(SysCtl_LFUUserRegister reg)¶

Gets the user register.

This function sets specified LFU user register. The

value parameter can have one enumerated value from SysCtl_LFUUserRegister.

Parameters

reg: is the register to be set

Return: value of the specified register.

void SysCtl_lockLFUConfigRegister(void)¶

Locks the LFUConfig register

Return: None.

void SysCtl_lockLFUUserRegister(SysCtl_LFUUserRegister reg)¶

Locks the LFU User registers

Return

None.

Parameters

register: to be locked

void SysCtl_unlockLFUConfigRegister(void)¶

Unlocks the LFUConfig register

Return: None.

void SysCtl_unlockLFUUserRegister(SysCtl_LFUUserRegister reg)¶

Unlocks the LFU User registers

Return

None.

Parameters

register: to be unlocked

void SysCtl_commitLFUConfigRegister(void)¶

Commits the LFUConfig register

Return: None.

void SysCtl_commitLFUUserRegister(SysCtl_LFUUserRegister reg)¶

Commits the LFU User registers

Return

None.

Parameters

register: to be committed

void SysCtl_allocateFlashBank(SysCtl_FlashBank flashBank, SysCtl_CPUSel cpu)¶

Allocates the Flash Bank to selected CPU

Note

This function should be called from CPU1 only

Return

None.

Parameters

flashBank: is Flash bank to be configured (SYSCTL_FLASH_BANK0-4)
cpu: is the CPU to be allocated to (SYSCTL_CPUSEL_CPU1/2)

void SysCtl_allocateDxRAM(SysCtl_SharedDxRAM ram, SysCtl_CPUSel cpu)¶

Allocates the DxRAM to selected CPU

Note

D0 and D1 RAMs are available only on CPU1. D2-5 RAMs can be allocated to CPU1 or CPU2

Note

This function should be called from CPU1 only

Return

None.

Parameters

ram: is DxRAM to be configured (SYSCTL_D2RAM - SYSCTL_D5RAM)
cpu: is the CPU to be allocated to (SYSCTL_CPUSEL_CPU1/2)

void SysCtl_lockDxRAMConfig(void)¶

Locks the DxRAM configuration

Note: This function should be called from CPU1 only
Return: None.

uint32_t SysCtl_getDeviceUID0(void)¶

Get the device UID_UNIQUE0 value

This function returns the device UID_UNIQUE0 value

Return: Returns the device UID_UNIQUE0 value

uint32_t SysCtl_getDeviceUID1(void)¶

Get the device UID_UNIQUE1 value

This function returns the device UID_UNIQUE1 value

Return: Returns the device UID_UNIQUE1 value

uint32_t SysCtl_getTapStatus(void)¶

Get the status of JTAG State machine and debugger connect

This function returns the JTAG status

Return: Returns the JTAG status. The bits representing will be - 0:TLR, 1:IDLE, 2:SELECTDR, 3:CAPDR, 4:SHIFTDR, 5:EXIT1DR, 6:PAUSEDR, 7:EXIT2DR, 8:UPDTDR, 9:SLECTIR, 10:CAPIR, 11:SHIFTIR, 12:EXIT1IR, 13:PAUSEIR, 14:EXIT2IR, 15:UPDTIR

void SysCtl_delay(uint32_t count)¶

Delays for a fixed number of cycles.

This function generates a constant length delay using assembly code. The loop takes 5 cycles per iteration plus 9 cycles of overhead.

Parameters

count: is the number of delay loop iterations to perform.

Note: If count is equal to zero, the loop will underflow and run for a very long time.
Note: Refer to the macro DEVICE_DELAY_US(x) in device.h which can be used to insert a delay in microseconds.
Return: None.

uint32_t SysCtl_getClock(uint32_t clockInHz)¶

Calculates the system clock frequency (SYSCLK).

This function determines the frequency of the system clock based on the frequency of the oscillator clock source (from

clockInHz) and the PLL and clock divider configuration registers.

Parameters

clockInHz: is the frequency of the oscillator clock source (OSCCLK).

Return: Returns the system clock frequency. If a missing clock is detected, the function will return the INTOSC1 frequency. This needs to be corrected and cleared (see SysCtl_resetMCD()) before trying to call this function again.

uint32_t SysCtl_getAuxClock(uint32_t clockInHz)¶

Calculates the system auxiliary clock frequency (AUXPLLCLK).

This function determines the frequency of the auxiliary clock based on the frequency of the oscillator clock source (from

clockInHz) and the AUXPLL and clock divider configuration registers.

Parameters

clockInHz: is the frequency of the oscillator clock source (AUXOSCCLK).

Return: Returns the auxiliary clock frequency.

bool SysCtl_setClock(uint32_t config)¶

Configures the clocking of the device.

This function configures the clocking of the device. The input crystal frequency, oscillator to be used, use of the PLL, and the system clock divider are all configured with this function.

Parameters

config: is the required configuration of the device clocking.

The config parameter is the OR of several different values, many of which are grouped into sets where only one can be chosen.

The system clock divider is chosen with the macro SYSCTL_SYSDIV(x) where x is either 1 or an even value up to 126.
The use of the PLL is chosen with ONLY one of the below modes: SYSCTL_PLL_ENABLE - This is to Enable the PLL Clock to the System or SYSCTL_PLL_BYPASS -This is to Bypass the PLLCLK from the System, this will also power up the PLL if the user desires to power up the PLL but not use it for System. or SYSCTL_PLL_DISABLE-This is to Power Down the PLL and Bypass the PLLCLK to the System.
The integer multiplier is chosen SYSCTL_IMULT(x) where x is a value from 1 to 127.
The oscillator source chosen with SYSCTL_OSCSRC_OSC2, SYSCTL_OSCSRC_XTAL, SYSCTL_OSCSRC_XTAL_SE or SYSCTL_OSCSRC_OSC1.

This function uses the DCC to check that the PLLRAWCLK is running at the expected rate. If you are using the DCC, you must back up its configuration before calling this function and restore it afterward. Locking PLL sequence is only done if the multipliers are updated.

Note: See your device errata for more details about locking the PLL.
Return: Returns false if a missing clock error is detected. This needs to be cleared (see SysCtl_resetMCD()) before trying to call this function again. Also, returns false if the PLLRAWCLK is not running and its expected rate. Otherwise, returns true.

bool SysCtl_isPLLValid(uint32_t base, uint32_t oscSource, SysCtl_PLLClockSource pllclk, uint32_t pllMultDiv)¶

Validates PLL Raw Clock Frequency (PLLRAWCLK)

This function uses DCC module to validate the PLL clock frequency. It uses oscSource as a reference clock for DCC, and PLL is used as clock under test. As long as the Counter0 (running of oscSource) & Counter1 (running of PLL) expire at the same time, DCC will not generate an Error. This function gives 100 attempts for PLL to lock and make sure frequency is as expected.

Parameters

base: is the DCC module base address
oscSource: is the Clock Source for the PLL that is also used for DCC
pllclk: is the PLL Clock which has to be validated.
pllMultDiv: has the PLL Multiplier Register configuration which include integer multiplier and divider values used to configure the DCC Counter1 clock

The oscSource parameter is the oscillator source chosen with SYSCTL_OSCSRC_OSC2, SYSCTL_OSCSRC_XTAL, SYSCTL_OSCSRC_XTAL_SE or SYSCTL_OSCSRC_OSC1.
The pllclk parameter can have one enumerated value from SysCtl_PLLClockSource
The pllMultDiv parameter is a bitwise OR of SYSCTL_IMULT(x) where x is a value from 1 to 127 and both of the following divider values which is chosen with the macro SYSCTL_REFDIV(x) and SYSCTL_ODIV(x) where x is a value from 1 to 32 and can be different for both macros.

Return
Returns true if the DCCSTATUS error flag is not set. Otherwise, returns false.

Note: This function does not validate if PLL output frequency (PLLRAWCLK) is within the operating range as per the datasheet.

void SysCtl_selectXTAL(void)¶

Configures the external oscillator for the clocking of the device.

This function configures the external oscillator (XTAL) to be used for the clocking of the device in crystal mode. It follows the procedure to turn on the oscillator, wait for it to power up, and select it as the source of the system clock.

Please note that this function blocks while it waits for the XTAL to power up. If the XTAL does not manage to power up properly, the function will loop for a long time. It is recommended that you modify this function to add an appropriate timeout and error-handling procedure.

Return: None.

void SysCtl_selectXTALSingleEnded(void)¶

Configures the external oscillator for the clocking of the device in single-ended mode.

This function configures the external oscillator (XTAL) to be used for the clocking of the device in single-ended mode. It follows the procedure to turn on the oscillator, wait for it to power up, and select it as the source of the system clock.

Please note that this function blocks while it waits for the XTAL to power up. If the XTAL does not manage to power up properly, the function will loop for a long time. It is recommended that you modify this function to add an appropriate timeout and error-handling procedure.

Return: None.

void SysCtl_selectOscSource(uint32_t oscSource)¶

Selects the oscillator to be used for the clocking of the device.

This function configures the oscillator to be used in the clocking of the device. The

oscSource parameter may take a value of SYSCTL_OSCSRC_OSC2, SYSCTL_OSCSRC_XTAL, SYSCTL_OSCSRC_XTAL_SE, or SYSCTL_OSCSRC_OSC1.

Parameters

oscSource: is the oscillator source to be configured.

See: SysCtl_turnOnOsc()
Return: None.

void SysCtl_selectOscSourceAuxPLL(uint32_t oscSource)¶

Selects the oscillator to be used for the AUXPLL.

This function configures the oscillator to be used in the clocking of the AUXPLL. The

oscSource parameter may take a value of SYSCTL_OSCSRC_OSC2, SYSCTL_OSCSRC_XTAL, SYSCTL_OSCSRC_XTAL_SE, or SYSCTL_OSCSRC_OSC1.

Parameters

oscSource: is the oscillator source to be configured.

See: SysCtl_turnOnOsc()
Return: None.

uint32_t SysCtl_getLowSpeedClock(uint32_t clockInHz)¶

Calculates the low-speed peripheral clock frequency (LSPCLK).

This function determines the frequency of the low-speed peripheral clock based on the frequency of the oscillator clock source (from

clockInHz) and the PLL and clock divider configuration registers.

Parameters

clockInHz: is the frequency of the oscillator clock source (OSCCLK).

Return: Returns the low-speed peripheral clock frequency.

uint16_t SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric)¶

Get the device part parametric value

This function gets the device part parametric value.

Parameters

parametric: is the requested device parametric value

The parametric parameter can have one the following enumerated values:

SYSCTL_DEVICE_QUAL - Device Qualification Status
SYSCTL_DEVICE_PINCOUNT - Device Pin Count
SYSCTL_DEVICE_FLASH - Device Flash size (KB)
SYSCTL_DEVICE_FAMILY - Device Family
SYSCTL_DEVICE_PARTNO - Device Part Number
SYSCTL_DEVICE_CLASSID - Device Class ID

Note: This API is applicable only for the CPU1 subsystem.
Return: Returns the specified parametric value.

void SysCtl_setAuxClock(uint32_t config)¶

Configures the auxiliary PLL.

This function configures the clock source for auxiliary PLL, the integer multiplier, fractional multiplier and divider.

Parameters

config: is the required configuration of the device clocking.

The config parameter is the OR of several different values, many of which are grouped into sets where only one can be chosen.

The system clock divider is chosen with one of the following macros: SYSCTL_AUXPLL_DIV_1, SYSCTL_AUXPLL_DIV_2, SYSCTL_AUXPLL_DIV_4, SYSCTL_AUXPLL_DIV_8 SYSCTL_AUXPLL_DIV_3, SYSCTL_AUXPLL_DIV_5, SYSCTL_AUXPLL_DIV_6, SYSCTL_AUXPLL_DIV_7
The use of the PLL is chosen with ONLY one of the below modes: SYSCTL_AUXPLL_ENABLE - This is to Enable the PLL Clock to the System or SYSCTL_AUXPLL_BYPASS -This is to Bypass the PLLCLK from the System, this will also power up the PLL if the user desires to power up the PLL but not use it for System. or SYSCTL_AUXPLL_DISABLE-This is to Power Down the PLL and Bypass the PLLCLK to the System.
The integer multiplier is chosen with SYSCTL_AUXPLL_IMULT(x) where x is a value from 1 to 127.
The reference clock divider is chosen SYSCTL_AUXPLL_REFDIV((x) where x is a value from 1 to 32.
The output clock divider is chosen SYSCTL_AUXPLL_ODIV(x) where x is a value from 1 to 32.
The DCC module selected for checking PLL clock validity chosen with either SYSCTL_DCC_BASE_0, SYSCTL_DCC_BASE_1, or SYSCTL_DCC_BASE_2.
The oscillator source chosen with one of SYSCTL_AUXPLL_OSCSRC_OSC2, SYSCTL_AUXPLL_OSCSRC_XTAL, SYSCTL_AUXPLL_OSCSRC_AUXCLKIN, SYSCTL_AUXPLL_OSCSRC_XTAL_SE

Please note the PLL can take inputs from 2Mhz to 48Mhz. PLL can be locked from 220Mhz to 800Mhz. The output of PLL cannot be more than 500Mhz (after ODIV).

Note: This function uses the DCC to check that the AUXPLLRAWCLK is expected rate. If you are using the DCC, you must back up its configuration before calling this function and restore it afterward. Locking PLL sequence is only done if the multipliers are updated.

Note: See your device errata for more details about locking the PLL.
Return: None.

void SysCtl_controlCPU2Reset(SysCtl_CoreReset control)¶

Controls the reset of CPU2 by CPU1

The

control parameter can be a value from the enumeration SysCtl_CoreReset

Parameters

control: is to deactivate / activate the reset to the CPU2.

Note: This API is applicable only for the CPU1 subsystem.
Return: None.

void SysCtl_configureType(SysCtl_SelType type, uint16_t config, uint16_t lock)¶

Configures & locks/unlocks the peripheral type

The

type parameter can be a value from the enumeration SysCtl_SelType The config parameter can be a value from the ones below: 0x0U : disables the feature for the type. 0x1U : enables the feature for the type.

Parameters

type: is the peripheral type that needs to be configured.
config: is the configuration done to the peripheral which is dependent on the peripheral type.
lock: is to decide if writes for any further configuration is to be allowed or not.

For ECAP: ECAP registers are EALLOW protected or not. For SDFM: Data Ready conditions do not generate the SDFMINT. & Each filter generates a separate data ready interrupts. For USB : Global interrupt feature is enabled or not For MEMMAP: Enables remapping SDRAM in lower 64kb of address space or not.

The lock parameter can be a value from the ones below: 0x1U : Write for any further configuration is not allowed. 0x0U : Write for any further configuration is allowed.

Note: This API is applicable only for the CPU1 subsystem.
Return: None.

bool SysCtl_isConfigTypeLocked(SysCtl_SelType type)¶

Check if writes for any further configuration of peripheral types is to be allowed or not.

Note

This API is applicable only for the CPU1 subsystem.

Return

true if Write for any further configuration is not allowed. false if Write for any further configuration is allowed.

Parameters

type: is the peripheral type for which permissions are being checked

void SysCtl_setSemOwner(SysCtl_CPUSel cpuInst)¶

Sets the owner for clock configuration

The

cpuInst parameter can be a value from the enumeration SysCtl_CPUSel

Parameters

cpuInst: is owner for the clock configuration.

Return: None.

void SysCtl_lockClkConfig(SysCtl_ClkRegSel registerName)¶

Locks the Clock configuration registers

The

registerName parameter can be a value from the enumeration SysCtl_ClkRegSel

Parameters

registerName: is clock configuration register which needs to be locked.

Return: None.
Note: The register is unlocked only on a system reset.

void SysCtl_lockSysConfig(SysCtl_CpuRegSel registerName)¶

Locks the CPU system configuration registers

The

registerName parameter can be a value from the enumeration SysCtl_CpuRegSel

Parameters

registerName: is CPU system configuration register which needs to be locked.

Return: None.
Note: The register is unlocked only on a system reset.

void SysCtl_emulateDevice(SysCtl_DevicePartNumber partNumber)¶

configures the MCUCNF registers

The

partNumber parameter can be a value from the enumeration SysCtl_DevicePartNumber

Parameters

partNumber: is the device part number

Return: None.

Many of the functions provided by the SysCtl API are related to device clocking. The most important of these functions is SysCtl_setClock() which will configure which oscillator is to be used, configure the PLL, and configure the system clock divider. SysCtl_getClock() is a complementary function to this one that will, given the frequency of the oscillator source used, read back the configuration of the PLL and clock divider and calculate the system clock frequency. A similar pair of functions is provided for the low-speed peripheral clock, SysCtl_setLowSpeedClock() and SysCtl_getLowSpeedClock().

The ability to enable (turn on the module clock), disable (gate off the module clock), and perform a software reset on most of the peripherals on a device is provided by SysCtl_enablePeripheral(), SysCtl_disablePeripheral(), and SysCtl_resetPeripheral() respectively.

The device’s windowed watchdog is enabled and disabled by SysCtl_enableWatchdog() and SysCtl_disableWatchdog() respectively. The watchdog can be serviced by SysCtl_serviceWatchdog(). Several functions are also provided to configure the watchdog’s clock and windowed functionality.

This section will give further details of these functions and each of the others used for the configuration of SysCtl. These could include clock configurations, CPU selections, permissions, NMI setup, interrupts etc.

{color{red}textsc{Note: System error interrupts for PLL SLIP and Clock source control of INTOSC2 ON/OFF are not supported on this device. The required software changes are scoped for the next C2000Ware release and are not supported in this release. Users are advised to not use this feature on this device.}}

The code for this module is contained in driverlib/sysctl.c, with driverlib/sysctl.h containing the API declarations for use by applications.