//###########################################################################
// FILE:   hw_uart.h
// TITLE:  Macros and defines used when accessing the UART hardware.
//###########################################################################
// $TI Release: F28M35x Support Library v201 $
// $Release Date: Fri Jun  7 10:51:13 CDT 2013 $
//###########################################################################

#ifndef __HW_UART_H__
#define __HW_UART_H__

//*****************************************************************************
// The following are defines for the UART register offsets.
//*****************************************************************************
#define UART_O_DR              0x00000000   // UART Data
#define UART_O_RSR             0x00000004   // UART Receive Status/Error Clear
#define UART_O_ECR             0x00000004   // UART Receive Status/Error Clear
#define UART_O_FR              0x00000018   // UART Flag
#define UART_O_ILPR            0x00000020   // UART IrDA Low-Power Register
#define UART_O_IBRD            0x00000024   // UART Integer Baud-Rate Divisor
#define UART_O_FBRD            0x00000028   // UART Fractional Baud-Rate
                                            // Divisor
#define UART_O_LCRH            0x0000002C   // UART Line Control
#define UART_O_CTL             0x00000030   // UART Control
#define UART_O_IFLS            0x00000034   // UART Interrupt FIFO Level Select
#define UART_O_IM              0x00000038   // UART Interrupt Mask
#define UART_O_RIS             0x0000003C   // UART Raw Interrupt Status
#define UART_O_MIS             0x00000040   // UART Masked Interrupt Status
#define UART_O_ICR             0x00000044   // UART Interrupt Clear
#define UART_O_DMACTL          0x00000048   // UART DMA Control
#define UART_O_LCTL            0x00000090   // UART LIN Control
#define UART_O_LSS             0x00000094   // UART LIN Snap Shot
#define UART_O_LTIM            0x00000098   // UART LIN Timer

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_DR register.
//*****************************************************************************
#define UART_DR_OE             0x00000800   // UART Overrun Error
#define UART_DR_BE             0x00000400   // UART Break Error
#define UART_DR_PE             0x00000200   // UART Parity Error
#define UART_DR_FE             0x00000100   // UART Framing Error
#define UART_DR_DATA_M         0x000000FF   // Data Transmitted or Received
#define UART_DR_DATA_S         0

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_RSR register.
//*****************************************************************************
#define UART_RSR_OE            0x00000008   // UART Overrun Error
#define UART_RSR_BE            0x00000004   // UART Break Error
#define UART_RSR_PE            0x00000002   // UART Parity Error
#define UART_RSR_FE            0x00000001   // UART Framing Error

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_ECR register.
//*****************************************************************************
#define UART_ECR_DATA_M        0x000000FF   // Error Clear
#define UART_ECR_DATA_S        0

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_FR register.
//*****************************************************************************
#define UART_FR_RI             0x00000100   // Ring Indicator
#define UART_FR_TXFE           0x00000080   // UART Transmit FIFO Empty
#define UART_FR_RXFF           0x00000040   // UART Receive FIFO Full
#define UART_FR_TXFF           0x00000020   // UART Transmit FIFO Full
#define UART_FR_RXFE           0x00000010   // UART Receive FIFO Empty
#define UART_FR_BUSY           0x00000008   // UART Busy
#define UART_FR_DCD            0x00000004   // Data Carrier Detect
#define UART_FR_DSR            0x00000002   // Data Set Ready
#define UART_FR_CTS            0x00000001   // Clear To Send

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_ILPR register.
//*****************************************************************************
#define UART_ILPR_ILPDVSR_M    0x000000FF   // IrDA Low-Power Divisor
#define UART_ILPR_ILPDVSR_S    0

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_IBRD register.
//*****************************************************************************
#define UART_IBRD_DIVINT_M     0x0000FFFF   // Integer Baud-Rate Divisor
#define UART_IBRD_DIVINT_S     0

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_FBRD register.
//*****************************************************************************
#define UART_FBRD_DIVFRAC_M    0x0000003F   // Fractional Baud-Rate Divisor
#define UART_FBRD_DIVFRAC_S    0

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_LCRH register.
//*****************************************************************************
#define UART_LCRH_SPS          0x00000080   // UART Stick Parity Select
#define UART_LCRH_WLEN_M       0x00000060   // UART Word Length
#define UART_LCRH_WLEN_5       0x00000000   // 5 bits (default)
#define UART_LCRH_WLEN_6       0x00000020   // 6 bits
#define UART_LCRH_WLEN_7       0x00000040   // 7 bits
#define UART_LCRH_WLEN_8       0x00000060   // 8 bits
#define UART_LCRH_FEN          0x00000010   // UART Enable FIFOs
#define UART_LCRH_STP2         0x00000008   // UART Two Stop Bits Select
#define UART_LCRH_EPS          0x00000004   // UART Even Parity Select
#define UART_LCRH_PEN          0x00000002   // UART Parity Enable
#define UART_LCRH_BRK          0x00000001   // UART Send Break

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_CTL register.
//*****************************************************************************
#define UART_CTL_CTSEN         0x00008000   // Enable Clear To Send
#define UART_CTL_RTSEN         0x00004000   // Enable Request to Send
#define UART_CTL_RTS           0x00000800   // Request to Send
#define UART_CTL_DTR           0x00000400   // Data Terminal Ready
#define UART_CTL_RXE           0x00000200   // UART Receive Enable
#define UART_CTL_TXE           0x00000100   // UART Transmit Enable
#define UART_CTL_LBE           0x00000080   // UART Loop Back Enable
#define UART_CTL_LIN           0x00000040   // LIN Mode Enable
#define UART_CTL_HSE           0x00000020   // High-Speed Enable
#define UART_CTL_EOT           0x00000010   // End of Transmission
#define UART_CTL_SMART         0x00000008   // ISO 7816 Smart Card Support
#define UART_CTL_SIRLP         0x00000004   // UART SIR Low-Power Mode
#define UART_CTL_SIREN         0x00000002   // UART SIR Enable
#define UART_CTL_UARTEN        0x00000001   // UART Enable

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_IFLS register.
//*****************************************************************************
#define UART_IFLS_RX_M         0x00000038   // UART Receive Interrupt FIFO
                                            // Level Select
#define UART_IFLS_RX1_8        0x00000000   // RX FIFO >= 1/8 full
#define UART_IFLS_RX2_8        0x00000008   // RX FIFO >= 1/4 full
#define UART_IFLS_RX4_8        0x00000010   // RX FIFO >= 1/2 full (default)
#define UART_IFLS_RX6_8        0x00000018   // RX FIFO >= 3/4 full
#define UART_IFLS_RX7_8        0x00000020   // RX FIFO >= 7/8 full
#define UART_IFLS_TX_M         0x00000007   // UART Transmit Interrupt FIFO
                                            // Level Select
#define UART_IFLS_TX1_8        0x00000000   // TX FIFO <= 1/8 full
#define UART_IFLS_TX2_8        0x00000001   // TX FIFO <= 1/4 full
#define UART_IFLS_TX4_8        0x00000002   // TX FIFO <= 1/2 full (default)
#define UART_IFLS_TX6_8        0x00000003   // TX FIFO <= 3/4 full
#define UART_IFLS_TX7_8        0x00000004   // TX FIFO <= 7/8 full

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_IM register.
//*****************************************************************************
#define UART_IM_LME5IM         0x00008000   // LIN Mode Edge 5 Interrupt Mask
#define UART_IM_LME1IM         0x00004000   // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM         0x00002000   // LIN Mode Sync Break Interrupt
                                            // Mask
#define UART_IM_OEIM           0x00000400   // UART Overrun Error Interrupt
                                            // Mask
#define UART_IM_BEIM           0x00000200   // UART Break Error Interrupt Mask
#define UART_IM_PEIM           0x00000100   // UART Parity Error Interrupt Mask
#define UART_IM_FEIM           0x00000080   // UART Framing Error Interrupt
                                            // Mask
#define UART_IM_RTIM           0x00000040   // UART Receive Time-Out Interrupt
                                            // Mask
#define UART_IM_TXIM           0x00000020   // UART Transmit Interrupt Mask
#define UART_IM_RXIM           0x00000010   // UART Receive Interrupt Mask
#define UART_IM_DSRMIM         0x00000008   // UART Data Set Ready Modem
                                            // Interrupt Mask
#define UART_IM_DCDMIM         0x00000004   // UART Data Carrier Detect Modem
                                            // Interrupt Mask
#define UART_IM_CTSMIM         0x00000002   // UART Clear to Send Modem
                                            // Interrupt Mask
#define UART_IM_RIMIM          0x00000001   // UART Ring Indicator Modem
                                            // Interrupt Mask

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_RIS register.
//*****************************************************************************
#define UART_RIS_LME5RIS       0x00008000   // LIN Mode Edge 5 Raw Interrupt
                                            // Status
#define UART_RIS_LME1RIS       0x00004000   // LIN Mode Edge 1 Raw Interrupt
                                            // Status
#define UART_RIS_LMSBRIS       0x00002000   // LIN Mode Sync Break Raw
                                            // Interrupt Status
#define UART_RIS_OERIS         0x00000400   // UART Overrun Error Raw Interrupt
                                            // Status
#define UART_RIS_BERIS         0x00000200   // UART Break Error Raw Interrupt
                                            // Status
#define UART_RIS_PERIS         0x00000100   // UART Parity Error Raw Interrupt
                                            // Status
#define UART_RIS_FERIS         0x00000080   // UART Framing Error Raw Interrupt
                                            // Status
#define UART_RIS_RTRIS         0x00000040   // UART Receive Time-Out Raw
                                            // Interrupt Status
#define UART_RIS_TXRIS         0x00000020   // UART Transmit Raw Interrupt
                                            // Status
#define UART_RIS_RXRIS         0x00000010   // UART Receive Raw Interrupt
                                            // Status
#define UART_RIS_DSRRIS        0x00000008   // UART Data Set Ready Modem Raw
                                            // Interrupt Status
#define UART_RIS_DCDRIS        0x00000004   // UART Data Carrier Detect Modem
                                            // Raw Interrupt Status
#define UART_RIS_CTSRIS        0x00000002   // UART Clear to Send Modem Raw
                                            // Interrupt Status
#define UART_RIS_RIRIS         0x00000001   // UART Ring Indicator Modem Raw
                                            // Interrupt Status

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_MIS register.
//*****************************************************************************
#define UART_MIS_LME5MIS       0x00008000   // LIN Mode Edge 5 Masked Interrupt
                                            // Status
#define UART_MIS_LME1MIS       0x00004000   // LIN Mode Edge 1 Masked Interrupt
                                            // Status
#define UART_MIS_LMSBMIS       0x00002000   // LIN Mode Sync Break Masked
                                            // Interrupt Status
#define UART_MIS_OEMIS         0x00000400   // UART Overrun Error Masked
                                            // Interrupt Status
#define UART_MIS_BEMIS         0x00000200   // UART Break Error Masked
                                            // Interrupt Status
#define UART_MIS_PEMIS         0x00000100   // UART Parity Error Masked
                                            // Interrupt Status
#define UART_MIS_FEMIS         0x00000080   // UART Framing Error Masked
                                            // Interrupt Status
#define UART_MIS_RTMIS         0x00000040   // UART Receive Time-Out Masked
                                            // Interrupt Status
#define UART_MIS_TXMIS         0x00000020   // UART Transmit Masked Interrupt
                                            // Status
#define UART_MIS_RXMIS         0x00000010   // UART Receive Masked Interrupt
                                            // Status
#define UART_MIS_DSRMIS        0x00000008   // UART Data Set Ready Modem Masked
                                            // Interrupt Status
#define UART_MIS_DCDMIS        0x00000004   // UART Data Carrier Detect Modem
                                            // Masked Interrupt Status
#define UART_MIS_CTSMIS        0x00000002   // UART Clear to Send Modem Masked
                                            // Interrupt Status
#define UART_MIS_RIMIS         0x00000001   // UART Ring Indicator Modem Masked
                                            // Interrupt Status

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_ICR register.
//*****************************************************************************
#define UART_ICR_LME5MIC       0x00008000   // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC       0x00004000   // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC       0x00002000   // LIN Mode Sync Break Interrupt
                                            // Clear
#define UART_ICR_OEIC          0x00000400   // Overrun Error Interrupt Clear
#define UART_ICR_BEIC          0x00000200   // Break Error Interrupt Clear
#define UART_ICR_PEIC          0x00000100   // Parity Error Interrupt Clear
#define UART_ICR_FEIC          0x00000080   // Framing Error Interrupt Clear
#define UART_ICR_RTIC          0x00000040   // Receive Time-Out Interrupt Clear
#define UART_ICR_TXIC          0x00000020   // Transmit Interrupt Clear
#define UART_ICR_RXIC          0x00000010   // Receive Interrupt Clear
#define UART_ICR_DSRMIC        0x00000008   // UART Data Set Ready Modem
                                            // Interrupt Clear
#define UART_ICR_DCDMIC        0x00000004   // UART Data Carrier Detect Modem
                                            // Interrupt Clear
#define UART_ICR_CTSMIC        0x00000002   // UART Clear to Send Modem
                                            // Interrupt Clear
#define UART_ICR_RIMIC         0x00000001   // UART Ring Indicator Modem
                                            // Interrupt Clear

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_DMACTL register.
//*****************************************************************************
#define UART_DMACTL_DMAERR     0x00000004   // DMA on Error
#define UART_DMACTL_TXDMAE     0x00000002   // Transmit DMA Enable
#define UART_DMACTL_RXDMAE     0x00000001   // Receive DMA Enable

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_LCTL register.
//*****************************************************************************
#define UART_LCTL_BLEN_M       0x00000030   // Sync Break Length
#define UART_LCTL_BLEN_13T     0x00000000   // Sync break length is 13T bits
                                            // (default)
#define UART_LCTL_BLEN_14T     0x00000010   // Sync break length is 14T bits
#define UART_LCTL_BLEN_15T     0x00000020   // Sync break length is 15T bits
#define UART_LCTL_BLEN_16T     0x00000030   // Sync break length is 16T bits
#define UART_LCTL_MASTER       0x00000001   // LIN Master Enable

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_LSS register.
//*****************************************************************************
#define UART_LSS_TSS_M         0x0000FFFF   // Timer Snap Shot
#define UART_LSS_TSS_S         0

//*****************************************************************************
// The following are defines for the bit fields in the UART_O_LTIM register.
//*****************************************************************************
#define UART_LTIM_TIMER_M      0x0000FFFF   // Timer Value
#define UART_LTIM_TIMER_S      0


#endif // __HW_UART_H__



