/*
 * Drivers.c
 *
 *  Created on: Aug 17, 2022
 *      Author: 210055498
 */
#include <F2837xD_device.h>
#include <F2837xD_EPwm_defines.h>
#include <F2837xD_epwm.h>
#include <F2837xD_Examples.h>
#include "Func.h"
#include "C1_Def.h"
#include "C1_Proto.h"
#include "C1_Struct.h"
#include "C1_Vars.h"

//
// InitPeripheralClocksCustom - Initializes the clocks for the peripherals.
//
// Note: In order to reduce power consumption, turn off the clocks to any
// peripheral that is not specified for your part-number or is not used in the
// application
//
void InitPeripheralClocksCustom(void)
{
    EALLOW;

    CpuSysRegs.PCLKCR0.bit.CLA1 = 0;
    CpuSysRegs.PCLKCR0.bit.DMA = 1;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 0;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 0;
    CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 0;

#ifdef CPU1
    CpuSysRegs.PCLKCR0.bit.HRPWM = 1;
#endif

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

#ifdef CPU1
    CpuSysRegs.PCLKCR1.bit.EMIF1 = 1;
    CpuSysRegs.PCLKCR1.bit.EMIF2 = 0;
#endif

    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM3 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM4 = 1;
    CpuSysRegs.PCLKCR2.bit.EPWM5 = 0;
    CpuSysRegs.PCLKCR2.bit.EPWM6 = 0;
    CpuSysRegs.PCLKCR2.bit.EPWM7 = 0;
    CpuSysRegs.PCLKCR2.bit.EPWM8 = 0;
    CpuSysRegs.PCLKCR2.bit.EPWM9 = 01;
    CpuSysRegs.PCLKCR2.bit.EPWM10 = 0;
    CpuSysRegs.PCLKCR2.bit.EPWM11 = 0;
    CpuSysRegs.PCLKCR2.bit.EPWM12 = 0;

    CpuSysRegs.PCLKCR3.bit.ECAP1 = 0;
    CpuSysRegs.PCLKCR3.bit.ECAP2 = 0;
    CpuSysRegs.PCLKCR3.bit.ECAP3 = 0;
    CpuSysRegs.PCLKCR3.bit.ECAP4 = 0;
    CpuSysRegs.PCLKCR3.bit.ECAP5 = 0;
    CpuSysRegs.PCLKCR3.bit.ECAP6 = 0;

    CpuSysRegs.PCLKCR4.bit.EQEP1 = 0;
    CpuSysRegs.PCLKCR4.bit.EQEP2 = 0;
    CpuSysRegs.PCLKCR4.bit.EQEP3 = 0;

    CpuSysRegs.PCLKCR6.bit.SD1 = 1;
    CpuSysRegs.PCLKCR6.bit.SD2 = 1;

    CpuSysRegs.PCLKCR7.bit.SCI_A = 0;
    CpuSysRegs.PCLKCR7.bit.SCI_B = 0;
    CpuSysRegs.PCLKCR7.bit.SCI_C = 0;
    CpuSysRegs.PCLKCR7.bit.SCI_D = 0;

    CpuSysRegs.PCLKCR8.bit.SPI_A = 0;
    CpuSysRegs.PCLKCR8.bit.SPI_B = 1;
    CpuSysRegs.PCLKCR8.bit.SPI_C = 0;

    CpuSysRegs.PCLKCR9.bit.I2C_A = 0;
    CpuSysRegs.PCLKCR9.bit.I2C_B = 0;

    CpuSysRegs.PCLKCR10.bit.CAN_A = 0;
    CpuSysRegs.PCLKCR10.bit.CAN_B = 1;

    CpuSysRegs.PCLKCR11.bit.McBSP_A = 0;
    CpuSysRegs.PCLKCR11.bit.McBSP_B = 0;

#ifdef CPU1
    CpuSysRegs.PCLKCR11.bit.USB_A = 0;

    CpuSysRegs.PCLKCR12.bit.uPP_A = 1;
#endif

    CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
    CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
    CpuSysRegs.PCLKCR13.bit.ADC_C = 1;
    CpuSysRegs.PCLKCR13.bit.ADC_D = 1;

    CpuSysRegs.PCLKCR14.bit.CMPSS1 = 0;
    CpuSysRegs.PCLKCR14.bit.CMPSS2 = 0;
    CpuSysRegs.PCLKCR14.bit.CMPSS3 = 0;
    CpuSysRegs.PCLKCR14.bit.CMPSS4 = 0;
    CpuSysRegs.PCLKCR14.bit.CMPSS5 = 0;
    CpuSysRegs.PCLKCR14.bit.CMPSS6 = 0;
    CpuSysRegs.PCLKCR14.bit.CMPSS7 = 0;
    CpuSysRegs.PCLKCR14.bit.CMPSS8 = 0;

    CpuSysRegs.PCLKCR16.bit.DAC_A = 1;
    CpuSysRegs.PCLKCR16.bit.DAC_B = 1;
    CpuSysRegs.PCLKCR16.bit.DAC_C = 1;

    EDIS;
}

//***************************************************************************************
//
//                                   Table 3-2. PIE Channel Mapping
//        INTx.1  INTx.2  INTx.3  INTx.4  INTx.5   INTx.6   INTx.7   INTx.8   INTx.9  INTx.10  INTx.11   INTx.12  NTx.13 INTx.14 INTx.15 INTx.16
//INT1.y  ADCA1   ADCB1   ADCC1   XINT1   XINT2    ADCD1    TIMER0   WAKE     -       -         -        -       IPC0   IPC1    IPC2    IPC3
//INT2.y  EPWM1TZ EPWM2TZ EPWM3TZ EPWM4TZ EPWM5TZ  EPWM6TZ  EPWM7TZ  EPWM8TZ  EPWM9TZ EPWM10TZ EPWM11TZ  EPWM12TZ -      -       -       -
//INT3.y  EPWM1   EPWM2   EPWM3   EPWM4   EPWM5    EPWM6    EPWM7    EPWM8    EPWM9   EPWM10   EPWM11    EPWM12   -      -       -       -
//INT4.y  ECAP1   ECAP2   ECAP3   ECAP4   ECAP5    ECAP6    -        -        -       -        -         -        -      -       -       -
//INT5.y  EQEP1   EQEP2   EQEP3   -       CLB1     CLB2     CLB3     CLB4     SD1     SD2      -         -        -      -       -       -
//INT6.y  SPIARX  SPIATX  SPIBRX  SPIBTX  MCBSPARX MCBSPATX MCBSPBRX MCBSPBTX SPICRX  SPICTX   -         -        -      -       -       -
//INT7.y  DMACH1  DMACH2  DMACH3  DMACH4  DMACH5   DMACH6   -        -        -       -        -         -        -      -       -       -
//INT8.y  I2CA   I2CAFIFO I2CB   I2CBFIFO SCIC_RX  SCIC_TX  SCID_RX  SCID_TX  -       -        -         -        -      -       UPPA    -
//INT9.y  SCIARX  SCIATX  SCIBRX  SCIBTX  CANA_0   CANA_1   CANB_0   CANB_1   -       -        -         -        -      -       USBA    -
//INT10.y ADCAEVT ADCA2   ADCA3   ADCA4   ADCBEVT  ADCB2    ADCB3    ADCB4   ADCCEVT  ADCC2    ADCC3    ADCC4    ADCDEVT ADCD2   ADCD3   ADCD4
//INT11.y CLA1_1  CLA1_2  CLA1_3  CLA1_4  CLA1_5   CLA1_6   CLA1_7   CLA1_8  -        -        -        -        -       -       -       -
//INT12.y XINT3   XINT4   XINT5    -      -        VCU      FPUOVRF  FPUUNDF EMIFERR  RAMCERR  FLSHCERR RAMACCV  SYSPLL  AUXPLL  CLAOVRF CLAUNDRF
//
// In MiniEAU application enabled Pie interrupts are INT1.1 (ADCA1), INT3.1 (EPWM1), and INT7.1 (DMACH1)
// Note that USER1 is not PIE Mapped.
//***************************************************************************************
void InitPie()
{
   // Install custom interrupts by replacing default TI ISR addresses
   EALLOW;
   PieVectTable.EPWM1_INT = &EPWM1_Interrupt;
   PieVectTable.ADCA1_INT = &ADC_A1_Interrupt;
   PieVectTable.DMA_CH1_INT = &DMA_CH1_Interrupt;
   PieVectTable.USER1_INT = &USER1_Interrupt;

   // Reset value of all PIEIERx registers is 0x0000 (everything disabled)
   PieCtrlRegs.PIEIER1.bit.INTx1 = 1;     // Enable INT1.1 (ADCA1)
   PieCtrlRegs.PIEIER3.bit.INTx1 = 1;     // Enable INT3.1 (EPWM1)
   PieCtrlRegs.PIEIER7.bit.INTx1 = 1;     // enable INT7.1 (DMACH1)

   IER |= (M_INT7 | M_INT3 | M_INT1);     // Enable group interrupts in IER

   // Enable the PIE
   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
   // Enables PIE to drive a pulse into the CPU
   PieCtrlRegs.PIEACK.all = 0xFFFF;
   EDIS;
}

void InitGpio()
{
   EALLOW;

   // Set all MUXes to zero
   GpioCtrlRegs.GPAGMUX1.all = 0;
   GpioCtrlRegs.GPBGMUX1.all = 0;
   GpioCtrlRegs.GPCGMUX1.all = 0;
   GpioCtrlRegs.GPDGMUX1.all = 0;
   GpioCtrlRegs.GPEGMUX1.all = 0;
   GpioCtrlRegs.GPFGMUX1.all = 0;
   GpioCtrlRegs.GPAMUX1.all = 0;
   GpioCtrlRegs.GPBMUX1.all = 0;
   GpioCtrlRegs.GPCMUX1.all = 0;
   GpioCtrlRegs.GPDMUX1.all = 0;
   GpioCtrlRegs.GPEMUX1.all = 0;
   GpioCtrlRegs.GPFMUX1.all = 0;

   // PORT A - GPIO0 to GPIO31
   // GPIO0 -  EPWM1A,
   // GPIO1 -  EPWM1B,
   // GPIO2 -  EPWM2A,
   // GPIO3 -  EPWM2B,
   // GPIO4 -  EPWM3A,
   // GPIO5 -  EPWM3B,
   // GPIO6 -  EPWM4A,
   // GPIO7 -  EPWM4B,
   // GPIO8 -  EPWM5A,
   // GPIO9 -  EPWM5B,
   // GPIO10 - EPWM6A,
   // GPIO11 - EPWM6B,

   // GPIO12 - DESAT Fault routed to Trip Zone by input X-bar
   // GPIO13 - FAULT1A   input
   // GPIO14 - FAULT2A   input
   // GPIO15 - FAULT_EXC input
   // GPIO16 - 8MHz clock for RDC - not used since Kang got all connection to RDC wrong, it is configured as DOUT
   // GPIO17 - nPWM1_EN  output

   // GPIO18 - EPWM10A,
   // GPIO19 - EPWM10B,
   // GPIO20 - EPWM11A,
   // GPIO21 - EPWM11B,
   // GPIO22 - EPWM12A,
   // GPIO23 - EPWM12B,

   // GPIO27 - DUTY1_CH input
   // GPIO28 - DUTY1_AH input
   // GPIO29 - DUTY1_BH input
   // GPIO30 - CANRXA
   // GPIO31 - CANTXA

   // disable pullups on all EPWM pins
   GpioCtrlRegs.GPAPUD.all = 0x00FC0FFF;
   GpioCtrlRegs.GPAMUX1.all = 0x00005555;

   //GPIO17 - nPWM1_EN
   nPWM1_EN_OFF;
   GpioCtrlRegs.GPADIR.bit.GPIO17 = 1;       // GPIO-17 Output

   // CANRXA (GPIO30)
   GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;
   // CANTXA (GPIO31)
   GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;

   // PORT B - GPIO32 to GPIO63
   // GPIO32 - FAULT1B    input
   // GPIO33 - FAULT1C    input
   // GPIO34 - FAULT2C    input
   // GPIO35 - DRV_OT_RDC input
   // GPIO36 - DRV_OT_RDC input
   // GPIO37 - RSVR_LOT_RDC input
   // GPIO38 - RSVR_DOS_RDC input
   // GPIO39 - FAULT2B    input
   // GPIO40 - DUTY2_AH   input
   // GPIO41 - DUTY2_BH   input
   // GPIO42 - DUTY2_CH   input
   // GPIO43 - nPWM2_EN   output
   // GPIO44 - nPWM_RESET output
   // GPIO45 - DIG_INP_A  input
   // GPIO46 - DIG_INP_B  input
   // GPIO47 - DIG_INP_C  input

   // GPIO49 - AMUX_A0    output
   // GPIO50 - AMUX_A1    output
   // GPIO51 - nREADY_EXC input
   // GPIO52 - nPWM_EXC_RESET output
   // GPIO53 - nPWM_EXC_EN    output
   // GPIO54 - DIG_INP_D  input
   // GPIO55 - WHITE_LED  output
   // GPIO56 - BLUE_LED   output
   // GPIO57 - DIG_OUTA   output
   // GPIO58 - DIG_OUTC   output
   // GPIO60 - A0_RDC     output
   // GPIO61 - A1_RDC     output
   // GPIO62 - RES0_RDC   output
   // GPIO63 - RES1_RDC   output

   GpioCtrlRegs.GPFPUD.all = 0xF7860000;    // Disable the Pull-Up resistors on selected outputs

   //GPIO43 - nPWM2_EN
   nPWM2_EN_OFF;                            // Disable PWM2
   GpioCtrlRegs.GPBDIR.bit.GPIO43 = 1;      // GPIO-43 Output

   //GPIO44 - nPWM_RESET
   nPWM_RESET_OFF;                          // Disable PWM_RESET
   GpioCtrlRegs.GPBDIR.bit.GPIO44 = 1;      // GPIO-44 Output

   //GPIO49 - AMUX_A0
   AMUX_A0_LOW;
   GpioCtrlRegs.GPBDIR.bit.GPIO49 = 1;      // GPIO-49 Output

   //GPIO50 - AMUX_A1
   AMUX_A1_LOW;                             // AMUX_A1=0
   GpioCtrlRegs.GPBDIR.bit.GPIO50 = 1;      // GPIO-50 Output

   //GPIO52 - nPWM_EXC_RESET
   nPWM_EXC_RESET_OFF;                      // Disable PWM_EXC_RESET
   GpioCtrlRegs.GPBDIR.bit.GPIO52 = 1;      // GPIO-52 Output

   //GPIO53 - nPWM_EXC_EN
   nPWM_EXC_EN_OFF;                         // Disable PWM_Exc
   GpioCtrlRegs.GPBDIR.bit.GPIO53 = 1;      // GPIO-53 Output

   //GPIO55 - WHITE_LED
   WHITE_LED_OFF;                           // WHITE LED OFF
   GpioCtrlRegs.GPBDIR.bit.GPIO55 = 1;      // GPIO-55 Output

   //GPIO56 - BLUE_LED
   BLUE_LED_OFF;                            // BLUE LED OFF
   GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1;      // GPIO-56 Output

   //GPIO57 - DIG_OUTA
   DIG_OUTA_LOW;                            // GPIO_OUTa output low
   GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;      // GPIO-57 Output

   //GPIO58 - DIG_OUTC
   DIG_OUTC_LOW;                             // GPIO_OUTc output low
   GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1;       // GPIO-58 Output

   //GPIO59 - DIG_OUTB
   DIG_OUTB_LOW;                             // GPIO_OUTb output low
   GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1;       // GPIO-58 Output

   //GPIO163 - SYNC_MI
   SYNC_MI_OFF;                              // SYNC_MI_OFF
   GpioCtrlRegs.GPFDIR.bit.GPIO163 = 1;      // GPIO-163 Output

   // Kang got all connections to RDC wrong but these wrong GPIO pins still need to be configured to keep RDC in known state

   // GPIO60 - A0_RDC
   GpioDataRegs.GPBCLEAR.bit.GPIO60 = 1;     // Set output to 0
   GpioCtrlRegs.GPBDIR.bit.GPIO60 = 1;       // GPIO60 Output

   // GPIO61 - A1_RDC
   GpioDataRegs.GPBCLEAR.bit.GPIO61 = 1;     // Set output to 0
   GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1;       // GPIO61 Output

   // GPIO62 - RES0_RDC
   GpioDataRegs.GPBCLEAR.bit.GPIO62 = 1;     // Set output to 0
   GpioCtrlRegs.GPBDIR.bit.GPIO62 = 1;       // GPIO62 Output

   // GPIO63 - RES1_RDC
   GpioDataRegs.GPBCLEAR.bit.GPIO63 = 1;     // Set output to 0
   GpioCtrlRegs.GPBDIR.bit.GPIO63 = 1;       // GPIO63 Output

   // PORT C -  GPIO64 to GPIO95
   // GPIO64 -  EXC_EN_RDC    output
   // GPIO65 -  nRESET_RDC    output
   // GPIO66 -  nSAMPLE_RDC   output
   // GPIO67 -  nCS_RDC       output
   // GPIO68 -  nRD_RDC       output
   // GPIO69 -  nWR/FSYNC_RDC output

   // GPIO92 -  SHOWSTATE_B0  output
   // GPIO94 -  SHOWSTATE_B1  output

   GpioCtrlRegs.GPCPUD.all = 0x50000000;   // Disable the Pull-Up resistor on selected outputs

   // GPIO64 - EXC_EN_RDC
   GpioDataRegs.GPCCLEAR.bit.GPIO64 = 1;     // Set output to 0 - Disable resolver excitation
   GpioCtrlRegs.GPCDIR.bit.GPIO64 = 1;       // GPIO64 Output

   // GPIO65 - nRESET_RDC
   GpioDataRegs.GPCSET.bit.GPIO65 = 1;       // Set output to 1
   GpioCtrlRegs.GPCDIR.bit.GPIO65 = 1;       // GPIO65 Output

   // GPIO66 - nSAMPLE_RDC
   GpioDataRegs.GPCSET.bit.GPIO66 = 1;       // Set output to 1
   GpioCtrlRegs.GPCDIR.bit.GPIO66 = 1;       // GPIO66 Output

   // GPIO67 - nCS_RDC
   GpioDataRegs.GPCSET.bit.GPIO67 = 1;       // Set output to 1
   GpioCtrlRegs.GPCDIR.bit.GPIO67 = 1;       // GPIO67 Output

   // GPIO68- nRD_RDC
   GpioDataRegs.GPCSET.bit.GPIO68 = 1;       // Set output to 1
   GpioCtrlRegs.GPCDIR.bit.GPIO68 = 1;       // GPIO68 Output

   // GPIO69 - nWR/FSYNC_RDC - WARNING: THIS NEEDS TO BE MOVED TO EITHER
   // GPIO23 or GPIO27 or GPIO59 or GPIO66 IN ORDER TO CONNECT RDC SPI PORT FSYNC
   // TO DSP SPI CONTROLLER TX ENABLE
   GpioDataRegs.GPCSET.bit.GPIO69 = 1;       // Set output to 1
   GpioCtrlRegs.GPCDIR.bit.GPIO69 = 1;       // GPIO69 Output

   // GPIO92 - SHOWSTATE_B0
   GpioDataRegs.GPCCLEAR.bit.GPIO92 = 1;     // Set output to 0
   GpioCtrlRegs.GPCDIR.bit.GPIO92 = 1;       // Output

   // GPIO94 - SHOWSTATE_B1
   GpioDataRegs.GPCCLEAR.bit.GPIO94 = 1;     // Set output to 0
   GpioCtrlRegs.GPCDIR.bit.GPIO94 = 1;       // Output

   // PORT D -  GPIO96 to GPIO127
   // GPIO120 - SHOWSTATE_B2  output
   // GPIO121 - SHOWSTATE_A0  output

   GpioCtrlRegs.GPDPUD.all = 0x03000000;  // Disable the Pull-Up resistor on selected outputs

   // GPIO120 - SHOWSTATE_B2
   GpioDataRegs.GPDCLEAR.bit.GPIO120 = 1;    // Set output to 0
   GpioCtrlRegs.GPDDIR.bit.GPIO120 = 1;      // Output

   // GPIO121 - SHOWSTATE_A0
   GpioDataRegs.GPDCLEAR.bit.GPIO121 = 1;    // Set output to 0
   GpioCtrlRegs.GPDDIR.bit.GPIO121 = 1;      // Output

   // PORT F -  GPIO159 to GPIO191
   // GPIO162 - SHOWSTATE_A0  output
   // GPIO162 - SHOWSTATE_A0  output

   // GPIO162 - SHOWSTATE_A1
   GpioDataRegs.GPFCLEAR.bit.GPIO162 = 1;    // Set output to 0
   GpioCtrlRegs.GPFDIR.bit.GPIO162 = 1;      // Output

   // GPIO164 - SHOWSTATE_A2
   GpioDataRegs.GPFCLEAR.bit.GPIO164 = 1;    // Set output to 0
   GpioCtrlRegs.GPFDIR.bit.GPIO164 = 1;      // Output

   EDIS;
}

void InitEPwm(void)
{
   EALLOW;
   // The proper procedure for enabling ePWM clocks is as follows:
   // 1. Enable ePWM module clocks in the PCLKCR1 register.
   // 2. Set TBCLKSYNC to 0.
   // 3. Configure prescaler values and ePWM modes.
   // 4. Set TBCLKSYNC to 1.
   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;

   // Master ePWM channel
   EPwm1Regs.TBPRD = PeriodCounter;                  // Set timer period
   EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;               // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                         // Clear counter
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;           // Disable phase loading
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;          // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
   EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;       // Sync down-stream module
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // Count up and down
   EPwm1Regs.TBCTL.bit.FREE_SOFT = 3;                // Free run
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_LD_DISABLE;
   EPwm1Regs.CMPA.bit.CMPA = PeriodCounter - DeadTimeCounts;  // Set compare A value
   EPwm1Regs.CMPB.bit.CMPB = 0;                      // Set Compare B value - not used
   EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;              // Clear PWM1A on event A, up count
   EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;                // Set PWM1A on event B, down count
   EPwm1Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
   EPwm1Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
   EPwm1Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
   EPwm1Regs.AQCTLA.bit.CBD = AQ_NO_ACTION;
   EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;    // enable Dead-band module
   EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;         // Active Hi complementary
   EPwm1Regs.DBFED.bit.DBFED = DeadTimeCounts;       // FED = 50 TBCLKs, dead time = 500ns;
   EPwm1Regs.DBRED.bit.DBRED = DeadTimeCounts;       // RED = 50 TBCLKs
   EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;            // Enable /TZ1 one shot mode
   EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;            // Force low id trips
   EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
   EPwm1Regs.TZFRC.bit.OST = 1;                      // Force One time trip zone event - turns off all switches
   EPwm1Regs.TZEINT.bit.OST = TZ_DISABLE;            // Disable trip interrupt
   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO;      // Select INT on Zero and Period events (2x controller)
   EPwm1Regs.ETSEL.bit.INTEN = 0;                    // Temporary disable INT, enabled in the main.c
   EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;               // Generate INT on 1st event

   // Slave ePWM channels
   EPwm2Regs.TBPRD = PeriodCounter;                  // Set timer period
   EPwm2Regs.TBPHS.bit.TBPHS = PeriodCounter;        // Phase is PeriodCounter so ePWM2 is 180 deg phase shifted
   EPwm2Regs.TBCTR = PeriodCounter;                  // Clear counter
   EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;            // Enable phase loading
   EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;             // Count down after phase is loaded to create 180 deg phase shift
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;          // Clock ratio to SYSCLKOUT
   EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
   EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;       // Sync down-stream module
   EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // Count up and down
   EPwm2Regs.TBCTL.bit.FREE_SOFT = 3;                // Free run
   EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
   EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_LD_DISABLE;
   EPwm2Regs.CMPA.bit.CMPA = PeriodCounter - DeadTimeCounts;  // Set compare A value
   EPwm2Regs.CMPB.bit.CMPB = 0;                      // Set Compare B value - not used
   EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;              // Clear PWM1A on event A, up count
   EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;                // Set PWM1A on event B, down count
   EPwm2Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
   EPwm2Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
   EPwm2Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
   EPwm2Regs.AQCTLA.bit.CBD = AQ_NO_ACTION;
   EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;    // enable Dead-band module
   EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;         // Active Hi complementary
   EPwm2Regs.DBFED.bit.DBFED = DeadTimeCounts;       // FED = 50 TBCLKs, dead time = 500ns;
   EPwm2Regs.DBRED.bit.DBRED = DeadTimeCounts;       // RED = 50 TBCLKs
   EPwm2Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;            // Enable /TZ1 one shot mode
   EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;            // Force low id trips
   EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
   EPwm2Regs.TZFRC.bit.OST = 1;                      // Force One time trip zone event - turns off all switches
   EPwm2Regs.TZEINT.bit.OST = TZ_DISABLE;            // Disable trip interrupt
   EPwm2Regs.ETSEL.bit.INTEN = 0;                    // Disable INT

   // ePWM3 generates ADC SOC at Cal.Oversampling rate
   EPwm3Regs.TBPRD = AdcCounter;                     // Set timer period
   EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;               // Phase is 0
   EPwm3Regs.TBCTR = 0x0000;                         // Clear counter
   EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;           // Disable phase loading
   EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;          // Clock ratio to SYSCLKOUT
   EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
   EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;       // Sync down-stream module
   EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // Count up and down
   EPwm3Regs.TBCTL.bit.FREE_SOFT = 3;                // Free run
   EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_LD_DISABLE;
   EPwm3Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
   EPwm3Regs.AQCTLA.bit.CAD = AQ_NO_ACTION;
   EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;                // Set PWM1A on counter equal zero (50% duty cycle)
   EPwm3Regs.AQCTLA.bit.PRD = AQ_CLEAR;              // Clear PWM1A on counter equal period (50% duty cycle)
   EPwm3Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
   EPwm3Regs.AQCTLA.bit.CBD = AQ_NO_ACTION;
   EPwm3Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;        // Disable Dead-band module since this is not real PWM
   EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;         // Active Hi complementary
   EPwm3Regs.DBFED.bit.DBFED = 0;                    // FED = 50 TBCLKs, dead time = 500ns;
   EPwm3Regs.DBRED.bit.DBRED = 0;                    // RED = 50 TBCLKs
   EPwm3Regs.TZSEL.bit.OSHT1 = TZ_DISABLE;           // Enable /TZ1 one shot mode
   EPwm3Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;           // Force low id trips
   EPwm3Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
   EPwm3Regs.TZEINT.bit.OST = TZ_DISABLE;            // Disable trip interrupt
   EPwm3Regs.CMPA.bit.CMPA = 0;                      // Set compare A value - not used
   EPwm3Regs.CMPB.bit.CMPB = PeriodCounter;          // Set Compare B value - not used
   EPwm3Regs.ETSEL.bit.INTEN = 0;                    // Disable INT
   EPwm3Regs.ETSEL.bit.SOCAEN = 0;                   // Disable SOCA - enabled in ePWM1 interrupt
   EPwm3Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;        // Start ADC when EPWM3 counter equal to Zero
   EPwm3Regs.ETPS.bit.SOCAPRD = ET_1ST;              // Start ADC on the first period...

   // ePWM4 generates 50% duty cycle for debug purpose (oscilloscope sync)
   EPwm4Regs.TBPRD = PeriodCounter;                  // Set timer period
   EPwm4Regs.TBPHS.bit.TBPHS = 0x0000;               // Phase is 0
   EPwm4Regs.TBCTR = 0x0000;                         // Clear counter
   EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;           // Disable phase loading
   EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;          // Clock ratio to SYSCLKOUT
   EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
   EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
   EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;    // Count up and down
   EPwm4Regs.TBCTL.bit.FREE_SOFT = 3;                // Free run
   EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_LD_DISABLE;
   EPwm4Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
   EPwm4Regs.AQCTLA.bit.CAD = AQ_NO_ACTION;
   EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;                // Set PWM4A on counter equal zero (50% duty cycle)
   EPwm4Regs.AQCTLA.bit.PRD = AQ_CLEAR;              // Clear PWM4A on counter equal period (50% duty cycle)
   EPwm4Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;
   EPwm4Regs.AQCTLA.bit.CBD = AQ_NO_ACTION;
   EPwm4Regs.DBCTL.bit.OUT_MODE = DB_DISABLE;        // Disable Dead-band module since this is not real PWM
   EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;         // Active Hi complementary
   EPwm4Regs.DBFED.bit.DBFED = 0;                    // FED = 50 TBCLKs, dead time = 500ns;
   EPwm4Regs.DBRED.bit.DBRED = 0;                    // RED = 50 TBCLKs
   EPwm4Regs.TZSEL.bit.OSHT1 = TZ_DISABLE;           // Enable /TZ1 one shot mode
   EPwm4Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;           // Force low id trips
   EPwm4Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
   EPwm4Regs.TZEINT.bit.OST = TZ_DISABLE;            // Disable trip interrupt
   EPwm4Regs.CMPA.bit.CMPA = 0;                      // Set compare A value - not used
   EPwm4Regs.CMPB.bit.CMPB = PeriodCounter;          // Set Compare B value - not used
   EPwm4Regs.ETSEL.bit.INTEN = 0;                    // Disable INT

   // ePWM5, ePWM56, ePWM510, ePWM511, and ePWM512 are not used in MiniEAU application,
   // If they are needed, here is the place to configure them.

   // Input 1 of the Input X-Bar is connected to /TZ1, connect GPIO12 (DESAT_ADC) to INPUT1
   InputXbarRegs.INPUT1SELECT = 12;

   CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
   EDIS;
}

void InitDAC(void)
{
   EALLOW;
   DacaRegs.DACCTL.bit.LOADMODE = 0;      // load DAC as soon as it is given with a new value
   DacaRegs.DACCTL.bit.DACREFSEL = 1;     // use ADC reference (3V) for DAC range
   DacaRegs.DACVALS.all = 2048;           // midscale
   DacaRegs.DACOUTEN.bit.DACOUTEN = 1;    // turn on the DAC

   DacbRegs.DACCTL.bit.LOADMODE = 0;      // load DAC as soon as we give it a new value
   DacbRegs.DACCTL.bit.DACREFSEL = 1;     // use ADC reference (3V) for DAC range
   DacbRegs.DACVALS.all = 2048;           // midscale
   DacbRegs.DACOUTEN.bit.DACOUTEN = 1;    // turn on the DAC

   DaccRegs.DACCTL.bit.LOADMODE = 0;      // load DAC as soon as we give it a new value
   DaccRegs.DACCTL.bit.DACREFSEL = 1;     // use ADC reference (3V) for DAC range
   DaccRegs.DACVALS.all = 2048;           // midscale
   DaccRegs.DACOUTEN.bit.DACOUTEN = 1;    // turn on the DAC
   EDIS;
}

//*****************************************************************************
// ADC channels configuration
//
// SOC8  => A2 - Iind1     B2 - Iind2     C2 - I load    D0 - Vdc
// SOC9  => A0 - DACA      B0 - BodeExc   C4 - unused    D2 - VdcOut
// SOC10 => A2 - Iind1     B2 - Iind2     C2 - I load    D0 - Vdc
// SOC11 => A0 - DACA      B0 - BodeExc   C4 - unused    D2 - VdcOut
// SOC12 => A2 - Iind1     B2 - Iind2     C2 - I load    D0 - Vdc
// SOC13 => A0 - DACA      B0 - BodeExc   C4 - unused    D2 - VdcOut
// SOC14 => A2 - Iind1     B2 - Iind2     C2 - I load    D0 - Vdc
// SOC15 => A0 - DACA      B0 - BodeExc   C4 - unused    D2 - VdcOut
//
// The ADC Interrupt is placed after SOC15 conversion is done
//
//  |        Control Cycle              |        Control Cycle              |
//  ePWM1                               ePWM1                               ePWM1
//
//  |        |        |        |        |        |        |        |        |
//  ePWM3    ePWM3    ePWM3    ePWM3    epWM3    ePWM3    ePWM3    ePWM3    epWM3
//  SOC8,9   SOC10,11 SOC12,13 SOC14,15 SOC8,9   SOC10,11 SOC12,13 SOC14,15 SOC8,9
//                               DMA_CH1                            DMA_CH1
//  AdcIntCounter
//    0        1        2        3        0        1        2         3       0
//*****************************************************************************
void InitADC(void)
{
   EALLOW;

   AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

   //Set pulse positions to late
   AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;      // interrupt generated at the end of conversion
   AdcaRegs.ADCCTL2.bit.PRESCALE = 6;         // ADCCLK divider is set to divide by 4
   AdcaRegs.ADCCTL2.bit.RESOLUTION = 0;       // 12 bit
   AdcaRegs.ADCCTL2.bit.SIGNALMODE = 0;       // single ended
   AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 1;    // 2 SOCs converted
   AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 9; // trigger on ePWM3 SOCA
   AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;      // enable burst mode

   AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;      // interrupt generated at the end of conversion
   AdcbRegs.ADCCTL2.bit.PRESCALE = 6;         // ADCCLK divider is set to divide by 4
   AdcbRegs.ADCCTL2.bit.RESOLUTION = 0;       // 12 bit
   AdcbRegs.ADCCTL2.bit.SIGNALMODE = 0;       // single ended
   AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 1;    // 2 SOCs converted
   AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 9; // trigger on ePWM3 SOCA
   AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1;      // enable burst mode

   AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;      // interrupt generated at the end of conversion
   AdccRegs.ADCCTL2.bit.PRESCALE = 6;         // ADCCLK divider is set to divide by 4
   AdccRegs.ADCCTL2.bit.RESOLUTION = 0;       // 12 bit
   AdccRegs.ADCCTL2.bit.SIGNALMODE = 0;       // single ended
   AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 1;    // 2 SOCs converted
   AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 9; // trigger on ePWM3 SOCA
   AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1;      // enable burst mode

   AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;      // interrupt generated at the end of conversion
   AdcdRegs.ADCCTL2.bit.PRESCALE = 6;         // ADCCLK divider is set to divide by 4
   AdcdRegs.ADCCTL2.bit.RESOLUTION = 0;       // 12 bit
   AdcdRegs.ADCCTL2.bit.SIGNALMODE = 0;       // single ended
   AdcdRegs.ADCBURSTCTL.bit.BURSTSIZE = 1;    // 2 SOCs converted
   AdcdRegs.ADCBURSTCTL.bit.BURSTTRIGSEL = 9; // trigger on ePWM3 SOCA
   AdcdRegs.ADCBURSTCTL.bit.BURSTEN = 1;      // enable burst mode

   AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;         //power up the ADC
   AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
   AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
   AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;

   // SOC8 ADC Channel A //
   AdcaRegs.ADCSOC8CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC8CTL.bit.CHSEL = 2;      // SOC8 converts pin A2 - Phase 1 EAU Current
//   AdcaRegs.ADCSOC8CTL.bit.TRIGSEL = 0;    // trigger ePWM3 SOCA

   // SOC8 ADC Channel B //
   AdcbRegs.ADCSOC8CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC8CTL.bit.CHSEL = 2;      // SOC8 will convert pin B2 - Phase 1 EAU Current
   AdcbRegs.ADCSOC8CTL.bit.TRIGSEL = 9;    // trigger software only since it is used in burst mode

   // SOC8 ADC Channel C //
   AdccRegs.ADCSOC8CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC8CTL.bit.CHSEL = 2;      // SOC8 will convert pin C2 - Load Current
   AdccRegs.ADCSOC8CTL.bit.TRIGSEL = 9;    // trigger on ePWM3 SOCA

   // SOC8 ADC Channel D //
   AdcdRegs.ADCSOC8CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC8CTL.bit.CHSEL = 0;      // SOC8 will convert pin D0 - DC Link Voltage
   AdcdRegs.ADCSOC8CTL.bit.TRIGSEL = 9;    // trigger on ePWM3 SOCA

   // SOC9 ADC Channel A //
   AdcaRegs.ADCSOC9CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC9CTL.bit.CHSEL = 0;      // SOC9 converts pin A0 - DACA, controller does not need it, had to convert something
   AdcaRegs.ADCSOC9CTL.bit.TRIGSEL = 9;    // trigger on ePWM3 SOCA

   // SOC9 ADC Channel B //
   AdcbRegs.ADCSOC9CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC9CTL.bit.CHSEL = 0;      // SOC9 will convert pin B0 - Bode Input
   AdcbRegs.ADCSOC9CTL.bit.TRIGSEL = 9;    // trigger on ePWM3 SOCA

   // SOC9 ADC Channel C //
   AdccRegs.ADCSOC9CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC9CTL.bit.CHSEL = 4;      // SOC9 will convert pin C4 - unused, had to convert something
   AdccRegs.ADCSOC9CTL.bit.TRIGSEL = 9;    // trigger on ePWM3 SOCA

   // SOC9 ADC Channel D //
   AdcdRegs.ADCSOC9CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC9CTL.bit.CHSEL = 2;      // SOC9 will convert pin D2 - Vout (270V side)
   AdcdRegs.ADCSOC9CTL.bit.TRIGSEL = 9;    // trigger on ePWM3 SOCA

   // SOC10 ADC Channel A //
   AdcaRegs.ADCSOC10CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC10CTL.bit.CHSEL = 2;      // SOC10 converts pin A2 - Phase 1 EAU Current
//   AdcaRegs.ADCSOC10CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC10 ADC Channel B //
   AdcbRegs.ADCSOC10CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC10CTL.bit.CHSEL = 2;      // SOC10 will convert pin B2 - Phase 1 EAU Current
//   AdcbRegs.ADCSOC10CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC10 ADC Channel C //
   AdccRegs.ADCSOC10CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC10CTL.bit.CHSEL = 2;      // SOC10 will convert pin C2 - Load Current
//   AdccRegs.ADCSOC10CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC10 ADC Channel D //
   AdcdRegs.ADCSOC10CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC10CTL.bit.CHSEL = 0;      // SOC10 will convert pin D0 - DC Link Voltage
//   AdcdRegs.ADCSOC10CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC11 ADC Channel A //
   AdcaRegs.ADCSOC11CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC11CTL.bit.CHSEL = 0;      // SOC11 converts pin A0 - DACA, controller does not need it, had to convert something
//   AdcaRegs.ADCSOC11CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC11 ADC Channel B //
   AdcbRegs.ADCSOC11CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC11CTL.bit.CHSEL = 0;      // SOC11 will convert pin B0 - Bode Input
//   AdcbRegs.ADCSOC11CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC11 ADC Channel C //
   AdccRegs.ADCSOC11CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC11CTL.bit.CHSEL = 4;      // SOC11 will convert pin C4 - unused, had to convert something
//   AdccRegs.ADCSOC11CTL.bit.TRIGSEL = 0x09; // trigger on ePWM3 SOCA

   // SOC11 ADC Channel D //
   AdcdRegs.ADCSOC11CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC11CTL.bit.CHSEL = 2;      // SOC11 will convert pin D2 - Vout (270V side)
//   AdcdRegs.ADCSOC11CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC12 ADC Channel A //
   AdcaRegs.ADCSOC12CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC12CTL.bit.CHSEL = 2;      // SOC12 converts pin A2 - Phase 1 EAU Current
//   AdcaRegs.ADCSOC12CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC12 ADC Channel B //
   AdcbRegs.ADCSOC12CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC12CTL.bit.CHSEL = 2;      // SOC12 will convert pin B2 - Phase 1 EAU Current
//   AdcbRegs.ADCSOC12CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC12 ADC Channel C //
   AdccRegs.ADCSOC12CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC12CTL.bit.CHSEL = 2;      // SOC12 will convert pin C2 - Load Current
//   AdccRegs.ADCSOC12CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC12 ADC Channel D //
   AdcdRegs.ADCSOC12CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC12CTL.bit.CHSEL = 0;      // SOC12 will convert pin D0 - DC Link Voltage
//   AdcdRegs.ADCSOC12CTL.bit.TRIGSEL = 0x09; // trigger on ePWM3 SOCA

   // SOC13 ADC Channel A //
   AdcaRegs.ADCSOC13CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC13CTL.bit.CHSEL = 0;      // SOC13 converts pin A0 - DACA, controller does not need it, had to convert something
//   AdcaRegs.ADCSOC13CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC13 ADC Channel B //
   AdcbRegs.ADCSOC13CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC13CTL.bit.CHSEL = 0;      // SOC13 will convert pin B0 - Bode Input
//   AdcbRegs.ADCSOC13CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC13 ADC Channel C //
   AdccRegs.ADCSOC13CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC13CTL.bit.CHSEL = 4;      // SOC13 will convert pin C4 - unused, had to convert something
//   AdccRegs.ADCSOC13CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC13 ADC Channel D //
   AdcdRegs.ADCSOC13CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC13CTL.bit.CHSEL = 2;      // SOC13 will convert pin D2 - Vout (270V side)
//   AdcdRegs.ADCSOC13CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC14 ADC Channel A //
   AdcaRegs.ADCSOC14CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC14CTL.bit.CHSEL = 2;      // SOC14 converts pin A2 - Phase 1 EAU Current
//   AdcaRegs.ADCSOC14CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC14 ADC Channel B //
   AdcbRegs.ADCSOC14CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC14CTL.bit.CHSEL = 2;      // SOC14 will convert pin B2 - Phase 1 EAU Current
//   AdcbRegs.ADCSOC14CTL.bit.TRIGSEL  0;    // trigger software only since it is used in burst mode

   // SOC14 ADC Channel C //
   AdccRegs.ADCSOC14CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC14CTL.bit.CHSEL = 2;      // SOC14 will convert pin C2 - Load Current
//   AdccRegs.ADCSOC14CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC14 ADC Channel D //
   AdcdRegs.ADCSOC14CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC14CTL.bit.CHSEL = 0;      // SOC14 will convert pin D0 - DC Link Voltage
//   AdcdRegs.ADCSOC14CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC15 ADC Channel A //
   AdcaRegs.ADCSOC15CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcaRegs.ADCSOC15CTL.bit.CHSEL = 0;      // SOC15 converts pin A0 - DACA, controller does not need it, had to convert something
//   AdcaRegs.ADCSOC15CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC15 ADC Channel B //
   AdcbRegs.ADCSOC15CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcbRegs.ADCSOC15CTL.bit.CHSEL = 0;      // SOC15 will convert pin B0 - Bode Input
//   AdcbRegs.ADCSOC15CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC15 ADC Channel C //
   AdccRegs.ADCSOC15CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdccRegs.ADCSOC15CTL.bit.CHSEL = 4;      // SOC15 will convert pin C4 - unused, had to convert something
//   AdccRegs.ADCSOC15CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   // SOC15 ADC Channel D //
   AdcdRegs.ADCSOC15CTL.bit.ACQPS = 63;     // sample window min 320ns = 64 sysclk * (1/200MHz), 63 -> 64 cycles (n-1)
   AdcdRegs.ADCSOC15CTL.bit.CHSEL = 2;      // SOC15 will convert pin D2 - Vout (270V side)
//   AdcdRegs.ADCSOC15CTL.bit.TRIGSEL = 0;    // trigger software only since it is used in burst mode

   AdcdRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 8; // setting SOC to SOC7 in high priority mode takes them out of round robin

   // Trigger the ADC interrupt after SOC15 conversion is done on ADC A
   AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;  // make sure INT1 flag is cleared
   AdcaRegs.ADCINTSEL1N2.all = 0;
//   AdcaRegs.ADCINTSEL1N2.bit.INT1E = 0;    // disable interrupt at this time, enabled later - ADCA INT1 is source for DMA FIXME
   AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 15;  // end of SOC15 on ADCA will set INT1 flag. INT1 triggers DMA
   AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Continuous mode - no need to clear interrupt to generate next one
   AdcaRegs.ADCINTSEL3N4.all = 0;
   // Other ADCs do not generate interrupts
   AdcbRegs.ADCINTSEL1N2.all = 0;
   AdcbRegs.ADCINTSEL3N4.all = 0;
   AdccRegs.ADCINTSEL1N2.all = 0;
   AdccRegs.ADCINTSEL3N4.all = 0;
   AdcdRegs.ADCINTSEL1N2.all = 0;
   AdcdRegs.ADCINTSEL3N4.all = 0;

   EDIS;
   //delay for 1ms to allow ADC time to power up
   DELAY_US(1000);
}

//*****************************************************************************************
// DMA has to read result registers 0 and 1 on ADCA (0xB00, 0xB01), then result register
// 0 and 1 on ADCB (0x0B20 and 0xB21), then result registers 0 and 1 on ADCC (0x0B40 and
// 0x0B41), and then result registers 0and 1 on ADCD (0xB60 and 0xB61). The way to achieve
// this is to use wrap feature that will add extra offset in the source address every two
// reads.
//*****************************************************************************************
void InitDMA(void)
{
   EALLOW;
   // Perform a hard reset on DMA
   DmaRegs.DMACTRL.all = 3;
   // Allow DMA to run free on emulation suspend
   DmaRegs.DEBUGCTRL.bit.FREE = 1;
   // Set Ch1 priority
   DmaRegs.PRIORITYCTRL1.bit.CH1PRIORITY = 1; // Channel 1 has the highest priority
   // Set up MODE Register:
   DmaRegs.CH1.MODE.all = 0;
   DmaRegs.CH1.MODE.bit.PERINTSEL = 1;       // These are legacy bits and should be set to the channel number
   DmaRegs.CH1.MODE.bit.PERINTE = 1;         // Peripheral Event Trigger Enable
   DmaRegs.CH1.MODE.bit.CHINTMODE = 1;       // Generate interrupt to CPU at end of transfer
   DmaRegs.CH1.MODE.bit.CONTINUOUS = 1;      // Continuous enable
   DmaRegs.CH1.MODE.bit.ONESHOT = 1;         // One shot enabled
   DmaRegs.CH1.MODE.bit.CHINTE = 1;          // Channel Interrupt to CPU enable
   // From Table 5-1. 2837xD Technical Reference, 37xD DSPs have DMA source selected in DmaClaSrcSelRegs.DMACHSRCSEL1
   DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = 1; // 1 = ADCA.1  ADCA INT1  selected as the source for DMA

   // Set up CONTROL register
   DmaRegs.CH1.CONTROL.all = 0;
   DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1;    // Clear any spurious interrupt flags
   DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;       // Clear any spurious sync error flags

   PieCtrlRegs.PIEIER7.bit.INTx1 = 1;        // Enable DMA CH1 interrupt in PIE

   // Set up BURST registers:
   DmaRegs.CH1.BURST_SIZE.bit.BURSTSIZE = 7; // Number of words (x+1) x-ferred in a burst (two channels per ADC x 4 = 8 samples)
   DmaRegs.CH1.SRC_BURST_STEP = 1;           // Increment source address between each word x-ferred
   DmaRegs.CH1.DST_BURST_STEP = 1;           // Increment destination address between each word x-ferred
   // Set up TRANSFER registers:
   // Number of bursts (x+1) per transfer, DMA interrupt will occur after completed transfer
   DmaRegs.CH1.TRANSFER_SIZE = Cal.OversamplingRate - 1;  // 4 burst for 4 oversampling sets
   // TRANSFER_STEP is ignored when WRAP occurs
   DmaRegs.CH1.SRC_TRANSFER_STEP = 0x19;     // source to the next ADC output register set 0x7 + 0x19 = 0x20
   DmaRegs.CH1.DST_TRANSFER_STEP = 1;        // destination to the next address

   // Channel 1 setup - moves ADC data
   // Set up SOURCE address:
   DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (unsigned long)0x0B00; // Point to beginning of source buffer
   DmaRegs.CH1.SRC_ADDR_SHADOW = (unsigned long)0x0B00;
   // Set up DESTINATION address:
   DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (unsigned long)&AdcBuffer[0]; // Point to beginning of destination buffer
   DmaRegs.CH1.DST_ADDR_SHADOW = (unsigned long)&AdcBuffer[0];

   // Set up WRAP registers:
   DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF;  // Wrapping action never happens since it never reaches zero
   DmaRegs.CH1.SRC_WRAP_STEP = 0;       // Step for source wrap
   DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF;  // Wrapping action never happens since it never reaches zero
   DmaRegs.CH1.DST_WRAP_STEP = 0;       // Step for destination wrap

   DmaRegs.CH1.CONTROL.bit.RUN = 0;     // Do not start DMA channel 1 yet.
   EDIS;
}

//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
void InitPieCtrl(void)
{
    // Disable Interrupts at the CPU level:
    DINT;

    // Disable the PIE
    PieCtrlRegs.PIECTRL.bit.ENPIE = 0;

   // Clear all PIEIER registers:
   PieCtrlRegs.PIEIER1.all = 0;
   PieCtrlRegs.PIEIER2.all = 0;
   PieCtrlRegs.PIEIER3.all = 0;
   PieCtrlRegs.PIEIER4.all = 0;
   PieCtrlRegs.PIEIER5.all = 0;
   PieCtrlRegs.PIEIER6.all = 0;
   PieCtrlRegs.PIEIER7.all = 0;
   PieCtrlRegs.PIEIER8.all = 0;
   PieCtrlRegs.PIEIER9.all = 0;
   PieCtrlRegs.PIEIER10.all = 0;
   PieCtrlRegs.PIEIER11.all = 0;
   PieCtrlRegs.PIEIER12.all = 0;

   // Clear all PIEIFR registers:
   PieCtrlRegs.PIEIFR1.all = 0;
   PieCtrlRegs.PIEIFR2.all = 0;
   PieCtrlRegs.PIEIFR3.all = 0;
   PieCtrlRegs.PIEIFR4.all = 0;
   PieCtrlRegs.PIEIFR5.all = 0;
   PieCtrlRegs.PIEIFR6.all = 0;
   PieCtrlRegs.PIEIFR7.all = 0;
   PieCtrlRegs.PIEIFR8.all = 0;
   PieCtrlRegs.PIEIFR9.all = 0;
   PieCtrlRegs.PIEIFR10.all = 0;
   PieCtrlRegs.PIEIFR11.all = 0;
   PieCtrlRegs.PIEIFR12.all = 0;

}

void InitMemory(void)
{
   // GS0 to  GS7 assigned to CPU1
   // GS8 to GS14 assigned to CPU2
   // GS15        assigned to CPU1 and DMA access
   MemCfgRegs.GSxMSEL.all = 0x00007F00;
   // D26 = 0 => GS15 DMA writes are allowed
   // D25 = 1 => GS15 CPU writes are blocked
   // D24 = 1 => GS15 CPU fetches are blocked
   MemCfgRegs.GSxACCPROT3.all = 0x03000000;
}
