> 16U);
return((uint16_t)stat);
}
//*****************************************************************************
//
//! Returns the Control Status of zone 2
//!
//! This function returns the Control Status of zone 2 CSM
//!
//! \return Returns the contents of the Control Register which can be
//! used with the provided defines.
//
//*****************************************************************************
static inline uint16_t
DCSM_getZone2ControlStatus(void)
{
uint32_t stat;
//
// Return the contents of the CR register.
//
stat = (((*((volatile uint32_t *)(0x0005F080U + 0x18U)))) >> 16U);
return((uint16_t)stat);
}
//*****************************************************************************
//
//! Returns the security zone a RAM section belongs to
//!
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
//! C28x RAMs :
//! - \b DCSM_RAMLS0
//! - \b DCSM_RAMLS1
//! - \b DCSM_RAMLS2
//! - \b DCSM_RAMLS3
//! - \b DCSM_RAMLS4
//! - \b DCSM_RAMLS5
//! - \b DCSM_RAMLS6
//! - \b DCSM_RAMLS7
//!
//! This function returns the security zone a RAM section belongs to.
//!
//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible,
//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if
//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section
//! doesn't belong to any zone (or if the section is unsecure).
//
//*****************************************************************************
static inline DCSM_MemoryStatus
DCSM_getRAMZone(DCSM_RAMModule module)
{
uint16_t shift = (uint16_t)module * 2U;
uint32_t ramStatus;
//
//Read the RAMSTAT register for the specific RAM Module.
//
ramStatus = (((*((volatile uint32_t *)(0x0005F0C0U + 0x10U))) >>
shift) & 0x03U);
return((DCSM_MemoryStatus)ramStatus);
}
//*****************************************************************************
//
//! Returns the security zone a flash sector belongs to
//!
//! \param sector is the flash sector value. Use DCSM_Sector type.
//!
//! This function returns the security zone a flash sector belongs to.
//!
//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible ,
//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if
//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section
//! doesn't belong to any zone (or if the section is unsecure)..
//
//*****************************************************************************
static inline DCSM_MemoryStatus
DCSM_getFlashSectorZone(DCSM_Sector sector)
{
uint32_t sectStat;
uint16_t shift;
//
// Get the Sector status register for the specific bank
//
if(sector <= DCSM_BANK0_SECTOR15)
{
sectStat = (*((volatile uint32_t *)(0x0005F0C0U + 0x8U)));
shift = (uint16_t)sector * 2U;
}
else if(sector <= DCSM_BANK1_SECTOR15)
{
sectStat = (*((volatile uint32_t *)(0x0005F0C0U + 0xAU)));
shift = ((uint16_t)sector & 0xFU) * (uint16_t)2U;
}
else
{
sectStat = (*((volatile uint32_t *)(0x0005F0C0U + 0xCU)));
shift = ((uint16_t)sector & 0xFU) * (uint16_t)2U;
}
//
//Read the SECTSTAT register for the specific Flash Sector.
//
return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U)));
}
//*****************************************************************************
//
//! Read Zone 1 Link Pointer Error
//!
//! A non-zero value indicates an error on the bit position that is set to 1.
//!
//! \return Returns the value of the Zone 1 Link Pointer error.
//
//*****************************************************************************
static inline uint32_t
DCSM_getZone1LinkPointerError(void)
{
//
// Return the LinkPointer Error for specific bank
//
return((*((volatile uint32_t *)(0x0005F000U + 0x6U))));
}
//*****************************************************************************
//
//! Read Zone 2 Link Pointer Error
//!
//! A non-zero value indicates an error on the bit position that is set to 1.
//!
//! \return Returns the value of the Zone 2 Link Pointer error.
//
//*****************************************************************************
static inline uint32_t
DCSM_getZone2LinkPointerError(void)
{
//
// Return the LinkPointer Error for specific bank
//
return((*((volatile uint32_t *)(0x0005F080U + 0x6U))));
}
//*****************************************************************************
//
//! Get the status of the security configuration load from USER-OTP or sector
//! error status
//!
//! \return Returns 0 if no error in loading security information from
//! USER-OTP, 1 if an error has occurred in the load from USER-OTP.
//
//*****************************************************************************
static inline _Bool
DCSM_getFlashErrorStatus(void)
{
return((_Bool)((*((volatile uint32_t *)(0x0005F0C0U + 0x18U))) &
0x1U));
}
//*****************************************************************************
//
//! Clear the Flash Error Status bit
//!
//! Write a '1' to the clear bit to clear the sector error status bit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCSM_clearFlashErrorStatus(void)
{
(*((volatile uint32_t *)(0x0005F0C0U + 0x1AU))) |= 0x1U;
}
//*****************************************************************************
//
//! Set the force Flash Error Status bit
//!
//! Write a '1' to force bit to set the sector error status bit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCSM_forceFlashErrorStatus(void)
{
(*((volatile uint32_t *)(0x0005F0C0U + 0x1CU))) = 0x1U |
((uint32_t)0x5A5AU
<< 16U);
}
//*****************************************************************************
//
//! Returns the OTP secure Lock status of zone 1
//!
//! \param lockType is the OTP secure Lock feature type .
//!
//! The \e lockType parameter can have one of the following values of the
//! DCSM_CPUSel type:
//! - \b DCSM_OTPSECLOCK_JTAG - JTAG Lock Status
//! - \b DCSM_OTPSECLOCK_CRCLOCK - Zone CRC Lock
//! - \b DCSM_OTPSECLOCK_PSWDLOCK - Zone Password Lock
//!
//! This function takes in a valid OTP secure Lock feature type and
//! returns the status of zone 1 lock feature
//!
//! \return Returns security lock status can be:
//! For JTAG lock : 0 - JTAG is not locked , 1 - JTAG is locked
//!
//! For Zone Password Lock : 1111 - CSM Pwd locations in the OTP are not
//! protected and can be read from the debugger as well as code running
//! from anywhere.
//! Other Value : CSM Pwd locations in the OTP are protected and can't be read
//! without unlocking CSM of that zone.
//!
//! For Zone CRC Lock : 1111 : VCU has ability to calculate CRC
//! on secure memories.
//! Other Value : VCU doesn't have the ability to calculate CRC on
//! secure memories.
//
//*****************************************************************************
static inline uint32_t
DCSM_getZone1OTPSecureLockStatus(DCSM_OTPLock lockType)
{
uint32_t status, returnStatus;
status = (*((volatile uint32_t *)(0x0005F000U + 0x2U)));
//
// Reflects the state of the OTP Sec LOCK feature.
//
if(lockType == DCSM_OTPSECLOCK_JTAG)
{
returnStatus = (status & 0x1U) >>
0U;
}
else if(lockType == DCSM_OTPSECLOCK_CRCLOCK)
{
returnStatus = (status & 0xF00U) >>
8U;
}
else if(lockType == DCSM_OTPSECLOCK_PSWDLOCK)
{
returnStatus = (status & 0xF0U) >>
4U;
}
else
{
returnStatus = (uint32_t)0xFFFFU;
}
return(returnStatus);
}
//*****************************************************************************
//
//! Returns the OTP secure Lock status of zone 2
//!
//! \param lockType is the OTP secure Lock feature type .
//!
//! The \e lockType parameter can have one of the following values of the
//! DCSM_CPUSel type:
//! - \b DCSM_OTPSECLOCK_CRCLOCK - Zone CRC Lock
//! - \b DCSM_OTPSECLOCK_PSWDLOCK - Zone Password Lock
//!
//! This function takes in a valid OTP secure Lock feature type and
//! returns the status of zone 2 lock feature
//!
//! \return Returns security lock status can be:
//!
//! For Zone Password Lock : 1111 - CSM Pwd locations in the OTP are not
//! protected and can be read from the debugger as well as code running
//! from anywhere.
//! Other Value : CSM Pwd locations in the OTP are protected and can't be read
//! without unlocking CSM of that zone.
//!
//! For Zone CRC Lock : 1111 : VCU has ability to calculate CRC
//! on secure memories.
//! Other Value : VCU doesn't have the ability to calculate CRC on
//! secure memories.
//
//*****************************************************************************
static inline uint32_t
DCSM_getZone2OTPSecureLockStatus(DCSM_OTPLock lockType)
{
uint32_t status, returnStatus;
status = (*((volatile uint32_t *)(0x0005F080U + 0x2U)));
//
// Reflects the state of the OTP Sec LOCK feature.
//
if(lockType == DCSM_OTPSECLOCK_CRCLOCK)
{
returnStatus = (status & 0xF00U) >>
8U;
}
else if(lockType == DCSM_OTPSECLOCK_PSWDLOCK)
{
returnStatus = (status & 0xF0U) >>
4U;
}
else
{
returnStatus = (uint32_t)0xFFFFU;
}
return(returnStatus);
}
//*****************************************************************************
//
//! Unlocks Zone 1 CSM.
//!
//! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the
//! CSM password for zone 1.
//!
//! This function unlocks the CSM password. It first reads the
//! four password locations in the User OTP. If any of the password values is
//! different from 0xFFFFFFFF, it unlocks the device by writing the provided
//! passwords into CSM Key registers
//!
//! \return None.
//!
//! \note This function should not be called in an actual application,
//! should only be used for once to program the OTP memory. Ensure flash data
//! cache is disabled before calling this function(Flash_disableCache).
//
//*****************************************************************************
extern void
DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey);
//*****************************************************************************
//
//! Unlocks Zone 2 CSM.
//!
//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM
//! password for zone 2.
//!
//! This function unlocks the CSM password. It first reads
//! the four password locations in the User OTP. If any of the password values
//! is different from 0xFFFFFFFF, it unlocks the device by writing the
//! provided passwords into CSM Key registers
//!
//! \return None.
//!
//! \note This function should not be called in an actual application,
//! should only be used for once to program the OTP memory. Ensure flash data
//! cache is disabled before calling this function(Flash_disableCache).
//
//*****************************************************************************
extern void
DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey);
//*****************************************************************************
//
//! Write Zone 1 CSM.
//!
//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM
//! password for zone 1.
//!
//! Password match flow is essentially a sequence of dummy reads
//! from password locations (PWL) followed by writes to CSMKEY registers.
//! This function helps writing the provided passwords into the CSM Key
//! registers. The DCSM_readZone1CSMPwd() should be called
//! by CPU1 before calling this API.
//!
//! \return None.
//
//*****************************************************************************
extern void
DCSM_writeZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey);
//*****************************************************************************
//
//! Write Zone 2 CSM.
//!
//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM
//! password for zone 2.
//!
//! Password match flow is essentially a sequence of dummy reads
//! from password locations (PWL) followed by writes to CSMKEY registers.
//! This function helps writing the provided passwords into the CSM Key
//! registers. The DCSM_readZone2CSMPwd() should be called
//! by CPU1 before calling this API.
//!
//! \return None.
//
//*****************************************************************************
extern void
DCSM_writeZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 1 for a flash sector
//!
//! \param sector is the flash sector value. Use DCSM_Sector type.
//!
//! This function takes in a valid sector value and returns the status of EXE
//! ONLY security protection for the sector.
//!
//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if sector does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone1FlashEXEStatus(DCSM_Sector sector);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 1 for a RAM module
//!
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
//! C28x RAMs :
//! - \b DCSM_RAMLS0
//! - \b DCSM_RAMLS1
//! - \b DCSM_RAMLS2
//! - \b DCSM_RAMLS3
//! - \b DCSM_RAMLS4
//! - \b DCSM_RAMLS5
//! - \b DCSM_RAMLS6
//! - \b DCSM_RAMLS7
//!
//! This function takes in a valid module value and returns the status of EXE
//! ONLY security protection for that module. DCSM_CLA is an invalid module
//! value. There is no EXE-ONLY available for DCSM_CLA.
//!
//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if module does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 2 for a flash sector
//!
//! \param sector is the flash sector value. Use DCSM_Sector type.
//!
//! This function takes in a valid sector value and returns the status of EXE
//! ONLY security protection for the sector.
//!
//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if sector does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone2FlashEXEStatus(DCSM_Sector sector);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 2 for a RAM module
//!
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
//! C28x RAMs :
//! - \b DCSM_RAMLS0
//! - \b DCSM_RAMLS1
//! - \b DCSM_RAMLS2
//! - \b DCSM_RAMLS3
//! - \b DCSM_RAMLS4
//! - \b DCSM_RAMLS5
//! - \b DCSM_RAMLS6
//! - \b DCSM_RAMLS7
//!
//! This function takes in a valid module value and returns the status of EXE
//! ONLY security protection for that module. DCSM_CLA is an invalid module
//! value. There is no EXE-ONLY available for DCSM_CLA.
//!
//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if module does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module);
//*****************************************************************************
//
//! Claims the zone semaphore which allows access to the Flash Wrapper register
//! for that zone.
//!
//! \param zone is the zone which is trying to claim the semaphore which allows
//! access to the Flash Wrapper registers.
//!
//! \return Returns true for a successful semaphore capture, false if it was
//! unable to capture the semaphore.
//
//*****************************************************************************
extern _Bool
DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone);
//*****************************************************************************
//
//! Releases the zone semaphore.
//!
//! \return Returns true if it was successful in releasing the zone semaphore
//! and false if it was unsuccessful in releasing the zone semaphore.
//!
//! \note If the calling function is not in the right zone to be able
//! to access this register, it will return a false.
//
//*****************************************************************************
extern _Bool
DCSM_releaseZoneSemaphore(void);
//*****************************************************************************
//
//! Perform dummy reads on the 128-bit Zone 1 CSM password.
//!
//! This function reads the four password locations in the User OTP
//! needed to be done as part of the Password Match Flow before
//! writes to the CSMKEY registers.
//! This would need to be done before a DCSM_writeZone1CSM().
//!
//! \return None.
//!
//! \note This API to be called from CPU1.
//
//*****************************************************************************
extern void
DCSM_readZone1CSMPwd(void);
//*****************************************************************************
//
//! Perform dummy reads on the 128-bit Zone 2 CSM password.
//!
//! This function reads the four password locations in the User OTP
//! needed to be done as part of the Password Match Flow before
//! writes to the CSMKEY registers.
//! This would need to be done before a DCSM_writeZone2CSM().
//!
//! \return None.
//!
//! \note This API to be called from CPU1.
//
//*****************************************************************************
extern void
DCSM_readZone2CSMPwd(void);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: dma.h
//
// TITLE: C28x DMA driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup dma_api DMA
//! \brief This module is used for DMA configurations.
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_dma.h
//
// TITLE: Definitions for the DMA registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the DMA register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DMACTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DEBUGCTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PRIORITYCTRL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PRIORITYSTAT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MODE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CONTROL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the BURST_SIZE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the BURST_COUNT register
//
//*************************************************************************************************
//*****************************************************************************
//
// Values that can be passed to DMA_configMode() as the config parameter.
//
//*****************************************************************************
//! Only one burst transfer performed per trigger.
//! Burst transfers occur without additional event triggers after the first.
//! DMA channel will be disabled at the end of a transfer.
//! DMA reinitializes when the transfer count is zero and waits for a trigger.
//! DMA transfers 16 bits at a time.
//! DMA transfers 32 bits at a time.
//*****************************************************************************
//
//! Values that can be passed to DMA_configMode() as the \e trigger parameter.
//
//*****************************************************************************
typedef enum
{
DMA_TRIGGER_SOFTWARE = 0,
DMA_TRIGGER_ADCA1 = 1,
DMA_TRIGGER_ADCA2 = 2,
DMA_TRIGGER_ADCA3 = 3,
DMA_TRIGGER_ADCA4 = 4,
DMA_TRIGGER_ADCAEVT = 5,
DMA_TRIGGER_ADCB1 = 6,
DMA_TRIGGER_ADCB2 = 7,
DMA_TRIGGER_ADCB3 = 8,
DMA_TRIGGER_ADCB4 = 9,
DMA_TRIGGER_ADCBEVT = 10,
DMA_TRIGGER_ADCC1 = 11,
DMA_TRIGGER_ADCC2 = 12,
DMA_TRIGGER_ADCC3 = 13,
DMA_TRIGGER_ADCC4 = 14,
DMA_TRIGGER_ADCCEVT = 15,
DMA_TRIGGER_XINT1 = 29,
DMA_TRIGGER_XINT2 = 30,
DMA_TRIGGER_XINT3 = 31,
DMA_TRIGGER_XINT4 = 32,
DMA_TRIGGER_XINT5 = 33,
DMA_TRIGGER_EPWM1SOCA = 36,
DMA_TRIGGER_EPWM1SOCB = 37,
DMA_TRIGGER_EPWM2SOCA = 38,
DMA_TRIGGER_EPWM2SOCB = 39,
DMA_TRIGGER_EPWM3SOCA = 40,
DMA_TRIGGER_EPWM3SOCB = 41,
DMA_TRIGGER_EPWM4SOCA = 42,
DMA_TRIGGER_EPWM4SOCB = 43,
DMA_TRIGGER_EPWM5SOCA = 44,
DMA_TRIGGER_EPWM5SOCB = 45,
DMA_TRIGGER_EPWM6SOCA = 46,
DMA_TRIGGER_EPWM6SOCB = 47,
DMA_TRIGGER_EPWM7SOCA = 48,
DMA_TRIGGER_EPWM7SOCB = 49,
DMA_TRIGGER_EPWM8SOCA = 50,
DMA_TRIGGER_EPWM8SOCB = 51,
DMA_TRIGGER_TINT0 = 68,
DMA_TRIGGER_TINT1 = 69,
DMA_TRIGGER_TINT2 = 70,
DMA_TRIGGER_ECAP1 = 75,
DMA_TRIGGER_ECAP2 = 76,
DMA_TRIGGER_ECAP3 = 77,
DMA_TRIGGER_SDFM1FLT1 = 96,
DMA_TRIGGER_SDFM1FLT2 = 97,
DMA_TRIGGER_SDFM1FLT3 = 98,
DMA_TRIGGER_SDFM1FLT4 = 99,
DMA_TRIGGER_SDFM2FLT1 = 101,
DMA_TRIGGER_SDFM2FLT2 = 102,
DMA_TRIGGER_SDFM2FLT3 = 103,
DMA_TRIGGER_SDFM2FLT4 = 104,
DMA_TRIGGER_SPIATX = 109,
DMA_TRIGGER_SPIARX = 110,
DMA_TRIGGER_SPIBTX = 111,
DMA_TRIGGER_SPIBRX = 112,
DMA_TRIGGER_LINATX = 117,
DMA_TRIGGER_LINARX = 118,
DMA_TRIGGER_LINBTX = 119,
DMA_TRIGGER_LINBRX = 120,
DMA_TRIGGER_FSITXA = 123,
DMA_TRIGGER_FSI_DATA_TAG_MATCH = 124,
DMA_TRIGGER_FSIRXA = 125,
DMA_TRIGGER_FSI_PING_DATA_MATCH = 126,
DMA_TRIGGER_CLB1INT = 127,
DMA_TRIGGER_CLB2INT = 128,
DMA_TRIGGER_CLB3INT = 129,
DMA_TRIGGER_CLB4INT = 130,
DMA_TRIGGER_CANAIF1 = 167,
DMA_TRIGGER_CANAIF2 = 168,
DMA_TRIGGER_CANAIF3 = 169,
DMA_TRIGGER_HICA = 179,
DMA_TRIGGER_AESA_CONTEXTIN = 180,
DMA_TRIGGER_AESA_DATAIN = 181,
DMA_TRIGGER_AESA_CONTEXTOUT = 182,
DMA_TRIGGER_AESA_DATAOUT = 183,
DMA_TRIGGER_EPG1 = 184
} DMA_Trigger;
//*****************************************************************************
//
//! Values that can be passed to DMA_setInterruptMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! DMA interrupt is generated at the beginning of a transfer
DMA_INT_AT_BEGINNING,
//! DMA interrupt is generated at the end of a transfer
DMA_INT_AT_END
} DMA_InterruptMode;
//*****************************************************************************
//
//! Values that can be passed to DMA_setEmulationMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! Transmission stops after current read-write access is completed
DMA_EMULATION_STOP,
//! Continue DMA operation regardless of emulation suspend
DMA_EMULATION_FREE_RUN
} DMA_EmulationMode;
//*****************************************************************************
//
//! Values that can be passed to DMA_configChannel() as the
//! configure parameter.
//
//*****************************************************************************
typedef struct
{
DMA_Trigger transferTrigger; //DMA transfer triggers
DMA_InterruptMode interruptMode; //Channel interrupt mode
//! enableInterrupt can have a value 1(Enable) or 0(Disable)
_Bool enableInterrupt; //Enable/Disable interrupt mode
//! configSize can have a value DMA_CFG_SIZE_16BIT/32BIT
uint32_t configSize; //Data bus width (16 or 32 bits)
//! transferMode can have a value DMA_CFG_ONESHOT_DISABLE/ENABLE
uint32_t transferMode; //Burst transfer mode
//! reinitMode can have a value DMA_CFG_CONTINUOUS_DISABLE/ENABLE
uint32_t reinitMode; //DMA reinitialization mode
//! burstSize value range from 1 word to 32 sixteen-bit words.
uint32_t burstSize; //Number of words transferred per burst
//! transferSize value range from 1 to 65536
uint32_t transferSize; //Number of bursts per transfer
//! Number of bursts to be transferred before a wrap of the source address
//! occurs. srcWrapSize value range from 1 to 65536
uint32_t srcWrapSize;
//! Number of bursts to be transferred before a wrap of the destination
//! address occurs. destWrapSize value range from 1 to 65536
uint32_t destWrapSize;
uint32_t destAddr; //destination address
uint32_t srcAddr; //source address
//! Amount to inc or dec the source address after each word of a burst.
//! srcBurstStep can have only signed values from -4096 to 4095
int16_t srcBurstStep;
//! Amount to inc or dec the destination address after each word of a burst.
//! destBurstStep can have only signed values from -4096 to 4095
int16_t destBurstStep;
//! Amount to inc or dec the source address after each burst of a transfer.
//! srcTransferStep can have only signed values from -4096 to 4095
int16_t srcTransferStep;
//! Amount to inc or dec the destination address after each burst of a
//! transfer. destTransferStep can have only signed values from -4096 to 4095
int16_t destTransferStep;
//! Amount to inc or dec the source address when the wrap occurs.
//! srcWrapStep can have only signed values from -4096 to 4095
int16_t srcWrapStep;
//! Amount to inc or dec the destination address when the wrap occurs.
//! destWrapStep can have only signed values from -4096 to 4095
int16_t destWrapStep;
} DMA_ConfigParams;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an DMA channel base address.
//!
//! \param base specifies the DMA channel base address.
//!
//! This function determines if a DMA channel base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Initializes the DMA controller to a known state.
//!
//! This function configures does a hard reset of the DMA controller in order
//! to put it into a known state. The function also sets the DMA to run free
//! during an emulation suspend (see the field DEBUGCTRL.FREE for more info).
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_initController(void)
{
__eallow();
//
// Set the hard reset bit. One NOP is required after HARDRESET.
//
(*((volatile uint16_t *)(0x00001000U + 0x0U))) |= 0x1U;
__asm(" NOP");
__edis();
}
//*****************************************************************************
//
//! Channel Soft Reset
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function does a soft reset to place the channel into its default state
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_triggerSoftReset(uint32_t base)
{
__eallow();
//
// Set the soft reset bit. One NOP is required after SOFTRESET.
//
(*((volatile uint16_t *)(base + 0x1U))) |= 0x4U;
__asm(" NOP");
__edis();
}
//*****************************************************************************
//
//! Sets DMA emulation mode.
//!
//! \param mode is the emulation mode to be selected.
//!
//! This function sets the behavior of the DMA operation when an emulation
//! suspend occurs. The \e mode parameter can be one of the following:
//!
//! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is
//! completed.
//! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a
//! the suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_setEmulationMode(DMA_EmulationMode mode)
{
__eallow();
//
// Set emulation mode
//
if(mode == DMA_EMULATION_STOP)
{
(*((volatile uint16_t *)(0x00001000U + 0x1U))) &= ~0x8000U;
}
else
{
(*((volatile uint16_t *)(0x00001000U + 0x1U))) |= 0x8000U;
}
__edis();
}
//*****************************************************************************
//
//! Enables peripherals to trigger a DMA transfer.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function enables the selected peripheral trigger to start a DMA
//! transfer on the specified channel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_enableTrigger(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the peripheral interrupt trigger enable bit.
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) |= 0x100U;
__edis();
}
//*****************************************************************************
//
//! Disables peripherals from triggering a DMA transfer.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function disables the selected peripheral trigger from starting a DMA
//! transfer on the specified channel. This also disables the use of the
//! software force using the DMA_forceTrigger() API.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_disableTrigger(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear the peripheral interrupt trigger enable bit.
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x100U;
__edis();
}
//*****************************************************************************
//
//! Force a peripheral trigger to a DMA channel.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function sets the peripheral trigger flag and if triggering a DMA
//! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be
//! forced.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_forceTrigger(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the peripheral interrupt trigger force bit.
//
__eallow();
(*((volatile uint16_t *)(base + 0x1U))) |= 0x8U;
__edis();
}
//*****************************************************************************
//
//! Clears a DMA channel's peripheral trigger flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function clears the peripheral trigger flag. Normally, you would use
//! this function when initializing the DMA for the first time. The flag is
//! cleared automatically when the DMA starts the first burst of a transfer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_clearTriggerFlag(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Write a one to the clear bit to clear the peripheral trigger flag.
//
__eallow();
(*((volatile uint16_t *)(base + 0x1U))) |= 0x10U;
__edis();
}
//*****************************************************************************
//
//! Gets the status of a DMA channel's Transfer Status Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Transfer Status Flag is set, which
//! means a DMA transfer has begun.
//! This flag is cleared when TRANSFER_COUNT reaches zero, or when the
//! HARDRESET or SOFTRESET bit is set.
//!
//! \return Returns \b true if the Transfer Status Flag is set. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getTransferStatusFlag(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read the Transfer Status Flag and return appropriately.
//
return(((*((volatile uint16_t *)(base + 0x1U))) & 0x800U) != 0U);
}
//*****************************************************************************
//
//! Gets the status of a DMA channel's Burst Status Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Burst Status Flag is set, which
//! means a DMA burst has begun.
//! This flag is cleared when BURST_COUNT reaches zero, or when the
//! HARDRESET or SOFTRESET bit is set.
//!
//! \return Returns \b true if the Burst Status Flag is set. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getBurstStatusFlag(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read the Burst Status Flag and return appropriately.
//
return(((*((volatile uint16_t *)(base + 0x1U))) & 0x1000U) != 0U);
}
//*****************************************************************************
//
//! Gets the status of a DMA channel's Run Status Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Run Status Flag is set, which
//! means the DMA channel is enabled.
//! This flag is cleared when a transfer completes (TRANSFER_COUNT = 0) and
//! continuous mode is disabled, or when the HARDRESET, SOFTRESET, or HALT bit
//! is set.
//!
//! \return Returns \b true if the channel is enabled. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getRunStatusFlag(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read the Run Status Flag and return appropriately.
//
return(((*((volatile uint16_t *)(base + 0x1U))) & 0x2000U) != 0U);
}
//*****************************************************************************
//
//! Gets the status of a DMA channel's Overflow Flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if the Overflow Flag is set, which
//! means peripheral event trigger was received while Peripheral Event Trigger
//! Flag was already set.
//! This flag can be cleared by writing to ERRCLR bit, using the function
//! DMA_clearErrorFlag().
//!
//! \return Returns \b true if the channel is enabled. Returns \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getOverflowFlag(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read the Overflow Flag and return appropriately.
//
return(((*((volatile uint16_t *)(base + 0x1U))) & 0x4000U) != 0U);
}
//*****************************************************************************
//
//! Gets the status of a DMA channel's peripheral trigger flag.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function returns \b true if a peripheral trigger event has occurred
//! The flag is automatically cleared when the first burst transfer begins, but
//! if needed, it can be cleared using DMA_clearTriggerFlag().
//!
//! \return Returns \b true if a peripheral trigger event has occurred and its
//! flag is set. Returns \b false otherwise.
//
//*****************************************************************************
static inline _Bool
DMA_getTriggerFlagStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read the peripheral trigger flag and return appropriately.
//
return(((*((volatile uint16_t *)(base + 0x1U))) & 0x100U) != 0U);
}
//*****************************************************************************
//
//! Starts a DMA channel.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function starts the DMA running, typically after you have configured
//! it. It will wait for the first trigger event to start operation. To halt
//! the channel use DMA_stopChannel().
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_startChannel(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the run bit.
//
__eallow();
(*((volatile uint16_t *)(base + 0x1U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Halts a DMA channel.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function halts the DMA at its current state and any current read-write
//! access is completed. To start the channel again use DMA_startChannel().
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_stopChannel(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the halt bit.
//
__eallow();
(*((volatile uint16_t *)(base + 0x1U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! Enables a DMA channel interrupt source.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function enables the indicated DMA channel interrupt source.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_enableInterrupt(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the specified DMA channel interrupt.
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) |= 0x8000U;
__edis();
}
//*****************************************************************************
//
//! Disables a DMA channel interrupt source.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function disables the indicated DMA channel interrupt source.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_disableInterrupt(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the specified DMA channel interrupt.
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x8000U;
__edis();
}
//*****************************************************************************
//
//! Enables the DMA channel overrun interrupt.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function enables the indicated DMA channel's ability to generate an
//! interrupt upon the detection of an overrun. An overrun is when a peripheral
//! event trigger is received by the DMA before a previous trigger on that
//! channel had been serviced and its flag had been cleared.
//!
//! Note that this is the same interrupt signal as the interrupt that gets
//! generated at the beginning/end of a transfer. That interrupt must first be
//! enabled using DMA_enableInterrupt() in order for the overrun interrupt to
//! be generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_enableOverrunInterrupt(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the specified DMA channel interrupt.
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) |= 0x80U;
__edis();
}
//*****************************************************************************
//
//! Disables the DMA channel overrun interrupt.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function disables the indicated DMA channel's ability to generate an
//! interrupt upon the detection of an overrun.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_disableOverrunInterrupt(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the specified DMA channel interrupt.
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x80U;
__edis();
}
//*****************************************************************************
//
//! Clears the DMA channel error flags.
//!
//! \param base is the base address of the DMA channel control registers.
//!
//! This function clears both the DMA channel's sync error flag and its
//! overrun error flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_clearErrorFlag(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Write to the error clear bit.
//
__eallow();
(*((volatile uint16_t *)(base + 0x1U))) |= 0x80U;
__edis();
}
//*****************************************************************************
//
//! Sets the interrupt generation mode of a DMA channel interrupt.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param mode is a flag to indicate the channel interrupt mode.
//!
//! This function sets the channel interrupt mode. When the \e mode parameter
//! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the
//! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be
//! generated at the beginning of a new transfer. Generating at the beginning
//! of a new transfer is the default behavior.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode)
{
//
// Check the arguments.
//
;
__eallow();
//
// Write the selected interrupt generation mode to the register.
//
if(mode == DMA_INT_AT_END)
{
(*((volatile uint16_t *)(base + 0x0U))) |= 0x200U;
}
else
{
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x200U;
}
__edis();
}
//*****************************************************************************
//
//! Sets the DMA channel priority mode.
//!
//! \param ch1IsHighPri is a flag to indicate the channel interrupt mode.
//!
//! This function sets the channel interrupt mode. When the \e ch1IsHighPri
//! parameter is \b false, the DMA channels are serviced in round-robin mode.
//! This is the default behavior.
//!
//! If \b true, channel 1 will be given higher priority than the other
//! channels. This means that if a channel 1 trigger occurs, the current word
//! transfer on any other channel is completed and channel 1 is serviced for
//! the complete burst count. The lower-priority channel's interrupted transfer
//! will then resume.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_setPriorityMode(_Bool ch1IsHighPri)
{
__eallow();
//
// Write the selected priority mode to the register.
//
if(ch1IsHighPri)
{
(*((volatile uint16_t *)(0x00001000U + 0x4U))) |=
0x1U;
}
else
{
(*((volatile uint16_t *)(0x00001000U + 0x4U))) &=
~0x1U;
}
__edis();
}
//*****************************************************************************
//
//! Configures the source address for the DMA channel
//!
//! \param base is the base address of the DMA channel control registers.
//! \param *srcAddr is a source address.
//!
//! This function configures the source address of a DMA
//! channel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_configSourceAddress(uint32_t base, const void *srcAddr)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set up SOURCE address.
//
(*((volatile uint32_t *)(base + 0x10U))) = (uint32_t)srcAddr;
(*((volatile uint32_t *)(base + 0x12U))) = (uint32_t)srcAddr;
__edis();
}
//*****************************************************************************
//
//! Configures the destination address for the DMA channel
//!
//! \param base is the base address of the DMA channel control registers.
//! \param *destAddr is the destination address.
//!
//! This function configures the destinaton address of a DMA
//! channel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DMA_configDestAddress(uint32_t base, const void *destAddr)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set up DESTINATION address.
//
(*((volatile uint32_t *)(base + 0x18U))) = (uint32_t)destAddr;
(*((volatile uint32_t *)(base + 0x1AU))) = (uint32_t)destAddr;
__edis();
}
//*****************************************************************************
//
//! Setup DMA to transfer data on the specified channel.
//!
//! \param base is Base address of the DMA channel control register
//! \param *transfParams configuration parameter
//! Refer struct #DMA_ConfigParams
//!
//! This function configures the DMA transfer on the specified channel.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams);
//*****************************************************************************
//
//! Configures the DMA channel
//!
//! \param base is the base address of the DMA channel control registers.
//! \param *destAddr is the destination address.
//! \param *srcAddr is a source address.
//!
//! This function configures the source and destination addresses of a DMA
//! channel. The parameters are pointers to the data to be transferred.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr);
//*****************************************************************************
//
//! Configures the DMA channel's burst settings.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param size is the number of words transferred per burst.
//! \param srcStep is the amount to increment or decrement the source address
//! after each word of a burst.
//! \param destStep is the amount to increment or decrement the destination
//! address after each word of a burst.
//!
//! This function configures the size of each burst and the address step size.
//!
//! The \e size parameter is the number of words that will be transferred
//! during a single burst. Possible amounts range from 1 word to 32 words.
//!
//! The \e srcStep and \e destStep parameters specify the address step that
//! should be added to the source and destination addresses after each
//! transferred word of a burst. Only signed values from -4096 to 4095 are
//! valid.
//!
//! \note Note that regardless of what data size (configured by
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
//!
//! \return None.
//
//*****************************************************************************
extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep,
int16_t destStep);
//*****************************************************************************
//
//! Configures the DMA channel's transfer settings.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param transferSize is the number of bursts per transfer.
//! \param srcStep is the amount to increment or decrement the source address
//! after each burst of a transfer unless a wrap occurs.
//! \param destStep is the amount to increment or decrement the destination
//! address after each burst of a transfer unless a wrap occurs.
//!
//! This function configures the transfer size and the address step that is
//! made after each burst.
//!
//! The \e transferSize parameter is the number of bursts per transfer. If DMA
//! channel interrupts are enabled, they will occur after this number of bursts
//! have completed. The maximum number of bursts is 65536.
//!
//! The \e srcStep and \e destStep parameters specify the address step that
//! should be added to the source and destination addresses after each
//! transferred burst of a transfer. Only signed values from -4096 to 4095 are
//! valid. If a wrap occurs, these step values will be ignored. Wrapping is
//! configured with DMA_configWrap().
//!
//! \note Note that regardless of what data size (configured by
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep,
int16_t destStep);
//*****************************************************************************
//
//! Configures the DMA channel's wrap settings.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param srcWrapSize is the number of bursts to be transferred before a wrap
//! of the source address occurs.
//! \param srcStep is the amount to increment or decrement the source address
//! after each burst of a transfer unless a wrap occurs.
//! \param destWrapSize is the number of bursts to be transferred before a wrap
//! of the destination address occurs.
//! \param destStep is the amount to increment or decrement the destination
//! address after each burst of a transfer unless a wrap occurs.
//!
//! This function configures the DMA channel's wrap settings.
//!
//! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts
//! that are to be transferred before their respective addresses are wrapped.
//! The maximum wrap size is 65536 bursts.
//!
//! The \e srcStep and \e destStep parameters specify the address step that
//! should be added to the source and destination addresses when the wrap
//! occurs. Only signed values from -4096 to 4095 are valid.
//!
//! \note Note that regardless of what data size (configured by
//! DMA_configMode()) is used, parameters are in terms of 16-bits words.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep,
uint32_t destWrapSize, int16_t destStep);
//*****************************************************************************
//
//! Configures the DMA channel trigger and mode.
//!
//! \param base is the base address of the DMA channel control registers.
//! \param trigger is the interrupt source that triggers a DMA transfer.
//! \param config is a bit field of several configuration selections.
//!
//! This function configures the DMA channel's trigger and mode.
//!
//! The \e trigger parameter is the interrupt source that will trigger the
//! start of a DMA transfer.
//!
//! The \e config parameter is the logical OR of the following values:
//! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled,
//! the subsequent burst transfers occur without additional event triggers
//! after the first event trigger. If disabled, only one burst transfer is
//! performed per event trigger.
//! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled
//! the DMA reinitializes when the transfer count is zero and waits for the
//! next interrupt event trigger. If disabled, the DMA stops and clears the
//! run status bit.
//! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects
//! whether the databus width is 16 or 32 bits.
//!
//! \return None.
//
//*****************************************************************************
extern void
DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: ecap.h
//
// TITLE: C28x ECAP driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ecap_api eCAP
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Includes
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_ecap.h
//
// TITLE: Definitions for the ECAP registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the ECAP register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL2 register
//
//*************************************************************************************************
// flags.
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECEINT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAPSYNCINSEL register
//
//*************************************************************************************************
//*****************************************************************************
//
// eCAP minimum and maximum values
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to ECAP_enableInterrupt(),
// ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as
// the intFlags parameter and returned by ECAP_getInterruptSource().
//
//*****************************************************************************
//! Event 1 ISR source
//!
//! Event 2 ISR source
//!
//! Event 3 ISR source
//!
//! Event 4 ISR source
//!
//! Counter overflow ISR source
//!
//! Counter equals period ISR source
//!
//! Counter equals compare ISR source
//!
//*****************************************************************************
//
//! Values that can be passed to ECAP_setEmulationMode() as the
//! \e mode parameter.
//
//*****************************************************************************
typedef enum
{
//! TSCTR is stopped on emulation suspension
ECAP_EMULATION_STOP = 0x0U,
//! TSCTR runs until 0 before stopping on emulation suspension
ECAP_EMULATION_RUN_TO_ZERO = 0x1U,
//! TSCTR is not affected by emulation suspension
ECAP_EMULATION_FREE_RUN = 0x2U
}ECAP_EmulationMode;
//*****************************************************************************
//
//! Values that can be passed to ECAP_setCaptureMode() as the
//! \e mode parameter.
//
//*****************************************************************************
typedef enum
{
//! eCAP operates in continuous capture mode
ECAP_CONTINUOUS_CAPTURE_MODE = 0U,
//! eCAP operates in one shot capture mode
ECAP_ONE_SHOT_CAPTURE_MODE = 1U
}ECAP_CaptureMode;
//*****************************************************************************
//
//! Values that can be passed to ECAP_setEventPolarity(),ECAP_setCaptureMode(),
//! ECAP_enableCounterResetOnEvent(),ECAP_disableCounterResetOnEvent(),
//! ECAP_getEventTimeStamp(),ECAP_setDMASource() as the \e event parameter.
//
//*****************************************************************************
typedef enum
{
ECAP_EVENT_1 = 0U, //!< eCAP event 1
ECAP_EVENT_2 = 1U, //!< eCAP event 2
ECAP_EVENT_3 = 2U, //!< eCAP event 3
ECAP_EVENT_4 = 3U //!< eCAP event 4
}ECAP_Events;
//*****************************************************************************
//
//! Values that can be passed to ECAP_setSyncOutMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! sync out on the sync in signal and software force
ECAP_SYNC_OUT_SYNCI = 0x00U,
//! sync out on counter equals period
ECAP_SYNC_OUT_COUNTER_PRD = 0x40U,
//! Disable sync out signal
ECAP_SYNC_OUT_DISABLED = 0x80U
}ECAP_SyncOutMode;
//*****************************************************************************
//
//! Values that can be passed to ECAP_setAPWMPolarity() as the \e polarity
//! parameter.
//
//*****************************************************************************
typedef enum
{
ECAP_APWM_ACTIVE_HIGH = 0x000, //!< APWM is active high
ECAP_APWM_ACTIVE_LOW = 0x400 //!< APWM is active low
}ECAP_APWMPolarity;
//*****************************************************************************
//
//! Values that can be passed to ECAP_setEventPolarity() as the \e polarity
//! parameter.
//
//*****************************************************************************
typedef enum
{
ECAP_EVNT_RISING_EDGE = 0U, //!< Rising edge polarity
ECAP_EVNT_FALLING_EDGE = 1U //!< Falling edge polarity
}ECAP_EventPolarity;
//*****************************************************************************
//
//! Values that can be passed to ECAP_selectECAPInput() as the \e input
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! GPIO Input Crossbar output signal-1
ECAP_INPUT_INPUTXBAR1 = 0,
//! GPIO Input Crossbar output signal-2
ECAP_INPUT_INPUTXBAR2 = 1,
//! GPIO Input Crossbar output signal-3
ECAP_INPUT_INPUTXBAR3 = 2,
//! GPIO Input Crossbar output signal-4
ECAP_INPUT_INPUTXBAR4 = 3,
//! GPIO Input Crossbar output signal-5
ECAP_INPUT_INPUTXBAR5 = 4,
//! GPIO Input Crossbar output signal-6
ECAP_INPUT_INPUTXBAR6 = 5,
//! GPIO Input Crossbar output signal-7
ECAP_INPUT_INPUTXBAR7 = 6,
//! GPIO Input Crossbar output signal-8
ECAP_INPUT_INPUTXBAR8 = 7,
//! GPIO Input Crossbar output signal-9
ECAP_INPUT_INPUTXBAR9 = 8,
//! GPIO Input Crossbar output signal-10
ECAP_INPUT_INPUTXBAR10 = 9,
//! GPIO Input Crossbar output signal-11
ECAP_INPUT_INPUTXBAR11 = 10,
//! GPIO Input Crossbar output signal-12
ECAP_INPUT_INPUTXBAR12 = 11,
//! GPIO Input Crossbar output signal-13
ECAP_INPUT_INPUTXBAR13 = 12,
//! GPIO Input Crossbar output signal-14
ECAP_INPUT_INPUTXBAR14 = 13,
//! GPIO Input Crossbar output signal-15
ECAP_INPUT_INPUTXBAR15 = 14,
//! GPIO Input Crossbar output signal-16
ECAP_INPUT_INPUTXBAR16 = 15,
//! CLB1 CLBOUT14 input for ECAP1 instance
ECAP_INPUT_ECAP1_CLB1_CLBOUT14 = 16,
//! CLB2 CLBOUT14 input for ECAP2 instance
ECAP_INPUT_ECAP2_CLB2_CLBOUT14 = 16,
//! CLB1 CLBOUT14 input for ECAP3 instance
ECAP_INPUT_ECAP3_CLB1_CLBOUT14 = 16,
//! CLB1 CLBOUT15 input for ECAP1 instance
ECAP_INPUT_ECAP1_CLB1_CLBOUT15 = 17,
//! CLB2 CLBOUT15 input for ECAP2 instance
ECAP_INPUT_ECAP2_CLB2_CLBOUT15 = 17,
//! CLB1 CLBOUT15 input for ECAP3 instance
ECAP_INPUT_ECAP3_CLB1_CLBOUT15 = 17,
//! CLB2 CLBOUT14 input for ECAP1 instance
ECAP_INPUT_ECAP1_CLB2_CLBOUT14 = 18,
//! CLB1 CLBOUT14 input for ECAP2 instance
ECAP_INPUT_ECAP2_CLB1_CLBOUT14 = 18,
//! CLB2 CLBOUT14 input for ECAP3 instance
ECAP_INPUT_ECAP3_CLB2_CLBOUT14 = 18,
//! CLB2 CLBOUT15 input for ECAP1 instance
ECAP_INPUT_ECAP1_CLB2_CLBOUT15 = 19,
//! CLB1 CLBOUT15 input for ECAP2 instance
ECAP_INPUT_ECAP2_CLB1_CLBOUT15 = 19,
//! CLB2 CLBOUT15 input for ECAP3 instance
ECAP_INPUT_ECAP3_CLB2_CLBOUT15 = 19,
//! CANA INT0 Input
ECAP_INPUT_CANA_INT0 = 20,
//! Output Xbar Output-1
ECAP_INPUT_OUTPUTXBAR1 = 24,
//! Output Xbar Output-2
ECAP_INPUT_OUTPUTXBAR2 = 25,
//! Output Xbar Output-3
ECAP_INPUT_OUTPUTXBAR3 = 26,
//! Output Xbar Output-4
ECAP_INPUT_OUTPUTXBAR4 = 27,
//! Output Xbar Output-5
ECAP_INPUT_OUTPUTXBAR5 = 28,
//! Output Xbar Output-6
ECAP_INPUT_OUTPUTXBAR6 = 29,
//! Output Xbar Output-7
ECAP_INPUT_OUTPUTXBAR7 = 30,
//! Output Xbar Output-8
ECAP_INPUT_OUTPUTXBAR8 = 31,
//! ADCC Event4
ECAP_INPUT_ADC_C_EVENT4 = 36,
//! ADCC Event3
ECAP_INPUT_ADC_C_EVENT3 = 37,
//! ADCC Event2
ECAP_INPUT_ADC_C_EVENT2 = 38,
//! ADCC Event1
ECAP_INPUT_ADC_C_EVENT1 = 39,
//! ADCB Event4
ECAP_INPUT_ADC_B_EVENT4 = 40,
//! ADCB Event3
ECAP_INPUT_ADC_B_EVENT3 = 41,
//! ADCB Event2
ECAP_INPUT_ADC_B_EVENT2 = 42,
//! ADCB Event1
ECAP_INPUT_ADC_B_EVENT1 = 43,
//! ADCA Event4
ECAP_INPUT_ADC_A_EVENT4 = 44,
//! ADCA Event3
ECAP_INPUT_ADC_A_EVENT3 = 45,
//! ADCA Event2
ECAP_INPUT_ADC_A_EVENT2 = 46,
//! ADCA Event1
ECAP_INPUT_ADC_A_EVENT1 = 47,
//! FSIA Rx MSR Line
ECAP_INPUT_FSIA_RX_MSR_LINE = 48,
//! FSIA Rx MSR Line Rise
ECAP_INPUT_FSIA_RX_MSR_LINE_RISE = 49,
//! FSIA Rx MSR Line Fall
ECAP_INPUT_FSIA_RX_MSR_LINE_FALL = 50,
//! SDFM-2 Filter-1 Compare Low Trip
ECAP_INPUT_SDFM2_FLT1_COMPARE_LOW = 60,
//! SDFM-2 Filter-2 Compare Low Trip
ECAP_INPUT_SDFM2_FLT2_COMPARE_LOW = 61,
//! SDFM-2 Filter-3 Compare Low Trip
ECAP_INPUT_SDFM2_FLT3_COMPARE_LOW = 62,
//! SDFM-2 Filter-4 Compare Low Trip
ECAP_INPUT_SDFM2_FLT4_COMPARE_LOW = 63,
//! SDFM-1 Filter-1 Compare Low Trip
ECAP_INPUT_SDFM1_FLT1_COMPARE_LOW = 64,
//! SDFM-1 Filter-2 Compare Low Trip
ECAP_INPUT_SDFM1_FLT2_COMPARE_LOW = 65,
//! SDFM-1 Filter-3 Compare Low Trip
ECAP_INPUT_SDFM1_FLT3_COMPARE_LOW = 66,
//! SDFM-1 Filter-4 Compare Low Trip
ECAP_INPUT_SDFM1_FLT4_COMPARE_LOW = 67,
//! SDFM-2 Filter-1 Compare Z Trip
ECAP_INPUT_SDFM2_FLT1_COMPARE_Z = 68,
//! SDFM-2 Filter-2 Compare Low Trip
ECAP_INPUT_SDFM2_FLT2_COMPARE_Z = 69,
//! SDFM-2 Filter-3 Compare Low Trip
ECAP_INPUT_SDFM2_FLT3_COMPARE_Z = 70,
//! SDFM-2 Filter-4 Compare Low Trip
ECAP_INPUT_SDFM2_FLT4_COMPARE_Z = 71,
//! SDFM-1 Filter-1 Compare Z Trip
ECAP_INPUT_SDFM1_FLT1_COMPARE_Z = 72,
//! SDFM-1 Filter-2 Compare Low Trip
ECAP_INPUT_SDFM1_FLT2_COMPARE_Z = 73,
//! SDFM-1 Filter-3 Compare Low Trip
ECAP_INPUT_SDFM1_FLT3_COMPARE_Z = 74,
//! SDFM-1 Filter-4 Compare Low Trip
ECAP_INPUT_SDFM1_FLT4_COMPARE_Z = 75,
//! SDFM-2 Filter-1 Compare High Trip
ECAP_INPUT_SDFM2_FLT1_COMPARE_HIGH = 76,
//! SDFM-2 Filter-2 Compare High Trip
ECAP_INPUT_SDFM2_FLT2_COMPARE_HIGH = 77,
//! SDFM-2 Filter-3 Compare High Trip
ECAP_INPUT_SDFM2_FLT3_COMPARE_HIGH = 78,
//! SDFM-2 Filter-4 Compare High Trip
ECAP_INPUT_SDFM2_FLT4_COMPARE_HIGH = 79,
//! SDFM-1 Filter-1 Compare High Trip
ECAP_INPUT_SDFM1_FLT1_COMPARE_HIGH = 80,
//! SDFM-1 Filter-2 Compare High Trip
ECAP_INPUT_SDFM1_FLT2_COMPARE_HIGH = 81,
//! SDFM-1 Filter-3 Compare High Trip
ECAP_INPUT_SDFM1_FLT3_COMPARE_HIGH = 82,
//! SDFM-1 Filter-4 Compare High Trip
ECAP_INPUT_SDFM1_FLT4_COMPARE_HIGH = 83,
//! SDFM-2 Filter-1 Compare High Trip or Low Trip
ECAP_INPUT_SDFM2_FLT1_COMPARE_HIGH_OR_LOW = 84,
//! SDFM-2 Filter-2 Compare High Trip or Low Trip
ECAP_INPUT_SDFM2_FLT2_COMPARE_HIGH_OR_LOW = 85,
//! SDFM-2 Filter-3 Compare High Trip or Low Trip
ECAP_INPUT_SDFM2_FLT3_COMPARE_HIGH_OR_LOW = 86,
//! SDFM-2 Filter-4 Compare High Trip or Low Trip
ECAP_INPUT_SDFM2_FLT4_COMPARE_HIGH_OR_LOW = 87,
//! SDFM-1 Filter-1 Compare High Trip or Low Trip
ECAP_INPUT_SDFM1_FLT1_COMPARE_HIGH_OR_LOW = 88,
//! SDFM-1 Filter-2 Compare High Trip or Low Trip
ECAP_INPUT_SDFM1_FLT2_COMPARE_HIGH_OR_LOW = 89,
//! SDFM-1 Filter-3 Compare High Trip or Low Trip
ECAP_INPUT_SDFM1_FLT3_COMPARE_HIGH_OR_LOW = 90,
//! SDFM-1 Filter-4 Compare High Trip or Low Trip
ECAP_INPUT_SDFM1_FLT4_COMPARE_HIGH_OR_LOW = 91,
//! Compare Subsystem-1 Low Trip
ECAP_INPUT_CMPSS1_CTRIP_LOW = 96,
//! Compare Subsystem-2 Low Trip
ECAP_INPUT_CMPSS2_CTRIP_LOW = 97,
//! Compare Subsystem-3 Low Trip
ECAP_INPUT_CMPSS3_CTRIP_LOW = 98,
//! Compare Subsystem-4 Low Trip
ECAP_INPUT_CMPSS4_CTRIP_LOW = 99,
//! Compare Subsystem-1 High Trip
ECAP_INPUT_CMPSS1_CTRIP_HIGH = 108,
//! Compare Subsystem-2 High Trip
ECAP_INPUT_CMPSS2_CTRIP_HIGH = 109,
//! Compare Subsystem-3 High Trip
ECAP_INPUT_CMPSS3_CTRIP_HIGH = 110,
//! Compare Subsystem-4 High Trip
ECAP_INPUT_CMPSS4_CTRIP_HIGH = 111,
//! GPIO8
ECAP_INPUT_GPIO8 = 115,
//! GPIO9
ECAP_INPUT_GPIO9 = 116,
//! GPIO22
ECAP_INPUT_GPIO22 = 117,
//! GPIO23
ECAP_INPUT_GPIO23 = 118,
//! Compare Subsystem-1 High Trip or Low Trip
ECAP_INPUT_CMPSS1_CTRIP_HIGH_OR_LOW = 120,
//! Compare Subsystem-2 High Trip or Low Trip
ECAP_INPUT_CMPSS2_CTRIP_HIGH_OR_LOW = 121,
//! Compare Subsystem-3 High Trip or Low Trip
ECAP_INPUT_CMPSS3_CTRIP_HIGH_OR_LOW = 122,
//! Compare Subsystem-4 High Trip or Low Trip
ECAP_INPUT_CMPSS4_CTRIP_HIGH_OR_LOW = 123,
//! GPTRIP7 input for instance ECAP1
ECAP_INPUT_ECAP1_GPTRIP7 = 127,
//! GPTRIP8 input for instance ECAP2
ECAP_INPUT_ECAP2_GPTRIP8 = 127,
//! GPTRIP9 input for instance ECAP3
ECAP_INPUT_ECAP3_GPTRIP9 = 127,
}ECAP_InputCaptureSignals;
//*****************************************************************************
//
//! Values that can be passed to ECAP_setSyncInPulseSource() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! Disable Sync-in
ECAP_SYNC_IN_PULSE_SRC_DISABLE = 0x0,
//! Sync-in source is EPWM1 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1 = 0x1,
//! Sync-in source is EPWM2 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2 = 0x2,
//! Sync-in source is EPWM3 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3 = 0x3,
//! Sync-in source is EPWM4 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4 = 0x4,
//! Sync-in source is EPWM5 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5 = 0x5,
//! Sync-in source is EPWM6 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6 = 0x6,
//! Sync-in source is EPWM7 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7 = 0x7,
//! Sync-in source is EPWM8 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8 = 0x8,
//! Sync-in source is ECAP1 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1 = 0x11,
//! Sync-in source is ECAP2 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2 = 0x12,
//! Sync-in source is ECAP3 sync-out signal
ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3 = 0x13,
//! Sync-in source is Input XBAR out5 signal
ECAP_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT5 = 0x18,
//! Sync-in source is Input XBAR out6 signal
ECAP_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT6 = 0x19,
//! Sync-in source is FSI RXA RX signal
ECAP_SYNC_IN_PULSE_SRC_FSIRXA_RX_TRIG1 = 0x1F,
}ECAP_SyncInPulseSource;
//*****************************************************************************
//
//! \internal
//! Checks eCAP base address.
//!
//! \param base specifies the eCAP module base address.
//!
//! This function determines if an eCAP module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the input prescaler.
//!
//! \param base is the base address of the ECAP module.
//! \param preScalerValue is the pre scaler value for ECAP input
//!
//! This function divides the ECAP input scaler. The pre scale value is
//! doubled inside the module. For example a preScalerValue of 5 will divide
//! the scaler by 10. Use a value of 1 to divide the pre scaler by 1.
//! The \e preScalerValue should be less than \b ECAP_MAX_PRESCALER_VALUE.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setEventPrescaler(uint32_t base,
uint16_t preScalerValue)
{
;
;
__eallow();
//
// Write to PRESCALE bit
//
(*((volatile uint16_t *)(base + 0x14U))) =
(((*((volatile uint16_t *)(base + 0x14U))) & (~0x3E00U)) |
(preScalerValue << 9U));
__edis();
}
//*****************************************************************************
//
//! Sets the Capture event polarity.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number.
//! \param polarity is the polarity of the event.
//!
//! This function sets the polarity of a given event. The value of event
//! is between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 inclusive corresponding to
//! the four available events.For each event the polarity value determines the
//! edge on which the capture is activated. For a rising edge use a polarity
//! value of \b ECAP_EVNT_RISING_EDGE and for a falling edge use a polarity of
//! \b ECAP_EVNT_FALLING_EDGE.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setEventPolarity(uint32_t base,
ECAP_Events event,
ECAP_EventPolarity polarity)
{
uint16_t shift;
;
shift = ((uint16_t)event) << 1U;
__eallow();
//
// Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL
//
(*((volatile uint16_t *)(base + 0x14U))) =
((*((volatile uint16_t *)(base + 0x14U))) & ~(1U << shift)) |
((uint16_t)polarity << shift);
__edis();
}
//*****************************************************************************
//
//! Sets the capture mode.
//!
//! \param base is the base address of the ECAP module.
//! \param mode is the capture mode.
//! \param event is the event number at which the counter stops or wraps.
//!
//! This function sets the eCAP module to a continuous or one-shot mode.
//! The value of mode should be either \b ECAP_CONTINUOUS_CAPTURE_MODE or
//! \b ECAP_ONE_SHOT_CAPTURE_MODE corresponding to continuous or one-shot mode
//! respectively.
//!
//! The value of event determines the event number at which the counter stops
//! (in one-shot mode) or the counter wraps (in continuous mode). The value of
//! event should be between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 corresponding
//! to the valid event numbers.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setCaptureMode(uint32_t base,
ECAP_CaptureMode mode,
ECAP_Events event)
{
;
__eallow();
//
// Write to CONT/ONESHT
//
(*((volatile uint16_t *)(base + 0x15U))) =
(((*((volatile uint16_t *)(base + 0x15U))) & (~0x1U)) |
(uint16_t)mode);
//
// Write to STOP_WRAP
//
(*((volatile uint16_t *)(base + 0x15U))) =
(((*((volatile uint16_t *)(base + 0x15U))) & (~0x6U)) |
(((uint16_t)event) << 1U ));
__edis();
}
//*****************************************************************************
//
//! Re-arms the eCAP module.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function re-arms the eCAP module.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_reArm(uint32_t base)
{
;
__eallow();
//
// Write to RE-ARM bit
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x8U;
__edis();
}
//*****************************************************************************
//
//! Enables interrupt source.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source to be enabled.
//!
//! This function sets and enables eCAP interrupt source. The following are
//! valid interrupt sources.
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates
//! interrupt
//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates
//! interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableInterrupt(uint32_t base,
uint16_t intFlags)
{
;
;
__eallow();
//
// Set bits in ECEINT register
//
(*((volatile uint16_t *)(base + 0x16U))) |= intFlags;
__edis();
}
//*****************************************************************************
//
//! Disables interrupt source.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source to be disabled.
//!
//! This function clears and disables eCAP interrupt source. The following are
//! valid interrupt sources.
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates
//! interrupt
//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates
//! interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableInterrupt(uint32_t base,
uint16_t intFlags)
{
;
;
__eallow();
//
// Clear bits in ECEINT register
//
(*((volatile uint16_t *)(base + 0x16U))) &= ~intFlags;
__edis();
}
//*****************************************************************************
//
//! Returns the interrupt flag.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the eCAP interrupt flag. The following are valid
//! interrupt sources corresponding to the eCAP interrupt flag.
//!
//! \return Returns the eCAP interrupt that has occurred. The following are
//! valid return values.
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates
//! interrupt
//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates
//! interrupt
//!
//! \note - User can check if a combination of various interrupts have occurred
//! by ORing the above return values.
//
//*****************************************************************************
static inline uint16_t ECAP_getInterruptSource(uint32_t base)
{
;
//
// Return contents of ECFLG register
//
return((*((volatile uint16_t *)(base + 0x17U))) & 0xFEU);
}
//*****************************************************************************
//
//! Returns the Global interrupt flag.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the eCAP Global interrupt flag.
//!
//! \return Returns true if there is a global eCAP interrupt, false otherwise.
//
//*****************************************************************************
static inline _Bool ECAP_getGlobalInterruptStatus(uint32_t base)
{
;
//
// Return contents of Global interrupt bit
//
return(((*((volatile uint16_t *)(base + 0x17U))) & 0x1U) == 0x1U);
}
//*****************************************************************************
//
//! Clears interrupt flag.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source.
//!
//! This function clears eCAP interrupt flags. The following are valid
//! interrupt sources.
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates
//! interrupt
//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates
//! interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_clearInterrupt(uint32_t base,
uint16_t intFlags)
{
;
;
//
// Write to ECCLR register
//
(*((volatile uint16_t *)(base + 0x18U))) = intFlags;
}
//*****************************************************************************
//
//! Clears global interrupt flag
//!
//! \param base is the base address of the ECAP module.
//!
//! This function clears the global interrupt bit.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_clearGlobalInterrupt(uint32_t base)
{
;
//
// Write to INT bit
//
(*((volatile uint16_t *)(base + 0x18U))) = 0x1U;
}
//*****************************************************************************
//
//! Forces interrupt source.
//!
//! \param base is the base address of the ECAP module.
//! \param intFlags is the interrupt source.
//!
//! This function forces and enables eCAP interrupt source. The following are
//! valid interrupt sources.
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt
//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt
//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates
//! interrupt
//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates
//! interrupt
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_forceInterrupt(uint32_t base,
uint16_t intFlags)
{
;
;
__eallow();
//
// Write to ECFRC register
//
(*((volatile uint16_t *)(base + 0x19U))) = intFlags;
__edis();
}
//*****************************************************************************
//
//! Sets eCAP in Capture mode.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function sets the eCAP module to operate in Capture mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableCaptureMode(uint32_t base)
{
;
__eallow();
//
// Clear CAP/APWM bit
//
(*((volatile uint16_t *)(base + 0x15U))) &= ~0x200U;
__edis();
}
//*****************************************************************************
//
//! Sets eCAP in APWM mode.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function sets the eCAP module to operate in APWM mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableAPWMMode(uint32_t base)
{
;
__eallow();
//
// Set CAP/APWM bit
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x200U;
__edis();
}
//*****************************************************************************
//
//! Enables counter reset on an event.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number the time base gets reset.
//!
//! This function enables the base timer, TSCTR, to be reset on capture
//! event provided by the variable event. Valid inputs for event are
//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableCounterResetOnEvent(uint32_t base,
ECAP_Events event)
{
;
__eallow();
//
// Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
//
(*((volatile uint16_t *)(base + 0x14U))) |= 1U << ((2U * (uint16_t)event) + 1U);
__edis();
}
//*****************************************************************************
//
//! Disables counter reset on events.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number the time base gets reset.
//!
//! This function disables the base timer, TSCTR, from being reset on capture
//! event provided by the variable event. Valid inputs for event are
//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableCounterResetOnEvent(uint32_t base,
ECAP_Events event)
{
;
__eallow();
//
// Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits
//
(*((volatile uint16_t *)(base + 0x14U))) &= ~(1U << ((2U * (uint16_t)event) + 1U));
__edis();
}
//*****************************************************************************
//
//! Enables time stamp capture.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function enables time stamp count to be captured
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableTimeStampCapture(uint32_t base)
{
;
__eallow();
//
// Set CAPLDEN bit
//
(*((volatile uint16_t *)(base + 0x14U))) |= 0x100U;
__edis();
}
//*****************************************************************************
//
//! Disables time stamp capture.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function disables time stamp count to be captured
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableTimeStampCapture(uint32_t base)
{
;
__eallow();
//
// Clear CAPLDEN bit
//
(*((volatile uint16_t *)(base + 0x14U))) &= ~0x100U;
__edis();
}
//*****************************************************************************
//
//! Sets a phase shift value count.
//!
//! \param base is the base address of the ECAP module.
//! \param shiftCount is the phase shift value.
//!
//! This function writes a phase shift value to be loaded into the main time
//! stamp counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount)
{
;
//
// Write to CTRPHS
//
(*((volatile uint32_t *)(base + 0x2U))) = shiftCount;
}
//*****************************************************************************
//
//! Set up the source for sync-in pulse.
//!
//! \param base is the base address of the ECAP module.
//! \param source is the sync-in pulse source.
//!
//! This function set the sync out pulse mode.
//! Valid values for mode are:
//! - ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_EPWMx - sync-in pulse source can be
//! any of the EPWMx sync-out
//! signal
//! - ECAP_SYNC_IN_PULSE_SRC_SYNCOUT_ECAPx - sync-in pulse source can be
//! selected as any of the ECAPx
//! sync-out signal
//! - ECAP_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT5-6 - sync-in pulse source can be
//! selected as any of the Input
//! xbar out5-6 signal
//! - ECAP_SYNC_IN_PULSE_SRC_FSI_RXA_RX_TRIG1 - sync-in pulse source can be
//! selected as FSI RXA RX trig
//! signal
//! - ECAP_SYNC_IN_PULSE_SRC_DISABLE - sync-in pulse is disabled for the
//! ECAP module
//!
//! \return None.
//
//*****************************************************************************
static inline void
ECAP_setSyncInPulseSource(uint32_t base, ECAP_SyncInPulseSource source)
{
;
__eallow();
//
// Set ECAP Sync-In Source Mode.
//
(*((volatile uint16_t *)(base + 0x1EU))) =
((*((volatile uint16_t *)(base + 0x1EU))) & (~0x1FU)) |
((uint16_t)source & 0x1FU);
__edis();
}
//*****************************************************************************
//
//! Enable counter loading with phase shift value.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function enables loading of the counter with the value present in the
//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_enableLoadCounter(uint32_t base)
{
;
__eallow();
//
// Write to SYNCI_EN
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x20U;
__edis();
}
//*****************************************************************************
//
//! Disable counter loading with phase shift value.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function disables loading of the counter with the value present in the
//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_disableLoadCounter(uint32_t base)
{
;
__eallow();
//
// Write to SYNCI_EN
//
(*((volatile uint16_t *)(base + 0x15U))) &= ~0x20U;
__edis();
}
//*****************************************************************************
//
//! Load time stamp counter
//!
//! \param base is the base address of the ECAP module.
//!
//! This function forces the value in the phase shift counter register to be
//! loaded into Time stamp counter register.
//! Make sure to enable loading of Time stamp counter by calling
//! ECAP_enableLoadCounter() function before calling this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_loadCounter(uint32_t base)
{
;
__eallow();
//
// Write to SWSYNC
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x100U;
__edis();
}
//*****************************************************************************
//
//! Configures Sync out signal mode.
//!
//! \param base is the base address of the ECAP module.
//! \param mode is the sync out mode.
//!
//! This function sets the sync out mode. Valid parameters for mode are:
//! - ECAP_SYNC_OUT_SYNCI - Trigger sync out on sync-in event.
//! - ECAP_SYNC_OUT_COUNTER_PRD - Trigger sync out when counter equals period.
//! - ECAP_SYNC_OUT_DISABLED - Disable sync out.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setSyncOutMode(uint32_t base,
ECAP_SyncOutMode mode)
{
;
__eallow();
//
// Write to SYNCO_SEL
//
(*((volatile uint16_t *)(base + 0x15U))) =
(((*((volatile uint16_t *)(base + 0x15U))) & (~0xC0U)) |
(uint16_t)mode);
__edis();
}
//*****************************************************************************
//
//! Stops Time stamp counter.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function stops the time stamp counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_stopCounter(uint32_t base)
{
;
__eallow();
//
// Clear TSCTR
//
(*((volatile uint16_t *)(base + 0x15U))) &= ~0x10U;
__edis();
}
//*****************************************************************************
//
//! Starts Time stamp counter.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function starts the time stamp counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_startCounter(uint32_t base)
{
;
__eallow();
//
// Set TSCTR
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x10U;
__edis();
}
//*****************************************************************************
//
//! Set eCAP APWM polarity.
//!
//! \param base is the base address of the ECAP module.
//! \param polarity is the polarity of APWM
//!
//! This function sets the polarity of the eCAP in APWM mode. Valid inputs for
//! polarity are:
//! - ECAP_APWM_ACTIVE_HIGH - For active high.
//! - ECAP_APWM_ACTIVE_LOW - For active low.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMPolarity(uint32_t base,
ECAP_APWMPolarity polarity)
{
;
__eallow();
(*((volatile uint16_t *)(base + 0x15U))) =
(((*((volatile uint16_t *)(base + 0x15U))) & ~0x400U) |
(uint16_t)polarity);
__edis();
}
//*****************************************************************************
//
//! Set eCAP APWM period.
//!
//! \param base is the base address of the ECAP module.
//! \param periodCount is the period count for APWM.
//!
//! This function sets the period count of the APWM waveform.
//! periodCount takes the actual count which is written to the register. The
//! user is responsible for converting the desired frequency or time into
//! the period count.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount)
{
;
//
// Write to CAP1
//
(*((volatile uint32_t *)(base + 0x4U))) = periodCount;
}
//*****************************************************************************
//
//! Set eCAP APWM on or off time count.
//!
//! \param base is the base address of the ECAP module.
//! \param compareCount is the on or off count for APWM.
//!
//! This function sets the on or off time count of the APWM waveform depending
//! on the polarity of the output. If the output , as set by
//! ECAP_setAPWMPolarity(), is active high then compareCount determines the on
//! time. If the output is active low then compareCount determines the off
//! time. compareCount takes the actual count which is written to the register.
//! The user is responsible for converting the desired frequency or time into
//! the appropriate count value.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount)
{
;
//
// Write to CAP2
//
(*((volatile uint32_t *)(base + 0x6U))) = compareCount;
}
//*****************************************************************************
//
//! Load eCAP APWM shadow period.
//!
//! \param base is the base address of the ECAP module.
//! \param periodCount is the shadow period count for APWM.
//!
//! This function sets the shadow period count of the APWM waveform.
//! periodCount takes the actual count which is written to the register. The
//! user is responsible for converting the desired frequency or time into
//! the period count.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMShadowPeriod(uint32_t base,
uint32_t periodCount)
{
;
//
// Write to CAP3
//
(*((volatile uint32_t *)(base + 0x8U))) = periodCount;
}
//*****************************************************************************
//
//! Set eCAP APWM shadow on or off time count.
//!
//! \param base is the base address of the ECAP module.
//! \param compareCount is the on or off count for APWM.
//!
//! This function sets the shadow on or off time count of the APWM waveform
//! depending on the polarity of the output. If the output , as set by
//! ECAP_setAPWMPolarity() , is active high then compareCount determines the
//! on time. If the output is active low then compareCount determines the off
//! time. compareCount takes the actual count which is written to the register.
//! The user is responsible for converting the desired frequency or time into
//! the appropriate count value.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setAPWMShadowCompare(uint32_t base,
uint32_t compareCount)
{
;
//
// Write to CAP4
//
(*((volatile uint32_t *)(base + 0xAU))) = compareCount;
}
//*****************************************************************************
//
//! Returns the time base counter value.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the time base counter value.
//!
//! \return Returns the time base counter value.
//
//*****************************************************************************
static inline uint32_t ECAP_getTimeBaseCounter(uint32_t base)
{
;
//
// Read the Time base counter value
//
return((*((volatile uint32_t *)(base + 0x0U))));
}
//*****************************************************************************
//
//! Returns event time stamp.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the event number.
//!
//! This function returns the current time stamp count of the given event.
//! Valid values for event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return Event time stamp value or 0 if \e event is invalid.
//
//*****************************************************************************
static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event)
{
uint32_t count;
;
switch(event)
{
case ECAP_EVENT_1:
//
// Read CAP1 register
//
count = (*((volatile uint32_t *)(base + 0x4U)));
break;
case ECAP_EVENT_2:
//
// Read CAP2 register
//
count = (*((volatile uint32_t *)(base + 0x6U)));
break;
case ECAP_EVENT_3:
//
// Read CAP3 register
//
count = (*((volatile uint32_t *)(base + 0x8U)));
break;
case ECAP_EVENT_4:
//
// Read CAP4 register
//
count = (*((volatile uint32_t *)(base + 0xAU)));
break;
default:
//
// Invalid event parameter
//
count = 0U;
break;
}
return(count);
}
//*****************************************************************************
//
//! Select eCAP input.
//!
//! \param base is the base address of the ECAP module.
//! \param input is the eCAP input signal.
//!
//! This function selects the eCAP input signal.
//!
//! Please refer to the ::ECAP_InputCaptureSignals Enum for the valid values
//! to be passed to \e input parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_selectECAPInput(uint32_t base,
ECAP_InputCaptureSignals input)
{
;
__eallow();
//
// Write to ECCTL0
//
(*((volatile uint16_t *)(base + 0x12U))) =
(((*((volatile uint16_t *)(base + 0x12U))) & ~0x7FU) |
(uint16_t)input);
__edis();
}
//*****************************************************************************
//
//! Resets eCAP counters and flags.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function resets the main counter (TSCTR register), event filter,
//! modulo counter, capture events and counter overflow flags
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_resetCounters(uint32_t base)
{
;
__eallow();
//
// Write to ECCTL2
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x800U;
__edis();
}
//*****************************************************************************
//
//! Sets the eCAP DMA source.
//!
//! \param base is the base address of the ECAP module.
//! \param event is the eCAP event for the DMA
//!
//! This function sets the eCAP event source for the DMA trigger.
//! Valid values for \e event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4.
//!
//! \return None.
//
//*****************************************************************************
static inline void ECAP_setDMASource(uint32_t base, ECAP_Events event)
{
;
__eallow();
//
// Write to ECCTL2
//
(*((volatile uint16_t *)(base + 0x15U))) =
(((*((volatile uint16_t *)(base + 0x15U))) & ~0x3000U) |
((uint16_t)event << 12U));
__edis();
}
//*****************************************************************************
//
//! Return the Modulo counter status.
//!
//! \param base is the base address of the ECAP module.
//!
//! This function returns the modulo counter status, indicating which register
//! gets loaded on the next capture event.
//!
//! \return Returns an \b ECAP_EVENT_n value indicating that CAPn is the
//! register to be loaded on the next event.
//
//*****************************************************************************
static inline ECAP_Events ECAP_getModuloCounterStatus(uint32_t base)
{
uint16_t counterStatusValue;
;
counterStatusValue = ((((*((volatile uint16_t *)(base + 0x15U))) &
0xC000U) >>
14U));
//
// Read MODCNTRSTS bit
//
return((ECAP_Events)(counterStatusValue));
}
//*****************************************************************************
//
//! Configures emulation mode.
//!
//! \param base is the base address of the ECAP module.
//! \param mode is the emulation mode.
//!
//! This function configures the eCAP counter, TSCTR, to the desired emulation
//! mode when emulation suspension occurs. Valid inputs for mode are:
//! - ECAP_EMULATION_STOP - Counter is stopped immediately.
//! - ECAP_EMULATION_RUN_TO_ZERO - Counter runs till it reaches 0.
//! - ECAP_EMULATION_FREE_RUN - Counter is not affected.
//!
//! \return None.
//
//*****************************************************************************
extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: epg.h
//
// TITLE: C28x EPG driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//###########################################################################
//
// FILE: hw_epg.h
//
// TITLE: Definitions for the EPG registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the EPG register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL2 register
//
//*************************************************************************************************
// output 0.
// output 1.
// output 2.
// output 3.
// output 4.
// output 5.
// output 6.
// output 7.
//*************************************************************************************************
//
// The following are defines for the bit fields in the GCTL3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGCOMMIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTSTS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV0_CTL0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV0_CLKOFFSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV1_CTL0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLKDIV1_CLKOFFSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SIGGEN0_CTL0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SIGGEN0_CTL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGMXSEL0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGMXSELLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPGMXSELCOMMIT register
//
//*************************************************************************************************
//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to EPG_selectGlobalOutput() as the \e gPinOutSel
//! parameter.
//
//*****************************************************************************
typedef enum
{
EPG_OUT_SEL_SIG = 0x0U, //!< Signal Generator mux output
EPG_OUT_SEL_CLK = 0x1U //!< Clock Generator mux output
} EPG_OutputSelect;
//*****************************************************************************
//
//! Values that can be passed to EPG_selectSignalOutput() as the
//! \e sigGenOutput parameter.
//
//*****************************************************************************
typedef enum
{
EPG_SIGGEN0_DATATRANOUT0 = 0x0U, //!< Signal Generator 0 Data Transform out 0
EPG_SIGGEN0_DATATRANOUT1 = 0x1U, //!< Signal Generator 0 Data Transform out 1
EPG_SIGGEN0_DATATRANOUT2 = 0x2U, //!< Signal Generator 0 Data Transform out 2
EPG_SIGGEN0_DATATRANOUT3 = 0x3U, //!< Signal Generator 0 Data Transform out 3
EPG_SIGGEN0_DATATRANOUT4 = 0x4U, //!< Signal Generator 0 Data Transform out 4
EPG_SIGGEN0_DATATRANOUT5 = 0x5U, //!< Signal Generator 0 Data Transform out 5
EPG_SIGGEN0_DATATRANOUT6 = 0x6U, //!< Signal Generator 0 Data Transform out 6
EPG_SIGGEN0_DATATRANOUT7 = 0x7U, //!< Signal Generator 0 Data Transform out 7
} EPG_SignalGenOut;
//*****************************************************************************
//
//! Values that can be passed to EPG_selectClkOutput()
//! as the \e clkGenOutput parameter.
//
//*****************************************************************************
typedef enum
{
EPG_CLKGEN0_CLKOUT0_DCLK = 0x0U, //!< Clock Generator 0 Clk output 0 DCLK
EPG_CLKGEN0_CLKOUT1_DCLK = 0x1U, //!< Clock Generator 0 Clk output 1 DCLK
EPG_CLKGEN0_CLKOUT2_DCLK = 0x2U, //!< Clock Generator 0 Clk output 2 DCLK
EPG_CLKGEN0_CLKOUT3_DCLK = 0x3U, //!< Clock Generator 0 Clk output 3 DCLK
EPG_CLKGEN1_CLKOUT0_DCLK = 0x4U, //!< Clock Generator 1 Clk output 0 DCLK
EPG_CLKGEN1_CLKOUT1_DCLK = 0x5U, //!< Clock Generator 1 Clk output 1 DCLK
EPG_CLKGEN1_CLKOUT2_DCLK = 0x6U, //!< Clock Generator 1 Clk output 2 DCLK
EPG_CLKGEN1_CLKOUT3_DCLK = 0x7U, //!< Clock Generator 1 Clk output 3 DCLK
} EPG_ClockGenOut;
//*****************************************************************************
//
//! Values that can be passed to EPG_selectSigGenClkSource()
//! as the \e clkGenOutput parameter.
//
//*****************************************************************************
typedef enum
{
EPG_CLKGEN0_CLKOUT0_GCLK = 0x0U, //!< Clock Generator 0 Clk output 0 GCLK
EPG_CLKGEN0_CLKOUT1_GCLK = 0x1U, //!< Clock Generator 0 Clk output 1 GCLK
EPG_CLKGEN0_CLKOUT2_GCLK = 0x2U, //!< Clock Generator 0 Clk output 2 GCLK
EPG_CLKGEN0_CLKOUT3_GCLK = 0x3U, //!< Clock Generator 0 Clk output 3 GCLK
EPG_CLKGEN1_CLKOUT0_GCLK = 0x4U, //!< Clock Generator 1 Clk output 0 GCLK
EPG_CLKGEN1_CLKOUT1_GCLK = 0x5U, //!< Clock Generator 1 Clk output 1 GCLK
EPG_CLKGEN1_CLKOUT2_GCLK = 0x6U, //!< Clock Generator 1 Clk output 2 GCLK
EPG_CLKGEN1_CLKOUT3_GCLK = 0x7U, //!< Clock Generator 1 Clk output 3 GCLK
} EPG_ClockGenGclkOut;
//*****************************************************************************
//
//! Values that can be passed to EPG_setClkGenStopEdge(),
//! as the \e stopEdge parameter.
//
//*****************************************************************************
typedef enum
{
EPG_CLK_STOP_EDGE_CLKOUT0 = 0x000U, //!< Stop on Clk output 0
EPG_CLK_STOP_EDGE_CLKOUT1 = 0x010U, //!< Stop on Clk output 1
EPG_CLK_STOP_EDGE_CLKOUT2 = 0x100U, //!< Stop on Clk output 2
EPG_CLK_STOP_EDGE_CLKOUT3 = 0x110U, //!< Stop on Clk output 3
} EPG_ClockStopEdge;
//*****************************************************************************
//
//! Values that can be passed to EPG_setSignalGenMode(),
//! as the \e sigGenMode parameter.
//
//*****************************************************************************
typedef enum
{
EPG_SIGGEN_MODE_BIT_BANG = 0x0U, //!< BIT BANG MODE
EPG_SIGGEN_MODE_SHIFT_RIGHT_ONCE = 0x1U, //!< SHIFT RIGHT ONCE MODE
EPG_SIGGEN_MODE_ROTATE_RIGHT_ONCE = 0x2U, //!< ROTATE RIGHT ONCE MODE
EPG_SIGGEN_MODE_ROTATE_RIGHT_REPEAT = 0x3U, //!< ROTATE RIGHT REPEAT MODE
EPG_SIGGEN_MODE_SHIFT_LEFT_ONCE = 0x4U, //!< SHIFT LEFT ONCE MODE
EPG_SIGGEN_MODE_ROTATE_LEFT_ONCE = 0x5U, //!< ROTATE LEFT ONCE MODE
EPG_SIGGEN_MODE_ROTATE_LEFT_REPEAT = 0x6U, //!< ROTATE LEFT REPEAT
EPG_SIGGEN_MODE_SHIFT_RIGHT_REPEAT = 0x7U, //!< SHIFT RIGHT REPEAT MODE
EPG_SIGGEN_MODE_SHIFT_LEFT_REPEAT = 0x8U, //!< SHIGT LEFT REPEAT MODE
} EPG_SignalGenMode;
//*****************************************************************************
//
//! Values that can be passed to EPG_setData0In(),
//! as the \e data0Input parameter.
//
//*****************************************************************************
typedef enum
{
EPG_SIGGEN_DATA0_DATA_NEXT0 = 0x0U, //!< DATA TRANSFORM NEXT[0]
EPG_SIGGEN_DATA0_EPGIN0 = 0x1U, //!< EPG Input 0
EPG_SIGGEN_DATA0_EPGIN1 = 0x2U, //!< EPG Input 1
EPG_SIGGEN_DATA0_EPGIN2 = 0x3U, //!< EPG Input 2
EPG_SIGGEN_DATA0_EPGIN3 = 0x4U, //!< EPG Input 3
EPG_SIGGEN_DATA0_EPGIN4 = 0x5U, //!< EPG Input 4
EPG_SIGGEN_DATA0_EPGIN5 = 0x6U, //!< EPG Input 5
EPG_SIGGEN_DATA0_EPGIN6 = 0x7U, //!< EPG Input 6
EPG_SIGGEN_DATA0_EPGIN7 = 0x8U, //!< EPG Input 7
} EPG_SignalGenData0In;
//*****************************************************************************
//
//! Values that can be passed to EPG_setData63In(),
//! as the \e data63Input parameter.
//
//*****************************************************************************
typedef enum
{
EPG_SIGGEN_DATA63_DATA_NEXT63 = 0x0U, //!< DATA TRANSFORM NEXT[63]
EPG_SIGGEN_DATA63_EPGIN0 = 0x1U, //!< EPG Input 0
EPG_SIGGEN_DATA63_EPGIN1 = 0x2U, //!< EPG Input 1
EPG_SIGGEN_DATA63_EPGIN2 = 0x3U, //!< EPG Input 2
EPG_SIGGEN_DATA63_EPGIN3 = 0x4U, //!< EPG Input 3
EPG_SIGGEN_DATA63_EPGIN4 = 0x5U, //!< EPG Input 4
EPG_SIGGEN_DATA63_EPGIN5 = 0x6U, //!< EPG Input 5
EPG_SIGGEN_DATA63_EPGIN6 = 0x7U, //!< EPG Input 6
EPG_SIGGEN_DATA63_EPGIN7 = 0x8U, //!< EPG Input 7
} EPG_SignalGenData63In;
//*****************************************************************************
//
//! Values that can be passed to EPG_selectEPGOutput(), EPG_selectClkOutput,
//! EPG_selectSignalOutput as the \e gPinNum parameter.
//
//*****************************************************************************
typedef enum
{
EPG_OUT0 = 0x0U, //!< EPG Output 0
EPG_OUT1 = 0x1U, //!< EPG Output 1
EPG_OUT2 = 0x2U, //!< EPG Output 2
EPG_OUT3 = 0x3U, //!< EPG Output 3
EPG_OUT4 = 0x4U, //!< EPG Output 4
EPG_OUT5 = 0x5U, //!< EPG Output 5
EPG_OUT6 = 0x6U, //!< EPG Output 6
} EPG_OUT;
//*****************************************************************************
//
//! Values that can be used for \e sigGenNum parameter.
//
//*****************************************************************************
typedef enum
{
EPG_SIGGEN0 = 0x0U, //!< Signal Generator 0
} EPG_SIGGEN;
//*****************************************************************************
//
//! Values that can be used for \e clkGenNum parameter.
//
//*****************************************************************************
typedef enum
{
EPG_CLKGEN0 = 0x0U, //!< Clock Generator 0
EPG_CLKGEN1 = 0x1U, //> 2U) << syncModeOffset) |
(((uint16_t)loadMode & 0x3U) << loadModeOffset)));
}
//*****************************************************************************
//
//! Disable Counter Compare shadow load mode
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the counter compare module.
//!
//! This function disables counter compare shadow load mode.
//! Valid values for the variables are:
//! - compModule
//! - EPWM_COUNTER_COMPARE_A - counter compare A.
//! - EPWM_COUNTER_COMPARE_B - counter compare B.
//! - EPWM_COUNTER_COMPARE_C - counter compare C.
//! - EPWM_COUNTER_COMPARE_D - counter compare D.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableCounterCompareShadowLoadMode(uint32_t base,
EPWM_CounterCompareModule compModule)
{
uint16_t shadowModeOffset;
uint32_t registerOffset;
//
// Check the arguments
//
;
if((compModule == EPWM_COUNTER_COMPARE_A) ||
(compModule == EPWM_COUNTER_COMPARE_C))
{
shadowModeOffset = 4U;
}
else
{
shadowModeOffset = 6U;
}
//
// Get the register offset. EPWM_O_CMPCTL for A&B or
// EPWM_O_CMPCTL2 for C&D
//
registerOffset = base + 0x8U + ((uint32_t)compModule & 0x1U);
//
// Disable shadow load mode.
//
(*((volatile uint16_t *)(registerOffset))) = ((*((volatile uint16_t *)(registerOffset))) |
(0x1U << shadowModeOffset));
}
//*****************************************************************************
//
//! Set counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare value module.
//! \param compCount is the counter compare count value.
//!
//! This function sets the counter compare value for counter compare registers.
//! The maximum value for compCount is 0xFFFF.
//! Valid values for compModule are:
//! - EPWM_COUNTER_COMPARE_A - counter compare A.
//! - EPWM_COUNTER_COMPARE_B - counter compare B.
//! - EPWM_COUNTER_COMPARE_C - counter compare C.
//! - EPWM_COUNTER_COMPARE_D - counter compare D.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule,
uint16_t compCount)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
//
// Get the register offset for the Counter compare
//
registerOffset = 0x6AU + (uint32_t)compModule;
//
// Write to the counter compare registers.
//
if((compModule == EPWM_COUNTER_COMPARE_A) ||
(compModule == EPWM_COUNTER_COMPARE_B))
{
//
// Write to COMPA or COMPB bits
//
(*((volatile uint16_t *)(base + registerOffset + 0x1U))) = compCount;
}
else
{
//
// Write to COMPC or COMPD bits
//
(*((volatile uint16_t *)(base + registerOffset))) = compCount;
}
}
//*****************************************************************************
//
//! Get counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare value module.
//!
//! This function gets the counter compare value for counter compare registers.
//! Valid values for compModule are:
//! - EPWM_COUNTER_COMPARE_A - counter compare A.
//! - EPWM_COUNTER_COMPARE_B - counter compare B.
//! - EPWM_COUNTER_COMPARE_C - counter compare C.
//! - EPWM_COUNTER_COMPARE_D - counter compare D.
//!
//! \return The counter compare count value.
//
//*****************************************************************************
static inline uint16_t
EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
{
uint32_t registerOffset;
uint16_t compCount;
//
// Check the arguments
//
;
//
// Get the register offset for the Counter compare
//
registerOffset = 0x6AU + (uint32_t)compModule;
//
// Read from the counter compare registers.
//
if((compModule == EPWM_COUNTER_COMPARE_A) ||
(compModule == EPWM_COUNTER_COMPARE_B))
{
//
// Read COMPA or COMPB bits
//
compCount = (uint16_t)(((*((volatile uint32_t *)(base + registerOffset))) &
0xFFFF0000UL) >> 16U);
}
else
{
//
// Read COMPC or COMPD bits
//
compCount = (*((volatile uint16_t *)(base + registerOffset)));
}
return(compCount);
}
//*****************************************************************************
//
//! Return the counter compare shadow register full status.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare value module.
//!
//! This function returns the counter Compare shadow register full status flag.
//! Valid values for compModule are:
//! - EPWM_COUNTER_COMPARE_A - counter compare A.
//! - EPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \return Returns true if the shadow register is full.
//! Returns false if the shadow register is not full.
//
//*****************************************************************************
static inline _Bool
EPWM_getCounterCompareShadowStatus(uint32_t base,
EPWM_CounterCompareModule compModule)
{
//
// Check the arguments
//
;
//
// Check the validity of input.
// COMPA and COMPB are valid input arguments.
//
;
//
// Read the value of SHDWAFULL or SHDWBFULL bit
//
return(((((*((volatile uint32_t *)(base + 0x8U))) >>
((((uint16_t)compModule >> 1U) & 0x1U) + 8U)) &
0x1U) == 0x1U) ? 1:0);
}
//
// Action Qualifier module related APIs
//
//*****************************************************************************
//
//! Sets the Action Qualifier shadow load mode
//!
//! \param base is the base address of the EPWM module.
//! \param aqModule is the Action Qualifier module value.
//! \param loadMode is the shadow to active load mode.
//!
//! This function enables and sets the Action Qualifier shadow load mode.
//! Valid values for the variables are:
//! - aqModule
//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A.
//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B.
//! - loadMode
//! - EPWM_AQ_LOAD_ON_CNTR_ZERO - load when counter equals zero
//! - EPWM_AQ_LOAD_ON_CNTR_PERIOD - load when counter equals period
//! - EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals
//! zero or period
//! - EPWM_AQ_LOAD_FREEZE - Freeze shadow to active load
//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO - load on sync or when counter
//! equals zero
//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD - load on sync or when counter
//! equals period
//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load on sync or when
//! counter equals zero or period
//! - EPWM_AQ_LOAD_ON_SYNC_ONLY - load on sync only
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierShadowLoadMode(uint32_t base,
EPWM_ActionQualifierModule aqModule,
EPWM_ActionQualifierLoadMode loadMode)
{
uint16_t syncModeOffset;
uint16_t shadowModeOffset;
//
// Check the arguments
//
;
syncModeOffset = 8U + (uint16_t)aqModule;
shadowModeOffset = 4U + (uint16_t)aqModule;
//
// Set the appropriate sync and load mode bits and also enable shadow
// load mode. Shadow to active load can also be frozen.
//
(*((volatile uint16_t *)(base + 0x10U))) = (((*((volatile uint16_t *)(base + 0x10U))) &
(~((0x3U << (uint16_t)aqModule) |
(0x3U << (uint16_t)syncModeOffset))) |
(0x1U << shadowModeOffset)) |
((((uint16_t)loadMode >> 2U) <<
syncModeOffset) | (((uint16_t)loadMode &
0x3U) << (uint16_t)aqModule)));
}
//*****************************************************************************
//
//! Disable Action Qualifier shadow load mode
//!
//! \param base is the base address of the EPWM module.
//! \param aqModule is the Action Qualifier module value.
//!
//! This function disables the Action Qualifier shadow load mode.
//! Valid values for the variables are:
//! - aqModule
//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A.
//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableActionQualifierShadowLoadMode(uint32_t base,
EPWM_ActionQualifierModule aqModule)
{
uint16_t shadowModeOffset;
//
// Check the arguments
//
;
shadowModeOffset = 4U + (uint16_t)aqModule;
//
// Disable shadow load mode. Action qualifier is loaded on
// immediate mode only.
//
(*((volatile uint16_t *)(base + 0x10U))) &= ~(1U << shadowModeOffset);
}
//*****************************************************************************
//
//! Set up Action qualifier trigger source for event T1
//!
//! \param base is the base address of the EPWM module.
//! \param trigger sources for Action Qualifier triggers.
//!
//! This function sets up the sources for Action Qualifier event T1.
//! Valid values for trigger are:
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT - Digital compare filter event
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierT1TriggerSource(uint32_t base,
EPWM_ActionQualifierTriggerSource trigger)
{
//
// Check the arguments
//
;
//
// Set T1 trigger source
//
(*((volatile uint16_t *)(base + 0x11U))) =
(((*((volatile uint16_t *)(base + 0x11U))) & (~0xFU)) |
((uint16_t)trigger));
}
//*****************************************************************************
//
//! Set up Action qualifier trigger source for event T2
//!
//! \param base is the base address of the EPWM module.
//! \param trigger sources for Action Qualifier triggers.
//!
//! This function sets up the sources for Action Qualifier event T2.
//! Valid values for trigger are:
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync
//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT - Digital compare filter event
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierT2TriggerSource(uint32_t base,
EPWM_ActionQualifierTriggerSource trigger)
{
//
// Check the arguments
//
;
//
// Set T2 trigger source
//
(*((volatile uint16_t *)(base + 0x11U))) =
(((*((volatile uint16_t *)(base + 0x11U))) & (~0xF0U)) |
((uint16_t)trigger << 4U));
}
//*****************************************************************************
//
//! Set up Action qualifier outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param output is the Action Qualifier output.
//! \param event is the event that causes a change in output.
//!
//! This function sets up the Action Qualifier output on ePWM A or ePWMB,
//! depending on the value of epwmOutput, to a value specified by outPut based
//! on the input events - specified by event.
//! The following are valid values for the parameters.
//! - epwmOutput
//! - EPWM_AQ_OUTPUT_A - ePWMxA output
//! - EPWM_AQ_OUTPUT_B - ePWMxB output
//! - output
//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins
//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High
//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins
//! - event
//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO - Time base counter equals
//! zero
//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD - Time base counter equals
//! period
//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA - Time base counter up equals
//! COMPA
//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA - Time base counter down
//! equals COMPA
//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB - Time base counter up equals
//! COMPB
//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB - Time base counter down
//! equals COMPB
//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_UP - T1 event on count up
//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN - T1 event on count down
//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_UP - T2 event on count up
//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN - T2 event on count down
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierAction(uint32_t base,
EPWM_ActionQualifierOutputModule epwmOutput,
EPWM_ActionQualifierOutput output,
EPWM_ActionQualifierOutputEvent event)
{
uint32_t registerOffset;
uint32_t registerTOffset;
//
// Check the arguments
//
;
//
// Get the register offset
//
registerOffset = 0x40U + (uint32_t)epwmOutput;
registerTOffset = 0x41U + (uint32_t)epwmOutput;
//
// If the event occurs on T1 or T2 events
//
if(((uint16_t)event & 0x1U) == 1U)
{
//
// Write to T1U,T1D,T2U or T2D of AQCTLA2 register
//
(*((volatile uint16_t *)(base + registerTOffset))) =
(((*((volatile uint16_t *)(base + registerTOffset))) & ~(3U << ((uint16_t)event - 1U))) |
((uint16_t)output << ((uint16_t)event - 1U)));
}
else
{
//
// Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register
//
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~(3U << (uint16_t)event)) |
((uint16_t)output << (uint16_t)event));
}
}
//*****************************************************************************
//
//! Set up Action qualifier event outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param action is the desired action when the specified event occurs
//!
//! This function sets up the Action Qualifier output on ePWMA or ePWMB,
//! depending on the value of epwmOutput, to a value specified by action.
//! Valid action param values from different time base counter scenarios
//! should be OR'd together to configure complete action for a pwm output.
//! The following are valid values for the parameters.
//! - epwmOutput
//! - EPWM_AQ_OUTPUT_A - ePWMxA output
//! - EPWM_AQ_OUTPUT_B - ePWMxB output
//!
//! - action
//! - When time base counter equals zero
//! - EPWM_AQ_OUTPUT_NO_CHANGE_ZERO - Time base counter equals zero
//! and no change in output pins
//! - EPWM_AQ_OUTPUT_LOW_ZERO - Time base counter equals zero
//! and set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH_ZERO - Time base counter equals zero
//! and set output pins to high
//! - EPWM_AQ_OUTPUT_TOGGLE_ZERO - Time base counter equals zero
//! and toggle the output pins
//! - When time base counter equals period
//! - EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD - Time base counter equals period
//! and no change in output pins
//! - EPWM_AQ_OUTPUT_LOW_PERIOD - Time base counter equals period
//! and set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH_PERIOD - Time base counter equals period
//! and set output pins to high
//! - EPWM_AQ_OUTPUT_TOGGLE_PERIOD - Time base counter equals period
//! and toggle the output pins
//! - When time base counter equals CMPA during up-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA - Time base counter up equals
//! COMPA and no change in the
//! output pins
//! - EPWM_AQ_OUTPUT_LOW_UP_CMPA - Time base counter up equals
//! COMPA and set output pins low
//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPA - Time base counter up equals
//! COMPA and set output pins high
//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA - Time base counter up equals
//! COMPA and toggle output pins
//! - When time base counter equals CMPA during down-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA - Time base counter down equals
//! COMPA and no change in the
//! output pins
//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPA - Time base counter down equals
//! COMPA and set output pins low
//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA - Time base counter down equals
//! COMPA and set output pins high
//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA - Time base counter down equals
//! COMPA and toggle output pins
//! - When time base counter equals CMPB during up-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB - Time base counter up equals
//! COMPB and no change in the
//! output pins
//! - EPWM_AQ_OUTPUT_LOW_UP_CMPB - Time base counter up equals
//! COMPB and set output pins low
//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPB - Time base counter up equals
//! COMPB and set output pins high
//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB - Time base counter up equals
//! COMPB and toggle output pins
//! - When time base counter equals CMPB during down-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB- Time base counter down equals
//! COMPB and no change in the
//! output pins
//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPB - Time base counter down equals
//! COMPB and set output pins low
//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB - Time base counter down equals
//! COMPB and set output pins high
//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB - Time base counter down equals
//! COMPB and toggle output pins
//!
//! \b note: A logical OR of the valid values should be passed as the action
//! parameter. Single action should be configured for each time base
//! counter scenario.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierActionComplete(uint32_t base,
EPWM_ActionQualifierOutputModule epwmOutput,
uint16_t action)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
//
// Get the register offset
//
registerOffset = 0x40U + (uint32_t)epwmOutput;
//
// Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register
//
(*((volatile uint16_t *)(base + registerOffset))) = (uint16_t)action;
}
//*****************************************************************************
//
//! Set up Additional action qualifier event outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param action is the desired action when the specified event occurs
//!
//! This function sets up the Additional Action Qualifier output on ePWMA or
//! ePWMB depending on the value of epwmOutput, to a value specified by action.
//! Valid action param values from different event scenarios should be OR'd
//! together to configure complete action for a pwm output.
//! The following are valid values for the parameters.
//! - epwmOutput
//! - EPWM_AQ_OUTPUT_A - ePWMxA output
//! - EPWM_AQ_OUTPUT_B - ePWMxB output
//! - action
//! - When T1 event occurs during up-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 - T1 event on count up
//! and no change in output pins
//! - EPWM_AQ_OUTPUT_LOW_UP_T1 - T1 event on count up
//! and set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH_UP_T1 - T1 event on count up
//! and set output pins to high
//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T1 - T1 event on count up
//! and toggle the output pins
//! - When T1 event occurs during down-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1- T1 event on count down
//! and no change in output pins
//! - EPWM_AQ_OUTPUT_LOW_DOWN_T1 - T1 event on count down
//! and set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T1 - T1 event on count down
//! and set output pins to high
//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 - T1 event on count down
//! and toggle the output pins
//! - When T2 event occurs during up-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 - T2 event on count up
//! and no change in output pins
//! - EPWM_AQ_OUTPUT_LOW_UP_T2 - T2 event on count up
//! and set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH_UP_T2 - T2 event on count up
//! and set output pins to high
//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T2 - T2 event on count up
//! and toggle the output pins
//! - When T2 event occurs during down-count
//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 - T2 event on count down
//! and no change in output pins
//! - EPWM_AQ_OUTPUT_LOW_DOWN_T2 - T2 event on count down
//! and set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T2 - T2 event on count down
//! and set output pins to high
//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 - T2 event on count down
//! and toggle the output pins
//!
//! \b note: A logical OR of the valid values should be passed as the action
//! parameter. Single action should be configured for each event
//! scenario.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setAdditionalActionQualifierActionComplete(uint32_t base,
EPWM_ActionQualifierOutputModule epwmOutput,
uint16_t action)
{
uint32_t registerTOffset;
//
// Check the arguments
//
;
//
// Get the register offset
//
registerTOffset = 0x41U + (uint32_t)epwmOutput;
//
// Write to T1U, T1D, T2U or T2D of AQCTLA2 register
//
(*((volatile uint16_t *)(base + registerTOffset))) = (uint16_t)action;
}
//*****************************************************************************
//
//! Sets up Action qualifier continuous software load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param mode is the mode for shadow to active load mode.
//!
//! This function sets up the AQCFRSC register load mode for continuous
//! software force reload mode. The software force actions are determined by
//! the EPWM_setActionQualifierContSWForceAction() function.
//! Valid values for mode are:
//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO - shadow mode load when counter
//! equals zero
//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD - shadow mode load when counter
//! equals period
//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter
//! equals zero or period
//! - EPWM_AQ_SW_IMMEDIATE_LOAD - immediate mode load only
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierContSWForceShadowMode(uint32_t base,
EPWM_ActionQualifierContForce mode)
{
//
// Check the arguments
//
;
//
// Set the Action qualifier software action reload mode.
// Write to RLDCSF bit
//
(*((volatile uint16_t *)(base + 0x47U))) =
(((*((volatile uint16_t *)(base + 0x47U))) & ~0xC0U) |
((uint16_t)mode << 6U));
}
//*****************************************************************************
//
//! Triggers a continuous software forced event.
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param output is the Action Qualifier output.
//!
//! This function triggers a continuous software forced Action Qualifier output
//! on ePWM A or B based on the value of epwmOutput.
//! Valid values for the parameters are:
//! - epwmOutput
//! - EPWM_AQ_OUTPUT_A - ePWMxA output
//! - EPWM_AQ_OUTPUT_B - ePWMxB output
//! - output
//! - EPWM_AQ_SW_DISABLED - Software forcing disabled.
//! - EPWM_AQ_SW_OUTPUT_LOW - Set output pins to low
//! - EPWM_AQ_SW_OUTPUT_HIGH - Set output pins to High
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierContSWForceAction(uint32_t base,
EPWM_ActionQualifierOutputModule epwmOutput,
EPWM_ActionQualifierSWOutput output)
{
//
// Check the arguments
//
;
//
// Initiate a continuous software forced output
//
if(epwmOutput == EPWM_AQ_OUTPUT_A)
{
(*((volatile uint16_t *)(base + 0x49U))) =
(((*((volatile uint16_t *)(base + 0x49U))) & ~0x3U) |
((uint16_t)output));
}
else
{
(*((volatile uint16_t *)(base + 0x49U))) =
(((*((volatile uint16_t *)(base + 0x49U))) & ~0xCU) |
((uint16_t)output << 2U)) ;
}
}
//*****************************************************************************
//
//! Set up one time software forced Action qualifier outputs
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//! \param output is the Action Qualifier output.
//!
//! This function sets up the one time software forced Action Qualifier output
//! on ePWM A or ePWMB, depending on the value of epwmOutput to a value
//! specified by outPut.
//! The following are valid values for the parameters.
//! - epwmOutput
//! - EPWM_AQ_OUTPUT_A - ePWMxA output
//! - EPWM_AQ_OUTPUT_B - ePWMxB output
//! - output
//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins
//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low
//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High
//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setActionQualifierSWAction(uint32_t base,
EPWM_ActionQualifierOutputModule epwmOutput,
EPWM_ActionQualifierOutput output)
{
//
// Check the arguments
//
;
//
// Set the one time software forced action
//
if(epwmOutput == EPWM_AQ_OUTPUT_A)
{
(*((volatile uint16_t *)(base + 0x47U))) =
(((*((volatile uint16_t *)(base + 0x47U))) & ~0x3U) |
((uint16_t)output));
}
else
{
(*((volatile uint16_t *)(base + 0x47U))) =
(((*((volatile uint16_t *)(base + 0x47U))) & ~0x18U) |
((uint16_t)output << 3U));
}
}
//*****************************************************************************
//
//! Triggers a one time software forced event on Action qualifier
//!
//! \param base is the base address of the EPWM module.
//! \param epwmOutput is the ePWM pin type.
//!
//! This function triggers a one time software forced Action Qualifier event
//! on ePWM A or B based on the value of epwmOutput.
//! Valid values for epwmOutput are:
//! - EPWM_AQ_OUTPUT_A - ePWMxA output
//! - EPWM_AQ_OUTPUT_B - ePWMxB output
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceActionQualifierSWAction(uint32_t base,
EPWM_ActionQualifierOutputModule epwmOutput)
{
//
// Check the arguments
//
;
//
// Initiate a software forced event
//
if(epwmOutput == EPWM_AQ_OUTPUT_A)
{
(*((volatile uint16_t *)(base + 0x47U))) |= 0x4U;
}
else
{
(*((volatile uint16_t *)(base + 0x47U))) |= 0x20U;
}
}
//
// Dead Band Module related APIs
//
//*****************************************************************************
//
//! Sets Dead Band signal output swap mode.
//!
//! \param base is the base address of the EPWM module.
//! \param output is the ePWM Dead Band output.
//! \param enableSwapMode is the output swap mode.
//!
//! This function sets up the output signal swap mode. For example if the
//! output variable is set to EPWM_DB_OUTPUT_A and enableSwapMode is true, then
//! the ePWM A output gets its signal from the ePWM B signal path. Valid values
//! for the input variables are:
//! - output
//! - EPWM_DB_OUTPUT_A - ePWM output A
//! - EPWM_DB_OUTPUT_B - ePWM output B
//! - enableSwapMode
//! - true - the output is swapped
//! - false - the output and the signal path are the same.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output,
_Bool enableSwapMode)
{
uint16_t mask;
//
// Check the arguments
//
;
mask = (uint16_t)1U << ((uint16_t)output + 12U);
if(enableSwapMode)
{
//
// Set the appropriate outswap bit to swap output
//
(*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) | mask);
}
else
{
//
// Clear the appropriate outswap bit to disable output swap
//
(*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) & ~mask);
}
}
//*****************************************************************************
//
//! Sets Dead Band signal output mode.
//!
//! \param base is the base address of the EPWM module.
//! \param delayMode is the Dead Band delay type.
//! \param enableDelayMode is the dead band delay mode.
//!
//! This function sets up the dead band delay mode. The delayMode variable
//! determines if the applied delay is Rising Edge or Falling Edge. The
//! enableDelayMode determines if a dead band delay should be applied.
//! Valid values for the variables are:
//! - delayMode
//! - EPWM_DB_RED - Rising Edge delay
//! - EPWM_DB_FED - Falling Edge delay
//! - enableDelayMode
//! - true - Falling edge or Rising edge delay is applied.
//! - false - Dead Band delay is bypassed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode,
_Bool enableDelayMode)
{
uint16_t mask;
//
// Check the arguments
//
;
mask = (uint16_t)1U << ((uint16_t)delayMode + 0U);
if(enableDelayMode)
{
//
// Set the appropriate outmode bit to enable Dead Band delay
//
(*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) | mask);
}
else
{
//
// Clear the appropriate outswap bit to disable output swap
//
(*((volatile uint16_t *)(base + 0xCU))) = ((*((volatile uint16_t *)(base + 0xCU))) & ~ mask);
}
}
//*****************************************************************************
//
//! Sets Dead Band delay polarity.
//!
//! \param base is the base address of the EPWM module.
//! \param delayMode is the Dead Band delay type.
//! \param polarity is the polarity of the delayed signal.
//!
//! This function sets up the polarity as determined by the variable polarity
//! of the Falling Edge or Rising Edge delay depending on the value of
//! delayMode. Valid values for the variables are:
//! - delayMode
//! - EPWM_DB_RED - Rising Edge delay
//! - EPWM_DB_FED - Falling Edge delay
//! - polarity
//! - EPWM_DB_POLARITY_ACTIVE_HIGH - polarity is not inverted.
//! - EPWM_DB_POLARITY_ACTIVE_LOW - polarity is inverted.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandDelayPolarity(uint32_t base,
EPWM_DeadBandDelayMode delayMode,
EPWM_DeadBandPolarity polarity)
{
uint16_t shift;
//
// Check the arguments
//
;
shift = (((uint16_t)delayMode ^ 0x1U) + 2U);
//
// Set the appropriate polsel bits for dead band polarity
//
(*((volatile uint16_t *)(base + 0xCU))) =
(((*((volatile uint16_t *)(base + 0xCU))) & ~ (1U << shift)) |
((uint16_t)polarity << shift));
}
//*****************************************************************************
//
//! Sets Rising Edge Dead Band delay input.
//!
//! \param base is the base address of the EPWM module.
//! \param input is the input signal to the dead band.
//!
//! This function sets up the rising Edge delay input signal.
//! Valid values for input are:
//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA( Valid for both Falling
//! Edge and Rising Edge)
//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB( Valid for both Falling
//! Edge and Rising Edge)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
{
//
// Check the arguments
//
;
;
//
// Set the Rising Edge Delay input
//
(*((volatile uint16_t *)(base + 0xCU))) =
(((*((volatile uint16_t *)(base + 0xCU))) & ~(1U << (4U))) |
(input << 4U));
}
//*****************************************************************************
//
//! Sets Dead Band delay input.
//!
//! \param base is the base address of the EPWM module.
//! \param input is the input signal to the dead band.
//!
//! This function sets up the rising Edge delay input signal.
//! Valid values for input are:
//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA(Valid for both Falling
//! Edge and Rising Edge)
//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB(Valid for both Falling
//! Edge and Rising Edge)
//! - EPWM_DB_INPUT_DB_RED - Input signal is the output of Rising
//! Edge delay.
//! (Valid only for Falling Edge delay)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
{
//
// Check the arguments
//
;
;
if(input == 2U)
{
//
// Set the Falling Edge Delay input
//
(*((volatile uint16_t *)(base + 0xCU))) |= 0x4000U;
}
else
{
//
// Set the Falling Edge Delay input
//
(*((volatile uint16_t *)(base + 0xCU))) &= ~0x4000U;
//
// Set the Rising Edge Delay input
//
(*((volatile uint16_t *)(base + 0xCU))) =
(((*((volatile uint16_t *)(base + 0xCU))) & ~(1U << (4U + 1U))) |
(input << (4U + 1U)));
}
}
//*****************************************************************************
//
//! Set the Dead Band control shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadMode is the shadow to active load mode.
//!
//! This function enables and sets the Dead Band control register shadow
//! load mode.
//! Valid values for the \e loadMode parameter are:
//! - EPWM_DB_LOAD_ON_CNTR_ZERO - load when counter equals zero.
//! - EPWM_DB_LOAD_ON_CNTR_PERIOD - load when counter equals period.
//! - EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or
//! period.
//! - EPWM_DB_LOAD_FREEZE - Freeze shadow to active load.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandControlShadowLoadMode(uint32_t base,
EPWM_DeadBandControlLoadMode loadMode)
{
//
// Check the arguments
//
;
//
// Enable the shadow mode and setup the load event
//
(*((volatile uint16_t *)(base + 0xDU))) =
(((*((volatile uint16_t *)(base + 0xDU))) & ~0x3U) |
(0x4U | (uint16_t)loadMode));
}
//*****************************************************************************
//
//! Disable Dead Band control shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Dead Band control register shadow
//! load mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable the shadow load mode. Only immediate load mode only.
//
(*((volatile uint16_t *)(base + 0xDU))) =
((*((volatile uint16_t *)(base + 0xDU))) & ~0x4U);
}
//*****************************************************************************
//
//! Set the RED (Rising Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadMode is the shadow to active load event.
//!
//! This function sets the Rising Edge Delay register shadow load mode.
//! Valid values for the \e loadMode parameter are:
//! - EPWM_RED_LOAD_ON_CNTR_ZERO - load when counter equals zero.
//! - EPWM_RED_LOAD_ON_CNTR_PERIOD - load when counter equals period.
//! - EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or
//! period.
//! - EPWM_RED_LOAD_FREEZE - Freeze shadow to active load.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base,
EPWM_RisingEdgeDelayLoadMode loadMode)
{
//
// Check the arguments
//
;
//
// Enable the shadow mode. Set-up the load mode
//
(*((volatile uint16_t *)(base + 0xCU))) =
(((*((volatile uint16_t *)(base + 0xCU))) & ~0xC0U) |
((uint16_t)0x400U |
((uint16_t)loadMode << 6U)));
}
//*****************************************************************************
//
//! Disable the RED (Rising Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Rising Edge Delay register shadow load mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable the shadow mode.
//
(*((volatile uint16_t *)(base + 0xCU))) =
((*((volatile uint16_t *)(base + 0xCU))) & ~0x400U);
}
//*****************************************************************************
//
//! Set the FED (Falling Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadMode is the shadow to active load event.
//!
//! This function enables and sets the Falling Edge Delay register shadow load
//! mode. Valid values for the \e loadMode parameters are:
//! - EPWM_FED_LOAD_ON_CNTR_ZERO - load when counter equals zero.
//! - EPWM_FED_LOAD_ON_CNTR_PERIOD - load when counter equals period.
//! - EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or
//! period.
//! - EPWM_FED_LOAD_FREEZE - Freeze shadow to active load.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base,
EPWM_FallingEdgeDelayLoadMode loadMode)
{
//
// Check the arguments
//
;
//
// Enable the shadow mode. Setup the load mode.
//
(*((volatile uint16_t *)(base + 0xCU))) =
(((*((volatile uint16_t *)(base + 0xCU))) & ~0x300U) |
(0x800U |
((uint16_t)loadMode << 8U)));
}
//*****************************************************************************
//
//! Disables the FED (Falling Edge Delay) shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Falling Edge Delay register shadow load mode.
//! Valid values for the parameters are:
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable the shadow mode.
//
(*((volatile uint16_t *)(base + 0xCU))) =
((*((volatile uint16_t *)(base + 0xCU))) & ~0x800U);
}
//*****************************************************************************
//
//! Sets Dead Band Counter clock rate.
//!
//! \param base is the base address of the EPWM module.
//! \param clockMode is the Dead Band counter clock mode.
//!
//! This function sets up the Dead Band counter clock rate with respect to
//! TBCLK (ePWM time base counter).
//! Valid values for clockMode are:
//! - EPWM_DB_COUNTER_CLOCK_FULL_CYCLE -Dead band counter runs at TBCLK
//! (ePWM Time Base Counter) rate.
//! - EPWM_DB_COUNTER_CLOCK_HALF_CYCLE -Dead band counter runs at 2*TBCLK
//! (twice ePWM Time Base Counter)rate.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDeadBandCounterClock(uint32_t base,
EPWM_DeadBandClockMode clockMode)
{
//
// Check the arguments
//
;
//
// Set the DB clock mode
//
(*((volatile uint16_t *)(base + 0xCU))) =
(((*((volatile uint16_t *)(base + 0xCU))) & ~0x8000U) |
((uint16_t)clockMode << 15U));
}
//*****************************************************************************
//
//! Set ePWM RED count
//!
//! \param base is the base address of the EPWM module.
//! \param redCount is the RED(Rising Edge Delay) count.
//!
//! This function sets the RED (Rising Edge Delay) count value.
//! The value of redCount should be less than 0x4000U.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
{
//
// Check the arguments
//
;
;
//
// Set the RED (Rising Edge Delay) count
//
(*((volatile uint16_t *)(base + 0x51U))) = redCount;
}
//*****************************************************************************
//
//! Set ePWM FED count
//!
//! \param base is the base address of the EPWM module.
//! \param fedCount is the FED(Falling Edge Delay) count.
//!
//! This function sets the FED (Falling Edge Delay) count value.
//! The value of fedCount should be less than 0x4000U.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
{
//
// Check the arguments
//
;
;
//
// Set the RED (Rising Edge Delay) count
//
(*((volatile uint16_t *)(base + 0x53U))) = fedCount;
}
//
// Chopper module related APIs
//
//*****************************************************************************
//
//! Enable chopper mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables ePWM chopper module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableChopper(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set CHPEN bit. Enable Chopper
//
(*((volatile uint16_t *)(base + 0x14U))) |= 0x1U;
}
//*****************************************************************************
//
//! Disable chopper mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables ePWM chopper module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableChopper(uint32_t base)
{
//
// Check the arguments
//
;
//
// Clear CHPEN bit. Disable Chopper
//
(*((volatile uint16_t *)(base + 0x14U))) &= ~0x1U;
}
//*****************************************************************************
//
//! Set chopper duty cycle.
//!
//! \param base is the base address of the EPWM module.
//! \param dutyCycleCount is the chopping clock duty cycle count.
//!
//! This function sets the chopping clock duty cycle. The value of
//! dutyCycleCount should be less than 7. The dutyCycleCount value is converted
//! to the actual chopper duty cycle value base on the following equation:
//! chopper duty cycle = (dutyCycleCount + 1) / 8
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
{
//
// Check the arguments
//
;
;
//
// Set the chopper duty cycle
//
(*((volatile uint16_t *)(base + 0x14U))) =
(((*((volatile uint16_t *)(base + 0x14U))) & ~0x700U) |
(dutyCycleCount << 8U));
}
//*****************************************************************************
//
//! Set chopper clock frequency scaler.
//!
//! \param base is the base address of the EPWM module.
//! \param freqDiv is the chopping clock frequency divider.
//!
//! This function sets the scaler for the chopping clock frequency. The value
//! of freqDiv should be less than 8. The chopping clock frequency is altered
//! based on the following equation.
//! chopper clock frequency = SYSCLKOUT / ( 1 + freqDiv)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
{
//
// Check the arguments
//
;
;
//
// Set the chopper clock
//
(*((volatile uint16_t *)(base + 0x14U))) =
(((*((volatile uint16_t *)(base + 0x14U))) &
~(uint16_t)0xE0U) |
(freqDiv << 5U));
}
//*****************************************************************************
//
//! Set chopper clock frequency scaler.
//!
//! \param base is the base address of the EPWM module.
//! \param firstPulseWidth is the width of the first pulse.
//!
//! This function sets the first pulse width of chopper output waveform. The
//! value of firstPulseWidth should be less than 0x10. The value of the first
//! pulse width in seconds is given using the following equation:
//! first pulse width = 1 / (((firstPulseWidth + 1) * SYSCLKOUT)/8)
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
{
//
// Check the arguments
//
;
;
//
// Set the chopper clock
//
(*((volatile uint16_t *)(base + 0x14U))) =
(((*((volatile uint16_t *)(base + 0x14U))) &
~(uint16_t)0x1EU) |
(firstPulseWidth << 1U));
}
//
// Trip Zone module related APIs
//
//*****************************************************************************
//
//! Enables Trip Zone signal.
//!
//! \param base is the base address of the EPWM module.
//! \param tzSignal is the Trip Zone signal.
//!
//! This function enables the Trip Zone signals specified by tzSignal as a
//! source for the Trip Zone module.
//! Valid values for tzSignal are:
//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1
//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2
//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3
//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4
//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5
//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6
//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1
//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1
//!
//! \b note: A logical OR of the valid values can be passed as the tzSignal
//! parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneSignals(uint32_t base, uint16_t tzSignal)
{
//
// Check the arguments
//
;
//
// Set the trip zone bits
//
__eallow();
(*((volatile uint16_t *)(base + 0x80U))) |= tzSignal;
__edis();
}
//*****************************************************************************
//
//! Disables Trip Zone signal.
//!
//! \param base is the base address of the EPWM module.
//! \param tzSignal is the Trip Zone signal.
//!
//! This function disables the Trip Zone signal specified by tzSignal as a
//! source for the Trip Zone module.
//! Valid values for tzSignal are:
//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle
//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1
//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2
//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3
//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4
//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5
//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6
//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1
//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1
//!
//! \b note: A logical OR of the valid values can be passed as the tzSignal
//! parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableTripZoneSignals(uint32_t base, uint16_t tzSignal)
{
//
// Check the arguments
//
;
//
// Clear the trip zone bits
//
__eallow();
(*((volatile uint16_t *)(base + 0x80U))) &= ~tzSignal;
__edis();
}
//*****************************************************************************
//
//! Set Digital compare conditions that cause Trip Zone event.
//!
//! \param base is the base address of the EPWM module.
//! \param dcType is the Digital compare output type.
//! \param dcEvent is the Digital Compare output event.
//!
//! This function sets up the Digital Compare output Trip Zone event sources.
//! The dcType variable specifies the event source to be whether Digital
//! Compare output A or Digital Compare output B. The dcEvent parameter
//! specifies the event that causes Trip Zone.
//! Valid values for the parameters are:
//! - dcType
//! - EPWM_TZ_DC_OUTPUT_A1 - Digital Compare output 1 A
//! - EPWM_TZ_DC_OUTPUT_A2 - Digital Compare output 2 A
//! - EPWM_TZ_DC_OUTPUT_B1 - Digital Compare output 1 B
//! - EPWM_TZ_DC_OUTPUT_B2 - Digital Compare output 2 B
//! - dcEvent
//! - EPWM_TZ_EVENT_DC_DISABLED - Event Trigger is disabled
//! - EPWM_TZ_EVENT_DCXH_LOW - Trigger event when DCxH low
//! - EPWM_TZ_EVENT_DCXH_HIGH - Trigger event when DCxH high
//! - EPWM_TZ_EVENT_DCXL_LOW - Trigger event when DCxL low
//! - EPWM_TZ_EVENT_DCXL_HIGH - Trigger event when DCxL high
//! - EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW - Trigger event when DCxL high
//! DCxH low
//!
//! \note x in DCxH/DCxL represents DCAH/DCAL or DCBH/DCBL
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base,
EPWM_TripZoneDigitalCompareOutput dcType,
EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
{
//
// Check the arguments
//
;
//
// Set Digital Compare Events conditions that cause a Digital Compare trip
//
__eallow();
(*((volatile uint16_t *)(base + 0x82U))) =
(((*((volatile uint16_t *)(base + 0x82U))) & ~(0x7U << (uint16_t)dcType)) |
((uint16_t)dcEvent << (uint16_t)dcType));
__edis();
}
//*****************************************************************************
//
//! Enable advanced Trip Zone event Action.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the advanced actions of the Trip Zone events. The
//! advanced features combine the trip zone events with the direction of the
//! counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneAdvAction(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable Advanced feature. Set ETZE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U;
__edis();
}
//*****************************************************************************
//
//! Disable advanced Trip Zone event Action.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the advanced actions of the Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableTripZoneAdvAction(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable Advanced feature. clear ETZE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x85U))) &= ~0x8000U;
__edis();
}
//*****************************************************************************
//
//! Set Trip Zone Action.
//!
//! \param base is the base address of the EPWM module.
//! \param tzEvent is the Trip Zone event type.
//! \param tzAction is the Trip zone Action.
//!
//! This function sets the Trip Zone Action to be taken when a Trip Zone event
//! occurs.
//! Valid values for the parameters are:
//! - tzEvent
//! - EPWM_TZ_ACTION_EVENT_DCBEVT2 - DCBEVT2 (Digital Compare B event 2)
//! - EPWM_TZ_ACTION_EVENT_DCBEVT1 - DCBEVT1 (Digital Compare B event 1)
//! - EPWM_TZ_ACTION_EVENT_DCAEVT2 - DCAEVT2 (Digital Compare A event 2)
//! - EPWM_TZ_ACTION_EVENT_DCAEVT1 - DCAEVT1 (Digital Compare A event 1)
//! - EPWM_TZ_ACTION_EVENT_TZB - TZ1 - TZ6, DCBEVT2, DCBEVT1
//! - EPWM_TZ_ACTION_EVENT_TZA - TZ1 - TZ6, DCAEVT2, DCAEVT1
//! - tzAction
//! - EPWM_TZ_ACTION_HIGH_Z - high impedance output
//! - EPWM_TZ_ACTION_HIGH - high output
//! - EPWM_TZ_ACTION_LOW - low low
//! - EPWM_TZ_ACTION_DISABLE - disable action
//!
//! \note Disable the advanced Trip Zone event using
//! EPWM_disableTripZoneAdvAction() before calling this function.
//! \note This function operates on both ePWMA and ePWMB depending on the
//! tzEvent parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent,
EPWM_TripZoneAction tzAction)
{
//
// Check the arguments
//
;
//
// Set the Action for Trip Zone events
//
__eallow();
(*((volatile uint16_t *)(base + 0x84U))) =
(((*((volatile uint16_t *)(base + 0x84U))) & ~(0x3U << (uint16_t)tzEvent)) |
((uint16_t)tzAction << (uint16_t)tzEvent)) ;
__edis();
}
//*****************************************************************************
//
//! Set Advanced Trip Zone Action.
//!
//! \param base is the base address of the EPWM module.
//! \param tzAdvEvent is the Trip Zone event type.
//! \param tzAdvAction is the Trip zone Action.
//!
//! This function sets the Advanced Trip Zone Action to be taken when an
//! advanced Trip Zone event occurs.
//!
//! Valid values for the parameters are:
//! - tzAdvEvent
//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_D - TZ1 - TZ6, DCBEVT2, DCBEVT1 while
//! counting down
//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_U - TZ1 - TZ6, DCBEVT2, DCBEVT1 while
//! counting up
//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_D - TZ1 - TZ6, DCAEVT2, DCAEVT1 while
//! counting down
//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_U - TZ1 - TZ6, DCAEVT2, DCAEVT1 while
//! counting up
//! - tzAdvAction
//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output
//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state
//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state
//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output
//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action
//!
//! \note This function enables the advanced Trip Zone event.
//!
//! \note This function operates on both ePWMA and ePWMB depending on the
//! tzAdvEvent parameter.
//! \note Advanced Trip Zone events take into consideration the direction of
//! the counter in addition to Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent,
EPWM_TripZoneAdvancedAction tzAdvAction)
{
//
// Check the arguments
//
;
//
// Set the Advanced Action for Trip Zone events
//
__eallow();
(*((volatile uint16_t *)(base + 0x85U))) =
(((*((volatile uint16_t *)(base + 0x85U))) & ~(0x7U << (uint16_t)tzAdvEvent)) |
((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent));
(*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U;
__edis();
}
//*****************************************************************************
//
//! Set Advanced Digital Compare Trip Zone Action on ePWMA.
//!
//! \param base is the base address of the EPWM module.
//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type.
//! \param tzAdvDCAction is the Digital Compare Trip zone Action.
//!
//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be
//! taken on ePWMA when an advanced Digital Compare Trip Zone A event occurs.
//! Valid values for the parameters are:
//! - tzAdvDCEvent
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event A2 while
//! counting down
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event A2 while
//! counting up
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event A1 while
//! counting down
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event A1 while
//! counting up
//! - tzAdvDCAction
//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output
//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state
//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state
//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output
//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action
//!
//! \note This function enables the advanced Trip Zone event.
//!
//! \note Advanced Trip Zone events take into consideration the direction of
//! the counter in addition to Digital Compare Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base,
EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
EPWM_TripZoneAdvancedAction tzAdvDCAction)
{
//
// Check the arguments
//
;
//
// Set the Advanced Action for Trip Zone events
//
__eallow();
(*((volatile uint16_t *)(base + 0x86U))) =
(((*((volatile uint16_t *)(base + 0x86U))) & ~(0x7U << (uint16_t)tzAdvDCEvent)) |
((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent));
(*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U;
__edis();
}
//*****************************************************************************
//
//! Set Advanced Digital Compare Trip Zone Action on ePWMB.
//!
//! \param base is the base address of the EPWM module.
//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type.
//! \param tzAdvDCAction is the Digital Compare Trip zone Action.
//!
//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be
//! taken on ePWMB when an advanced Digital Compare Trip Zone B event occurs.
//! Valid values for the parameters are:
//! - tzAdvDCEvent
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event B2 while
//! counting down
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event B2 while
//! counting up
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event B1 while
//! counting down
//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event B1 while
//! counting up
//! - tzAdvDCAction
//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output
//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state
//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state
//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output
//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action
//!
//! \note This function enables the advanced Trip Zone event.
//!
//! \note Advanced Trip Zone events take into consideration the direction of
//! the counter in addition to Digital Compare Trip Zone events.
//!
//! \return None.
//
//*****************************************************************************
static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base,
EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent,
EPWM_TripZoneAdvancedAction tzAdvDCAction)
{
//
// Check the arguments
//
;
//
// Set the Advanced Action for Trip Zone events
//
__eallow();
(*((volatile uint16_t *)(base + 0x87U))) =
(((*((volatile uint16_t *)(base + 0x87U))) & ~(0x7U << (uint16_t)tzAdvDCEvent)) |
((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent));
(*((volatile uint16_t *)(base + 0x85U))) |= 0x8000U;
__edis();
}
//*****************************************************************************
//
//! Enable Trip Zone interrupts.
//!
//! \param base is the base address of the EPWM module.
//! \param tzInterrupt is the Trip Zone interrupt.
//!
//! This function enables the Trip Zone interrupts.
//! Valid values for tzInterrupt are:
//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt
//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt
//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt
//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt
//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt
//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt
//!
//! \b note: A logical OR of the valid values can be passed as the tzInterrupt
//! parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
{
//
// Check the arguments
//
;
;
//
// Enable Trip zone interrupts
//
__eallow();
(*((volatile uint16_t *)(base + 0x8DU))) |= tzInterrupt;
__edis();
}
//*****************************************************************************
//
//! Disable Trip Zone interrupts.
//!
//! \param base is the base address of the EPWM module.
//! \param tzInterrupt is the Trip Zone interrupt.
//!
//! This function disables the Trip Zone interrupts.
//! Valid values for tzInterrupt are:
//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt
//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt
//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt
//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt
//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt
//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt
//!
//! \b note: A logical OR of the valid values can be passed as the tzInterrupt
//! parameter.
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
{
//
// Check the arguments
//
;
;
//
// Disable Trip zone interrupts
//
__eallow();
(*((volatile uint16_t *)(base + 0x8DU))) &= ~tzInterrupt;
__edis();
}
//*****************************************************************************
//
//! Gets the Trip Zone status flag
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the Trip Zone status flag.
//!
//! \return The function returns the following or the bitwise OR value
//! of the following values.
//! - EPWM_TZ_INTERRUPT - Trip Zone interrupt was generated
//! due to the following TZ events.
//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle event status flag
//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot event status flag
//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 status flag
//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 status flag
//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 status flag
//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 status flag
//
//***************************************************************************
static inline uint16_t
EPWM_getTripZoneFlagStatus(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the Trip zone flag status
//
return((*((volatile uint16_t *)(base + 0x93U))) & 0x7FU);
}
//*****************************************************************************
//
//! Gets the Trip Zone Cycle by Cycle flag status
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the specific Cycle by Cycle Trip Zone flag
//! status.
//!
//! \return The function returns the following values.
//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 status flag
//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 status flag
//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 status flag
//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 status flag
//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 status flag
//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 status flag
//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC status flag for Digital compare
//! event A2
//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC status flag for Digital compare
//! event B2
//
//***************************************************************************
static inline uint16_t
EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the Cycle By Cycle Trip zone flag status
//
return((*((volatile uint16_t *)(base + 0x94U))) & 0xFFU);
}
//*****************************************************************************
//
//! Gets the Trip Zone One Shot flag status
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the specific One Shot Trip Zone flag status.
//!
//! \return The function returns the bitwise OR of the following flags.
//! - EPWM_TZ_OST_FLAG_OST1 - OST status flag for OST1
//! - EPWM_TZ_OST_FLAG_OST2 - OST status flag for OST2
//! - EPWM_TZ_OST_FLAG_OST3 - OST status flag for OST3
//! - EPWM_TZ_OST_FLAG_OST4 - OST status flag for OST4
//! - EPWM_TZ_OST_FLAG_OST5 - OST status flag for OST5
//! - EPWM_TZ_OST_FLAG_OST6 - OST status flag for OST6
//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST status flag for Digital
//! compare event A1
//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST status flag for Digital
//! compare event B1
//
//***************************************************************************
static inline uint16_t
EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the One Shot Trip zone flag status
//
return((*((volatile uint16_t *)(base + 0x95U))) & 0xFFU);
}
//*****************************************************************************
//
//! Set the Trip Zone CBC pulse clear event.
//!
//! \param base is the base address of the EPWM module.
//! \param clearEvent is the CBC trip zone clear event.
//!
//! This function set the event which automatically clears the
//! CBC (Cycle by Cycle) latch.
//! Valid values for clearEvent are:
//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO - Clear CBC pulse when counter
//! equals zero
//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD - Clear CBC pulse when counter
//! equals period
//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD - Clear CBC pulse when counter
//! equals zero or period
//!
//! \return None.
//
//**************************************************************************
static inline void
EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base,
EPWM_CycleByCycleTripZoneClearMode clearEvent)
{
//
// Check the arguments
//
;
//
// Set the Cycle by Cycle Trip Latch mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x97U))) =
(((*((volatile uint16_t *)(base + 0x97U))) & ~0xC000U) |
((uint16_t)clearEvent << 14U));
__edis();
}
//*****************************************************************************
//
//! Clear Trip Zone flag
//!
//! \param base is the base address of the EPWM module.
//! \param tzFlags is the Trip Zone flags.
//!
//! This function clears the Trip Zone flags
//! Valid values for tzFlags are:
//! - EPWM_TZ_INTERRUPT - Global Trip Zone interrupt flag
//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle flag
//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot flag
//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 flag
//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 flag
//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 flag
//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 flag
//!
//! \b note: A bitwise OR of the valid values can be passed as the tzFlags
//! parameter.
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
{
//
// Check the arguments
//
;
;
//
// Clear Trip zone event flag
//
__eallow();
(*((volatile uint16_t *)(base + 0x97U))) |= tzFlags;
__edis();
}
//*****************************************************************************
//
//! Clear the Trip Zone Cycle by Cycle flag.
//!
//! \param base is the base address of the EPWM module.
//! \param tzCBCFlags is the CBC flag to be cleared.
//!
//! This function clears the specific Cycle by Cycle Trip Zone flag.
//! The following are valid values for tzCBCFlags.
//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 flag
//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 flag
//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 flag
//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 flag
//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 flag
//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 flag
//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC flag Digital compare
//! event A2
//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC flag Digital compare
//! event B2
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
{
//
// Check the arguments
//
;
;
//
// Clear the Cycle By Cycle Trip zone flag
//
__eallow();
(*((volatile uint16_t *)(base + 0x98U))) |= tzCBCFlags;
__edis();
}
//*****************************************************************************
//
//! Clear the Trip Zone One Shot flag.
//!
//! \param base is the base address of the EPWM module.
//! \param tzOSTFlags is the OST flags to be cleared.
//!
//! This function clears the specific One Shot (OST) Trip Zone flag.
//! The following are valid values for tzOSTFlags.
//! - EPWM_TZ_OST_FLAG_OST1 - OST flag for OST1
//! - EPWM_TZ_OST_FLAG_OST2 - OST flag for OST2
//! - EPWM_TZ_OST_FLAG_OST3 - OST flag for OST3
//! - EPWM_TZ_OST_FLAG_OST4 - OST flag for OST4
//! - EPWM_TZ_OST_FLAG_OST5 - OST flag for OST5
//! - EPWM_TZ_OST_FLAG_OST6 - OST flag for OST6
//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST flag for Digital compare event A1
//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST flag for Digital compare event B1
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
{
//
// Check the arguments
//
;
;
//
// Clear the Cycle By Cycle Trip zone flag
//
__eallow();
(*((volatile uint16_t *)(base + 0x99U))) |= tzOSTFlags;
__edis();
}
//*****************************************************************************
//
//! Force Trip Zone events.
//!
//! \param base is the base address of the EPWM module.
//! \param tzForceEvent is the forced Trip Zone event.
//!
//! This function forces a Trip Zone event.
//! Valid values for tzForceEvent are:
//! - EPWM_TZ_FORCE_EVENT_CBC - Force Trip Zones Cycle By Cycle event
//! - EPWM_TZ_FORCE_EVENT_OST - Force Trip Zones One Shot Event
//! - EPWM_TZ_FORCE_EVENT_DCAEVT1 - Force Digital Compare A Event 1
//! - EPWM_TZ_FORCE_EVENT_DCAEVT2 - Force Digital Compare A Event 2
//! - EPWM_TZ_FORCE_EVENT_DCBEVT1 - Force Digital Compare B Event 1
//! - EPWM_TZ_FORCE_EVENT_DCBEVT2 - Force Digital Compare B Event 2
//!
//! \return None.
//
//***************************************************************************
static inline void
EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
{
//
// Check the arguments
//
;
;
//
// Force a Trip Zone event
//
__eallow();
(*((volatile uint16_t *)(base + 0x9BU))) |= tzForceEvent;
__edis();
}
//
// Event Trigger related APIs
//
//*****************************************************************************
//
//! Enable ePWM interrupt.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the ePWM interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableInterrupt(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable ePWM interrupt
//
(*((volatile uint16_t *)(base + 0xA4U))) |= 0x8U;
}
//*****************************************************************************
//
//! disable ePWM interrupt.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the ePWM interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableInterrupt(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable ePWM interrupt
//
(*((volatile uint16_t *)(base + 0xA4U))) &= ~0x8U;
}
//*****************************************************************************
//
//! Sets the ePWM interrupt source.
//!
//! \param base is the base address of the EPWM module.
//! \param interruptSource is the ePWM interrupt source.
//!
//! This function sets the ePWM interrupt source.
//! Valid values for interruptSource are:
//! - EPWM_INT_TBCTR_DISABLED - Time-base counter is disabled
//! - EPWM_INT_TBCTR_ZERO - Time-base counter equal to zero
//! - EPWM_INT_TBCTR_PERIOD - Time-base counter equal to period
//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or
//! period
//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or
//! period
//! - EPWM_INT_TBCTR_U_CMPx - Where x is A,B,C or D
//! Time-base counter equal to CMPA, CMPB,
//! CMPC or CMPD (depending the value of x)
//! when the timer is incrementing
//! - EPWM_INT_TBCTR_D_CMPx - Where x is A,B,C or D
//! Time-base counter equal to CMPA, CMPB,
//! CMPC or CMPD (depending the value of x)
//! when the timer is decrementing
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource)
{
uint16_t intSource;
//
// Check the arguments
//
;
;
if((interruptSource == 8U) ||
(interruptSource == 12U) ||
(interruptSource == 10U) ||
(interruptSource == 14U))
{
//
// Shift the interrupt source by 1
//
intSource = interruptSource >> 1U;
//
// Enable events based on comp C or comp D
//
(*((volatile uint16_t *)(base + 0xA4U))) |= 0x40U;
}
else if((interruptSource == 4U) ||
(interruptSource == 6U) ||
(interruptSource == 5U) ||
(interruptSource == 7U))
{
intSource = interruptSource;
//
// Enable events based on comp A or comp B
//
(*((volatile uint16_t *)(base + 0xA4U))) &= ~0x40U;
}
else
{
intSource = interruptSource;
}
//
// Set the interrupt source
//
(*((volatile uint16_t *)(base + 0xA4U))) =
(((*((volatile uint16_t *)(base + 0xA4U))) & ~0x7U) | intSource);
}
//*****************************************************************************
//
//! Sets the ePWM interrupt event counts.
//!
//! \param base is the base address of the EPWM module.
//! \param eventCount is the event count for interrupt scale
//!
//! This function sets the interrupt event count that determines the number of
//! events that have to occur before an interrupt is issued.
//! Maximum value for eventCount is 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
{
//
// Check the arguments
//
;
;
//
// Enable advanced feature of interrupt every up to 15 events
//
(*((volatile uint16_t *)(base + 0xA6U))) |= 0x10U;
(*((volatile uint16_t *)(base + 0xAEU))) =
(((*((volatile uint16_t *)(base + 0xAEU))) & ~0xFU) |
eventCount);
}
//*****************************************************************************
//
//! Return the interrupt status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the ePWM interrupt status.
//! \b Note This function doesn't return the Trip Zone status.
//!
//! \return Returns true if ePWM interrupt was generated.
//! Returns false if no interrupt was generated
//
//*****************************************************************************
static inline _Bool
EPWM_getEventTriggerInterruptStatus(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return INT bit of ETFLG register
//
return((((*((volatile uint16_t *)(base + 0xA8U))) & 0x1U) == 0x1U) ? 1 : 0);
}
//*****************************************************************************
//
//! Clear interrupt flag.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function clears the ePWM interrupt flag.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_clearEventTriggerInterruptFlag(uint32_t base)
{
//
// Check the arguments
//
;
//
// Clear INT bit of ETCLR register
//
(*((volatile uint16_t *)(base + 0xAAU))) |= 0x1U;
}
//*****************************************************************************
//
//! Enable Pre-interrupt count load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the ePWM interrupt counter to be pre-interrupt loaded
//! with a count value.
//!
//! \note This is valid only for advanced/expanded interrupt mode
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableInterruptEventCountInit(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable interrupt event count initializing/loading
//
(*((volatile uint16_t *)(base + 0xB2U))) |= 0x2000U;
}
//*****************************************************************************
//
//! Disable interrupt count load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the ePWM interrupt counter from being loaded with
//! pre-interrupt count value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableInterruptEventCountInit(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable interrupt event count initializing/loading
//
(*((volatile uint16_t *)(base + 0xB2U))) &= ~0x2000U;
}
//*****************************************************************************
//
//! Force a software pre interrupt event counter load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function forces the ePWM interrupt counter to be loaded with the
//! contents set by EPWM_setPreInterruptEventCount().
//!
//! \note make sure the EPWM_enablePreInterruptEventCountLoad() function is
//! is called before invoking this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceInterruptEventCountInit(uint32_t base)
{
//
// Check the arguments
//
;
//
// Load the Interrupt Event counter value
//
(*((volatile uint16_t *)(base + 0xB2U))) |= 0x400U;
}
//*****************************************************************************
//
//! Set interrupt count.
//!
//! \param base is the base address of the EPWM module.
//! \param eventCount is the ePWM interrupt count value.
//!
//! This function sets the ePWM interrupt count. eventCount is the value of the
//! pre-interrupt value that is to be loaded. The maximum value of eventCount
//! is 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
{
//
// Check the arguments
//
;
;
//
// Set the Pre-interrupt event count
//
(*((volatile uint16_t *)(base + 0xB4U))) =
(((*((volatile uint16_t *)(base + 0xB4U))) & ~0xFU) |
(uint16_t)(eventCount & 0xFU));
}
//*****************************************************************************
//
//! Get the interrupt count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the ePWM interrupt event count.
//!
//! \return The interrupt event counts that have occurred.
//
//*****************************************************************************
static inline uint16_t
EPWM_getInterruptEventCount(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the interrupt event count
//
return((((*((volatile uint16_t *)(base + 0xAEU))) & 0xF0U) >>
4U));
}
//*****************************************************************************
//
//! Force ePWM interrupt.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function forces an ePWM interrupt.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_forceEventTriggerInterrupt(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set INT bit of ETFRC register
//
(*((volatile uint16_t *)(base + 0xACU))) |= 0x1U;
}
//
// ADC SOC configuration related APIs
//
//*****************************************************************************
//
//! Enable ADC SOC event.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function enables the ePWM module to trigger an ADC SOC event.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Enable an SOC
//
if(adcSOCType == EPWM_SOC_A)
{
(*((volatile uint16_t *)(base + 0xA4U))) |= 0x800U;
}
else
{
(*((volatile uint16_t *)(base + 0xA4U))) |= 0x8000U;
}
}
//*****************************************************************************
//
//! Disable ADC SOC event.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function disables the ePWM module from triggering an ADC SOC event.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Disable an SOC
//
if(adcSOCType == EPWM_SOC_A)
{
(*((volatile uint16_t *)(base + 0xA4U))) &= ~0x800U;
}
else
{
(*((volatile uint16_t *)(base + 0xA4U))) &= ~0x8000U;
}
}
//*****************************************************************************
//
//! Sets the ePWM SOC source.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//! \param socSource is the SOC source.
//!
//! This function sets the ePWM ADC SOC source.
//! Valid values for socSource are:
//! - adcSOCType
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//! - socSource
//! - EPWM_SOC_DCxEVT1 - Event is based on DCxEVT1
//! - EPWM_SOC_TBCTR_ZERO - Time-base counter equal to zero
//! - EPWM_SOC_TBCTR_PERIOD - Time-base counter equal to period
//! - EPWM_SOC_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or
//! period
//! - EPWM_SOC_TBCTR_U_CMPx - Where x is A,B,C or D
//! Time-base counter equal to CMPA, CMPB,
//! CMPC or CMPD(depending the value of x)
//! when the timer is incrementing
//! - EPWM_SOC_TBCTR_D_CMPx - Where x is A,B,C or D
//! Time-base counter equal to CMPA, CMPB,
//! CMPC or CMPD(depending the value of x)
//! when the timer is decrementing
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerSource(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType,
EPWM_ADCStartOfConversionSource socSource)
{
uint16_t source;
//
// Check the arguments
//
;
if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
(socSource == EPWM_SOC_TBCTR_U_CMPD) ||
(socSource == EPWM_SOC_TBCTR_D_CMPC) ||
(socSource == EPWM_SOC_TBCTR_D_CMPD))
{
source = (uint16_t)socSource >> 1U;
}
else
{
source = (uint16_t)socSource;
}
if(adcSOCType == EPWM_SOC_A)
{
//
// Set the SOC source
//
(*((volatile uint16_t *)(base + 0xA4U))) =
(((*((volatile uint16_t *)(base + 0xA4U))) & ~0x700U) |
(source << 8U));
//
// Enable the comparator selection
//
if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
(socSource == EPWM_SOC_TBCTR_U_CMPB) ||
(socSource == EPWM_SOC_TBCTR_D_CMPA) ||
(socSource == EPWM_SOC_TBCTR_D_CMPB))
{
//
// Enable events based on comp A or comp B
//
(*((volatile uint16_t *)(base + 0xA4U))) &= ~0x10U;
}
else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
(socSource == EPWM_SOC_TBCTR_U_CMPD) ||
(socSource == EPWM_SOC_TBCTR_D_CMPC) ||
(socSource == EPWM_SOC_TBCTR_D_CMPD))
{
//
// Enable events based on comp C or comp D
//
(*((volatile uint16_t *)(base + 0xA4U))) |= 0x10U;
}
else
{
//
// No action required for the other socSource options
//
}
}
else
{
//
// Enable the comparator selection
//
(*((volatile uint16_t *)(base + 0xA4U))) =
(((*((volatile uint16_t *)(base + 0xA4U))) & ~0x7000U) |
(source << 12U));
//
// Enable the comparator selection
//
if((socSource == EPWM_SOC_TBCTR_U_CMPA) ||
(socSource == EPWM_SOC_TBCTR_U_CMPB) ||
(socSource == EPWM_SOC_TBCTR_D_CMPA) ||
(socSource == EPWM_SOC_TBCTR_D_CMPB))
{
//
// Enable events based on comp A or comp B
//
(*((volatile uint16_t *)(base + 0xA4U))) &= ~0x20U;
}
else if((socSource == EPWM_SOC_TBCTR_U_CMPC) ||
(socSource == EPWM_SOC_TBCTR_U_CMPD) ||
(socSource == EPWM_SOC_TBCTR_D_CMPC) ||
(socSource == EPWM_SOC_TBCTR_D_CMPD))
{
//
// Enable events based on comp C or comp D
//
(*((volatile uint16_t *)(base + 0xA4U))) |= 0x20U;
}
else
{
//
// No action required for the other socSource options
//
}
}
}
//*****************************************************************************
//
//! Sets the ePWM SOC event counts.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//! \param preScaleCount is the event count number.
//!
//! This function sets the SOC event count that determines the number of
//! events that have to occur before an SOC is issued.
//! Valid values for the parameters are:
//! - adcSOCType
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//! - preScaleCount
//! - [1 - 15] - Generate SOC pulse every preScaleCount
//! up to 15 events.
//!
//! \note A preScaleCount value of 0 disables the prescale.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerEventPrescale(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType,
uint16_t preScaleCount)
{
//
// Check the arguments
//
;
;
//
// Enable advanced feature of SOC every up to 15 events
//
(*((volatile uint16_t *)(base + 0xA6U))) |= 0x20U;
if(adcSOCType == EPWM_SOC_A)
{
//
// Set the count for SOC A
//
(*((volatile uint16_t *)(base + 0xB0U))) =
(((*((volatile uint16_t *)(base + 0xB0U))) & ~0xFU) |
preScaleCount);
}
else
{
//
// Set the count for SOC B
//
(*((volatile uint16_t *)(base + 0xB0U))) =
(((*((volatile uint16_t *)(base + 0xB0U))) & ~0xF00U) |
(preScaleCount << 8U));
}
}
//*****************************************************************************
//
//! Return the SOC event status.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function returns the ePWM SOC status.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \return Returns true if the selected adcSOCType SOC was generated.
//! Returns false if the selected adcSOCType SOC was not generated.
//
//*****************************************************************************
static inline _Bool
EPWM_getADCTriggerFlagStatus(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Return the SOC A/ B status
//
return(((((*((volatile uint16_t *)(base + 0xA8U))) >>
((uint16_t)adcSOCType + 2U)) & 0x1U) == 0x1U) ? 1 : 0);
}
//*****************************************************************************
//
//! Clear SOC flag.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function clears the ePWM SOC flag.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_clearADCTriggerFlag(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Clear SOC A/B bit of ETCLR register
//
(*((volatile uint16_t *)(base + 0xAAU))) |= 1U << ((uint16_t)adcSOCType + 2U);
}
//*****************************************************************************
//
//! Enable Pre-SOC event count load.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function enables the ePWM SOC event counter which is set by the
//! EPWM_setADCTriggerEventCountInitValue() function to be loaded before
//! an SOC event.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \note This is valid only for advanced/expanded SOC mode
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableADCTriggerEventCountInit(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Enable SOC event count initializing/loading
//
(*((volatile uint16_t *)(base + 0xB2U))) |= 1U << ((uint16_t)adcSOCType + 14U);
}
//*****************************************************************************
//
//! Disable Pre-SOC event count load.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function disables the ePWM SOC event counter from being loaded before
//! an SOC event (only an SOC event causes an increment of the counter value).
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \note This is valid only for advanced/expanded SOC mode
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableADCTriggerEventCountInit(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Disable SOC event count initializing/loading
//
(*((volatile uint16_t *)(base + 0xB2U))) &=
~(1U << ((uint16_t)adcSOCType + 14U));
}
//*****************************************************************************
//
//! Force a software pre SOC event counter load.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type
//!
//! This function forces the ePWM SOC counter to be loaded with the
//! contents set by EPWM_setPreADCStartOfConversionEventCount().
//!
//! \note make sure the EPWM_enableADCTriggerEventCountInit()
//! function is called before invoking this function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceADCTriggerEventCountInit(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Load the Interrupt Event counter value
//
(*((volatile uint16_t *)(base + 0xB2U))) |= 1U << ((uint16_t)adcSOCType + 11U);
}
//*****************************************************************************
//
//! Set ADC Trigger count values.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//! \param eventCount is the ePWM interrupt count value.
//!
//! This function sets the ePWM ADC Trigger count values.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//! The eventCount has a maximum value of 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setADCTriggerEventCountInitValue(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType,
uint16_t eventCount)
{
//
// Check the arguments
//
;
;
//
// Set the ADC Trigger event count
//
if(adcSOCType == EPWM_SOC_A)
{
(*((volatile uint16_t *)(base + 0xB4U))) =
(((*((volatile uint16_t *)(base + 0xB4U))) & ~0xF0U) |
(uint16_t)(eventCount << 4U));
}
else
{
(*((volatile uint16_t *)(base + 0xB4U))) =
(((*((volatile uint16_t *)(base + 0xB4U))) & ~0xF00U) |
(eventCount << 8U));
}
}
//*****************************************************************************
//
//! Get the SOC event count.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function returns the ePWM SOC event count.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \return The SOC event counts that have occurred.
//
//*****************************************************************************
static inline uint16_t
EPWM_getADCTriggerEventCount(uint32_t base,
EPWM_ADCStartOfConversionType adcSOCType)
{
uint16_t eventCount;
//
// Check the arguments
//
;
//
// Return the SOC event count
//
if(adcSOCType == EPWM_SOC_A)
{
eventCount = ((*((volatile uint16_t *)(base + 0xB0U))) >>
4U) & 0xFU;
}
else
{
eventCount = ((*((volatile uint16_t *)(base + 0xB0U))) >>
12U) & 0xFU;
}
return(eventCount);
}
//*****************************************************************************
//
//! Force SOC event.
//!
//! \param base is the base address of the EPWM module.
//! \param adcSOCType is the ADC SOC type.
//!
//! This function forces an ePWM SOC event.
//! Valid values for adcSOCType are:
//! - EPWM_SOC_A - SOC A
//! - EPWM_SOC_B - SOC B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
{
//
// Check the arguments
//
;
//
// Set SOC A/B bit of ETFRC register
//
(*((volatile uint16_t *)(base + 0xACU))) |= 1U << ((uint16_t)adcSOCType + 2U);
}
//
// Digital Compare module related APIs
//
//*****************************************************************************
//
//! Set the DC trip input.
//!
//! \param base is the base address of the EPWM module.
//! \param tripSource is the tripSource.
//! \param dcType is the Digital Compare type.
//!
//! This function sets the trip input to the Digital Compare (DC). For a given
//! dcType the function sets the tripSource to be the input to the DC.
//! Valid values for the parameter are:
//! - tripSource
//! - EPWM_DC_TRIP_TRIPINx - Trip x,where x ranges from 1 to 15 excluding 13
//! - EPWM_DC_TRIP_COMBINATION - selects all the Trip signals whose input
//! is enabled by the following function
//! EPWM_enableDigitalCompareTripCombinationInput()
//! - dcType
//! - EPWM_DC_TYPE_DCAH - Digital Compare A High
//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low
//! - EPWM_DC_TYPE_DCBH - Digital Compare B High
//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_selectDigitalCompareTripInput(uint32_t base,
EPWM_DigitalCompareTripInput tripSource,
EPWM_DigitalCompareType dcType)
{
//
// Check the arguments
//
;
//
// Set the DC trip input
//
__eallow();
(*((volatile uint16_t *)(base + 0xC0U))) =
(((*((volatile uint16_t *)(base + 0xC0U))) & ~(0xFU << ((uint16_t)dcType << 2U))) |
((uint16_t)tripSource << ((uint16_t)dcType << 2U)));
__edis();
}
//
// DCFILT
//
//*****************************************************************************
//
//! Enable DC filter blanking window.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the DC filter blanking window.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable DC filter blanking window
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) |= 0x4U;
__edis();
}
//*****************************************************************************
//
//! Disable DC filter blanking window.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the DC filter blanking window.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable DC filter blanking window
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) &= ~0x4U;
__edis();
}
//*****************************************************************************
//
//! Enable Digital Compare Window inverse mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the Digital Compare Window inverse mode. This will
//! invert the blanking window.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable DC window inverse mode.
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) |= 0x8U;
__edis();
}
//*****************************************************************************
//
//! Disable Digital Compare Window inverse mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Digital Compare Window inverse mode.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable DC window inverse mode.
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) &= ~0x8U;
__edis();
}
//*****************************************************************************
//
//! Set the Digital Compare filter blanking pulse.
//!
//! \param base is the base address of the EPWM module.
//! \param blankingPulse is Pulse that starts blanking window.
//!
//! This function sets the input pulse that starts the Digital Compare blanking
//! window.
//! Valid values for blankingPulse are:
//! - EPWM_DC_WINDOW_START_TBCTR_PERIOD - Time base counter equals period
//! - EPWM_DC_WINDOW_START_TBCTR_ZERO - Time base counter equals zero
//! - EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD - Time base counter equals zero
//! or period.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareBlankingEvent(uint32_t base,
EPWM_DigitalCompareBlankingPulse blankingPulse)
{
//
// Check the arguments
//
;
//
// Set DC blanking event
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) =
(((*((volatile uint16_t *)(base + 0xC7U))) & ~0x30U) |
((uint16_t)((uint32_t)blankingPulse << 4U)));
__edis();
}
//*****************************************************************************
//
//! Set up the Digital Compare filter input.
//!
//! \param base is the base address of the EPWM module.
//! \param filterInput is Digital Compare signal source.
//!
//! This function sets the signal input source that will be filtered by the
//! Digital Compare module.
//! Valid values for filterInput are:
//! - EPWM_DC_WINDOW_SOURCE_DCAEVT1 - DC filter signal source is DCAEVT1
//! - EPWM_DC_WINDOW_SOURCE_DCAEVT2 - DC filter signal source is DCAEVT2
//! - EPWM_DC_WINDOW_SOURCE_DCBEVT1 - DC filter signal source is DCBEVT1
//! - EPWM_DC_WINDOW_SOURCE_DCBEVT2 - DC filter signal source is DCBEVT2
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareFilterInput(uint32_t base,
EPWM_DigitalCompareFilterInput filterInput)
{
//
// Check the arguments
//
;
//
// Set the signal source that will be filtered
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) =
(((*((volatile uint16_t *)(base + 0xC7U))) & ~0x3U) |
((uint16_t)filterInput));
__edis();
}
//
// DC Edge Filter
//
//*****************************************************************************
//
//! Enable Digital Compare Edge Filter.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the Digital Compare Edge filter to generate event
//! after configured number of edges.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable DC Edge Filter
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) |= 0x40U;
__edis();
}
//*****************************************************************************
//
//! Disable Digital Compare Edge Filter.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the Digital Compare Edge filter.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable DC Edge Filter
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) &= ~0x40U;
__edis();
}
//*****************************************************************************
//
//! Set the Digital Compare Edge Filter Mode.
//!
//! \param base is the base address of the EPWM module.
//! \param edgeMode is Digital Compare Edge filter mode.
//!
//! This function sets the Digital Compare Event filter mode. Valid values
//! for edgeMode are:
//! - EPWM_DC_EDGEFILT_MODE_RISING - DC edge filter mode is rising edge
//! - EPWM_DC_EDGEFILT_MODE_FALLING - DC edge filter mode is falling edge
//! - EPWM_DC_EDGEFILT_MODE_BOTH - DC edge filter mode is both edges
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEdgeFilterMode(uint32_t base,
EPWM_DigitalCompareEdgeFilterMode edgeMode)
{
//
// Check the arguments
//
;
//
// Set DC Edge filter mode
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) =
((*((volatile uint16_t *)(base + 0xC7U))) & ~0x300U) |
((uint16_t)edgeMode << 8U);
__edis();
}
//*****************************************************************************
//
//! Set the Digital Compare Edge Filter Edge Count.
//!
//! \param base is the base address of the EPWM module.
//! \param edgeCount is Digital Compare event filter count
//!
//! This function sets the Digital Compare Event filter Edge Count to generate
//! events. Valid values for edgeCount can be:
//! - EPWM_DC_EDGEFILT_EDGECNT_0 - No edge is required to generate event
//! - EPWM_DC_EDGEFILT_EDGECNT_1 - 1 edge is required for event generation
//! - EPWM_DC_EDGEFILT_EDGECNT_2 - 2 edges are required for event generation
//! - EPWM_DC_EDGEFILT_EDGECNT_3 - 3 edges are required for event generation
//! - EPWM_DC_EDGEFILT_EDGECNT_4 - 4 edges are required for event generation
//! - EPWM_DC_EDGEFILT_EDGECNT_5 - 5 edges are required for event generation
//! - EPWM_DC_EDGEFILT_EDGECNT_6 - 6 edges are required for event generation
//! - EPWM_DC_EDGEFILT_EDGECNT_7 - 7 edges are required for event generation
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, uint16_t edgeCount)
{
//
// Check the arguments
//
;
//
// Set DC Edge filter edge count
//
__eallow();
(*((volatile uint16_t *)(base + 0xC7U))) = ((*((volatile uint16_t *)(base + 0xC7U))) &
~0x1C00U) |
(edgeCount << 10U);
__edis();
}
//*****************************************************************************
//
//! Returns the Digital Compare Edge Filter Edge Count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the configured Digital Compare Edge filter edge
//! count required to generate events. It can return values from 0-7.
//!
//! \return Returns the configured DigitalCompare Edge filter edge count.
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return configured DC edge filter edge count
//
return(((*((volatile uint16_t *)(base + 0xC7U))) & 0x1C00U) >>
10U);
}
//*****************************************************************************
//
//! Returns the Digital Compare Edge filter captured edge count status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the count of edges captured by Digital Compare Edge
//! filter. It can return values from 0-7.
//!
//! \return Returns the count of captured edges
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return captured edge count by DC Edge filter
//
return(((*((volatile uint16_t *)(base + 0xC7U))) & 0xE000U) >>
13U);
}
//*****************************************************************************
//
//! Set up the Digital Compare filter window offset
//!
//! \param base is the base address of the EPWM module.
//! \param windowOffsetCount is blanking window offset length.
//!
//! This function sets the offset between window start pulse and blanking
//! window in TBCLK count.
//! The function take a 16bit count value for the offset value.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
{
//
// Check the arguments
//
;
//
// Set the blanking window offset in TBCLK counts
//
(*((volatile uint16_t *)(base + 0xC9U))) = windowOffsetCount;
}
//*****************************************************************************
//
//! Set up the Digital Compare filter window length
//!
//! \param base is the base address of the EPWM module.
//! \param windowLengthCount is blanking window length.
//!
//! This function sets up the Digital Compare filter blanking window length in
//! TBCLK count.The function takes a 16bit count value for the window length.
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
{
//
// Check the arguments
//
;
//
// Set the blanking window length in TBCLK counts
//
(*((volatile uint16_t *)(base + 0xCBU))) = windowLengthCount;
}
//*****************************************************************************
//
//! Return DC filter blanking window offset count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns DC filter blanking window offset count.
//!
//! \return None
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the Blanking Window Offset count
//
return((*((volatile uint16_t *)(base + 0xCAU))));
}
//*****************************************************************************
//
//! Return DC filter blanking window length count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns DC filter blanking window length count.
//!
//! \return None
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the Blanking Window Length count
//
return((*((volatile uint16_t *)(base + 0xCCU))));
}
//*****************************************************************************
//
//! Set up the Digital Compare Event source.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param dcEventSource is the - Digital Compare Event source.
//!
//! This function sets up the Digital Compare module Event sources.
//! The following are valid values for the parameters.
//! - dcModule
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//! - dcEvent
//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1
//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2
//! - dcEventSource
//! - EPWM_DC_EVENT_SOURCE_FILT_SIGNAL - signal source is filtered
//! \note The signal source for this option is DCxEVTy, where the
//! value of x is dependent on dcModule and the value of y is
//! dependent on dcEvent. Possible signal sources are DCAEVT1,
//! DCBEVT1, DCAEVT2 or DCBEVT2 depending on the value of both
//! dcModule and dcEvent.
//! - EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL - signal source is unfiltered
//! The signal source for this option is DCxEVTy.
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEventSource(uint32_t base,
EPWM_DigitalCompareModule dcModule,
EPWM_DigitalCompareEvent dcEvent,
EPWM_DigitalCompareEventSource dcEventSource)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Set the DC event 1 source source
//
__eallow();
if(dcEvent == EPWM_DC_EVENT_1)
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x1U) |
(uint16_t)dcEventSource);
}
else
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x100U) |
((uint16_t)dcEventSource << 8U));
}
__edis();
}
//*****************************************************************************
//
//! Set up the Digital Compare input sync mode.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param syncMode is the Digital Compare Event sync mode.
//!
//! This function sets up the Digital Compare module Event sources.
//! The following are valid values for the parameters.
//! - dcModule
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//! - dcEvent
//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1
//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2
//! - syncMode
//! - EPWM_DC_EVENT_INPUT_SYNCED - DC input signal is synced with
//! TBCLK
//! - EPWM_DC_EVENT_INPUT_NOT SYNCED - DC input signal is not synced with
//! TBCLK
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareEventSyncMode(uint32_t base,
EPWM_DigitalCompareModule dcModule,
EPWM_DigitalCompareEvent dcEvent,
EPWM_DigitalCompareSyncMode syncMode)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Set the DC event sync mode
//
__eallow();
if(dcEvent == EPWM_DC_EVENT_1)
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x2U) |
((uint16_t)syncMode << 1U));
}
else
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x200U) |
((uint16_t)syncMode << 9U));
}
__edis();
}
//*****************************************************************************
//
//! Enable Digital Compare to generate Start of Conversion.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function enables the Digital Compare Event 1 to generate Start of
//! Conversion.
//! The following are valid values for the \e dcModule parameter.
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareADCTrigger(uint32_t base,
EPWM_DigitalCompareModule dcModule)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Enable Digital Compare start of conversion generation
//
__eallow();
(*((volatile uint16_t *)(base + registerOffset))) =
((*((volatile uint16_t *)(base + registerOffset))) | 0x4U);
__edis();
}
//*****************************************************************************
//
//! Disable Digital Compare from generating Start of Conversion.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function disables the Digital Compare Event 1 from generating Start of
//! Conversion.
//! The following are valid values for the \e dcModule parameter.
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareADCTrigger(uint32_t base,
EPWM_DigitalCompareModule dcModule)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Disable Digital Compare start of conversion generation
//
__eallow();
(*((volatile uint16_t *)(base + registerOffset))) =
((*((volatile uint16_t *)(base + registerOffset))) & ~0x4U);
__edis();
}
//*****************************************************************************
//
//! Enable Digital Compare to generate sync out pulse.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function enables the Digital Compare Event 1 to generate sync out
//! pulse
//! The following are valid values for the \e dcModule parameter.
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareSyncEvent(uint32_t base,
EPWM_DigitalCompareModule dcModule)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Enable Digital Compare sync out pulse generation
//
__eallow();
(*((volatile uint16_t *)(base + registerOffset))) =
((*((volatile uint16_t *)(base + registerOffset))) | 0x8U);
__edis();
}
//*****************************************************************************
//
//! Disable Digital Compare from generating Start of Conversion.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//!
//! This function disables the Digital Compare Event 1 from generating synch
//! out pulse.
//! The following are valid values for the \e dcModule parameters.
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareSyncEvent(uint32_t base,
EPWM_DigitalCompareModule dcModule)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Disable Digital Compare sync out pulse generation
//
__eallow();
(*((volatile uint16_t *)(base + registerOffset))) =
((*((volatile uint16_t *)(base + registerOffset))) & ~0x8U);
__edis();
}
//*****************************************************************************
//
//! Set up the Digital Compare CBC latch mode.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param latchMode is the Digital Compare CBC latch mode.
//!
//! This function sets up the Digital Compare CBC latch mode.
//! The following are valid values for the parameters.
//! - dcModule
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//! - dcEvent
//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1
//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2
//! - latchMode
//! - EPWM_DC_CBC_LATCH_DISABLED - DC cycle-by-cycle(CBC) latch is disabled
//! - EPWM_DC_CBC_LATCH_ENABLED - DC cycle-by-cycle(CBC) latch is enabled
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareCBCLatchMode(uint32_t base,
EPWM_DigitalCompareModule dcModule,
EPWM_DigitalCompareEvent dcEvent,
EPWM_DigitalCompareCBCLatchMode latchMode)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Set the DC CBC Latch Mode
//
__eallow();
if(dcEvent == EPWM_DC_EVENT_1)
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x10U) |
((uint16_t)latchMode << 4U));
}
else
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x1000U) |
((uint16_t)latchMode << 12U));
}
__edis();
}
//*****************************************************************************
//
//! Sets the Digital Compare CBC latch clear event.
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//! \param clearEvent is the Digital Compare CBC latch clear event.
//!
//! This function sets the Digital Compare CBC latch clear event.
//! The following are valid values for the parameters.
//! - dcModule
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//! - dcEvent
//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1
//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2
//! - clearEvent
//! - EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO - DC CBC latch is cleared when
//! counter is zero
//! - EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD - DC CBC latch is cleared when
//! counter is equal to period
//! - EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD - DC CBC latch is cleared
//! when either counter is
//! zero or equal to period
//!
//! \return None
//
//*****************************************************************************
static inline void
EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base,
EPWM_DigitalCompareModule dcModule,
EPWM_DigitalCompareEvent dcEvent,
EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Set the DC CBC Latch Clear Event
//
__eallow();
if(dcEvent == EPWM_DC_EVENT_1)
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x60U) |
((uint16_t)clearEvent << 5U));
}
else
{
(*((volatile uint16_t *)(base + registerOffset))) =
(((*((volatile uint16_t *)(base + registerOffset))) & ~0x6000U) |
((uint16_t)clearEvent << 13U));
}
__edis();
}
//*****************************************************************************
//
//! Gets the Digital Compare CBC latch status
//!
//! \param base is the base address of the EPWM module.
//! \param dcModule is the Digital Compare module.
//! \param dcEvent is the Digital Compare Event number.
//!
//! This function returns the Digital Compare module cycle-by-cycle(CBC) latch
//! status.
//! The following are valid values for the parameters.
//! - dcModule
//! - EPWM_DC_MODULE_A - Digital Compare Module A
//! - EPWM_DC_MODULE_B - Digital Compare Module B
//! - dcEvent
//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1
//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2
//!
//! \return Returns Digital Compare CBC latch status.
//! -\b true - CBC latch is enabled
//! -\b false - CBC latch is disabled
//
//*****************************************************************************
static inline _Bool
EPWM_getDigitalCompareCBCLatchStatus(uint32_t base,
EPWM_DigitalCompareModule dcModule,
EPWM_DigitalCompareEvent dcEvent)
{
uint32_t registerOffset;
uint16_t status;
//
// Check the arguments
//
;
registerOffset = 0xC3U + (uint32_t)dcModule;
//
// Get DC CBC Latch Clear Event
//
if(dcEvent == EPWM_DC_EVENT_1)
{
status = (*((volatile uint16_t *)(base + registerOffset))) & 0x80U;
}
else
{
status = (*((volatile uint16_t *)(base + registerOffset))) & 0x8000U;
}
return(status != 0U);
}
//
// DC capture mode
//
//*****************************************************************************
//
//! Enables the Time Base Counter Capture controller.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the time Base Counter Capture.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareCounterCapture(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable Time base counter capture
//
__eallow();
(*((volatile uint16_t *)(base + 0xC8U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Disables the Time Base Counter Capture controller.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disable the time Base Counter Capture.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareCounterCapture(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable Time base counter capture
//
__eallow();
(*((volatile uint16_t *)(base + 0xC8U))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! Set the Time Base Counter Capture mode.
//!
//! \param base is the base address of the EPWM module.
//! \param enableShadowMode is the shadow read mode flag.
//!
//! This function sets the mode the Time Base Counter value is read from. If
//! enableShadowMode is true, CPU reads of the DCCAP register will return the
//! shadow register contents.If enableShadowMode is false, CPU reads of the
//! DCCAP register will return the active register contents.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setDigitalCompareCounterShadowMode(uint32_t base, _Bool enableShadowMode)
{
//
// Check the arguments
//
;
__eallow();
if(enableShadowMode)
{
//
// Enable DC counter shadow mode
//
(*((volatile uint16_t *)(base + 0xC8U))) &= ~0x2U;
}
else
{
//
// Disable DC counter shadow mode
//
(*((volatile uint16_t *)(base + 0xC8U))) |= 0x2U;
}
__edis();
}
//*****************************************************************************
//
//! Return the DC Capture event status.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the DC capture event status.
//!
//! \return Returns true if a DC capture event has occurs.
//! Returns false if no DC Capture event has occurred.
//!
//! \return None.
//
//*****************************************************************************
static inline _Bool
EPWM_getDigitalCompareCaptureStatus(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the DC compare status
//
return(((*((volatile uint16_t *)(base + 0xC8U))) & 0x2000U) ==
0x2000U);
}
//*****************************************************************************
//
//! Clears DC capture latched status flag
//!
//! \param base is the base address of the EPWM module.
//! This function is used to clear the CAPSTS (set) condition.
//!
//! \return None.
//*****************************************************************************
static inline void
EPWM_clearDigitalCompareCaptureStatusFlag(uint32_t base)
{
//
// Check the arguments
//
;
//
// Clear digital compare capture status flag
//
__eallow();
(*((volatile uint16_t *)(base + 0xC8U))) &= ~0x4000U;
__edis();
}
//*****************************************************************************
//
//! Configures DC capture operating mode
//!
//! \param base is the base address of the EPWM module.
//! \param disableClearMode is the clear mode bit.
//!
//! This function is used to configure the DC capture operating mode. If
//! \e disableClearMode is false, the TBCNT value is captured in active register
//! on occurance of DCEVTFILT event. The trip events are ignored until next
//! PRD or ZRO event re-triggers the capture mechanism.
//! If \e disableClearMode is true, the TBCNT value is captured, CAPSTS flag is
//! set and further trips are ignored until CAPSTS bit is cleared.
//!
//! \return None.
//*****************************************************************************
static inline void
EPWM_configureDigitalCompareCounterCaptureMode(uint32_t base,
_Bool disableClearMode)
{
//
// Check the arguments
//
;
__eallow();
if(disableClearMode)
{
//
// Disable DC counter auto-clear on PULSESEL event
//
(*((volatile uint16_t *)(base + 0xC8U))) |= 0x8000U;
}
else
{
//
// Enable DC counter clear on PULSESEL events
//
(*((volatile uint16_t *)(base + 0xC8U))) &= ~0x8000U;
}
__edis();
}
//*****************************************************************************
//
//! Return the DC Time Base Counter capture value.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the DC Time Base Counter capture value. The value
//! read is determined by the mode as set in the
//! EPWM_setTimeBaseCounterReadMode() function.
//!
//! \return Returns the DC Time Base Counter Capture count value.
//
//*****************************************************************************
static inline uint16_t
EPWM_getDigitalCompareCaptureCount(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the DC Time Base Counter Capture count value
//
return((*((volatile uint16_t *)(base + 0xCFU))));
}
//*****************************************************************************
//
//! Enable DC TRIP combinational input.
//!
//! \param base is the base address of the EPWM module.
//! \param tripInput is the Trip number.
//! \param dcType is the Digital Compare module.
//!
//! This function enables the specified Trip input.
//! Valid values for the parameters are:
//! - tripInput
//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15
//! - dcType
//! - EPWM_DC_TYPE_DCAH - Digital Compare A High
//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low
//! - EPWM_DC_TYPE_DCBH - Digital Compare B High
//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableDigitalCompareTripCombinationInput(uint32_t base,
uint16_t tripInput,
EPWM_DigitalCompareType dcType)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
//
// Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
// offset with respect to DCAHTRIPSEL
//
registerOffset = 0xD2U + (uint32_t)dcType;
//
// Set the DC trip input
//
__eallow();
(*((volatile uint16_t *)(base + registerOffset))) =
((*((volatile uint16_t *)(base + registerOffset))) | tripInput);
//
// Enable the combination input
//
(*((volatile uint16_t *)(base + 0xC0U))) =
((*((volatile uint16_t *)(base + 0xC0U))) | (0xFU << ((uint16_t)dcType << 2U)));
__edis();
}
//*****************************************************************************
//
//! Disable DC TRIP combinational input.
//!
//! \param base is the base address of the EPWM module.
//! \param tripInput is the Trip number.
//! \param dcType is the Digital Compare module.
//!
//! This function disables the specified Trip input.
//! Valid values for the parameters are:
//! - tripInput
//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15
//! - dcType
//! - EPWM_DC_TYPE_DCAH - Digital Compare A High
//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low
//! - EPWM_DC_TYPE_DCBH - Digital Compare B High
//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableDigitalCompareTripCombinationInput(uint32_t base,
uint16_t tripInput,
EPWM_DigitalCompareType dcType)
{
uint32_t registerOffset;
//
// Check the arguments
//
;
//
// Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register
// offset with respect to DCAHTRIPSEL
//
registerOffset = 0xD2U + (uint32_t)dcType;
//
// Set the DC trip input
//
__eallow();
(*((volatile uint16_t *)(base + registerOffset))) =
((*((volatile uint16_t *)(base + registerOffset))) & ~tripInput);
__edis();
}
//
// Valley switching
//
//*****************************************************************************
//
//! Enable valley capture mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables Valley Capture mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableValleyCapture(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set VCAPE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x18U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Disable valley capture mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables Valley Capture mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableValleyCapture(uint32_t base)
{
//
// Check the arguments
//
;
//
// Clear VCAPE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x18U))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! Start valley capture mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function starts Valley Capture sequence.
//!
//! \b Make sure you invoke EPWM_setValleyTriggerSource with the trigger
//! variable set to EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE before calling this
//! function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_startValleyCapture(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set VCAPSTART bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x18U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! Set valley capture trigger.
//!
//! \param base is the base address of the EPWM module.
//! \param trigger is the Valley counter trigger.
//!
//! This function sets the trigger value that initiates Valley Capture sequence
//!
//! \b Set the number of Trigger source events for starting and stopping the
//! valley capture using EPWM_setValleyTriggerEdgeCounts().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
{
//
// Check the arguments
//
;
//
// Write to TRIGSEL bits
//
__eallow();
(*((volatile uint16_t *)(base + 0x18U))) =
(((*((volatile uint16_t *)(base + 0x18U))) & ~0x1CU) |
((uint16_t)trigger << 2U));
__edis();
}
//*****************************************************************************
//
//! Set valley capture trigger source count.
//!
//! \param base is the base address of the EPWM module.
//! \param startCount
//! \param stopCount
//!
//! This function sets the number of trigger events required to start and stop
//! the valley capture count.
//! Maximum values for both startCount and stopCount is 15 corresponding to the
//! 15th edge of the trigger event.
//!
//! \b Note:
//! A startCount value of 0 prevents starting the valley counter.
//! A stopCount value of 0 prevents the valley counter from stopping.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount,
uint16_t stopCount)
{
//
// Check the arguments
//
;
;
//
// Write to STARTEDGE and STOPEDGE bits
//
__eallow();
(*((volatile uint16_t *)(base + 0x19U))) =
(((*((volatile uint16_t *)(base + 0x19U))) &
~(0xFU | 0xF00U)) |
(startCount | (stopCount << 8U)));
__edis();
}
//*****************************************************************************
//
//! Enable valley switching delay.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables Valley switching delay.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableValleyHWDelay(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set EDGEFILTDLYSEL bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x18U))) |= 0x400U;
__edis();
}
//*****************************************************************************
//
//! Disable valley switching delay.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables Valley switching delay.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableValleyHWDelay(uint32_t base)
{
//
// Check the arguments
//
;
//
// Clear EDGEFILTDLYSEL bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x18U))) &= ~0x400U;
__edis();
}
//*****************************************************************************
//
//! Set Valley delay values.
//!
//! \param base is the base address of the EPWM module.
//! \param delayOffsetValue is the software defined delay offset value.
//!
//! This function sets the Valley delay value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
{
//
// Check the arguments
//
;
//
// Write to SWVDELVAL bits
//
(*((volatile uint16_t *)(base + 0x77U))) = delayOffsetValue;
}
//*****************************************************************************
//
//! Set Valley delay mode.
//!
//! \param base is the base address of the EPWM module.
//! \param delayMode is the Valley delay mode.
//!
//! This function sets the Valley delay mode values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
{
//
// Check the arguments
//
;
//
// Write to VDELAYDIV bits
//
__eallow();
(*((volatile uint16_t *)(base + 0x18U))) =
(((*((volatile uint16_t *)(base + 0x18U))) & ~0x380U) |
((uint16_t)delayMode << 7U));
__edis();
}
//*****************************************************************************
//
//! Get the valley edge status bit.
//!
//! \param base is the base address of the EPWM module.
//! \param edge is the start or stop edge.
//!
//! This function returns the status of the start or stop valley status
//! depending on the value of edge.
//! If a start or stop edge has occurred, the function returns true, if not it
//! returns false.
//!
//! \return Returns true if the specified edge has occurred,
//! Returns false if the specified edge has not occurred.
//
//*****************************************************************************
static inline _Bool
EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
{
//
// Check the arguments
//
;
if(edge == EPWM_VALLEY_COUNT_START_EDGE)
{
//
// Returns STARTEDGESTS status
//
return((((*((volatile uint16_t *)(base + 0x19U))) & 0x80U) ==
0x80U ) ? 1 : 0);
}
else
{
//
// Returns STOPEDGESTS status
//
return((((*((volatile uint16_t *)(base + 0x19U))) & 0x8000U) ==
0x8000U) ? 1 : 0);
}
}
//*****************************************************************************
//
//! Get the Valley Counter value.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the valley time base count value which is captured
//! upon occurrence of the stop edge condition selected by
//! EPWM_setValleyTriggerSource() and by the stopCount variable of the
//! EPWM_setValleyTriggerEdgeCounts() function.
//!
//! \return Returns the valley base time count.
//
//*****************************************************************************
static inline uint16_t
EPWM_getValleyCount(uint32_t base)
{
//
// Check the arguments
//
;
//
// Read VCNTVAL register
//
return((*((volatile uint16_t *)(base + 0xFEU))));
}
//*****************************************************************************
//
//! Get the Valley delay value.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the hardware valley delay count.
//!
//! \return Returns the valley delay count.
//
//*****************************************************************************
static inline uint16_t
EPWM_getValleyHWDelay(uint32_t base)
{
//
// Check the arguments
//
;
//
// Read HWVDELVAL register
//
return((*((volatile uint16_t *)(base + 0xFDU))));
}
//*****************************************************************************
//
//! Enable Global shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables Global shadow to active load mode of registers.
//! The trigger source for loading shadow to active is determined by
//! EPWM_setGlobalLoadTrigger() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoad(uint32_t base)
{
//
// Check the arguments
//
;
//
// Shadow to active load is controlled globally
//
__eallow();
(*((volatile uint16_t *)(base + 0x34U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Disable Global shadow load mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables Global shadow to active load mode of registers.
//! Loading shadow to active is determined individually.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoad(uint32_t base)
{
//
// Check the arguments
//
;
//
// Shadow to active load is controlled individually
//
__eallow();
(*((volatile uint16_t *)(base + 0x34U))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! Set the Global shadow load pulse.
//!
//! \param base is the base address of the EPWM module.
//! \param loadTrigger is the pulse that causes global shadow load.
//!
//! This function sets the pulse that causes Global shadow to active load.
//! Valid values for the loadTrigger parameter are:
//!
//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO - load when counter is equal
//! to zero
//! - EPWM_GL_LOAD_PULSE_CNTR_PERIOD - load when counter is equal
//! to period
//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD - load when counter is equal
//! to zero or period
//! - EPWM_GL_LOAD_PULSE_SYNC - load on sync event
//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO - load on sync event or when
//! counter is equal to zero
//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD - load on sync event or when
//! counter is equal to period
//! - EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD - load on sync event or when
//! counter is equal to period
//! or zero
//! - EPWM_GL_LOAD_PULSE_GLOBAL_FORCE - load on global force
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
{
//
// Check the arguments
//
;
//
// Set the Global shadow to active load pulse
//
__eallow();
(*((volatile uint16_t *)(base + 0x34U))) =
(((*((volatile uint16_t *)(base + 0x34U))) & ~0x1EU) |
((uint16_t)loadTrigger << 1U));
__edis();
}
//*****************************************************************************
//
//! Set the number of Global load pulse event counts
//!
//! \param base is the base address of the EPWM module.
//! \param prescalePulseCount is the pulse event counts.
//!
//! This function sets the number of Global Load pulse events that have to
//! occurred before a global load pulse is issued. Valid values for
//! prescaleCount range from 0 to 7. 0 being no event (disables counter), and 7
//! representing 7 events.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
{
//
// Check the arguments
//
;
;
//
// Set the number of counts that have to occur before
// a load strobe is issued
//
__eallow();
(*((volatile uint16_t *)(base + 0x34U))) =
(((*((volatile uint16_t *)(base + 0x34U))) & ~0x380U) |
(prescalePulseCount << 7U));
__edis();
}
//*****************************************************************************
//
//! Return the number of Global load pulse event counts
//!
//! \param base is the base address of the EPWM module.
//!
//! This function returns the number of Global Load pulse events that have
//! occurred. These pulse events are set by the EPWM_setGlobalLoadTrigger()
//! function.
//!
//! \return None.
//
//*****************************************************************************
static inline uint16_t
EPWM_getGlobalLoadEventCount(uint32_t base)
{
//
// Check the arguments
//
;
//
// Return the number of events that have occurred
//
return(((*((volatile uint16_t *)(base + 0x34U))) >> 10U) & 0x7U);
}
//*****************************************************************************
//
//! Enable continuous global shadow to active load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables global continuous shadow to active load. Register
//! load happens every time the event set by the
//! EPWM_setGlobalLoadTrigger() occurs.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoadOneShotMode(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable global continuous shadow to active load
//
__eallow();
(*((volatile uint16_t *)(base + 0x34U))) &= ~0x20U;
__edis();
}
//*****************************************************************************
//
//! Enable One shot global shadow to active load.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables a one time global shadow to active load. Register
//! load happens every time the event set by the
//! EPWM_setGlobalLoadTrigger() occurs.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoadOneShotMode(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable global continuous shadow to active load
//
__eallow();
(*((volatile uint16_t *)(base + 0x34U))) |= 0x20U;
__edis();
}
//*****************************************************************************
//
//! Set One shot global shadow to active load pulse.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function sets a one time global shadow to active load pulse. The pulse
//! propagates to generate a load signal if any of the events set by
//! EPWM_setGlobalLoadTrigger() occur.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_setGlobalLoadOneShotLatch(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set a one shot Global shadow load pulse.
//
__eallow();
(*((volatile uint16_t *)(base + 0x74U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Force a software One shot global shadow to active load pulse.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function forces a software a one time global shadow to active load
//! pulse.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
{
//
// Check the arguments
//
;
//
// Force a Software Global shadow load pulse
//
__eallow();
(*((volatile uint16_t *)(base + 0x74U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! Enable a register to be loaded Globally.
//!
//! \param base is the base address of the EPWM module.
//! \param loadRegister is the register.
//!
//! This function enables the register specified by loadRegister to be globally
//! loaded.
//! Valid values for loadRegister are:
//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR
//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR
//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR
//! - EPWM_GL_REGISTER_CMPC - Register CMPC
//! - EPWM_GL_REGISTER_CMPD - Register CMPD
//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR
//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR
//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL
//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2
//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2
//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
{
//
// Check the arguments
//
;
;
//
// The register specified by loadRegister is loaded globally
//
__eallow();
(*((volatile uint16_t *)(base + 0x35U))) |= loadRegister;
__edis();
}
//*****************************************************************************
//
//! Disable a register to be loaded Globally.
//!
//! \param base is the base address of the EPWM module.
//! \param loadRegister is the register.
//!
//! This function disables the register specified by loadRegister from being
//! loaded globally. The shadow to active load happens as specified by the
//! register control
//! Valid values for loadRegister are:
//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR
//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR
//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR
//! - EPWM_GL_REGISTER_CMPC - Register CMPC
//! - EPWM_GL_REGISTER_CMPD - Register CMPD
//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR
//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR
//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL
//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2
//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2
//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
{
//
// Check the arguments
//
;
;
//
// The register specified by loadRegister is loaded by individual
// register configuration setting
//
__eallow();
(*((volatile uint16_t *)(base + 0x35U))) &= ~loadRegister;
__edis();
}
//*****************************************************************************
//
//! Lock EALLOW protected register groups
//!
//! \param base is the base address of the EPWM module.
//! \param registerGroup is the EALLOW register groups.
//!
//! This functions locks the EALLOW protected register groups specified by
//! the registerGroup variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
{
//
// Check the arguments
//
;
//
// Write the Key to EPWMLOCK register
//
(*((volatile uint32_t *)(base + 0xFAU))) =
(0xA5A50000UL | ((uint32_t)registerGroup));
}
//*****************************************************************************
//
//! Set emulation mode
//!
//! \param base is the base address of the EPWM module.
//! \param emulationMode is the emulation mode.
//!
//! This function sets the emulation behaviours of the time base counter. Valid
//! values for emulationMode are:
//! - EPWM_EMULATION_STOP_AFTER_NEXT_TB - Stop after next Time Base counter
//! increment or decrement.
//! - EPWM_EMULATION_STOP_AFTER_FULL_CYCLE - Stop when counter completes whole
//! cycle.
//! - EPWM_EMULATION_FREE_RUN - Free run.
//!
//! \return None.
//
//*****************************************************************************
extern void
EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode);
//*****************************************************************************
//
//! Configures ePWM signal with desired frequency & duty
//!
//! \param base is the base address of the EPWM module.
//! \param signalParams is the desired signal parameters.
//!
//! This function configures the ePWM module to generate a signal with
//! desired frequency & duty.
//!
//! \return None.
//
//*****************************************************************************
extern void
EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: eqep.h
//
// TITLE: C28x eQEP driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup eqep_api eQEP
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_eqep.h
//
// TITLE: Definitions for the EQEP registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the EQEP register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QDECCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QCAPCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QPOSCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEINT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPSTS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the REV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPSTROBESEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QMACTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPSRCSEL register
//
//*************************************************************************************************
//*****************************************************************************
//
// Values that can be passed to EQEP_setDecoderConfig() as the config
// parameter.
//
//*****************************************************************************
//
// Operation Mode
//
//
// Resolution
//
//
// Swap QEPA and QEPB
//
//
// Index pulse gating option
//
//*****************************************************************************
//
// Values that can be passed to EQEP_setCompareConfig() as the config
// parameter.
//
//*****************************************************************************
//
// Sync pulse pin
//
//
// Shadow register use
//
//*****************************************************************************
//
// Values that can be passed to EQEP_enableInterrupt(),
// EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the
// intFlags parameter and returned by EQEP_clearInterruptStatus().
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be returned by EQEP_getStatus().
//
//*****************************************************************************
//! Unit position event detected
//! Direction was clockwise on first index event
//! Direction is CW (forward)
//! Direction was CW on index
//! Capture timer overflow
//! Direction changed between position capture events
//! First index pulse occurred
//! Position counter error
//*****************************************************************************
//
// Values that can be passed to EQEP_setLatchMode() as the latchMode parameter.
//
//*****************************************************************************
//
// Position counter latch event
//
//
// Strobe position counter latch event
//
//! On rising edge of strobe
//! On rising edge when clockwise, on falling when counter clockwise
//
// Index position counter latch event
//
//*****************************************************************************
//
// Values that can be passed to EQEP_setPositionInitMode() as the initMode
// parameter.
//
//*****************************************************************************
//
// Strobe events
//
//! On rising edge of strobe
//! On rising edge when clockwise, on falling when counter clockwise
//
// Index events
//
//*****************************************************************************
//
//! Values that can be passed to EQEP_setPositionCounterConfig() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! Reset position on index pulse
EQEP_POSITION_RESET_IDX = 0x0000,
//! Reset position on maximum position
EQEP_POSITION_RESET_MAX_POS = 0x1000,
//! Reset position on the first index pulse
EQEP_POSITION_RESET_1ST_IDX = 0x2000,
//! Reset position on a unit time event
EQEP_POSITION_RESET_UNIT_TIME_OUT = 0x3000
} EQEP_PositionResetMode;
//*****************************************************************************
//
//! Values that can be passed to EQEP_setCaptureConfig() as the \e capPrescale
//! parameter. CAPCLK is the capture timer clock frequency.
//
//*****************************************************************************
typedef enum
{
EQEP_CAPTURE_CLK_DIV_1 = 0x00, //!< CAPCLK = SYSCLKOUT/1
EQEP_CAPTURE_CLK_DIV_2 = 0x10, //!< CAPCLK = SYSCLKOUT/2
EQEP_CAPTURE_CLK_DIV_4 = 0x20, //!< CAPCLK = SYSCLKOUT/4
EQEP_CAPTURE_CLK_DIV_8 = 0x30, //!< CAPCLK = SYSCLKOUT/8
EQEP_CAPTURE_CLK_DIV_16 = 0x40, //!< CAPCLK = SYSCLKOUT/16
EQEP_CAPTURE_CLK_DIV_32 = 0x50, //!< CAPCLK = SYSCLKOUT/32
EQEP_CAPTURE_CLK_DIV_64 = 0x60, //!< CAPCLK = SYSCLKOUT/64
EQEP_CAPTURE_CLK_DIV_128 = 0x70 //!< CAPCLK = SYSCLKOUT/128
} EQEP_CAPCLKPrescale;
//*****************************************************************************
//
//! Values that can be passed to EQEP_setCaptureConfig() as the \e evntPrescale
//! parameter. UPEVNT is the unit position event frequency.
//
//*****************************************************************************
typedef enum
{
EQEP_UNIT_POS_EVNT_DIV_1, //!< UPEVNT = QCLK/1
EQEP_UNIT_POS_EVNT_DIV_2, //!< UPEVNT = QCLK/2
EQEP_UNIT_POS_EVNT_DIV_4, //!< UPEVNT = QCLK/4
EQEP_UNIT_POS_EVNT_DIV_8, //!< UPEVNT = QCLK/8
EQEP_UNIT_POS_EVNT_DIV_16, //!< UPEVNT = QCLK/16
EQEP_UNIT_POS_EVNT_DIV_32, //!< UPEVNT = QCLK/32
EQEP_UNIT_POS_EVNT_DIV_64, //!< UPEVNT = QCLK/64
EQEP_UNIT_POS_EVNT_DIV_128, //!< UPEVNT = QCLK/128
EQEP_UNIT_POS_EVNT_DIV_256, //!< UPEVNT = QCLK/256
EQEP_UNIT_POS_EVNT_DIV_512, //!< UPEVNT = QCLK/512
EQEP_UNIT_POS_EVNT_DIV_1024, //!< UPEVNT = QCLK/1024
EQEP_UNIT_POS_EVNT_DIV_2048 //!< UPEVNT = QCLK/2048
} EQEP_UPEVNTPrescale;
//*****************************************************************************
//
//! Values that can be passed to EQEP_setStrobeSource() as the \e strobeSrc
//! parameter.
//
//*****************************************************************************
typedef enum
{
EQEP_STROBE_FROM_GPIO = 0, //!< Strobe signal comes from GPIO
EQEP_STROBE_OR_ADCSOCA = 2, //!< Strobe signal is OR'd with ADCSOCA
EQEP_STROBE_OR_ADCSOCB = 3 //!< Strobe signal is OR'd with ADCSOCB
} EQEP_StrobeSource;
//*****************************************************************************
//
//! Values that can be passed to EQEP_setQMAModuleMode() as the \e qmaMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
EQEP_QMA_MODE_BYPASS, //!< QMA module is bypassed
EQEP_QMA_MODE_1, //!< QMA mode-1 operation is selected
EQEP_QMA_MODE_2 //!< QMA mode-2 operation is selected
} EQEP_QMAMode;
//*****************************************************************************
//
//! Possible values of sources for QEPA,QEPB and Index signal which are passed
//! as a structure to EQEP_selectSource() as \e sourceConfig
//
//*****************************************************************************
typedef enum
{
EQEP_SOURCE_DEVICE_PIN = 0x0000U, //!< signal comes from Device Pin
EQEP_SOURCE_CMPSS1 = 0x0001U, //!< signal comes from CMPSS1
EQEP_SOURCE_CMPSS2 = 0x0002U, //!< signal comes from CMPSS2
EQEP_SOURCE_CMPSS3 = 0x0003U, //!< signal comes from CMPSS3
EQEP_SOURCE_CMPSS4 = 0x0004U, //!< signal comes from CMPSS4
EQEP_SOURCE_ZERO = 0x0008U, //!< signal tied to zero
EQEP_SOURCE_PWMXBAR1 = 0x0009U, //!< signal comes from PWMXBAR1
EQEP_SOURCE_PWMXBAR2 = 0x000AU, //!< signal comes from PWMXBAR2
EQEP_SOURCE_PWMXBAR3 = 0x000BU, //!< signal comes from PWMXBAR3
EQEP_SOURCE_PWMXBAR4 = 0x000CU, //!< signal comes from PWMXBAR4
EQEP_SOURCE_PWMXBAR5 = 0x000DU, //!< signal comes from PWMXBAR5
EQEP_SOURCE_PWMXBAR6 = 0x000EU, //!< signal comes from PWMXBAR6
EQEP_SOURCE_PWMXBAR7 = 0x000FU, //!< signal comes from PWMXBAR7
} EQEP_Source;
//*****************************************************************************
//
//! Structure to be passed to EQEP_selectSource() as \e sourceConfig
//
//*****************************************************************************
typedef struct {
EQEP_Source sourceA;
EQEP_Source sourceB;
EQEP_Source sourceIndex;
}EQEP_SourceSelect;
//*****************************************************************************
//
//! Values that can be passed to EQEP_setEmulationMode() as the \e emuMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
EQEP_EMULATIONMODE_STOPIMMEDIATELY, //!< Counters stop immediately
EQEP_EMULATIONMODE_STOPATROLLOVER, //!< Counters stop at period rollover
EQEP_EMULATIONMODE_RUNFREE //!< Counter unaffected by suspend
}EQEP_EmulationMode;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an eQEP base address.
//!
//! \param base specifies the eQEP module base address.
//!
//! This function determines if a eQEP module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the eQEP module.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables operation of the enhanced quadrature encoder pulse
//! (eQEP) module. The module must be configured before it is enabled.
//!
//! \sa EQEP_setConfig()
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the eQEP module.
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x8U;
}
//*****************************************************************************
//
//! Disables the eQEP module.
//!
//! \param base is the base address of the enhanced quadrature encoder pulse
//! (eQEP) module
//!
//! This function disables operation of the eQEP module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the eQEP module.
//
(*((volatile uint16_t *)(base + 0x15U))) &= ~(0x8U);
}
//*****************************************************************************
//
//! Configures eQEP module's quadrature decoder unit.
//!
//! \param base is the base address of the eQEP module.
//! \param config is the configuration for the eQEP module decoder unit.
//!
//! This function configures the operation of the eQEP module's quadrature
//! decoder unit. The \e config parameter provides the configuration
//! of the decoder and is the logical OR of several values:
//!
//! - \b EQEP_CONFIG_2X_RESOLUTION or \b EQEP_CONFIG_1X_RESOLUTION specify
//! if both rising and falling edges should be counted or just rising edges.
//! - \b EQEP_CONFIG_QUADRATURE, \b EQEP_CONFIG_CLOCK_DIR,
//! \b EQEP_CONFIG_UP_COUNT, or \b EQEP_CONFIG_DOWN_COUNT specify if
//! quadrature signals are being provided on QEPA and QEPB, if a direction
//! signal and a clock are being provided, or if the direction should be
//! hard-wired for a single direction with QEPA used for input.
//! - \b EQEP_CONFIG_NO_SWAP or \b EQEP_CONFIG_SWAP to specify if the
//! signals provided on QEPA and QEPB should be swapped before being
//! processed.
//! - \b EQEP_CONFIG_IGATE_DISABLE or \b EQEP_CONFIG_IGATE_ENABLE to specify
//! if the gating of the index pulse should be enabled or disabled
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setDecoderConfig(uint32_t base, uint16_t config)
{
//
// Check the arguments.
//
;
//
// Write the new decoder configuration to the hardware.
//
(*((volatile uint16_t *)(base + 0x14U))) = ((*((volatile uint16_t *)(base + 0x14U))) &
~(0x400U |
0x800U |
0xC000U |
0x200U)) | config;
}
//*****************************************************************************
//
//! Configures eQEP module position counter unit.
//!
//! \param base is the base address of the eQEP module.
//! \param mode is the configuration for the eQEP module position counter.
//! \param maxPosition specifies the maximum position value.
//!
//! This function configures the operation of the eQEP module position
//! counter. The \e mode parameter determines the event on which the position
//! counter gets reset. It should be passed one of the following values:
//! \b EQEP_POSITION_RESET_IDX, \b EQEP_POSITION_RESET_MAX_POS,
//! \b EQEP_POSITION_RESET_1ST_IDX, or \b EQEP_POSITION_RESET_UNIT_TIME_OUT.
//!
//! \e maxPosition is the maximum value of the position counter and is
//! the value used to reset the position capture when moving in the reverse
//! (negative) direction.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode,
uint32_t maxPosition)
{
//
// Check the arguments.
//
;
//
// Write the position counter reset configuration to the hardware.
//
(*((volatile uint16_t *)(base + 0x15U))) = ((*((volatile uint16_t *)(base + 0x15U))) &
~0x3000U) | (uint16_t)mode;
//
// Set the maximum position.
//
(*((volatile uint32_t *)(base + 0x4U))) = maxPosition;
}
//*****************************************************************************
//
//! Gets the current encoder position.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the current position of the encoder. Depending upon
//! the configuration of the encoder, and the incident of an index pulse, this
//! value may or may not contain the expected data (that is, if in reset on
//! index mode, if an index pulse has not been encountered, the position
//! counter is not yet aligned with the index pulse).
//!
//! \return The current position of the encoder.
//
//*****************************************************************************
static inline uint32_t
EQEP_getPosition(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current position counter.
//
return((*((volatile uint32_t *)(base + 0x0U))));
}
//*****************************************************************************
//
//! Sets the current encoder position.
//!
//! \param base is the base address of the eQEP module.
//! \param position is the new position for the encoder.
//!
//! This function sets the current position of the encoder; the encoder
//! position is then measured relative to this value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setPosition(uint32_t base, uint32_t position)
{
//
// Check the arguments.
//
;
//
// Set the position counter.
//
(*((volatile uint32_t *)(base + 0x0U))) = position;
}
//*****************************************************************************
//
//! Gets the current direction of rotation.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the current direction of rotation. In this case,
//! current means the most recently detected direction of the encoder; it may
//! not be presently moving but this is the direction it last moved before it
//! stopped.
//!
//! \return Returns 1 if moving in the forward direction or -1 if moving in the
//! reverse direction.
//
//*****************************************************************************
static inline int16_t
EQEP_getDirection(uint32_t base)
{
int16_t direction;
//
// Check the arguments.
//
;
//
// Return the direction of rotation.
//
if(((*((volatile uint16_t *)(base + 0x1CU))) & 0x20U) != 0U)
{
direction = 1;
}
else
{
direction = -1;
}
return(direction);
}
//*****************************************************************************
//
//! Enables individual eQEP module interrupt sources.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables eQEP module interrupt sources. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//! - \b EQEP_INT_QMA_ERROR - QMA error
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableInterrupt(uint32_t base, uint16_t intFlags)
{
//
// Check the arguments.
//
;
//
// Enable the specified interrupts.
//
(*((volatile uint16_t *)(base + 0x18U))) |= intFlags;
}
//*****************************************************************************
//
//! Disables individual eQEP module interrupt sources.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables eQEP module interrupt sources. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//! - \b EQEP_INT_QMA_ERROR - QMA error
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableInterrupt(uint32_t base, uint16_t intFlags)
{
//
// Check the arguments.
//
;
//
// Disable the specified interrupts.
//
(*((volatile uint16_t *)(base + 0x18U))) &= ~(intFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the interrupt status for the eQEP module
//! module.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! the following values:
//! - \b EQEP_INT_GLOBAL - Global interrupt flag
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//! - \b EQEP_INT_QMA_ERROR - QMA error
//
//*****************************************************************************
static inline uint16_t
EQEP_getInterruptStatus(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0x19U))));
}
//*****************************************************************************
//
//! Clears eQEP module interrupt sources.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears eQEP module interrupt flags. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_GLOBAL - Global interrupt flag
//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error
//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error
//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change
//! - \b EQEP_INT_WATCHDOG - Watchdog time-out
//! - \b EQEP_INT_UNDERFLOW - Position counter underflow
//! - \b EQEP_INT_OVERFLOW - Position counter overflow
//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready
//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match
//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch
//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch
//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out
//! - \b EQEP_INT_QMA_ERROR - QMA error
//!
//! Note that the \b EQEP_INT_GLOBAL value is the global interrupt flag. In
//! order to get any further eQEP interrupts, this flag must be cleared.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags)
{
//
// Check the arguments.
//
;
//
// Clear the requested interrupt sources.
//
(*((volatile uint16_t *)(base + 0x1AU))) = intFlags;
}
//*****************************************************************************
//
//! Forces individual eQEP module interrupts.
//!
//! \param base is the base address of the eQEP module.
//! \param intFlags is a bit mask of the interrupt sources to be forced.
//!
//! This function forces eQEP module interrupt flags. The \e intFlags
//! parameter can be any of the following values OR'd together:
//! - \b EQEP_INT_POS_CNT_ERROR
//! - \b EQEP_INT_PHASE_ERROR
//! - \b EQEP_INT_DIR_CHANGE
//! - \b EQEP_INT_WATCHDOG
//! - \b EQEP_INT_UNDERFLOW
//! - \b EQEP_INT_OVERFLOW
//! - \b EQEP_INT_POS_COMP_READY
//! - \b EQEP_INT_POS_COMP_MATCH
//! - \b EQEP_INT_STROBE_EVNT_LATCH
//! - \b EQEP_INT_INDEX_EVNT_LATCH
//! - \b EQEP_INT_UNIT_TIME_OUT
//! - \b EQEP_INT_QMA_ERROR
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_forceInterrupt(uint32_t base, uint16_t intFlags)
{
//
// Check the arguments.
//
;
//
// Force the specified interrupts.
//
(*((volatile uint16_t *)(base + 0x1BU))) |= intFlags;
}
//*****************************************************************************
//
//! Gets the encoder error indicator.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the error indicator for the eQEP module. It is an
//! error for both of the signals of the quadrature input to change at the same
//! time.
//!
//! \return Returns \b true if an error has occurred and \b false otherwise.
//
//*****************************************************************************
static inline _Bool
EQEP_getError(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the error indicator.
//
return(((*((volatile uint16_t *)(base + 0x19U))) & 0x4U) != 0U);
}
//*****************************************************************************
//
//! Returns content of the eQEP module status register
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the contents of the status register. The value it
//! returns is an OR of the following values:
//!
//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected
//! - \b EQEP_STS_DIR_ON_1ST_IDX - If set, clockwise rotation (forward
//! movement) occurred on the first index event
//! - \b EQEP_STS_DIR_FLAG - If set, movement is clockwise rotation
//! - \b EQEP_STS_DIR_LATCH - If set, clockwise rotation occurred on last
//! index event marker
//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer
//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position
//! capture events
//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index
//! pulse
//! - \b EQEP_STS_POS_CNT_ERROR - Position counter error occurred
//!
//! \return Returns the value of the QEP status register.
//
//*****************************************************************************
static inline uint16_t
EQEP_getStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the status register.
//
return((*((volatile uint16_t *)(base + 0x1CU))) & 0x00FFU);
}
//*****************************************************************************
//
//! Clears selected fields of the eQEP module status register
//!
//! \param base is the base address of the eQEP module.
//! \param statusFlags is the bit mask of the status flags to be cleared.
//!
//! This function clears the status register fields indicated by
//! \e statusFlags. The \e statusFlags parameter is the logical OR of any of
//! the following:
//!
//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected
//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer
//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position
//! capture events
//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index
//! pulse
//!
//! \note Only the above status fields can be cleared. All others are
//! read-only, non-sticky fields.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_clearStatus(uint32_t base, uint16_t statusFlags)
{
//
// Check the arguments.
//
;
//
// Clear the requested interrupt sources.
//
(*((volatile uint16_t *)(base + 0x1CU))) = statusFlags;
}
//*****************************************************************************
//
//! Configures eQEP module edge-capture unit.
//!
//! \param base is the base address of the eQEP module.
//! \param capPrescale is the prescaler setting of the eQEP capture timer clk.
//! \param evntPrescale is the prescaler setting of the unit position event
//! frequency.
//!
//! This function configures the operation of the eQEP module edge-capture
//! unit. The \e capPrescale parameter provides the configuration of the eQEP
//! capture timer clock rate. It determines by which power of 2 between 1 and
//! 128 inclusive SYSCLKOUT is divided. The macros for this parameter are in
//! the format of EQEP_CAPTURE_CLK_DIV_X, where X is the divide value. For
//! example, \b EQEP_CAPTURE_CLK_DIV_32 will give a capture timer clock
//! frequency that is SYSCLKOUT/32.
//!
//! The \e evntPrescale parameter determines how frequently a unit position
//! event occurs. The macro that can be passed this parameter is in the format
//! EQEP_UNIT_POS_EVNT_DIV_X, where X is the number of quadrature clock
//! periods between unit position events. For example,
//! \b EQEP_UNIT_POS_EVNT_DIV_16 will result in a unit position event
//! frequency of QCLK/16.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale,
EQEP_UPEVNTPrescale evntPrescale)
{
//
// Check the arguments.
//
;
//
// Write new prescaler configurations to the appropriate registers.
//
(*((volatile uint16_t *)(base + 0x16U))) =
((*((volatile uint16_t *)(base + 0x16U))) &
~(0xFU | 0x70U)) |
((uint16_t)evntPrescale | (uint16_t)capPrescale);
}
//*****************************************************************************
//
//! Enables the eQEP module edge-capture unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables operation of the eQEP module's edge-capture unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableCapture(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable edge capture.
//
(*((volatile uint16_t *)(base + 0x16U))) |= 0x8000U;
}
//*****************************************************************************
//
//! Disables the eQEP module edge-capture unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's edge-capture unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableCapture(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable edge capture.
//
(*((volatile uint16_t *)(base + 0x16U))) &= ~(0x8000U);
}
//*****************************************************************************
//
//! Gets the encoder capture period.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the period count value between the last successive
//! eQEP position events.
//!
//! \return The period count value between the last successive position events.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCapturePeriod(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the capture period.
//
return((*((volatile uint16_t *)(base + 0x1EU))));
}
//*****************************************************************************
//
//! Gets the encoder capture timer value.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the time base for the edge capture unit.
//!
//! \return The capture timer value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCaptureTimer(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the capture timer value.
//
return((*((volatile uint16_t *)(base + 0x1DU))));
}
//*****************************************************************************
//
//! Enables the eQEP module position-compare unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables operation of the eQEP module's position-compare unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableCompare(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable position compare.
//
(*((volatile uint16_t *)(base + 0x17U))) |= 0x1000U;
}
//*****************************************************************************
//
//! Disables the eQEP module position-compare unit.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's position-compare
//! unit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableCompare(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable position compare.
//
(*((volatile uint16_t *)(base + 0x17U))) &= ~(0x1000U);
}
//*****************************************************************************
//
//! Configures the position-compare unit's sync output pulse width.
//!
//! \param base is the base address of the eQEP module.
//! \param cycles is the width of the pulse that can be generated on a
//! position-compare event. It is in units of 4 SYSCLKOUT cycles.
//!
//! This function configures the width of the sync output pulse. The width of
//! the pulse will be \e cycles * 4 * the width of a SYSCLKOUT cycle. The
//! maximum width is 4096 * 4 * SYSCLKOUT cycles.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles)
{
//
// Check the arguments.
//
;
;
//
// Set the pulse width.
//
(*((volatile uint16_t *)(base + 0x17U))) = ((*((volatile uint16_t *)(base + 0x17U))) &
~(uint16_t)0xFFFU) |
(cycles - 1U);
}
//*****************************************************************************
//
//! Loads the eQEP module unit timer period as number of SYSCLK cycles.
//!
//! \param base is the base address of the eQEP module.
//! \param period is period value at which a unit time-out interrupt is set.
//!
//! This function sets the unit time-out interrupt when it matches the value
//! specified by \e period
//! The unit timer is clocked by SYSCLKOUT
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_loadUnitTimer(uint32_t base, uint32_t period)
{
//
// Check the arguments.
//
;
//
// Set the period of the unit timer.
//
(*((volatile uint32_t *)(base + 0x10U))) = period;
}
//*****************************************************************************
//
//! Enables the eQEP module unit timer.
//!
//! \param base is the base address of the eQEP module.
//! \param period is period value at which a unit time-out interrupt is set.
//!
//! This function enables operation of the eQEP module's peripheral unit timer.
//! The unit timer is clocked by SYSCLKOUT and will set the unit time-out
//! interrupt when it matches the value specified by \e period.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableUnitTimer(uint32_t base, uint32_t period)
{
//
// Check the arguments.
//
;
//
// Set the period of the unit timer.
//
(*((volatile uint32_t *)(base + 0x10U))) = period;
//
// Enable peripheral unit timer.
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x2U;
}
//*****************************************************************************
//
//! Disables the eQEP module unit timer.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's peripheral
//! unit timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableUnitTimer(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable peripheral unit timer.
//
(*((volatile uint16_t *)(base + 0x15U))) &= ~(0x2U);
}
//*****************************************************************************
//
//! Enables the eQEP module watchdog timer.
//!
//! \param base is the base address of the eQEP module.
//! \param period is watchdog period value at which a time-out will occur if
//! no quadrature-clock event is detected.
//!
//! This function enables operation of the eQEP module's peripheral watchdog
//! timer.
//!
//! \note When selecting \e period, note that the watchdog timer is clocked
//! from SYSCLKOUT/64.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableWatchdog(uint32_t base, uint16_t period)
{
//
// Check the arguments.
//
;
//
// Set the timeout count for the eQEP peripheral watchdog timer.
//
(*((volatile uint16_t *)(base + 0x13U))) = period;
//
// Enable peripheral watchdog.
//
(*((volatile uint16_t *)(base + 0x15U))) |= 0x1U;
}
//*****************************************************************************
//
//! Disables the eQEP module watchdog timer.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables operation of the eQEP module's peripheral watchdog
//! timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableWatchdog(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable peripheral watchdog.
//
(*((volatile uint16_t *)(base + 0x15U))) &= ~(0x1U);
}
//*****************************************************************************
//
//! Sets the eQEP module watchdog timer value.
//!
//! \param base is the base address of the eQEP module.
//! \param value is the value to be written to the watchdog timer.
//!
//! This function sets the eQEP module's watchdog timer value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value)
{
//
// Check the arguments.
//
;
//
// Write the value to the watchdog timer register.
//
(*((volatile uint16_t *)(base + 0x12U))) = value;
}
//*****************************************************************************
//
//! Gets the eQEP module watchdog timer value.
//!
//! \param base is the base address of the eQEP module.
//!
//! \return Returns the current watchdog timer value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getWatchdogTimerValue(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read the value from the watchdog timer register.
//
return((*((volatile uint16_t *)(base + 0x12U))));
}
//*****************************************************************************
//
//! Configures the mode in which the position counter is initialized.
//!
//! \param base is the base address of the eQEP module.
//! \param initMode is the configuration for initializing the position count.
//! See below for a description of this parameter.
//!
//! This function configures the events on which the position count can be
//! initialized. The \e initMode parameter provides the mode as either
//! \b EQEP_INIT_DO_NOTHING (no action configured) or one of the following
//! strobe events, index events, or a logical OR of both a strobe event and an
//! index event.
//!
//! - \b EQEP_INIT_RISING_STROBE or \b EQEP_INIT_EDGE_DIR_STROBE specify
//! which strobe event will initialize the position counter.
//! - \b EQEP_INIT_RISING_INDEX or \b EQEP_INIT_FALLING_INDEX specify
//! which index event will initialize the position counter.
//!
//! Use EQEP_setSWPositionInit() to cause a software initialization and
//! EQEP_setInitialPosition() to set the value that gets loaded into the
//! position counter upon initialization.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setPositionInitMode(uint32_t base, uint16_t initMode)
{
//
// Check the arguments.
//
;
//
// Set the init mode in the QEP Control register.
//
(*((volatile uint16_t *)(base + 0x15U))) = ((*((volatile uint16_t *)(base + 0x15U))) &
~(0x300U | 0xC00U)) |
initMode;
}
//*****************************************************************************
//
//! Sets the software initialization of the encoder position counter.
//!
//! \param base is the base address of the eQEP module.
//! \param initialize is a flag to specify if software initialization of the
//! position counter is enabled.
//!
//! This function does a software initialization of the position counter when
//! the \e initialize parameter is \b true. When \b false, the QEPCTL[SWI] bit
//! is cleared and no action is taken.
//!
//! The init value to be loaded into the position counter can be set with
//! EQEP_setInitialPosition(). Additional initialization causes can be
//! configured with EQEP_setPositionInitMode().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setSWPositionInit(uint32_t base, _Bool initialize)
{
//
// Check the arguments.
//
;
//
// Set or clear the software initialization bit.
//
if(initialize)
{
(*((volatile uint16_t *)(base + 0x15U))) |= 0x80U;
}
else
{
(*((volatile uint16_t *)(base + 0x15U))) &= ~0x80U;
}
}
//*****************************************************************************
//
//! Sets the init value for the encoder position counter.
//!
//! \param base is the base address of the eQEP module.
//! \param position is the value to be written to the position counter upon.
//! initialization.
//!
//! This function sets the init value for position of the encoder. See
//! EQEP_setPositionInitMode() to set the initialization cause or
//! EQEP_setSWPositionInit() to cause a software initialization.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setInitialPosition(uint32_t base, uint32_t position)
{
//
// Check the arguments.
//
;
//
// Write position to position counter init register
//
(*((volatile uint32_t *)(base + 0x2U))) = position;
}
//*****************************************************************************
//
//! Configures the quadrature modes in which the position count can be latched.
//!
//! \param base is the base address of the eQEP module.
//! \param latchMode is the configuration for latching of the position count
//! and several other registers. See below for a description of this
//! parameter.
//!
//! This function configures the events on which the position count and several
//! other registers can be latched. The \e latchMode parameter provides the
//! mode as the logical OR of several values.
//!
//! - \b EQEP_LATCH_CNT_READ_BY_CPU or \b EQEP_LATCH_UNIT_TIME_OUT specify
//! the event that latches the position counter. This latch register can be
//! read using EQEP_getPositionLatch(). The capture timer and capture
//! period are also latched based on this setting, and can be read using
//! EQEP_getCaptureTimerLatch() and EQEP_getCapturePeriodLatch().
//! - \b EQEP_LATCH_RISING_STROBE or \b EQEP_LATCH_EDGE_DIR_STROBE
//! specify which strobe event will latch the position counter into the
//! strobe position latch register. This register can be read with
//! EQEP_getStrobePositionLatch().
//! - \b EQEP_LATCH_RISING_INDEX, \b EQEP_LATCH_FALLING_INDEX, or
//! \b EQEP_LATCH_SW_INDEX_MARKER specify which index event will latch the
//! position counter into the index position latch register. This register
//! can be read with EQEP_getIndexPositionLatch().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setLatchMode(uint32_t base, uint32_t latchMode)
{
//
// Check the arguments.
//
;
//
// Set the latch mode in the QEP Control register.
//
(*((volatile uint16_t *)(base + 0x15U))) = ((*((volatile uint16_t *)(base + 0x15U))) &
~(0x4U | 0x30U |
0x40U)) | latchMode;
}
//*****************************************************************************
//
//! Gets the encoder position that was latched on an index event.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the index position latch register. The
//! position counter is latched into this register on either a rising index
//! edge, a falling index edge, or a software index marker. This is configured
//! using EQEP_setLatchMode().
//!
//! \return The position count latched on an index event.
//
//*****************************************************************************
static inline uint32_t
EQEP_getIndexPositionLatch(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current position counter.
//
return((*((volatile uint32_t *)(base + 0x8U))));
}
//*****************************************************************************
//
//! Gets the encoder position that was latched on a strobe event.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the strobe position latch register. The
//! position counter can be configured to be latched into this register on
//! rising strobe edges only or on rising strobe edges while moving clockwise
//! and falling strobe edges while moving counter-clockwise. This is configured
//! using EQEP_setLatchMode().
//!
//! \return The position count latched on a strobe event.
//
//*****************************************************************************
static inline uint32_t
EQEP_getStrobePositionLatch(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current position counter.
//
return((*((volatile uint32_t *)(base + 0xAU))));
}
//*****************************************************************************
//
//! Gets the encoder position that was latched on a unit time-out event.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the position latch register. The
//! position counter is latched into this register either on a unit time-out
//! event.
//!
//! \return The position count latch register value.
//
//*****************************************************************************
static inline uint32_t
EQEP_getPositionLatch(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current position counter.
//
return((*((volatile uint32_t *)(base + 0xCU))));
}
//*****************************************************************************
//
//! Gets the encoder capture timer latch.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the capture timer latch register. The
//! capture timer value is latched into this register either on a unit time-out
//! event or upon the CPU reading the eQEP position counter. This is configured
//! using EQEP_setLatchMode().
//!
//! \return The edge-capture timer latch value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCaptureTimerLatch(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current position counter.
//
return((*((volatile uint16_t *)(base + 0x1FU))));
}
//*****************************************************************************
//
//! Gets the encoder capture period latch.
//!
//! \param base is the base address of the eQEP module.
//!
//! This function returns the value in the capture period latch register. The
//! capture period value is latched into this register either on a unit
//! time-out event or upon the CPU reading the eQEP position counter. This is
//! configured using EQEP_setLatchMode().
//!
//! \return The edge-capture period latch value.
//
//*****************************************************************************
static inline uint16_t
EQEP_getCapturePeriodLatch(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current position counter.
//
return((*((volatile uint16_t *)(base + 0x20U))));
}
//*****************************************************************************
//
//! Set the quadrature mode adapter (QMA) module mode
//!
//! \param base is the base address of the eQEP module.
//! \param qmaMode is the mode in which the QMA module will operate.
//!
//! This function sets the quadrature mode adapter module mode. The possible
//! modes are passed to the function through the \e qmaMode parameter which
//! can take the values EQEP_QMA_MODE_BYPASS, EQEP_QMA_MODE_1, or
//! EQEP_QMA_MODE_2.
//!
//! To use the QMA module, you must first put the eQEP module into
//! direction-count mode (\b EQEP_CONFIG_CLOCK_DIR) using EQEP_setConfig().
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setQMAModuleMode(uint32_t base, EQEP_QMAMode qmaMode)
{
//
// Check the arguments.
//
;
//
// Write the QMA module mode into the appropriate register.
//
(*((volatile uint16_t *)(base + 0x34U))) =
((*((volatile uint16_t *)(base + 0x34U))) & ~0x7U) |
(uint16_t)qmaMode;
}
//*****************************************************************************
//
//! Set the strobe input source of the eQEP module.
//!
//! \param base is the base address of the eQEP module.
//! \param strobeSrc is the source of the strobe signal.
//!
//! This function sets the source of the eQEP module's strobe signal. The
//! possible values of the \e strobeSrc parameter are
//! - \b EQEP_STROBE_FROM_GPIO - The strobe is used as-is after passing through
//! the polarity select logic.
//! - \b EQEP_STROBE_OR_ADCSOCA - The strobe is OR'd with the ADCSOCA signal
//! after passing through the polarity select logic.
//! - \b EQEP_STROBE_OR_ADCSOCB - The strobe is OR'd with the ADCSOCB signal
//! after passing through the polarity select logic.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setStrobeSource(uint32_t base, EQEP_StrobeSource strobeSrc)
{
//
// Check the arguments.
//
;
//
// Write the strobe source selection into the appropriate register.
//
(*((volatile uint16_t *)(base + 0x32U))) =
((*((volatile uint16_t *)(base + 0x32U))) & ~0x3U) |
(uint16_t)strobeSrc;
}
//*****************************************************************************
//
//! Enables the index direction enhancement mode of the eQEP module
//!
//! \param base is the base address of the eQEP module.
//!
//! This function enables the enhancement mode for direction change
//! during Index event
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_enableDirectionChangeDuringIndex(uint32_t base)
{
//
// Check the arguments.
//
;
//
//Sets the index direction enhancement bit
//
(*((volatile uint16_t *)(base + 0x14U))) |= 0x1U;
}
//*****************************************************************************
//
//! Disables the index direction enhancement mode of the eQEP module
//!
//! \param base is the base address of the eQEP module.
//!
//! This function disables the enhancement mode for direction change
//! during Index event
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_disableDirectionChangeDuringIndex(uint32_t base)
{
//
// Check the arguments.
//
;
//
//Clears the index direction enhancement bit
//
(*((volatile uint16_t *)(base + 0x14U))) &= ~(0x1U);
}
//*****************************************************************************
//
//! Selects the source for eQEPA/B/I signals
//!
//! \param base is the base address of the enhanced quadrature encoder pulse
//! (eQEP) module
//! \param sourceConfig is the structure that contains source configuration
//!
//! This function configures the sources for QEPA,QEPB and Index of eQEP module
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_selectSource(uint32_t base, EQEP_SourceSelect sourceConfig )
{
//
// Check the arguments.
//
;
//
// Selecting sources for eQEP signals
//
(*((volatile uint32_t *)(base + 0x36U))) =
((*((volatile uint32_t *)(base + 0x36U))) & ~(0xFU |
0xF0U | 0xF00U)) |
((uint32_t)((uint32_t)(sourceConfig.sourceA) <<
0U) |
(uint32_t)((uint32_t)(sourceConfig.sourceB) <<
4U) |
(uint32_t)((uint32_t)(sourceConfig.sourceIndex) <<
8U));
}
//*****************************************************************************
//
//! Set the emulation mode of the eQEP module.
//!
//! \param base is the base address of the eQEP module.
//! \param emuMode is the mode operation upon an emulation suspend.
//!
//! This function sets the eQEP module's emulation mode. This mode determines
//! how the timers are affected by an emulation suspend. Valid values for the
//! \e emuMode parameter are the following:
//!
//! - \b EQEP_EMULATIONMODE_STOPIMMEDIATELY - The position counter, watchdog
//! counter, unit timer, and capture timer all stop immediately.
//! - \b EQEP_EMULATIONMODE_STOPATROLLOVER - The position counter, watchdog
//! counter, unit timer all count until period rollover. The capture timer
//! counts until the next unit period event.
//! - \b EQEP_EMULATIONMODE_RUNFREE - The position counter, watchdog counter,
//! unit timer, and capture timer are all unaffected by an emulation suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode)
{
//
// Check the arguments.
//
;
//
// Write the emulation mode to the FREE_SOFT bits.
//
(*((volatile uint16_t *)(base + 0x15U))) =
((*((volatile uint16_t *)(base + 0x15U))) & ~0xC000U) |
((uint16_t)emuMode << 14U);
}
//*****************************************************************************
//
//! Configures eQEP module position-compare unit.
//!
//! \param base is the base address of the eQEP module.
//! \param config is the configuration for the eQEP module
//! position-compare unit. See below for a description of this parameter.
//! \param compareValue is the value to which the position count value is
//! compared for a position-compare event.
//! \param cycles is the width of the pulse that can be generated on a
//! position-compare event. It is in units of 4 SYSCLKOUT cycles.
//!
//! This function configures the operation of the eQEP module position-compare
//! unit. The \e config parameter provides the configuration of the
//! position-compare unit and is the logical OR of several values:
//!
//! - \b EQEP_COMPARE_NO_SYNC_OUT, \b EQEP_COMPARE_IDX_SYNC_OUT, or
//! \b EQEP_COMPARE_STROBE_SYNC_OUT specify if there is a sync output pulse
//! and which pin should be used.
//! - \b EQEP_COMPARE_NO_SHADOW, \b EQEP_COMPARE_LOAD_ON_ZERO, or
//! \b EQEP_COMPARE_LOAD_ON_MATCH specify if a shadow is enabled and when
//! should the load should occur--QPOSCNT = 0 or QPOSCNT = QPOSCOMP.
//!
//! The \e cycles is used to select the width of the sync output pulse. The
//! width of the resulting pulse will be \e cycles * 4 * the width of a
//! SYSCLKOUT cycle. The maximum width is 4096 * 4 * SYSCLKOUT cycles.
//!
//! \note You can set the sync pulse width independently using the
//! EQEP_setComparePulseWidth() function.
//!
//! \return None.
//
//*****************************************************************************
extern void
EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue,
uint16_t cycles);
//*****************************************************************************
//
//! Sets the polarity of the eQEP module's input signals.
//!
//! \param base is the base address of the eQEP module.
//! \param invertQEPA is the flag to negate the QEPA input.
//! \param invertQEPB is the flag to negate the QEPA input.
//! \param invertIndex is the flag to negate the index input.
//! \param invertStrobe is the flag to negate the strobe input.
//!
//! This function configures the polarity of the inputs to the eQEP module. To
//! negate the polarity of any of the input signals, pass \b true into its
//! corresponding parameter in this function. Pass \b false to leave it as-is.
//!
//! \return None.
//
//*****************************************************************************
extern void
EQEP_setInputPolarity(uint32_t base, _Bool invertQEPA, _Bool invertQEPB,
_Bool invertIndex, _Bool invertStrobe);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: erad.h
//
// TITLE: C28x ERAD driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup erad_api ERAD
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_erad.h
//
// TITLE: Definitions for the ERAD registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the ERAD register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_EVENT_STAT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_HALT_STAT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_ENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_CTM_RESET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_NMI_CTL register
//
//*************************************************************************************************
// enable
// enable
// enable
// enable
// enable
// enable
// enable
// enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_OWNER register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_EVENT_AND_MASK register
//
//*************************************************************************************************
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_EVENT_OR_MASK register
//
//*************************************************************************************************
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask1
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask2
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask3
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
// Event Mask4
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_AND_EVENT_INT_MASK register
//
//*************************************************************************************************
// AND events
// AND events
// AND events
// AND events
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLBL_OR_EVENT_INT_MASK register
//
//*************************************************************************************************
// events
// events
// events
// events
//*************************************************************************************************
//
// The following are defines for the bit fields in the HWBP_CLEAR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HWBP_CNTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HWBP_STATUS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_CNTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_STATUS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_INPUT_SEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_CLEAR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_INPUT_SEL_2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTM_INPUT_COND register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CRC_GLOBAL_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CRC_QUALIFIER register
//
//*************************************************************************************************
//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************
//
// Macros for but positions of some register bit fields
//
//
// Macro function for getting the instance number from the base address
//
//
// Macro function to get the HWBP event number from the base address
//
//*****************************************************************************
//
//! Values that can be passed to ERAD_enableModules() or
//! ERAD_disableModules() as \e instances parameter.
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to ERAD_setCounterInputConditioning() as options
//! parameter.
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to ERAD_initModule() as \e owner parameter to
//! set owner of ERAD.
//
//*****************************************************************************
typedef enum
{
ERAD_OWNER_NOOWNER = 0, //!< No owner
ERAD_OWNER_APPLICATION = 1, //!< Application owned
ERAD_OWNER_DEBUGGER = 2 //!< Debugger owned
} ERAD_Owner;
//*****************************************************************************
//
//! Values that can are returned by ERAD_getBusCompStatus() and
//! ERAD_getCounterStatus() to indicate the state of the respective module.
//
//*****************************************************************************
typedef enum
{
ERAD_STATE_IDLE = 0, //!< Module is idle
ERAD_STATE_ENABLED = 2, //!< Module is enabled
ERAD_STATE_COMPLETED = 3 //!< Module was enabled and an event occurred
} ERAD_Status;
//*****************************************************************************
//
//! Values that can be passed to ERAD_configBusComp() and ERAD_profile()
//! as \e config_params.bus_sel parameter to choose which CPU bus to monitor.
//
//*****************************************************************************
typedef enum
{
ERAD_BUSCOMP_BUS_PAB = 0, //!< Use the Program Address Bus
ERAD_BUSCOMP_BUS_VPC = 1, //!< Use the Virtual Program Counter
ERAD_BUSCOMP_BUS_DWAB = 2, //!< Use the Data Write Address Bus
ERAD_BUSCOMP_BUS_DRAB = 3, //!< Use the Data Read Address Bus
ERAD_BUSCOMP_BUS_DWDB = 4, //!< Use the Data Write Data Bus
ERAD_BUSCOMP_BUS_DRDB = 5, //!< Use the Data Read Data Bus
ERAD_BUSCOMP_BUS_VPC_I_ALIGNED = 6, //!< Use VPC Instruction aligned match
ERAD_BUSCOMP_BUS_VPC_R1_ALIGNED = 7, //!< Use VPC R1 aligned match
ERAD_BUSCOMP_BUS_VPC_R2_ALIGNED = 8, //!< Use VPC R2 aligned match
ERAD_BUSCOMP_BUS_VPC_W_ALIGNED = 9, //!< Use VPC Word aligned match
} ERAD_BusComp_Bus_Select;
//*****************************************************************************
//
//! Values that can be passed to ERAD_configBusComp() and ERAD_profile()
//! as \e config_params.comp_mode to indicate what kind of comparison to use
//! for the bus comparators.
//
//*****************************************************************************
typedef enum
{
ERAD_BUSCOMP_COMPMODE_GT = 4, //!< Check for greater than
ERAD_BUSCOMP_COMPMODE_GE = 5, //!< Check for greater than equal to
ERAD_BUSCOMP_COMPMODE_LT = 6, //!< Check for lesser than
ERAD_BUSCOMP_COMPMODE_LE = 7, //!< Check for lesser than equal to
ERAD_BUSCOMP_COMPMODE_EQ = 0 //!< Check for only equality
} ERAD_BusComp_Comp_Mode;
//*****************************************************************************
//
//! Values that can be passed to ERAD_configCounterInStartStopMode()
//! and ERAD_configCounterInCountingMode() as \e config_params.event_mode to
//! indicate whether to count rising edges or the number of CPU clock cycles an
//! is active.
//
//*****************************************************************************
typedef enum
{
ERAD_COUNTER_MODE_ACTIVE = 0, //!< Count number of CPU
//! Cycles event is active for
ERAD_COUNTER_MODE_RISING_EDGE = 1 //!< Count number of Rising
//! Edges of event
} ERAD_Counter_Event_Mode;
//*****************************************************************************
//
//! Values that can be passed to ERAD_configCounterInStartStopMode()
//! and ERAD_configCounterInCountingMode() as \e config_params.event to
//! indicate what event to consider as input. Also may be passed to
//! ERAD_configCounterInStartStopMode() as \e start_event and \e stop_event
//! to indicate start and stop events for the counter.
//
//*****************************************************************************
typedef enum
{
ERAD_EVENT_HWBP1 = 0,
ERAD_EVENT_HWBP2 = 1,
ERAD_EVENT_HWBP3 = 2,
ERAD_EVENT_HWBP4 = 3,
ERAD_EVENT_HWBP5 = 4,
ERAD_EVENT_HWBP6 = 5,
ERAD_EVENT_HWBP7 = 6,
ERAD_EVENT_HWBP8 = 7,
ERAD_EVENT_COUNTER1_EVENT = 8,
ERAD_EVENT_COUNTER2_EVENT = 9,
ERAD_EVENT_COUNTER3_EVENT = 10,
ERAD_EVENT_COUNTER4_EVENT = 11,
ERAD_EVENT_ERAD_OR_MASK0 = 12,
ERAD_EVENT_ERAD_OR_MASK1 = 13,
ERAD_EVENT_ERAD_OR_MASK2 = 14,
ERAD_EVENT_ERAD_OR_MASK3 = 15,
ERAD_EVENT_ERAD_AND_MASK0 = 16,
ERAD_EVENT_ERAD_AND_MASK1 = 17,
ERAD_EVENT_ERAD_AND_MASK2 = 18,
ERAD_EVENT_ERAD_AND_MASK3 = 19,
ERAD_EVENT_PIE_INT1 = 20,
ERAD_EVENT_PIE_INT2 = 21,
ERAD_EVENT_PIE_INT3 = 22,
ERAD_EVENT_PIE_INT4 = 23,
ERAD_EVENT_PIE_INT5 = 24,
ERAD_EVENT_PIE_INT6 = 25,
ERAD_EVENT_PIE_INT7 = 26,
ERAD_EVENT_PIE_INT8 = 27,
ERAD_EVENT_PIE_INT9 = 28,
ERAD_EVENT_PIE_INT10 = 29,
ERAD_EVENT_PIE_INT11 = 30,
ERAD_EVENT_PIE_INT12 = 31,
ERAD_EVENT_TIMER1_TINT0 = 32,
ERAD_EVENT_TIMER1_TINT1 = 33,
ERAD_EVENT_TIMER2_TINT2 = 34,
ERAD_EVENT_DMACH1INT = 35,
ERAD_EVENT_DMACH2INT = 36,
ERAD_EVENT_DMACH3INT = 37,
ERAD_EVENT_DMACH4INT = 38,
ERAD_EVENT_DMACH5INT = 39,
ERAD_EVENT_DMACH6INT = 40,
ERAD_EVENT_FSI_DATA_PKT_RCVD = 41,
ERAD_EVENT_FSI_ERROR_PKT_RCVD = 42,
ERAD_EVENT_FSI_PING_PKT_RCVD = 43,
ERAD_EVENT_FSI_PING_FRAME_TAG_MATCH = 44,
ERAD_EVENT_FSI_DATA_FRAME_TAG_MATCH = 45,
ERAD_EVENT_FSI_ERROR_FRAME_TAG_MATCH = 46,
ERAD_EVENT_FSI_FRAME_DONE = 47,
ERAD_EVENT_ADCAEVTINT = 48,
ERAD_EVENT_ADCCEVTINT = 49,
ERAD_EVENT_MCANA_EVT0 = 50,
ERAD_EVENT_MCANA_EVT1 = 51,
ERAD_EVENT_MCANA_EVT2 = 52,
ERAD_EVENT_ADCSOCA = 53,
ERAD_EVENT_ADCSOCB = 54,
ERAD_EVENT_CLATASKRUN1 = 55,
ERAD_EVENT_CLATASKRUN2 = 56,
ERAD_EVENT_CLATASKRUN3 = 57,
ERAD_EVENT_CLATASKRUN4 = 58,
ERAD_EVENT_CLATASKRUN5 = 59,
ERAD_EVENT_CLATASKRUN6 = 60,
ERAD_EVENT_CLATASKRUN7 = 61,
ERAD_EVENT_CLATASKRUN8 = 62,
ERAD_EVENT_EPWMXBAR_OUT1 = 63,
ERAD_EVENT_EPWMXBAR_OUT2 = 64,
ERAD_EVENT_EPWMXBAR_OUT3 = 65,
ERAD_EVENT_EPWMXBAR_OUT4 = 66,
ERAD_EVENT_EPWMXBAR_OUT5 = 67,
ERAD_EVENT_EPWMXBAR_OUT6 = 68,
ERAD_EVENT_EPWMXBAR_OUT7 = 69,
ERAD_EVENT_EPWMXBAR_OUT8 = 70,
ERAD_EVENT_INPUTXBAR0 = 71,
ERAD_EVENT_INPUTXBAR1 = 72,
ERAD_EVENT_INPUTXBAR2 = 73,
ERAD_EVENT_INPUTXBAR3 = 74,
ERAD_EVENT_INPUTXBAR4 = 75,
ERAD_EVENT_INPUTXBAR5 = 76,
ERAD_EVENT_INPUTXBAR6 = 77,
ERAD_EVENT_INPUTXBAR7 = 78,
ERAD_EVENT_INPUTXBAR8 = 79,
ERAD_EVENT_INPUTXBAR9 = 80,
ERAD_EVENT_INPUTXBAR10 = 81,
ERAD_EVENT_INPUTXBAR11 = 82,
ERAD_EVENT_INPUTXBAR12 = 83,
ERAD_EVENT_INPUTXBAR13 = 84,
ERAD_EVENT_INPUTXBAR14 = 85,
ERAD_EVENT_INPUTXBAR15 = 86,
ERAD_EVENT_CPUx_CPUSTAT = 87,
ERAD_EVENT_CPUx_DBGACK = 88,
ERAD_EVENT_CPUx_NMI = 89,
ERAD_EVENT_CMPSS1_CTRIPH_OR_CTRIPL = 90,
ERAD_EVENT_CMPSS2_CTRIPH_OR_CTRIPL = 91,
ERAD_EVENT_CMPSS3_CTRIPH_OR_CTRIPL = 92,
ERAD_EVENT_CMPSS4_CTRIPH_OR_CTRIPL = 93,
ERAD_EVENT_SD1FLT1_COMPH_OR_COMPL = 98,
ERAD_EVENT_SD1FLT2_COMPH_OR_COMPL = 99,
ERAD_EVENT_SD1FLT3_COMPH_OR_COMPL = 100,
ERAD_EVENT_SD1FLT4_COMPH_OR_COMPL = 101,
ERAD_EVENT_SD2FLT1_COMPH_OR_COMPL = 102,
ERAD_EVENT_SD2FLT2_COMPH_OR_COMPL = 103,
ERAD_EVENT_SD2FLT3_COMPH_OR_COMPL = 104,
ERAD_EVENT_SD2FLT4_COMPH_OR_COMPL = 105,
ERAD_EVENT_ADCAINT1 = 106,
ERAD_EVENT_ADCAINT2 = 107,
ERAD_EVENT_ADCAINT3 = 108,
ERAD_EVENT_ADCAINT4 = 109,
ERAD_EVENT_ADCBINT1 = 110,
ERAD_EVENT_ADCBINT2 = 111,
ERAD_EVENT_ADCBINT3 = 112,
ERAD_EVENT_ADCBINT4 = 113,
ERAD_EVENT_ADCCINT1 = 114,
ERAD_EVENT_ADCCINT2 = 115,
ERAD_EVENT_ADCCINT3 = 116,
ERAD_EVENT_ADCCINT4 = 117,
ERAD_EVENT_HIC_nOE = 122,
ERAD_EVENT_HIC_nWE = 123,
ERAD_EVENT_HIC_nRDY = 124,
ERAD_EVENT_ADCBEVTINT = 125,
ERAD_EVENT_NO_EVENT = 256
} ERAD_Counter_Input_Event;
typedef enum
{
ERAD_AND_MASK1 = 0,
ERAD_AND_MASK2 = 1,
ERAD_AND_MASK3 = 2,
ERAD_AND_MASK4 = 3,
ERAD_OR_MASK1 = 4,
ERAD_OR_MASK2 = 5,
ERAD_OR_MASK3 = 6,
ERAD_OR_MASK4 = 7
} ERAD_Mask;
//*****************************************************************************
//
//! Values that can be passed to ERAD_setCRCQualifier() as the \e qualifier
//! paramter to specify which events to set as the qualifier for the CRC unit.
//
//*****************************************************************************
typedef enum
{
ERAD_CRC_QUAL_NONE = 0, //!< Use every valid event as qualifier
//!< for CRC computation
ERAD_CRC_QUAL_HWBP1 = 1, //!< CRC Compute Qualified by HWBP_EVENT1
ERAD_CRC_QUAL_HWBP2 = 2, //!< CRC Compute Qualified by HWBP_EVENT2
ERAD_CRC_QUAL_HWBP3 = 3, //!< CRC Compute Qualified by HWBP_EVENT3
ERAD_CRC_QUAL_HWBP4 = 4, //!< CRC Compute Qualified by HWBP_EVENT4
ERAD_CRC_QUAL_HWBP5 = 5, //!< CRC Compute Qualified by HWBP_EVENT5
ERAD_CRC_QUAL_HWBP6 = 6, //!< CRC Compute Qualified by HWBP_EVENT6
ERAD_CRC_QUAL_HWBP7 = 7, //!< CRC Compute Qualified by HWBP_EVENT7
ERAD_CRC_QUAL_HWBP8 = 8, //!< CRC Compute Qualified by HWBP_EVENT8
ERAD_CRC_QUAL_HWBP_OR1 = 9, //!< CRC Compute Qualified by HWBP_EVENT_OR1
ERAD_CRC_QUAL_HWBP_OR2 = 10, //!< CRC Compute Qualified by HWBP_EVENT_OR1
ERAD_CRC_QUAL_HWBP_OR3 = 11, //!< CRC Compute Qualified by HWBP_EVENT_OR1
ERAD_CRC_QUAL_HWBP_OR4 = 12, //!< CRC Compute Qualified by HWBP_EVENT_OR1
ERAD_CRC_QUAL_HWBP_AND1 = 13, //!< CRC Compute Qualified by HWBP_EVENT_AND2
ERAD_CRC_QUAL_HWBP_AND2 = 14, //!< CRC Compute Qualified by HWBP_EVENT_AND2
ERAD_CRC_QUAL_HWBP_AND3 = 15, //!< CRC Compute Qualified by HWBP_EVENT_AND2
ERAD_CRC_QUAL_HWBP_AND4 = 16 //!< CRC Compute Qualified by HWBP_EVENT_AND2
} ERAD_CRC_Qualifiers;
//*****************************************************************************
//
//! Values that can be passed to ERAD_setCounterInputConditioning() as
//! \e input_type parameter. To specify which input to condition.
//
//*****************************************************************************
typedef enum
{
ERAD_COUNTER_COUNT_INPUT = 0,
ERAD_COUNTER_START_INPUT = 1,
ERAD_COUNTER_STOP_INPUT = 2,
ERAD_COUNTER_RESET_INPUT = 3
} ERAD_Counter_Input_Type;
//*****************************************************************************
//
//! Structure that is passed to ERAD_configBusComp() as \e config_params
//! to configure a bus comparator.
//
//*****************************************************************************
typedef struct
{
uint32_t mask; //!< Mask to be used for comparing
uint32_t reference; //!< Reference value to be compared
ERAD_BusComp_Comp_Mode comp_mode; //!< Comparison mode
_Bool enable_int; //!< Enable Interrupt on event match
_Bool enable_stop; //!< Enable CPU halt on event match
ERAD_BusComp_Bus_Select bus_sel; //!< Bus to be monitored
} ERAD_BusComp_Config;
//*****************************************************************************
//
//! Structure that is passed to ERAD_profile() as \e config_params to setup
//! the required modules appropriately for each use case.
//
//*****************************************************************************
typedef struct
{
uint32_t start_address; //!< Start address
uint32_t end_address; //!< End address
ERAD_BusComp_Bus_Select bus_sel; //!< Bus to be monitored
uint32_t busComp_base1; //!< Bus comparators to be used
uint32_t busComp_base2; //!< Bus comparators to be used
uint32_t counter_base; //!< Counter to be used
} ERAD_Profile_Params;
//*****************************************************************************
//
//! Structure that is passed to ERAD_configCounterInStartStopMode() and
//! ERA_configCounterInCountingMode() as \e config_params to setup a
//! counter appropriately.
//
//*****************************************************************************
typedef struct
{
ERAD_Counter_Input_Event event; //!< Input Event to be counted
ERAD_Counter_Event_Mode event_mode; //!< Active / rising edge
uint32_t reference; //!< Reference to be compared
_Bool rst_on_match; //!< Enable counter reset on match
_Bool enable_int; //!< Enable Interrupt on match
_Bool enable_stop; //!< Enable CPU halt on match
} ERAD_Counter_Config;
//*****************************************************************************
//
//! Structure that is passed to ERAD_enableInterruptOnAddressHit() and
//! ERAD_countAddressHits() as \e config_params to select the bus and the
//! address to compare. \e bus_Sel can be one of the following:
//! \b ERAD_BUSCOMP_BUS_PAB : for instruction fetch at the address
//! \b ERAD_BUSCOMP_BUS_DWAB : for data write access to the address
//! \b ERAD_BUSCOMP_BUS_DRAB : for data read access to the address
//
//*****************************************************************************
typedef struct
{
uint32_t address; //!< Address to compare
uint32_t mask; //!< Mask for the address compare
ERAD_BusComp_Bus_Select bus_sel; //!< Bus to be monitored
} ERAD_AddressHit_Params;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Gets the current owner of ERAD.
//!
//! \param None.
//!
//! This function returns the current owner of ERAD.
//!
//! \return Owner of ERAD.
//
//*****************************************************************************
static inline ERAD_Owner
ERAD_getOwnership(void)
{
//
// Read Global Owner register and return value
//
return((ERAD_Owner)((uint16_t)(((*((volatile uint16_t *)(0x0005E800U + 0xAU))) &
0x3U) >> 0U)));
}
//*****************************************************************************
//
//! Sets the current owner of ERAD.
//!
//! \param owner is the Owner of ERAD that is to be set
//!
//! This function sets the current owner of ERAD.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setOwnership(ERAD_Owner owner)
{
//
// Set the Global Owner as owner
//
__eallow();
(*((volatile uint16_t *)(0x0005E800U + 0xAU))) =
((uint16_t)owner & 0x3U) << 0U;
__edis();
}
//*****************************************************************************
//
//! Resets the counter using the global registers.
//!
//! \param instances is the OR'd value of counter instances to be reset.
//! Following macros can be used:
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function resets the selected counters using the global registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_resetCounter(uint16_t instances)
{
//
// Resets the counter by writing into the global registers
//
__eallow();
(*((volatile uint16_t *)(0x0005E800U + 0x6U))) |= instances >> 8U;
__edis();
}
//*****************************************************************************
//
//! Enables counters and bus comparators.
//!
//! \param instances is the OR'd value of instances of the counters and bus
//! comparators. Following macros can be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function enables bus comparators and counters whose instances are
//! passed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableModules(uint16_t instances)
{
//
// Write into Global register for enabling the required modules
//
__eallow();
(*((volatile uint16_t *)(0x0005E800U + 0x4U))) |= instances;
__edis();
}
//*****************************************************************************
//
//! Disables counters and bus comparators.
//!
//! \param instances is the OR'd value of instances of the counters and bus
//! comparators. Following macros can be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function disables bus comparators and counters whose instances are
//! passed.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableModules(uint16_t instances)
{
//
// Write into Global register for disabling the required modules
//
__eallow();
(*((volatile uint16_t *)(0x0005E800U + 0x4U))) &= (~instances);
__edis();
}
//*****************************************************************************
//
//! Initialises ERAD.
//!
//! \param owner is the owner of ERAD that is to be set.
//!
//! This function resets all the counters and disables all bus comparators and
//! counters.
//! Also sets the owner of the ERAD to the required owner.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_initModule(ERAD_Owner owner)
{
//
// Set the owner of ERAD as required
//
ERAD_setOwnership(owner);
//
// Disable all counters and bus comparators
//
ERAD_disableModules(0x00000001UL | 0x00000002UL |
0x00000004UL | 0x00000008UL |
0x00000010UL | 0x00000020UL |
0x00000040UL | 0x00000080UL |
0x00000100UL | 0x00000200UL |
0x00000400UL | 0x00000800UL);
//
// Reset all counters
//
ERAD_resetCounter(0x00000100UL | 0x00000200UL |
0x00000400UL | 0x00000800UL);
}
//*****************************************************************************
//
//! Returns the completed status of any of the modules.
//!
//! \param None.
//!
//! This function returns the completed status of the counters and bus
//! comparators as stored in the global registers. This allows us to read just
//! one register and see if any of the modules are in a completed state.
//!
//! \return Completed status of all the modules as stored in the global
//! register.
//
//*****************************************************************************
static inline uint16_t
ERAD_getHaltStatus(void)
{
//
// Read and return from the global register
//
return((*((volatile uint16_t *)(0x0005E800U + 0x2U))));
}
//*****************************************************************************
//
//! Returns the event fired status of any of the modules.
//!
//! \param None.
//!
//! This function returns the event fired status of the counters and bus
//! comparators as stored in the global registers. This allows us to read just
//! one register and see if any of the modules have fired.
//!
//! \return Event fired status of all the modules as stored in the global
//! register.
//
//*****************************************************************************
static inline uint16_t
ERAD_getEventStatus(void)
{
//
// Read and return from the global register
//
return((*((volatile uint16_t *)(0x0005E800U + 0x0U))));
}
//*****************************************************************************
//
//! Enables an NMI for the specified modules.
//!
//! \param instances is the OR'd value of the instances of the counters and
//! bus comparator units that need to have an NMI enabled. Following macros can
//! be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function enables an NMI to be generated whenever any of the specified
//! counters or bus comparator units generate and event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableNMI(uint16_t instances)
{
__eallow();
(*((volatile uint16_t *)(0x0005E800U + 0x8U))) |= instances;
__edis();
}
//*****************************************************************************
//
//! Disables an NMI for the specified modules.
//!
//! \param instances is the OR'd value of the instances of the counters and
//! bus comparator units that need to have an NMI disabled. Following macros can
//! be used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! This function disables the NMI for the specified counters and bus
//! comparator units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableNMI(uint16_t instances)
{
__eallow();
(*((volatile uint16_t *)(0x0005E800U + 0x8U))) &= (~instances);
__edis();
}
//*****************************************************************************
//
//! Returns the status of a bus comparator.
//!
//! \param base is the base of the bus comparator.
//!
//! This function returns the status of the bus comparator whose base was
//! passed. It may be either \b ERAD_STATE_IDLE, \b ERAD_STATE_ENABLED or
//! \b ERAD_STATE_COMPLETED.
//!
//! \return Status of bus comparator.
//
//*****************************************************************************
static inline ERAD_Status
ERAD_getBusCompStatus(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Read and return status of bus comparator
//
return((ERAD_Status)((uint16_t)(((*((volatile uint16_t *)(base + 0x7U))) &
0xC000U) >> 14U)));
}
//*****************************************************************************
//
//! Clears the event fired status of any of the modules.
//!
//! \param base is the base of the bus comparator.
//!
//! This function clears the event fired status of the bus comparator and
//! brings the module and brings the module back to \b ERAD_STATE_IDLE .
//!
//! \return None
//
//*****************************************************************************
static inline void
ERAD_clearBusCompEvent(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Clear the event fired bit by writing into EVENT_CLR register
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) = 0x1U;
__edis();
}
//*****************************************************************************
//
//! Returns the status of a counter.
//!
//! \param base is the base of the counter.
//!
//! This function returns the status of the counter whose base was
//! passed. It may be either \b ERAD_STATE_IDLE, \b ERAD_STATE_ENABLED or
//! \b ERAD_STATE_COMPLETED.
//!
//! \return Status of counter.
//
//*****************************************************************************
static inline ERAD_Status
ERAD_getCounterStatus(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Read and return status of the counter
//
return((ERAD_Status)((uint16_t)(((*((volatile uint16_t *)(base + 0x1U))) &
0xF000U) >> 12U)));
}
//*****************************************************************************
//
//! Configures the bus comparators.
//!
//! \param base is the base of the bus comparator to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the bus comparator.
//!
//! This function configures the bus comparator with the given parameters.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configBusComp(uint32_t base, ERAD_BusComp_Config config_params);
//*****************************************************************************
//
//! Configures the counter in Counting mode.
//!
//! \param base is the base of the counter to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the counter.
//!
//! This function configures the counter with the given parameters. The counter
//! is setup in Counting mode, which means counting begins as soon as the
//! counter is enabled.
//! NOTE: This function does not enable the counter. The counter must be
//! enabled using the \b ERAD_enableModules method to begin counting.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configCounterInCountingMode(uint32_t base,
ERAD_Counter_Config config_params);
//*****************************************************************************
//
//! Configures the counter in Start-Stop mode.
//!
//! \param base is the base of the counter to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the counter.
//! \param start_event is the event that starts the counter
//! \param stop_event is the event which stops that counter
//!
//! This function configures the counter with the given parameters. The counter
//! is setup in Start-Stop mode, which means counting will happen only between
//! two specified events. The event that will be counted can be any of the
//! \b ERAD_Counter_Input_Event and not only CPU cycles.
//! NOTE: \b ERAD_EVENT_NO_EVENT causes the counter to use the CPU cycles.
//! NOTE: This function does not enable the counter. The counter must be
//! enabled using the \b ERAD_enableModules method to begin counting.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configCounterInStartStopMode(uint32_t base,
ERAD_Counter_Config config_params,
ERAD_Counter_Input_Event start_event,
ERAD_Counter_Input_Event stop_event);
//*****************************************************************************
//
//! Configures the counter in Start-Stop Cumulative mode.
//!
//! \param base is the base of the counter to be configured.
//! \param config_params are the configuration parameters to be used to
//! configure the counter.
//! \param start_event is the event that starts the counter
//! \param stop_event is the event which stops that counter
//!
//! This function configures the counter with the given parameters. The counter
//! is setup in Cumulative mode, which means counting will happen only between
//! two specified events and the counter will not reset on \b stop_event. The
//! event that will be counted can be any of the \b ERAD_Counter_Input_Event
//! and not only CPU cycles.
//! NOTE: \b ERAD_EVENT_NO_EVENT causes the counter to use the CPU cycles.
//! NOTE: This function does not enable the counter. The counter must be
//! enabled using the \b ERAD_enableModules method to begin counting.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configCounterInCumulativeMode(uint32_t base,
ERAD_Counter_Config config_params,
ERAD_Counter_Input_Event start_event,
ERAD_Counter_Input_Event stop_event);
//*****************************************************************************
//
//! Configures the AND and OR masks
//!
//! \param mask is the Mask to be used.
//!
//! \param instances is the OR'd value of the instances of the bus comparator
//! units whose events need to be used for the mask. Following macros can be
//! used:
//! - \b ERAD_INST_BUSCOMP1
//! - \b ERAD_INST_BUSCOMP2
//! - \b ERAD_INST_BUSCOMP3
//! - \b ERAD_INST_BUSCOMP4
//! - \b ERAD_INST_BUSCOMP5
//! - \b ERAD_INST_BUSCOMP6
//! - \b ERAD_INST_BUSCOMP7
//! - \b ERAD_INST_BUSCOMP8
//! - \b ERAD_INST_COUNTER1
//! - \b ERAD_INST_COUNTER2
//! - \b ERAD_INST_COUNTER3
//! - \b ERAD_INST_COUNTER4
//!
//! \param enable_int True if interrupt needs to be enabled, False if not
//!
//! This function enables the event generated from the specified bus comparator
//! units to be used for the specified Mask. It also configures the interrupt
//! generation when the mask event occurs.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_configMask(ERAD_Mask mask, uint32_t instances, _Bool enable_int);
//*****************************************************************************
//
//! Configures the reset event of the counter.
//!
//! \param base is the base of the counter to be configured.
//! \param reset_event is the event upon which the counter must be reset.
//!
//! This function sets the event upon which the counter must reset and enables
//! reset upon such an event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableCounterResetInput(uint32_t base,
ERAD_Counter_Input_Event reset_event)
{
//
// Check if the base is valid
//
;
//
// Setup up the counter such that the reset event is set and enabled
//
__eallow();
(*((volatile uint32_t *)(base + 0x0U))) |= 0x400U;
(*((volatile uint32_t *)(base + 0xAU))) =
((*((volatile uint32_t *)(base + 0xAU))) &
~0x7F00U) |
((uint16_t)reset_event << 8U);
__edis();
}
//*****************************************************************************
//
//! Disables the reset event of the counter.
//!
//! \param base is the base of the counter.
//!
//! This function disables the reset event that may have been set earlier
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableCounterResetInput(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Disable the reset bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) &= (~0x400U);
__edis();
}
//*****************************************************************************
//
//! Clears an event that may have fired in the counter upon match.
//!
//! \param base is the base of the counter.
//!
//! This function clears a counter event that may have fired when the counter
//! hit a match.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_clearCounterEvent(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Clear the event by writing into CTM_CLEAR register
//
__eallow();
(*((volatile uint16_t *)(base + 0x9U))) = 0x1U;
__edis();
}
//*****************************************************************************
//
//! Clears an overflow that may have occured in the counter.
//!
//! \param base is the base of the counter.
//!
//! This function clears the overflow bit that may have got set when the
//! counter may have crossed 0xFFFFFFFF.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_clearCounterOverflow(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Clear the overflow bit by writing into the CTM_CLEAR register
//
__eallow();
(*((volatile uint16_t *)(base + 0x9U))) = 0x2U;
__edis();
}
//*****************************************************************************
//
//! Gets the current count of a counter.
//!
//! \param base is the base of the counter.
//!
//! This function returns the current count of the counter which was
//! configured earlier.
//!
//! \return Returns the value of the current count of the counter.
//
//*****************************************************************************
static inline uint32_t
ERAD_getCurrentCount(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Return the current count
//
return((*((volatile uint32_t *)(base + 0x4U))));
}
//*****************************************************************************
//
//! Sets the current count of a counter.
//!
//! \param base is the base of the counter.
//! \param value is the value to be written as the current count.
//!
//! This function sets the current count of the counter which was
//! configured earlier. This can be used to reset the counter or start at
//! a value other than 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setCurrentCount(uint32_t base, uint32_t value)
{
//
// Check if owner is APPLICATION or NO_OWNER
//
;
//
// Check if the base is valid
//
;
//
// Write the value into CTM_COUNT register
//
__eallow();
(*((volatile uint32_t *)(base + 0x4U))) = value;
__edis();
}
//*****************************************************************************
//
//! Gets the maximum count of a counter.
//!
//! \param base is the base of the counter.
//!
//! This function returns the current maximum count of the counter which was
//! configured earlier.
//!
//! \return Returns the value of the current maximum count of the counter.
//
//*****************************************************************************
static inline uint32_t
ERAD_getMaxCount(uint32_t base)
{
//
// Check if the base is valid
//
;
//
// Return the maximum value
//
return((*((volatile uint32_t *)(base + 0x6U))));
}
//*****************************************************************************
//
//! Sets the maximum count of a counter.
//!
//! \param base is the base of the counter.
//! \param value is the value to be written as the maximum count.
//!
//! This function sets the current maximum count of the counter which was
//! configured earlier.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setMaxCount(uint32_t base, uint32_t value)
{
//
// Check if owner is APPLICATION or NO_OWNER
//
;
//
// Check if the base is valid
//
;
//
// Write the value into the CTM_MAX_COUNT register
//
__eallow();
(*((volatile uint32_t *)(base + 0x6U))) = value;
__edis();
}
//*****************************************************************************
//
//! Sets conditioning on the inputs to the counter.
//!
//! \param base is the base value of the counter to be configured
//! \param input_type defines which input needs to be conditioned
//! \param options is the kind of conditioning that needs to applied. This will
//! be an OR'd value of \b ERAD_INVERT_ENABLE, \b ERAD_INVERT_DISABLE,
//! \b ERAD_SYNC_ENABLE or \b ERAD_SYNC_DISABLE.
//!
//! This function conditions the inputs to the counter specified. This includes
//! inverting the input and enabling a 2-stage synchronizer for any 4 of the
//! inputs: \e reset, \e stop, \e start, \e count_input.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setCounterInputConditioning(uint32_t base,
ERAD_Counter_Input_Type input_type,
uint16_t options)
{
//
// Write into the Input Conditioning register
//
__eallow();
(*((volatile uint16_t *)(base + 0xBU))) =
((*((volatile uint16_t *)(base + 0xBU))) &
~(0x03U << (uint16_t)input_type)) |
(options << (uint16_t)input_type);
__edis();
}
//*****************************************************************************
//
//! Initialises the CRC unit.
//!
//! \param instances is the OR'd value of CRC instances. Following macros can
//! be used:
//! - \b ERAD_INST_CRC1
//! - \b ERAD_INST_CRC2
//! - \b ERAD_INST_CRC3
//! - \b ERAD_INST_CRC4
//! - \b ERAD_INST_CRC5
//! - \b ERAD_INST_CRC6
//! - \b ERAD_INST_CRC7
//! - \b ERAD_INST_CRC8
//!
//! This function initialises the specified CRC units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_initCRC(uint16_t instances)
{
//
// Write into the CRC GLOBAL CTRL register
//
__eallow();
(*((volatile uint16_t *)(0x0005EA00U + 0x0U))) |= instances;
__edis();
}
//*****************************************************************************
//
//! Enables the CRC unit.
//!
//! \param instances is the OR'd value of CRC instances. Following macros can
//! be used:
//! - \b ERAD_INST_CRC1
//! - \b ERAD_INST_CRC2
//! - \b ERAD_INST_CRC3
//! - \b ERAD_INST_CRC4
//! - \b ERAD_INST_CRC5
//! - \b ERAD_INST_CRC6
//! - \b ERAD_INST_CRC7
//! - \b ERAD_INST_CRC8
//!
//! This function enables the specified CRC units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_enableCRC(uint16_t instances)
{
//
// Write into the CRC GLOBAL CTRL register
//
__eallow();
(*((volatile uint16_t *)(0x0005EA00U + 0x0U))) |= instances << 8;
__edis();
}
//*****************************************************************************
//
//! Disables the CRC unit.
//!
//! \param instances is the OR'd value of CRC instances. Following macros can
//! be used:
//! - \b ERAD_INST_CRC1
//! - \b ERAD_INST_CRC2
//! - \b ERAD_INST_CRC3
//! - \b ERAD_INST_CRC4
//! - \b ERAD_INST_CRC5
//! - \b ERAD_INST_CRC6
//! - \b ERAD_INST_CRC7
//! - \b ERAD_INST_CRC8
//!
//! This function disables the specified CRC units.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_disableCRC(uint16_t instances)
{
//
// Write into the CRC GLOBAL CTRL register
//
__eallow();
(*((volatile uint16_t *)(0x0005EA00U + 0x0U))) &= ~(instances << 8);
__edis();
}
//*****************************************************************************
//
//! Gets the current value of the CRC unit.
//!
//! \param base is the base value of CRC unit
//!
//! This function returns the current value of te specified CRC unit.
//!
//! \return Current CRC value.
//
//*****************************************************************************
static inline uint32_t
ERAD_getCurrentCRC(uint32_t base)
{
//
// Check if base is valid
//
;
//
// Read from the current value register of the specified CRC unit
//
return((*((volatile uint32_t *)(base + 0x0U))));
}
//*****************************************************************************
//
//! Sets the seed value of the CRC unit
//!
//! \param base is the base value of the CRC unit
//! \param seed is the value of seed to be set
//!
//! This function sets a seed value of the CRC unit.
//! Note: The corresponding CRC unit must be disabled before setting the seed
//! value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setSeed(uint32_t base, uint32_t seed)
{
//
// Check if base is valid
//
;
//
// Check if the unit is disabled
//
;
//
// Write into the CRC SEED register
//
__eallow();
(*((volatile uint16_t *)(base + 0x2U))) = seed;
__edis();
}
//*****************************************************************************
//
//! Sets the qualifier event of the CRC unit
//!
//! \param base is the base value of the CRC unit
//! \param qualifier is the type of qualifier to be set
//!
//! This function sets a qualifier to decide which events require a CRC
//! computation.
//! Note: The corresponding CRC unit must be disabled before setting the
//! qualifier.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ERAD_setCRCQualifier(uint32_t base, ERAD_CRC_Qualifiers qualifier)
{
//
// Check if base is valid
//
;
//
// Check if the unit is disabled
//
;
//
// Write into the CRC Qualifier register
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) = qualifier;
__edis();
}
//*****************************************************************************
//
//! Configures the ERAD to profile a certain piece of code
//!
//! \param config_params are the parameters that will be used to configure ERAD
//!
//! This function configures 2 bus comparators and 1 counter to profile a
//! certain piece of code. The base address of the bus comparators and the
//! counter to be used are specified in \e config_params.
//! Note: Use \b ERAD_getMaxCount to get the latest profiled value. The
//! maximum count of the counter being used must be reset to 0x0 to get the
//! correct value everytime.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_profile(ERAD_Profile_Params config_params);
//*****************************************************************************
//
//! Enables an RTOS interrupt at a specified address.
//!
//! \param config_params contrains the bus to be monitored and the address
//! \param busComp_base is the base of the bus compoarator to be used
//!
//! This function enables an RTOS interrupt to be generated when an address
//! in memory or instruction is hit.
//!
//! If the selected bus is \b ERAD_BUSCOMP_BUS_PAB, then the ERAD will be
//! configured to trigger an interrupt when there is instruction fetch happening
//! at the specified address. Similary, if \b ERAD_BUSCOMP_BUS_DWAB is selected,
//! the ERAD will be configured to trigger an interrupt when there write
//! access to the specified address, and so on.
//!
//! Use \e
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_enableInterruptOnAddressHit(ERAD_AddressHit_Params config_params,
uint32_t busComp_base);
//*****************************************************************************
//
//! Configures the ERAD to count the number of times a the specified address
//! is hit
//!
//! \param config_params are the parameters that will be used to configure ERAD
//! \param busComp_base is the base of the bus compoarator to be used
//! \param counter_base is the base of the counter to be used
//!
//! This function configures 1 bus comparator and 1 counter to count how many
//! times a the specified address is hit.
//!
//! If the selected bus is \b ERAD_BUSCOMP_BUS_PAB, then the ERAD will be
//! configured to count the number of times an instruction fetch happens
//! at the specified address. Similary, if \b ERAD_BUSCOMP_BUS_DWAB is selected,
//! the ERAD will be configured to count the number of times there is a write
//! access to the specified address, and so on.
//!
//! \return None.
//
//*****************************************************************************
extern void
ERAD_countAddressHits(ERAD_AddressHit_Params config_params,
uint32_t busComp_base, uint32_t counter_base);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: flash.h
//
// TITLE: C28x Flash driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup flash_api Flash
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_flash.h
//
// TITLE: Definitions for the FLASH registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the FLASH register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FRDCNTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FBAC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FBFALLBACK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FBPRDY register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FPAC1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FPAC2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FMSTAT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FRD_INTF_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECC_ENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_STATUS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_POS register
//
//*************************************************************************************************
// bits
// bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_STATUS_CLR register
//
//*************************************************************************************************
// Value 0 Clear
// Value 1 Clear
// occurred Clear
// Value 0 Clear
// Value 1 Clear
// occurred Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_CNT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_THRESHOLD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_INTFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_INTCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FADDR_TEST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_TEST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_STATUS register
//
//*************************************************************************************************
#pragma CODE_SECTION(Flash_setBankPowerMode, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_setPumpPowerMode, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_disableCache, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_disablePrefetch, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_setWaitstates, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_enableCache, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_enablePrefetch, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_enableECC, ".TI.ramfunc");
//*****************************************************************************
//
//! Values that can be passed to Flash_setBankPowerMode() as the bank parameter
//
//*****************************************************************************
typedef enum
{
FLASH_BANK0 = 0x0, //!< Bank 0
FLASH_BANK1 = 0x1, //!< Bank 1
FLASH_BANK2 = 0x2 //!< Bank 2
} Flash_BankNumber;
//*****************************************************************************
//
//! Values that can be passed to Flash_setBankPowerMode() as the powerMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
FLASH_BANK_PWR_SLEEP = 0x0, //!< Sleep fallback mode
FLASH_BANK_PWR_STANDBY = 0x1, //!< Standby fallback mode
FLASH_BANK_PWR_ACTIVE = 0x3 //!< Active fallback mode
} Flash_BankPowerMode;
//*****************************************************************************
//
//! Values that can be passed to Flash_setPumpPowerMode() as the powerMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
FLASH_PUMP_PWR_SLEEP = 0x0, //!< Sleep fallback mode
FLASH_PUMP_PWR_ACTIVE = 0x1 //!< Active fallback mode
} Flash_PumpPowerMode;
//*****************************************************************************
//
//! Type that correspond to values returned from Flash_getLowErrorStatus() and
//! Flash_getHighErrorStatus() determining the error status code.
//
//*****************************************************************************
typedef enum
{
FLASH_NO_ERR = 0x0, //!< No error
FLASH_FAIL_0 = 0x1, //!< Fail on 0
FLASH_FAIL_1 = 0x2, //!< Fail on 1
FLASH_UNC_ERR = 0x4 //!< Uncorrectable error
} Flash_ErrorStatus;
//*****************************************************************************
//
//! Values that can be returned from Flash_getLowErrorType() and
//! Flash_getHighErrorType() determining the error type.
//
//*****************************************************************************
typedef enum
{
FLASH_DATA_ERR = 0x0, //!< Data error
FLASH_ECC_ERR = 0x1 //!< ECC error
} Flash_ErrorType;
//*****************************************************************************
//
//! Values that can be returned from Flash_getECCTestSingleBitErrorType().
//
//*****************************************************************************
typedef enum
{
FLASH_DATA_BITS = 0x0, //!< Data bits
FLASH_CHECK_BITS = 0x1 //!< ECC bits
} Flash_SingleBitErrorIndicator;
//*****************************************************************************
//
// Values that can be passed to Flash_clearLowErrorStatus and
// Flash_clearHighErrorStatus.
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be returned from Flash_getInterruptFlag and
// Flash_getECCTestStatus.
//
//*****************************************************************************
//*****************************************************************************
//
// Delay instruction that allows for register configuration to complete.
//
//*****************************************************************************
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a flash wrapper base address for the control registers.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! This function determines if a flash wrapper control base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a flash wrapper base address for the ECC registers.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function determines if a flash wrapper ECC base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the random read wait state amount.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param waitstates is the wait-state value.
//!
//! This function sets the number of wait states for a flash read access. The
//! \e waitstates parameter is a number between 0 and 15. It is \b important
//! to look at your device's datasheet for information about what the required
//! minimum flash wait-state is for your selected SYSCLK frequency.
//!
//! By default the wait state amount is configured to the maximum 15.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setWaitstates(uint32_t ctrlBase, uint16_t waitstates)
{
//
// Check the arguments.
//
;
//
// waitstates is 4 bits wide.
//
;
__eallow();
//
// Write flash read wait-state amount to appropriate register.
//
(*((volatile uint32_t *)(ctrlBase + 0x0U))) =
((*((volatile uint32_t *)(ctrlBase + 0x0U))) &
~(uint32_t)0xF00U) |
((uint32_t)waitstates << 8U);
__edis();
}
//*****************************************************************************
//
//! Sets the fallback power mode of a flash bank.
//!
//! \param ctrlBase is the base address of the flash wrapper registers.
//! \param bank is the flash bank that is being configured.
//! \param powerMode is the power mode to be entered.
//!
//! This function sets the fallback power mode of the flash bank specified by
//! them \e bank parameter. The power mode is specified by the \e powerMode
//! parameter with one of the following values:
//!
//! - \b FLASH_BANK_PWR_SLEEP - Sense amplifiers and sense reference disabled.
//! - \b FLASH_BANK_PWR_STANDBY - Sense amplifiers disabled but sense reference
//! enabled.
//! - \b FLASH_BANK_PWR_ACTIVE - Sense amplifiers and sense reference enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setBankPowerMode(uint32_t ctrlBase, Flash_BankNumber bank,
Flash_BankPowerMode powerMode)
{
//
// Check the arguments.
//
;
__eallow();
//
// Write the power mode to the appropriate register.
//
(*((volatile uint32_t *)(ctrlBase + 0x20U))) =
((*((volatile uint32_t *)(ctrlBase + 0x20U))) &
~((0x3U) << ((uint32_t)bank * 2U))) |
((uint32_t)powerMode << ((uint32_t)bank * 2U));
__edis();
}
//*****************************************************************************
//
//! Sets the fallback power mode of the charge pump.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param powerMode is the power mode to be entered.
//!
//! This function sets the fallback power mode flash charge pump.
//!
//! - \b FLASH_PUMP_PWR_SLEEP - All circuits disabled.
//! - \b FLASH_PUMP_PWR_ACTIVE - All pump circuits active.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setPumpPowerMode(uint32_t ctrlBase, Flash_PumpPowerMode powerMode)
{
//
// Check the arguments.
//
;
__eallow();
//
// Write the power mode to the appropriate register.
//
(*((volatile uint32_t *)(ctrlBase + 0x24U))) =
((*((volatile uint32_t *)(ctrlBase + 0x24U))) &
~(uint32_t)0x1U) | (uint32_t)powerMode;
__edis();
}
//*****************************************************************************
//
//! Enables prefetch mechanism.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enablePrefetch(uint32_t ctrlBase)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set the prefetch enable bit.
//
(*((volatile uint32_t *)(ctrlBase + 0x180U))) |=
0x1U;
__edis();
}
//*****************************************************************************
//
//! Disables prefetch mechanism.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disablePrefetch(uint32_t ctrlBase)
{
//
// Check the arguments.
//
;
__eallow();
//
// Clear the prefetch enable bit.
//
(*((volatile uint32_t *)(ctrlBase + 0x180U))) &=
~(uint32_t)0x1U;
__edis();
}
//*****************************************************************************
//
//! Enables data cache.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enableCache(uint32_t ctrlBase)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set the data cache enable bit.
//
(*((volatile uint32_t *)(ctrlBase + 0x180U))) |=
0x2U;
__edis();
}
//*****************************************************************************
//
//! Disables data cache.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disableCache(uint32_t ctrlBase)
{
//
// Check the arguments.
//
;
__eallow();
//
// Clear the data cache enable bit.
//
(*((volatile uint32_t *)(ctrlBase + 0x180U))) &=
~(uint32_t)0x2U;
__edis();
}
//*****************************************************************************
//
//! Enables flash error correction code (ECC) protection.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enableECC(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
//
// Write the key value 0xA to ECC_ENABLE register.
//
(*((volatile uint32_t *)(eccBase + 0x0U))) =
((*((volatile uint32_t *)(eccBase + 0x0U))) &
~(uint32_t)0xFU) | 0xAU;
__edis();
}
//*****************************************************************************
//
//! Disables flash error correction code (ECC) protection.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disableECC(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
//
// Clear ECC enable field with the one's complement of the key.
//
(*((volatile uint32_t *)(eccBase + 0x0U))) =
((*((volatile uint32_t *)(eccBase + 0x0U))) &
~(uint32_t)0xFU) | 0x5U;
__edis();
}
//*****************************************************************************
//
//! Sets the bank active grace period.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param period is the starting count value for the BAGP down counter.
//!
//! This function sets the bank active grace period specified by the
//! \e period parameter. The \e period is a value between 0 and 255. This
//! value must be greater than 1 when the fallback mode is not Active.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setBankActiveGracePeriod(uint32_t ctrlBase, uint32_t period)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Write period to the BAGP of the FBAC register.
//
(*((volatile uint32_t *)(ctrlBase + 0x1EU))) =
((*((volatile uint32_t *)(ctrlBase + 0x1EU))) &
~(uint32_t)0xFF00U) | (period << 8U);
__edis();
}
//*****************************************************************************
//
//! Sets the pump active grace period.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param period is the starting count value for the PAGP down counter.
//!
//! This function sets the pump active grace period specified by the
//! \e period parameter. The \e period is a value between 0 and 65535. The
//! counter is reloaded after any flash access. After the counter expires, the
//! charge pump falls back to the power mode determined by FPAC1, bit PMPPWR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setPumpActiveGracePeriod(uint32_t ctrlBase, uint16_t period)
{
//
// Check the arguments.
//
;
__eallow();
//
// Write period to the PAGP of the FPAC2 register.
//
(*((volatile uint32_t *)(ctrlBase + 0x26U))) =
((*((volatile uint32_t *)(ctrlBase + 0x26U))) &
~(uint32_t)0xFFFFU) |
((uint32_t)period << 0U);
__edis();
}
//*****************************************************************************
//
//! Sets the pump wake up time.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param sysclkCycles is the number of SYSCLK cycles it takes for the pump
//! to wakeup.
//!
//! This function sets the wakeup time with \e sysclkCycles parameter.
//! The \e sysclkCycles is a value between 0 and 8190. When the charge pump
//! exits sleep power mode, it will take sysclkCycles to wakeup.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setPumpWakeupTime(uint32_t ctrlBase, uint16_t sysclkCycles)
{
//
// Check the arguments.
//
;
//
// PSLEEP = sysclkCycles/2. PSLEEP maximum value is 4095(12 bits wide)
//
;
__eallow();
//
// Write sysclkCycles/2 to PSLEEP of the FPAC1 register.
//
(*((volatile uint32_t *)(ctrlBase + 0x24U))) =
((*((volatile uint32_t *)(ctrlBase + 0x24U))) &
~(uint32_t)0xFFF0000U) |
(((uint32_t)sysclkCycles / (uint32_t)2) <<
(uint32_t)16U);
__edis();
}
//*****************************************************************************
//
//! Reads the bank active power state.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param bank is the flash bank that is being used.
//!
//! \return Returns \b true if the Bank is in Active power state and \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
Flash_isBankReady(uint32_t ctrlBase, Flash_BankNumber bank)
{
//
// Check the arguments.
//
;
_Bool ready;
uint32_t bitMask = (uint32_t)0x1U << (uint32_t)bank;
//
// Return the BANKXRDY bit in FBPRDY.
//
if(((*((volatile uint32_t *)(ctrlBase + 0x22U))) & bitMask) == bitMask)
{
ready = 1;
}
else
{
ready = 0;
}
return(ready);
}
//*****************************************************************************
//
//! Reads the pump active power state.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! \return Returns \b true if the Pump is in Active power state and \b false
//! otherwise.
//
//*****************************************************************************
static inline _Bool
Flash_isPumpReady(uint32_t ctrlBase)
{
//
// Check the arguments.
//
;
_Bool ready;
//
// Return the PUMPRDY bit in FBPRDY.
//
if(((*((volatile uint32_t *)(ctrlBase + 0x22U))) &
(uint32_t)0x8000U) == 0x8000U)
{
ready = 1;
}
else
{
ready = 0;
}
return(ready);
}
//*****************************************************************************
//
//! Gets the single error address low.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the 32-bit address of the single bit error that
//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where a single bit
//! error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getSingleBitErrorAddressLow(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(eccBase + 0x2U))));
}
//*****************************************************************************
//
//! Gets the single error address high.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the 32-bit address of the single bit error that
//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where a single bit
//! error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getSingleBitErrorAddressHigh(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(eccBase + 0x4U))));
}
//*****************************************************************************
//
//! Gets the uncorrectable error address low.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the 32-bit address of the uncorrectable error that
//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where an
//! uncorrectable error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getUncorrectableErrorAddressLow(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(eccBase + 0x6U))));
}
//*****************************************************************************
//
//! Gets the uncorrectable error address high.
//!
//! \param eccBase is the base address of the flash wrapper ECC base.
//!
//! This function returns the 32-bit address of the uncorrectable error that
//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The
//! returned address is to that 64-bit aligned data.
//!
//! \return Returns the 32 bits of a 64-bit aligned address where an
//! uncorrectable error occurred.
//
//*****************************************************************************
static inline uint32_t
Flash_getUncorrectableErrorAddressHigh(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(eccBase + 0x8U))));
}
//*****************************************************************************
//
//! Gets the error status of the Lower 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error status of the lower 64-bits of a 128-bit
//! aligned address.
//!
//! \return Returns value of the low error status bits which can be used with
//! Flash_ErrorStatus type.
//
//*****************************************************************************
static inline Flash_ErrorStatus
Flash_getLowErrorStatus(uint32_t eccBase)
{
uint32_t errorStatus;
//
// Check the arguments.
//
;
//
// Get the Low Error Status bits
//
errorStatus = ((*((volatile uint32_t *)(eccBase + 0xAU))) & 0x7UL);
return((Flash_ErrorStatus)errorStatus);
}
//*****************************************************************************
//
//! Gets the error status of the Upper 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error status of the upper 64-bits of a 128-bit
//! aligned address.
//!
//! \return Returns value of the high error status bits which can be used with
//! Flash_ErrorStatus type.
//
//*****************************************************************************
static inline Flash_ErrorStatus
Flash_getHighErrorStatus(uint32_t eccBase)
{
uint32_t errorStatus;
//
// Check the arguments.
//
;
//
// Get the High Error Status bits
//
errorStatus = (((*((volatile uint32_t *)(eccBase + 0xAU))) >> 16U) & 0x7UL);
return((Flash_ErrorStatus)errorStatus);
}
//*****************************************************************************
//
//! Gets the error position of the lower 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error position of the lower 64-bits. If the
//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges
//! from 0-63 for FLASH_DATA_ERR.
//!
//! \return Returns the position of the lower error bit.
//
//*****************************************************************************
static inline uint32_t
Flash_getLowErrorPosition(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return(((*((volatile uint32_t *)(eccBase + 0xCU))) &
(uint32_t)0x3FU) >>
0U);
}
//*****************************************************************************
//
//! Gets the error position of the upper 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error position of the upper 64-bits. If the
//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges
//! from 0-63 for FLASH_DATA_ERR.
//!
//! \return Returns the position of the upper error bit.
//
//*****************************************************************************
static inline uint32_t
Flash_getHighErrorPosition(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return(((*((volatile uint32_t *)(eccBase + 0xCU))) &
(uint32_t)0x3F0000U) >>
16U);
}
//*****************************************************************************
//
//! Clears the error position bit of the lower 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error position bit of the lower 64-bits.
//!
//! \return None
//
//*****************************************************************************
static inline void
Flash_clearLowErrorPosition(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0xCU))) &= ~(uint32_t)0x3FU;
__edis();
}
//*****************************************************************************
//
//! Clears the error position of the upper 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error position bit of the upper 64-bits.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearHighErrorPosition(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0xCU))) &= ~(uint32_t)0x3F0000U;
__edis();
}
//*****************************************************************************
//
//! Gets the error type of the lower 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error type of the lower 64-bits. The error type
//! can be FLASH_ECC_ERR or FLASH_DATA_ERR.
//!
//! \return Returns the type of the lower 64-bit error.
//
//*****************************************************************************
static inline Flash_ErrorType
Flash_getLowErrorType(uint32_t eccBase)
{
Flash_ErrorType errorType;
//
// Check the arguments.
//
;
//
// Check which error type.
// If bit is 1 then ECC error, else it is a Data error.
//
if(((*((volatile uint32_t *)(eccBase + 0xCU))) & 0x100U)
== 0x100U)
{
errorType = FLASH_ECC_ERR;
}
else
{
errorType = FLASH_DATA_ERR;
}
return(errorType);
}
//*****************************************************************************
//
//! Gets the error type of the upper 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the error type of the upper 64-bits. The error type
//! can be FLASH_ECC_ERR or FLASH_DATA_ERR.
//!
//! \return Returns the type of the upper 64-bit error.
//
//*****************************************************************************
static inline Flash_ErrorType
Flash_getHighErrorType(uint32_t eccBase)
{
Flash_ErrorType errorType;
//
// Check the arguments.
//
;
//
// Check which error type.
// If bit is 1 then ECC error, else it is a Data error.
//
if(((*((volatile uint32_t *)(eccBase + 0xCU))) & 0x1000000U)
== 0x1000000U)
{
errorType = FLASH_ECC_ERR;
}
else
{
errorType = FLASH_DATA_ERR;
}
return(errorType);
}
//*****************************************************************************
//
//! Clears the error type bit of the lower 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error type bit of the lower 64-bits.
//!
//! \return None
//
//*****************************************************************************
static inline void
Flash_clearLowErrorType(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0xCU))) &= ~(uint32_t)0x100U;
__edis();
}
//*****************************************************************************
//
//! Clears the error type of the upper 64-bits for a single bit error.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function clears the error type bit of the upper 64-bits.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearHighErrorType(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0xCU))) &= ~(uint32_t)0x1000000U;
__edis();
}
//*****************************************************************************
//
//! Clears the errors status of the lower 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param errorStatus is the error status to clear. errorStatus is a uint16_t.
//! errorStatus is a bitwise OR of the following value:
//!
//! - \b FLASH_FAIL_0_CLR
//! - \b FLASH_FAIL_1_CLR
//! - \b FLASH_UNC_ERR_CLR
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearLowErrorStatus(uint32_t eccBase, uint16_t errorStatus)
{
//
// Check the arguments.
//
;
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0xEU))) |= ((uint32_t)errorStatus);
__edis();
}
//*****************************************************************************
//
//! Clears the errors status of the upper 64-bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param errorStatus is the error status to clear. errorStatus is a uint16_t.
//! errorStatus is a bitwise OR of the following value:
//!
//! - \b FLASH_FAIL_0_CLR
//! - \b FLASH_FAIL_1_CLR
//! - \b FLASH_UNC_ERR_CLR
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearHighErrorStatus(uint32_t eccBase, uint16_t errorStatus)
{
//
// Check the arguments.
//
;
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0xEU))) |= ((uint32_t)errorStatus << 16U);
__edis();
}
//*****************************************************************************
//
//! Gets the single bit error count.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the single bit error count.
//
//*****************************************************************************
static inline uint32_t
Flash_getErrorCount(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(eccBase + 0x10U))) &
(uint32_t)0xFFFFU);
}
//*****************************************************************************
//
//! Sets the single bit error threshold.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param threshold is the single bit error threshold. Valid ranges are from
//! 0-65535.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setErrorThreshold(uint32_t eccBase, uint16_t threshold)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x12U))) = ((uint32_t)threshold &
(uint32_t)0xFFFFU);
__edis();
}
//*****************************************************************************
//
//! Gets the error interrupt.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the type of error interrupt that occurred. The
//! values can be used with
//! - \b FLASH_NO_ERROR
//! - \b FLASH_SINGLE_ERROR
//! - \b FLASH_UNC_ERROR
//!
//! \return Returns the interrupt flag.
//
//*****************************************************************************
static inline uint32_t
Flash_getInterruptFlag(uint32_t eccBase)
{
//
// Check the arguments.
//
;
//
// Read which type of error occurred.
//
return(((*((volatile uint32_t *)(eccBase + 0x14U))) & (uint32_t)0x3U));
}
//*****************************************************************************
//
//! Clears the single error interrupt flag.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearSingleErrorInterruptFlag(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x16U))) |=
0x1U;
__edis();
}
//*****************************************************************************
//
//! Clears the uncorrectable error interrupt flag.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_clearUncorrectableInterruptFlag(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x16U))) |=
0x2U;
__edis();
}
//*****************************************************************************
//
//! Sets the Data Low Test register for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param data is a 32-bit value that is the low double word of selected
//! 64-bit data
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setDataLowECCTest(uint32_t eccBase, uint32_t data)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x1AU))) = data;
__edis();
}
//*****************************************************************************
//
//! Sets the Data High Test register for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param data is a 32-bit value that is the high double word of selected
//! 64-bit data
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setDataHighECCTest(uint32_t eccBase, uint32_t data)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x18U))) = data;
__edis();
}
//*****************************************************************************
//
//! Sets the test address register for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param address is a 32-bit value containing an address. Bits 21-3 will be
//! used as the flash word (128-bit) address.
//!
//! This function left shifts the address 1 bit to convert it to a byte address
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setECCTestAddress(uint32_t eccBase, uint32_t address)
{
//
// Check the arguments.
//
;
//
// Left shift the address 1 bit to make it byte-addressable
//
uint32_t byteAddress = address << 1;
__eallow();
//
// Write bits 21-3 to the register.
//
(*((volatile uint32_t *)(eccBase + 0x1CU))) = byteAddress;
__edis();
}
//*****************************************************************************
//
//! Sets the ECC test bits for ECC testing.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param ecc is a 32-bit value. The least significant 8 bits are used as
//! the ECC Control Bits in the ECC Test.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_setECCTestECCBits(uint32_t eccBase, uint16_t ecc)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Write the 8 ECC Control Bits.
//
(*((volatile uint32_t *)(eccBase + 0x1EU))) =
((uint32_t)ecc & (uint32_t)0xFFU);
__edis();
}
//*****************************************************************************
//
//! Enables ECC Test mode.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_enableECCTestMode(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x20U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Disables ECC Test mode.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_disableECCTestMode(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x20U))) &=
~(uint32_t)0x1U;
__edis();
}
//*****************************************************************************
//
//! Selects the ECC block on bits [63:0] of bank data.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_selectLowECCBlock(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x20U))) &=
~(uint32_t)0x2U;
__edis();
}
//*****************************************************************************
//
//! Selects the ECC block on bits [127:64] of bank data.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_selectHighECCBlock(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x20U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! Performs the ECC calculation on the test block.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Flash_performECCCalculation(uint32_t eccBase)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(eccBase + 0x20U))) |= 0x4U;
__edis();
}
//*****************************************************************************
//
//! Gets the ECC Test data out high 63:32 bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the ECC TEst data out High.
//
//*****************************************************************************
static inline uint32_t
Flash_getTestDataOutHigh(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(eccBase + 0x22U))));
}
//*****************************************************************************
//
//! Gets the ECC Test data out low 31:0 bits.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the ECC Test data out Low.
//
//*****************************************************************************
static inline uint32_t
Flash_getTestDataOutLow(uint32_t eccBase)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(eccBase + 0x24U))));
}
//*****************************************************************************
//
//! Gets the ECC Test status.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! This function returns the ECC test status. The values can be used with
//! - \b FLASH_NO_ERROR
//! - \b FLASH_SINGLE_ERROR
//! - \b FLASH_UNC_ERROR
//!
//! \return Returns the ECC test status.
//
//*****************************************************************************
static inline uint32_t
Flash_getECCTestStatus(uint32_t eccBase)
{
//
// Check the arguments.
//
;
//
// Read which type of error occurred.
//
return(((*((volatile uint32_t *)(eccBase + 0x26U)))) & (uint32_t)0x3U);
}
//*****************************************************************************
//
//! Gets the ECC Test single bit error position.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the ECC Test single bit error position. If the error type
//! is check bits than the position can range from 0 to 7. If the error type
//! is data bits than the position can range from 0 to 63.
//
//*****************************************************************************
static inline uint32_t
Flash_getECCTestErrorPosition(uint32_t eccBase)
{
//
// Check the arguments.
//
;
//
// Read the position bits and shift it to the right.
//
return(((*((volatile uint32_t *)(eccBase + 0x26U))) &
(uint32_t)0xFCU) >>
2U);
}
//*****************************************************************************
//
//! Gets the single bit error type.
//!
//! \param eccBase is the base address of the flash wrapper ECC registers.
//!
//! \return Returns the single bit error type as a
//! Flash_SingleBitErrorIndicator. FLASH_DATA_BITS and FLASH_CHECK_BITS
//! indicate where the single bit error occurred.
//
//*****************************************************************************
static inline Flash_SingleBitErrorIndicator
Flash_getECCTestSingleBitErrorType(uint32_t eccBase)
{
uint32_t errorType;
//
// Check the arguments.
//
;
//
// Read the ERR_TYPE bit to see where the single bit error was.
//
errorType = (((*((volatile uint32_t *)(eccBase + 0x26U))) &
(uint32_t)0x100U) >> 8U);
return((Flash_SingleBitErrorIndicator)errorType);
}
//*****************************************************************************
//
//! Initializes the flash control registers.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//! \param eccBase is the base address of the flash wrapper ECC registers.
//! \param waitstates is the wait-state value.
//!
//! This function initializes the flash control registers. At reset bank and
//! pump are in sleep. A flash access will power up the bank and pump
//! automatically. This function will power up Flash bank and pump and set the
//! fallback mode of flash and pump as active.
//!
//! This function also sets the number of wait-states for a flash access
//! (see Flash_setWaitstates() for more details), and enables cache, the
//! prefetch mechanism, and ECC.
//!
//! \return None.
//
//*****************************************************************************
extern void
Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates);
//*****************************************************************************
//
//! Powers down the flash.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! This function powers down the flash bank(s) and the flash pump.
//!
//! \return None.
//
//*****************************************************************************
extern void
Flash_powerDown(uint32_t ctrlBase);
//*****************************************************************************
//
//! Wakes the flash from low power mode.
//!
//! \param ctrlBase is the base address of the flash wrapper control registers.
//!
//! This function will power up Flash bank and pump and set the
//! fallback mode of flash and pump as active.
//!
//! \return None.
//
//*****************************************************************************
extern void
Flash_wakeFromLPM(uint32_t ctrlBase);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: fsi.h
//
// TITLE: C28x FSI Driver API header file
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup fsi_api FSI
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_fsi.h
//
// TITLE: Definitions for the FSI registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the FSI register offsets
//
//*************************************************************************************************
// register
// buffer
// RX_INT1
// RX_INT2
// buffer
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_MASTER_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_CLK_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_OPER_CTRL_LO register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_OPER_CTRL_HI register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_FRAME_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_FRAME_TAG_UDATA register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_BUF_PTR_LOAD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_BUF_PTR_STS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_PING_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_PING_TAG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_INT_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_DMA_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_LOCK_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_EVT_STS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_EVT_CLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_EVT_FRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_USER_CRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_ECC_DATA register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_ECC_VAL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TX_DLYLINE_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_MASTER_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_OPER_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_INFO register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_TAG_UDATA register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_DMA_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_EVT_STS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_CRC_INFO register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_EVT_CLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_EVT_FRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_BUF_PTR_LOAD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_BUF_PTR_STS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_WD_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_PING_WD_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_PING_TAG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_INT1_CTRL register
//
//*************************************************************************************************
// Interrupt to INT1
// Interrupt to INT1
// to INT1
// to INT1
// Interrupt to INT1
// INT1
// Interrupt to INT1
// Interrupt to INT1
// INT1
// Interrupt to INT1
// Interrupt to INT1
// Interrupt to INT1
// Interrupt to INT1
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_INT2_CTRL register
//
//*************************************************************************************************
// Interrupt to INT2
// Interrupt to INT2
// to INT2
// to INT2
// INT2
// INT2
// Interrupt to INT2
// Interrupt to INT2
// INT2
// Interrupt to INT2
// Interrupt to INT2
// Interrupt to INT2
// Interrupt to INT2
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_LOCK_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_ECC_DATA register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_ECC_VAL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_ECC_LOG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_FRAME_TAG_CMP register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_PING_TAG_CMP register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_WIDTH_0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_DLYLINE_CTRL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_TRIG_CTRL_3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_VIS_1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the RX_UDATA_FILTER register
//
//*************************************************************************************************
//*****************************************************************************
// PMBUS
//*****************************************************************************
//*****************************************************************************
// FSI
//*****************************************************************************
//*****************************************************************************
// SPI
//*****************************************************************************
//*****************************************************************************
// I2C
//*****************************************************************************
//*****************************************************************************
// LIN
//*****************************************************************************
//*****************************************************************************
//
// FSI Tx defines
//
//*****************************************************************************
//*****************************************************************************
//
// FSI Tx events defines
//
// Values that can be passed to APIs to enable/disable interrupts and
// also to set/get/clear event status on FSI Tx operation.
//
// There are 4 supported interrupts related to Tx events-
// All are available as event status as well except 4th one.
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Flag for event status not available as interrupt
//!
//! Ping frame transmission upon hardware trigger(ping watchdog or
//! external trigger) is shown as event status.
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Mask of all Tx Events, ORing all event defines
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Maximum number of external input for triggering frame-transmission
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Shifts needed to control FSI Tx interrupt generation on INT2
//
//*****************************************************************************
//*****************************************************************************
//
// FSI Rx Defines
//
//*****************************************************************************
//*****************************************************************************
//
// FSI Rx event defines
//
// Values that can be passed to APIs to enable/disable interrupts and
// also to set/get/clear event status on FSI Rx operation.
//
// There are 15 supported interrupts related to Rx events.
// All are available as event status as well.
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Mask of all Rx Events, ORing all event defines
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Maximum value in Rx delay line tap control
//
//*****************************************************************************
//*****************************************************************************
//
// Common defines for both FSI Tx and Rx
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Maximum data length(16 words) for user/software defined data frame
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Maximum value for user data field(8 bits)
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Maximum value of Buffer pointer offset(4 bits)
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Key value for writing some FSI Tx/Rx registers
//
//*****************************************************************************
//*****************************************************************************
//
// typedefs
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Data lines used for transmit/receive operation
//!
//! \details Supported number of data lines is only 2 - 1 lane or 2 lanes
//
//*****************************************************************************
typedef enum
{
FSI_DATA_WIDTH_1_LANE = 0x0000U,
FSI_DATA_WIDTH_2_LANE = 0x0001U
} FSI_DataWidth;
//*****************************************************************************
//
//! \brief List of TX submodules that can be reset, can be used with reset APIs
//!
//! \details Three kind of resets can be made-
//! 1) reset entire Tx Module
//! 2) reset only TX clock
//! 3) reset ping timeout counter
//
//*****************************************************************************
typedef enum
{
FSI_TX_MAIN_CORE_RESET = 0x0000U,
FSI_TX_CLOCK_RESET = 0x0001U,
FSI_TX_PING_TIMEOUT_CNT_RESET = 0x0002U
} FSI_TxSubmoduleInReset;
//*****************************************************************************
//
//! \brief Start Mode for Tx frame transmission
//!
//! \details Three start modes(that is, how transmission will start) are
//! supported-
//! 1. SW write of START bit in \b TX_PKT_CTRL register
//! 2. Rising edge on external trigger
//! 3. Either SW write of START bit or Frame completion
//
//*****************************************************************************
typedef enum
{
FSI_TX_START_FRAME_CTRL = 0x0000U,
FSI_TX_START_EXT_TRIG = 0x0001U,
FSI_TX_START_FRAME_CTRL_OR_UDATA_TAG = 0x0002U
} FSI_TxStartMode;
//*****************************************************************************
//
//! \brief Various FSI frame types
//!
//! \details Three frame types exist-
//! - \b Ping: Used for checking line integrity, can be sent by
//! software or automatically by hardware.
//! - \b Error: Used typically during error conditions or when one
//! side wants to signal the other side for attention.
//! - \b Data: Two subtypes exist based on data-length-
//! a) \b Fixed (1/2/4/6 words)
//! b) \b Nwords Software programs number of data words
//!
//! \note 4 bit code for frame types- 0x1, 0x2 and 0x8 to 0xE are reserved
//
//*****************************************************************************
typedef enum
{
FSI_FRAME_TYPE_PING = 0x0000U,
FSI_FRAME_TYPE_ERROR = 0x000FU,
FSI_FRAME_TYPE_1WORD_DATA = 0x0004U,
FSI_FRAME_TYPE_2WORD_DATA = 0x0005U,
FSI_FRAME_TYPE_4WORD_DATA = 0x0006U,
FSI_FRAME_TYPE_6WORD_DATA = 0x0007U,
FSI_FRAME_TYPE_NWORD_DATA = 0x0003U
} FSI_FrameType;
//*****************************************************************************
//
//! \brief Possible values of a FSI frame
//!
//! \details 4 bit field inside FSI frame is available to set tag value(0-15)
//
//*****************************************************************************
typedef enum
{
FSI_FRAME_TAG0 = 0x0000U,
FSI_FRAME_TAG1 = 0x0001U,
FSI_FRAME_TAG2 = 0x0002U,
FSI_FRAME_TAG3 = 0x0003U,
FSI_FRAME_TAG4 = 0x0004U,
FSI_FRAME_TAG5 = 0x0005U,
FSI_FRAME_TAG6 = 0x0006U,
FSI_FRAME_TAG7 = 0x0007U,
FSI_FRAME_TAG8 = 0x0008U,
FSI_FRAME_TAG9 = 0x0009U,
FSI_FRAME_TAG10 = 0x000AU,
FSI_FRAME_TAG11 = 0x000BU,
FSI_FRAME_TAG12 = 0x000CU,
FSI_FRAME_TAG13 = 0x000DU,
FSI_FRAME_TAG14 = 0x000EU,
FSI_FRAME_TAG15 = 0x000FU
} FSI_FrameTag;
//*****************************************************************************
//
//! \brief Ping timeout mode
//!
//! \details Ping timeout can reset and restart only on hardware initiated PING
//! frames (PING Watchdog timeout)
//! OR
//! on any software initiated frame being sent out also based on
//! which mode is selected
//
//*****************************************************************************
typedef enum
{
FSI_PINGTIMEOUT_ON_HWINIT_PING_FRAME = 0x0000U,
FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME = 0x0001U
} FSI_PingTimeoutMode;
//! \brief ECC Computation width- 16 bit or 32 bit
//!
typedef enum
{
FSI_32BIT_ECC_COMPUTE = 0x0000U,
FSI_16BIT_ECC_COMPUTE = 0x0001U
} FSI_ECCComputeWidth;
//*****************************************************************************
//
//! \brief Interrupt lines supported in FSI
//!
//! \details Any event on FSI Tx or Rx can be enabled to trigger interrupt on 2
//! interrupt lines to CPU/CLA- \b INT1 and \b INT2
//
//*****************************************************************************
typedef enum
{
FSI_INT1 = 0x0000U,
FSI_INT2 = 0x0001U
} FSI_InterruptNum;
//*****************************************************************************
//
//! \brief List of RX modules that can be reset, can be used with reset APIs
//!
//! \details Three submodules can be reset-
//! 1) RX main core
//! 2) frame watchdog counter
//! 3) ping watchdog counter
//
//*****************************************************************************
typedef enum
{
FSI_RX_MAIN_CORE_RESET = 0x0000U,
FSI_RX_FRAME_WD_CNT_RESET = 0x0001U,
FSI_RX_PING_WD_CNT_RESET = 0x0002U
} FSI_RxSubmoduleInReset;
//*****************************************************************************
//
//! \brief Available Rx lines for delay tap selection
//!
//! \details Delay tapping can be done on 3 lines- 1)RXCLK 2)RXD0 and 3)RXD1
//
//*****************************************************************************
typedef enum
{
FSI_RX_DELAY_CLK = 0x0000U,
FSI_RX_DELAY_D0 = 0x0001U,
FSI_RX_DELAY_D1 = 0x0002U
} FSI_RxDelayTapType;
//*****************************************************************************
//
//! \brief Indexes of available EPWM SOC triggers
//!
//
//*****************************************************************************
typedef enum
{
FSI_EXT_TRIGSRC_EPWM_XBARTRIP4 = 0U,
FSI_EXT_TRIGSRC_EPWM_XBARTRIP5 = 1U,
FSI_EXT_TRIGSRC_EPWM_XBARTRIP7 = 2U,
FSI_EXT_TRIGSRC_EPWM_XBARTRIP8 = 3U,
FSI_EXT_TRIGSRC_EPWM_XBARTRIP9 = 4U,
FSI_EXT_TRIGSRC_EPWM_XBARTRIP10 = 5U,
FSI_EXT_TRIGSRC_EPWM_XBARTRIP11 = 6U,
FSI_EXT_TRIGSRC_EPWM_XBARTRIP12 = 7U,
FSI_EXT_TRIGSRC_EPWM1_SOCA = 8U,
FSI_EXT_TRIGSRC_EPWM1_SOCB = 9U,
FSI_EXT_TRIGSRC_EPWM2_SOCA = 10U,
FSI_EXT_TRIGSRC_EPWM2_SOCB = 11U,
FSI_EXT_TRIGSRC_EPWM3_SOCA = 12U,
FSI_EXT_TRIGSRC_EPWM3_SOCB = 13U,
FSI_EXT_TRIGSRC_EPWM4_SOCA = 14U,
FSI_EXT_TRIGSRC_EPWM4_SOCB = 15U,
FSI_EXT_TRIGSRC_EPWM5_SOCA = 16U,
FSI_EXT_TRIGSRC_EPWM5_SOCB = 17U,
FSI_EXT_TRIGSRC_EPWM6_SOCA = 18U,
FSI_EXT_TRIGSRC_EPWM6_SOCB = 19U,
FSI_EXT_TRIGSRC_EPWM7_SOCA = 20U,
FSI_EXT_TRIGSRC_EPWM7_SOCB = 21U,
FSI_EXT_TRIGSRC_EPWM8_SOCA = 22U,
FSI_EXT_TRIGSRC_EPWM8_SOCB = 23U,
FSI_EXT_TRIGSRC_CLB1_CLBOUT30 = 40U,
FSI_EXT_TRIGSRC_CLB1_CLBOUT31 = 41U,
FSI_EXT_TRIGSRC_CLB2_CLBOUT30 = 42U,
FSI_EXT_TRIGSRC_CLB2_CLBOUT31 = 43U,
FSI_EXT_TRIGSRC_ADC_SOCA = 52U,
FSI_EXT_TRIGSRC_ADC_SOCB = 53U,
FSI_EXT_TRIGSRC_CPU1_TIMER0INT = 54U,
FSI_EXT_TRIGSRC_CPU1_TIMER1INT = 55U,
FSI_EXT_TRIGSRC_CPU1_TIMER2INT = 56U
} FSI_ExtFrameTriggerSrc;
//*****************************************************************************
//
// FSI Tx function prototypes/defintion
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Validates if FSI-Tx base address is correct
//!
//! \param[in] base is the base address of the FSI-Tx module
//!
//! \return returns \b true if the base address is valid and \b false otherwise
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Sends FLUSH pattern
//!
//! \details FLUSH pattern (toggle data lines followed by toggle on clocks)
//! should be sent only when FSI Tx is not under \b SOFT_RESET and the
//! clock to the transmit core has been turned ON.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_sendTxFlush(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) |= ((uint16_t)0x2U |
((0x00A5U) <<
8U));
__edis();
}
//*****************************************************************************
//
//! \brief Stops FLUSH pattern transmission
//!
//! \details Transmission of FLUSH pattern should be stopped before starting
//! sending frames. Generally during initilization a pair of send/stop
//! APIs for FLUSH pattern is called to clear data/clock lines.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_stopTxFlush(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) = (((~0x2U) &
(*((volatile uint16_t *)(base + 0x0U)))) |
((0x00A5U) <<
8U));
__edis();
}
//*****************************************************************************
//
//! \brief Selects PLL clock as source for clock dividers
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_selectTxPLLClock(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set PLLCLK as source for clock divider
//
(*((volatile uint16_t *)(base + 0x4U))) |= 0x100U;
__edis();
}
//*****************************************************************************
//
//! \brief sets clock division prescalar and enables the transmit clock
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxClock(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enable Tx clock
//
(*((volatile uint16_t *)(base + 0x2U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables transmit clock
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxClock(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Disable Tx clock
//
(*((volatile uint16_t *)(base + 0x2U))) &= ~0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Sets the prescalar clock keeping the transmit clock in reset
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] preScaleValue used to generate transmit clock, it defines the
//! division value of /2,/3,/4,etc. of \b PLLCLK. Prescale value is
//! is to be set while keeping the clock in reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_configPrescalar(uint32_t base, uint16_t preScaleValue)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Disable Tx clock
//
(*((volatile uint16_t *)(base + 0x2U))) &= ~0x2U;
//
// Set prescalar value
//
(*((volatile uint16_t *)(base + 0x2U))) = ((*((volatile uint16_t *)(base + 0x2U))) &
(~0x3FCU)) |
(preScaleValue <<
2U);
__edis();
}
//*****************************************************************************
//
//! \brief Sets Data width for transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] dataWidth selection between 1 or 2 lane transmission
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxDataWidth(uint32_t base, FSI_DataWidth dataWidth)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) =
((*((volatile uint16_t *)(base + 0x4U))) &
(~0x3U)) |
(uint16_t)dataWidth;
__edis();
}
//*****************************************************************************
//
//! \brief Enables SPI compatible mode
//!
//! \details FSI supports a \b compatibility mode in order to communicate with
//! \b legacy peripherals like \b SPI. Only the 16-bit mode of SPI will
//! be supported. All the frame structures, CRC checks and will be
//! identical to the normal FSI frames.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxSPIMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) |= 0x4U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables SPI compatible mode
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxSPIMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x4U;
__edis();
}
//*****************************************************************************
//
//! \brief Sets start mode for any frame transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] txStartMode is one of supported 3 start modes in transmission
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxStartMode(uint32_t base, FSI_TxStartMode txStartMode)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) =
((*((volatile uint16_t *)(base + 0x4U))) &
(~0x38U)) |
((uint16_t)txStartMode << 3U);
__edis();
}
//*****************************************************************************
//
//! \brief Setting for when Ping timeout can reset and restart
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] pingTimeoutMode can be HW or both HW/SW initiated
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxPingTimeoutMode(uint32_t base, FSI_PingTimeoutMode pingTimeoutMode)
{
//
// Check the arguments.
//
;
__eallow();
if(pingTimeoutMode == FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME)
{
(*((volatile uint16_t *)(base + 0x4U))) |=
0x80U;
}
else
{
(*((volatile uint16_t *)(base + 0x4U))) &=
~0x80U;
}
__edis();
}
//*****************************************************************************
//
//! \brief Enables the Tx TDM mode for multi-node configuration
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxTDMMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enable Tx TDM Mode
//
(*((volatile uint16_t *)(base + 0x4U))) |= 0x200U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the Tx TDM mode.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxTDMMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x200U;
__edis();
}
//*****************************************************************************
//
//! \brief Enables RX TDM as TDM source.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxTDMMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enable Tx TDM Mode
//
(*((volatile uint16_t *)(base + 0x4U))) |= 0x400U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the Rx TDM mode.
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxTDMMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x400U;
__edis();
}
//*****************************************************************************
//
//! \brief Sets a particular external input to trigger transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] extInputNum can be one of ports from 0 to 63. See also
//! FSI_ExtFrameTriggerSrc enum members for valid external triggers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxExtFrameTrigger(uint32_t base, uint16_t extInputNum)
{
//
// Check the arguments.
//
;
;
__eallow();
(*((volatile uint16_t *)(base + 0x5U))) =
((*((volatile uint16_t *)(base + 0x5U))) &
(~0x1F80U)) |
(extInputNum << 7U);
__edis();
}
//*****************************************************************************
//
//! \brief Enables CRC value of a data frame to be forced to zero
//!
//! \details CRC value of the data frame will be forced to 0 whenever there is
//! a transmission and buffer over-run or under-run condition happens.
//! The idea is to force a corruption of the CRC since the data is not
//! guaranteed to be reliable
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxCRCForceError(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x5U))) |= 0x20U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables forcing of CRC value of a data frame to zero
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxCRCForceError(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x5U))) &= ~0x20U;
__edis();
}
//*****************************************************************************
//
//! \brief Select between 16-bit and 32-bit ECC computation
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] eccComputeWidth is ECC Computation width
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxECCComputeWidth(uint32_t base, FSI_ECCComputeWidth eccComputeWidth)
{
//
// Check the arguments.
//
;
__eallow();
if(eccComputeWidth == FSI_16BIT_ECC_COMPUTE)
{
(*((volatile uint16_t *)(base + 0x5U))) |= 0x40U;
}
else
{
(*((volatile uint16_t *)(base + 0x5U))) &= ~0x40U;
}
__edis();
}
//*****************************************************************************
//
//! \brief Sets frame type for transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] frameType value of frame type
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxFrameType(uint32_t base, FSI_FrameType frameType)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x6U))) = ((*((volatile uint16_t *)(base + 0x6U))) &
(~0xFU)) |
(uint16_t)frameType;
}
//*****************************************************************************
//
//! \brief Sets the frame size if frame type is user/software defined frame
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] nWords is number of data words in a software defined frame
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxSoftwareFrameSize(uint32_t base, uint16_t nWords)
{
//
// Check the arguments.
//
;
;
(*((volatile uint16_t *)(base + 0x6U))) = ((*((volatile uint16_t *)(base + 0x6U))) &
(~0xF0U)) |
((nWords - 1U) <<
4U);
}
//*****************************************************************************
//
//! \brief Starts transmitting frames
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_startTxTransmit(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x6U))) |= 0x8000U;
}
//*****************************************************************************
//
//! \brief Sets frame tag for transmission
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] frameTag value of frame tag, 4 bit value (0 to 15)
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxFrameTag(uint32_t base, FSI_FrameTag frameTag)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x7U))) =
((*((volatile uint16_t *)(base + 0x7U))) &
(~0xFU)) |
(uint16_t)frameTag;
}
//*****************************************************************************
//
//! \brief Sets user defined data for transmission
//! It is an extra data field(8 bit) apart from regular data
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] userDefData 8 bit user defined data value
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxUserDefinedData(uint32_t base, uint16_t userDefData)
{
//
// Check the arguments.
//
;
;
(*((volatile uint16_t *)(base + 0x7U))) =
((*((volatile uint16_t *)(base + 0x7U))) &
(~0xFF00U)) |
(userDefData << 8U);
}
//*****************************************************************************
//
//! \brief Sets the value for transmit buffer pointer at desired location
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] bufPtrOff 4 bit offset pointer in Tx buffer where transmitter
//! will pick the data
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxBufferPtr(uint32_t base, uint16_t bufPtrOff)
{
//
// Check the arguments.
//
;
;
__eallow();
(*((volatile uint16_t *)(base + 0x8U))) = bufPtrOff;
__edis();
}
//*****************************************************************************
//
//! \brief Returns current buffer pointer location
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return current buffer pointer location
//!
//! \note there could be lag due to synchronization hence value is accurate
//! only when no current transmission is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getTxBufferPtr(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0x9U))) &
0xFU);
}
//*****************************************************************************
//
//! \brief Returns valid number of data words present in buffer which have not
//! been transmitted yet
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return number of data words present in buffer which have not been
//! transmitted yet
//! \note there could be lag due to synchronization hence value is accurate
//! only when no current transmission is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getTxWordCount(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint16_t *)(base + 0x9U))) &
0x1F00U) >>
8U);
}
//*****************************************************************************
//
//! \brief Enables ping timer logic and once set time elapses it sends signal
//! to transmitter to send ping frame
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] refValue 32 bit reference value for ping time-out counter
//! \param[in] pingFrameTag 4 bit tag value for ping time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxPingTimer(uint32_t base, uint32_t refValue,
FSI_FrameTag pingFrameTag)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0xBU))) = (uint16_t)pingFrameTag;
__eallow();
(*((volatile uint32_t *)(base + 0xCU))) = refValue;
(*((volatile uint16_t *)(base + 0xAU))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Sets the ping tag value, used by either timeout counter initiated
//! PING frame transfer or by external ping trigger input.
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] frameTag 4 bit tag value for ping time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxPingTag(uint32_t base, FSI_FrameTag frameTag)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0xBU))) = (uint16_t)frameTag;
}
//*****************************************************************************
//
//! \brief Disables ping timer logic
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxPingTimer(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0xAU))) &= ~0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Enables external trigger to transmit a ping frame
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] extTrigSel can be one of the external inputs from 0 to 63.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxExtPingTrigger(uint32_t base, uint16_t extTrigSel)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Select external input trigger
//
(*((volatile uint16_t *)(base + 0xAU))) = ((*((volatile uint16_t *)(base + 0xAU))) &
(~0x1F8U)) |
(extTrigSel <<
3U);
//
// Enable ping frame transmission through external trigger
//
(*((volatile uint16_t *)(base + 0xAU))) |= 0x4U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables external trigger logic
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxExtPingTrigger(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0xAU))) &= ~0x4U;
__edis();
}
//*****************************************************************************
//
//! \brief Gives Current value of Ping Timeout Logic Counter
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return Current value of counter is returned
//
//*****************************************************************************
static inline uint32_t
FSI_getTxCurrentPingTimeoutCounter(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(base + 0xEU))));
}
//*****************************************************************************
//
//! \brief Enables to generate DMA event on completion of a frame transfer
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxDMAEvent(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x11U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! \brief Disable to generate DMA event on completion of a frame transfer
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxDMAEvent(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x11U))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! \brief Locks the control of all transmit control registers,once locked
//! further writes will not take effect until system reset occurs
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \note System reset only can unlock registers once locked.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_lockTxCtrl(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x12U))) = ((uint16_t)0x1U |
((0x00A5U) <<
8U));
__edis();
}
//*****************************************************************************
//
//! \brief Returns current status of all the error flags
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return the status of error flags,each bit of integer is associated with
//! one error flag.
//!
//! Example Usage - function will set the bits corresponding to respective
//! error flag in return value
//! evtStatus = FSI_getTxEventStatus(FSI_base)
//! if bit value of evtStatus is 12(01100) means
//! FSI_TX_EVT_OVERRUN and FSI_TX_EVT_PING_HW_TRIG flags are set
//
//*****************************************************************************
static inline uint16_t
FSI_getTxEventStatus(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0x14U))) & (0x000FU));
}
//*****************************************************************************
//
//! \brief Enables user to set TX error flags
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] evtFlags contains list of event and error flags that are
//! supposed to be set.
//!
//! \details Writing a 1 to this bit position will cause the corresponding bit
//! in \b TX_EVT_ERR_STATUS register to get set. The purpose of this
//! register is to allow software to simulate the effect of the event
//! and test the associated software/ISR.
//!
//! Example Usage
//! evtFlags = FSI_TX_EVT_FRAME_DONE & FSI_TX_EVT_OVERRUN
//! FSI_forceTxEvents(FSI_base,evtFlags)
//! Above call sets error flag to frameDone and overRun events
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_forceTxEvents(uint32_t base, uint16_t evtFlags)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x17U))) = (evtFlags & (0x000FU));
__edis();
}
//*****************************************************************************
//
//! \brief Enables user to clear TX error flags
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] evtFlags contains list of event and error flags that are
//! supposed to be cleared.
//!
//! \details Writing a 1 to this bit position will cause the corresponding bit
//! in the TX_EVT_ERR_STATUS register to get cleared to 0
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_clearTxEvents(uint32_t base, uint16_t evtFlags)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x16U))) = (evtFlags & (0x000FU));
__edis();
}
//*****************************************************************************
//
//! \brief Sets the CRC value to be picked transmission if transmission is
//! configured to use user defined SW CRC
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] userCRCValue is user defined CRC
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxUserCRC(uint32_t base, uint16_t userCRCValue)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) |= 0x40U;
__edis();
(*((volatile uint16_t *)(base + 0x18U))) = userCRCValue;
}
//*****************************************************************************
//
//! \brief Sets the CRC value to be picked transmission if transmission is
//! configured to use user defined SW CRC
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxUserCRC(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x40U;
__edis();
}
//*****************************************************************************
//
//! \brief Sets data for ECC logic computaion
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] data data value for which ECC needs to be computed
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setTxECCdata(uint32_t base, uint32_t data)
{
//
// Check the arguments.
//
;
(*((volatile uint32_t *)(base + 0x20U))) = data;
}
//*****************************************************************************
//
//! \brief Returns ECC value evaluated for 16/32 bit data
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return ECC value for input data
//
//*****************************************************************************
static inline uint16_t
FSI_getTxECCValue(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0x22U))) & 0x7FU);
}
//*****************************************************************************
//
//! \brief Enables user to generate interrupt on occurrence of FSI_TxEventList
//! events
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] intNum is the type of interrupt to be generated
//! interrupt1 or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//! should be generated.
//!
//! Example Usage
//! intFlags = FSI_TX_EVT_FRAME_DONE && FSI_TX_EVT_BUF_OVERRUN
//! && FSI_TX_EVT_PING_TIMEOUT
//! FSI_enableTxInterrupt(FSI_base, FSI_INT1, intFlags)
//! above configuration will generate signal on interrupt line 1 upon
//! frameDone, BufOverRun and PingTimeOut event
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableTxInterrupt(uint32_t base, FSI_InterruptNum intNum,
uint16_t intFlags)
{
//
// Check the arguments.
//
;
__eallow();
if(intNum == FSI_INT1)
{
(*((volatile uint16_t *)(base + 0x10U))) |= (intFlags & (0x000FU));
}
else
{
(*((volatile uint16_t *)(base + 0x10U))) |= ((intFlags & (0x000FU)) <<
(0x8U));
}
__edis();
}
//*****************************************************************************
//
//! \brief Enables user to disable generation interrupt on occurrence of
//! FSI_TxEventList events
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] intNum is the type of interrupt to be generated
//! interrupt1 or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//! generation has to be disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableTxInterrupt(uint32_t base, FSI_InterruptNum intNum,
uint16_t intFlags)
{
//
// Check the arguments.
//
;
__eallow();
if(intNum == FSI_INT1)
{
(*((volatile uint16_t *)(base + 0x10U))) &= ~(intFlags & (0x000FU));
}
else
{
(*((volatile uint16_t *)(base + 0x10U))) &= ((~(intFlags & (0x000FU)) <<
(0x8U)) | 0xFFU);
}
__edis();
}
//*****************************************************************************
//
//! \brief Returns address of Tx data buffer
//!
//! \details Data buffer is consisting of 16 words from offset- 0x40 to 0x4e
//!
//! \param[in] base is the FSI Tx module base address
//!
//! \return Tx data buffer address
//
//*****************************************************************************
static inline uint32_t
FSI_getTxBufferAddress(uint32_t base)
{
//
// Check the arguments.
//
;
return(base + (0x40U + (0U)));
}
//*****************************************************************************
//
//! \brief Resets clock or ping timeout counter or entire TX module
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] submodule the name of submodule which is supposed to be reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_resetTxModule(uint32_t base, FSI_TxSubmoduleInReset submodule);
//*****************************************************************************
//
//! \brief Clears reset on clock or ping timeout counter or entire TX module
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] submodule the name of submodule, to be brought out of reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_clearTxModuleReset(uint32_t base, FSI_TxSubmoduleInReset submodule);
//*****************************************************************************
//
//! \brief Writes data in FSI Tx buffer
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] array is the address of the array of words to be transmitted.
//! \param[in] length is the number of words in the array to be transmitted.
//! \param[in] bufOffset is the offset in Tx buffer where data will be written
//!
//! \note Data Overwrite protection is implemented in this function by ensuring
//! not more than 16 words are written and also wrap around case is taken
//! care when more words need to be written if last write happens at
//! maximum offset in Tx buffer
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_writeTxBuffer(uint32_t base, const uint16_t array[], uint16_t length,
uint16_t bufOffset);
//*****************************************************************************
//*****************************************************************************
//
// FSI Rx function prototypes/definitions
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Checks the FSI-Rx base address
//!
//! \param base is the base address of the FSI-Rx module
//!
//! \return returns \b true if the base address is valid and \b false otherwise
//
//*****************************************************************************
//*****************************************************************************
//
//! \brief Enables internal loopback where mux will select
//! internal pins coming from TX module instead of what comes from pins
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxInternalLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) |=
((uint16_t)0x2U |
((0x00A5U) << 8U));
__edis();
}
//*****************************************************************************
//
//! \brief Disables internal loopback where mux will not use internal pins
//! coming from TX module
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxInternalLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) =
((*((volatile uint16_t *)(base + 0x0U))) &
(~0x2U)) |
((0x00A5U) << 8U);
__edis();
}
//*****************************************************************************
//
//! \brief Receive clock is selected from the internal port coming
//! from TX module
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxSPIPairing(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) |=
((uint16_t)0x4U |
((0x00A5U) << 8U));
__edis();
}
//*****************************************************************************
//
//! \brief Selects regular receive clock coming from the pins
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxSPIPairing(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) &
(~0x4U)) |
((0x00A5U) <<
8U);
__edis();
}
//*****************************************************************************
//
//! \brief Selects number of data lines used for receiving
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] dataWidth selection between 1 or 2 lane receive operation
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxDataWidth(uint32_t base, FSI_DataWidth dataWidth)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) &
(~0x3U)) |
(uint16_t)dataWidth;
__edis();
}
//*****************************************************************************
//
//! \brief Enables SPI compatible mode in FSI Rx
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxSPIMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) |= 0x4U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables SPI compatible mode in FSI Rx
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxSPIMode(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x4U;
__edis();
}
//*****************************************************************************
//
//! \brief Sets the frame size if frame type is user/software defined frame
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] nWords is number of data words in a software defined frame
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxSoftwareFrameSize(uint32_t base, uint16_t nWords)
{
//
// Check the arguments.
//
;
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) &
(~0x78U)) |
((nWords - 1U) <<
3U);
__edis();
}
//*****************************************************************************
//
//! \brief Select between 16-bit and 32-bit ECC computation
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] eccComputeWidth is ECC Computation width
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxECCComputeWidth(uint32_t base, FSI_ECCComputeWidth eccComputeWidth)
{
//
// Check the arguments.
//
;
__eallow();
if(eccComputeWidth == FSI_16BIT_ECC_COMPUTE)
{
(*((volatile uint16_t *)(base + 0x4U))) |= 0x80U;
}
else
{
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x80U;
}
__edis();
}
//*****************************************************************************
//
//! \brief Setting for when Ping timeout can reset and restart
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] pingTimeoutMode can be HW or both HW/SW initiated
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxPingTimeoutMode(uint32_t base, FSI_PingTimeoutMode pingTimeoutMode)
{
//
// Check the arguments.
//
;
__eallow();
if(pingTimeoutMode == FSI_PINGTIMEOUT_ON_HWSWINIT_PING_FRAME)
{
(*((volatile uint16_t *)(base + 0x4U))) |= 0x100U;
}
else
{
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x100U;
}
__edis();
}
//*****************************************************************************
//
//! \brief Gets frame type received in the last successful frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return value of Frame type received on last successful frame
//
//*****************************************************************************
static inline FSI_FrameType
FSI_getRxFrameType(uint32_t base)
{
//
// Check the arguments.
//
;
return((FSI_FrameType)((*((volatile uint16_t *)(base + 0x6U))) &
0xFU));
}
//*****************************************************************************
//
//! \brief Enables to generate DMA event on completion of a successful
//! frame reception
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxDMAEvent(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x8U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the DMA event generation on completion of a successful
//! frame reception
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxDMAEvent(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x8U))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! \brief Returns Frame tag received for the last successful frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return frame tag value.
//
//*****************************************************************************
static inline uint16_t
FSI_getRxFrameTag(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint16_t *)(base + 0x7U))) &
0x1EU) >>
1U);
}
//*****************************************************************************
//
//! \brief Returns User-Data(8-bit) field for received data frame.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return user data field value.
//
//*****************************************************************************
static inline uint16_t
FSI_getRxUserDefinedData(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint16_t *)(base + 0x7U))) &
0xFF00U) >>
8U);
}
//*****************************************************************************
//
//! \brief Returns current status of all the evetn/error flags
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return the status of error flags,each bit of integer is associated
//! with one error flag.
//!
//! Example Usage - function will set the bits corresponding to respective
//! error flag in return value
//! evtFlags = FSI_getRxEventStatus(FSI_base)
//! if value of evtFlags is 1036(0100000001100) means
//! FSI_RX_EVT_FRAME_OVERRUN,FSI_RX_EVT_TYPE_ERR and
//! FSI_RX_EVT_CRC_ERR flags are set
//
//*****************************************************************************
static inline uint16_t
FSI_getRxEventStatus(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0xAU))) & (0x7FFFU));
}
//*****************************************************************************
//
//! \brief Enables user to set RX event/error flags
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] evtFlags contains list of error flags to be set
//!
//! \return None.
//!
//! Example Usage
//! evtFlags = FSI_RX_EVT_EOF_ERR && FSI_RX_EVT_TYPE_ERR
//! FSI_forceRxEvents(FSI_base,evtFlags)
//! Above call sets error flag to FSI_RX_ERR_EOF_ERR and
//! FSI_RX_ERR_TYPE_ERR events
//
//*****************************************************************************
static inline void
FSI_forceRxEvents(uint32_t base, uint16_t evtFlags)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0xDU))) = (evtFlags & (0x7FFFU));
__edis();
}
//*****************************************************************************
//
//! \brief Enables user to clear RX event/error flags
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] evtFlags contains list of error flags to be cleared
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_clearRxEvents(uint32_t base, uint16_t evtFlags)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0xCU))) = (evtFlags & (0x7FFFU));
__edis();
}
//*****************************************************************************
//
//! \brief Returns CRC value received in data frame/frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return CRC value received in data frame
//
//*****************************************************************************
static inline uint16_t
FSI_getRxReceivedCRC(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0xBU))) & 0xFFU);
}
//*****************************************************************************
//
//! \brief Computes and returns CRC value for data received
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return CRC value computed on received data
//
//*****************************************************************************
static inline uint16_t
FSI_getRxComputedCRC(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint16_t *)(base + 0xBU))) &
0xFF00U) >> 8U);
}
//*****************************************************************************
//
//! \brief Sets the value for receive buffer pointer at desired location
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] bufPtrOff 4 bit offset pointer in Rx buffer from where received
//! data will be read
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxBufferPtr(uint32_t base, uint16_t bufPtrOff)
{
//
// Check the arguments.
//
;
;
__eallow();
(*((volatile uint16_t *)(base + 0xEU))) = bufPtrOff;
__edis();
}
//*****************************************************************************
//
//! \brief Returns current buffer pointer location
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return current buffer pointer location
//!
//! \note there could be lag due to synchronization, hence value is accurate
//! only when no current reception is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getRxBufferPtr(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0xFU))) &
0xFU);
}
//*****************************************************************************
//
//! \brief Returns valid number of data words present in buffer which have
//! not been read out yet
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return number of data words present in buffer which have not been read
//! out yet
//!
//! \note there could be lag due to synchronization, hence value is accurate
//! only when no current reception is happening
//
//*****************************************************************************
static inline uint16_t
FSI_getRxWordCount(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint16_t *)(base + 0xFU))) &
0x1F00U) >>
8U);
}
//*****************************************************************************
//
//! \brief Enables the frame watchdog counter logic to count every time it
//! start to receive a frame
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] wdRef reference value for ping watchdog time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxFrameWatchdog(uint32_t base, uint32_t wdRef)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(base + 0x12U))) = wdRef;
(*((volatile uint16_t *)(base + 0x10U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the frame watchdog counter logic
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxFrameWatchdog(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x10U))) &= ~0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Returns current value of frame watchdog counter
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return current value of frame watchdog counter
//
//*****************************************************************************
static inline uint32_t
FSI_getRxFrameWatchdogCounter(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(base + 0x14U))));
}
//*****************************************************************************
//
//! \brief Enables the ping watchdog counter logic and once the set time
//! elapses it will indicate ping watchdog time-out has occurred
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] wdRef reference value for ping watchdog time-out counter
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxPingWatchdog(uint32_t base, uint32_t wdRef)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(base + 0x18U))) = wdRef;
(*((volatile uint16_t *)(base + 0x16U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the ping watchdog counter logic
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxPingWatchdog(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x16U))) &= ~0x2U;
__edis();
}
//*****************************************************************************
//
//! \brief Returns current value of ping watchdog counter
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return current value(32 bit) of ping watchdog counter
//
//*****************************************************************************
static inline uint32_t
FSI_getRxPingWatchdogCounter(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(base + 0x1AU))));
}
//*****************************************************************************
//
//! \brief Returns the value of tag received for last ping frame
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return the tagValue received for last ping frame
//
//*****************************************************************************
static inline uint16_t
FSI_getRxPingTag(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint16_t *)(base + 0x17U))) & 0x1EU) >>
1U);
}
//*****************************************************************************
//
//! \brief Locks the control of all receive control registers,
//! once locked further writes will not take effect until system
//! reset occurs
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_lockRxCtrl(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x1EU))) = ((uint16_t)0x1U |
((0x00A5U) <<
8U));
__edis();
}
//*****************************************************************************
//
//! \brief Sets Rx ECC data on which ECC (SEC-DED) computaion logic runs
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] rxECCdata Data for ECC logic
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxECCData(uint32_t base, uint32_t rxECCdata)
{
//
// Check the arguments.
//
;
(*((volatile uint32_t *)(base + 0x20U))) = rxECCdata;
}
//*****************************************************************************
//
//! \brief Sets received ECC value on which ECC (SEC-DED) computaion logic runs
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] rxECCvalue Received ECC value in a data frame
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_setRxReceivedECCValue(uint32_t base, uint16_t rxECCvalue)
{
//
// Check the arguments.
//
;
//
// ECC value can be passed as 8 bit value in USERDATA field in a frame
//
;
(*((volatile uint16_t *)(base + 0x22U))) = rxECCvalue;
}
//*****************************************************************************
//
//! \brief Returns ECC Corrected data
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return 32 bit ECC corrected data
//
//*****************************************************************************
static inline uint32_t
FSI_getRxECCCorrectedData(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(base + 0x24U))));
}
//*****************************************************************************
//
//! \brief Returns ECC Log details
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return ECC Log value(8 bit)
//
//*****************************************************************************
static inline uint16_t
FSI_getRxECCLog(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0x26U))) &
(0x1U | 0x2U));
}
//*****************************************************************************
//
//! \brief Let user generate interrupt on occurrence of Rx events
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] intNum the type of interrupt to be generated interrupt1
//! or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//! should be generated. Each bit will represent one event,bits for
//! the events on which user want to generate interrupt will be set
//! others remain clear
//!
//! \return None.
//!
//! Example Usage
//! evtFlags = FSI_RX_EVT_PING_WD_TIMEOUT & FSI_RX_INT_TYPE_ERR
//! FSI_enableRxInterrupt(FSI_base,FSI_INT1,evtFlags)
//! Above call will generate interrupt1 on events
//! FSI_RX_INT_PING_WD_TIMEOUT and FSI_RX_INT_TYPE_ERR
//
//*****************************************************************************
static inline void
FSI_enableRxInterrupt(uint32_t base, FSI_InterruptNum intNum,
uint16_t intFlags)
{
//
// Check the arguments.
//
;
__eallow();
if(intNum == FSI_INT1)
{
(*((volatile uint16_t *)(base + 0x1CU))) |= (intFlags &
(0x7FFFU));
}
else
{
(*((volatile uint16_t *)(base + 0x1DU))) |= (intFlags &
(0x7FFFU));
}
__edis();
}
//*****************************************************************************
//
//! \brief Let user disable interrupt generation on Rx events
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] intNum the type of interrupt to be generated interrupt1
//! or interrupt2
//! \param[in] intFlags contains list of events on which interrupt
//! generation has to be disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxInterrupt(uint32_t base, FSI_InterruptNum intNum,
uint16_t intFlags)
{
//
// Check the arguments.
//
;
__eallow();
if(intNum == FSI_INT1)
{
(*((volatile uint16_t *)(base + 0x1CU))) &= ~(intFlags &
(0x7FFFU));
}
else
{
(*((volatile uint16_t *)(base + 0x1DU))) &= ~(intFlags &
(0x7FFFU));
}
__edis();
}
//*****************************************************************************
//
//! \brief Returns address of Rx data buffer
//!
//! \details Data buffer is consisting of 16 words from offset- 0x40 to 0x4e
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return Rx data buffer address
//
//*****************************************************************************
static inline uint32_t
FSI_getRxBufferAddress(uint32_t base)
{
//
// Check the arguments.
//
;
return(base + (0x40U + (0U)));
}
//*****************************************************************************
//
//! \brief Sets the Rx Frame Reference Tag Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming frame tag.
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] refVal is the Rx frame reference tag value to be set
//!
//! \return Rx data buffer address
//
//*****************************************************************************
static inline void
FSI_setRxFrameTagRef(uint32_t base, uint16_t refVal)
{
//
// Check the arguments.
//
;
__eallow();
//
// Sets the Rx frame tag reference.
//
(*((volatile uint16_t *)(base + 0x28U))) =
(((*((volatile uint16_t *)(base + 0x28U))) &
~((uint16_t)0xFU)) |
(refVal << 0U));
__edis();
}
//*****************************************************************************
//
//! \brief Returns the Rx Frame Reference Tag Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming frame tag.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return Rx frame reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxFrameTagRef(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Returns the Rx frame tag reference.
//
return(((*((volatile uint16_t *)(base + 0x28U))) &
0xFU) >> 0U);
}
//*****************************************************************************
//
//! \brief Sets the Rx Frame Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] maskVal is the Rx frame tag mask value to be set
//!
//! \return Rx frame tag mask
//
//*****************************************************************************
static inline void
FSI_setRxFrameTagMask(uint32_t base, uint16_t maskVal)
{
//
// Check the arguments.
//
;
__eallow();
//
// Sets the Rx frame tag mask.
//
(*((volatile uint16_t *)(base + 0x28U))) =
(((*((volatile uint16_t *)(base + 0x28U))) &
~((uint16_t)0xF0U)) |
(maskVal << 4U));
__edis();
}
//*****************************************************************************
//
//! \brief Returns the Rx Frame Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return Rx frame reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxFrameTagMask(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Returns the frame tag mask.
//
return(((*((volatile uint16_t *)(base + 0x28U))) &
0xF0U) >> 4U);
}
//*****************************************************************************
//
//! \brief Enables the Rx Frame Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxFrameTagCompare(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enables the frame tag compare mode.
//
(*((volatile uint16_t *)(base + 0x28U))) |= 0x100U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the Rx Frame Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxFrameTagCompare(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Disables the Rx frame tag compare mode.
//
(*((volatile uint16_t *)(base + 0x28U))) &=
~(uint16_t)0x100U;
__edis();
}
//*****************************************************************************
//
//! \brief Enables the Rx Frame Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxFrameBroadcast(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enables Rx frame broadcast mode.
//
(*((volatile uint16_t *)(base + 0x28U))) |= 0x200U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the Rx Frame Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxFrameBroadcast(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Disables Rx frame broadcast mode.
//
(*((volatile uint16_t *)(base + 0x28U))) &=
~(uint16_t)0x200U;
__edis();
}
//
// ping frame related APIs
//
//*****************************************************************************
//
//! \brief Sets the Rx Ping Tag Reference Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming ping tag.
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] refVal is the Rx frame reference tag value to be set
//!
//! \return Rx data buffer address
//
//*****************************************************************************
static inline void
FSI_setRxPingTagRef(uint32_t base, uint16_t refVal)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set Rx ping tag reference value.
//
(*((volatile uint16_t *)(base + 0x29U))) =
(((*((volatile uint16_t *)(base + 0x29U))) &
~((uint16_t)0xFU)) |
(refVal << 0U));
__edis();
}
//*****************************************************************************
//
//! \brief Returns the Rx Ping Reference Tag Value
//!
//! \details The reference tag is used to check against when comparing the
//! TAG_MASK and the incoming ping tag.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return Rx frame reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxPingTagRef(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Returns Rx ping tag reference.
//
return(((*((volatile uint16_t *)(base + 0x29U))) &
0xFU) >> 0U);
}
//*****************************************************************************
//
//! \brief Sets the Rx Ping Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] maskVal is the Rx frame tag mask value to be set
//!
//! \return Rx ping tag mask
//
//*****************************************************************************
static inline void
FSI_setRxPingTagMask(uint32_t base, uint16_t maskVal)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set Rx ping tag mask.
//
(*((volatile uint16_t *)(base + 0x29U))) =
(((*((volatile uint16_t *)(base + 0x29U))) &
~((uint16_t)0xF0U)) |
(maskVal << 4U));
__edis();
}
//*****************************************************************************
//
//! \brief Returns the Rx Ping Tag Mask Value
//!
//! \details Any bit position set to 0 will be used in the comparison of
//! incoming tag & the reference tag. A bit position set to 1 will be ignored
//! in the tag comparison.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return Rx ping reference tag
//
//*****************************************************************************
static inline uint16_t
FSI_getRxPingTagMask(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Returns ping tag mask.
//
return(((*((volatile uint16_t *)(base + 0x29U))) &
0xF0U) >> 4U);
}
//*****************************************************************************
//
//! \brief Enables the Rx Ping Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxPingTagCompare(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enables the Rx ping tag compare mode.
//
(*((volatile uint16_t *)(base + 0x29U))) |= 0x100U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the Rx Ping Compare Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxPingTagCompare(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Disables Rx ping tag compare mode.
//
(*((volatile uint16_t *)(base + 0x29U))) &=
~(uint16_t)0x100U;
__edis();
}
//*****************************************************************************
//
//! \brief Enables the Rx Ping Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_enableRxPingBroadcast(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enables the Rx ping broadcast mode.
//
(*((volatile uint16_t *)(base + 0x29U))) |= 0x200U;
__edis();
}
//*****************************************************************************
//
//! \brief Disables the Rx Ping Broadcast Mode
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
static inline void
FSI_disableRxPingBroadcast(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Disables the Rx ping broadcast.
//
(*((volatile uint16_t *)(base + 0x29U))) &=
~(uint16_t)0x200U;
__edis();
}
//*****************************************************************************
//
//! \brief Resets frame watchdog,ping watchdog or entire RX module
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] submodule the name of module which is supposed to be reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_resetRxModule(uint32_t base, FSI_RxSubmoduleInReset submodule);
//*****************************************************************************
//
//! \brief Clears resets on frame watchdog,ping watchdog or entire RX module
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] submodule module which is to be brought out of reset
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_clearRxModuleReset(uint32_t base, FSI_RxSubmoduleInReset submodule);
//*****************************************************************************
//
//! \brief Reads data from FSI Rx buffer
//!
//! \param[in] base is the FSI Rx module base address
//! \param[out] array is the address of the array of words to receive the data
//! \param[in] length is the number of words in the array to be received
//! \param[in] bufOffset is the offset in Rx buffer from where data will
//! be read
//!
//! \note This function ensures that not more than 16 words are read and
//! wrap around case is also taken care when more words need to be read
//! wherein last read happens at maximum offset in Rx buffer
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_readRxBuffer(uint32_t base, uint16_t array[], uint16_t length,
uint16_t bufOffset);
//*****************************************************************************
//
//! \brief Adds delay for selected tap line
//!
//! \param[in] base is the FSI Rx module base address
//! \param[in] delayTapType the line for which delay needs to be added
//! it can be either RXCLK,RXD0 or RXD1
//! \param[in] tapValue 5 bit value of the amount of delay to be added
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_configRxDelayLine(uint32_t base, FSI_RxDelayTapType delayTapType,
uint16_t tapValue);
//*****************************************************************************
//
//! \brief Initializes FSI Tx module
//!
//! \details Software based initialization of the FSI transmitter IP. This is
//! typically needed only once during initialization or if the module
//! needs to be reset due to an underrun condition that occurred during
//! operation.
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] prescalar is the user configurable clock divider for PLL input
//! clock
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_performTxInitialization(uint32_t base, uint16_t prescalar);
//*****************************************************************************
//
//! \brief Initializes FSI Rx module
//!
//! \details Software based initialization of the FSI receiver module.This is
//! typically needed only once during initialization. However, if there
//! are framing errors in the received frames, then the receive module
//! needs to be reset so that subsequent frames/packets can be handled
//! fresh.
//!
//! \param[in] base is the FSI Rx module base address
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_performRxInitialization(uint32_t base);
//*****************************************************************************
//
//! \brief Sends Flush pattern sequence
//!
//! \details Flush pattern sequence sent by a FSI transmit module will bring the
//! FSI receive module out of reset so that it will then be ready to
//! receive subsequent frames.
//!
//! \param[in] base is the FSI Tx module base address
//! \param[in] prescalar is the user configurable clock divider for PLL input
//! clock
//!
//! \return None.
//
//*****************************************************************************
extern void
FSI_executeTxFlushSequence(uint32_t base, uint16_t prescalar);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: gpio.h
//
// TITLE: C28x GPIO driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup gpio_api GPIO
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_gpio.h
//
// TITLE: Definitions for the GPIO registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the GPIO register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACTRL register
//
//*************************************************************************************************
// GPIO15
// GPIO23
// GPIO31
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAQSEL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAQSEL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAMUX1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAMUX2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPADIR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAPUD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAINV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAODR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAAMSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAGMUX1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPAGMUX2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACSEL4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPALOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCTRL register
//
//*************************************************************************************************
// GPIO39
// GPIO47
// GPIO55
// GPIO63
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBQSEL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBQSEL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBMUX1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBMUX2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBDIR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBPUD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBINV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBODR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBGMUX1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBGMUX2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCSEL4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCTRL register
//
//*************************************************************************************************
// GPIO231
// GPIO239
// GPIO247
// GPIO255
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHQSEL1 register
//
//*************************************************************************************************
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
// Pin
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHQSEL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHMUX1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHMUX2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHINV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHAMSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHGMUX1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHGMUX2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCSEL4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHCR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPADAT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPASET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPACLEAR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPATOGGLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBDAT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBCLEAR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPBTOGGLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GPHDAT register
//
//*************************************************************************************************
//###########################################################################
//
// FILE: hw_xint.h
//
// TITLE: Definitions for the XINT registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the XINT register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT1CR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT2CR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT3CR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT4CR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT5CR register
//
//*************************************************************************************************
//###########################################################################
//
// FILE: xbar.h
//
// TITLE: C28x X-BAR driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup xbar_api XBAR
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_clbxbar.h
//
// TITLE: Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG0MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG0MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG1MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG1MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG2MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG2MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG3MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG3MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG4MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG4MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG5MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG5MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG6MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG6MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG7MUX0TO15CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG7MUX16TO31CFG register
//
//*************************************************************************************************
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
// CLB-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG0MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG1MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG2MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG3MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG4MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG5MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG6MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIG7MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIGOUTINV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AUXSIGLOCK register
//
//*************************************************************************************************
//###########################################################################
//
// FILE: hw_epwmxbar.h
//
// TITLE: Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP4MUX0TO15CFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP4MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP5MUX0TO15CFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP5MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP7MUX0TO15CFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP7MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP8MUX0TO15CFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP8MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP9MUX0TO15CFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP9MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP10MUX0TO15CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP10MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP11MUX0TO15CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP11MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP12MUX0TO15CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP12MUX16TO31CFG register
//
//*************************************************************************************************
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
// EPWM-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP4MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP5MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP7MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP8MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP9MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP10MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP11MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIP12MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIPOUTINV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRIPLOCK register
//
//*************************************************************************************************
//###########################################################################
//
// FILE: hw_inputxbar.h
//
// TITLE: Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the INPUTSELECTLOCK register
//
//*************************************************************************************************
//###########################################################################
//
// FILE: hw_outputxbar.h
//
// TITLE: Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT1MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT1MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT2MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT2MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT3MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT3MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT4MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT4MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT5MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT5MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT6MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT6MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT7MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT7MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT8MUX0TO15CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT8MUX16TO31CFG register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT1MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT2MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT3MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT4MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT5MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT6MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT7MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUT8MUXENABLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCH register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCHCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCHFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLATCHENABLE register
//
//*************************************************************************************************
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
// OUTPUT-XBAR
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTINV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the OUTPUTLOCK register
//
//*************************************************************************************************
//###########################################################################
//
// FILE: hw_xbar.h
//
// TITLE: Definitions for the XBAR registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR4 register
//
//*************************************************************************************************
//*****************************************************************************
//
// Useful defines used within the driver functions.
// Not intended for use by application code.
//
//*****************************************************************************
//
// To acheive backward compatibilty for previously defined macros naming
// in XBAR
//
//
//OUTPUTXBAR
//
//
//EPWMXBAR
//
//*****************************************************************************
//
// The following values define the muxes parameter for XBAR_enableEPWMMux(),
// XBAR_enableOutputMux(), XBAR_disableEPWMMux(), and
// XBAR_disableOutputMux().
//
//*****************************************************************************
//*****************************************************************************
//
//! The following values define the \e output parameter for
//! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and
//! XBAR_disableOutputMux().
//
//*****************************************************************************
typedef enum
{
XBAR_OUTPUT1 = 0, //!< OUTPUT1 of the Output X-BAR
XBAR_OUTPUT2 = 2, //!< OUTPUT2 of the Output X-BAR
XBAR_OUTPUT3 = 4, //!< OUTPUT3 of the Output X-BAR
XBAR_OUTPUT4 = 6, //!< OUTPUT4 of the Output X-BAR
XBAR_OUTPUT5 = 8, //!< OUTPUT5 of the Output X-BAR
XBAR_OUTPUT6 = 10, //!< OUTPUT6 of the Output X-BAR
XBAR_OUTPUT7 = 12, //!< OUTPUT7 of the Output X-BAR
XBAR_OUTPUT8 = 14, //!< OUTPUT8 of the Output X-BAR
} XBAR_OutputNum;
//*****************************************************************************
//
//! The following values define the \e trip parameter for
//! XBAR_setEPWMMuxConfig(), XBAR_invertEPWMSignal(), XBAR_enableEPWMMux(),
//! and XBAR_disableEPWMMux().
//
//*****************************************************************************
typedef enum
{
XBAR_TRIP4 = 0, //!< TRIP4 of the ePWM X-BAR
XBAR_TRIP5 = 2, //!< TRIP5 of the ePWM X-BAR
XBAR_TRIP7 = 4, //!< TRIP7 of the ePWM X-BAR
XBAR_TRIP8 = 6, //!< TRIP8 of the ePWM X-BAR
XBAR_TRIP9 = 8, //!< TRIP9 of the ePWM X-BAR
XBAR_TRIP10 = 10, //!< TRIP10 of the ePWM X-BAR
XBAR_TRIP11 = 12, //!< TRIP11 of the ePWM X-BAR
XBAR_TRIP12 = 14 //!< TRIP12 of the ePWM X-BAR
} XBAR_TripNum;
//*****************************************************************************
//
// The following values define the trip parameter for XBAR_setCLBMuxConfig(),
// XBAR_enableCLBMux(), and XBAR_disableCLBMux().
//
//*****************************************************************************
typedef enum
{
XBAR_AUXSIG0 = 0,
XBAR_AUXSIG1 = 2,
XBAR_AUXSIG2 = 4,
XBAR_AUXSIG3 = 6,
XBAR_AUXSIG4 = 8,
XBAR_AUXSIG5 = 10,
XBAR_AUXSIG6 = 12,
XBAR_AUXSIG7 = 14
} XBAR_AuxSigNum;
//*****************************************************************************
//
//! The following values define the \e input parameter for XBAR_setInputPin().
//
//*****************************************************************************
typedef enum
{
XBAR_INPUT1, //!< ePWM[TZ1], ePWM[TRIP1], X-BARs, eCAPs
XBAR_INPUT2, //!< ePWM[TZ2], ePWM[TRIP2], X-BARs, eCAPs
XBAR_INPUT3, //!< ePWM[TZ3], ePWM[TRIP3], X-BARs, eCAPs
XBAR_INPUT4, //!< ADC wrappers, X-BARs, XINT1, eCAPs
XBAR_INPUT5, //!< EXTSYNCIN1, X-BARs, XINT2, eCAPs
XBAR_INPUT6, //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3, eCAPs
XBAR_INPUT7, //!< X-BARs, eCAPs
XBAR_INPUT8, //!< X-BARs, eCAPs
XBAR_INPUT9, //!< X-BARs, eCAPs
XBAR_INPUT10, //!< X-BARs, eCAPs
XBAR_INPUT11, //!< X-BARs, eCAPs
XBAR_INPUT12, //!< X-BARs, eCAPs
XBAR_INPUT13, //!< XINT4, X-BARs, eCAPs
XBAR_INPUT14, //!< XINT5, X-BARs, eCAPs
XBAR_INPUT15, //!< eCAPs
XBAR_INPUT16 //!< eCAPs
} XBAR_InputNum;
//*****************************************************************************
//
//! The following values define the \e muxConfig parameter for
//! XBAR_setOutputMuxConfig().
//
//*****************************************************************************
typedef enum
{
//
//OUTPUTXBAR
//
XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH = 0x0000,
XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L = 0x0001,
XBAR_OUT_MUX00_ADCAEVT1 = 0x0002,
XBAR_OUT_MUX00_ECAP1_OUT = 0x0003,
XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL = 0x0200,
XBAR_OUT_MUX01_INPUTXBAR1 = 0x0201,
XBAR_OUT_MUX01_CLB1_OUT4 = 0x0202,
XBAR_OUT_MUX01_ADCCEVT1 = 0x0203,
XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH = 0x0400,
XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L = 0x0401,
XBAR_OUT_MUX02_ADCAEVT2 = 0x0402,
XBAR_OUT_MUX02_ECAP2_OUT = 0x0403,
XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL = 0x0600,
XBAR_OUT_MUX03_INPUTXBAR2 = 0x0601,
XBAR_OUT_MUX03_CLB1_OUT5 = 0x0602,
XBAR_OUT_MUX03_ADCCEVT2 = 0x0603,
XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH = 0x0800,
XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L = 0x0801,
XBAR_OUT_MUX04_ADCAEVT3 = 0x0802,
XBAR_OUT_MUX04_ECAP3_OUT = 0x0803,
XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL = 0x0A00,
XBAR_OUT_MUX05_INPUTXBAR3 = 0x0A01,
XBAR_OUT_MUX05_CLB2_OUT4 = 0x0A02,
XBAR_OUT_MUX05_ADCCEVT3 = 0x0A03,
XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH = 0x0C00,
XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L = 0x0C01,
XBAR_OUT_MUX06_ADCAEVT4 = 0x0C02,
XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL = 0x0E00,
XBAR_OUT_MUX07_INPUTXBAR4 = 0x0E01,
XBAR_OUT_MUX07_CLB2_OUT5 = 0x0E02,
XBAR_OUT_MUX07_ADCCEVT4 = 0x0E03,
XBAR_OUT_MUX08_ADCBEVT1 = 0x1002,
XBAR_OUT_MUX09_INPUTXBAR5 = 0x1201,
XBAR_OUT_MUX09_CLB3_OUT4 = 0x1202,
XBAR_OUT_MUX10_ADCBEVT2 = 0x1402,
XBAR_OUT_MUX11_INPUTXBAR6 = 0x1601,
XBAR_OUT_MUX11_CLB3_OUT5 = 0x1602,
XBAR_OUT_MUX12_ADCBEVT3 = 0x1802,
XBAR_OUT_MUX14_EXTSYNCOUT = 0x1C03,
XBAR_OUT_MUX14_ADCBEVT4 = 0x1C02,
XBAR_OUT_MUX13_ADCSOCA = 0x1A01,
XBAR_OUT_MUX13_CLB4_OUT4 = 0x1A02,
XBAR_OUT_MUX15_ADCSOCB = 0x1E01,
XBAR_OUT_MUX15_CLB4_OUT5 = 0x1E02,
XBAR_OUT_MUX16_SD1FLT1_CEVT1 = 0x2000,
XBAR_OUT_MUX16_SD1FLT1_CEVT1_OR_CEVT2 = 0x2001,
XBAR_OUT_MUX17_SD1FLT1_CEVT2 = 0x2200,
XBAR_OUT_MUX17_CLAHALT = 0x2203,
XBAR_OUT_MUX18_SD1FLT2_CEVT1 = 0x2400,
XBAR_OUT_MUX18_SD1FLT2_CEVT1_OR_CEVT2 = 0x2401,
XBAR_OUT_MUX19_SD1FLT2_CEVT2 = 0x2600,
XBAR_OUT_MUX20_SD1FLT3_CEVT1 = 0x2800,
XBAR_OUT_MUX20_SD1FLT3_CEVT1_OR_CEVT2 = 0x2801,
XBAR_OUT_MUX21_SD1FLT3_CEVT2 = 0x2A00,
XBAR_OUT_MUX21_FSIA_RX_TRIG2 = 0x2A03,
XBAR_OUT_MUX22_SD1FLT4_CEVT1 = 0x2C00,
XBAR_OUT_MUX22_SD1FLT4_CEVT1_OR_CEVT2 = 0x2C01,
XBAR_OUT_MUX23_SD1FLT4_CEVT2 = 0x2E00,
XBAR_OUT_MUX24_SD2FLT1_CEVT1 = 0x3000,
XBAR_OUT_MUX24_SD2FLT1_CEVT1_OR_CEVT2 = 0x3001,
XBAR_OUT_MUX25_SD2FLT1_CEVT2 = 0x3200,
XBAR_OUT_MUX26_SD2FLT2_CEVT1 = 0x3400,
XBAR_OUT_MUX26_SD2FLT2_CEVT1_OR_CEVT2 = 0x3401,
XBAR_OUT_MUX27_SD2FLT2_CEVT2 = 0x3600,
XBAR_OUT_MUX28_SD2FLT3_CEVT1 = 0x3800,
XBAR_OUT_MUX28_SD2FLT3_CEVT1_OR_CEVT2 = 0x3801,
XBAR_OUT_MUX29_SD2FLT3_CEVT2 = 0x3A00,
XBAR_OUT_MUX30_SD2FLT4_CEVT1 = 0x3C00,
XBAR_OUT_MUX30_SD2FLT4_CEVT1_OR_CEVT2 = 0x3C01,
XBAR_OUT_MUX31_SD2FLT4_CEVT2 = 0x3E00,
XBAR_OUT_MUX19_ERRSTS = 0x2603,
XBAR_OUT_MUX30_EPG1_OUT0 = 0x3C03,
XBAR_OUT_MUX31_ERRSTS = 0x3E02,
XBAR_OUT_MUX31_EPG1_OUT1 = 0x3E03,
//
//CLBOUTPUTXBAR
//
XBAR_OUT_MUX00_CLB1_OUT0 = 0x0000,
XBAR_OUT_MUX00_XTRIP_OUT1 = 0x0003,
XBAR_OUT_MUX01_CLB1_OUT1 = 0x0200,
XBAR_OUT_MUX01_XTRIP_OUT2 = 0x0203,
XBAR_OUT_MUX02_CLB1_OUT2 = 0x0400,
XBAR_OUT_MUX03_CLB1_OUT3 = 0x0600,
XBAR_OUT_MUX04_CLB1_OUT4 = 0x0800,
XBAR_OUT_MUX05_CLB1_OUT5 = 0x0A00,
XBAR_OUT_MUX06_CLB1_OUT6 = 0x0C00,
XBAR_OUT_MUX07_CLB1_OUT7 = 0x0E00,
XBAR_OUT_MUX08_CLB2_OUT0 = 0x1000,
XBAR_OUT_MUX08_XTRIP_OUT3 = 0x1003,
XBAR_OUT_MUX09_CLB2_OUT1 = 0x1200,
XBAR_OUT_MUX09_XTRIP_OUT4 = 0x1203,
XBAR_OUT_MUX10_CLB2_OUT2 = 0x1400,
XBAR_OUT_MUX11_CLB2_OUT3 = 0x1600,
XBAR_OUT_MUX12_CLB2_OUT4 = 0x1800,
XBAR_OUT_MUX13_CLB2_OUT5 = 0x1A00,
XBAR_OUT_MUX14_CLB2_OUT6 = 0x1C00,
XBAR_OUT_MUX15_CLB2_OUT7 = 0x1E00,
XBAR_OUT_MUX16_CLB3_OUT0 = 0x2000,
XBAR_OUT_MUX16_XTRIP_OUT5 = 0x2003,
XBAR_OUT_MUX17_CLB3_OUT1 = 0x2200,
XBAR_OUT_MUX17_XTRIP_OUT6 = 0x2203,
XBAR_OUT_MUX18_CLB3_OUT2 = 0x2400,
XBAR_OUT_MUX19_CLB3_OUT3 = 0x2600,
XBAR_OUT_MUX20_CLB3_OUT4 = 0x2800,
XBAR_OUT_MUX21_CLB3_OUT5 = 0x2A00,
XBAR_OUT_MUX22_CLB3_OUT6 = 0x2C00,
XBAR_OUT_MUX23_CLB3_OUT7 = 0x2E00,
XBAR_OUT_MUX24_CLB4_OUT0 = 0x3000,
XBAR_OUT_MUX24_XTRIP_OUT7 = 0x3003,
XBAR_OUT_MUX25_CLB4_OUT1 = 0x3200,
XBAR_OUT_MUX25_XTRIP_OUT8 = 0x3203,
XBAR_OUT_MUX26_CLB4_OUT2 = 0x3400,
XBAR_OUT_MUX27_CLB4_OUT3 = 0x3600,
XBAR_OUT_MUX28_CLB4_OUT4 = 0x3800,
XBAR_OUT_MUX29_CLB4_OUT5 = 0x3A00,
XBAR_OUT_MUX30_CLB4_OUT6 = 0x3C00,
XBAR_OUT_MUX30_EPG1_OUT2 = 0x3C03,
XBAR_OUT_MUX31_CLB4_OUT7 = 0x3E00,
XBAR_OUT_MUX31_EPG1_OUT3 = 0x3E03,
} XBAR_OutputMuxConfig;
//*****************************************************************************
//
//! The following values define the \e muxConfig parameter for
//! XBAR_setEPWMMuxConfig().
//
//*****************************************************************************
typedef enum
{
XBAR_EPWM_MUX00_CMPSS1_CTRIPH = 0x0000,
XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001,
XBAR_EPWM_MUX00_ADCAEVT1 = 0x0002,
XBAR_EPWM_MUX00_ECAP1_OUT = 0x0003,
XBAR_EPWM_MUX01_CMPSS1_CTRIPL = 0x0200,
XBAR_EPWM_MUX01_INPUTXBAR1 = 0x0201,
XBAR_EPWM_MUX01_CLB1_OUT4 = 0x0202,
XBAR_EPWM_MUX01_ADCCEVT1 = 0x0203,
XBAR_EPWM_MUX02_CMPSS2_CTRIPH = 0x0400,
XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401,
XBAR_EPWM_MUX02_ADCAEVT2 = 0x0402,
XBAR_EPWM_MUX02_ECAP2_OUT = 0x0403,
XBAR_EPWM_MUX03_CMPSS2_CTRIPL = 0x0600,
XBAR_EPWM_MUX03_INPUTXBAR2 = 0x0601,
XBAR_EPWM_MUX03_CLB1_OUT5 = 0x0602,
XBAR_EPWM_MUX03_ADCCEVT2 = 0x0603,
XBAR_EPWM_MUX04_CMPSS3_CTRIPH = 0x0800,
XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801,
XBAR_EPWM_MUX04_ADCAEVT3 = 0x0802,
XBAR_EPWM_MUX04_ECAP3_OUT = 0x0803,
XBAR_EPWM_MUX05_CMPSS3_CTRIPL = 0x0A00,
XBAR_EPWM_MUX05_INPUTXBAR3 = 0x0A01,
XBAR_EPWM_MUX05_CLB2_OUT4 = 0x0A02,
XBAR_EPWM_MUX05_ADCCEVT3 = 0x0A03,
XBAR_EPWM_MUX06_CMPSS4_CTRIPH = 0x0C00,
XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01,
XBAR_EPWM_MUX06_ADCAEVT4 = 0x0C02,
XBAR_EPWM_MUX07_CMPSS4_CTRIPL = 0x0E00,
XBAR_EPWM_MUX07_INPUTXBAR4 = 0x0E01,
XBAR_EPWM_MUX07_CLB2_OUT5 = 0x0E02,
XBAR_EPWM_MUX07_ADCCEVT4 = 0x0E03,
XBAR_EPWM_MUX08_ADCBEVT1 = 0x1002,
XBAR_EPWM_MUX09_INPUTXBAR5 = 0x1201,
XBAR_EPWM_MUX09_CLB3_OUT4 = 0x1202,
XBAR_EPWM_MUX10_ADCBEVT2 = 0x1402,
XBAR_EPWM_MUX11_INPUTXBAR6 = 0x1601,
XBAR_EPWM_MUX11_CLB3_OUT5 = 0x1602,
XBAR_EPWM_MUX12_ADCBEVT3 = 0x1802,
XBAR_EPWM_MUX13_ADCSOCA = 0x1A01,
XBAR_EPWM_MUX13_CLB4_OUT4 = 0x1A02,
XBAR_EPWM_MUX14_ADCBEVT4 = 0x1C02,
XBAR_EPWM_MUX14_EXTSYNCOUT = 0x1C03,
XBAR_EPWM_MUX15_ADCSOCB = 0x1E01,
XBAR_EPWM_MUX15_CLB4_OUT5 = 0x1E02,
XBAR_EPWM_MUX16_SD1FLT1_CEVT1 = 0x2000,
XBAR_EPWM_MUX16_SD1FLT1_CEVT1_OR_CEVT2 = 0x2001,
XBAR_EPWM_MUX16_SD1FLT1_COMPZ = 0x2002,
XBAR_EPWM_MUX16_SD1FLT1_DRINT = 0x2003,
XBAR_EPWM_MUX17_SD1FLT1_CEVT2 = 0x2200,
XBAR_EPWM_MUX17_INPUTXBAR7 = 0x2201,
XBAR_EPWM_MUX17_CLAHALT = 0x2203,
XBAR_EPWM_MUX18_SD1FLT2_CEVT1 = 0x2400,
XBAR_EPWM_MUX18_SD1FLT2_CEVT1_OR_CEVT2 = 0x2401,
XBAR_EPWM_MUX18_SD1FLT2_COMPZ = 0x2402,
XBAR_EPWM_MUX18_SD1FLT2_DRINT = 0x2403,
XBAR_EPWM_MUX19_SD1FLT2_CEVT2 = 0x2600,
XBAR_EPWM_MUX19_INPUTXBAR8 = 0x2601,
XBAR_EPWM_MUX19_ERRORSTS = 0x2603,
XBAR_EPWM_MUX20_SD1FLT3_CEVT1 = 0x2800,
XBAR_EPWM_MUX20_SD1FLT3_CEVT1_OR_CEVT2 = 0x2801,
XBAR_EPWM_MUX20_SD1FLT3_COMPZ = 0x2802,
XBAR_EPWM_MUX20_SD1FLT3_DRINT = 0x2803,
XBAR_EPWM_MUX21_SD1FLT3_CEVT2 = 0x2A00,
XBAR_EPWM_MUX21_INPUTXBAR9 = 0x2A01,
XBAR_EPWM_MUX22_SD1FLT4_CEVT1 = 0x2C00,
XBAR_EPWM_MUX22_SD1FLT4_CEVT1_OR_CEVT2 = 0x2C01,
XBAR_EPWM_MUX22_SD1FLT4_COMPZ = 0x2C02,
XBAR_EPWM_MUX22_SD1FLT4_DRINT = 0x2C03,
XBAR_EPWM_MUX23_SD1FLT4_CEVT2 = 0x2E00,
XBAR_EPWM_MUX23_INPUTXBAR10 = 0x2E01,
XBAR_EPWM_MUX24_SD2FLT1_CEVT1 = 0x3000,
XBAR_EPWM_MUX24_SD2FLT1_CEVT1_OR_CEVT2 = 0x3001,
XBAR_EPWM_MUX24_SD2FLT1_COMPZ = 0x3002,
XBAR_EPWM_MUX24_SD2FLT1_DRINT = 0x3003,
XBAR_EPWM_MUX25_SD2FLT1_CEVT2 = 0x3200,
XBAR_EPWM_MUX25_INPUTXBAR11 = 0x3201,
XBAR_EPWM_MUX25_MCAN_FEVT0 = 0x3202,
XBAR_EPWM_MUX26_SD2FLT2_CEVT1 = 0x3400,
XBAR_EPWM_MUX26_SD2FLT2_CEVT1_OR_CEVT2 = 0x3401,
XBAR_EPWM_MUX26_SD2FLT2_COMPZ = 0x3402,
XBAR_EPWM_MUX26_SD2FLT2_DRINT = 0x3403,
XBAR_EPWM_MUX27_SD2FLT2_CEVT2 = 0x3600,
XBAR_EPWM_MUX27_INPUTXBAR12 = 0x3601,
XBAR_EPWM_MUX27_MCAN_FEVT1 = 0x3602,
XBAR_EPWM_MUX28_SD2FLT3_CEVT1 = 0x3800,
XBAR_EPWM_MUX28_SD2FLT3_CEVT1_OR_CEVT2 = 0x3801,
XBAR_EPWM_MUX28_SD2FLT3_COMPZ = 0x3802,
XBAR_EPWM_MUX28_SD2FLT3_DRINT = 0x3803,
XBAR_EPWM_MUX29_SD2FLT3_CEVT2 = 0x3A00,
XBAR_EPWM_MUX29_INPUTXBAR13 = 0x3A01,
XBAR_EPWM_MUX29_MCAN_FEVT2 = 0x3A02,
XBAR_EPWM_MUX30_SD2FLT4_CEVT1 = 0x3C00,
XBAR_EPWM_MUX30_SD2FLT4_CEVT1_OR_CEVT2 = 0x3C01,
XBAR_EPWM_MUX30_SD2FLT4_COMPZ = 0x3C02,
XBAR_EPWM_MUX30_SD2FLT4_DRINT = 0x3C03,
XBAR_EPWM_MUX31_SD2FLT4_CEVT2 = 0x3E00,
XBAR_EPWM_MUX31_ERRORSTS = 0x3E02,
XBAR_EPWM_MUX31_INPUTXBAR14 = 0x3E01
} XBAR_EPWMMuxConfig;
//*****************************************************************************
//
// The following values define the muxConfig parameter for
// XBAR_setCLBMuxConfig().
//
//*****************************************************************************
typedef enum
{
XBAR_CLB_MUX00_CMPSS1_CTRIPH = 0x0000,
XBAR_CLB_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001,
XBAR_CLB_MUX00_ADCAEVT1 = 0x0002,
XBAR_CLB_MUX00_ECAP1_OUT = 0x0003,
XBAR_CLB_MUX01_CMPSS1_CTRIPL = 0x0200,
XBAR_CLB_MUX01_INPUTXBAR1 = 0x0201,
XBAR_CLB_MUX01_CLB1_OUT4 = 0x0202,
XBAR_CLB_MUX01_ADCCEVT1 = 0x0203,
XBAR_CLB_MUX02_CMPSS2_CTRIPH = 0x0400,
XBAR_CLB_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401,
XBAR_CLB_MUX02_ADCAEVT2 = 0x0402,
XBAR_CLB_MUX02_ECAP2_OUT = 0x0403,
XBAR_CLB_MUX03_CMPSS2_CTRIPL = 0x0600,
XBAR_CLB_MUX03_INPUTXBAR2 = 0x0601,
XBAR_CLB_MUX03_CLB1_OUT5 = 0x0602,
XBAR_CLB_MUX03_ADCCEVT2 = 0x0603,
XBAR_CLB_MUX04_CMPSS3_CTRIPH = 0x0800,
XBAR_CLB_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801,
XBAR_CLB_MUX04_ADCAEVT3 = 0x0802,
XBAR_CLB_MUX04_ECAP3_OUT = 0x0803,
XBAR_CLB_MUX05_CMPSS3_CTRIPL = 0x0A00,
XBAR_CLB_MUX05_INPUTXBAR3 = 0x0A01,
XBAR_CLB_MUX05_CLB2_OUT4 = 0x0A02,
XBAR_CLB_MUX05_ADCCEVT3 = 0x0A03,
XBAR_CLB_MUX06_CMPSS4_CTRIPH = 0x0C00,
XBAR_CLB_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01,
XBAR_CLB_MUX06_ADCAEVT4 = 0x0C02,
XBAR_CLB_MUX07_CMPSS4_CTRIPL = 0x0E00,
XBAR_CLB_MUX07_INPUTXBAR4 = 0x0E01,
XBAR_CLB_MUX07_CLB2_OUT5 = 0x0E02,
XBAR_CLB_MUX07_ADCCEVT4 = 0x0E03,
XBAR_CLB_MUX08_ADCBEVT1 = 0x1002,
XBAR_CLB_MUX09_INPUTXBAR5 = 0x1201,
XBAR_CLB_MUX09_CLB3_OUT4 = 0x1202,
XBAR_CLB_MUX10_ADCBEVT2 = 0x1402,
XBAR_CLB_MUX11_INPUTXBAR6 = 0x1601,
XBAR_CLB_MUX11_CLB3_OUT5 = 0x1602,
XBAR_CLB_MUX12_ADCBEVT3 = 0x1802,
XBAR_CLB_MUX13_ADCSOCA = 0x1A01,
XBAR_CLB_MUX13_CLB4_OUT4 = 0x1A02,
XBAR_CLB_MUX14_ADCBEVT4 = 0x1C02,
XBAR_CLB_MUX14_EXTSYNCOUT = 0x1C03,
XBAR_CLB_MUX15_ADCSOCB = 0x1E01,
XBAR_CLB_MUX15_CLB4_OUT5 = 0x1E02,
XBAR_CLB_MUX16_SD1FLT1_COMPH = 0x2000,
XBAR_CLB_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001,
XBAR_CLB_MUX16_SD1FLT1_COMPZ = 0x2002,
XBAR_CLB_MUX16_SD1FLT1_DRINT = 0x2003,
XBAR_CLB_MUX17_SD1FLT1_COMPL = 0x2200,
XBAR_CLB_MUX17_INPUTXBAR7 = 0x2201,
XBAR_CLB_MUX17_CLAHALT = 0x2203,
XBAR_CLB_MUX18_SD1FLT2_COMPH = 0x2400,
XBAR_CLB_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401,
XBAR_CLB_MUX18_SD1FLT2_COMPZ = 0x2402,
XBAR_CLB_MUX18_SD1FLT2_DRINT = 0x2403,
XBAR_CLB_MUX19_SD1FLT2_COMPL = 0x2600,
XBAR_CLB_MUX19_INPUTXBAR8 = 0x2601,
XBAR_CLB_MUX19_ERRORSTS = 0x2603,
XBAR_CLB_MUX20_SD1FLT3_COMPH = 0x2800,
XBAR_CLB_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801,
XBAR_CLB_MUX20_SD1FLT3_COMPZ = 0x2802,
XBAR_CLB_MUX20_SD1FLT3_DRINT = 0x2803,
XBAR_CLB_MUX21_SD1FLT3_COMPL = 0x2A00,
XBAR_CLB_MUX21_INPUTXBAR9 = 0x2A01,
XBAR_CLB_MUX22_SD1FLT4_COMPH = 0x2C00,
XBAR_CLB_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01,
XBAR_CLB_MUX22_SD1FLT4_COMPZ = 0x2C02,
XBAR_CLB_MUX22_SD1FLT4_DRINT = 0x2C03,
XBAR_CLB_MUX23_SD1FLT4_COMPL = 0x2E00,
XBAR_CLB_MUX23_INPUTXBAR10 = 0x2E01,
XBAR_CLB_MUX24_SD2FLT1_COMPH = 0x3000,
XBAR_CLB_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001,
XBAR_CLB_MUX24_SD2FLT1_COMPZ = 0x3002,
XBAR_CLB_MUX24_SD2FLT1_DRINT = 0x3003,
XBAR_CLB_MUX25_SD2FLT1_COMPL = 0x3200,
XBAR_CLB_MUX25_INPUTXBAR11 = 0x3201,
XBAR_CLB_MUX25_MCAN_FEVT0 = 0x3202,
XBAR_CLB_MUX26_SD2FLT2_COMPH = 0x3400,
XBAR_CLB_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401,
XBAR_CLB_MUX26_SD2FLT2_COMPZ = 0x3402,
XBAR_CLB_MUX26_SD2FLT2_DRINT = 0x3403,
XBAR_CLB_MUX27_SD2FLT2_COMPL = 0x3600,
XBAR_CLB_MUX27_INPUTXBAR12 = 0x3601,
XBAR_CLB_MUX27_MCAN_FEVT1 = 0x3602,
XBAR_CLB_MUX28_SD2FLT3_COMPH = 0x3800,
XBAR_CLB_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801,
XBAR_CLB_MUX28_SD2FLT3_COMPZ = 0x3802,
XBAR_CLB_MUX28_SD2FLT3_DRINT = 0x3803,
XBAR_CLB_MUX29_SD2FLT3_COMPL = 0x3A00,
XBAR_CLB_MUX29_INPUTXBAR13 = 0x3A01,
XBAR_CLB_MUX29_MCAN_FEVT2 = 0x3A02,
XBAR_CLB_MUX30_SD2FLT4_COMPH = 0x3C00,
XBAR_CLB_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01,
XBAR_CLB_MUX30_SD2FLT4_COMPZ = 0x3C02,
XBAR_CLB_MUX30_SD2FLT4_DRINT = 0x3C03,
XBAR_CLB_MUX31_SD2FLT4_COMPL = 0x3E00,
XBAR_CLB_MUX31_ERRORSTS = 0x3E02,
XBAR_CLB_MUX31_INPUTXBAR14 = 0x3E01
} XBAR_CLBMuxConfig;
//*****************************************************************************
//
//! The following values define the \e inputFlag parameter for
//! XBAR_getInputFlagStatus() and XBAR_clearInputFlag().
//
//*****************************************************************************
typedef enum
{
//
// XBARFLG1
//
XBAR_INPUT_FLG_CMPSS1_CTRIPL = 0x0000,
XBAR_INPUT_FLG_CMPSS1_CTRIPH = 0x0001,
XBAR_INPUT_FLG_CMPSS2_CTRIPL = 0x0002,
XBAR_INPUT_FLG_CMPSS2_CTRIPH = 0x0003,
XBAR_INPUT_FLG_CMPSS3_CTRIPL = 0x0004,
XBAR_INPUT_FLG_CMPSS3_CTRIPH = 0x0005,
XBAR_INPUT_FLG_CMPSS4_CTRIPL = 0x0006,
XBAR_INPUT_FLG_CMPSS4_CTRIPH = 0x0007,
XBAR_INPUT_FLG_CMPSS1_CTRIPOUTL = 0x0010,
XBAR_INPUT_FLG_CMPSS1_CTRIPOUTH = 0x0011,
XBAR_INPUT_FLG_CMPSS2_CTRIPOUTL = 0x0012,
XBAR_INPUT_FLG_CMPSS2_CTRIPOUTH = 0x0013,
XBAR_INPUT_FLG_CMPSS3_CTRIPOUTL = 0x0014,
XBAR_INPUT_FLG_CMPSS3_CTRIPOUTH = 0x0015,
XBAR_INPUT_FLG_CMPSS4_CTRIPOUTL = 0x0016,
XBAR_INPUT_FLG_CMPSS4_CTRIPOUTH = 0x0017,
//
// XBARFLG2
//
XBAR_INPUT_FLG_INPUT1 = 0x0100,
XBAR_INPUT_FLG_INPUT2 = 0x0101,
XBAR_INPUT_FLG_INPUT3 = 0x0102,
XBAR_INPUT_FLG_INPUT4 = 0x0103,
XBAR_INPUT_FLG_INPUT5 = 0x0104,
XBAR_INPUT_FLG_INPUT6 = 0x0105,
XBAR_INPUT_FLG_ADCSOCA = 0x0106,
XBAR_INPUT_FLG_ADCSOCB = 0x0107,
XBAR_INPUT_FLG_INPUT7 = 0x0108,
XBAR_INPUT_FLG_INPUT8 = 0x0109,
XBAR_INPUT_FLG_INPUT9 = 0x010A,
XBAR_INPUT_FLG_INPUT10 = 0x010B,
XBAR_INPUT_FLG_INPUT11 = 0x010C,
XBAR_INPUT_FLG_INPUT12 = 0x010D,
XBAR_INPUT_FLG_INPUT13 = 0x010E,
XBAR_INPUT_FLG_INPUT14 = 0x010F,
XBAR_INPUT_FLG_ECAP1_OUT = 0x0110,
XBAR_INPUT_FLG_ECAP2_OUT = 0x0111,
XBAR_INPUT_FLG_ECAP3_OUT = 0x0112,
XBAR_INPUT_FLG_EXTSYNCOUT = 0x0116,
XBAR_INPUT_FLG_ADCAEVT1 = 0x0117,
XBAR_INPUT_FLG_ADCAEVT2 = 0x0118,
XBAR_INPUT_FLG_ADCAEVT3 = 0x0119,
XBAR_INPUT_FLG_ADCAEVT4 = 0x011A,
XBAR_INPUT_FLG_ADCCEVT1 = 0x011F,
//
// XBARFLG3
//
XBAR_INPUT_FLG_ADCCEVT2 = 0x0200,
XBAR_INPUT_FLG_ADCCEVT3 = 0x0201,
XBAR_INPUT_FLG_ADCCEVT4 = 0x0202,
XBAR_INPUT_FLG_SD1FLT1_COMPL = 0x0207,
XBAR_INPUT_FLG_SD1FLT1_COMPH = 0x0208,
XBAR_INPUT_FLG_SD1FLT2_COMPL = 0x0209,
XBAR_INPUT_FLG_SD1FLT2_COMPH = 0x020A,
XBAR_INPUT_FLG_SD1FLT3_COMPL = 0x020B,
XBAR_INPUT_FLG_SD1FLT3_COMPH = 0x020C,
XBAR_INPUT_FLG_SD1FLT4_COMPL = 0x020D,
XBAR_INPUT_FLG_SD1FLT4_COMPH = 0x020E,
XBAR_INPUT_FLG_SD2FLT1_COMPL = 0x020F,
XBAR_INPUT_FLG_SD2FLT1_COMPH = 0x0210,
XBAR_INPUT_FLG_SD2FLT2_COMPL = 0x0211,
XBAR_INPUT_FLG_SD2FLT2_COMPH = 0x0212,
XBAR_INPUT_FLG_SD2FLT3_COMPL = 0x0213,
XBAR_INPUT_FLG_SD2FLT3_COMPH = 0x0214,
XBAR_INPUT_FLG_SD2FLT4_COMPL = 0x0215,
XBAR_INPUT_FLG_SD2FLT4_COMPH = 0x0216,
XBAR_INPUT_FLG_SD1FLT1_COMPZ = 0x0218,
XBAR_INPUT_FLG_SD1FLT1_DRINT = 0x0219,
XBAR_INPUT_FLG_SD1FLT2_COMPZ = 0x021A,
XBAR_INPUT_FLG_SD1FLT2_DRINT = 0x021B,
XBAR_INPUT_FLG_SD1FLT3_COMPZ = 0x021C,
XBAR_INPUT_FLG_SD1FLT3_DRINT = 0x021D,
XBAR_INPUT_FLG_SD1FLT4_COMPZ = 0x021E,
XBAR_INPUT_FLG_SD1FLT4_DRINT = 0x021F,
//
// XBARFLG4
//
XBAR_INPUT_FLG_SD2FLT1_COMPZ = 0x0300,
XBAR_INPUT_FLG_SD2FLT1_DRINT = 0x0301,
XBAR_INPUT_FLG_SD2FLT2_COMPZ = 0x0302,
XBAR_INPUT_FLG_SD2FLT2_DRINT = 0x0303,
XBAR_INPUT_FLG_SD2FLT3_COMPZ = 0x0304,
XBAR_INPUT_FLG_SD2FLT3_DRINT = 0x0305,
XBAR_INPUT_FLG_SD2FLT4_COMPZ = 0x0306,
XBAR_INPUT_FLG_SD2FLT4_DRINT = 0x0307,
XBAR_INPUT_FLG_EMAC_PPS0 = 0x0308,
XBAR_INPUT_FLG_MCANA_FEVT0 = 0x0309,
XBAR_INPUT_FLG_MCANA_FEVT1 = 0x030A,
XBAR_INPUT_FLG_MCANA_FEVT2 = 0x030B,
XBAR_INPUT_FLG_CLB1_OUT4 = 0x0310,
XBAR_INPUT_FLG_CLB1_OUT5 = 0x0311,
XBAR_INPUT_FLG_CLB2_OUT4 = 0x0312,
XBAR_INPUT_FLG_CLB2_OUT5 = 0x0313,
XBAR_INPUT_FLG_CLB3_OUT4 = 0x0314,
XBAR_INPUT_FLG_CLB3_OUT5 = 0x0315,
XBAR_INPUT_FLG_CLB4_OUT4 = 0x0316,
XBAR_INPUT_FLG_CLB4_OUT5 = 0x0317,
XBAR_INPUT_FLG_ERRORSTS_ERROR = 0x031C,
XBAR_INPUT_FLG_CLAHALT = 0x031F,
} XBAR_InputFlag;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a X-BAR base address.
//!
//! \param base is the base address of the X-BAR.
//!
//! This function determines if a X-BAR base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the Output X-BAR mux values to be passed to the output signal.
//!
//! \param base specifies the X-BAR Enable register base address.
//! \param output is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be enabled.
//!
//! This function enables the mux values to be passed to the X-BAR output
//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is
//! the output number between 1 and 8 inclusive.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! The \e muxes parameter is a bit field of the muxes being enabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be OR'd together to enable several
//! muxes on an output at the same time. For example, passing this function
//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_enableOutputMux(uint32_t base, XBAR_OutputNum output, uint32_t muxes)
{
uint16_t outputNum = (uint16_t)output;
//
// Check the arguments.
//
;
//
// Set the enable bit.
//
__eallow();
(*((volatile uint32_t *)(base + 0x20U + outputNum))) |= muxes;
__edis();
}
//*****************************************************************************
//
//! Disables the Output X-BAR mux values from being passed to the output.
//!
//! \param base specifies the X-BAR Enable Register base address.
//! \param output is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be disabled.
//!
//! This function disables the mux values from being passed to the X-BAR output
//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is
//! the output number between 1 and 8 inclusive.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! The \e muxes parameter is a bit field of the muxes being disabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be OR'd together to disable several
//! muxes on an output at the same time. For example, passing this function
//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would disable muxes 4 and 10.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_disableOutputMux(uint32_t base, XBAR_OutputNum output, uint32_t muxes)
{
uint16_t outputNum = (uint16_t)output;
//
// Check the arguments.
//
;
//
// Clear the enable bit.
//
__eallow();
(*((volatile uint32_t *)(base + 0x20U + outputNum))) &= ~(muxes);
__edis();
}
//*****************************************************************************
//
//! Enables or disables the output latch to drive the selected output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8.
//! \param enable is a flag that determines whether or not the latch is
//! selected to drive the X-BAR output.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function sets the Output X-BAR output signal latch mode. If the
//! \e enable parameter is \b true, the output specified by \e output will be
//! driven by the output latch.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_setOutputLatchMode(uint32_t base, XBAR_OutputNum output, _Bool enable)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set or clear the latch setting bit based on the enable parameter.
//
if(enable)
{
(*((volatile uint16_t *)(base + 0x36U))) |=
0x1U << ((uint16_t)output / 2U);
}
else
{
(*((volatile uint16_t *)(base + 0x36U))) &=
~(0x1U << ((uint16_t)output / 2U));
}
__edis();
}
//*****************************************************************************
//
//! Returns the status of the output latch
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being checked.
//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! \return Returns \b true if the output corresponding to \e output was
//! triggered. If not, it will return \b false.
//
//*****************************************************************************
static inline _Bool
XBAR_getOutputLatchStatus(uint32_t base, XBAR_OutputNum output)
{
//
// Check the arguments.
//
;
//
// Get the status of the Output X-BAR output latch.
//
return(((*((volatile uint16_t *)(base + 0x30U))) &
(0x1U << ((uint16_t)output / 2U))) != 0U);
}
//*****************************************************************************
//
//! Clears the output latch for the specified output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function clears the Output X-BAR output latch. The output to be
//! configured is specified by the \e output parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_clearOutputLatch(uint32_t base, XBAR_OutputNum output)
{
//
// Check the arguments.
//
;
//
// Set the bit that clears the corresponding OUTPUTLATCH bit.
//
(*((volatile uint16_t *)(base + 0x32U))) |=
0x1U << ((uint16_t)output / 2U);
}
//*****************************************************************************
//
//! Forces the output latch for the specified output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function forces the Output X-BAR output latch. The output to be
//! configured is specified by the \e output parameter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_forceOutputLatch(uint32_t base, XBAR_OutputNum output)
{
//
// Check the arguments.
//
;
//
// Set the bit that forces the corresponding OUTPUTLATCH bit.
//
(*((volatile uint16_t *)(base + 0x34U))) =
(uint16_t)0x1U << ((uint16_t)output / 2U);
}
//*****************************************************************************
//
//! Configures the polarity of an Output X-BAR output.
//!
//! \param base specifies the X-BAR base address.
//! \param output is the X-BAR output being configured.
//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8.
//! \param invert is a flag that determines whether the output is active-high
//! or active-low.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! This function inverts the Output X-BAR signal if the \e invert parameter is
//! \b true. If \e invert is \b false, the signal will be passed as is. The
//! \e output parameter is a value \b XBAR_OUTPUTy where y is the output
//! number between 1 and 8 inclusive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_invertOutputSignal(uint32_t base, XBAR_OutputNum output, _Bool invert)
{
//
// Check the arguments.
//
;
//
// Set or clear the polarity setting bit based on the invert parameter.
//
__eallow();
if(invert)
{
(*((volatile uint16_t *)(base + 0x38U))) |=
0x1U << ((uint16_t)output / 2U);
}
else
{
(*((volatile uint16_t *)(base + 0x38U))) &=
~(0x1U << ((uint16_t)output / 2U));
}
__edis();
}
//*****************************************************************************
//
//! Enables the ePWM X-BAR mux values to be passed to an ePWM module.
//!
//! \param trip is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be enabled.
//!
//! This function enables the mux values to be passed to the X-BAR trip
//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is
//! the number of the trip signal on the ePWM.
//!
//! The \e muxes parameter is a bit field of the muxes being enabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! enable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_enableEPWMMux(XBAR_TripNum trip, uint32_t muxes)
{
//
// Set the enable bit.
//
__eallow();
(*((volatile uint32_t *)((0x00007A00U + 0x20U) + (uint32_t)trip))) |= muxes;
__edis();
}
//*****************************************************************************
//
//! Disables the ePWM X-BAR mux values to be passed to an ePWM module.
//!
//! \param trip is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be disabled.
//!
//! This function disables the mux values to be passed to the X-BAR trip
//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is
//! the number of the trip signal on the ePWM.
//!
//! The \e muxes parameter is a bit field of the muxes being disabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! disable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_disableEPWMMux(XBAR_TripNum trip, uint32_t muxes)
{
//
// Clear the enable bit.
//
__eallow();
(*((volatile uint32_t *)((0x00007A00U + 0x20U) + (uint32_t)trip))) &= ~(muxes);
__edis();
}
//*****************************************************************************
//
//! Configures the polarity of an ePWM X-BAR output.
//!
//! \param trip is the X-BAR output being configured.
//! \param invert is a flag that determines whether the output is active-high
//! or active-low.
//!
//! This function inverts the ePWM X-BAR trip signal if the \e invert
//! parameter is \b true. If \e invert is \b false, the signal will be passed
//! as is. The \e trip parameter is a value \b XBAR_TRIPy where y is
//! the number of the trip signal on the ePWM X-BAR that is being configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_invertEPWMSignal(XBAR_TripNum trip, _Bool invert)
{
//
// Set or clear the polarity setting bit based on the invert parameter.
//
__eallow();
if(invert)
{
(*((volatile uint16_t *)(0x00007A00U + 0x38U))) |=
0x1U << ((uint16_t)trip / 2U);
}
else
{
(*((volatile uint16_t *)(0x00007A00U + 0x38U))) &=
~(0x1U << ((uint16_t)trip / 2U));
}
__edis();
}
//*****************************************************************************
//
//! Sets the GPIO / non-GPIO pin for an Input X-BAR input.
//!
//! \param base specifies the X-BAR base address.
//! \param input is the X-BAR input being configured.
//! \param pin is the identifying number of the pin.
//!
//! The \e base parameter can take base addresses
//! INPUTXBAR_BASE
//! or CLBINPUTXBAR_BASE.
//!
//! This function configures which GPIO is assigned to an Input X-BAR input.
//! The \e input parameter is a value in the form of a define \b XBAR_INPUTy
//! where y is a the input number for the Input X-BAR.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! For the other non - GPIO values:
//! 0xFFFD: '1' will be driven to the destination
//! 0xFFFE: '1' will be driven to the destination
//! 0xFFFF: '0' will be driven to the destination
//! NOTE: Pin value greater than the available number of GPIO pins on a
//! device (except 0xFFFF) will cause the destination to be driven '1'.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_setInputPin(uint32_t base, XBAR_InputNum input, uint16_t pin)
{
//
// Check the argument.
//
;
;
//
// Write the requested pin to the appropriate input select register.
//
__eallow();
(*((volatile uint16_t *)(base + 0x0U + (uint16_t)input))) = pin;
__edis();
}
//*****************************************************************************
//
//! Locks an input to the Input X-BAR.
//!
//! \param base specifies the X-BAR base address.
//! \param input is an input to the Input X-BAR.
//!
//! This function locks the specific input on the Input X-BAR.
//!
//! The \e base parameter can take base addresses
//! INPUTXBAR_BASE
//! or CLBINPUTXBAR_BASE .
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_lockInput(uint32_t base, XBAR_InputNum input)
{
//
// Check the arguments.
//
;
//
// lock the input in the INPUTSELECTLOCK register.
//
__eallow();
(*((volatile uint32_t *)(base + 0x1EU))) =
1UL << (uint16_t)input;
__edis();
}
//*****************************************************************************
//
//! Locks the Output X-BAR.
//!
//! \param base specifies the X-BAR base address.
//! This function locks the Output X-BAR.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_lockOutput(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Lock the Output X-BAR with the OUTPUTLOCK register.
// Write key 0x5A5A to the KEY bits and 1 to LOCK bit.
//
__eallow();
(*((volatile uint32_t *)(base + 0x3EU))) =
((uint32_t)0x5A5A << 16U) |
(uint32_t)0x1U;
__edis();
}
//*****************************************************************************
//
//! Locks the ePWM X-BAR.
//!
//! This function locks the ePWM X-BAR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_lockEPWM(void)
{
//
// Lock the ePWM X-BAR with the TRIPLOCK register.
// Write key 0x5A5A to the KEY bits and 1 to LOCK bit.
//
__eallow();
(*((volatile uint32_t *)(0x00007A00U + 0x3EU))) =
((uint32_t)0x5A5A << 16U) |
(uint32_t)0x1U;
__edis();
}
//*****************************************************************************
//
//! Enables the CLB X-BAR mux values to be passed to an CLB module.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be enabled.
//!
//! This function enables the mux values to be passed to the X-BAR auxSignal
//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is
//! the number of the signal on the CLB.
//!
//! The \e muxes parameter is a bit field of the muxes being enabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! enable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_enableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes)
{
//
// Set the enable bit.
//
__eallow();
(*((volatile uint32_t *)((0x00007A40U + 0x20U) + (uint32_t)auxSignal))) |= muxes;
__edis();
}
//*****************************************************************************
//
//! Disables the CLB X-BAR mux values to be passed to an CLB module.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param muxes is a bit field of the muxes to be disabled.
//!
//! This function disables the mux values to be passed to the X-BAR auxSignal
//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is
//! the number of the signal on the CLB.
//!
//! The \e muxes parameter is a bit field of the muxes being disabled where bit
//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided
//! in the form of \b XBAR_MUXnn that can be logically OR'd together to
//! disable several muxes on an output at the same time.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_disableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes)
{
//
// Clear the enable bit.
//
__eallow();
(*((volatile uint32_t *)((0x00007A40U + 0x20U) + (uint32_t)auxSignal))) &= ~(muxes);
__edis();
}
//*****************************************************************************
//
//! Configures the polarity of an CLB X-BAR output.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param invert is a flag that determines whether the output is active-high
//! or active-low.
//!
//! This function inverts the CLB X-BAR auxSignal signal if the \e invert
//! parameter is \b true. If \e invert is \b false, the signal will be passed
//! as is. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is
//! the number of the signal on the CLB X-BAR that is being configured.
//!
//! \return None.
//
//*****************************************************************************
static inline void
XBAR_invertCLBSignal(XBAR_AuxSigNum auxSignal, _Bool invert)
{
//
// Set or clear the polarity setting bit based on the invert parameter.
//
__eallow();
if(invert)
{
(*((volatile uint16_t *)(0x00007A40U + 0x38U))) |=
0x1U << ((uint16_t)auxSignal / 2U);
}
else
{
(*((volatile uint16_t *)(0x00007A40U + 0x38U))) &=
~(0x1U << ((uint16_t)auxSignal / 2U));
}
__edis();
}
//*****************************************************************************
//
//! Configures the Output X-BAR mux that determines the signals passed to an
//! output.
//!
//! \param base specifies the X-BAR Config Register base address.
//! \param output is the X-BAR output being configured.
//! \param muxConfig is mux configuration that specifies the signal.
//!
//! This function configures an Output X-BAR mux. This determines which
//! signal(s) should be passed through the X-BAR to a GPIO. The \e output
//! parameter is a value \b XBAR_OUTPUTy where y is a the output number
//! between 1 and 8 inclusive.
//!
//! The \e base parameter can take base addresses
//! OUTPUTXBAR_BASE
//! or CLBOUTPUTXBAR_BASE.
//!
//! The \e muxConfig parameter for OUTPUT XBAR is the mux configuration
//! value that specifies which signal will be passed from the mux. The
//! values have the format of \b XBAR_OUT_MUXnn_xx where the 'xx' is
//! the signal and nn is the mux number.
//!
//! The \e muxConfig parameter for the CLB OUTPUT XBAR have the similar
//! format as \b XBAR_OUT_MUXnn_xx where the 'xx' is the signal and nn is
//! the mux number.
//!
//! This function may be called for each mux of an output and their values will
//! be logically OR'd before being passed to the output signal. This means that
//! this function may be called, for example, with the argument
//! \b XBAR_OUT_MUX00_ECAP1_OUT and then with the argument
//! \b XBAR_OUT_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01
//! being logically OR'd if both are enabled. Calling the function twice for
//! the same mux on the output will result in the configuration in the second
//! call overwriting the first.
//!
//! \return None.
//
//*****************************************************************************
extern void
XBAR_setOutputMuxConfig(uint32_t base, XBAR_OutputNum output,
XBAR_OutputMuxConfig muxConfig);
//*****************************************************************************
//
//! Configures the ePWM X-BAR mux that determines the signals passed to an
//! ePWM module.
//!
//! \param trip is the X-BAR output being configured.
//! \param muxConfig is mux configuration that specifies the signal.
//!
//! This function configures an ePWM X-BAR mux. This determines which signal(s)
//! should be passed through the X-BAR to an ePWM module. The \e trip
//! parameter is a value \b XBAR_TRIPy where y is a the number of the trip
//! signal on the ePWM.
//!
//! The \e muxConfig parameter is the mux configuration value that specifies
//! which signal will be passed from the mux. The values have the format of
//! \b XBAR_EPWM_MUXnn_xx where the 'xx' is the signal and nn is the mux
//! number (0 through 31). The possible values are found in xbar.h
//!
//! This function may be called for each mux of an output and their values will
//! be logically OR'd before being passed to the trip signal. This means that
//! this function may be called, for example, with the argument
//! \b XBAR_EPWM_MUX00_ECAP1_OUT and then with the argument
//! \b XBAR_EPWM_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01
//! being logically OR'd if both are enabled. Calling the function twice for
//! the same mux on the output will result in the configuration in the second
//! call overwriting the first.
//!
//! \return None.
//
//*****************************************************************************
extern void
XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig);
//*****************************************************************************
//
//! Returns the status of the input latch.
//!
//! \param inputFlag is the X-BAR input latch being checked. Values are in the
//! format of /b XBAR_INPUT_FLG_XXXX where "XXXX" is name of the signal.
//!
//! \return Returns \b true if the X-BAR input corresponding to the
//! \e inputFlag has been triggered. If not, it will return \b false.
//
//*****************************************************************************
extern _Bool
XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag);
//*****************************************************************************
//
//! Clears the input latch for the specified input latch.
//!
//! \param inputFlag is the X-BAR input latch being cleared.
//!
//! This function clears the Input X-BAR input latch. The input latch to be
//! cleared is specified by the \e inputFlag parameter.
//!
//! \return None.
//
//*****************************************************************************
extern void
XBAR_clearInputFlag(XBAR_InputFlag inputFlag);
//*****************************************************************************
//
//! Configures the CLB X-BAR mux that determines the signals passed to a
//! CLB module.
//!
//! \param auxSignal is the X-BAR output being configured.
//! \param muxConfig is mux configuration that specifies the signal.
//!
//! This function configures an CLB X-BAR mux. This determines which signal(s)
//! should be passed through the X-BAR to an CLB module. The \e auxSignal
//! parameter is a value \b XBAR_AUXSIGy where y is a the number of the
//! signal on the CLB.
//!
//! The \e muxConfig parameter is the mux configuration value that specifies
//! which signal will be passed from the mux. The values have the format of
//! \b XBAR_CLB_MUXnn_xx where the 'xx' is the signal and nn is the mux
//! number (0 through 31). The possible values are found in xbar.h
//!
//! This function may be called for each mux of an output and their values will
//! be logically OR'd before being passed to the signal. This means that
//! this function may be called, for example, with the argument
//! \b XBAR_CLB_MUX00_ECAP1_OUT and then with the argument
//! \b XBAR_CLB_MUX03_INPUTXBAR2, resulting in the values of MUX00 and MUX03
//! being logically OR'd if both are enabled. Calling the function twice for
//! the same mux on the output will result in the configuration in the second
//! call overwriting the first.
//!
//! \return None.
//
//*****************************************************************************
extern void XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal,
XBAR_CLBMuxConfig muxConfig);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//*****************************************************************************
//
// Useful defines used within the driver functions to access gpio registers.
// Not intended for use by application code.
//
// Divide by 2 is for C28x which has word access
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to GPIO_setPadConfig() as the pinType parameter
// and returned by GPIO_getPadConfig().
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to GPIO_setDirectionMode() as the \e pinIO
//! parameter and returned from GPIO_getDirectionMode().
//
//*****************************************************************************
typedef enum
{
GPIO_DIR_MODE_IN, //!< Pin is a GPIO input
GPIO_DIR_MODE_OUT //!< Pin is a GPIO output
} GPIO_Direction;
//*****************************************************************************
//
//! Values that can be passed to GPIO_setInterruptType() as the \e intType
//! parameter and returned from GPIO_getInterruptType().
//
//*****************************************************************************
typedef enum
{
GPIO_INT_TYPE_FALLING_EDGE = 0x00, //!< Interrupt on falling edge
GPIO_INT_TYPE_RISING_EDGE = 0x04, //!< Interrupt on rising edge
GPIO_INT_TYPE_BOTH_EDGES = 0x0C //!< Interrupt on both edges
} GPIO_IntType;
//*****************************************************************************
//
//! Values that can be passed to GPIO_setQualificationMode() as the
//! \e qualification parameter and returned by GPIO_getQualificationMode().
//
//*****************************************************************************
typedef enum
{
GPIO_QUAL_SYNC, //!< Synchronization to SYSCLK
GPIO_QUAL_3SAMPLE, //!< Qualified with 3 samples
GPIO_QUAL_6SAMPLE, //!< Qualified with 6 samples
GPIO_QUAL_ASYNC //!< No synchronization
} GPIO_QualificationMode;
//*****************************************************************************
//
//! Values that can be passed to GPIO_setAnalogMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
GPIO_ANALOG_DISABLED, //!< Pin is in digital mode
GPIO_ANALOG_ENABLED //!< Pin is in analog mode
} GPIO_AnalogMode;
//*****************************************************************************
//
//! Values that can be passed to GPIO_setControllerCore() as the \e core
//! parameter.
//
//*****************************************************************************
typedef enum
{
GPIO_CORE_CPU1, //!< CPU1 selected as controller core
GPIO_CORE_CPU1_CLA1 //!< CPU1's CLA1 selected as controller core
} GPIO_CoreSelect;
//*****************************************************************************
//
//! Values that can be passed to GPIO_readPortData(), GPIO_setPortPins(),
//! GPIO_clearPortPins(), and GPIO_togglePortPins() as the \e port parameter.
//
//*****************************************************************************
typedef enum
{
GPIO_PORT_A = 0, //!< GPIO port A
GPIO_PORT_B = 1, //!< GPIO port B
GPIO_PORT_H = 7 //!< GPIO port H
} GPIO_Port;
//*****************************************************************************
//
//! Values that can be passed to GPIO_setInterruptPin(),
//! GPIO_setInterruptType(), GPIO_getInterruptType(), GPIO_enableInterrupt(),
//! GPIO_disableInterrupt(), as the \e extIntNum parameter.
//
//*****************************************************************************
typedef enum
{
GPIO_INT_XINT1, //!< External Interrupt 1
GPIO_INT_XINT2, //!< External Interrupt 2
GPIO_INT_XINT3, //!< External Interrupt 3
GPIO_INT_XINT4, //!< External Interrupt 4
GPIO_INT_XINT5 //!< External Interrupt 5
} GPIO_ExternalIntNum;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks that a pin number is valid for a device.
//!
//! Note that this function reflects the highest possible GPIO number of a
//! device on its biggest package. Check the datasheet to see what the actual
//! range of valid pin numbers is for a specific package.
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the interrupt type for the specified pin.
//!
//! \param extIntNum specifies the external interrupt.
//! \param intType specifies the type of interrupt trigger mechanism.
//!
//! This function sets up the various interrupt trigger mechanisms for the
//! specified pin on the selected GPIO port.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! One of the following flags can be used to define the \e intType
//! parameter:
//!
//! - \b GPIO_INT_TYPE_FALLING_EDGE sets detection to edge and trigger to
//! falling
//! - \b GPIO_INT_TYPE_RISING_EDGE sets detection to edge and trigger to rising
//! - \b GPIO_INT_TYPE_BOTH_EDGES sets detection to both edges
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_setInterruptType(GPIO_ExternalIntNum extIntNum, GPIO_IntType intType)
{
//
// Write the selected polarity to the appropriate register.
//
(*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) =
((*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) & ~0xCU) |
(uint16_t)intType;
}
//*****************************************************************************
//
//! Gets the interrupt type for a pin.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! This function gets the interrupt type for a interrupt. The interrupt can be
//! configured as a falling-edge, rising-edge, or both-edges detected
//! interrupt.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! \return Returns one of the flags described for GPIO_setInterruptType().
//
//*****************************************************************************
static inline GPIO_IntType
GPIO_getInterruptType(GPIO_ExternalIntNum extIntNum)
{
//
// Read the selected polarity from the appropriate register.
//
return((GPIO_IntType)((uint16_t)((*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) &
0xCU)));
}
//*****************************************************************************
//
//! Enables the specified external interrupt.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! This function enables the indicated external interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_enableInterrupt(GPIO_ExternalIntNum extIntNum)
{
//
// Set the enable bit for the specified interrupt.
//
(*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) |= 0x1U;
}
//*****************************************************************************
//
//! Disables the specified external interrupt.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! This function disables the indicated external interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_disableInterrupt(GPIO_ExternalIntNum extIntNum)
{
//
// Clear the enable bit for the specified interrupt
//
(*((volatile uint16_t *)(0x00007070U + (uint16_t)extIntNum))) &= ~0x1U;
}
//*****************************************************************************
//
//! Gets the value of the external interrupt counter.
//!
//! \param extIntNum specifies the external interrupt.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//!
//! \b Note: The counter is clocked at the SYSCLKOUT rate.
//!
//! \return Returns external interrupt counter value.
//
//*****************************************************************************
static inline uint16_t
GPIO_getInterruptCounter(GPIO_ExternalIntNum extIntNum)
{
;
//
// Read the counter value from the appropriate register.
//
return(((*((volatile uint16_t *)(0x00007070U + 0x8U + (uint16_t)extIntNum)))));
}
//*****************************************************************************
//
//! Reads the value present on the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! The value at the specified pin are read, as specified by \e pin. The value
//! is returned for both input and output pins.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return Returns the value in the data register for the specified pin.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPin(uint32_t pin)
{
volatile uint32_t *gpioDataReg;
//
// Check the arguments.
//
;
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((pin / 32U) * ((0x8U - 0x0U) / 2U));
return((gpioDataReg[(0x0U / 2U)] >> (pin % 32U)) & (uint32_t)0x1U);
}
//*****************************************************************************
//
//! Reads the data register value for specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! The value available at the data register for the specified pin is read, as
//! specified by \e pin. The value is returned for both input and output pins.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \sa GPIO_readPin()
//!
//! \return Returns the value in the data register for the specified pin.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPinDataRegister(uint32_t pin)
{
volatile uint32_t *gpioDataReg;
//
// Check the arguments.
//
;
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F80U) +
((pin / 32U) * ((0x2U - 0x0U) / 2U));
return((gpioDataReg[(0x0U / 2U)] >> (pin % 32U)) & (uint32_t)0x1U);
}
//*****************************************************************************
//
//! Writes a value to the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param outVal is the value to write to the pin.
//!
//! Writes the corresponding bit values to the output pin specified by
//! \e pin. Writing to a pin configured as an input pin has no effect.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_writePin(uint32_t pin, uint32_t outVal)
{
volatile uint32_t *gpioDataReg;
uint32_t pinMask;
//
// Check the arguments.
//
;
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((pin / 32U) * ((0x8U - 0x0U) / 2U));
pinMask = (uint32_t)1U << (pin % 32U);
if(outVal == 0U)
{
gpioDataReg[(0x4U / 2U)] = pinMask;
}
else
{
gpioDataReg[(0x2U / 2U)] = pinMask;
}
}
//*****************************************************************************
//
//! Toggles the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! Writes the corresponding bit values to the output pin specified by
//! \e pin. Writing to a pin configured as an input pin has no effect.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_togglePin(uint32_t pin)
{
volatile uint32_t *gpioDataReg;
//
// Check the arguments.
//
;
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((pin / 32U) * ((0x8U - 0x0U) / 2U));
gpioDataReg[(0x6U / 2U)] = (uint32_t)1U << (pin % 32U);
}
//*****************************************************************************
//
//! Reads the data on the specified port.
//!
//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X
//! where X is the port letter.
//!
//! \return Returns the value available on pin for the specified port. Each
//! bit of the the return value represents a pin on the port, where bit 0
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPortData(GPIO_Port port)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and return DATA.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((uint32_t)port * ((0x8U - 0x0U) / 2U));
return(gpioDataReg[(0x0U / 2U)]);
}
//*****************************************************************************
//
//! Reads the data written in GPIO Data Register.
//!
//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X
//! where X is the port letter.
//!
//! Reads the data written in GPIO Data Register for the specified port. In
//! previous devices, read of GPIO data registers resulted in read of
//! corespoinding pins. The function \b GPIO_readPortData() returns the value
//! on pin.
//!
//! \sa GPIO_readPortData()
//!
//! \return Returns the value in the data register for the specified port. Each
//! bit of the the return value represents a pin on the port, where bit 0
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//
//*****************************************************************************
static inline uint32_t
GPIO_readPortDataRegister(GPIO_Port port)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and return DATA.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F80U) +
((uint32_t)port * ((0x2U - 0x0U) / 2U));
return(gpioDataReg[(0x0U / 2U)]);
}
//*****************************************************************************
//
//! Writes a value to the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param outVal is the value to write to the port.
//!
//! This function writes the value \e outVal to the port specified by the
//! \e port parameter which takes a value in the form of \b GPIO_PORT_X where X
//! is the port letter. For example, use \b GPIO_PORT_A to affect port A
//! (GPIOs 0-31).
//!
//! The \e outVal is a bit-packed value, where each bit represents a bit on a
//! GPIO port. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO port
//! pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_writePortData(GPIO_Port port, uint32_t outVal)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and write to DATA.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((uint32_t)port * ((0x8U - 0x0U) / 2U));
gpioDataReg[(0x0U / 2U)] = outVal;
}
//*****************************************************************************
//
//! Sets all of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function sets all of the pins specified by the \e pinMask parameter on
//! the port specified by the \e port parameter which takes a value in the
//! form of \b GPIO_PORT_X where X is the port letter. For example, use
//! \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be set. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO
//! port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_setPortPins(GPIO_Port port, uint32_t pinMask)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and write to SET.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((uint32_t)port * ((0x8U - 0x0U) / 2U));
gpioDataReg[(0x2U / 2U)] = pinMask;
}
//*****************************************************************************
//
//! Clears all of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function clears all of the pins specified by the \e pinMask parameter
//! on the port specified by the \e port parameter which takes a value in the
//! form of \b GPIO_PORT_X where X is the port letter. For example, use
//! \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is \b set
//! identifies the pin to be cleared. Bit 0 represents GPIO port pin 0, bit 1
//! represents GPIO port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_clearPortPins(GPIO_Port port, uint32_t pinMask)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and write to CLEAR.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((uint32_t)port * ((0x8U - 0x0U) / 2U));
gpioDataReg[(0x4U / 2U)] = pinMask;
}
//*****************************************************************************
//
//! Toggles all of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function toggles all of the pins specified by the \e pinMask parameter
//! on the port specified by the \e port parameter which takes a value in the
//! form of \b GPIO_PORT_X where X is the port letter. For example, use
//! \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be toggled. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_togglePortPins(GPIO_Port port, uint32_t pinMask)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and write to TOGGLE.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007F00U) +
((uint32_t)port * ((0x8U - 0x0U) / 2U));
gpioDataReg[(0x6U / 2U)] = pinMask;
}
//*****************************************************************************
//
//! Locks the configuration of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function locks the configuration registers of the pins specified by
//! the \e pinMask parameter on the port specified by the \e port parameter
//! which takes a value in the form of \b GPIO_PORT_X where X is the port
//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on.
//!
//! Note that this function is for locking the configuration of a pin such as
//! the pin muxing, direction, open drain mode, and other settings. It does not
//! affect the ability to change the value of the pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_lockPortConfig(GPIO_Port port, uint32_t pinMask)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and write to the lock.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007C00U) +
((uint32_t)port * ((0x40U - 0x0U) / 2U));
__eallow();
gpioDataReg[(0x3CU / 2U)] |= pinMask;
__edis();
}
//*****************************************************************************
//
//! Unlocks the configuration of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function unlocks the configuration registers of the pins specified by
//! the \e pinMask parameter on the port specified by the \e port parameter
//! which takes a value in the form of \b GPIO_PORT_X where X is the port
//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be unlocked. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_unlockPortConfig(GPIO_Port port, uint32_t pinMask)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and write to the lock.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007C00U) +
((uint32_t)port * ((0x40U - 0x0U) / 2U));
__eallow();
gpioDataReg[(0x3CU / 2U)] &= ~pinMask;
__edis();
}
//*****************************************************************************
//
//! Commits the lock configuration of the specified pins on the specified port.
//!
//! \param port is the GPIO port being accessed.
//! \param pinMask is a mask of which of the 32 pins on the port are affected.
//!
//! This function commits the lock configuration registers of the pins
//! specified by the \e pinMask parameter on the port specified by the \e port
//! parameter which takes a value in the form of \b GPIO_PORT_X where X is the
//! port letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31).
//!
//! The \e pinMask is a bit-packed value, where each bit that is set identifies
//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on.
//!
//! Note that once this function is called, GPIO_lockPortConfig() and
//! GPIO_unlockPortConfig() will no longer have any effect on the specified
//! pins.
//!
//! \return None.
//
//*****************************************************************************
static inline void
GPIO_commitPortConfig(GPIO_Port port, uint32_t pinMask)
{
volatile uint32_t *gpioDataReg;
//
// Get the starting address of the port's registers and write to the lock.
//
gpioDataReg = (uint32_t *)((uintptr_t)0x00007C00U) +
((uint32_t)port * ((0x40U - 0x0U) / 2U));
__eallow();
gpioDataReg[(0x3EU / 2U)] |= pinMask;
__edis();
}
//*****************************************************************************
//
//! Sets the direction and mode of the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param pinIO is the pin direction mode.
//!
//! This function configures the specified pin on the selected GPIO port as
//! either input or output.
//!
//! The parameter \e pinIO is an enumerated data type that can be one of the
//! following values:
//!
//! - \b GPIO_DIR_MODE_IN
//! - \b GPIO_DIR_MODE_OUT
//!
//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as an input
//! and \b GPIO_DIR_MODE_OUT specifies that the pin is programmed as an output.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO);
//*****************************************************************************
//
//! Gets the direction mode of a pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! This function gets the direction mode for a specified pin. The pin can be
//! configured as either an input or output The type of direction is returned
//! as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIO_setDirectionMode().
//
//*****************************************************************************
extern GPIO_Direction
GPIO_getDirectionMode(uint32_t pin);
//*****************************************************************************
//
//! Sets the pin for the specified external interrupt.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param extIntNum specifies the external interrupt.
//!
//! This function sets which pin triggers the selected external interrupt.
//!
//! The following defines can be used to specify the external interrupt for the
//! \e extIntNum parameter:
//!
//! - \b GPIO_INT_XINT1
//! - \b GPIO_INT_XINT2
//! - \b GPIO_INT_XINT3
//! - \b GPIO_INT_XINT4
//! - \b GPIO_INT_XINT5
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \sa XBAR_setInputPin()
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum);
//*****************************************************************************
//
//! Sets the pad configuration for the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param pinType specifies the pin type.
//!
//! This function sets the pin type for the specified pin. The parameter
//! \e pinType can be the following values:
//!
//! - \b GPIO_PIN_TYPE_STD specifies a push-pull output or a floating input
//! - \b GPIO_PIN_TYPE_PULLUP specifies the pull-up is enabled for an input
//! - \b GPIO_PIN_TYPE_OD specifies an open-drain output pin
//! - \b GPIO_PIN_TYPE_INVERT specifies inverted polarity on an input
//!
//! \b GPIO_PIN_TYPE_INVERT may be OR-ed with \b GPIO_PIN_TYPE_STD or
//! \b GPIO_PIN_TYPE_PULLUP.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setPadConfig(uint32_t pin, uint32_t pinType);
//*****************************************************************************
//
//! Gets the pad configuration for a pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! This function returns the pin type for the specified pin. The value
//! returned corresponds to the values used in GPIO_setPadConfig().
//!
//! \return Returns a bit field of the values \b GPIO_PIN_TYPE_STD,
//! \b GPIO_PIN_TYPE_PULLUP, \b GPIO_PIN_TYPE_OD, and \b GPIO_PIN_TYPE_INVERT.
//
//*****************************************************************************
extern uint32_t
GPIO_getPadConfig(uint32_t pin);
//*****************************************************************************
//
//! Sets the qualification mode for the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param qualification specifies the qualification mode of the pin.
//!
//! This function sets the qualification mode for the specified pin. The
//! parameter \e qualification can be one of the following values:
//! - \b GPIO_QUAL_SYNC
//! - \b GPIO_QUAL_3SAMPLE
//! - \b GPIO_QUAL_6SAMPLE
//! - \b GPIO_QUAL_ASYNC
//!
//! To set the qualification sampling period, use
//! GPIO_setQualificationPeriod().
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification);
//*****************************************************************************
//
//! Gets the qualification type for the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//!
//! \return Returns the qualification mode in the form of one of the values
//! \b GPIO_QUAL_SYNC, \b GPIO_QUAL_3SAMPLE, \b GPIO_QUAL_6SAMPLE, or
//! \b GPIO_QUAL_ASYNC.
//
//*****************************************************************************
extern GPIO_QualificationMode
GPIO_getQualificationMode(uint32_t pin);
//*****************************************************************************
//
//! Sets the qualification period for a set of pins
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param divider specifies the output drive strength.
//!
//! This function sets the qualification period for a set of \b 8 \b pins,
//! specified by the \e pin parameter. For instance, passing in 3 as the value
//! of \e pin will set the qualification period for GPIO0 through GPIO7, and a
//! value of 98 will set the qualification period for GPIO96 through GPIO103.
//! This is because the register field that configures the divider is shared.
//!
//! To think of this in terms of an equation, configuring \e pin as \b n will
//! configure GPIO (n & ~(7)) through GPIO ((n & ~(7)) + 7).
//!
//! \e divider is the value by which the frequency of SYSCLKOUT is divided. It
//! can be 1 or an even value between 2 and 510 inclusive.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider);
//*****************************************************************************
//
//! Selects the controller core of a specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param core is the core that is controller of the specified pin.
//!
//! This function configures which core owns the specified pin's data registers
//! (DATA, SET, CLEAR, and TOGGLE). The \e core parameter is an enumerated data
//! type that specifies the core, such as \b GPIO_CORE_CPU1_CLA1 to make CPU1's
//! CLA1 controller of the pin.
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core);
//*****************************************************************************
//
//! Sets the analog mode of the specified pin.
//!
//! \param pin is the identifying GPIO number of the pin.
//! \param mode is the selected analog mode.
//!
//! This function configures the specified pin for either analog or digital
//! mode. Not all GPIO pins have the ability to be switched to analog mode,
//! so refer to the technical reference manual for details. This setting should
//! be thought of as another level of muxing.
//!
//! The parameter \e mode is an enumerated data type that can be one of the
//! following values:
//!
//! - \b GPIO_ANALOG_DISABLED - Pin is in digital mode
//! - \b GPIO_ANALOG_ENABLED - Pin is in analog mode
//!
//! The pin is specified by its numerical value. For example, GPIO34 is
//! specified by passing 34 as \e pin.
//!
//! \b Note: The pin parameter is applicable for both AIO and GPIO because
//! the GPAxMSEL.GPIOy register configures for both
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode);
//*****************************************************************************
//
//! Configures the alternate function of a GPIO pin.
//!
//! \param pinConfig is the pin configuration value, specified as only one
//! of the \b GPIO_#_???? values.
//!
//! This function configures the pin mux that selects the peripheral function
//! associated with a particular GPIO pin. Only one peripheral function at a
//! time can be associated with a GPIO pin, and each peripheral function should
//! only be associated with a single GPIO pin at a time (despite the fact that
//! many of them can be associated with more than one GPIO pin).
//!
//! The available mappings are supplied in pin_map.h.
//!
//! \return None.
//
//*****************************************************************************
extern void
GPIO_setPinConfig(uint32_t pinConfig);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: hic.h
//
// TITLE: C28x Host Interface Controller (HIC) driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup hic_api HIC
//! \brief This module is used for Host Interface Controller(HIC) configuration
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_hic.h
//
// TITLE: Definitions for the HIC registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the HIC register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICREV register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICGCR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICMODECR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICPINPOLCR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICBASESEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICHOSTCR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICERRADDR register
//
//*************************************************************************************************
// error for Device
// error for Host
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR5 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR6 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR7 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICCOMMIT register
//
//*************************************************************************************************
//
//Generic defines
//
//
//Number of Regions of Base addresses supported in HIC module
//
//
//Number of Device to Host and Host to Device Buffer Registers of the module
//
//
//Used in HIC_enableHostInterface() API
//
//
//Used in HIC_enableLock() and HIC_disableLock() APIs
//
//
//Flag for Unlocking in LOCK register
//
//*****************************************************************************
//
//! Values that can be passed to HIC_setConfig() as \e flags or
//! used with HIC_getConfig() API return value parsing
//
//*****************************************************************************
//
//Enumerations for HICMODECR Register
//
//
//For Read/Write Pin
//
//
//For Byte Enable BEn Pins
//
//
//For Ready nRDY Pin
//
//
//For Host to Device Buffer Device Write Enable
//
//
//For Device to Host Buffer Host Write Enable
//
//
//For Enabling Host Access to Device Region
//
//
//For Enabling Host Write to EALLOWCTL Register
//
//*****************************************************************************
//
//! Values that can be passed to HIC_setPinPolarity() API as \e flags or
//! used with HIC_getPinPolarity() API return value parsing
//
//*****************************************************************************
//
//For Pin Polarity Configuration
//Chip Select Pin (CS)
//
//
// Byte Enable Pin
//
//
// Output Enable OE Pin
//
//
// Write Enable (WE) Pin Polarity
//
//
// Ready Pin( RDY) Polarity
//
//*****************************************************************************
//
//! Values that can be passed to HIC_configureHostAccessMode() API as \e config
//! or used with HIC_getHostAccessMode() API return value parsing
//
//*****************************************************************************
//
//Host Control Register
//
//
//Access size of MMR registers
//
//
//Page selection via Pin/BASESEL Register
//
//*****************************************************************************
//
//! Values that can be passed to HIC_enableD2HInterrupt() API or
//! or used with HIC_disableD2HInterrupt() API to enable/disable interrupt
//! or with HIC_clearD2HInterrupt() API to clear interrupt
//
//*****************************************************************************
//
//SOC Internal Event Trigger (EVTTRIG)
//Refer Device TRM for details of the event(s)
//
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Returns the Revision of HIC Controller interface.
//!
//! This function returns the hardware revision of the Host Interface
//! controller module
//!
//! \return The Hardware Version number
//! returns the content of HICREV register. Please refer to device TRM
//! for field wise details.
//
//*****************************************************************************
static inline uint32_t
HIC_getRevision(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x0U))));
}
//*****************************************************************************
//
//! Enables the Host Access to the Device region and to the Mailbox
//!
//! \return none
//!
//! \n The Host interface Controller module provides two mechanisms of access
//! 1. Using Device Memory access, the host can access the memory directly
//! read/write/poll for registers
//! 2. Using the Mailbox mechanism which can be used when the Host can write
//! the parameters to the mailbox Host-to-Device buffer region and then
//! trigger an interrupt to the Device. The HIC module with the
//! other application running on device side can then be used
//! to signal to the host, using the Device-to-Host buffer region
//! in response.
//! This API enables the access to the Device region and Mailbox.
//! This should be used as the first API in sequence of configuring
//! the HIC module.
//
//*****************************************************************************
static inline void
HIC_enableHostInterface(void)
{
__eallow();
(*((volatile uint32_t *)(0x00006500U + 0x2U))) = 0x0AU;
__edis();
}
//*****************************************************************************
//
//! Enables the Lock for the HIC module registers protected by Writes
//!
//! \n This API enables the lock, which protects the writes to registers
//! protected by Lock. Calling this API prevents writes to the write protected
//! registers.
//!
//! \return none
//
//*****************************************************************************
static inline void
HIC_enableLock(void)
{
__eallow();
(*((volatile uint32_t *)(0x00006500U + 0x4U))) = (0x1U |
((uint32_t)0x5A5AU <<
16U));
__edis();
}
//*****************************************************************************
//
//! Disables the Lock for the HIC module registers protected by Writes
//!
//! \n This API disables the lock(unlocks), which enables the writes
//! to registers protected by Lock.
//! Calling this API enables writes to the write protected
//! registers.
//! This API must be called one time before calling any of these APIs
//! - HIC_setConfig()
//! - HIC_setPinPolarity()
//! - HIC_selectBaseAddress()
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_disableLock(void)
{
__eallow();
(*((volatile uint32_t *)(0x00006500U + 0x4U))) = (0x0U |
((uint32_t)0x5A5AU <<
16U));
__edis();
}
//*****************************************************************************
//
//! Sets the Host Interface Controller Configurations
//! \n This API configures the HICMODECR register for the selected configuration
//! HIC_disableLock() API should have been called prior to this API.
//!
//! \param flags specifies the ORed values of any of following flags.
//!
//! Any one of following values for Data Width
//! - \b HIC_MODE_DW_8BIT -for 8bit Data
//! - \b HIC_MODE_DW_16BIT -for 16bit Data
//! - \b HIC_MODE_DW_32BIT -for 32bit Data
//!
//! Any one of following values for Read Write Pin
//! - \b HIC_MODE_RW_PIN_SEPARATE - for Separate Read and Write Pin
//! - \b HIC_MODE_RW_PIN_SINGLE - for Same Read and Write Pin
//!
//! Any one of following values for Byte Enable Pin configuration
//! - \b HIC_MODE_BEN_PRESENT - for using Byte Enable Pin
//! - \b HIC_MODE_BEN_ABSENT - for not using Byte Enable Pin
//!
//! Any one of following values for Ready Pin
//! - \b HIC_MODE_RDY_PRESENT - for using Ready Pin for extended wait
//! - \b HIC_MODE_RDY_ABSENT - for not using Extended Wait pin
//!
//! Other configurations:
//! - \b HIC_MODE_H2DBUF_DEVWREN - for enabling Device access to
//! host to Device Buffers. If this is not enabled the device cannot write to
//! Host to Device buffers
//! - \b HIC_MODE_D2HBUF_HOST_WR_ENABLE - for enabling host access to
//! device to host buffers. If this is not enabled the host cannot write to
//! device to host buffers.
//! - \b HIC_MODE_DEVICE_HOST_ACCESS_ENABLE - for enabling access to the device
//! region. Only if this is enabled the regions selected by
//! Base select registers using the HIC_selectBaseAddress() API
//! shall be accessible.
//! Without this only the HIC registers and Mailbox registers will be
//! accessible for the host.
//! - \b HIC_MODE_HOST_WREALLOW_ENABLE - for enabling host access to write to
//! EALLOW bitfield using HIC_configureHostAccessMode() API. Without enabling
//! this HIC_configureHostAccessMode(HIC_HOSTCR_EALLOW_EN)
//! will not work.
//
//! \return None
//
//*****************************************************************************
static inline void
HIC_setConfig(uint32_t flags)
{
__eallow();
(*((volatile uint32_t *)(0x00006500U + 0x6U))) = flags;
__edis();
}
//*****************************************************************************
//
//! Returns the Host Interface Controller Configurations
//!
//! \return
//! 32-bit integer specifies the ORed values of following flags
//! Any one of following values for Data Width
//! - \b HIC_MODE_DW_8BIT -for 8bit Data
//! - \b HIC_MODE_DW_16BIT -for 16bit Data
//! - \b HIC_MODE_DW_32BIT -for 32bit Data
//!
//! Following values for Other Configurations
//! - \b HIC_MODE_RW_PIN_SEPARATE/ HIC_MODE_RW_PIN_SINGLE - for Read/Write Pin
//! - \b HIC_MODE_BEN_PRESENT/HIC_MODE_BEN_ABSENT - for Byte Enable Pin Usage
//! - \b HIC_MODE_RDY_PRESENT/HIC_MODE_RDY_ABSENT - for using Ready Pin for
//! extended wait
//! - \b HIC_MODE_H2DBUF_DEVWREN- Device access to Host to Device Buffer Enabled
//! - \b HIC_MODE_D2HBUF_HOST_WR_ENABLE - Host access to Device to Host Buffer
//! enabled
//! - \b HIC_MODE_DEVICE_HOST_ACCESS_ENABLE - for enabling access to the device
//! - \b HIC_MODE_HOST_WREALLOW_ENABLE - for host access to write to EALLOW
//!
//! This API returns the current configuration of HIC module.
//! It can be used along with macros defined in hw_hic.h as below.
//! For querying the Data width use like in below examples
//! \n HIC_getConfig() & HIC_MODECR_DW_MODE_M == HIC_MODE_DW_8BIT for Data width
//! \n HIC_getConfig() & HIC_MODECR_RW_MODE == HIC_MODE_RW_PIN_SINGLE for RW Pin
//! \n HIC_getConfig() & HIC_MODECR_BEN_PRESENT == HIC_MODE_BEN_PRESENT
//! for BE Pin
//
//*****************************************************************************
static inline uint32_t
HIC_getConfig(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x6U))));
}
//*****************************************************************************
//
//! Sets the Host Interface Controller Pin Polarity.
//! This API configures the HICPINPOLCR register for the selected configuration.
//! HIC_disableLock() API should have been called prior to this API.
//!
//! \param flags specifies the ORed values of any of following flags
//!
//! Any one of following values for Chip Select Pin
//! - \b HIC_PIN_POLARITY_CS_HIGH - for Active High Chip Select Pin
//! - \b HIC_PIN_POLARITY_CS_LOW - for Active Low Chip Select Pin
//!
//! Any one of following values for Byte Enable Pin configuration
//! - \b HIC_PIN_POLARITY_BEN_HIGH - for Active High Byte Enable
//! - \b HIC_PIN_POLARITY_BEN_LOW - for Active Low Byte Enable
//!
//! Any one of following values for Output Enable Pin
//! - \b HIC_PIN_POLARITY_OE_HIGH - for Active High Output Enable
//! - \b HIC_PIN_POLARITY_OE_LOW - for Active Low Output Enable
//!
//! Any one of following values for Write Enable Pin
//! - \b HIC_PIN_POLARITY_WE_HIGH - for Active High Write Enable
//! - \b HIC_PIN_POLARITY_WE_LOW - for Active Low Write Enable
//!
//! Any one of following values for Ready Pin
//! - \b HIC_PIN_POLARITY_RDY_HIGH - for Active High Write Enable
//! - \b HIC_PIN_POLARITY_RDY_LOW - for Active Low Write Enable
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_setPinPolarity(uint16_t flags)
{
__eallow();
(*((volatile uint32_t *)(0x00006500U + 0x8U))) = flags;
__edis();
}
//*****************************************************************************
//
//! Returns the Host Interface Controller Pin Polarity Configurations
//!
//! This API returns the HICPINPOLCR register for the selected configuration
//!
//! \return
//! 32-bit integer specifies the ORed values of any of following flags
//! Following values for corresponding Pin Configuration
//! - \b HIC_PIN_POLARITY_CS_HIGH/ HIC_PIN_POLARITY_CS_HIGH - for CS Pin
//! - \b HIC_PIN_POLARITY_BEN_HIGH/HIC_PIN_POLARITY_BEN_HIGH- for
//! Byte Enable pin
//! - \b HIC_PIN_POLARITY_OE_HIGH/HIC_PIN_POLARITY_OE_LOW - for OE Pin
//! - \b HIC_PIN_POLARITY_WE_HIGH/HIC_PIN_POLARITY_WE_LOW- for WE Pin
//! - \b HIC_PIN_POLARITY_RDY_HIGH/HIC_PIN_POLARITY_RDY_LOW - for RDY Pin
//!
//! This API returns the Pin Polarity.This can be used with the macros defined
//! in hw_hic.h as shown below
//! HIC_getPinPolarity & HIC_PINPOLCR_BEN_POL == HIC_PIN_POLARITY_BEN_HIGH for
//! checking the status of Byte Enable Pin Polarity
//
//*****************************************************************************
static inline uint32_t
HIC_getPinPolarity(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x8U))));
}
//*****************************************************************************
//
//! Selects the Base Address for the device memory access
//!
//! \param selectIndex specifies the index of Base address in the Base Address
//! regions can vary from 0 to HIC_NUM_BASE_ADDRESS-1
//!
//! The Device memory region will be accessible by the region selected in this
//! API. Also look at HIC_configureHostAccessMode(HIC_HOSTCR_PAGESEL)
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_selectBaseAddress(uint16_t selectIndex)
{
//
//Check the arguments.
//
;
(*((volatile uint32_t *)(0x00006500U + 0xAU))) = selectIndex;
}
//*****************************************************************************
//
//! Returns the Selected Base address index for the device memory access
//!
//! The Device memory region will be accessible by the region selected in this
//! API. Also look at HIC_configureHostAccessMode(HIC_HOSTCR_PAGESEL)
//!
//! \return selected index of Base address in the Base Address
//! regions. can vary from 0 to HIC_NUM_BASE_ADDRESS-1
//
//*****************************************************************************
static inline uint16_t
HIC_getSelectedBaseAddressIndex(void)
{
return((*((volatile uint16_t *)(0x00006500U + 0xAU))));
}
//*****************************************************************************
//
//! Configures the Host Access modes to the device region
//!
//! \param config logical OR of the following values
//! - \b HIC_HOSTCR_EALLOW_EN for enabling module writes to EALLOW Protected
//! registers
//! - either of
//! HIC_HOST_CONTROL_ACCSIZE_16BIT/HIC_HOST_CONTROL_ACCSIZE_32BIT
//! to select 16 bit or 32 bit device side master port accesses
//! - either of
//! HIC_HOST_CONTROL_PAGESEL_REG/HIC_HOST_CONTROL_PAGESEL_PIN
//! to select Page/Region selection based on PAGESEL register
//! programmed using HIC_selectBaseAddress()API or the PAGESEL Pin
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_configureHostAccessMode(uint16_t config)
{
//
//Needs a key to be written for the write to go through
//
(*((volatile uint32_t *)(0x00006500U + 0xCU))) = (config |
0xA5U <<
8U);
}
//*****************************************************************************
//
//! Provides the Host Access modes configured currently
//!
//! \return Host Access mode value as configured
//! HIC_configureHostAccessMode()
//! API which is a logical OR of
//! - \b HIC_HOSTCR_EALLOW_EN for enabling module writes to EALLOW Protected
//! registers
//! - either of
//! HIC_HOST_CONTROL_ACCSIZE_16BIT/HIC_HOST_CONTROL_ACCSIZE_32BIT
//! for selected 16 bit or 32 bit device side master port accesses
//! - either of
//! HIC_HOST_CONTROL_PAGESEL_REG/HIC_HOST_CONTROL_PAGESEL_PIN
//! for selected Page/Region selection based on PAGESEL register
//! programmed using HIC_selectBaseAddress()API or the PAGESEL Pin
//!
//! This API can be used with few Macros defined in hw_hic.h as below
//! (HIC_getAccessMode() & HIC_HOSTCR_ACCSIZE) == HIC_HOST_CONTROL_ACCSIZE_32BIT
//! for Access size checking. Similarly it can be used for other bit fields.
//
//*****************************************************************************
static inline uint32_t
HIC_getHostAccessMode(void)
{
//
//Returns the lower 16 bits that contains the configuration
//
return((*((volatile uint16_t *)(0x00006500U + 0xCU))));
}
//*****************************************************************************
//
//! Returns the Host and Device side Status when an Error happened on interface
//!
//! \return returns the logical OR of the following
//! - 8 bit Host to Device Error Address when Host to Device Error happens
//! - 3 bit Base select value when Host to Device Error happens
//! - 8 bit Device to Host Error Address when Device to Host Error happens
//! - 3 bit Base select value when Device to Host Error Happens.
//! \n Please refer to TRM HICERRADDR register for more details on this.
//
//*****************************************************************************
static inline uint32_t
HIC_getErrorAddress(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0xEU))));
}
//*****************************************************************************
//
//! Returns the token written by the token written onto the Host to Device Token
//!
//! \return the 32 bit Token value written into the register
//!
//! This API can be used while using the Mailbox mechanism.
//
//*****************************************************************************
static inline uint32_t
HIC_getH2DToken(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x10U))));
}
//*****************************************************************************
//
//! Writes the Token to the Host from Device
//!
//! \param token is the 32 bit token value to be written. It could be used
//! to denote the number of bytes written on to the Device-to-Host buffer
//!
//! \return None
//!
//! This API can be used while using the Mailbox mechanism.
//! Writing to this register could be used to trigger an interrupt
//! to the Host using the Device to Host
//! interrupt line(D2HINT) of the module.
//! It can be used to interrupt the external host.
//
//*****************************************************************************
static inline void
HIC_setD2HToken(uint32_t token)
{
(*((volatile uint32_t *)(0x00006500U + 0x12U))) = token;
}
//*****************************************************************************
//
//! Returns the token written by the token written onto the Device to Host Token
//!
//! \return the 32 bit Token value written into the register
//!
//! This API can be used while using the Mailbox mechanism.
//
//*****************************************************************************
static inline uint32_t
HIC_getD2HToken(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x12U))));
}
//*****************************************************************************
//
//! Configures the Base Address of the region
//!
//! \param index specifies the index of the Device Region to be configured
//! can be from 0 to HIC_NUM_BASE_ADDRESS-1
//!
//! \param baseAddress the 32 bit base address of the device region
//! being configured
//!
//! The device memory which HIC module can access can be divided into multiple
//! 256 byte regions.
//! For Example: GSRAM in Region 0,
//! ADC registers in Region 1
//! FSI registers in Region 2,etc
//! This API helps to configure the base address for each region
//! The HIC address Pin can then be used to offset into the specific region
//! by the host
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_setBaseAddress(uint16_t index,
uint32_t baseAddress)
{
//
//Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(0x00006500U + 0x14U + (index * 2)))) = baseAddress;
__edis();
}
//*****************************************************************************
//
//! Returns the Base Address configured for the region
//!
//! \param index specifies the index of the Device Region to be configured
//! can be from 0 to HIC_NUM_BASE_ADDRESS-1
//!
//! Returns the configured base address for the Region index provided
//!
//! \return 32 bit base address configured for the region
//
//*****************************************************************************
static inline uint32_t
HIC_getBaseAddress(uint16_t index)
{
//
//Check the arguments.
//
;
return(0x00006500U + 0x14U + (index * 2));
}
//*****************************************************************************
//
//! Enables the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_H2DINTEN_H2D_INTEN - Data Ready interrupt Enable
//! - \b HIC_H2DINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_H2DINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_H2DINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//!
//! Enables the specified interrupts. This will result in a HIC interrupt
//! generated to the C28x core.
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_enableH2DInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x28U))) |= flags;
}
//*****************************************************************************
//
//! Disables the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_H2DINTEN_H2D_INTEN - Data Ready interrupt Enable
//! - \b HIC_H2DINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_H2DINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_H2DINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//!
//! Disables the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_disableH2DInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x28U))) &= ~flags;
}
//*****************************************************************************
//
//! Gives the status of Host to Device interrupts
//!
//! \return 32bit flag with the logical ORed values below
//! - \b HIC_H2DINTFLG_H2D_FLG - Data Ready interrupt Status
//! - \b HIC_H2DINTFLG_BUSERR_FLG - Bus error Interrupt Status
//! - \b HIC_H2DINTFLG_ILLWR_FLG - Illegal Write Interrupt Status
//! - \b HIC_H2DINTFLG_ILLRD_FLG - Illegal Read Interrupt Status.
//!
//! \n The Flag if Set indicates that the corresponding Interrupt is active
//! (has occured)
//
//*****************************************************************************
static inline uint32_t
HIC_getH2DInterruptStatus(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x2AU))));
}
//*****************************************************************************
//
//! Clears the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be cleared
//! - \b HIC_H2DINTCLR_H2D_CLR - Data Ready interrupt Clear
//! - \b HIC_H2DINTCLR_BUSERR_CLR - Bus error Interrupt Clear
//! - \b HIC_H2DINTCLR_ILLWR_CLR - Illegal Write Interrupt Clear
//! - \b HIC_H2DINTCLR_ILLRD_CLR - Illegal Read Interrupt Clear
//!
//! Clears the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_clearH2DInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x2CU))) = flags;
}
//*****************************************************************************
//
//! Forces the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be Forced
//! - \b HIC_H2DINTFRC_H2D_INTFRC - Data Ready interrupt Force
//! - \b HIC_H2DINTFRC_BUSERR_INTFRC - Bus error Interrupt Force
//! - \b HIC_H2DINTFRC_ILLWR_INTFRC - Illegal Write Interrupt Force
//! - \b HIC_H2DINTFRC_ILLRD_INTFRC - Illegal Read Interrupt Force
//!
//! Forces the interrupt flags specified. Can be used for Debug purpose.
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_forceH2DInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x2EU))) = flags;
}
//*****************************************************************************
//
//! Enables the Interrupts from Device to Host
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_D2HINTEN_D2H_INTEN - Data Ready interrupt Enable
//! - \b HIC_D2HINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_D2HINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_D2HINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//! - \b HIC_D2HINTEN_ACCVIO_INTEN - Access Violation Interrupt Enable
//! - \b Event Trigger interrupt flags - The higher 16 bits when Set will enable
//! corresponding D2H interrupts. Refer TRM for details.
//!
//! Enables the specified interrupts. This will result in a HIC interrupt
//! generated to the Host(D2HINT).
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_enableD2HInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x30U))) |= flags;
}
//*****************************************************************************
//
//! Disables the Interrupts from Device to Host
//!
//! \param flags specifies the logical ORed values below
//! - \b HIC_D2HINTEN_D2H_INTEN - Data Ready interrupt Enable
//! - \b HIC_D2HINTEN_BUSERR_INTEN - Bus error Interrupt Enable
//! - \b HIC_D2HINTEN_ILLWR_INTEN - Illegal Write Interrupt Enable
//! - \b HIC_D2HINTEN_ILLRD_INTEN - Illegal Read Interrupt Enable
//! - \b HIC_D2HINTEN_ACCVIO_INTEN - Access Violation Interrupt Enable
//! - Event Trigger interrupt flags - The higher 16 bits when set will
//! disable corresponding D2H interrupts. Refer TRM for details.
//!
//! Disables the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_disableD2HInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x30U))) &= ~flags;
}
//*****************************************************************************
//
//! Gives the status of Device to Host interrupts
//!
//! \return 32bit flag with the logical ORed values below
//! - \b HIC_D2HINTFLG_D2H_FLG - Data Ready interrupt Status
//! - \b HIC_D2HINTFLG_BUSERR_FLG - Bus error Interrupt Status
//! - \b HIC_D2HINTFLG_ILLWR_FLG - Illegal Write Interrupt Status
//! - \b HIC_D2HINTFLG_ILLRD_FLG - Illegal Read Interrupt Status
//! - \b HIC_D2HINTFLG_ACCVIO_FLG - Access Violation Interrupt Status
//! - Event Trigger Interrupt Flags - The higher 16 bits give
//! the status of event Trigger Interrupt flags.
//! Refer TRM for the sources of these interrupts.
//!
//! The Flag if Set indicates that the corresponding Interrupt is active
//! (has occurred)
//
//*****************************************************************************
static inline uint32_t
HIC_getD2HInterruptStatus(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x32U))));
}
//*****************************************************************************
//
//! Clears the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be cleared
//! - \b HIC_D2HINTCLR_D2H_CLR - Data Ready interrupt Clear
//! - \b HIC_D2HINTCLR_BUSERR_CLR - Bus error Interrupt Clear
//! - \b HIC_D2HINTCLR_ILLWR_CLR - Illegal Write Interrupt Clear
//! - \b HIC_D2HINTCLR_ILLRD_CLR - Illegal Read Interrupt Clear
//! - \b HIC_D2HINTCLR_ACCVIO_CLR - Access Violation Interrupt Clear
//! - Event Trigger Interrupt Clear Flags - The higher 16 bits
//! indicates event trigger flags to be cleared.
//! Refer TRM for the sources of these interrupts.
//!
//! Clears the interrupt flags specified
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_clearD2HInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x34U))) = flags;
}
//*****************************************************************************
//
//! Forces the Interrupts from Host to Device
//!
//! \param flags specifies the logical ORed values below to be Forced
//! - \b HIC_D2HINTFRC_D2H_INTFRC - Data Ready interrupt Force
//! - \b HIC_D2HINTFRC_BUSERR_INTFRC - Bus error Interrupt Force
//! - \b HIC_D2HINTFRC_ILLWR_INTFRC - Illegal Write Interrupt Force
//! - \b HIC_D2HINTFRC_ILLRD_INTFRC - Illegal Read Interrupt Force
//! - \b HIC_D2HINTFRC_ACCVIO_INTFRC - Access violation Interrupt Force
//! - Event Trigger Interrupt Force Flags - The higher 16 bits
//! indicates event trigger flags to be cleared.
//! Refer TRM for the sources of these interrupts.
//!
//! Forces the interrupt flags specified. Can be used for Debug purposes.
//!
//! \return None
//
//*****************************************************************************
static inline void
HIC_forceD2HInterrupt(uint32_t flags)
{
(*((volatile uint32_t *)(0x00006500U + 0x36U))) = flags;
}
//*****************************************************************************
//
//! Returns the Address when Access violation happened
//!
//! \return returns the 32 bit address when the Access violation happened
//!
//! While the HIC module internal access port accesses a memory, if there is
//! an access violation, the module updates the address in this register.
//
//*****************************************************************************
static inline uint32_t
HIC_getAccessViolationAddress(void)
{
return((*((volatile uint32_t *)(0x00006500U + 0x38U))));
}
//*****************************************************************************
//
//! Returns the Host to Device Buffer for the offset specified
//!
//! \param offset specifies the offset of the H2D buffer
//! can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return returns the 32 bit content of the Host to Device buffer.
//!
//! The Host to Device buffer can be used to implement a communication
//! scheme on which the Host writes the data to sent to the Control peripherals.
//! The MCU can pick it up and stream it over control peripherals.
//! The Device to Host Buffer can be used to write the response back.
//! The External host need not continuously wait for the data/response.
//
//*****************************************************************************
static inline uint32_t
HIC_readH2DBuffer(uint16_t offset)
{
//
//Check the arguments.
//
;
return((*((volatile uint32_t *)(0x00006500U + 0x40U + (offset * 2)))));
}
//*****************************************************************************
//
//! Writes to the Host to Device buffer
//!
//! \param offset specifies the offset of the H2D buffer
//! can vary from 0 to HIC_NUM_BUFFER_REGS-1
//! \param data the 32bit data to be written onto the buffer
//!
//! \return none
//!
//! This API should be used only when the Device write to Host buffer
//! is enabled, using HIC_setConfig(HIC_MODECR_H2DBUF_DEVWREN) API.
//
//*****************************************************************************
static inline void
HIC_writeH2DBuffer(uint16_t offset, uint32_t data)
{
//
//Check the arguments.
//
;
(*((volatile uint32_t *)(0x00006500U + 0x40U + (offset * 2)))) = data;
}
//*****************************************************************************
//
//! Clears the Host to Device buffer (by making it Zero)
//!
//! \param offset specifies the offset of the H2D buffer
//! can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return none
//!
//! This API should be used only when the Device write to Host buffer
//! is enabled, using HIC_setConfig(HIC_MODECR_H2DBUF_DEVWREN) API.
//! This API can be used to clear the content of H2D Buffer
//
//*****************************************************************************
static inline void
HIC_clearH2DBuffer(uint16_t offset)
{
//
//Check the arguments.
//
;
(*((volatile uint32_t *)(0x00006500U + 0x40U + (offset * 2)))) = 0;
}
//*****************************************************************************
//
//! Returns the Device to Host Buffer for the offset specified
//!
//! \param offset specifies the offset of the D2H buffer
//! can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return returns the 32 bit content of the Device to Host buffer
//!
//! The Device to Host Buffer can be used to write the response back to host
//! The External host need not continuously wait for the data/response.
//
//*****************************************************************************
static inline uint32_t
HIC_readD2HBuffer(uint16_t offset)
{
//
//Check the arguments.
//
;
return((*((volatile uint32_t *)(0x00006500U + 0x60U + (offset * 2)))));
}
//*****************************************************************************
//
//! Writes to the Device to Host buffer
//!
//! \param offset specifies the offset of the D2H buffer
//! can vary from 0 to HIC_NUM_BUFFER_REGS-1
//! \param data the 32bit data to be written onto the buffer
//!
//! \return none
//
//*****************************************************************************
static inline void
HIC_writeD2HBuffer(uint16_t offset, uint32_t data)
{
//
//Check the arguments.
//
;
(*((volatile uint32_t *)(0x00006500U + 0x60U + (offset * 2)))) = data;
}
//*****************************************************************************
//
//! Clears the Device to Host buffer (by making it Zero)
//!
//! \param offset specifies the offset of the D2H buffer
//! can vary from 0 to HIC_NUM_BUFFER_REGS-1
//!
//! \return none
//!
//! This API can be used to clear the content of D2H Buffer
//
//*****************************************************************************
static inline void
HIC_clearD2HBuffer(uint16_t offset)
{
//
//Check the arguments.
//
;
(*((volatile uint32_t *)(0x00006500U + 0x60U + (offset * 2)))) = 0U;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: hrcap.h
//
// TITLE: C28x HRCAP Driver.
//
//#############################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup hrcap_api HRCAP
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_hrcap.h
//
// TITLE: Definitions for the HRCAP registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the HRCAP register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL2 register
//
//*************************************************************************************************
// flags.
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECEINT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECAPSYNCINSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRINTEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRFRC register
//
//*************************************************************************************************
//*****************************************************************************
//
// Values that can be passed to HRCAP_enableCalibrationInterrupt(),
// HRCAP_disableCalibrationInterrupt() as the intFlags parameter and
// HRCAP_clearCalibrationFlags() and HRCAP_forceCalibrationFlags() as the flags
// parameter and returned by HRCAP_getCalibrationFlags().
//
//*****************************************************************************
//! Global calibration interrupt flag
//!
//! Calibration done flag
//!
//! Calibration period overflow flag
//!
//*****************************************************************************
//
//! Values that can be passed to HRCAP_getCalibrationClockPeriod() as the
//! \e clockSource parameter.
//
//*****************************************************************************
typedef enum
{
HRCAP_CALIBRATION_CLOCK_SYSCLK = 0x0, //!< Use SYSCLK for period match.
HRCAP_CALIBRATION_CLOCK_HRCLK = 0x4 //!< Use HRCLK for period match.
}HRCAP_CalibrationClockSource;
//*****************************************************************************
//
//! Values that can be passed to HRCAP_setCalibrationMode(),
//! as the \e continuousMode parameter.
//
//*****************************************************************************
typedef enum
{
//! Continuous calibration disabled.
HRCAP_CONTINUOUS_CALIBRATION_DISABLED = 0x00,
//! Continuous calibration enabled.
HRCAP_CONTINUOUS_CALIBRATION_ENABLED = 0x20
}HRCAP_ContinuousCalibrationMode;
//*****************************************************************************
//
//! \internal
//! Checks HRCAP base address.
//!
//! \param base specifies the HRCAP module base address.
//!
//! This function determines if an HRCAP module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! enables HRCAP.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function enables High Resolution Capture module.
//!
//! \note High resolution clock must be enabled before High Resolution Module
//! is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_enableHighResolution(uint32_t base)
{
;
__eallow();
//
// Set HRE bit.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Disables HRCAP.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function disable High Resolution Capture module.
//!
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_disableHighResolution(uint32_t base)
{
;
__eallow();
//
// Set HRE bit.
//
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! Enables high resolution clock.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function enables High Resolution clock.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_enableHighResolutionClock(uint32_t base)
{
;
__eallow();
//
// Set HRCLKE bit.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! Disables High resolution clock.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function disables High Resolution clock.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_disbleHighResolutionClock(uint32_t base)
{
;
__eallow();
//
// Clear HRCLKE bit.
//
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x2U;
__edis();
}
//*****************************************************************************
//
//! Starts calibration.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function starts calibration.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_startCalibration(uint32_t base)
{
;
__eallow();
//
// Set CALIBSTART bit.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x8U;
__edis();
}
//*****************************************************************************
//
//! Sets the calibration mode.
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function sets the the calibration mode by turning on continuous
//! calibration.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_setCalibrationMode(uint32_t base)
{
;
__eallow();
//
// Write to CALIBSTS and CALIBCONT bits.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x20U;
__edis();
}
//*****************************************************************************
//
//! Enables calibration interrupt.
//!
//! \param base is the base address of the HRCAP module.
//! \param intFlags is the calibration interrupt flags to be enabled.
//!
//! This function enables HRCAP calibration interrupt flags.
//! Valid values for intFlags are:
//! - HRCAP_CALIBRATION_DONE - Calibration done interrupt.
//! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow
//! check interrupt.
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_enableCalibrationInterrupt(uint32_t base, uint16_t intFlags)
{
;
;
__eallow();
//
// Set CALIBDONE or CALPRDCHKSTS.
//
(*((volatile uint16_t *)(base + 0x4U))) |= intFlags;
__edis();
}
//*****************************************************************************
//
//! Disables calibration interrupt source.
//!
//! \param base is the base address of the HRCAP module.
//! \param intFlags is the calibration interrupt flags to be disabled.
//!
//! This function disables HRCAP calibration interrupt flags.
//! Valid values for intFlags are:
//! - HRCAP_CALIBRATION_DONE - Calibration done interrupt.
//! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period check
//! interrupt.
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_disableCalibrationInterrupt(uint32_t base, uint16_t intFlags)
{
;
;
__eallow();
//
// Clear CALIBDONE or CALPRDCHKSTS.
//
(*((volatile uint16_t *)(base + 0x4U))) &= ~intFlags;
__edis();
}
//*****************************************************************************
//
//! Returns the calibration interrupt source.
//!
//! \param base is the base address of the HRCAP module.
//!
//! This function returns the HRCAP calibration interrupt source.
//!
//! \return Returns the HRCAP interrupt that has occurred. The following are
//! valid return values.
//! - HRCAP_GLOBAL_CALIBRATION_INTERRUPT - Global calibration
//! interrupt.
//! - HRCAP_CALIBRATION_DONE - Calibration done interrupt.
//! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow
//! interrupt.
//!
//! \note - User can check if a combination of the interrupts have occurred
//! by ORing the above return values.
//
//*****************************************************************************
static inline uint16_t
HRCAP_getCalibrationFlags(uint32_t base)
{
;
//
// Return contents of HRFLG register.
//
return((uint16_t)((*((volatile uint16_t *)(base + 0x6U))) & 0x7U));
}
//*****************************************************************************
//
//! Clears calibration flags.
//!
//! \param base is the base address of the HRCAP module.
//! \param flags is the calibration flags to be cleared.
//!
//! This function clears HRCAP calibration flags.
//! The following are valid values for flags.
//! - HRCAP_GLOBAL_CALIBRATION_INTERRUPT - Global calibration interrupt.
//! - HRCAP_CALIBRATION_DONE - Calibration done flag.
//! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_clearCalibrationFlags(uint32_t base, uint16_t flags)
{
;
;
//
// Write to HRCLR register.
//
(*((volatile uint16_t *)(base + 0x8U))) |= flags;
}
//*****************************************************************************
//
//! Return the Calibration status
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function returns the calibration status.
//!
//! \return This functions returns true if the calibration is in process,false
//! if there is no active calibration.
//
//*****************************************************************************
static inline _Bool
HRCAP_isCalibrationBusy(uint32_t base)
{
;
//
// Read CALIBSTS bit.
//
return(((*((volatile uint16_t *)(base + 0x0U))) & 0x10U) ==
0x10U);
}
//*****************************************************************************
//
//! Force a software based calibration
//!
//! \param base is the base address of the HRCAP instance used.
//! \param flag is the calibration flag source.
//!
//! This function forces a software based calibration done flag.
//! The following are valid values for flag.
//! - HRCAP_CALIBRATION_DONE - Calibration done flag.
//! - HRCAP_CALIBRATION_PERIOD_OVERFLOW - Calibration period overflow flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_forceCalibrationFlags(uint32_t base, uint16_t flag)
{
;
;
__eallow();
//
// Write to CALIBDONE or CALPRDCHKSTS bit.
//
(*((volatile uint16_t *)(base + 0xAU))) |= flag;
__edis();
}
//*****************************************************************************
//
//! Sets the calibration period count
//!
//! \param base is the base address of the HRCAP instance used.
//! \param sysclkHz is the rate of the SYSCLK in Hz.
//!
//! This function sets the calibration period count value to achieve a period
//! of 1.6 milliseconds given the SYSCLK frequency in Hz (the \e sysclkHz
//! parameter).
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_setCalibrationPeriod(uint32_t base, uint32_t sysclkHz)
{
;
__eallow();
(*((volatile uint32_t *)(base + 0xCU))) = (sysclkHz * 16U) / 10000U;
__edis();
}
//*****************************************************************************
//
//! Sets the calibration period count at a user configurable value.
//!
//! \param base is the base address of the HRCAP instance used.
//! \param sysclkHz is the rate of the SYSCLK in Hz.
//! \param periodInMs is the calibration period to be configured.
//!
//! This function sets the calibration period count value to the provided
//! period in milliseconds given the SYSCLK frequency in Hz (the \e sysclkHz
//! parameter).
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRCAP_configCalibrationPeriod(uint32_t base, uint32_t sysclkHz,
float periodInMs)
{
;
__eallow();
(*((volatile uint32_t *)(base + 0xCU))) =
(uint32_t)((float32_t)sysclkHz * periodInMs / 1000.0F);
__edis();
}
//*****************************************************************************
//
//! Returns the calibration clock period
//!
//! \param base is the base address of the HRCAP instance used.
//! \param clockSource is the calibration clock source
//! (\b HRCAP_CALIBRATION_CLOCK_SYSCLK or \b HRCAP_CALIBRATION_CLOCK_HRCLK).
//!
//! This function returns the period match value of the calibration clock. The
//! return value has a valid count when a period match occurs.
//!
//! \return This function returns the captured value of the clock counter
//! specified by clockSource.
//
//*****************************************************************************
static inline uint32_t
HRCAP_getCalibrationClockPeriod(uint32_t base,
HRCAP_CalibrationClockSource clockSource)
{
;
//
// Return HRCAP_O_HRSYSCLKCAP or HRCAP_O_HRCLKCAP.
//
return((*((volatile uint32_t *)(base + 0x10U + (uint32_t)clockSource))));
}
//*****************************************************************************
//
//! Calculates the scale factor
//!
//! \param base is the base address of the HRCAP instance used.
//!
//! This function reads the SYSCLK and HRCLK calibration periods and then
//! uses them to calculate the scale factor.
//!
//! \return This function returns the calculated scale factor.
//
//*****************************************************************************
static inline float32_t
HRCAP_getScaleFactor(uint32_t base)
{
;
//
// Calculate and return the scale factor.
//
return((float32_t)HRCAP_getCalibrationClockPeriod(base,
HRCAP_CALIBRATION_CLOCK_SYSCLK) /
(float32_t)HRCAP_getCalibrationClockPeriod(base,
HRCAP_CALIBRATION_CLOCK_HRCLK));
}
//*****************************************************************************
//
//! Returns event time stamp in nanoseconds
//!
//! \param timeStamp is a raw time stamp count returned by
//! ECAP_getEventTimeStamp().
//! \param scaleFactor is the calculated scale factor returned by
//! HRCAP_getScaleFactor().
//!
//! This function converts a raw CAP time stamp (the \e timeStamp parameter) to
//! nanoseconds using the provided scale factor (the \e scaleFactor parameter).
//!
//! \return Returns the converted time stamp in nanoseconds.
//
//*****************************************************************************
static inline float32_t
HRCAP_convertEventTimeStampNanoseconds(uint32_t timeStamp,
float32_t scaleFactor)
{
//
// Convert the raw count value to nanoseconds using the given scale factor.
//
return((float32_t)timeStamp * scaleFactor * ((float32_t)25.0 /
(float32_t)384.0));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//#############################################################################
//
// FILE: hrpwm.h
//
// TITLE: C28x HRPWM Driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup hrpwm_api HRPWM
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_hrpwm.h
//
// TITLE: Definitions for the HRPWM registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the HRPWM register offsets
//
//*************************************************************************************************
// Output A
// Output B
// Mirror Register
// Mirror Register
// Resolution Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMSYNCINSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TBSTS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMSYNCOUTEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TBCTL3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPCTL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DBCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DBCTL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQTSRCSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PCCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the VCAPCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the VCNTCFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCNFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRPWR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRMSTEP register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRCNFG2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the HRPCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TRREM register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCFG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMXLINK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLA register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLA2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLB register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCTLB2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQSFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the AQCSFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DBREDHR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DBRED register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DBFEDHR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DBFED register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TBPHS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPA register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CMPB register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GLDCTL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZDCSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCA register
//
//*************************************************************************************************
// UP
// DOWN
// UP
// DOWN
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCTLDCB register
//
//*************************************************************************************************
// UP
// DOWN
// UP
// DOWN
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZEINT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCBCFLG register
//
//*************************************************************************************************
// 2
// 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZOSTFLG register
//
//*************************************************************************************************
// 1
// 1
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZCBCCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZOSTCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the TZFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETPS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETFRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETINTPS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETSOCPS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCNTINITCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ETCNTINIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCTRIPSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCACTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCFCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCCAPCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the BLANKPULSEMIXSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCAHTRIPSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCALTRIPSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBHTRIPSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DCBLTRIPSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the EPWMLOCK register
//
//*************************************************************************************************
//#############################################################################
//
// FILE: hrpwm.h
//
// TITLE: C28x HRPWM Driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setMEPEdgeSelect(),
//! HRPWM_setMEPControlMode(), HRPWM_setCounterCompareShadowLoadEvent()
//! as the \e channel parameter.
//
//*****************************************************************************
typedef enum
{
HRPWM_CHANNEL_A = 0, //!< HRPWM A
HRPWM_CHANNEL_B = 8 //!< HRPWM B
} HRPWM_Channel;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setMEPEdgeSelect() as the \e mepEdgeMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! HRPWM is disabled
HRPWM_MEP_CTRL_DISABLE = 0,
//! MEP controls rising edge
HRPWM_MEP_CTRL_RISING_EDGE = 1,
//! MEP controls falling edge
HRPWM_MEP_CTRL_FALLING_EDGE = 2,
//! MEP controls both rising and falling edge
HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3
} HRPWM_MEPEdgeMode;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setHRMEPCtrlMode() as the \e
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! CMPAHR/CMPBHR or TBPRDHR controls MEP edge
HRPWM_MEP_DUTY_PERIOD_CTRL = 0,
//! TBPHSHR controls MEP edge
HRPWM_MEP_PHASE_CTRL = 1
} HRPWM_MEPCtrlMode;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setCounterCompareShadowLoadEvent(),
//! HRPWM_setRisingEdgeDelayLoadMode() and HRPWM_setFallingEdgeDelayLoadMode
//! as the \e loadEvent parameter.
//
//*****************************************************************************
typedef enum
{
//! load when counter equals zero
HRPWM_LOAD_ON_CNTR_ZERO = 0,
//! load when counter equals period
HRPWM_LOAD_ON_CNTR_PERIOD = 1,
//! load when counter equals zero or period
HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2,
} HRPWM_LoadMode;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setChannelBOutputPath() as the \e
//! outputOnB parameter.
//
//*****************************************************************************
typedef enum
{
HRPWM_OUTPUT_ON_B_NORMAL = 0, //!< ePWMxB output is normal.
HRPWM_OUTPUT_ON_B_INV_A = 1 //!< ePWMxB output is inverted
//!< version of ePWMxA signal
} HRPWM_ChannelBOutput;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setSyncPulseSource() as the \e
//! syncPulseSource parameter.
//
//*****************************************************************************
typedef enum
{
//! Counter equals Period
HRPWM_PWMSYNC_SOURCE_PERIOD = 0,
//! Counter equals zero
HRPWM_PWMSYNC_SOURCE_ZERO = 1,
//! Counter equals COMPC when counting up
HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4,
//! Counter equals COMPC when counting down
HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5,
//! Counter equals COMPD when counting up
HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6,
//! Counter equals COMPD when counting down
HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7
} HRPWM_SyncPulseSource;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setCounterCompareValue() as the \e
//! compModule parameter.
//
//*****************************************************************************
typedef enum
{
HRPWM_COUNTER_COMPARE_A = 0, //!< counter compare A
HRPWM_COUNTER_COMPARE_B = 4 //!< counter compare B
} HRPWM_CounterCompareModule;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_setDeadbandMEPEdgeSelect() as the \e
//! mepDBEdge.
//
//*****************************************************************************
typedef enum
{
//! HRPWM is disabled
HRPWM_DB_MEP_CTRL_DISABLE = 0,
//! MEP controls Rising Edge Delay
HRPWM_DB_MEP_CTRL_RED = 1,
//! MEP controls Falling Edge Delay
HRPWM_DB_MEP_CTRL_FED = 2,
//! MEP controls both Falling and Rising edge delay
HRPWM_DB_MEP_CTRL_RED_FED = 3
} HRPWM_MEPDeadBandEdgeMode;
//*****************************************************************************
//
//! Values that can be passed to HRPWM_lockRegisters() as the \e registerGroup
//! parameter.
//
//*****************************************************************************
typedef enum
{
HRPWM_REGISTER_GROUP_HRPWM = 0x1, //!< HRPWM register group
HRPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2, //!< Global load register group
HRPWM_REGISTER_GROUP_TRIP_ZONE = 0x4, //!< Trip zone register group
HRPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group
HRPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group
} HRPWM_LockRegisterGroup;
//*****************************************************************************
//
// Functions APIs shared with ePWM module
//
//*****************************************************************************
//
// Time Base Sub Module related APIs
//
//
// Action Qualifier module related APIs
//
/* HRPWM_setActionQualifierSwAction is kept for compatibility,
use HRPWM_setActionQualifierSWAction*/
/* HRPWM_forceActionQualifierSwAction is kept for compatibility,
use HRPWM_forceActionQualifierSWAction*/
//
// Dead Band Module related APIs
//
//
// Chopper module related APIs
//
//
// Trip Zone module related APIs
//
//
// HRPWM_getTripZoneInterruptStatus API define is obsolete please use
// HRPWM_getTripZoneFlagStatus going forward.
//
//
// HRPWM_getCycleByCycleTripZoneInterruptStatus API define is obsolete
// please use HRPWM_getCycleByCycleTripZoneFlagStatus going forward.
//
//
// HRPWM_getOneShotTripZoneInterruptStatus is obsolete please use
// HRPWM_getOneShotTripZoneFlagStatus going forward.
//
//
// HRPWM_clearTripZoneInterruptFlag is obsolete please use
// HRPWM_clearTripZoneFlag going forward.
//
//
// HRPWM_clearCycleByCycleTripZoneInterruptFlag is obsolete please use
// HRPWM_clearCycleByCycleTripZoneFlag going forward.
//
//
// HRPWM_clearOneShotTripZoneInterruptFlag is obsolete please use
// HRPWM_clearOneShotTripZoneFlag going forward.
//
//
// Event Trigger related APIs
//
//
// ADC SOC configuration related APIs
//
//
// Digital Compare Module related APIs
//
//
// Valley switching related APIs
//
//
// Global Load feature related APIs
//
//*****************************************************************************
//
// Prototypes for the API.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks HRPWM base address.
//!
//! \param base specifies the HRPWM module base address.
//!
//! This function determines if an HRPWM module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the consolidated phase shift value in high resolution mode.
//!
//! \param base is the base address of the EPWM module.
//! \param phaseCount is the consolidated phase shift count value.
//!
//! This function sets the consolidated phase shift value, that is, both TBPHS
//! and TBPHSHR values are configured together.
//!
//! Call EPWM_enablePhaseShiftLoad & HRPWM_enableHRPhaseShiftLoad() functions
//! to enable loading of the phaseCount in high resolution mode.
//!
//! \b Note: phaseCount is a 24-bit value.
//! \b Note: For configuring TBPHS = 0x3C, TBPHSHR = 0x2;
//! phaseCount = 0x3C02
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
{
//
// Check the arguments
//
;
;
//
// Write to TBPHS:TBPHSHR bits
//
(*((volatile uint32_t *)(base + 0x60U))) = phaseCount << 8U;
}
//*****************************************************************************
//
//! Sets only the high resolution phase shift value.
//!
//! \param base is the base address of the EPWM module.
//! \param hrPhaseCount is the high resolution phase shift count value.
//!
//! This function sets only the high resolution phase shift(TBPHSHR) value.
//! Call the HRPWM_enableHRPhaseShiftLoad() function to enable loading of
//! the hrPhaseCount.
//!
//! \b Note: hrPhaseCount is an 8-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResPhaseShiftOnly(uint32_t base, uint16_t hrPhaseCount)
{
//
// Check the arguments
//
;
;
//
// Write to TBPHSHR bits
//
(*((volatile uint16_t *)(base + 0x60U))) = hrPhaseCount << 8U;
}
//*****************************************************************************
//
//! Sets the consolidated period of time base counter used in HR mode.
//!
//! \param base is the base address of the EPWM module.
//! \param periodCount is the consolidated period count value.
//!
//! This function sets the consolidated period of time base counter value
//! (TBPRD:TBPRDHR) required in high resolution mode.
//!
//! User should map the desired period or frequency of the waveform into
//! the correct periodCount.
//!
//! \b Note: periodCount is a 24 bit value.
//! \b Note: For configuring TBPRD = 0x3C, TBPRDHR = 0xA;
//! periodCount = 0x3C0A
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setTimeBasePeriod(uint32_t base, uint32_t periodCount)
{
//
// Check the arguments
//
;
;
//
// Write to TBPRD:TBPRDHR bits
//
(*((volatile uint32_t *)(base + 0x62U))) = periodCount << 8U;
}
//*****************************************************************************
//
//! Sets only the high resolution time base counter.
//!
//! \param base is the base address of the EPWM module.
//! \param hrPeriodCount is the high resolution period count value.
//!
//! This function sets only the high resolution time base counter(TBPRDHR)
//! value.
//!
//! User should map the desired period or frequency of the waveform into
//! the correct hrPeriodCount.
//!
//! \b Note: hrPeriodCount is an 8-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResTimeBasePeriodOnly(uint32_t base, uint16_t hrPeriodCount)
{
//
// Check the arguments
//
;
;
//
// Write to TBPRDHR bits
//
(*((volatile uint16_t *)(base + 0x62U))) = hrPeriodCount << 8U;
}
//*****************************************************************************
//
//! Gets the consolidated time base period count used in HR mode
//!
//! \param base is the base address of the EPWM module.
//!
//! This function gets the consolidated time base period(TBPRD:TBPRDHR) value
//! used in high resolution mode.
//!
//! \return The consolidated time base period count value.
//
//*****************************************************************************
static inline uint32_t
HRPWM_getTimeBasePeriod(uint32_t base)
{
//
// Check the arguments
//
;
//
// Read from TBPRD:TBPRDHR bit
//
return((*((volatile uint32_t *)(base + 0x62U))) >> 8U);
}
//*****************************************************************************
//
//! Gets the only the high resolution time base period count.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function gets only the high resolution time base period(TBPRDHR) value.
//!
//! \return The high resolution time base period count value.
//
//*****************************************************************************
static inline uint16_t
HRPWM_getHiResTimeBasePeriodOnly(uint32_t base)
{
//
// Check the arguments
//
;
//
// Read from TBPRDHR bit
//
return((*((volatile uint16_t *)(base + 0x62U))) >> 8U);
}
//*****************************************************************************
//
//! Sets the high resolution edge controlled by MEP (Micro Edge Positioner).
//!
//! \param base is the base address of the EPWM module.
//! \param channel is high resolution period module.
//! \param mepEdgeMode edge of the PWM that is controlled by MEP (Micro Edge
//! Positioner).
//!
//! This function sets the edge of the PWM that is controlled by MEP (Micro
//! Edge Positioner). Valid values for the parameters are:
//! - channel
//! - HRPWM_CHANNEL_A - HRPWM A
//! - HRPWM_CHANNEL_B - HRPWM B
//! - mepEdgeMode
//! - HRPWM_MEP_CTRL_DISABLE - HRPWM is disabled
//! - HRPWM_MEP_CTRL_RISING_EDGE - MEP (Micro Edge Positioner)
//! controls rising edge.
//! - HRPWM_MEP_CTRL_FALLING_EDGE - MEP (Micro Edge Positioner)
//! controls falling edge.
//! - HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE - MEP (Micro Edge Positioner)
//! controls both edges.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel,
HRPWM_MEPEdgeMode mepEdgeMode)
{
//
// Check the arguments
//
;
//
// Set the edge mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x20U))) =
(((*((volatile uint16_t *)(base + 0x20U))) & ~(0x3U << (uint16_t)channel )) |
((uint16_t)mepEdgeMode << (uint16_t)channel));
__edis();
}
//*****************************************************************************
//
//! Sets the MEP (Micro Edge Positioner) control mode.
//!
//! \param base is the base address of the EPWM module.
//! \param channel is high resolution period module.
//! \param mepCtrlMode is the MEP (Micro Edge Positioner) control mode.
//!
//! This function sets the mode (register type) the MEP (Micro Edge Positioner)
//! will control. Valid values for the parameters are:
//! - channel
//! - HRPWM_CHANNEL_A - HRPWM A
//! - HRPWM_CHANNEL_B - HRPWM B
//! - mepCtrlMode
//! - HRPWM_MEP_DUTY_PERIOD_CTRL - MEP (Micro Edge Positioner) is
//! controlled by value of CMPAHR/
//! CMPBHR(depending on the value of
//! channel) or TBPRDHR.
//! - HRPWM_MEP_PHASE_CTRL - MEP (Micro Edge Positioner) is
//! controlled by TBPHSHR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel,
HRPWM_MEPCtrlMode mepCtrlMode)
{
//
// Check the arguments
//
;
//
// Set the MEP control
//
__eallow();
(*((volatile uint16_t *)(base + 0x20U))) =
(((*((volatile uint16_t *)(base + 0x20U))) & ~(0x1U << ((uint16_t)channel + 2U))) |
((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U)));
__edis();
}
//*****************************************************************************
//
//! Sets the high resolution comparator load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param channel is high resolution period module.
//! \param loadEvent is the MEP (Micro Edge Positioner) control mode.
//!
//! This function sets the shadow load mode of the high resolution comparator.
//! The function sets the COMPA or COMPB register depending on the channel
//! variable.
//! Valid values for the parameters are:
//! - channel
//! - HRPWM_CHANNEL_A - HRPWM A
//! - HRPWM_CHANNEL_B - HRPWM B
//! - loadEvent
//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero
//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period
//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or
//! period
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel,
HRPWM_LoadMode loadEvent)
{
//
// Check the arguments
//
;
//
// Set the CMPAHR or CMPBHR load mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x20U))) =
(((*((volatile uint16_t *)(base + 0x20U))) & ~(0x3U << ((uint16_t)channel + 3U))) |
((uint16_t)loadEvent << ((uint16_t)channel + 3U)));
__edis();
}
//*****************************************************************************
//
//! Sets the high resolution output swap mode.
//!
//! \param base is the base address of the EPWM module.
//! \param enableOutputSwap is the output swap flag.
//!
//! This function sets the HRPWM output swap mode. If enableOutputSwap is true,
//! ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA
//! output. If it is false ePWMxA and ePWMxB outputs are unchanged.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setOutputSwapMode(uint32_t base, _Bool enableOutputSwap)
{
//
// Check the arguments
//
;
//
// Set output swap mode
//
__eallow();
if(enableOutputSwap)
{
(*((volatile uint16_t *)(base + 0x20U))) |= 0x80U;
}
else
{
(*((volatile uint16_t *)(base + 0x20U))) &= ~0x80U;
}
__edis();
}
//*****************************************************************************
//
//! Sets the high resolution output on ePWMxB
//!
//! \param base is the base address of the EPWM module.
//! \param outputOnB is the output signal on ePWMxB.
//!
//! This function sets the HRPWM output signal on ePWMxB. If outputOnB is
//! HRPWM_OUTPUT_ON_B_INV_A, ePWMxB output is an inverted version of
//! ePWMxA. If outputOnB is HRPWM_OUTPUT_ON_B_NORMAL, ePWMxB output is
//! ePWMxB.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
{
//
// Check the arguments
//
;
//
// Set the output on ePWM B
//
__eallow();
(*((volatile uint16_t *)(base + 0x20U))) =
(((*((volatile uint16_t *)(base + 0x20U))) & ~(0x20U)) |
((uint16_t)outputOnB << 5U));
__edis();
}
//*****************************************************************************
//
//! Enables MEP (Micro Edge Positioner) automatic scale mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the MEP (Micro Edge Positioner) to automatically
//! scale HRMSTEP.
//!
//! The SFO library will calculate required MEP steps per coarse steps and
//! feed it to HRMSTEP register. The MEP calibration module will use the value
//! in HRMSTEP to determine appropriate number of MEP steps represented by
//! fractional duty cycle.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_enableAutoConversion(uint32_t base)
{
//
// Check the arguments
//
;
//
// Enable MEP automatic scale
//
__eallow();
(*((volatile uint16_t *)(base + 0x20U))) |= 0x40U;
__edis();
}
//*****************************************************************************
//
//! Disables MEP automatic scale mode.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the MEP (Micro Edge Positioner) from automatically
//! scaling HRMSTEP.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_disableAutoConversion(uint32_t base)
{
//
// Check the arguments
//
;
//
// Disable MEP automatic scale
//
__eallow();
(*((volatile uint16_t *)(base + 0x20U))) &= ~0x40U;
__edis();
}
//*****************************************************************************
//
//! Enable high resolution period feature.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables the high resolution period feature.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_enablePeriodControl(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set HRPE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x2DU))) |= 0x1U;
__edis();
}
//*****************************************************************************
//
//! Disable high resolution period feature.
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables the high resolution period feature.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_disablePeriodControl(uint32_t base)
{
//
// Check the arguments
//
;
//
// Clear HRPE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x2DU))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! Enable high resolution phase load
//!
//! \param base is the base address of the EPWM module.
//!
//! This function enables loading of high resolution phase shift value which is
//! set by the function HRPWM_setPhaseShift().
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_enablePhaseShiftLoad(uint32_t base)
{
//
// Check the arguments
//
;
//
// Set TBPHSHRLOADE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x2DU))) |= 0x4U;
__edis();
}
//*****************************************************************************
//
//! Disable high resolution phase load
//!
//! \param base is the base address of the EPWM module.
//!
//! This function disables loading of high resolution phase shift value.
//!
//! \return
//
//*****************************************************************************
static inline void
HRPWM_disablePhaseShiftLoad(uint32_t base)
{
//
// Check the arguments
//
;
//
// Clear TBPHSHRLOADE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x2DU))) &= ~0x4U;
__edis();
}
//*****************************************************************************
//
//! Set high resolution PWMSYNC source.
//!
//! \param base is the base address of the EPWM module.
//! \param syncPulseSource is the PWMSYNC source.
//!
//! This function sets the high resolution PWMSYNC pulse source.
//! Valid values for syncPulseSource are:
//! - HRPWM_PWMSYNC_SOURCE_PERIOD - Counter equals Period.
//! - HRPWM_PWMSYNC_SOURCE_ZERO - Counter equals zero.
//! - HRPWM_PWMSYNC_SOURCE_COMPC_UP - Counter equals COMPC when
//! counting up.
//! - HRPWM_PWMSYNC_SOURCE_COMPC_DOWN - Counter equals COMPC when
//! counting down.
//! - HRPWM_PWMSYNC_SOURCE_COMPD_UP - Counter equals COMPD when
//! counting up.
//! - HRPWM_PWMSYNC_SOURCE_COMPD_DOWN - Counter equals COMPD when
//! counting down.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
{
//
// Set the PWMSYNC source
//
__eallow();
//
// Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD
// or HRPWM_PWMSYNC_SOURCE_ZERO
//
if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP)
{
(*((volatile uint16_t *)(base + 0x2DU))) =
(((*((volatile uint16_t *)(base + 0x2DU))) &
~(0x70U | 0x2U)) |
((uint16_t)syncPulseSource << 1U));
}
else
{
(*((volatile uint16_t *)(base + 0x2DU))) =
(((*((volatile uint16_t *)(base + 0x2DU))) & ~0x70U) |
((uint16_t)syncPulseSource << 4U));
}
__edis();
}
//*****************************************************************************
//
//! Sets the Translator Remainder value.
//!
//! \param base is the base address of the EPWM module.
//! \param trremVal is the translator remainder value.
//!
//! This function sets the Translator Remainder value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
{
//
// Check the arguments
//
;
;
//
// Set Translator Remainder value
//
__eallow();
(*((volatile uint16_t *)(base + 0x2EU))) = (trremVal & 0x7FFU);
__edis();
}
//*****************************************************************************
//
//! Sets the consolidated counter compare values in HR mode.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module.
//! \param compCount is the consolidated counter compare count value.
//!
//! This function sets the consolidated counter compare(CMPx:CMPxHR) value
//! required in high resolution mode for counter compare registers.
//! Valid values for compModule are:
//! - HRPWM_COUNTER_COMPARE_A - counter compare A.
//! - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \b Note: compCount is a 24 bit value.
//! \b Note: For configuring CMPA = 0xB4, CMPAHR = 0x64; value of
//! compCount = 0xB464
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setCounterCompareValue(uint32_t base,
HRPWM_CounterCompareModule compModule,
uint32_t compCount)
{
//
// Check the arguments
//
;
;
//
// Write to counter compare registers
//
if(compModule == HRPWM_COUNTER_COMPARE_A)
{
//
// Write to CMPA:CMPAHR
//
(*((volatile uint32_t *)(base + 0x6AU))) = compCount << 8U;
}
else
{
//
// Write to CMPB:CMPBHR
//
(*((volatile uint32_t *)(base + 0x6CU))) = compCount << 8U;
}
}
//*****************************************************************************
//
//! Sets only the high resolution counter compare value.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module.
//! \param hrCompCount is the high resolution counter compare count value.
//!
//! This function sets the high resolution counter compare value(CMPxHR) for
//! counter compare registers.
//! Valid values for compModule are:
//! - HRPWM_COUNTER_COMPARE_A - counter compare A.
//! - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \b Note: hrCompCount is an 8-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResCounterCompareValueOnly(uint32_t base,
HRPWM_CounterCompareModule compModule,
uint16_t hrCompCount)
{
//
// Check the arguments
//
;
;
//
// Write to the high resolution counter compare registers
//
if(compModule == HRPWM_COUNTER_COMPARE_A)
{
//
// Write to CMPAHR
//
(*((volatile uint16_t *)(base + 0x6AU))) = hrCompCount << 8U;
}
else
{
//
// Write to CMPBHR
//
(*((volatile uint16_t *)(base + 0x6CU))) = hrCompCount << 8U;
}
}
//*****************************************************************************
//
//! Gets the consolidated counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module value.
//!
//! This function gets the consolidated counter compare(CMPx:CMPxHR) value
//! used in high resolution for the counter compare module specified.
//! Valid values for compModule are:
//! - HRPWM_COUNTER_COMPARE_A - counter compare A.
//! - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//!
//! \return None.
//
//*****************************************************************************
static inline uint32_t
HRPWM_getCounterCompareValue(uint32_t base,
HRPWM_CounterCompareModule compModule)
{
uint32_t compCount;
//
// Check the arguments
//
;
//
// Get counter compare value for selected module
//
if(compModule == HRPWM_COUNTER_COMPARE_A)
{
//
// Read from CMPAHR
//
compCount = (*((volatile uint32_t *)(base + 0x6AU))) >> 8U;
}
else
{
//
// Read from CMPBHR
//
compCount = (*((volatile uint32_t *)(base + 0x6CU))) >> 8U;
}
return(compCount);
}
//*****************************************************************************
//
//! Gets only the high resolution counter compare values.
//!
//! \param base is the base address of the EPWM module.
//! \param compModule is the Counter Compare module value.
//!
//! This function gets only the high resolution counter compare(CMPxHR) value
//! for the counter compare module specified.
//! Valid values for compModule are:
//! - HRPWM_COUNTER_COMPARE_A - counter compare A.
//! - HRPWM_COUNTER_COMPARE_B - counter compare B.
//!
//! \return None.
//
//*****************************************************************************
static inline uint16_t
HRPWM_getHiResCounterCompareValueOnly(uint32_t base,
HRPWM_CounterCompareModule compModule)
{
uint16_t hrCompCount;
//
// Check the arguments
//
;
//
// Get counter compare value for selected module
//
if(compModule == HRPWM_COUNTER_COMPARE_A)
{
//
// Read from CMPAHR
//
hrCompCount = (*((volatile uint16_t *)(base + 0x6AU))) >> 8U;
}
else
{
//
// Read from CMPBHR
//
hrCompCount = (*((volatile uint16_t *)(base + 0x6CU))) >> 8U;
}
return(hrCompCount);
}
//*****************************************************************************
//
//! Sets the consolidated RED count in high resolution mode.
//!
//! \param base is the base address of the EPWM module.
//! \param redCount is the high resolution RED count.
//!
//! This function sets the consolidated RED (Rising Edge Delay) count
//! (DBRED:DBREDHR) value used in high resolution mode. The value of
//! redCount should be less than 0x200000.
//!
//! \b Note: redCount is a 21 bit value.
//! \b Note: For configuring DBRED = 0x4, DBREDHR = 0x1; value of
//! redCount = ((0x4 << 7) | 0x1) = 0x201
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setRisingEdgeDelay(uint32_t base, uint32_t redCount)
{
//
// Check the arguments
//
;
;
//
// Set the consolidated RED (Rising Edge Delay) count
//
(*((volatile uint32_t *)(base + 0x50U))) = redCount << 9U;
}
//*****************************************************************************
//
//! Sets the high resolution RED count only.
//!
//! \param base is the base address of the EPWM module.
//! \param hrRedCount is the high resolution RED count.
//!
//! This function sets only the high resolution RED (Rising Edge Delay)
//! count(DBREDHR) value.
//! The value of hrRedCount should be less than 128.
//!
//! \b Note: hrRedCount is a 7-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResRisingEdgeDelayOnly(uint32_t base, uint16_t hrRedCount)
{
//
// Check the arguments
//
;
;
//
// Set the High Resolution RED (Rising Edge Delay) count only
//
(*((volatile uint16_t *)(base + 0x50U))) = hrRedCount << 9U;
}
//*****************************************************************************
//
//! Sets the consolidated FED value in high resolution mode.
//!
//! \param base is the base address of the EPWM module.
//! \param fedCount is the high resolution FED count.
//!
//! This function sets the consolidated FED (Falling Edge Delay) count
//! (DBFED: DBFEDHR) value used in high resolution mode. The value of fedCount
//! should be less than 0x200000.
//!
//! \b Note: fedCount is a 21 bit value.
//! \b Note: For configuring DBFED = 0x4, DBFEDHR = 0x1; value of
//! fedCount = ((0x4 << 7) | 0x1) = 0x201
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setFallingEdgeDelay(uint32_t base, uint32_t fedCount)
{
//
// Check the arguments
//
;
;
//
// Set the High Resolution FED (Falling Edge Delay) count
//
(*((volatile uint32_t *)(base + 0x52U))) = fedCount << 9U;
}
//*****************************************************************************
//
//! Sets high resolution FED count only.
//!
//! \param base is the base address of the EPWM module.
//! \param hrFedCount is the high resolution FED count.
//!
//! This function sets only the high resolution FED (Falling Edge Delay) count
//! (DBFEDHR)value. The value of hrFedCount should be less than 128.
//!
//! \b Note: hrFedCount is a 7-bit value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
{
//
// Check the arguments
//
;
;
//
// Set the high resolution FED (Falling Edge Delay) count
//
(*((volatile uint16_t *)(base + 0x52U))) = hrFedCount << 9U;
}
//*****************************************************************************
//
//! Set high resolution MEP (Micro Edge Positioner) step.
//!
//! \param base is the base address of the EPWM module.
//! \param mepCount is the high resolution MEP (Micro Edge Positioner) step
//! count.
//!
//! This function sets the high resolution MEP (Micro Edge Positioner) step
//! count. The maximum value for the MEP count step is 255.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
{
//
// Check the arguments
//
;
;
//
// Set HRPWM MEP count
//
__eallow();
(*((volatile uint16_t *)(base + 0x26U))) =
(((*((volatile uint16_t *)(base + 0x26U))) & ~0xFFU) |
mepCount);
__edis();
}
//*****************************************************************************
//
//! Set high resolution Dead Band MEP (Micro Edge Positioner) control.
//!
//! \param base is the base address of the EPWM module.
//! \param mepDBEdge is the high resolution MEP (Micro Edge Positioner) control
//! edge.
//!
//! This function sets the high resolution Dead Band edge that the MEP (Micro
//! Edge Positioner) controls Valid values for mepDBEdge are:
//! - HRPWM_DB_MEP_CTRL_DISABLE - HRPWM is disabled
//! - HRPWM_DB_MEP_CTRL_RED - MEP (Micro Edge Positioner) controls
//! Rising Edge Delay
//! - HRPWM_DB_MEP_CTRL_FED - MEP (Micro Edge Positioner) controls
//! Falling Edge Delay
//! - HRPWM_DB_MEP_CTRL_RED_FED - MEP (Micro Edge Positioner) controls both
//! Falling and Rising edge delays
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setDeadbandMEPEdgeSelect(uint32_t base,
HRPWM_MEPDeadBandEdgeMode mepDBEdge)
{
//
// Check the arguments
//
;
//
// Set the HRPWM DB edge mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x27U))) =
(((*((volatile uint16_t *)(base + 0x27U))) & ~0x3U) |
((uint16_t)mepDBEdge));
__edis();
}
//*****************************************************************************
//
//! Set the high resolution Dead Band RED load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadEvent is the shadow to active load event.
//!
//! This function sets the high resolution Rising Edge Delay(RED)Dead Band
//! count load mode.
//! Valid values for loadEvent are:
//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero.
//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period
//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero
//! or period.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setRisingEdgeDelayLoadMode(uint32_t base,
HRPWM_LoadMode loadEvent)
{
//
// Check the arguments
//
;
//
// Set the HRPWM RED load mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x27U))) =
(((*((volatile uint16_t *)(base + 0x27U))) & ~0xCU) |
((uint16_t)loadEvent << 2U));
__edis();
}
//*****************************************************************************
//
//! Set the high resolution Dead Band FED load mode.
//!
//! \param base is the base address of the EPWM module.
//! \param loadEvent is the shadow to active load event.
//!
//! This function sets the high resolution Falling Edge Delay(FED) Dead Band
//! count load mode.
//! Valid values for loadEvent are:
//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero.
//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period
//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero
//! or period.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
{
//
// Check the arguments
//
;
//
// Set the HRPWM FED load mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x27U))) =
(((*((volatile uint16_t *)(base + 0x27U))) & ~0x30U) |
((uint16_t)loadEvent << 4U));
__edis();
}
//*****************************************************************************
//
//! Lock EALLOW protected register groups
//!
//! \param base is the base address of the EPWM module.
//! \param registerGroup is the EALLOW register groups.
//!
//! This functions locks the EALLOW protected register groups specified by
//! the registerGroup variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
HRPWM_lockRegisters(uint32_t base, HRPWM_LockRegisterGroup registerGroup)
{
//
// Check the arguments
//
;
//
// Write the Key to EPWMLOCK register
//
(*((volatile uint32_t *)(base + 0xFAU))) =
(0xA5A50000UL | ((uint32_t)registerGroup));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: i2c.h
//
// TITLE: C28x I2C driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup i2c_api I2C
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_i2c.h
//
// TITLE: Definitions for the I2C registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the I2C register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2COAR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CIER register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CSTR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CDRR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CSAR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CDXR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CMDR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CISRC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CEMDR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CPSC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CFFTX register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CFFRX register
//
//*************************************************************************************************
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// I2C Controller commands.
//
//*****************************************************************************
//*****************************************************************************
//
// I2C interrupts for use with the intFlags parameter of I2C_enableInterrupt(),
// I2C_disableInterrupt(), and I2C_clearInterruptStatus() and to be returned by
// I2C_getInterruptStatus().
//
//*****************************************************************************
//
// Helpful define to mask out the bits in the I2CSTR register that aren't
// associated with interrupts.
//
//*****************************************************************************
//
// Flags for use as the stsFlags parameter of I2C_clearStatus() and to be
// returned by I2C_getStatus().
//
//*****************************************************************************
//*****************************************************************************
//
//! I2C interrupts to be returned by I2C_getInterruptSource().
//
//*****************************************************************************
typedef enum
{
I2C_INTSRC_NONE, //!< No interrupt pending
I2C_INTSRC_ARB_LOST, //!< Arbitration-lost interrupt
I2C_INTSRC_NO_ACK, //!< NACK interrupt
I2C_INTSRC_REG_ACCESS_RDY, //!< Register-access-ready interrupt
I2C_INTSRC_RX_DATA_RDY, //!< Receive-data-ready interrupt
I2C_INTSRC_TX_DATA_RDY, //!< Transmit-data-ready interrupt
I2C_INTSRC_STOP_CONDITION, //!< Stop condition detected
I2C_INTSRC_ADDR_TARGET //!< Addressed as target interrupt
} I2C_InterruptSource;
//*****************************************************************************
//
//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e txLevel
//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e txLevel
//! parameter, and returned by I2C_getTxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
I2C_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty
I2C_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty
I2C_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full
I2C_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full
I2C_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full
I2C_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full
I2C_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full
I2C_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full
I2C_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full
I2C_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full
I2C_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full
I2C_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full
I2C_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full
I2C_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full
I2C_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full
I2C_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full
I2C_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full
I2C_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full
I2C_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full
} I2C_TxFIFOLevel;
//*****************************************************************************
//
//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e rxLevel
//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e rxLevel
//! parameter, and returned by I2C_getRxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
I2C_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty
I2C_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty
I2C_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full
I2C_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full
I2C_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full
I2C_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full
I2C_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full
I2C_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full
I2C_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full
I2C_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full
I2C_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full
I2C_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full
I2C_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full
I2C_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full
I2C_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full
I2C_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full
I2C_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full
I2C_FIFO_RX16 = 0x0010U, //!< Receive FIFO full
I2C_FIFO_RXFULL = 0x0010U //!< Receive FIFO full
} I2C_RxFIFOLevel;
//*****************************************************************************
//
//! Values that can be passed to I2C_setBitCount() as the \e size parameter.
//
//*****************************************************************************
typedef enum
{
I2C_BITCOUNT_1 = 1U, //!< 1 bit per data byte
I2C_BITCOUNT_2 = 2U, //!< 2 bits per data byte
I2C_BITCOUNT_3 = 3U, //!< 3 bits per data byte
I2C_BITCOUNT_4 = 4U, //!< 4 bits per data byte
I2C_BITCOUNT_5 = 5U, //!< 5 bits per data byte
I2C_BITCOUNT_6 = 6U, //!< 6 bits per data byte
I2C_BITCOUNT_7 = 7U, //!< 7 bits per data byte
I2C_BITCOUNT_8 = 0U //!< 8 bits per data byte
} I2C_BitCount;
//*****************************************************************************
//
//! Values that can be passed to I2C_setAddressMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
I2C_ADDR_MODE_7BITS = 0x0000U, //!< 7-bit address
I2C_ADDR_MODE_10BITS = 0x0100U //!< 10-bit address
} I2C_AddressMode;
//*****************************************************************************
//
//! Values that can be passed to I2C_setExtendedMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
I2C_EADDR_MODE_BC = 1U, //!< Backward compatibility
I2C_EADDR_MODE_FWD = 2U //!< Forward compatibility
} I2C_ExtendedMode;
//*****************************************************************************
//
//! Values that can be passed to I2C_setEmulationMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! If SCL is low, keep it low. If high, stop when it goes low again.
I2C_EMULATION_STOP_SCL_LOW = 0x0000U,
//! Continue I2C operation regardless
I2C_EMULATION_FREE_RUN = 0x4000U
} I2C_EmulationMode;
//*****************************************************************************
//
//! Values that can be passed to I2C_initController() as the \e dutyCycle
//! parameter.
//
//*****************************************************************************
typedef enum
{
I2C_DUTYCYCLE_33, //!< Clock duty cycle is 33%
I2C_DUTYCYCLE_50 //!< Clock duty cycle is 55%
} I2C_DutyCycle;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an I2C base address.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function determines if a I2C module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function enables operation of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_enableModule(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x9U))) |= 0x20U;
}
//*****************************************************************************
//
//! Disables the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function disables operation of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_disableModule(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x9U))) &= ~(0x20U);
}
//*****************************************************************************
//
//! Enables the transmit and receive FIFOs.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This functions enables the transmit and receive FIFOs in the I2C.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_enableFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the FIFO.
//
(*((volatile uint16_t *)(base + 0x20U))) |= 0x4000U | 0x2000U;
(*((volatile uint16_t *)(base + 0x21U))) |= 0x2000U;
}
//*****************************************************************************
//
//! Disables the transmit and receive FIFOs.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This functions disables the transmit and receive FIFOs in the I2C.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_disableFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the FIFO.
//
(*((volatile uint16_t *)(base + 0x20U))) &= ~(0x4000U | 0x2000U);
(*((volatile uint16_t *)(base + 0x21U))) &= ~0x2000U;
}
//*****************************************************************************
//
//! Sets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the I2C instance used.
//! \param txLevel is the transmit FIFO interrupt level, specified as
//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, . . . or
//! \b I2C_FIFO_TX16.
//! \param rxLevel is the receive FIFO interrupt level, specified as
//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, . . . or
//! \b I2C_FIFO_RX16.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated. The transmit FIFO interrupt flag will be set when the FIFO
//! reaches a value less than or equal to \e txLevel. The receive FIFO
//! flag will be set when the FIFO reaches a value greater than or equal to
//! \e rxLevel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel txLevel,
I2C_RxFIFOLevel rxLevel)
{
//
// Check the arguments.
//
;
//
// Set the FIFO interrupt levels.
//
(*((volatile uint16_t *)(base + 0x20U))) = ((*((volatile uint16_t *)(base + 0x20U))) &
(~0x1FU)) | (uint16_t)txLevel;
(*((volatile uint16_t *)(base + 0x21U))) = ((*((volatile uint16_t *)(base + 0x21U))) &
(~0x1FU)) | (uint16_t)rxLevel;
}
//*****************************************************************************
//
//! Gets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the I2C instance used.
//! \param txLevel is a pointer to storage for the transmit FIFO level,
//! returned as one of \b I2C_FIFO_TX0, \b I2C_FIFO_TX1,
//! \b I2C_FIFO_TX2, . . . or \b I2C_FIFO_TX16.
//! \param rxLevel is a pointer to storage for the receive FIFO level,
//! returned as one of \b I2C_FIFO_RX0, \b I2C_FIFO_RX1,
//! \b I2C_FIFO_RX2, . . . or \b I2C_FIFO_RX16.
//!
//! This function gets the FIFO level at which transmit and receive interrupts
//! are generated. The transmit FIFO interrupt flag will be set when the FIFO
//! reaches a value less than or equal to \e txLevel. The receive FIFO
//! flag will be set when the FIFO reaches a value greater than or equal to
//! \e rxLevel.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_getFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel *txLevel,
I2C_RxFIFOLevel *rxLevel)
{
//
// Check the arguments.
//
;
//
// Extract the transmit and receive FIFO levels.
//
*txLevel = (I2C_TxFIFOLevel)((*((volatile uint16_t *)(base + 0x20U))) &
0x1FU);
*rxLevel = (I2C_RxFIFOLevel)((*((volatile uint16_t *)(base + 0x21U))) &
0x1FU);
}
//*****************************************************************************
//
//! Get the transmit FIFO status
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function gets the current number of words in the transmit FIFO.
//!
//! \return Returns the current number of words in the transmit FIFO specified
//! as one of the following:
//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, \b I2C_FIFO_TX3,
//! ..., or \b I2C_FIFO_TX16
//
//*****************************************************************************
static inline I2C_TxFIFOLevel
I2C_getTxFIFOStatus(uint32_t base)
{
uint16_t level;
//
// Check the arguments.
//
;
//
// Get the current FIFO status
//
level = (((*((volatile uint16_t *)(base + 0x20U))) & 0x1F00U) >>
8U);
return((I2C_TxFIFOLevel)level);
}
//*****************************************************************************
//
//! Get the receive FIFO status
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function gets the current number of words in the receive FIFO.
//!
//! \return Returns the current number of words in the receive FIFO specified
//! as one of the following:
//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, \b I2C_FIFO_RX3,
//! ..., or \b I2C_FIFO_RX16
//
//*****************************************************************************
static inline I2C_RxFIFOLevel
I2C_getRxFIFOStatus(uint32_t base)
{
uint16_t level;
//
// Check the arguments.
//
;
//
// Get the current FIFO status
//
level = (((*((volatile uint16_t *)(base + 0x21U))) & 0x1F00U) >>
8U);
return((I2C_RxFIFOLevel)level);
}
//*****************************************************************************
//
//! Reads I2C Module clock prescaler value.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function reads the I2C prescaler value which configures the I2C module
//! clock by dividing down the SYSCLK. I2C_MODULE_CLK = SYSCLK / (I2CPSC + )
//!
//! \return Returns the I2C prescaler(I2CPSC) cast as an uint16_t.
//
//*****************************************************************************
static inline uint16_t
I2C_getPreScaler(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the contents of the Prescaler register.
//
return((*((volatile uint16_t *)(base + 0xCU))));
}
//*****************************************************************************
//
//! Sets the address that the I2C Controller places on the bus.
//!
//! \param base is the base address of the I2C instance used.
//! \param targetAddr 7-bit or 10-bit target address
//!
//! This function configures the address that the I2C Controller places on the bus
//! when initiating a transaction.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setTargetAddress(uint32_t base, uint16_t targetAddr)
{
//
// Check the arguments.
//
;
;
(*((volatile uint16_t *)(base + 0x7U))) = targetAddr;
}
//*****************************************************************************
//
//! Sets the own address for this I2C module.
//!
//! \param base is the base address of the I2C Target module.
//! \param Addr is the 7-bit or 10-bit address
//!
//! This function writes the specified address.
//!
//! The parameter \e Addr is the value that is compared against the
//! target address sent by an I2C controller.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setOwnAddress(uint32_t base, uint16_t Addr)
{
//
// Check the arguments.
//
;
;
(*((volatile uint16_t *)(base + 0x0U))) = Addr;
}
//*****************************************************************************
//
//! Indicates whether or not the I2C bus is busy.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns an indication of whether or not the I2C bus is busy.
//! This function can be used in a multi-controller environment to determine if the
//! bus is free for another data transfer.
//!
//! \return Returns \b true if the I2C bus is busy; otherwise, returns
//! \b false.
//
//*****************************************************************************
static inline _Bool
I2C_isBusBusy(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint16_t *)(base + 0x2U))) & 0x1000U) == 0x1000U);
}
//*****************************************************************************
//
//! Gets the current I2C module status.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns the status for the I2C module.
//!
//! \return The current module status, enumerated as a bit field of
//! - \b I2C_STS_ARB_LOST - Arbitration-lost
//! - \b I2C_STS_NO_ACK - No-acknowledgment (NACK)
//! - \b I2C_STS_REG_ACCESS_RDY - Register-access-ready (ARDY)
//! - \b I2C_STS_RX_DATA_RDY - Receive-data-ready
//! - \b I2C_STS_TX_DATA_RDY - Transmit-data-ready
//! - \b I2C_STS_STOP_CONDITION - Stop condition detected
//! - \b I2C_STS_BYTE_SENT - Byte transmit complete
//! - \b I2C_STS_ADDR_ZERO - Address of all zeros detected
//! - \b I2C_STS_ADDR_TARGET - Addressed as Target
//! - \b I2C_STS_TX_EMPTY - Transmit shift register empty
//! - \b I2C_STS_RX_FULL - Receive shift register full
//! - \b I2C_STS_BUS_BUSY - Bus busy, wait for STOP or reset
//! - \b I2C_STS_NACK_SENT - NACK was sent
//! - \b I2C_STS_TARGET_DIR- Addressed as Target transmitter
//
//*****************************************************************************
static inline uint16_t
I2C_getStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return contents of the status register
//
return((*((volatile uint16_t *)(base + 0x2U))));
}
//*****************************************************************************
//
//! Clears I2C status flags.
//!
//! \param base is the base address of the I2C instance used.
//! \param stsFlags is a bit mask of the status flags to be cleared.
//!
//! This function clears the specified I2C status flags. The \e stsFlags
//! parameter is the logical OR of the following values:
//! - \b I2C_STS_ARB_LOST
//! - \b I2C_STS_NO_ACK,
//! - \b I2C_STS_REG_ACCESS_RDY
//! - \b I2C_STS_RX_DATA_RDY
//! - \b I2C_STS_STOP_CONDITION
//! - \b I2C_STS_BYTE_SENT
//! - \b I2C_STS_NACK_SENT
//! - \b I2C_STS_TARGET_DIR
//!
//! \note Note that some of the status flags returned by I2C_getStatus() cannot
//! be cleared by this function. Some may only be cleared by hardware or a
//! reset of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_clearStatus(uint32_t base, uint16_t stsFlags)
{
//
// Check the arguments.
//
;
//
// Write to the status registers to clear them.
//
(*((volatile uint16_t *)(base + 0x2U))) = stsFlags;
}
//*****************************************************************************
//
//! Controls the state of the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//! \param config is the command to be issued to the I2C module.
//!
//! This function is used to control the state of the controller and target send and
//! receive operations. The \e config is a logical OR of the following options.
//!
//! One of the following four options:
//! - \b I2C_CONTROLLER_SEND_MODE - Controller-transmitter mode
//! - \b I2C_CONTROLLER_RECEIVE_MODE - Controller-receiver mode
//! - \b I2C_TARGET_SEND_MODE - Target-transmitter mode
//! - \b I2C_TARGET_RECEIVE_MODE - Target-receiver mode
//!
//! Any of the following:
//! - \b I2C_REPEAT_MODE - Sends data until stop bit is set, ignores data count
//! - \b I2C_START_BYTE_MODE - Use start byte mode
//! - \b I2C_FREE_DATA_FORMAT - Use free data format, transfers have no address
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setConfig(uint32_t base, uint16_t config)
{
//
// Check the arguments.
//
;
//
// Write the selected options to the mode register.
//
(*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) &
~(0x400U | 0x200U | 0x80U |
0x10U | 0x8U)) | config;
}
//*****************************************************************************
//
//! Sets the data byte bit count the I2C module.
//!
//! \param base is the base address of the I2C instance used.
//! \param size is the number of bits per data byte.
//!
//! The \e size parameter is a value I2C_BITCOUNT_x where x is the number of
//! bits per data byte. The default and maximum size is 8 bits.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setBitCount(uint32_t base, I2C_BitCount size)
{
//
// Check the arguments.
//
;
//
// Write the selected options to the mode register.
//
(*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~0x7U) |
(uint16_t)size;
}
//*****************************************************************************
//
//! Issues an I2C START condition.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function causes the I2C module to generate a start condition. This
//! function is only valid when the I2C module specified by the \b base
//! parameter is a controller.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_sendStartCondition(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the START condition bit.
//
(*((volatile uint16_t *)(base + 0x9U))) |= 0x2000U;
}
//*****************************************************************************
//
//! Issues an I2C STOP condition.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function causes the I2C module to generate a stop condition. This
//! function is only valid when the I2C module specified by the \b base
//! parameter is a controller.
//!
//! To check on the status of the STOP condition, I2C_getStopConditionStatus()
//! can be used.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_sendStopCondition(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the STOP condition bit.
//
(*((volatile uint16_t *)(base + 0x9U))) |= 0x800U;
}
//*****************************************************************************
//
//! Issues a no-acknowledge (NACK) bit.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function causes the I2C module to generate a NACK bit. This is only
//! applicable when the I2C module is acting as a receiver.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_sendNACK(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the NACK mode bit.
//
(*((volatile uint16_t *)(base + 0x9U))) |= 0x8000U;
}
//*****************************************************************************
//
//! Receives a byte that has been sent to the I2C.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function reads a byte of data from the I2C Data Receive Register.
//!
//! \return Returns the byte received from by the I2C cast as an uint16_t.
//
//*****************************************************************************
static inline uint16_t
I2C_getData(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the contents of the receive register.
//
return((*((volatile uint16_t *)(base + 0x6U))));
}
//*****************************************************************************
//
//! Transmits a byte from the I2C.
//!
//! \param base is the base address of the I2C instance used.
//! \param data is the data to be transmitted from the I2C Controller.
//!
//! This function places the supplied data into I2C Data Transmit Register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_putData(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
//
// Place the data into the transmit register.
//
(*((volatile uint16_t *)(base + 0x8U))) = data;
}
//*****************************************************************************
//
//! Get stop condition status.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function reads and returns the stop condition bit status.
//!
//! \return Returns \b true if the STP bit has been set by the device to
//! generate a stop condition when the internal data counter of the I2C module
//! has reached 0. Returns \b false when the STP bit is zero. This bit is
//! automatically cleared after the stop condition has been generated.
//
//*****************************************************************************
static inline _Bool
I2C_getStopConditionStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Check the stop condition bit and return appropriately.
//
return(((*((volatile uint16_t *)(base + 0x9U))) & 0x800U) != 0U);
}
//*****************************************************************************
//
//! Set number of bytes to be to transfer or receive when repeat mode is off.
//!
//! \param base is the base address of the I2C instance used.
//! \param count is the value to be put in the I2C data count register.
//!
//! This function sets the number of bytes to transfer or receive when repeat
//! mode is off.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setDataCount(uint32_t base, uint16_t count)
{
//
// Check the arguments.
//
;
//
// Write the count value to the appropriate register.
//
(*((volatile uint16_t *)(base + 0x5U))) = count;
}
//*****************************************************************************
//
//! Sets the addressing mode to either 7-bit or 10-bit.
//!
//! \param base is the base address of the I2C instance used.
//! \param mode is the address mode, 7-bit or 10-bit.
//!
//! This function configures the I2C module for either a 7-bit address
//! (default) or a 10-bit address. The \e mode parameter configures the address
//! length to 10 bits when its value is \b I2C_ADDR_MODE_10BITS and 7 bits when
//! \b I2C_ADDR_MODE_7BITS.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setAddressMode(uint32_t base, I2C_AddressMode mode)
{
//
// Check the arguments.
//
;
//
// Write the appropriate value to the address expansion bit.
//
(*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~0x100U) |
(uint16_t)mode;
}
//*****************************************************************************
//
//! Sets I2C emulation mode.
//!
//! \param base is the base address of the I2C instance used.
//! \param mode is the emulation mode.
//!
//! This function sets the behavior of the I2C operation when an emulation
//! suspend occurs. The \e mode parameter can be one of the following:
//!
//! - \b I2C_EMULATION_STOP_SCL_LOW - If SCL is low when the breakpoint occurs,
//! the I2C module stops immediately. If SCL is high, the I2C module waits
//! until SCL becomes low and then stops.
//! - \b I2C_EMULATION_FREE_RUN - I2C operation continues regardless of a
//! the suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setEmulationMode(uint32_t base, I2C_EmulationMode mode)
{
//
// Check the arguments.
//
;
//
// Write the desired emulation mode to the register.
//
(*((volatile uint16_t *)(base + 0x9U))) = ((*((volatile uint16_t *)(base + 0x9U))) & ~0x4000U) |
(uint16_t)mode;
}
//*****************************************************************************
//
//! Enables I2C loopback mode.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function enables loopback mode. This mode is only valid during controller
//! mode and is helpful during device testing as it causes data transmitted out
//! of the data transmit register to be received in data receive register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_enableLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the bit that enables loopback mode.
//
(*((volatile uint16_t *)(base + 0x9U))) |= 0x40U;
}
//*****************************************************************************
//
//! Disables I2C loopback mode.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function disables loopback mode. Loopback mode is disabled by default
//! after reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_disableLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear the bit that enables loopback mode.
//
(*((volatile uint16_t *)(base + 0x9U))) &= ~0x40U;
}
//*****************************************************************************
//
//! Returns the current I2C interrupt source.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns the event that generated an I2C basic (non-FIFO)
//! interrupt. The possible sources are the following:
//! - \b I2C_INTSRC_NONE
//! - \b I2C_INTSRC_ARB_LOST
//! - \b I2C_INTSRC_NO_ACK
//! - \b I2C_INTSRC_REG_ACCESS_RDY
//! - \b I2C_INTSRC_RX_DATA_RDY
//! - \b I2C_INTSRC_TX_DATA_RDY
//! - \b I2C_INTSRC_STOP_CONDITION
//! - \b I2C_INTSRC_ADDR_TARGET
//!
//! Calling this function will result in hardware automatically clearing the
//! current interrupt code and if ready, loading the next pending enabled
//! interrupt. It will also clear the corresponding interrupt flag if the
//! source is \b I2C_INTSRC_ARB_LOST, \b I2C_INTSRC_NO_ACK, or
//! \b I2C_INTSRC_STOP_CONDITION.
//!
//! \note Note that this function differs from I2C_getInterruptStatus() in that
//! it returns a single interrupt source. I2C_getInterruptSource() will return
//! the status of all interrupt flags possible, including the flags that aren't
//! necessarily enabled to generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline I2C_InterruptSource
I2C_getInterruptSource(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the interrupt source value
//
return((I2C_InterruptSource)((*((volatile uint16_t *)(base + 0xAU))) &
0x7U));
}
//*****************************************************************************
//
//! Sets the compatibility mode to support I2C Extended Mode.
//!
//! \param base is the base address of the I2C instance used.
//! \param mode is the compatibility modes.
//!
//! This function configures the I2C module for either a Forward or Backward
//! compatibilty. The \e mode parameter configures the compatibility
//! to Forward when its value is \b I2C_EADDR_MODE_FWD and Backward when
//! \b I2C_EADDR_MODE_BC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
I2C_setExtendedMode(uint32_t base, I2C_ExtendedMode mode)
{
//
// Check the arguments.
//
;
//
// Write the appropriate value to the compatibility mode register.
//
(*((volatile uint16_t *)(base + 0xBU))) =
((*((volatile uint16_t *)(base + 0xBU))) & ~(0x1U | 0x2U)) |
(uint16_t)mode;
}
//*****************************************************************************
//
//! Initializes the I2C Controller.
//!
//! \param base is the base address of the I2C instance used.
//! \param sysclkHz is the rate of the clock supplied to the I2C module
//! (SYSCLK) in Hz.
//! \param bitRate is the rate of the controller clock signal, SCL.
//! \param dutyCycle is duty cycle of the SCL signal.
//!
//! This function initializes operation of the I2C Controller by configuring the
//! bus speed for the controller. Note that the I2C module \b must be put into
//! reset before calling this function. You can do this with the function
//! I2C_disableModule().
//!
//! A programmable prescaler in the I2C module divides down the input clock
//! (rate specified by \e sysclkHz) to produce the module clock (calculated to
//! be around 10 MHz in this function). That clock is then divided down further
//! to configure the SCL signal to run at the rate specified by \e bitRate. The
//! \e dutyCycle parameter determines the percentage of time high and time low
//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and
//! \b I2C_DUTYCYCLE_50 for 50%.
//!
//! The peripheral clock is the system clock. This value is returned by
//! SysCtl_getClock(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtl_getClock()).
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate,
I2C_DutyCycle dutyCycle);
//*****************************************************************************
//
//! Enables I2C interrupt sources.
//!
//! \param base is the base address of the I2C instance used.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated I2C Controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//!
//! - \b I2C_INT_ARB_LOST - Arbitration-lost interrupt
//! - \b I2C_INT_NO_ACK - No-acknowledgment (NACK) interrupt
//! - \b I2C_INT_REG_ACCESS_RDY - Register-access-ready interrupt
//! - \b I2C_INT_RX_DATA_RDY - Receive-data-ready interrupt
//! - \b I2C_INT_TX_DATA_RDY - Transmit-data-ready interrupt
//! - \b I2C_INT_STOP_CONDITION - Stop condition detected
//! - \b I2C_INT_ADDR_TARGET - Addressed as target interrupt
//! - \b I2C_INT_RXFF - RX FIFO level interrupt
//! - \b I2C_INT_TXFF - TX FIFO level interrupt
//!
//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO
//! interrupt vector. All others are associated with the I2C basic interrupt.
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_enableInterrupt(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Disables I2C interrupt sources.
//!
//! \param base is the base address of the I2C instance used.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated I2C Target interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to I2C_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_disableInterrupt(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Gets the current I2C interrupt status.
//!
//! \param base is the base address of the I2C instance used.
//!
//! This function returns the interrupt status for the I2C module.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! - \b I2C_INT_ARB_LOST
//! - \b I2C_INT_NO_ACK
//! - \b I2C_INT_REG_ACCESS_RDY
//! - \b I2C_INT_RX_DATA_RDY
//! - \b I2C_INT_TX_DATA_RDY
//! - \b I2C_INT_STOP_CONDITION
//! - \b I2C_INT_ADDR_TARGET
//! - \b I2C_INT_RXFF
//! - \b I2C_INT_TXFF
//!
//! \note This function will only return the status flags associated with
//! interrupts. However, a flag may be set even if its corresponding interrupt
//! is disabled.
//
//*****************************************************************************
extern uint32_t
I2C_getInterruptStatus(uint32_t base);
//*****************************************************************************
//
//! Clears I2C interrupt sources.
//!
//! \param base is the base address of the I2C instance used.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified I2C interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to I2C_enableInterrupt().
//!
//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO
//! interrupt vector. All others are associated with the I2C basic interrupt.
//!
//! \note Also note that some of the status flags returned by
//! I2C_getInterruptStatus() cannot be cleared by this function. Some may only
//! be cleared by hardware or a reset of the I2C module.
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Configures I2C Module Clock Frequency
//!
//! \param base is the base address of the I2C instance used.
//! \param sysclkHz is the rate of the clock supplied to the I2C module
//! (SYSCLK) in Hz.
//!
//! This function configures I2C module clock frequency by initializing
//! prescale register based on SYSCLK frequency.
//! Note that the I2C module \b must be put into
//! reset before calling this function. You can do this with the function
//! I2C_disableModule().
//!
//! \return None.
//
//*****************************************************************************
extern void
I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: lin.h
//
// TITLE: C28x LIN driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup lin_api LIN
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_lin.h
//
// TITLE: Definitions for the LIN registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the LIN register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIGCR0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIGCR1 register
//
//*************************************************************************************************
// mode.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIGCR2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCISETINT register
//
//*************************************************************************************************
// mode)
// (LIN only)
// Interrupt (LIN only)
// (LIN only)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICLEARINT register
//
//*************************************************************************************************
// compatible mode
// Interrupt (LIN only)
// Interrupt (LIN only)
// only)
// Interrupt (LIN only)
// only)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCISETINTLVL register
//
//*************************************************************************************************
// compatible mode)
// Interrupt Level (LIN only)
// Interrupt Level
// only)
// (LIN only)
// Interrupt Level
// (LIN only)
// (LIN only)
// only)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICLEARINTLVL register
//
//*************************************************************************************************
// (SCI compatible mode)
// only)
// Interrupt Level (LIN only)
// (LIN only)
// Level (LIN only)
// (LIN only)
// Level (LIN only)
// only)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIINTVECT0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIINTVECT1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFORMAT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the BRSR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIED register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCITD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIPIO0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIPIO2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LINCOMP register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LINRD0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LINRD1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LINMASK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LINID register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LINTD0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LINTD1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MBRSR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the IODFTCTRL register
//
//*************************************************************************************************
// compatibility mode)
// mode)
// mode)
// mode)
//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_GLB_INT_EN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_GLB_INT_FLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LIN_GLB_INT_CLR register
//
//*************************************************************************************************
//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************
//
// The IO DFT Enable Key
//
//
// LIN Wakeup Signal Key
//
//
// LIN Parity ID Masks
//
//*****************************************************************************
//
// Definitions for the intFlags parameter of LIN_enableInterrupt(),
// LIN_disableInterrupt(), LIN_clearInterruptStatus(),
// LIN_setInterruptLevel0() and LIN_setInterruptLevel1().
//
//*****************************************************************************
//*****************************************************************************
//
// Definitions for the return value of LIN_getInterruptStatus().
//
//*****************************************************************************
//!< signal
//!< signals
//!< Method Select
//!< Error
//*****************************************************************************
//
// Definitions for the return value of LIN_getInterruptLine0Offset() and
// LIN_getInterruptLine1Offset().
//
//*****************************************************************************
//*****************************************************************************
//
// Definitions for the LIN errors parameter of LIN_enableModuleErrors() and
// LIN_disableModuleErrors().
//
//*****************************************************************************
//*****************************************************************************
//
// Definitions for the SCI errors parameter of LIN_enableSCIModuleErrors() and
// LIN_disableSCIModuleErrors().
//
//*****************************************************************************
//*****************************************************************************
//
// Definitions for the intFlags parameter of LIN_enableSCIInterrupt(),
// LIN_disableSCIInterrupt(), LIN_clearSCIInterruptStatus(),
// LIN_setSCIInterruptLevel0() and LIN_setSCIInterruptLevel1().
//
//*****************************************************************************
//*****************************************************************************
//
//! The following are defines for the \e type parameter of the
//! LIN_enableExtLoopback() function.
//
//*****************************************************************************
typedef enum
{
LIN_LOOPBACK_DIGITAL = 0U, //!< Digital Loopback Mode
LIN_LOOPBACK_ANALOG = 2U //!< Analog Loopback Mode
} LIN_LoopbackType;
//*****************************************************************************
//
//! The following are defines for the \e path parameter of the
//! LIN_enableExtLoopback() function.
//
//*****************************************************************************
typedef enum
{
LIN_ANALOG_LOOP_NONE = 0U, //!< Default path for digital loopback mode
LIN_ANALOG_LOOP_TX = 0U, //!< Analog loopback through transmit pin
LIN_ANALOG_LOOP_RX = 1U //!< Analog loopback through receive pin
} LIN_AnalogLoopback;
//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the
//! LIN_setCommMode() function.
//
//*****************************************************************************
typedef enum
{
//! Use the length indicated in the LENGTH field of the SCIFORMAT register
LIN_COMM_LIN_USELENGTHVAL = 0x0000U,
//! Use ID4 and ID5 to convey the length
LIN_COMM_LIN_ID4ID5LENCTL = 0x0001U
} LIN_CommMode;
//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the
//! LIN_setSCICommMode() function.
//
//*****************************************************************************
typedef enum
{
//! Idle-line mode is used
LIN_COMM_SCI_IDLELINE = 0x0000U,
//! Address bit mode is used
LIN_COMM_SCI_ADDRBIT = 0x0001U
} LIN_SCICommMode;
//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the LIN_setLINMode()
//! function.
//
//*****************************************************************************
typedef enum
{
LIN_MODE_LIN_RESPONDER = 0x0000U, //!< The node is in responder mode
LIN_MODE_LIN_COMMANDER = 0x0020U //!< The node is in commander mode
} LIN_LINMode;
//*****************************************************************************
//
//! The following are defines for the \e line parameter of the
//! LIN_enableGlobalInterrupt(), LIN_disableGlobalInterrupt(),
//! LIN_clearGlobalInterruptStatus(), and LIN_getGlobalInterruptStatus()
//! functions.
//
//*****************************************************************************
typedef enum
{
LIN_INTERRUPT_LINE0 = 0x0U, //!< Interrupt line 0
LIN_INTERRUPT_LINE1 = 0x1U //!< Interrupt line 1
} LIN_InterruptLine;
//*****************************************************************************
//
//! The following are defines for the \e type parameter of the
//! LIN_setMessageFiltering() function.
//
//*****************************************************************************
typedef enum
{
LIN_MSG_FILTER_IDBYTE = 0x0U, //!< LIN Message ID Byte Filtering
LIN_MSG_FILTER_IDRESPONDER = 0x1U //!< Responder Task ID Byte Filtering
} LIN_MessageFilter;
//*****************************************************************************
//
//! The following are defines for the \e type parameter of the
//! LIN_setChecksumType() function.
//
//*****************************************************************************
typedef enum
{
LIN_CHECKSUM_CLASSIC = 0x0U, //!< Checksum Classic
LIN_CHECKSUM_ENHANCED = 0x1U //!< Checksum Enhanced
} LIN_ChecksumType;
//*****************************************************************************
//
//! The following are defines for the \e mode parameter of the
//! LIN_setDebugSuspendMode() function.
//
//*****************************************************************************
typedef enum
{
LIN_DEBUG_FROZEN = 0x0U, //!< Freeze module during debug
LIN_DEBUG_COMPLETE = 0x1U //!< Complete Tx/Rx before Freezing
} LIN_DebugMode;
//*****************************************************************************
//
//! The following are defines for the \e mask parameter of the
//! LIN_setPinSampleMask() function.
//
//*****************************************************************************
typedef enum
{
//! No Pin Mask
LIN_PINMASK_NONE = 0x0U,
//! Invert Tx Pin value at T-bit center
LIN_PINMASK_CENTER = 0x1U,
//! Invert Tx Pin value at T-bit center + SCLK
LIN_PINMASK_CENTER_SCLK = 0x2U,
//! Invert Tx Pin value at T-bit center + 2 SCLK
LIN_PINMASK_CENTER_2SCLK = 0x3U
} LIN_PinSampleMask;
//*****************************************************************************
//
//! The following are defines for the \e parity parameter of the
//! LIN_enableSCIParity() function.
//
//*****************************************************************************
typedef enum
{
LIN_SCI_PAR_ODD = 0x0U, //!< Odd parity
LIN_SCI_PAR_EVEN = 0x1U //!< Even parity
} LIN_SCIParityType;
//*****************************************************************************
//
//! The following are defines for the \e number parameter of the
//! LIN_setSCIStopBits() function.
//
//*****************************************************************************
typedef enum
{
LIN_SCI_STOP_ONE = 0x0U, //!< Use One Stop bit
LIN_SCI_STOP_TWO = 0x1U //!< Use Two Stop bits
} LIN_SCIStopBits;
//*****************************************************************************
//
//! The following are defines for the \e pin parameter of the
//! LIN_getPinStatus() function.
//
//*****************************************************************************
typedef enum
{
LIN_PINTYPE_TX = 0x4U, //!< Transmit Pin
LIN_PINTYPE_RX = 0x2U //!< Receive Pin
} LIN_PinType;
//*****************************************************************************
//
// Prototypes for the LIN mode APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//!
//! Checks a LIN base address.
//!
//! \param base is the base address of the LIN controller.
//!
//! This function determines if a LIN controller base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the LIN mode
//!
//! \param base is the LIN module base address
//! \param mode is the desired mode (responder or commander)
//!
//! In LIN mode only, this function sets the mode of the LIN mode to either
//! responder or commander. The \e mode parameter should be passed a value of
//! \b LIN_MODE_LIN_RESPONDER or \b LIN_MODE_LIN_COMMANDER to configure the mode of
//! the LIN module specified by \e base.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setLINMode(uint32_t base, LIN_LINMode mode)
{
//
// Check the arguments.
//
;
//
// Write the LIN mode to the appropriate register.
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) &
~0x20U) | (uint16_t)mode;
__edis();
}
//*****************************************************************************
//
//! Set Maximum Baud Rate Prescaler
//!
//! \param base is the LIN module base address
//! \param clock is the device system clock (Hz)
//!
//! In LIN mode only, this function is used to set the maximum baud rate
//! prescaler used during synchronization phase of a responder module if the
//! ADAPT bit is set. The maximum baud rate prescaler is used by the wakeup
//! and idle timer counters for a constant 4 second expiration time relative
//! to a 20kHz rate.
//!
//! \note Use LIN_enableAutomaticBaudrate() to set the ADAPT bit and enable
//! automatic bit rate mod detection.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setMaximumBaudRate(uint32_t base, uint32_t systemClock)
{
//
// Check the arguments.
//
;
//
// Calculate maximum baud rate prescaler
//
(*((volatile uint16_t *)(base + 0x7CU))) = (uint16_t)(systemClock / 20000U);
}
//*****************************************************************************
//
//! Set Message filtering Type
//!
//! \param base is the LIN module base address
//! \param type is the mask filtering comparison type
//!
//! In LIN mode only, this function sets the message filtering type. The \e
//! type parameter can be one of the following values:
//! - \b LIN_MSG_FILTER_IDBYTE - Filtering uses LIN message ID Byte
//! - \b LIN_MSG_FILTER_IDRESPONDER - Filtering uses the responder Task ID Byte
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setMessageFiltering(uint32_t base, LIN_MessageFilter type)
{
//
// Check the arguments.
//
;
//
// Sets the message filtering type
//
if(type == LIN_MSG_FILTER_IDBYTE)
{
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x1000U;
}
else
{
(*((volatile uint16_t *)(base + 0x4U))) |= 0x1000U;
}
}
//*****************************************************************************
//
//! Enable Parity mode.
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the parity check.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableParity(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the parity mode
//
(*((volatile uint16_t *)(base + 0x4U))) |= 0x4U;
}
//*****************************************************************************
//
//! Disable Parity mode.
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function disables the parity check.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableParity(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the parity mode
//
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x4U);
}
//*****************************************************************************
//
//! Generate Parity Identifier
//! \param identifier is the LIN header ID byte
//!
//! In LIN mode only, this function generates the identifier parity bits and
//! appends them to the identifier.
//!
//! \note An ID must be generated with parity before header generation in
//! LIN commander mode when parity is enabled using the function
//! LIN_enableParity().
//!
//! \return Returns the identifier appended with parity bits.
//
//*****************************************************************************
static inline uint16_t
LIN_generateParityID(uint16_t identifier)
{
uint16_t p0, p1, parityIdentifier;
//
// Calculate parity bits and generate updated identifier
//
p0 = ((identifier & (0x1U)) ^ ((identifier & (0x2U)) >> 1U) ^
((identifier & (0x4U)) >> 2U) ^ ((identifier & (0x10U)) >> 4U));
p1 = !(((identifier & (0x2U)) >> 1U) ^ ((identifier & (0x8U)) >> 3U) ^
((identifier & (0x10U)) >> 4U) ^ ((identifier & (0x20U)) >> 5U));
parityIdentifier = identifier | ((p0 << 6U) | (p1 << 7U));
return(parityIdentifier);
}
//*****************************************************************************
//
//! Set ID Byte
//!
//! \param base is the LIN module base address
//! \param identifier is the LIN header ID byte
//!
//! In LIN mode only, this function sets the message ID byte. In commander mode,
//! writing to this ID initiates a header transmission. In responder task, this
//! ID is used for message filtering when HGENCTRL is 0.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setIDByte(uint32_t base, uint16_t identifier)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x70U))) = ((*((volatile uint16_t *)(base + 0x70U))) & ~(0xFFU)) |
(identifier & 0xFFU);
}
//*****************************************************************************
//
//! Set ID-ResponderTask
//!
//! \param base is the LIN module base address
//! \param identifier is the Received ID comparison ID
//!
//! In LIN mode only, this function sets the identifier to which the received
//! ID of an incoming Header will be compared in order to decide whether a RX
//! response, a TX response, or no action is required.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setIDResponderTask(uint32_t base, uint16_t identifier)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x70U))) = (((*((volatile uint16_t *)(base + 0x70U))) &
~(0xFF00U)) |
((identifier & 0xFFU) <<
8U));
}
//*****************************************************************************
//
//! Send LIN wakeup signal
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function sends the LIN wakeup signal to terminate
//! the sleep mode of any LIN node connected to the bus.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_sendWakeupSignal(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set key in Byte 0 (MSB) of transmit buffer 0 register
//
__byte((int16_t *)(base + 0x74U + 0x3U),0) = (uint16_t)(0xF0U);
//
// Transmit TDO for wakeup
//
(*((volatile uint16_t *)(base + 0x8U))) |= 0x100U;
}
//*****************************************************************************
//
//! Enter LIN Sleep Mode.
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function puts the LIN module into a low-power, sleep
//! mode. This can also be called to forcefully enter sleep when there is no
//! activity on the bus.
//!
//! \note If this function is called while the receiver is actively receiving
//! data and the wakeup interrupt is disabled, then the module will delay
//! sleep mode from being entered until completion of reception.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enterSleep(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x8U))) |= 0x1U;
}
//*****************************************************************************
//
//! Send Checksum Byte
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the transmitter with extended
//! frames to send a checkbyte.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_sendChecksum(uint32_t base)
{
__byte_peripheral_32((uint32_t *)(base + 0x8U)) |= 0x10000U;
}
//*****************************************************************************
//
//! Trigger Checksum Compare
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the receiver for extended frames
//! to trigger a checksum compare.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_triggerChecksumCompare(uint32_t base)
{
//
// Check the arguments.
//
;
__byte_peripheral_32((uint32_t *)(base + 0x8U)) |= 0x20000U;
}
//*****************************************************************************
//
//! Check Tx buffer ready flag
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function checks to see if the Tx ready flag is set
//! indicating that the Tx buffer(s) is/are ready to get another character.
//!
//! \return Returns \b true if the TX ready flag is set, else returns \b false
//
//*****************************************************************************
static inline _Bool
LIN_isTxReady(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read Tx Buffer flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x100U) ==
0x100U);
}
//*****************************************************************************
//
//! Set LIN Frame Length
//!
//! \param base is the LIN module base address
//! \param length is the number of bytes.
//!
//! In LIN mode only, this function sets the number of bytes in the response
//! field.
//!
//! The \e length parameter must be in a range between 1 and 8.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setFrameLength(uint32_t base, uint16_t length)
{
//
// Check the arguments.
//
;
;
//
// Clear and set frame length value
//
__byte_peripheral_32((uint32_t *)(base + 0x28U)) &= ~(0x70000U);
__byte_peripheral_32((uint32_t *)(base + 0x28U)) |= ((((uint32_t)length - (uint32_t)1U) <<
16U));
}
//*****************************************************************************
//
//! Set LIN communication mode
//!
//! \param base is the LIN module base address
//! \param mode is the selected communication mode
//!
//! In LIN mode only, this function is used to choose how the length of data is
//! conveyed. This choice relates to the version of LIN being used. The \e mode
//! parameter can have one of two values:
//! - \b LIN_COMM_LIN_USELENGTHVAL will use the length set with the
//! LIN_setFrameLength() function.
//! - \b LIN_COMM_LIN_ID4ID5LENCTL will use ID4 and ID5 for length control.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setCommMode(uint32_t base, LIN_CommMode mode)
{
//
// Check the arguments.
//
;
//
// Write communication mode selection to the appropriate bit.
//
(*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) &
~0x1U) | (uint16_t)mode;
}
//*****************************************************************************
//
//! Sets the transmit ID mask
//!
//! \param base is the LIN module base address
//! \param mask is the mask value to be set
//!
//! In LIN mode only, this function sets the mask used for filtering an
//! incoming ID message to determine if the TX ID flag should be set.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setTxMask(uint32_t base, uint16_t mask)
{
//
// Check the arguments.
//
;
//
// Clear previous mask value and set new mask
//
(*((volatile uint16_t *)(base + 0x6CU))) &= ~(0xFFU);
(*((volatile uint16_t *)(base + 0x6CU))) |= (mask & 0xFFU);
}
//*****************************************************************************
//
//! Sets the receive ID mask
//!
//! \param base is the LIN module base address
//! \param mask is the mask value to be set
//!
//! In LIN mode only, this function sets the mask used for filtering an
//! incoming ID message to determine if the ID RX flag should be set.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setRxMask(uint32_t base, uint16_t mask)
{
//
// Check the arguments.
//
;
//
// Clear previous mask value and set new mask
//
__byte_peripheral_32((uint32_t *)(base + 0x6CU)) &= ~(0xFF0000U);
__byte_peripheral_32((uint32_t *)(base + 0x6CU)) |= ((uint32_t)mask << 16U) &
0xFF0000U;
}
//*****************************************************************************
//
//! Gets the transmit ID mask
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function gets the mask used for filtering an
//! incoming ID message to determine if the TX ID flag should be set.
//!
//! \return Returns the Transmit ID Mask.
//
//*****************************************************************************
static inline uint16_t
LIN_getTxMask(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint16_t *)(base + 0x6CU))) & 0xFFU);
}
//*****************************************************************************
//
//! Gets the receive ID mask
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function gets the mask used for filtering an
//! incoming ID message to determine if the ID RX flag should be set.
//!
//! \return Returns the Receive ID Mask.
//
//*****************************************************************************
static inline uint16_t
LIN_getRxMask(uint32_t base)
{
//
// Check the arguments.
//
;
return((uint16_t)((__byte_peripheral_32((uint32_t *)(base + 0x6CU)) & 0xFF0000U) >>
16U));
}
//*****************************************************************************
//
//! Check if Rx data is ready
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, checks to see if the Rx ready bit is set indicating that
//! a valid message frame has been received.
//!
//! \return Returns \b true if the Rx ready flag is set, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isRxReady(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Ready Rx ready flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x200U) ==
0x200U);
}
//*****************************************************************************
//
//! Get last received identifier
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function gets the last received identifier.
//!
//! \return Returns the Received Identifier.
//
//*****************************************************************************
static inline uint16_t
LIN_getRxIdentifier(uint32_t base)
{
//
// Check the arguments.
//
;
return((uint16_t)((__byte_peripheral_32((uint32_t *)(base + 0x70U)) & 0xFF0000U) >>
16U));
}
//*****************************************************************************
//
//! Checks for Tx ID Match Received
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function checks if an ID is received with a TX match
//! and no ID-parity error.
//!
//! \return Returns \b true if a valid ID is matched, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isTxMatch(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read Tx ID flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x2000U) ==
0x2000U);
}
//*****************************************************************************
//
//! Checks for Rx ID Match Received
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function checks if an ID is received with a RX match
//! and no ID-parity error.
//!
//! \return Returns \b true if a valid ID is matched, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isRxMatch(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read Rx ID flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x4000U) ==
0x4000U);
}
//*****************************************************************************
//
//! Enable interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! In LIN mode only, this function enables the interrupts for the specified
//! interrupt sources.
//!
//! The \e intFlags parameter can be set to the following value to set
//! all the flag bits:
//! - \b LIN_INT_ALL - All Interrupts
//!
//! To set individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_INT_WAKEUP - Wakeup
//! - \b LIN_INT_TO - Time out
//! - \b LIN_INT_TOAWUS - Time out after wakeup signal
//! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//! - \b LIN_INT_TX - Transmit buffer ready
//! - \b LIN_INT_RX - Receive buffer ready
//! - \b LIN_INT_ID - Received matching identifier
//! - \b LIN_INT_PE - Parity error
//! - \b LIN_INT_OE - Overrun error
//! - \b LIN_INT_FE - Framing error
//! - \b LIN_INT_NRE - No response error
//! - \b LIN_INT_ISFE - Inconsistent sync field error
//! - \b LIN_INT_CE - Checksum error
//! - \b LIN_INT_PBE - Physical bus error
//! - \b LIN_INT_BE - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
__byte_peripheral_32((uint32_t *)(base + 0xCU)) |= intFlags;
}
//*****************************************************************************
//
//! Disable interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! In LIN mode only, this function disables the interrupts for the specified
//! interrupt sources.
//!
//! The \e intFlags parameter can be set to the following value to disable
//! all the flag bits:
//! - \b LIN_INT_ALL - All Interrupts
//!
//! To disable individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_INT_WAKEUP - Wakeup
//! - \b LIN_INT_TO - Time out
//! - \b LIN_INT_TOAWUS - Time out after wakeup signal
//! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//! - \b LIN_INT_TX - Transmit buffer ready
//! - \b LIN_INT_RX - Receive buffer ready
//! - \b LIN_INT_ID - Received matching identifier
//! - \b LIN_INT_PE - Parity error
//! - \b LIN_INT_OE - Overrun error
//! - \b LIN_INT_FE - Framing error
//! - \b LIN_INT_NRE - No response error
//! - \b LIN_INT_ISFE - Inconsistent sync field error
//! - \b LIN_INT_CE - Checksum error
//! - \b LIN_INT_PBE - Physical bus error
//! - \b LIN_INT_BE - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
__byte_peripheral_32((uint32_t *)(base + 0x10U)) = intFlags;
}
//*****************************************************************************
//
//! Clear interrupt status
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be cleared.
//!
//! In LIN mode only, this function clears the specified status flags.
//!
//! The \e intFlags parameter can be set to the following value to clear
//! all the flag bits:
//! - \b LIN_INT_ALL - All Interrupts
//!
//! To clear individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_INT_WAKEUP - Wakeup
//! - \b LIN_INT_TO - Time out
//! - \b LIN_INT_TOAWUS - Time out after wakeup signal
//! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//! - \b LIN_INT_TX - Transmit buffer ready
//! - \b LIN_INT_RX - Receive buffer ready
//! - \b LIN_INT_ID - Received matching identifier
//! - \b LIN_INT_PE - Parity error
//! - \b LIN_INT_OE - Overrun error
//! - \b LIN_INT_FE - Framing error
//! - \b LIN_INT_NRE - No response error
//! - \b LIN_INT_ISFE - Inconsistent sync field error
//! - \b LIN_INT_CE - Checksum error
//! - \b LIN_INT_PBE - Physical bus error
//! - \b LIN_INT_BE - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_clearInterruptStatus(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
//
// Clear the status flags
//
__byte_peripheral_32((uint32_t *)(base + 0x1CU)) = intFlags;
}
//*****************************************************************************
//
//! Set interrupt level to 0
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In LIN mode only, this function sets the specified interrupt sources to
//! level 0.
//!
//! The \e intFlags parameter can be set to the following value to set
//! all the flag bits:
//! - \b LIN_INT_ALL - All Interrupts
//!
//! To set individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_INT_WAKEUP - Wakeup
//! - \b LIN_INT_TO - Time out
//! - \b LIN_INT_TOAWUS - Time out after wakeup signal
//! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//! - \b LIN_INT_TX - Transmit buffer ready
//! - \b LIN_INT_RX - Receive buffer ready
//! - \b LIN_INT_ID - Received matching identifier
//! - \b LIN_INT_PE - Parity error
//! - \b LIN_INT_OE - Overrun error
//! - \b LIN_INT_FE - Framing error
//! - \b LIN_INT_NRE - No response error
//! - \b LIN_INT_ISFE - Inconsistent sync field error
//! - \b LIN_INT_CE - Checksum error
//! - \b LIN_INT_PBE - Physical bus error
//! - \b LIN_INT_BE - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setInterruptLevel0(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
//
// Clear interrupt levels to 0
//
__byte_peripheral_32((uint32_t *)(base + 0x18U)) = intFlags;
}
//*****************************************************************************
//
//! Set interrupt level to 1
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In LIN mode only, this function sets the specified interrupt sources to
//! level 1.
//!
//! The \e intFlags parameter can be set to the following value to set
//! all the flag bits:
//! - \b LIN_INT_ALL - All Interrupts
//!
//! To set individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_INT_WAKEUP - Wakeup
//! - \b LIN_INT_TO - Time out
//! - \b LIN_INT_TOAWUS - Time out after wakeup signal
//! - \b LIN_INT_TOA3WUS - Time out after 3 wakeup signals
//! - \b LIN_INT_TX - Transmit buffer ready
//! - \b LIN_INT_RX - Receive buffer ready
//! - \b LIN_INT_ID - Received matching identifier
//! - \b LIN_INT_PE - Parity error
//! - \b LIN_INT_OE - Overrun error
//! - \b LIN_INT_FE - Framing error
//! - \b LIN_INT_NRE - No response error
//! - \b LIN_INT_ISFE - Inconsistent sync field error
//! - \b LIN_INT_CE - Checksum error
//! - \b LIN_INT_PBE - Physical bus error
//! - \b LIN_INT_BE - Bit error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setInterruptLevel1(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
//
// Set interrupt levels to 1
//
__byte_peripheral_32((uint32_t *)(base + 0x14U)) |= intFlags;
}
//*****************************************************************************
//
//! Enable Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be enabled
//!
//! In LIN mode only, this function enables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_ALL_ERRORS can be used to enable all of them:
//! - \b LIN_BIT_ERROR - Simulates a bit error
//! - \b LIN_BUS_ERROR - Simulates a physical bus error
//! - \b LIN_CHECKSUM_ERROR - Simulates a checksum error
//! - \b LIN_ISF_ERROR - Simulates an inconsistent synch field error
//!
//! \note To disable these errors, use the LIN_disableModuleErrors() function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableModuleErrors(uint32_t base, uint32_t errors)
{
//
// Check the arguments.
//
;
__eallow();
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
//
// Enable write access
//
(*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) <<
8U);
//
// Enable specified error bits
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) |= errors;
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) <<
8U);
__edis();
}
//*****************************************************************************
//
//! Disable Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be disabled
//!
//! In LIN mode only, this function disables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_ALL_ERRORS can be used to disable all of them:
//! - \b LIN_BIT_ERROR - Simulates a bit error
//! - \b LIN_BUS_ERROR - Simulates a physical bus error
//! - \b LIN_CHECKSUM_ERROR - Simulates a checksum error
//! - \b LIN_ISF_ERROR - Simulates an inconsistent synch field error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableModuleErrors(uint32_t base, uint32_t errors)
{
//
// Check the arguments.
//
;
__eallow();
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
//
// Enable write access
//
(*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) <<
8U);
//
// Disable specified error bits
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(errors);
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) <<
8U);
__edis();
}
//*****************************************************************************
//
//! Enable Automatic Baudrate Adjustment
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function enables the automatic baudrate adjustment
//! mode during the detection of the Synch Field.
//!
//! \note The baudrate selection register will be updated automatically by a
//! responder node if this mode is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableAutomaticBaudrate(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) |= 0x200U;
__edis();
}
//*****************************************************************************
//
//! Disable Automatic Baudrate Adjustment
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function disables the automatic baudrate adjustment
//! mode during the detection of the Synch Field. This results in a fixed
//! baud rate.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableAutomaticBaudrate(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x200U;
__edis();
}
//*****************************************************************************
//
//! Stops LIN Extended Frame Communication
//!
//! \param base is the LIN module base address
//!
//! In LIN mode only, this function stops the extended frame communication.
//! Once stopped, the bit is automatically cleared.
//!
//! \note This function can only be called during extended frame communication.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_stopExtendedFrame(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set stop bit
//
(*((volatile uint16_t *)(base + 0x4U))) |= 0x2000U;
}
//*****************************************************************************
//
//! Set Checksum Type
//!
//! \param base is the LIN module base address
//! \param type is the checksum type
//!
//! In LIN mode only, this function sets the checksum type. The \e type
//! parameter can be one of the following two values:
//! - \b LIN_CHECKSUM_CLASSIC - Checksum Classic
//! - \b LIN_CHECKSUM_ENHANCED - Checksum Enhanced
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setChecksumType(uint32_t base, LIN_ChecksumType type)
{
//
// Check the arguments.
//
;
if(type == LIN_CHECKSUM_ENHANCED)
{
(*((volatile uint16_t *)(base + 0x4U))) |= 0x800U;
}
else
{
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x800U);
}
}
//*****************************************************************************
//
//! Set Sync Break Extend and Delimiter
//!
//! \param base is the LIN module base address
//! \param syncBreak is the sync break extend value
//! \param delimiter is the sync delimiter value
//!
//! In LIN mode only, this function sets the 3-bit sync break extend value
//! and the 2-bit sync delimiter compare value.
//!
//! The \e break parameter can be a value between 0 to 7. Details:
//! - \b 0 - Sync Break has no additional T-bit
//! - \b 1 - Sync Break has 1 additional T-bit
//! - \b ...
//! - \b 7 - Sync Break has 7 additional T-bits
//!
//! The \e delimiter parameter can be a value between 1 to 4. Details:
//! - \b 1 - Delimiter has 1 T-bit
//! - \b 2 - Delimiter has 2 T-bits
//! - \b 3 - Delimiter has 3 T-bits
//! - \b 4 - Delimiter has 4 T-bits
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSyncFields(uint32_t base, uint16_t syncBreak, uint16_t delimiter)
{
//
// Check the arguments.
//
;
;
;
//
// Clear sync values and set new values
//
(*((volatile uint16_t *)(base + 0x60U))) &= ~((uint16_t)0x7U |
(uint16_t)0x300U);
(*((volatile uint16_t *)(base + 0x60U))) |= (syncBreak | ((delimiter - 1U) <<
8U));
}
//*****************************************************************************
//
// Prototypes for the SCI mode APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enable SCI Mode
//!
//! \param base is the LIN module base address
//!
//! This function enables the LIN peripheral to function as a SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable SCI communications mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x40U;
(*((volatile uint16_t *)(base + 0x4U))) |= 0x20U |
0x2U;
__edis();
}
//*****************************************************************************
//
//! Disable SCI Mode
//!
//! \param base is the LIN module base address
//!
//! This function disables the SCI mode of the LIN peripheral.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable SCI communications mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x20U |
0x2U);
(*((volatile uint16_t *)(base + 0x4U))) |= 0x40U;
__edis();
}
//*****************************************************************************
//
//! Set SCI communication mode
//!
//! \param base is the LIN module base address
//! \param mode is the selected communication mode
//!
//! In SCI mode only, this function is used to select between idle-line mode
//! and address-bit mode. The \e mode parameter can have one of the following
//! values:
//! - \b LIN_COMM_SCI_IDLELINE - Idle-line mode.
//! - \b LIN_COMM_SCI_ADDRBIT - Address-bit mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCICommMode(uint32_t base, LIN_SCICommMode mode)
{
//
// Check the arguments.
//
;
;
//
// Write communication mode selection to the appropriate bit.
//
(*((volatile uint16_t *)(base + 0x4U))) = ((*((volatile uint16_t *)(base + 0x4U))) &
~0x1U) | (uint16_t)mode;
}
//*****************************************************************************
//
//! Enable SCI Parity mode.
//!
//! \param base is the LIN module base address
//! \param parity is the SCI parity type
//!
//! In SCI mode only, this function enables the parity check and sets the
//! parity type. The \e parity parameter can one of the following values:
//! - \b LIN_SCI_PAR_ODD - Sets Odd parity
//! - \b LIN_SCI_PAR_EVEN - Sets Even parity
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIParity(uint32_t base, LIN_SCIParityType parity)
{
//
// Check the arguments.
//
;
;
//
// Enable the parity mode
//
(*((volatile uint16_t *)(base + 0x4U))) |= 0x4U;
//
// Set the parity type
//
if(parity == LIN_SCI_PAR_ODD)
{
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x8U);
}
else
{
(*((volatile uint16_t *)(base + 0x4U))) |= 0x8U;
}
}
//*****************************************************************************
//
//! Disable SCI Parity mode.
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function disables the parity check.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIParity(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Disable the parity mode
//
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x4U);
}
//*****************************************************************************
//
//! Set the number of stop bits for SCI
//!
//! \param base is the LIN module base address
//! \param number is the number of stop bits
//!
//! In SCI mode only, this function sets the number of stop bits transmitted.
//! The \e number parameter can be one of the following values:
//! - \b LIN_SCI_STOP_ONE - Set one stop bit
//! - \b LIN_SCI_STOP_TWO - Set two stop bits
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIStopBits(uint32_t base, LIN_SCIStopBits number)
{
//
// Check the arguments.
//
;
;
//
// Set the number of stop bits
//
if(number == LIN_SCI_STOP_ONE)
{
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x10U);
}
else
{
(*((volatile uint16_t *)(base + 0x4U))) |= 0x10U;
}
}
//*****************************************************************************
//
//! Enable SCI Sleep mode.
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function enables the receive sleep mode
//! functionality.
//!
//! \note The receiver still operates when the sleep mode is enabled, however,
//! RXRDY is updated and SCIRD is loaded with new data only when an address
//! frame is detected.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCISleepMode(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Set sleep mode bit
//
(*((volatile uint16_t *)(base + 0x4U))) |= 0x100U;
}
//*****************************************************************************
//
//! Disable SCI Sleep mode.
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function disables the receive sleep mode
//! functionality.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCISleepMode(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Clear sleep mode bit
//
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x100U);
}
//*****************************************************************************
//
//! Enter SCI Local Low-Power Mode
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function enters the SCI local low-power mode.
//!
//! \note If this function is called while the receiver is actively receiving
//! data and the wakeup interrupt is disabled, then the module will delay
//! sleep mode from being entered until completion of reception.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enterSCILowPower(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Set low power bit
//
(*((volatile uint16_t *)(base + 0x8U))) |= 0x1U;
}
//*****************************************************************************
//
//! Exit SCI Local Low-Power Mode
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function exits the SCI local low-power mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_exitSCILowPower(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Clear low power bit
//
(*((volatile uint16_t *)(base + 0x8U))) &= ~0x1U;
}
//*****************************************************************************
//
//! Set SCI character length
//!
//! \param base is the LIN module base address
//! \param numBits is the number of bits per character.
//!
//! In SCI mode only, this function sets the number of bits per character.
//!
//! The \e numBits parameter must be in a range between 1 and 8.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCICharLength(uint32_t base, uint16_t numBits)
{
//
// Check the arguments.
//
;
;
;
//
// Set the number of bits per character
//
(*((volatile uint16_t *)(base + 0x28U))) = ((*((volatile uint16_t *)(base + 0x28U))) &
~0x7U) |
(uint16_t)(numBits - 1U);
}
//*****************************************************************************
//
//! Set SCI Frame Length
//!
//! \param base is the LIN module base address
//! \param length is the number of characters
//!
//! In SCI mode only, this function sets the number of characters in the
//! response field.
//!
//! The \e length parameter must be in a range between 1 and 8.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIFrameLength(uint32_t base, uint16_t length)
{
//
// Check the arguments.
//
;
;
;
//
// Set number of characters
//
__byte_peripheral_32((uint32_t *)(base + 0x28U)) = (__byte_peripheral_32((uint32_t *)(base + 0x28U)) &
~(0x70000U)) |
(((uint32_t)length - (uint32_t)1U) <<
16U);
}
//*****************************************************************************
//
//! Check if new SCI data is ready to be read
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks to see if the Rx ready bit is set
//! indicating that a new data has been received.
//!
//! \return Returns \b true if the Rx ready flag is set, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isSCIDataAvailable(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Read Rx Ready flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x200U) ==
0x200U);
}
//*****************************************************************************
//
//! Check if Space is available in SCI Transmit Buffer
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks to see if the Tx ready flag is set
//! indicating that the Tx buffer(s) is/are ready to get another character.
//!
//! \return Returns \b true if the TX ready flag is set, else returns \b false
//
//*****************************************************************************
static inline _Bool
LIN_isSCISpaceAvailable(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Read Tx buffer flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x100U) ==
0x100U);
}
//*****************************************************************************
//
//! Reads a SCI character without Blocking
//!
//! \param base is the LIN module base address
//! \param emulation sets whether the data is being read by an emulator or not
//!
//! In SCI mode only, this function gets the byte of data received. The
//! \e emulation parameter can have one of the following values:
//! - \b true - Emulator is being used, the RXRDY flag won't be cleared
//! - \b false - Emulator isn't being used, the RXRDY flag will be cleared
//! automatically on read
//!
//! \note
//! -# If the SCI receives data that is fewer than 8 bits in length, the
//! data is left-justified and padded with trailing zeros.
//! -# To determine if new data is available to read, use the function
//! LIN_isSCIDataAvailable().
//!
//! \return Returns the received data.
//
//*****************************************************************************
static inline uint16_t
LIN_readSCICharNonBlocking(uint32_t base, _Bool emulation)
{
//
// Check the arguments.
//
;
;
//
// Read specific data register
//
return(emulation ? ((*((volatile uint16_t *)(base + 0x30U))) & 0xFFU) :
((*((volatile uint16_t *)(base + 0x34U))) & 0xFFU));
}
//*****************************************************************************
//
//! Reads a SCI character with Blocking
//!
//! \param base is the LIN module base address
//! \param emulation sets whether the data is being read by an emulator or not
//!
//! In SCI mode only, this function gets the byte of data received. If new data
//! isn't available, this function will wait until new data arrives. The
//! \e emulation parameter can have one of the following values:
//! - \b true - Emulator is being used, the RXRDY flag won't be cleared
//! - \b false - Emulator isn't being used, the RXRDY flag will be cleared
//! automatically on read
//!
//! \note If the SCI receives data that is fewer than 8 bits in length, the
//! data is left-justified and padded with trailing zeros.
//!
//! \return Returns the received data.
//
//*****************************************************************************
static inline uint16_t
LIN_readSCICharBlocking(uint32_t base, _Bool emulation)
{
//
// Check the arguments.
//
;
;
//
// Wait until a character is available in buffer.
//
while(!LIN_isSCIDataAvailable(base))
{
}
//
// Read specific data register
//
return(emulation ? ((*((volatile uint16_t *)(base + 0x30U))) & 0xFFU) :
((*((volatile uint16_t *)(base + 0x34U))) & 0xFFU));
}
//*****************************************************************************
//
//! Sends a SCI character without blocking
//!
//! \param base is the LIN module base address
//! \param data is the byte of data to be transmitted
//!
//! In SCI mode only, this function sets the byte of data to be transmitted
//! without blocking.
//!
//! \note The transmit ready flag gets set when this buffer is ready to be
//! loaded with another byte of data. Use LIN_isSCISpaceAvailable() to
//! determine if space is available to write another character.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_writeSCICharNonBlocking(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
;
;
//
// Set the Tx Data
//
(*((volatile uint16_t *)(base + 0x38U))) = (data & 0xFFU);
}
//*****************************************************************************
//
//! Sends a SCI character with blocking
//!
//! \param base is the LIN module base address
//! \param data is the byte of data to be transmitted
//!
//! In SCI mode only, this function sets the byte of data to be transmitted
//! with blocking functionality. If the buffer isn't ready to get new data
//! written to, this function will wait until space is available.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_writeSCICharBlocking(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
;
;
//
// Wait until space is available in the transmit buffer.
//
while(!LIN_isSCISpaceAvailable(base))
{
}
//
// Set the Tx Data
//
(*((volatile uint16_t *)(base + 0x38U))) = (data & 0xFFU);
}
//*****************************************************************************
//
//! Enable SCI Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be enabled
//!
//! In SCI mode only, this function enables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_SCI_ALL_ERRORS can be used to enable all of
//! them:
//! - \b LIN_SCI_FRAME_ERROR - Simulates a frame error
//! - \b LIN_SCI_PARITY_ERROR - Simulates a parity error
//! - \b LIN_SCI_BREAK_ERROR - Simulates a break detect error
//!
//! \note To disable these errors, use the LIN_disableSCIModuleErrors()
//! function.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIModuleErrors(uint32_t base, uint32_t errors)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
//
// Enable write access
//
(*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) <<
8U);
//
// Enable specified error bits
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) |= errors;
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) <<
8U);
__edis();
}
//*****************************************************************************
//
//! Disable SCI Module Errors for Testing
//!
//! \param base is the LIN module base address
//! \param errors is the specified errors to be disabled
//!
//! In SCI mode only, this function disables the specified errors in the module
//! for testing. The \e errors parameter can be a logical OR-ed result of the
//! following values or \b LIN_SCI_ALL_ERRORS can be used to enable all of
//! them:
//! - \b LIN_SCI_FRAME_ERROR - Simulates a frame error
//! - \b LIN_SCI_PARITY_ERROR - Simulates a parity error
//! - \b LIN_SCI_BREAK_ERROR - Simulates a break detect error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIModuleErrors(uint32_t base, uint32_t errors)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
//
// Enable write access
//
(*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) <<
8U);
//
// Disable specified error bits
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(errors);
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~((0xAU) <<
8U);
__edis();
}
//*****************************************************************************
//
//! Enable SCI interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! In SCI mode only, this function enables the interrupts for the specified
//! interrupt sources.
//!
//! The \e intFlags parameter can be set to the following value to set
//! all the flag bits:
//! - \b LIN_SCI_INT_ALL - All Interrupts
//!
//! To set individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_SCI_INT_BREAK - Break Detect
//! - \b LIN_SCI_INT_WAKEUP - Wakeup
//! - \b LIN_SCI_INT_TX - Transmit Buffer
//! - \b LIN_SCI_INT_RX - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA - DMA Receive
//! - \b LIN_SCI_INT_RX_DMA_ALL - DMA Receive All
//! - \b LIN_SCI_INT_PARITY - Parity Error
//! - \b LIN_SCI_INT_OVERRUN - Overrun Error
//! - \b LIN_SCI_INT_FRAME - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableSCIInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
;
//
// Set specified interrupts
//
__byte_peripheral_32((uint32_t *)(base + 0xCU)) |= intFlags;
}
//*****************************************************************************
//
//! Disable SCI interrupts
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! In SCI mode only, this function disables the interrupts for the specified
//! interrupt sources.
//!
//! The \e intFlags parameter can be set to the following value to disable
//! all the flag bits:
//! - \b LIN_SCI_INT_ALL - All Interrupts
//!
//! To disable individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_SCI_INT_BREAK - Break Detect
//! - \b LIN_SCI_INT_WAKEUP - Wakeup
//! - \b LIN_SCI_INT_TX - Transmit Buffer
//! - \b LIN_SCI_INT_RX - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA - DMA Receive
//! - \b LIN_SCI_INT_RX_DMA_ALL - DMA Receive All
//! - \b LIN_SCI_INT_PARITY - Parity Error
//! - \b LIN_SCI_INT_OVERRUN - Overrun Error
//! - \b LIN_SCI_INT_FRAME - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableSCIInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
;
//
// Set specified interrupts to be cleared
//
__byte_peripheral_32((uint32_t *)(base + 0x10U)) |= intFlags;
}
//*****************************************************************************
//
//! Clear SCI interrupt status
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of the interrupt sources to be cleared.
//!
//! In SCI mode only, this function clears the specified status flags.
//!
//! The \e intFlags parameter can be set to the following value to clear
//! all the flag bits:
//! - \b LIN_SCI_INT_ALL - All Interrupts
//!
//! To clear individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_SCI_INT_BREAK - Break Detect
//! - \b LIN_SCI_INT_WAKEUP - Wakeup
//! - \b LIN_SCI_INT_TX - Transmit Buffer
//! - \b LIN_SCI_INT_RX - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA - DMA Receive
//! - \b LIN_SCI_INT_RX_DMA_ALL - DMA Receive All
//! - \b LIN_SCI_INT_PARITY - Parity Error
//! - \b LIN_SCI_INT_OVERRUN - Overrun Error
//! - \b LIN_SCI_INT_FRAME - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_clearSCIInterruptStatus(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
;
//
// Clear the status flags
//
__byte_peripheral_32((uint32_t *)(base + 0x1CU)) |= intFlags;
}
//*****************************************************************************
//
//! Set SCI interrupt level to 0
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In SCI mode only, this function sets the specified interrupt sources to
//! level 0.
//!
//! The \e intFlags parameter can be set to the following value to set
//! all the flag bits:
//! - \b LIN_SCI_INT_ALL - All Interrupts
//!
//! To set individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_SCI_INT_BREAK - Break Detect
//! - \b LIN_SCI_INT_WAKEUP - Wakeup
//! - \b LIN_SCI_INT_TX - Transmit Buffer
//! - \b LIN_SCI_INT_RX - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA - DMA Receive
//! - \b LIN_SCI_INT_RX_DMA_ALL - DMA Receive All
//! - \b LIN_SCI_INT_PARITY - Parity Error
//! - \b LIN_SCI_INT_OVERRUN - Overrun Error
//! - \b LIN_SCI_INT_FRAME - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIInterruptLevel0(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
;
//
// Clear interrupt levels to 0
//
__byte_peripheral_32((uint32_t *)(base + 0x18U)) |= intFlags;
}
//*****************************************************************************
//
//! Set SCI interrupt level to 1
//!
//! \param base is the LIN module base address
//! \param intFlags is the bit mask of interrupt sources to be configured
//!
//! In SCI mode only, this function sets the specified interrupt sources to
//! level 1.
//!
//! The \e intFlags parameter can be set to the following value to set
//! all the flag bits:
//! - \b LIN_SCI_INT_ALL - All Interrupts
//!
//! To set individual flags, the \e intFlags parameter can be the logical
//! OR of any of the following:
//! - \b LIN_SCI_INT_BREAK - Break Detect
//! - \b LIN_SCI_INT_WAKEUP - Wakeup
//! - \b LIN_SCI_INT_TX - Transmit Buffer
//! - \b LIN_SCI_INT_RX - Receive Buffer
//! - \b LIN_SCI_INT_TX_DMA - DMA Transmit
//! - \b LIN_SCI_INT_RX_DMA - DMA Receive
//! - \b LIN_SCI_INT_RX_DMA_ALL - DMA Receive All
//! - \b LIN_SCI_INT_PARITY - Parity Error
//! - \b LIN_SCI_INT_OVERRUN - Overrun Error
//! - \b LIN_SCI_INT_FRAME - Framing Error
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setSCIInterruptLevel1(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
;
//
// Set interrupt levels to 1
//
__byte_peripheral_32((uint32_t *)(base + 0x14U)) |= intFlags;
}
//*****************************************************************************
//
//! Check if SCI Receiver is Idle
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks if the receiver is in an idle state.
//!
//! \return Returns \b true if the state is idle, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isSCIReceiverIdle(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Read Rx Idle flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x4U) == 0U);
}
//*****************************************************************************
//
//! Gets the SCI Transmit Frame Type
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function gets the transmit frame type which can be
//! either data or an address.
//!
//! \return Returns \b true if the frame will be an address, and returns
//! \b false if the frame will be data.
//
//*****************************************************************************
static inline _Bool
LIN_getSCITxFrameType(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Read Tx Wake flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x400U) ==
0x400U);
}
//*****************************************************************************
//
//! Gets the SCI Receiver Frame Type
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function gets the receiver frame type which can be
//! either an address or not an address.
//!
//! \return Returns \b true if the frame is an address, and returns
//! \b false if the frame isn't an address.
//
//*****************************************************************************
static inline _Bool
LIN_getSCIRxFrameType(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Read Rx Wake flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x1000U) ==
0x1000U);
}
//*****************************************************************************
//
//! Check if SCI Detected a Break Condition
//!
//! \param base is the LIN module base address
//!
//! In SCI mode only, this function checks if the module detected a break
//! condition on the Rx pin.
//!
//! \return Returns \b true if break detected, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isSCIBreakDetected(uint32_t base)
{
//
// Check the arguments.
//
;
;
//
// Read Break condition flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x1U) ==
0x1U);
}
//*****************************************************************************
//
// Prototypes for the LIN and SCI mode APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the LIN module.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function sets the RESET bit of the SCIGCR0
//! register. Registers in this module are not writable until this has been
//! done. Additionally, the transmit and receive pin control functionality is
//! enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableModule(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Set reset bit.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x1U;
//
// Enable TX and RX pin control functionality
//
(*((volatile uint16_t *)(base + 0x3CU))) |= (0x2U | 0x4U);
__edis();
}
//*****************************************************************************
//
//! Disable the LIN module.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function clears the RESET bit of the SCIGCR0
//! register. Registers in this module are not writable when this bit is
//! cleared. Additionally, the transmit and receive pin control functionality
//! is disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableModule(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
// Disable TX and RX pin control functionality
//
(*((volatile uint16_t *)(base + 0x3CU))) &= ~(0x2U | 0x4U);
//
// Clear reset bit.
//
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x1U;
__edis();
}
//*****************************************************************************
//
//! Set Baud Rate Prescaler
//!
//! \param base is the LIN module base address
//! \param prescaler is the 24-bit integer prescaler
//! \param divider is the 4-bit fractional divider
//!
//! In LIN and SCI mode, this function is used to set the baudrate based on
//! the \e prescaler and \e divider values.
//!
//! P = Prescaler \n
//! M = Fractional Divider \n
//! Bitrate = (SYSCLOCK) / ((P + 1 + M/16) * 16) \n
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setBaudRatePrescaler(uint32_t base, uint32_t prescaler,
uint32_t divider)
{
//
// Check the arguments.
//
;
;
;
//
// Set baud rate prescaler and divider
//
__byte_peripheral_32((uint32_t *)(base + 0x2CU)) = (prescaler | (divider << 24U));
}
//*****************************************************************************
//
//! Enable Transmit Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the transfer of data from
//! SCITD or TDy to the transmit shift register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableDataTransmitter(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable transmit bit
//
__byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x2000000U;
}
//*****************************************************************************
//
//! Disable Transmit Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the transfer of data from
//! SCITD or TDy to the transmit shift register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableDataTransmitter(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable transmit bit
//
__byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x2000000U);
}
//*****************************************************************************
//
//! Enable Receive Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the receiver to transfer data
//! from the shift buffer register to the receive buffer or multi-buffer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableDataReceiver(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable receive bit
//
__byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x1000000U;
}
//*****************************************************************************
//
//! Disable Receive Data Transfer.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the receiver to transfer data
//! from the shift buffer register to the receive buffer or multi-buffer.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableDataReceiver(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable receive bit
//
__byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x1000000U);
}
//*****************************************************************************
//
//! Perform software reset.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function will reset the LIN state machine and
//! clear all pending flags. It is required to call this function after a
//! wakeup signal has been sent.
//!
//! To enter the reset state separately, use LIN_enterSoftwareReset(). To come
//! out of reset, use LIN_exitSoftwareReset().
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_performSoftwareReset(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x80U);
(*((volatile uint16_t *)(base + 0x4U))) |= 0x80U;
}
//*****************************************************************************
//
//! Put LIN into its reset state.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function will reset the LIN state machine and
//! clear all pending flags. It is required to call this function after a
//! wakeup signal has been sent. When in this state, changes to the
//! configuration of this module may be made.
//!
//! To take LIN out of the reset state and back into the ready state, use
//! LIN_exitSoftwareReset().
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enterSoftwareReset(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x4U))) &= ~(0x80U);
}
//*****************************************************************************
//
//! Put LIN into its ready state.
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function will put LIN into its ready state.
//! Transmission and reception can be done in this state. While in the ready
//! state, configuration of the module should not be changed.
//!
//! To put the module into its reset state, use LIN_enterSoftwareReset().
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_exitSoftwareReset(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x4U))) |= 0x80U;
}
//*****************************************************************************
//
//! Check if Bus is Busy
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function checks if the receiver bus is busy
//! receiving a frame.
//!
//! \return Returns \b true if the bus is busy, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isBusBusy(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read Bus busy flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x8U) ==
0x8U);
}
//*****************************************************************************
//
//! Check if the Transmit Buffer is Empty
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function checks if the transmit buffer is empty
//! or not.
//!
//! \return Returns \b true if the Tx buffer is empty, else returns \b false.
//
//*****************************************************************************
static inline _Bool
LIN_isTxBufferEmpty(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read Tx Empty Flag and return status
//
return(((*((volatile uint16_t *)(base + 0x1CU))) & 0x800U) ==
0x800U);
}
//*****************************************************************************
//
//! Enable External Loopback mode for self test
//!
//! \param base is the LIN module base address
//! \param loopbackType is the loopback type (analog or digital)
//! \param path sets the transmit or receive pin to be included in the
//! communication path (Analog loopback mode only)
//!
//! In LIN and SCI mode, this function enables the external Loopback mode for
//! self test. The \e loopbackType parameter can be one of the following
//! values:
//! - \b LIN_LOOPBACK_DIGITAL - Digital Loopback
//! - \b LIN_LOOPBACK_ANALOG - Analog Loopback
//!
//! The \e path parameter is only applicable in analog loopback mode and can
//! be one of the following values:
//! - \b LIN_ANALOG_LOOP_NONE - Default option for digital loopback mode
//! - \b LIN_ANALOG_LOOP_TX - Enables analog loopback through the Tx pin
//! - \b LIN_ANALOG_LOOP_RX - Enables analog loopback through the Rx pin
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableExtLoopback(uint32_t base, LIN_LoopbackType loopbackType,
LIN_AnalogLoopback path)
{
//
// Check the arguments.
//
;
__eallow();
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
//
// Enable Loopback either in Analog or Digital Mode
//
(*((volatile uint16_t *)(base + 0x90U))) |= (((0xAU) <<
8U) |
(uint16_t)loopbackType |
(uint16_t)path);
__edis();
}
//*****************************************************************************
//
//! Disable External Loopback mode for self test
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the external Loopback mode.
//!
//! \note This function also resets the analog loopback communication path to
//! the default transmit pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableExtLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
//Disable Loopback Mode
//
__eallow();
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U |
0x2U |
0x1U);
__edis();
}
//*****************************************************************************
//
//! Enable Internal Loopback mode for self test
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the internal Loopback mode for
//! self test.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableIntLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the internal loopback
//
__byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x10000U;
}
//*****************************************************************************
//
//! Disable Internal Loopback mode for self test
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the internal Loopback mode for
//! self test.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableIntLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the internal loopback
//
__byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x10000U);
}
//*****************************************************************************
//
//! Get Interrupt Flags Status
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function returns the interrupt status register.
//!
//! The following flags can be used to mask the value returned:
//! - \b LIN_FLAG_BREAK - Break Detect Flag (SCI mode only)
//! - \b LIN_FLAG_WAKEUP - Wake-up Flag
//! - \b LIN_FLAG_IDLE - Receiver in Idle State (SCI mode only)
//! - \b LIN_FLAG_BUSY - Busy Flag
//! - \b LIN_FLAG_TO - Bus Idle Timeout Flag (LIN mode only)
//! - \b LIN_FLAG_TOAWUS - Timeout after Wakeup Signal (LIN mode only)
//! - \b LIN_FLAG_TOA3WUS - Timeout after 3 Wakeup Signals (LIN mode only)
//! - \b LIN_FLAG_TXRDY - Transmitter Buffer Ready Flag
//! - \b LIN_FLAG_RXRDY - Receiver Buffer Ready Flag
//! - \b LIN_FLAG_TXWAKE - Transmitter Wakeup Method Select (SCI mode only)
//! - \b LIN_FLAG_TXEMPTY - Transmitter Empty Flag
//! - \b LIN_FLAG_RXWAKE - Receiver Wakeup Detect Flag
//! - \b LIN_FLAG_TXID - Identifier on Transmit Flag (LIN mode only)
//! - \b LIN_FLAG_RXID - Identifier on Receive Flag (LIN mode only)
//! - \b LIN_FLAG_PE - Parity Error Flag
//! - \b LIN_FLAG_OE - Overrun Error Flag
//! - \b LIN_FLAG_FE - Framing Error Flag
//! - \b LIN_FLAG_NRE - No-Response Error Flag (LIN mode only)
//! - \b LIN_FLAG_ISFE - Inconsistent Synch Field Error Flag (LIN mode only)
//! - \b LIN_FLAG_CE - Checksum Error Flag (LIN mode only)
//! - \b LIN_FLAG_PBE - Physical Bus Error Flag (LIN mode only)
//! - \b LIN_FLAG_BE - Bit Error Flag (LIN mode only)
//!
//! \return Returns the status flag register.
//
//*****************************************************************************
static inline uint32_t
LIN_getInterruptStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Read and return the flag register
//
return(__byte_peripheral_32((uint32_t *)(base + 0x1CU)));
}
//*****************************************************************************
//
//! Get the Interrupt Level
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function gets the interrupt level status for
//! all interrupt sources.
//!
//! \return Returns the value of the interrupt level register.
//
//*****************************************************************************
static inline uint32_t
LIN_getInterruptLevel(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Gets the interrupt levels for all sources
//
return(__byte_peripheral_32((uint32_t *)(base + 0x14U)));
}
//*****************************************************************************
//
//! Gets the Interrupt Vector Offset for Line 0
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function gets the offset for interrupt line 0.
//! A read to the specified line register updates its value to the next highest
//! priority pending interrupt in the flag register and clears the flag
//! corresponding to the offset that was read.
//!
//! \note The flags for the receive and the transmit interrupts cannot be
//! cleared by reading the corresponding offset vector in this function.
//!
//! The following are values that can be returned:
//! - \b LIN_VECT_NONE - No Interrupt
//! - \b LIN_VECT_WAKEUP - Wakeup
//! - \b LIN_VECT_ISFE - Inconsistent-sync-field Error
//! - \b LIN_VECT_PE - Parity Error
//! - \b LIN_VECT_ID - ID Interrupt
//! - \b LIN_VECT_PBE - Physical Bus Error
//! - \b LIN_VECT_FE - Frame Error
//! - \b LIN_VECT_BREAK - Break detect
//! - \b LIN_VECT_CE - Checksum Error
//! - \b LIN_VECT_OE - Overrun Error
//! - \b LIN_VECT_BE - Bit Error
//! - \b LIN_VECT_RX - Receive Interrupt
//! - \b LIN_VECT_TX - Transmit Interrupt
//! - \b LIN_VECT_NRE - No-response Error
//! - \b LIN_VECT_TOAWUS - Timeout after wakeup signal
//! - \b LIN_VECT_TOA3WUS - Timeout after 3 wakeup signals
//! - \b LIN_VECT_TO - Timeout (Bus Idle)
//!
//! \return Returns the interrupt vector offset for interrupt line 0.
//
//*****************************************************************************
static inline uint16_t
LIN_getInterruptLine0Offset(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Get interrupt vector line offset
//
return((*((volatile uint16_t *)(base + 0x20U))) & 0x1FU);
}
//*****************************************************************************
//
//! Gets the Interrupt Vector Offset for Line 1
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function gets the offset for interrupt line 1.
//! A read to the specified line register updates its value to the next highest
//! priority pending interrupt in the flag register and clears the flag
//! corresponding to the offset that was read.
//!
//! \note The flags for the receive and the transmit interrupts cannot be
//! cleared by reading the corresponding offset vector in this function.
//!
//! The following are values that can be returned:
//! - \b LIN_VECT_NONE - No Interrupt
//! - \b LIN_VECT_WAKEUP - Wakeup
//! - \b LIN_VECT_ISFE - Inconsistent-sync-field Error
//! - \b LIN_VECT_PE - Parity Error
//! - \b LIN_VECT_ID - ID Interrupt
//! - \b LIN_VECT_PBE - Physical Bus Error
//! - \b LIN_VECT_FE - Frame Error
//! - \b LIN_VECT_BREAK - Break detect
//! - \b LIN_VECT_CE - Checksum Error
//! - \b LIN_VECT_OE - Overrun Error
//! - \b LIN_VECT_BE - Bit Error
//! - \b LIN_VECT_RX - Receive Interrupt
//! - \b LIN_VECT_TX - Transmit Interrupt
//! - \b LIN_VECT_NRE - No-response Error
//! - \b LIN_VECT_TOAWUS - Timeout after wakeup signal
//! - \b LIN_VECT_TOA3WUS - Timeout after 3 wakeup signals
//! - \b LIN_VECT_TO - Timeout (Bus Idle)
//!
//! \return Returns the interrupt vector offset for interrupt line 1.
//
//*****************************************************************************
static inline uint16_t
LIN_getInterruptLine1Offset(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Get interrupt vector line offset
//
return((*((volatile uint16_t *)(base + 0x24U))) & 0x1FU);
}
//*****************************************************************************
//
//! Enable Multi-buffer Mode
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function enables the multi-buffer mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableMultibufferMode(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x4U))) |= 0x400U;
}
//*****************************************************************************
//
//! Disable Multi-buffer Mode
//!
//! \param base is the LIN module base address
//!
//! In LIN and SCI mode, this function disables the multi-buffer mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableMultibufferMode(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x400U;
}
//*****************************************************************************
//
//! Set Transmit Pin Delay
//!
//! \param base is the LIN module base address
//! \param delay is number of clock delays for the Tx pin (0 to 7)
//!
//! In LIN and SCI mode, this function sets the delay by which the value on
//! the transmit pin is delayed so that the value on the receive pin is
//! asynchronous.
//!
//! \note This is not applicable to the Start bit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setTransmitDelay(uint32_t base, uint16_t delay)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
//
// Enable write access
//
(*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) <<
8U);
//
// Clear delay value
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(0x70000U);
//
// Set the delay value
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) |= ((uint32_t)delay <<
16U);
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
__edis();
}
//*****************************************************************************
//
//! Set Pin Sample Mask
//!
//! \param base is the LIN module base address
//! \param mask is the pin sample mask to be set
//!
//! In LIN and SCI mode, this function sets sample number at which the transmit
//! pin value that is being transmitted will be inverted to verify the
//! receive pin samples correctly with the majority detection circuitry.
//! The \e mask parameter can be one of the following values:
//! - \b LIN_PINMASK_NONE - No mask
//! - \b LIN_PINMASK_CENTER - Invert Tx Pin value at T-bit center
//! - \b LIN_PINMASK_CENTER_SCLK - Invert Tx Pin value at T-bit center + SCLK
//! - \b LIN_PINMASK_CENTER_2SCLK - Invert Tx Pin value at T-bit center +
//! 2 SCLK
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setPinSampleMask(uint32_t base, LIN_PinSampleMask mask)
{
//
// Check the arguments.
//
;
__eallow();
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
//
// Enable write access
//
(*((volatile uint16_t *)(base + 0x90U))) |= ((0xAU) <<
8U);
//
// Clear pin mask
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) &= ~(0x180000U);
//
// Set new pin mask value
//
__byte_peripheral_32((uint32_t *)(base + 0x90U)) |= ((uint32_t)mask <<
19U);
//
// Clear the IO DFT Enable Key
//
(*((volatile uint16_t *)(base + 0x90U))) &= ~(0xF00U);
__edis();
}
//*****************************************************************************
//
//! Set the Debug Suspended Mode
//!
//! \param base is the LIN module base address
//! \param mode is the debug mode
//!
//! In LIN and SCI mode, this function sets how the module operates when the
//! program is suspended and being debugged with an emulator. The \e mode
//! parameter can be one of the following values:
//! - \b LIN_DEBUG_FROZEN - The module state machine is frozen; transmissions
//! and LIN counters are halted until debug mode is exited.
//! - \b LIN_DEBUG_COMPLETE - The module continues to operate until the
//! current transmit and receive functions are complete.
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_setDebugSuspendMode(uint32_t base, LIN_DebugMode mode)
{
//
// Check the arguments.
//
;
//
// Set the debug suspend mode type
//
if(mode == LIN_DEBUG_FROZEN)
{
__byte_peripheral_32((uint32_t *)(base + 0x4U)) &= ~(0x20000U);
}
else
{
__byte_peripheral_32((uint32_t *)(base + 0x4U)) |= 0x20000U;
}
}
//*****************************************************************************
//
//! Enables a LIN global interrupt.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function globally enables an interrupt
//! corresponding to a specified interrupt line. The \e line parameter can be
//! one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_enableGlobalInterrupt(uint32_t base, LIN_InterruptLine line)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0xE0U))) |= 0x1U <<
(uint16_t)line;
}
//*****************************************************************************
//
//! Disables a LIN global interrupt.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function globally disables an interrupt
//! corresponding to a specified interrupt line. The \e line parameter can be
//! one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_disableGlobalInterrupt(uint32_t base, LIN_InterruptLine line)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0xE0U))) &= ~(0x1U <<
(uint16_t)line);
}
//*****************************************************************************
//
//! Clears a LIN global interrupt flag.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function clears the global interrupt flag that
//! corresponds to a specified interrupt line. The \e line parameter can be
//! one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1
//!
//! \return None.
//
//*****************************************************************************
static inline void
LIN_clearGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0xE8U))) = (uint16_t)0x1U <<
(uint16_t)line;
}
//*****************************************************************************
//
//! Returns a LIN global interrupt flag status.
//!
//! \param base is the LIN module base address
//! \param line is specified interrupt vector line
//!
//! In LIN and SCI mode, this function returns the status of a global interrupt
//! flag that corresponds to a specified interrupt line. The \e line parameter
//! can be one of the following enumerated values:
//!
//! - \b LIN_INTERRUPT_LINE0 - Interrupt Vector Line 0
//! - \b LIN_INTERRUPT_LINE1 - Interrupt Vector Line 1
//!
//! \return Returns \b true if the interrupt flag is set. Return \b false if
//! not.
//
//*****************************************************************************
static inline _Bool
LIN_getGlobalInterruptStatus(uint32_t base, LIN_InterruptLine line)
{
//
// Check the arguments.
//
;
//
// Read the flag register and return true if the specified flag is set.
//
return(((*((volatile uint16_t *)(base + 0xE4U))) &
(0x1U << (uint16_t)line)) ==
(0x1U << (uint16_t)line));
}
//*****************************************************************************
//
//! Get the Status of LIN TX/RX Pin status.
//!
//! \param base is the LIN module base address
//! \param pin is the type of pin that is being read.
//!
//! In LIN and SCI mode, this function indicates the current status of LINTX
//! and LINRX pins. the \e pin parameter can be either LIN_PINTYPE_TX or
//! LIN_PINTYPE_RX.
//!
//! \return Returns \b true if the pin is high else \b false if low.
//
//*****************************************************************************
static inline _Bool
LIN_getPinStatus(uint32_t base, LIN_PinType pin)
{
//
// Check the arguments.
//
;
//
// Read RX/Tx pin value and return status
//
return(((*((volatile uint16_t *)(base + 0x44U))) & (uint16_t)pin) == (uint16_t)pin);
}
//*****************************************************************************
//
//! Initializes the LIN Driver
//!
//! \param base is the LIN module base address
//!
//! This function initializes the LIN module.
//!
//! \return None.
//
//*****************************************************************************
extern void
LIN_initModule(uint32_t base);
//*****************************************************************************
//
//! Send Data
//!
//! \param base is the LIN module base address
//! \param data is the pointer to data to send
//!
//! In LIN mode only, this function sends a block of data pointed to by 'data'.
//! The number of data to transmit must be set with LIN_setFrameLength()
//! before.
//!
//! \return None.
//
//*****************************************************************************
extern void
LIN_sendData(uint32_t base, uint16_t *data);
//*****************************************************************************
//
//! Read received data
//!
//! \param base is the LIN module base address
//! \param data is the pointer to the data buffer
//!
//! In LIN mode only, this function reads a block of bytes and place it into
//! the data buffer pointed to by 'data'.
//!
//! \return None.
//
//*****************************************************************************
extern void
LIN_getData(uint32_t base, uint16_t * const data);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
/*
* Copyright (c) Texas Instruments Incorporated 2016
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/**
* \file mcan.h
*
* \brief This file contains the prototypes of the APIs present in the
* device abstraction layer file of MCAN.
* This also contains some related macros.
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
/*
* hw_mcanss.h
*
* Register-level header file for MCANSS2P0
*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/****************************************************************************************************
* Register Definitions
****************************************************************************************************/
// Sub-module base addresses
/****************************************************************************************************
* Field Definition Macros
****************************************************************************************************/
/* User defined ranges */
/**
* \file hw_types.h
*
* \brief This file contains the in-line functions required to read/write
* values from/to the hardware registers. This file also contains field
* manipulation macros to get and set field values.
*
* \copyright Copyright (C) 2013 Texas Instruments Incorporated - www.ti.com
*/
/**
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
/**
* \brief This macro reads a 32-bit value from a hardware register
* and returns the value.
*
* \param addr Address of the memory mapped hardware register.
*
* \return Unsigned 32-bit value read from a register.
*/
/**
* \brief This macro writes a 32-bit value to a hardware register.
*
* \param addr Address of the memory mapped hardware register.
* \param value unsigned 32-bit value which has to be written to the
* register.
*/
/**
* \brief This macro reads a 16-bit value from a hardware register
* and returns the value.
*
* \param addr Address of the memory mapped hardware register.
*
* \return Unsigned 16-bit value read from a register.
*/
/**
* \brief This macro writes a 16-bit value to a hardware register.
*
* \param addr Address of the memory mapped hardware register.
* \param value unsigned 16-bit value which has to be written to the
* register.
*/
/**
* \brief Macro to extract a field value. This macro extracts the field value
* from a 32-bit variable (which contains the register value).
* This macro does not read from actual register address, and only
* extracts the field from a variable.
*
* \param regVal 32-bit variable containing the register value.
* \param REG_FIELD Peripheral register bit field name, whose value has to
* be extracted.
*/
/*TI_INSPECTED 76 S : MISRAC_2012_R.20.11
* "The places in which order of evaluation has no side effects could be a
waiver. This used in SHIFT and MASK to extract specified field value " */
/*TI_INSPECTED 125 S : MISRAC_2012_R.20.12
* "The places in which order of evaluation has no side effects could be a
waiver. ## operator here used in SHIFT and MASK to extract specified field
value " */
/**
* \brief Macro to write a specific field value. This macro first clears the
* specified field value and then performs "OR" of the field value which
* is shifted and masked. This will set the field value at its
* desired position.
*
* \param regVal 32-bit variable containing the register value.
* \param REG_FIELD Peripheral register bit field name, to which specified
* value has to be set.
* \param fieldVal Value of the field which has to be set.
*/
/*TI_INSPECTED 76 S : MISRAC_2012_R.20.11
* "The places in which order of evaluation has no side effects could be a
waiver. This used in SHIFT and MASK to extract specified field value " */
/*TI_INSPECTED 125 S : MISRAC_2012_R.20.12
* "The places in which order of evaluation has no side effects could be a
waiver. ## operator here used in SHIFT and MASK to extract specified field
value " */
/**
* \brief Macro to write a specific field value. This macro first clears the
* specified field value and then performs "OR" of the field value which
* is shifted and masked. This will set the field value at its
* desired position.
*
* \param regVal 16-bit variable containing the register value.
* \param REG_FIELD Peripheral register bit field name, to which specified
* value has to be set.
* \param fieldVal Value of the field which has to be set.
*/
/*TI_INSPECTED 76 S : MISRAC_2012_R.20.11
* "The places in which order of evaluation has no side effects could be a
waiver. This used in SHIFT and MASK to extract specified field value " */
/*TI_INSPECTED 125 S : MISRAC_2012_R.20.12
* "The places in which order of evaluation has no side effects could be a
waiver. ## operator here used in SHIFT and MASK to extract specified field
value " */
/**
* \brief This macro calls read-modify-write API for 32 bit register. It also
* frames the mask and shift from register field macro.
*
* \param regAddr Register Address.
* \param REG_FIELD Peripheral register bit field name, to which specified
* value has to be set.
* \param fieldVal Value of the field which has to be set.
*/
/*TI_INSPECTED 76 S : MISRAC_2012_R.20.11
* "The places in which order of evaluation has no side effects could be a
waiver. This used in SHIFT and MASK to extract specified field value " */
/*TI_INSPECTED 125 S : MISRAC_2012_R.20.12
* "The places in which order of evaluation has no side effects could be a
waiver. ## operator here used in SHIFT and MASK to extract specified field
value " */
/**
* \brief This macro calls read-modify-write API for 16 bit register. It also
* frames the mask and shift from register field macro.
*
* \param regAddr Register Address.
* \param REG_FIELD Peripheral register bit field name, to which specified
* value has to be set.
* \param fieldVal Value of the field which has to be set.
*/
/*TI_INSPECTED 76 S : MISRAC_2012_R.20.11
* "The places in which order of evaluation has no side effects could be a
waiver. This used in SHIFT and MASK to extract specified field value " */
/*TI_INSPECTED 125 S : MISRAC_2012_R.20.12
* "The places in which order of evaluation has no side effects could be a
waiver. ## operator here used in SHIFT and MASK to extract specified field
value " */
/**
* \brief This macro calls read field API for 32 bit register. It also
* frames the mask and shift from register field macro.
*
* \param regAddr Register Address.
* \param REG_FIELD Peripheral register bit field name, from which
* specified bit-field value has to be read.
* \return Value of the bit-field
*/
/*TI_INSPECTED 76 S : MISRAC_2012_R.20.11
* "The places in which order of evaluation has no side effects could be a
waiver. This used in SHIFT and MASK to extract specified field value " */
/*TI_INSPECTED 125 S : MISRAC_2012_R.20.12
* "The places in which order of evaluation has no side effects could be a
waiver. ## operator here used in SHIFT and MASK to extract specified field
value " */
/**
* \brief This macro calls read field API for 16 bit register. It also
* frames the mask and shift from register field macro.
*
* \param regAddr Register Address.
* \param REG_FIELD Peripheral register bit field name, from which
* specified bit-field value has to be read.
* \return Value of the bit-field
*/
/*TI_INSPECTED 76 S : MISRAC_2012_R.20.11
* "The places in which order of evaluation has no side effects could be a
waiver. This used in SHIFT and MASK to extract specified field value " */
/*TI_INSPECTED 125 S : MISRAC_2012_R.20.12
* "The places in which order of evaluation has no side effects could be a
waiver. ## operator here used in SHIFT and MASK to extract specified field
value " */
/* ========================================================================== */
/* Structures and Enums */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Global Variables Declarations */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
/**
* \brief This function reads a 32-bit value from a hardware register
* and returns the value.
*
* \param addr Address of the memory mapped hardware register.
*
* \return Unsigned 32-bit value read from a register.
*/
static inline uint32_t HW_RD_REG32_RAW(uint32_t addr);
/**
* \brief This function writes a 32-bit value to a hardware register.
*
* \param addr Address of the memory mapped hardware register.
* \param value unsigned 32-bit value which has to be written to the
* register.
*/
static inline void HW_WR_REG32_RAW(uint32_t addr, uint32_t value);
/**
* \brief This function reads a 16-bit value from a hardware register
* and returns the value.
*
* \param addr Address of the memory mapped hardware register.
*
* \return Unsigned 16-bit value read from a register.
*/
static inline uint16_t HW_RD_REG16_RAW(uint32_t addr);
/**
* \brief This function writes a 16-bit value to a hardware register.
*
* \param addr Address of the memory mapped hardware register.
* \param value unsigned 16-bit value which has to be written to the
* register.
*/
static inline void HW_WR_REG16_RAW(uint32_t addr, uint16_t value);
/**
* \brief This function reads a 32 bit register, modifies specific set of
* bits and writes back to the register.
*
* \param addr Address of the memory mapped hardware register.
* \param mask Mask for the bit field.
* \param shift Bit field shift from LSB.
* \param value Value to be written to bit-field.
*/
static inline void HW_WR_FIELD32_RAW(uint32_t addr,
uint32_t mask,
uint32_t shift,
uint32_t value);
/**
* \brief This function reads a 16 bit register, modifies specific set of
* bits and writes back to the register.
*
* \param addr Address of the memory mapped hardware register.
* \param mask Mask for the bit field.
* \param shift Bit field shift from LSB.
* \param value Value to be written to bit-field.
*/
static inline void HW_WR_FIELD16_RAW(uint32_t addr,
uint16_t mask,
uint32_t shift,
uint16_t value);
/**
* \brief This function reads a 32 bit register, masks specific set of bits
* and the left shifted value.
*
* \param addr Address of the memory mapped hardware register.
* \param mask Mask for the bit field.
* \param shift Bit field shift from LSB.
*
* \return Bit-field value (absolute value - shifted to LSB position)
*/
static inline uint32_t HW_RD_FIELD32_RAW(uint32_t addr,
uint32_t mask,
uint32_t shift);
/**
* \brief This function reads a 16 bit register, masks specific set of bits
* and the left shifted value.
*
* \param addr Address of the memory mapped hardware register.
* \param mask Mask for the bit field.
* \param shift Bit field shift from LSB.
*
* \return Bit-field value (absolute value - shifted to LSB position)
*/
static inline uint16_t HW_RD_FIELD16_RAW(uint32_t addr,
uint16_t mask,
uint32_t shift);
/* ========================================================================== */
/* Static Function Definitions */
/* ========================================================================== */
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_RD_REG32 mcaro " */
/*TI_INSPECTED 101 S : MISRAC_2012_R.10.3
* "Reason - Tool Issue: Not able to understand Inline Function return type " */
/*TI_INSPECTED 102 S : MISRAC_2012_R.8.4
* "Reason - Tool Issue: Not able to understand Inline Function return type " */
static inline uint32_t HW_RD_REG32_RAW(uint32_t addr)
{
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
uint32_t regVal = *(volatile uint32_t *) addr;
return (regVal);
}
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_WR_REG32 mcaro " */
/*TI_INSPECTED 131 S : MISRAC_2012_R.5.3
* "Tool Issue - argument 'value' used here is in same scope " */
/*TI_INSPECTED 14 D 1: MISRAC_2012_R.5.8
* "Tool Issue - Modifying the contents stored at address not the addr itself */
static inline void HW_WR_REG32_RAW(uint32_t addr, uint32_t value)
{
/*TI_INSPECTED 18 D : MISRAC_2012_R.5.3
* "Tool Issue - argument 'value' used here is in same scope " */
*(volatile uint32_t *) addr = value;
return;
}
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_RD_REG16 mcaro " */
static inline uint16_t HW_RD_REG16_RAW(uint32_t addr)
{
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
uint16_t regVal = *(volatile uint16_t *) addr;
return (regVal);
}
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_WR_REG16 mcaro " */
/*TI_INSPECTED 131 S : MISRAC_2012_R.5.3
* "Tool Issue - argument 'value' used here is in same scope " */
/*TI_INSPECTED 14 D 1: MISRAC_2012_R.5.8
* "Tool Issue - Modifying the contents stored at address not the addr itself */
static inline void HW_WR_REG16_RAW(uint32_t addr, uint16_t value)
{
/*TI_INSPECTED 18 D : MISRAC_2012_R.5.3
* "Tool Issue - argument 'value' used here is in same scope " */
*(volatile uint16_t *) addr = value;
return;
}
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_WR_FIELD32 mcaro " */
/*TI_INSPECTED 14 D 1: MISRAC_2012_R.5.8
* "Tool Issue - Modifying the contents stored at address not the addr itself */
static inline void HW_WR_FIELD32_RAW(uint32_t addr,
uint32_t mask,
uint32_t shift,
uint32_t value)
{
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
uint32_t regVal = *(volatile uint32_t *) addr;
regVal &= (~mask);
regVal |= (value << shift) & mask;
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
*(volatile uint32_t *) addr = regVal;
return;
}
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_WR_FIELD16 mcaro " */
/*TI_INSPECTED 14 D 1: MISRAC_2012_R.5.8
* "Tool Issue - Modifying the contents stored at address not the addr itself */
static inline void HW_WR_FIELD16_RAW(uint32_t addr,
uint16_t mask,
uint32_t shift,
uint16_t value)
{
uint32_t tempVal;
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
uint16_t regVal = *(volatile uint16_t *) addr;
tempVal = ((uint32_t) regVal);
tempVal &= (~((uint32_t) mask));
tempVal |= (((uint32_t) value) << shift) & ((uint32_t) mask);
regVal = (uint16_t) tempVal;
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
*(volatile uint16_t *) addr = regVal;
return;
}
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_RD_FIELD32 mcaro " */
static inline uint32_t HW_RD_FIELD32_RAW(uint32_t addr,
uint32_t mask,
uint32_t shift)
{
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
uint32_t regVal = *(volatile uint32_t *) addr;
regVal = (regVal & mask) >> shift;
return (regVal);
}
/*TI_INSPECTED 35 S : MISRAC_2012_R.2.1
* "Reason - This function is called using HW_RD_FIELD16 mcaro " */
static inline uint16_t HW_RD_FIELD16_RAW(uint32_t addr,
uint16_t mask,
uint32_t shift)
{
uint32_t tempVal;
/*TI_INSPECTED 440 S : MISRAC_2012_R.11.4
* "Reason - Pointer typecast required here since addr variable holds
* required register value" */
uint16_t regVal = *(volatile uint16_t *) addr;
tempVal = (((uint32_t) regVal & (uint32_t) mask) >> shift);
regVal = (uint16_t) tempVal;
return (regVal);
}
//! \addtogroup mcan_api MCAN
//! @{
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
/**
* \brief MCAN MSG RAM BANK number for ECC AGGR.
*/
/**
* \brief Maximum Number of Rx Buffers.
*/
/**
* \brief Maximum Number of Tx Buffers.
*/
/**
* \brief Macro for standard Message ID filter.
*/
/**
* \brief Macro for extended Message ID filter.
*/
/**
* \brief Macro for Tx Event FIFO element size.
*/
/**
* \brief Macro for Interrupt Line enable mask.
*/
/**
* \brief Macro defines mask for all the interrupts status for MCAN.
*/
/**
* \brief Maximum payload supported by CAN-FD protocol in bytes.
*/
//*****************************************************************************
//
// These macro definitions are used to specify Standard Filter Types to
// set the sft values of the struct MCAN_StdMsgIDFilterElement
// used as a parameter in the function MCAN_addStdMsgIDFilter()
//
//*****************************************************************************
/**< Range Filter from SFID1 to SFID2 */
/**< Dual ID Filter for SFID1 or SFID2 */
/**< Classic Filter: SFID1 = filter, SFID2 = mask */
/**< Filter Element Disabled */
//*****************************************************************************
//
// These macro definitions are used to specify Standard Filter Element
// Configurations to set the sfec values of the struct MCAN_StdMsgIDFilterElement
// used as a parameter in the function MCAN_addStdMsgIDFilter()
//
//*****************************************************************************
/**< Filter Element Disabled */
/**< Store in RX FIFO 0 if filter matches */
/**< Store in RX FIFO 1 if filter matches */
/**< Reject ID if filter matches */
/**< Set priority if filter matches */
/**< Set priority and store in RX FIFO 0 if filter matches */
/**< Set priority and store in RX FIFO 1 if filter matches */
/**< Store in RX Buffer */
/* ========================================================================== */
/* Structures and Enums */
/* ========================================================================== */
/**
* \brief Enum to select the MCAN interrupt lines
*/
typedef enum
{
MCAN_INTR_LINE_NUM_0 = 0U,
/**< MCAN interrupt line 0 */
MCAN_INTR_LINE_NUM_1 = 1U
/**< MCAN interrupt line 1 */
}MCAN_IntrLineNum;
/**
* \brief Enum to represent the MCAN Identifier Type
*/
typedef enum
{
MCAN_ID_TYPE_11_BIT = 0U,
/**< 11bit MCAN Identifier */
MCAN_ID_TYPE_29_BIT = 1U
/**< 29bit MCAN Identifier */
}MCAN_IdType;
/**
* \brief Enum to represent the MCAN mode of operation
*/
typedef enum
{
MCAN_OPERATION_MODE_NORMAL = 0U,
/**< MCAN normal mode */
MCAN_OPERATION_MODE_SW_INIT = 1U
/**< MCAN SW initialization mode */
}MCAN_OperationMode;
/**
* \brief Enum to represent the MCAN Message RAM type.
*/
typedef enum
{
MCAN_MEM_TYPE_BUF = 0U,
/**< MCAN Msg RAM buffers */
MCAN_MEM_TYPE_FIFO = 1U
/**< MCAN Msg RAM FIFO/Queue */
}MCAN_MemType;
/**
* \brief Enum to represent the MCAN Rx FIFO number
*/
typedef enum
{
MCAN_RX_FIFO_NUM_0 = 0U,
/**< MCAN Rx FIFO 0 */
MCAN_RX_FIFO_NUM_1 = 1U
/**< MCAN Rx FIFO 1 */
}MCAN_RxFIFONum;
/**
* \brief Enum to represent the MCAN pin type
*/
typedef enum
{
MCAN_PIN_TYPE_RX = 0U,
/**< MCAN Rx Pin */
MCAN_PIN_TYPE_TX = 1U
/**< MCAN Tx Pin */
}MCAN_PinType;
/**
* \brief Enum to represent FIFO/Buffer element Size
*/
typedef enum
{
MCAN_ELEM_SIZE_8BYTES = 0U,
/**< 8 byte data field */
MCAN_ELEM_SIZE_12BYTES = 1U,
/**< 12 byte data field */
MCAN_ELEM_SIZE_16BYTES = 2U,
/**< 16 byte data field */
MCAN_ELEM_SIZE_20BYTES = 3U,
/**< 20 byte data field */
MCAN_ELEM_SIZE_24BYTES = 4U,
/**< 24 byte data field */
MCAN_ELEM_SIZE_32BYTES = 5U,
/**< 32 byte data field */
MCAN_ELEM_SIZE_48BYTES = 6U,
/**< 48 byte data field */
MCAN_ELEM_SIZE_64BYTES = 7U
/**< 64 byte data field */
}MCAN_ElemSize;
/**
* \brief Enum to represent the MCAN time-out counter configuration
*/
typedef enum
{
MCAN_TIMEOUT_SELECT_CONT = 0U,
/**< Continuous operation Mode */
MCAN_TIMEOUT_SELECT_TX_EVENT_FIFO = 1U,
/**< Timeout controlled by Tx Event FIFO */
MCAN_TIMEOUT_SELECT_RX_FIFO0 = 2U,
/**< Timeout controlled by Rx FIFO 0 */
MCAN_TIMEOUT_SELECT_RX_FIFO1 = 3U
/**< Timeout controlled by Rx FIFO 1 */
}MCAN_TimeOutSelect;
/**
* \brief Enum for MCAN interrupts.
*/
typedef enum
{
MCAN_INTR_SRC_RX_FIFO0_NEW_MSG = (0x00000001U),
/**< Rx FIFO 0 New Message interrupt */
MCAN_INTR_SRC_RX_FIFO0_WATERMARK = (0x00000002U),
/**< Rx FIFO 0 Watermark Reached interrupt */
MCAN_INTR_SRC_RX_FIFO0_FULL = (0x00000004U),
/**< Rx FIFO 0 Full interrupt */
MCAN_INTR_SRC_RX_FIFO0_MSG_LOST = (0x00000008U),
/**< Rx FIFO 0 Message Lost interrupt */
MCAN_INTR_SRC_RX_FIFO1_NEW_MSG = (0x00000010U),
/**< Rx FIFO 1 New Message interrupt */
MCAN_INTR_SRC_RX_FIFO1_WATERMARK = (0x00000020U),
/**< Rx FIFO 1 Watermark Reached interrupt */
MCAN_INTR_SRC_RX_FIFO1_FULL = (0x00000040U),
/**< Rx FIFO 1 Full interrupt */
MCAN_INTR_SRC_RX_FIFO1_MSG_LOST = (0x00000080U),
/**< Rx FIFO 1 Message Lost interrupt */
MCAN_INTR_SRC_HIGH_PRIO_MSG = (0x00000100U),
/**< High Priority Message interrupt */
MCAN_INTR_SRC_TRANS_COMPLETE = (0x00000200U),
/**< Transmission Completed interrupt */
MCAN_INTR_SRC_TRANS_CANCEL_FINISH = (0x00000400U),
/**< Transmission Cancellation Finished interrupt */
MCAN_INTR_SRC_TX_FIFO_EMPTY = (0x00000800U),
/**< Tx FIFO Empty interrupt */
MCAN_INTR_SRC_TX_EVT_FIFO_NEW_ENTRY = (0x00001000U),
/**< Tx Event FIFO New Entry interrupt */
MCAN_INTR_SRC_TX_EVT_FIFO_WATERMARK = (0x00002000U),
/**< Tx Event FIFO Watermark Reached interrupt */
MCAN_INTR_SRC_TX_EVT_FIFO_FULL = (0x00004000U),
/**< Tx Event FIFO Full interrupt */
MCAN_INTR_SRC_TX_EVT_FIFO_ELEM_LOST = (0x00008000U),
/**< Tx Event FIFO Element Lost interrupt */
MCAN_INTR_SRC_TIMESTAMP_WRAPAROUND = (0x00010000U),
/**< Timestamp Wraparound interrupt */
MCAN_INTR_SRC_MSG_RAM_ACCESS_FAILURE = (0x00020000U),
/**< Message RAM Access Failure interrupt */
MCAN_INTR_SRC_TIMEOUT = (0x00040000U),
/**< Timeout Occurred interrupt */
MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG = (0x00080000U),
/**< Message stored to Dedicated Rx Buffer interrupt */
MCAN_INTR_SRC_BIT_ERR_CORRECTED = (0x00100000U),
/**< Bit Error Corrected interrupt */
MCAN_INTR_SRC_BIT_ERR_UNCORRECTED = (0x00200000U),
/**< Bit Error Uncorrected interrupt */
MCAN_INTR_SRC_ERR_LOG_OVRFLW = (0x00400000U),
/**< Error Logging Overflow interrupt */
MCAN_INTR_SRC_ERR_PASSIVE = (0x00800000U),
/**< Error Passive interrupt */
MCAN_INTR_SRC_WARNING_STATUS = (0x01000000U),
/**< Warning Status interrupt */
MCAN_INTR_SRC_BUS_OFF_STATUS = (0x02000000U),
/**< Bus_Off Status interrupt */
MCAN_INTR_SRC_WATCHDOG = (0x04000000U),
/**< Watchdog Interrupt interrupt */
MCAN_INTR_SRC_PROTOCOL_ERR_ARB = (0x08000000U),
/**< Protocol Error in Arbitration Phase interrupt */
MCAN_INTR_SRC_PROTOCOL_ERR_DATA = (0x10000000U),
/**< Protocol Error in Data Phase interrupt */
MCAN_INTR_SRC_RES_ADDR_ACCESS = (0x20000000U)
/**< Access to Reserved Address interrupt */
}MCAN_IntrSrc;
/**
* \brief Enum to represent the ECC Error Types
*/
typedef enum
{
MCAN_ECC_ERR_TYPE_SEC = 0U,
/**< ECC Single Error Correction */
MCAN_ECC_ERR_TYPE_DED = 1U
/**< ECC Single Error Detection */
}MCAN_ECCErrType;
/**
* \brief Enum to select the MCAN Loopback mode
*/
typedef enum
{
MCAN_LPBK_MODE_INTERNAL = 0U,
/**< Internal Loop Back Mode
* This mode can be used for hot self-test and this mode will not
* affect bus state.
*/
MCAN_LPBK_MODE_EXTERNAL = 1U
/**< External Loop Back Mode
* In this mode, MCAN the M_CAN treats its own
**transmitted messages as
* received messages and stores them (if they
**pass acceptance filtering)
* into an Rx Buffer or an Rx FIFO.
* This mode will affect bus state
*/
}MCAN_LpbkMode;
/**
* \brief Enum to represent MCAN's communication state
*/
typedef enum
{
MCAN_COM_STATE_SYNCHRONIZING = 0U,
/**< MCAN is synchronizing on CAN communication */
MCAN_COM_STATE_IDLE = 1U,
/**< MCAN is neither receiver nor transmitter */
MCAN_COM_STATE_RECEIVER = 2U,
/**< MCAN is operating as receiver */
MCAN_COM_STATE_TRANSMITTER = 3U
/**< MCAN is operating as transmitter */
}MCAN_ComState;
/**
* \brief Enum to represent MCAN's Error Code
*/
typedef enum
{
MCAN_ERR_CODE_NO_ERROR = 0U,
/**< No error occurred since LEC has been reset by
* successful reception or transmission.
*/
MCAN_ERR_CODE_STUFF_ERROR = 1U,
/**< More than 5 equal bits in a sequence have occurred in a part of
* a received message where this is not allowed.
*/
MCAN_ERR_CODE_FORM_ERROR = 2U,
/**< A fixed format part of a received frame has the wrong format. */
MCAN_ERR_CODE_ACK_ERROR = 3U,
/**< The message transmitted by the M_CAN was not acknowledged
* by another node.
*/
MCAN_ERR_CODE_BIT1_ERROR = 4U,
/**< During the transmission of a message (with the exception of
* the arbitration field), the device wanted to send a
* recessive level (bit of logical value ‘1’),
* but the monitored bus value was dominant.
*/
MCAN_ERR_CODE_BIT0_ERROR = 5U,
/**< During the transmission of a message (or acknowledge bit,
* or active error flag, or overload flag), the device wanted to send
* a dominant level (data or identifier bit logical value ‘0’),
* but the monitored bus value was recessive. During Bus_Off recovery
* this status is set each time a sequence of 11 recessive bits has been
* monitored. This enables the CPU to monitor the proceeding of
* the Bus_Off recovery sequence (indicating the bus is not stuck at
* dominant or continuously disturbed).
*/
MCAN_ERR_CODE_CRC_ERROR = 6U,
/**< The CRC check sum of a received message was incorrect.
* The CRC of an incoming message does not match with the
* CRC calculated from the received data.
*/
MCAN_ERR_CODE_NO_CHANGE = 7U
/**< Any read access to the Protocol Status
* Register re-initializes
* the LEC to ‘7’. When the LEC shows the value
****‘7’,
* no CAN bus event was detected since the last
****CPU read access to
* the Protocol Status Register.
*/
}MCAN_ErrCode;
/**
* \brief Enum to determine the clock source that will be set
* up via a call to the MCAN_selectClockSource() API
*/
typedef enum
{
//! Peripheral System Clock Source
MCAN_CLOCK_SOURCE_SYS = 0x0,
//! Auxiliary Clock Input Source
MCAN_CLOCK_SOURCE_AUXIN = 0x2,
//! PLL Raw Clock Source
MCAN_CLOCK_SOURCE_PLLRAW = 0x3
} MCAN_ClockSource;
/**
* \brief Structure for bit timing calculation.
* Bit timing related to data phase will be valid only in case where
* MCAN is put in CAN-FD mode and will be '0' otherwise.
*/
typedef struct
{
uint32_t nomRatePrescalar;
/**< Nominal Baud Rate Pre-scaler
* Range:[0x0-0x1FF]
*/
uint32_t nomTimeSeg1;
/**< Nominal Time segment before sample point
* Range:[0x0-0xFF]
*/
uint32_t nomTimeSeg2;
/**< Nominal Time segment after sample point
* Range:[0x0-0x7F]
*/
uint32_t nomSynchJumpWidth;
/**< Nominal (Re)Synchronization Jump Width
* Range:[0x0-0x7F]
*/
uint32_t dataRatePrescalar;
/**< Data Baud Rate Pre-scaler
* Range:[0x0-0x1F]
*/
uint32_t dataTimeSeg1;
/**< Data Time segment before sample point
* Range:[0x0-0x1F]
*/
uint32_t dataTimeSeg2;
/**< Data Time segment after sample point
* Range:[0x0-0xF]
*/
uint32_t dataSynchJumpWidth;
/**< Data (Re)Synchronization Jump Width
* Range:[0x0-0xF]
*/
}MCAN_BitTimingParams;
/**
* \brief Structure for MCAN Transmitter Delay Compensation parameters.
*/
typedef struct
{
uint32_t tdcf;
/**< Transmitter Delay Compensation Filter Window Length
* Range:[0x0-0x7F]
*/
uint32_t tdco;
/**< Transmitter Delay Compensation Offset
* Range:[0x0-0x7F]
*/
}MCAN_TDCConfig;
/**
* \brief Structure for MCAN Global Filter Configuration parameters.
*/
typedef struct
{
uint32_t rrfe;
/**< Reject Remote Frames Extended
* 0 = Filter remote frames with 29-bit extended IDs
* 1 = Reject all remote frames with 29-bit extended IDs
*/
uint32_t rrfs;
/**< Reject Remote Frames Standard
* 0 = Filter remote frames with 11-bit standard IDs
* 1 = Reject all remote frames with 11-bit standard IDs
*/
uint32_t anfe;
/**< Accept Non-matching Frames Extended
* 0 = Accept in Rx FIFO 0
* 1 = Accept in Rx FIFO 1
* others = Reject
*/
uint32_t anfs;
/**< Accept Non-matching Frames Standard
* 0 = Accept in Rx FIFO 0
* 1 = Accept in Rx FIFO 1
* others = Reject
*/
}MCAN_GlobalFiltConfig;
/**
* \brief Structure for MCAN initialization parameters.
*/
typedef struct
{
uint32_t fdMode;
/**< FD Operation Enable
* 0 = FD operation disabled
* 1 = FD operation enabled
*/
uint32_t brsEnable;
/**< Bit Rate Switch Enable
* This is valid only when opMode = 1.
* 0 = Bit rate switching for transmissions disabled
* 1 = Bit rate switching for transmissions enabled
*/
uint32_t txpEnable;
/**< Transmit Pause
* 0 = Transmit pause disabled
* 1 = Transmit pause enabled
*/
uint32_t efbi;
/**< FEdge Filtering during Bus Integration
* 0 = Edge filtering disabled
* 1 = Two consecutive dominant tq required to detect an edge for
* hard synchronization
*/
uint32_t pxhddisable;
/**< Protocol Exception Handling Disable
* 0 = Protocol exception handling enabled
* 1 = Protocol exception handling disabled
*/
uint32_t darEnable;
/**< Disable Automatic Retransmission
* 0 = Automatic retransmission of messages not transmitted successfully
* enabled
* 1 = Automatic retransmission disabled
*/
uint32_t wkupReqEnable;
/**< Wakeup Request Enable
* 0 = Wakeup request is disabled
* 1 = Wakeup request is enabled
*/
uint32_t autoWkupEnable;
/**< Auto-Wakeup Enable
* 0 = Auto-Wakeup is disabled
* 1 = Auto-Wakeup is enabled
*/
uint32_t emulationEnable;
/**< Emulation/Debug Suspend Enable
* 0 = Emulation/Debug Suspend is disabled
* 1 = Emulation/Debug Suspend is enabled
*/
uint32_t wdcPreload;
/**< Start value of the Message RAM Watchdog Counter
* Range:[0x0-0xFF]
*/
MCAN_TDCConfig tdcConfig;
/**< Transmitter Delay Compensation parameters.
* Refer struct #MCAN_TDCConfig.
*/
uint32_t tdcEnable;
/**< Transmitter Delay Compensation Enable
* 0 = Transmitter Delay Compensation is disabled
* 1 = Transmitter Delay Compensation is enabled
*/
}MCAN_InitParams;
/**
* \brief Structure for MCAN configuration parameters.
*/
typedef struct
{
uint32_t monEnable;
/**< Bus Monitoring Mode
* 0 = Bus Monitoring Mode is disabled
* 1 = Bus Monitoring Mode is enabled
*/
uint32_t asmEnable;
/**< Restricted Operation Mode
* 0 = Normal CAN operation
* 1 = Restricted Operation Mode active
* This mode should not be combined with test modes.
*/
uint32_t tsPrescalar;
/**< Timestamp Counter Prescaler.
* Range:[0x0-0xF]
*/
uint32_t tsSelect;
/**< Timestamp source selection.
* 00= Timestamp counter value always 0x0000
* 01= Timestamp counter value incremented according to tsPrescalar
* 10= External timestamp counter value used
* 11= Same as “00”
*/
uint32_t timeoutSelect;
/**< Time-out counter source select.
* Refer enum #MCAN_TimeOutSelect.
*/
uint32_t timeoutPreload;
/**< Start value of the Timeout Counter (down-counter).
* The Timeout Counter is decremented in multiples of CAN bit times [1-16]
* depending on the configuration of the tsPrescalar.
* Range:[0x0-0xFFFF]
*/
uint32_t timeoutCntEnable;
/**< Time-out Counter Enable
* 0 = Time-out Counter is disabled
* 1 = Time-out Counter is enabled
*/
MCAN_GlobalFiltConfig filterConfig;
/**< Global Filter Configuration parameters.
* Refer struct #MCAN_GlobalFiltConfig.
*/
}MCAN_ConfigParams;
/**
* \brief Structure for MCAN error logging counters status.
*/
typedef struct
{
uint32_t transErrLogCnt;
/**< Transmit Error Counter */
uint32_t recErrCnt;
/**< Receive Error Counter */
uint32_t rpStatus;
/**< Receive Error Passive
* 0 = The Receive Error Counter is below the error passive level(128)
* 1 = The Receive Error Counter has reached the error passive level(128)
*/
uint32_t canErrLogCnt;
/**< CAN Error Logging */
}MCAN_ErrCntStatus;
/**
* \brief Structure for MCAN protocol status.
*/
typedef struct
{
uint32_t lastErrCode;
/**< Last Error Code
* Refer enum #MCAN_ErrCode
*/
uint32_t act;
/**< Activity - Monitors the module’s CAN communication state.
* refer enum #MCAN_ComState
*/
uint32_t errPassive;
/**< Error Passive
* 0 = The M_CAN is in the Error_Active state
* 1 = The M_CAN is in the Error_Passive state
*/
uint32_t warningStatus;
/**< Warning Status
* 0 = Both error counters are below the Error_Warning limit of 96
* 1 = At least one of error counter has reached the Error_Warning
* limit of 96
*/
uint32_t busOffStatus;
/**< Bus_Off Status
* 0 = The M_CAN is not Bus_Off
* 1 = The M_CAN is in Bus_Off state
*/
uint32_t dlec;
/**< Data Phase Last Error Code
* Refer enum #MCAN_ErrCode
*/
uint32_t resi;
/**< ESI flag of last received CAN FD Message
* 0 = Last received CAN FD message did not have its ESI flag set
* 1 = Last received CAN FD message had its ESI flag set
*/
uint32_t rbrs;
/**< BRS flag of last received CAN FD Message
* 0 = Last received CAN FD message did not have its BRS flag set
* 1 = TLast received CAN FD message had its BRS flag set
*/
uint32_t rfdf;
/**< Received a CAN FD Message
* 0 = Since this bit was reset by the CPU, no CAN FD message has been
* received
* 1 = Message in CAN FD format with FDF flag set has been received
*/
uint32_t pxe;
/**< Protocol Exception Event
* 0 = No protocol exception event occurred since last read access
* 1 = Protocol exception event occurred
*/
uint32_t tdcv;
/**< Transmitter Delay Compensation Value */
}MCAN_ProtocolStatus;
/**
* \brief Structure for MCAN Message RAM Configuration Parameters.
* Message RAM can contain following sections:
* Standard ID filters, Extended ID filters, TX FIFO(or TX Q),
* TX Buffers, TX EventFIFO, RX FIFO0, RX FIFO1, RX Buffer.
* Note: If particular section in the RAM is not used then it's size
* should be initialized to '0'
* (Number of buffers in case of Tx/Rx buffer).
*/
typedef struct
{
uint32_t flssa;
/**< Standard ID Filter List Start Address */
uint32_t lss;
/**< List Size: Standard ID
* 0 = No standard Message ID filter
* 1-127 = Number of standard Message ID filter elements
* others = Values greater than 128 are interpreted as 128
*/
uint32_t flesa;
/**< Extended ID Filter List Start Address */
uint32_t lse;
/**< List Size: Extended ID
* 0 = No standard Message ID filter
* 1-64 = Number of standard Message ID filter elements
* others = Values greater than 64 are interpreted as 64
*/
uint32_t txStartAddr;
/**< Tx Buffers Start Address */
uint32_t txBufNum;
/**< Number of Dedicated Transmit Buffers
* 0 = No Dedicated Tx Buffers
* 1-32 = Number of Dedicated Tx Buffers
* others = Values greater than 32 are interpreted as 32
*/
uint32_t txFIFOSize;
/**< Transmit FIFO/Queue Size
* 0 = No Tx FIFO/Queue
* 1-32 = Number of Tx Buffers used for Tx FIFO/Queue
* others = Values greater than 32 are interpreted as 32
*/
uint32_t txBufMode;
/**< Tx FIFO/Queue Mode
* 0 = Tx FIFO operation
* 1 = Tx Queue operation
*/
uint32_t txBufElemSize;
/**< Tx Buffer Element Size */
uint32_t txEventFIFOStartAddr;
/**< Tx Event FIFO Start Address */
uint32_t txEventFIFOSize;
/**< Event FIFO Size
* 0 = Tx Event FIFO disabled
* 1-32 = Number of Tx Event FIFO elements
* others = Values greater than 32 are interpreted as 32
*/
uint32_t txEventFIFOWaterMark;
/**< Tx Event FIFO Watermark
* 0 = Watermark interrupt disabled
* 1-32 = Level for Tx Event FIFO watermark interrupt
* others = Watermark interrupt disabled
*/
uint32_t rxFIFO0startAddr;
/**< Rx FIFO0 Start Address */
uint32_t rxFIFO0size;
/**< Rx FIFO0 Size
* 0 = No Rx FIFO
* 1-64 = Number of Rx FIFO elements
* others = Values greater than 64 are interpreted as 64
*/
uint32_t rxFIFO0waterMark;
/**< Rx FIFO0 Watermark
* 0 = Watermark interrupt disabled
* 1-63 = Level for Rx FIFO 0 watermark interrupt
* others = Watermark interrupt disabled
*/
uint32_t rxFIFO0OpMode;
/**< Rx FIFO0 Operation Mode
* 0 = FIFO blocking mode
* 1 = FIFO overwrite mode
*/
uint32_t rxFIFO1startAddr;
/**< Rx FIFO1 Start Address */
uint32_t rxFIFO1size;
/**< Rx FIFO1 Size
* 0 = No Rx FIFO
* 1-64 = Number of Rx FIFO elements
* others = Values greater than 64 are interpreted as 64
*/
uint32_t rxFIFO1waterMark;
/**< Rx FIFO1 Watermark
* 0 = Watermark interrupt disabled
* 1-63 = Level for Rx FIFO 1 watermark interrupt
* others = Watermark interrupt disabled
*/
uint32_t rxFIFO1OpMode;
/**< Rx FIFO1 Operation Mode
* 0 = FIFO blocking mode
* 1 = FIFO overwrite mode
*/
uint32_t rxBufStartAddr;
/**< Rx Buffer Start Address */
uint32_t rxBufElemSize;
/**< Rx Buffer Element Size */
uint32_t rxFIFO0ElemSize;
/**< Rx FIFO0 Element Size */
uint32_t rxFIFO1ElemSize;
/**< Rx FIFO1 Element Size */
}MCAN_MsgRAMConfigParams;
/**
* \brief Structure for MCAN High Priority Message.
*/
typedef struct
{
uint32_t bufIdx;
/**< Buffer Index
* Only valid when MSI[1] = ‘1’.
*/
uint32_t msi;
/**< Message Storage Indicator
* MSI[1:0]
* 00 = No FIFO selected
* 01 = FIFO message lost
* 10 = Message stored in FIFO 0
* 11 = Message stored in FIFO 1
*/
uint32_t filterIdx;
/**< Filter Index */
uint32_t filterList;
/**< Indicates the filter list of the matching filter element
* 0 = Standard Filter List
* 1 = Extended Filter List
*/
}MCAN_HighPriorityMsgInfo;
/**
* \brief Structure for MCAN new data flag for Rx buffer.
*/
typedef struct
{
uint32_t statusLow;
/**< New data flag for Rx buffer no. 0 to 31 */
uint32_t statusHigh;
/**< New data flag for Rx buffer no. 32 to 63 */
}MCAN_RxNewDataStatus;
/**
* \brief Structure for MCAN Rx FIFO Status.
*/
typedef struct
{
uint32_t num;
/**< Rx FIFO number
* Refer enum #MCAN_RxFIFONum
*/
uint32_t fillLvl;
/**< Rx FIFO Fill Level */
uint32_t getIdx;
/**< Rx FIFO Get Index */
uint32_t putIdx;
/**< Rx FIFO Put Index */
uint32_t fifoFull;
/**< Rx FIFO Full
* 0 = Rx FIFO not full
* 1 = Rx FIFO full
*/
uint32_t msgLost;
/**< Rx FIFO Message Lost */
}MCAN_RxFIFOStatus;
/**
* \brief Structure for MCAN Tx FIFO Status.
*/
typedef struct
{
uint32_t freeLvl;
/**< Tx FIFO Free Level */
uint32_t getIdx;
/**< Tx FIFO Get Index
* Read as zero when Tx Queue operation is configured.
*/
uint32_t putIdx;
/**< Tx FIFO/Queue Put Index */
uint32_t fifoFull;
/**< Tx FIFO/Queue Full
* 0 = Tx FIFO/Queue not full
* 1 = Tx FIFO/Queue full
*/
}MCAN_TxFIFOStatus;
/**
* \brief Structure for MCAN Tx Event FIFO Status.
*/
typedef struct
{
uint32_t fillLvl;
/**< Event FIFO Fill Level */
uint32_t getIdx;
/**< Event FIFO Gut Index */
uint32_t putIdx;
/**< Event FIFO Put Index */
uint32_t fifoFull;
/**< Event FIFO Full
* 0 = Tx Event FIFO not full
* 1 = Tx Event FIFO full
*/
uint32_t eleLost;
/**< Tx Event FIFO Element Lost
* 0 = No Tx Event FIFO element lost
* 1 = Tx Event FIFO element lost, also set after write attempt to
* Tx Event FIFO of size zero.
*/
}MCAN_TxEventFIFOStatus;
/**
* \brief Structure for ECC Error forcing.
*/
typedef struct
{
uint32_t errType;
/**< Error type to be forced
* Refer enum #MCAN_ECCErrType.
*/
uint32_t rowNum;
/**< Row address where error needs to be applied. */
uint32_t bit1;
/**< Column/Data bit that needs to be flipped when
* force_sec or force_ded is set
*/
uint32_t bit2;
/**< Data bit that needs to be flipped when force_ded is set */
uint32_t errOnce;
/**< Force Error once
* 1: The error will inject an error to the specified row only once
*/
uint32_t errForce;
/**< Force error on the next RAM read */
}MCAN_ECCErrForceParams;
/**
* \brief Structure for ECC Error Status.
*/
typedef struct
{
uint32_t secErr;
/**< Single Bit Error Status
* 0 = No Single Bit Error pending
* 1 = Single Bit Error pending
*/
uint32_t dedErr;
/**< Double Bit Error Status
* 0 = No Double Bit Error pending
* 1 = Double Bit Error pending
*/
uint32_t row;
/**< Indicates the row/address where the single or double bit
* error occurred.
*/
uint32_t bit1;
/**< Indicates the bit position in the ram data that is in error
*/
}MCAN_ECCErrStatus;
/**
* \brief Structure for accessing Revision ID and Core Release Info.
* of MCAN module.
*/
typedef struct
{
uint32_t scheme;
/**< Scheme */
uint32_t bu;
/**< Business Unit: 10 = Processors */
uint32_t modId;
/**< Module ID */
uint32_t rtlRev;
/**< RTL revision */
uint32_t major;
/**< Major revision */
uint32_t custom;
/**< Custom revision */
uint32_t minor;
/**< Minor revision */
uint32_t day;
/**< Time Stamp Day. Two digits, BCD-coded. */
uint32_t mon;
/**< Time Stamp Month. Two digits, BCD-coded. */
uint32_t year;
/**< Time Stamp Year. Single digit, BCD-coded. */
uint32_t subStep;
/**< Sub-step of Core Release Single digit, BCD-coded. */
uint32_t step;
/**< Step of Core Release.Two digits, BCD-coded Single digit, BCD-coded. */
uint32_t rel;
/**< Core Release. Single digit, BCD-coded. */
}MCAN_RevisionId;
/**
* \brief Structure for accessing Revision ID of ECC AGGR.
*/
typedef struct
{
uint32_t scheme;
/**< Scheme */
uint32_t bu;
/**< Business Unit: 10 = Processors */
uint32_t modId;
/**< Module ID */
uint32_t rtlRev;
/**< RTL revision */
uint32_t major;
/**< Major revision */
uint32_t custom;
/**< Custom revision */
uint32_t minor;
/**< Minor revision */
}MCAN_ECCAggrRevisionId;
/**
* \brief Structure for MCAN ECC configuration parameters.
*/
typedef struct
{
uint32_t enable;
/**< Enable/disable ECC
* 0 = Disable ECC
* 1 = Enable ECC
*/
uint32_t enableChk;
/**< Enable/disable ECC Check
* 0 = Disable ECC Check
* 1 = Enable ECC Check
*/
uint32_t enableRdModWr;
/**< Enable/disable Read Modify Write operation
* 0 = Disable Read Modify Write operation
* 1 = Enable Read Modify Write operation
*/
}MCAN_ECCConfigParams;
/**
* \brief Structure for accessing Revision ID of ECC wrapper.
*/
typedef struct
{
uint32_t scheme;
/**< Scheme */
uint32_t bu;
/**< Business Unit: 10 = Processors */
uint32_t modId;
/**< Module ID */
uint32_t rtlRev;
/**< RTL revision */
uint32_t major;
/**< Major revision */
uint32_t custom;
/**< Custom revision */
uint32_t minor;
/**< Minor revision */
}MCAN_ECCWrapRevisionId;
/**
* \brief Structure for MCAN Tx Buffer element.
*/
typedef struct
{
uint32_t id;
/**< Identifier */
uint32_t rtr;
/**< Remote Transmission Request
* 0 = Transmit data frame
* 1 = Transmit remote frame
*/
uint32_t xtd;
/**< Extended Identifier
* 0 = 11-bit standard identifier
* 1 = 29-bit extended identifier
*/
uint32_t esi;
/**< Error State Indicator
* 0 = ESI bit in CAN FD format depends only on error passive flag
* 1 = ESI bit in CAN FD format transmitted recessive
*/
uint32_t dlc;
/**< Data Length Code
* 0-8 = CAN + CAN FD: transmit frame has 0-8 data bytes
* 9-15 = CAN: transmit frame has 8 data bytes
* 9-15 = CAN FD: transmit frame has 12/16/20/24/32/48/64 data bytes
*/
uint32_t brs;
/**< Bit Rat Switching
* 0 = CAN FD frames transmitted without bit rate switching
* 1 = CAN FD frames transmitted with bit rate switching
*/
uint32_t fdf;
/**< FD Format
* 0 = Frame transmitted in Classic CAN format
* 1 = Frame transmitted in CAN FD format
*/
uint32_t efc;
/**< Event FIFO Control
* 0 = Don’t store Tx events
* 1 = Store Tx events
*/
uint32_t mm;
/**< Message Marker */
uint16_t data[(64U)];
/**< Data bytes.
* Only first dlc number of bytes are valid.
*/
}MCAN_TxBufElement;
/**
* \brief Structure for MCAN Rx Buffer element.
*/
typedef struct
{
uint32_t id;
/**< Identifier */
uint32_t rtr;
/**< Remote Transmission Request
* 0 = Received frame is a data frame
* 1 = Received frame is a remote frame
*/
uint32_t xtd;
/**< Extended Identifier
* 0 = 11-bit standard identifier
* 1 = 29-bit extended identifier
*/
uint32_t esi;
/**< Error State Indicator
* 0 = Transmitting node is error active
* 1 = Transmitting node is error passive
*/
uint32_t rxts;
/**< Rx Timestamp */
uint32_t dlc;
/**< Data Length Code
* 0-8 = CAN + CAN FD: received frame has 0-8 data bytes
* 9-15 = CAN: received frame has 8 data bytes
* 9-15 = CAN FD: received frame has 12/16/20/24/32/48/64 data bytes
*/
uint32_t brs;
/**< Bit Rat Switching
* 0 = Frame received without bit rate switching
* 1 = Frame received with bit rate switching
*/
uint32_t fdf;
/**< FD Format
* 0 = Standard frame format
* 1 = CAN FD frame format (new DLC-coding and CRC)
*/
uint32_t fidx;
/**< Filter Index */
uint32_t anmf;
/**< Accepted Non-matching Frame
* 0 = Received frame matching filter index FIDX
* 1 = Received frame did not match any Rx filter element
*/
uint16_t data[(64U)];
/**< Data bytes.
* Only first dlc number of bytes are valid.
*/
}MCAN_RxBufElement;
/**
* \brief Structure for MCAN Tx Event FIFO element.
*/
typedef struct
{
uint32_t id;
/**< Identifier */
uint32_t rtr;
/**< Remote Transmission Request
* 0 = Data frame transmitted
* 1 = Remote frame transmitted
*/
uint32_t xtd;
/**< Extended Identifier
* 0 = 11-bit standard identifier
* 1 = 29-bit extended identifier
*/
uint32_t esi;
/**< Error State Indicator
* 0 = Transmitting node is error active
* 1 = Transmitting node is error passive
*/
uint32_t txts;
/**< Tx Timestamp */
uint32_t dlc;
/**< Data Length Code
* 0-8 = CAN + CAN FD: frame with 0-8 data bytes transmitted
* 9-15 = CAN: frame with 8 data bytes transmitted
* 9-15 = CAN FD: frame with 12/16/20/24/32/48/64 data bytes transmitted
*/
uint32_t brs;
/**< Bit Rat Switching
* 0 = Frame transmitted without bit rate switching
* 1 = Frame transmitted with bit rate switching
*/
uint32_t fdf;
/**< FD Format
* 0 = Standard frame format
* 1 = CAN FD frame format (new DLC-coding and CRC)
*/
uint32_t et;
/**< Event Type
* 00 = Reserved
* 01 = Tx event
* 10 = Transmission in spite of cancellation
* (always set for transmissions in DAR mode)
* 11 = Reserved
*/
uint32_t mm;
/**< Message Marker */
}MCAN_TxEventFIFOElement;
/**
* \brief Structure for MCAN Standard Message ID Filter Element.
*/
typedef struct
{
uint32_t sfid2;
/**< Standard Filter ID 2 */
uint32_t sfid1;
/**< Standard Filter ID 1 */
uint32_t sfec;
/**< Standard Filter Element Configuration (macros defined for each value)
* 000 = Disable filter element (MCAN_STDFILTEC_DISABLE)
* 001 = Store in Rx FIFO 0 if filter matches (MCAN_STDFILTEC_FIFO0)
* 010 = Store in Rx FIFO 1 if filter matches (MCAN_STDFILTEC_FIFO1)
* 011 = Reject ID if filter matches (MCAN_STDFILTEC_REJECT)
* 100 = Set priority if filter matches (MCAN_STDFILTEC_PRI)
* 101 = Set priority and store in FIFO 0 if filter matches (MCAN_STDFILTEC_PRI_FIFO0)
* 110 = Set priority and store in FIFO 1 if filter matches (MCAN_STDFILTEC_PRI_FIFO1)
* 111 = Store into Rx Buffer or as debug message, (MCAN_STDFILTEC_RXBUFF)
* configuration of SFT[1:0] ignored.
* If SFEC = “100”, “101”, or “110” a match sets high priority
* message event is generated.
*/
uint32_t sft;
/**< Standard Filter Type (macros defined for each value)
* 00 = Range filter from SFID1 to SFID2 (SFID2 ≥ SFID1) (MCAN_STDFILT_RANGE)
* 01 = Dual ID filter for SFID1 or SFID2 (MCAN_STDFILT_DUAL)
* 10 = Classic filter: SFID1 = filter, SFID2 = mask (MCAN_STDFILT_CLASSIC)
* 11 = Filter element disabled (MCAN_STDFILT_DISABLED)
*/
}MCAN_StdMsgIDFilterElement;
/**
* \brief Structure for MCAN Extended Message ID Filter Element.
*/
typedef struct
{
uint32_t efid1;
/**< Extended Filter ID 1 */
uint32_t efec;
/**< Extended Filter Element Configuration
* 000 = Disable filter element
* 001 = Store in Rx FIFO 0 if filter matches
* 010 = Store in Rx FIFO 1 if filter matches
* 011 = Reject ID if filter matches
* 100 = Set priority if filter matches
* 101 = Set priority and store in FIFO 0 if filter matches
* 110 = Set priority and store in FIFO 1 if filter matches
* 111 = Store into Rx Buffer or as debug message,
* configuration of SFT[1:0] ignored.
* If EFEC = “100”, “101”, or “110” a match sets high priority
* message event is generated.
*/
uint32_t efid2;
/**< Extended Filter ID 2 */
uint32_t eft;
/**< Extended Filter Type
* 00 = Range filter from EFID1 to EFID2 (EFID2 ≥ EFID1)
* 01 = Dual ID filter for EFID1 or EFID2
* 10 = Classic filter: EFID1 = filter, EFID2 = mask
* 11 = Range filter from EFID1 to EFID2 (EFID2 ≥ EFID1),
* XIDAM mask not applied
*/
}MCAN_ExtMsgIDFilterElement;
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/* None */
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
/**
* \brief This function selects the specified clock source for the MCAN controller.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param source Clock source to use for the MCAN controller.
*
* The \e source parameter can be any one of the following:
* - \b MCAN_CLOCK_SOURCE_SYS - Peripheral System Clock
* - \b MCAN_CLOCK_SOURCE_AUXIN - Auxiliary Clock Input
* - \b MCAN_CLOCK_SOURCE_PLLRAW - PLL Raw Clock
*
* \retval None
*/
void MCAN_selectClockSource(uint32_t baseAddr, MCAN_ClockSource source);
/**
* \brief This function checks if the MCAN module is in Reset.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \retval state Returns TRUE if reset is in progress.
* Else returns FALSE.
*/
uint32_t MCAN_isInReset(uint32_t baseAddr);
/**
* \brief This API will return flexible data rate operation status
* MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return state Returns TRUE if flexible data rate operation
* is enabled. Else returns FALSE.
*/
uint32_t MCAN_isFDOpEnable(uint32_t baseAddr);
/**
* \brief This function checks if the memory initialization is done for
* MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \retval state Returns TRUE if memory initialization is done.
* Else returns FALSE.
*/
uint32_t MCAN_isMemInitDone(uint32_t baseAddr);
/**
* \brief This API will set MCAN module mode of operation.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param mode Mode of operation.
* Refer enum #MCAN_OperationMode.
*
* \return None.
*/
void MCAN_setOpMode(uint32_t baseAddr, uint32_t mode);
/**
* \brief This API will return MCAN module mode of operation.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return mode Mode of operation.
* Refer enum #MCAN_OperationMode.
*/
uint32_t MCAN_getOpMode(uint32_t baseAddr);
/**
* \brief This API will initialize MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param initParams Initialization parameters.
* Refer struct #MCAN_InitParams.
*
* \return status Initialization status.
*/
int32_t MCAN_init(uint32_t baseAddr, const MCAN_InitParams *initParams);
/**
* \brief This API will configure MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param configParams configuration parameters.
* Refer struct #MCAN_ConfigParams.
*
* \return status Configuration status.
*/
int32_t MCAN_config(uint32_t baseAddr, const MCAN_ConfigParams *configParams);
/**
* \brief This API will enable/disable ECC on the Message RAM.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param configParams MCAN ECC Configuration Parameters.
* Refer #struct MCAN_ECCConfigParams.
*
* \return None.
*/
void MCAN_eccConfig(uint32_t baseAddr,
const MCAN_ECCConfigParams *configParams);
/**
* \brief This API will configure a bit timings for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param configParams Configuration parameters for MCAN bit timing.
* Refer struct #MCAN_BitTimingParams.
*
* \return status Bit Timings configuration status.
*/
int32_t MCAN_setBitTime(uint32_t baseAddr,
const MCAN_BitTimingParams *configParams);
/**
* \brief This API will configure Different sections of Message RAM.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param msgRAMConfigParams
* Message RAM Configuration parameters.
* Refer struct #MCAN_MsgRAMConfigParams.
*
* \return status Configuration Status.
*/
int32_t MCAN_msgRAMConfig(uint32_t baseAddr,
const MCAN_MsgRAMConfigParams *msgRAMConfigParams);
/**
* \brief This API will configure Extended ID AND Mask.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param idMask Configuration parameters for MCAN Extended Id mask.
* This value is 29 bit wide.
*
* \return status Extended ID AND Mask configuration status.
*/
int32_t MCAN_setExtIDAndMask(uint32_t baseAddr, uint32_t idMask);
/**
* \brief This API is used to write Tx message to message RAM.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param memType Part of message ram to which given message to write.
* Refer enum #MCAN_MemType.
* \param bufNum Buffer number where message to write.
* This parameter will ignored if memType is FIFO/Q.
* \param elem Message Object.
* Refer struct #MCAN_TxBufElement.
*
* \return None.
*/
void MCAN_writeMsgRam(uint32_t baseAddr,
uint32_t memType,
uint32_t bufNum,
const MCAN_TxBufElement *elem);
/**
* \brief This API will set Tx Buffer Add Request.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param bufNum Tx Buffer number for which request is to be added.
*
* \return status Configuration Status.
*/
int32_t MCAN_txBufAddReq(uint32_t baseAddr, uint32_t bufNum);
/**
* \brief This API will return New Data Message Status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param newDataStatus Rx Buffer new data status.
* Refer struct #MCAN_RxNewDataStatus.
*
* \return None.
*/
void MCAN_getNewDataStatus(uint32_t baseAddr,
MCAN_RxNewDataStatus *newDataStatus);
/**
* \brief This API clear New Data Message Status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param newDataStatus
* Rx Buffer new data status.
* Refer struct #MCAN_RxNewDataStatus.
*
* \return None.
*/
void MCAN_clearNewDataStatus(uint32_t baseAddr,
const MCAN_RxNewDataStatus *newDataStatus);
/**
* \brief This API is used to read received message from Message RAM.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param memType Part of message ram to which given message to write.
* Refer enum #MCAN_MemType.
* \param bufNum Buffer number from where message is to read.
* This parameter will ignored if memType is FIFO/Q.
* \param fifoNum FIFOs number from where message is to read.
* Refer enum #MCAN_RxFIFONum.
* This parameter will ignored if memType is buffer.
* \param elem Message Object.
* Refer struct #MCAN_RxBufElement.
*
* \return None.
*/
void MCAN_readMsgRam(uint32_t baseAddr,
uint32_t memType,
uint32_t bufNum,
uint32_t fifoNum,
MCAN_RxBufElement *elem);
/**
* \brief This API is used to read from Tx Event FIFO.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param txEventElem Tx Event FIFO Message Object.
* Refer struct #MCAN_TxEventFIFOElement.
*
* \return None.
*/
void MCAN_readTxEventFIFO(uint32_t baseAddr,
MCAN_TxEventFIFOElement *txEventElem);
/**
* \brief This API is used to add Standard Message ID Filter Element.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param filtNum Filter number.
* \param elem Filter Object.
* Refer struct #MCAN_StdMsgIDFilterElement.
*
* \return None.
*/
void MCAN_addStdMsgIDFilter(uint32_t baseAddr,
uint32_t filtNum,
const MCAN_StdMsgIDFilterElement *elem);
/**
* \brief This API is used to add Extended Message ID Filter Element.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param filtNum Filter number.
* \param elem Filter Object.
* Refer struct #MCAN_ExtMsgIDFilterElement.
*
* \return None.
*/
void MCAN_addExtMsgIDFilter(uint32_t baseAddr,
uint32_t filtNum,
const MCAN_ExtMsgIDFilterElement *elem);
/**
* \brief This API will enable/disable Loop Back Test Mode for
* MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param lpbkMode Loopback mode for MCAN.
* Refer #enum MCAN_LpbkMode.
* \param enable Loop Back Mode is enabled if it is TRUE.
* Loop Back Mode is disabled if it is FALSE.
*
* \return None.
* \note This API can be called only when MCAN is in Software
* Initialization mode of operation.
*/
void MCAN_lpbkModeEnable(uint32_t baseAddr,
uint32_t lpbkMode,
uint32_t enable);
/**
* \brief This API will return error counter status for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param errCounter Error Counter Status.
* Refer struct #MCAN_ErrCntStatus.
*
* \return None.
*/
void MCAN_getErrCounters(uint32_t baseAddr,
MCAN_ErrCntStatus *errCounter);
/**
* \brief This API will return protocol status for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param protStatus Protocol Status.
* Refer struct #MCAN_ProtocolStatus.
*
* \return None.
*/
void MCAN_getProtocolStatus(uint32_t baseAddr,
MCAN_ProtocolStatus *protStatus);
/**
* \brief This API is used to enable/disable interrupts.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param intrMask Interrupts to enable.
* Refer enum #MCAN_IntrSrc.
* \param enable Interrupt is enabled if it is TRUE.
* Interrupt is disabled if it is FALSE.
*
* \return None.
*/
void MCAN_enableIntr(uint32_t baseAddr, uint32_t intrMask, uint32_t enable);
/**
* \brief This API is used to select interrupt line.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param intrMask Interrupt Number for which interrupt
* line is to be selected. Refer enum #MCAN_IntrSrc.
* \param lineNum Interrupt Line to select.
* Refer enum #MCAN_IntrLineNum,
*
* \return None.
*/
void MCAN_selectIntrLine(uint32_t baseAddr,
uint32_t intrMask,
uint32_t lineNum);
/**
* \brief This API is used to get interrupt line selected for each interrupt.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Interrupt Line Select Status.
*/
uint32_t MCAN_getIntrLineSelectStatus(uint32_t baseAddr);
/**
* \brief This API is used to enable/disable selected interrupt line.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param lineNum Interrupt Line to select.
* Refer enum #MCAN_IntrLineNum,
* \param enable Interrupt Line is enabled if it is 1.
* Interrupt Line is disabled if it is 0.
*
* \return None.
*/
void MCAN_enableIntrLine(uint32_t baseAddr,
uint32_t lineNum,
uint32_t enable);
/**
* \brief This API will return interrupt status.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Interrupt Status.
*/
uint32_t MCAN_getIntrStatus(uint32_t baseAddr);
/**
* \brief This API is used to clear the interrupt status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param intrMask Interrupts to clear status.
*
* \return None.
*/
void MCAN_clearIntrStatus(uint32_t baseAddr, uint32_t intrMask);
/**
* \brief This API is used to clear the interrupt.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param intrMask Interrupts to clear.
* 0x00 External TS Interrupt is cleared
* 0x01 Interrupt Line 0 is cleared
* 0x02 Interrupt Line 1 is cleared
* Other writes are ignored
*
* \return None.
*/
void MCAN_clearInterrupt(uint32_t baseAddr, uint16_t intrNum);
/**
* \brief This API will return High Priority Message Status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param hpm High Priority Message Status.
* Refer struct #MCAN_HighPriorityMsgInfo.
*
* \return None.
*/
void MCAN_getHighPriorityMsgStatus(uint32_t baseAddr,
MCAN_HighPriorityMsgInfo *hpm);
/**
* \brief This API will read the High Priority message object from Message RAM.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param elem Message Object.
* Refer struct #MCAN_RxBufElement.
*
* \return None.
*/
void MCAN_readHighPriorityMsgRam(uint32_t baseAddr,
MCAN_RxBufElement *elem);
/**
* \brief This API will Rx FIFO status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param fifoStatus Rx FIFO Status.
* Refer struct #MCAN_RxFIFOStatus.
*
* \return None.
*/
void MCAN_getRxFIFOStatus(uint32_t baseAddr,
MCAN_RxFIFOStatus *fifoStatus);
/**
* \brief This API will write Rx FIFO Acknowledgement.
*
* \param baseAddr Base Address of the MCAN Registers.
* Refer enum #MCAN_RxFIFONum.
* \param fifoNum FIFO Number.
* \param idx Rx FIFO Acknowledge Index
*
* \return status Acknowledgement Status.
*/
int32_t MCAN_writeRxFIFOAck(uint32_t baseAddr,
uint32_t fifoNum,
uint32_t idx);
/**
* \brief This API will Tx FIFO status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param fifoStatus Tx FIFO Status.
* Refer struct #MCAN_TxFIFOStatus.
*
* \return None.
*/
void MCAN_getTxFIFOQueStatus(uint32_t baseAddr,
MCAN_TxFIFOStatus *fifoStatus);
/**
* \brief This API will return Tx Buffer Request Pending status.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Tx Buffer Request Pending status.
*/
uint32_t MCAN_getTxBufReqPend(uint32_t baseAddr);
/**
* \brief This API will set Tx Buffer Cancellation Request.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param buffNum Tx Buffer number for which request is to be added.
*
* \return status Configuration Status.
*/
int32_t MCAN_txBufCancellationReq(uint32_t baseAddr, uint32_t buffNum);
/**
* \brief This API will return Tx Buffer Transmission Occurred status.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Tx Buffer Transmission Occurred status.
*/
uint32_t MCAN_getTxBufTransmissionStatus(uint32_t baseAddr);
/**
* \brief This API will return Transmit Buffer Cancellation Finished status.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Transmit Buffer Cancellation Finished status.
*/
uint32_t MCAN_txBufCancellationStatus(uint32_t baseAddr);
/**
* \brief This API is used to enable/disable Tx Buffer Transmission Interrupt.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param bufNum Buffer number for which interrupt is to enable.
* \param enable Interrupt is enabled if it is TRUE.
* Interrupt is disabled if it is FALSE.
*
* \return status Configuration status.
*/
int32_t MCAN_txBufTransIntrEnable(uint32_t baseAddr,
uint32_t bufNum,
uint32_t enable);
/**
* \brief This API is used to enable/disable Tx Buffer Cancellation Finished
* Interrupt.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param bufNum Buffer number for which interrupt is to enable.
* \param enable Interrupt is enabled if it is TRUE.
* Interrupt is disabled if it is FALSE.
*
* \return status Configuration status.
*/
int32_t MCAN_getTxBufCancellationIntrEnable(uint32_t baseAddr,
uint32_t bufNum,
uint32_t enable);
/**
* \brief This API add clock stop request for MCAN module to put it in
* power down mode.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param enable Add CLock Stop Request.
* Adds Clock Clock stop Request is TRUE otherwise
* removes it.
*
* \return None.
*/
void MCAN_addClockStopRequest(uint32_t baseAddr, uint32_t enable);
/**
* \brief This API will Tx Event FIFO status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param fifoStatus Tx Event FIFO Status.
* Refer struct #MCAN_TxEventFIFOStatus.
*
* \return None.
*/
void MCAN_getTxEventFIFOStatus(uint32_t baseAddr,
MCAN_TxEventFIFOStatus *fifoStatus);
/**
* \brief This API will write Event FIFO Acknowledge Index.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param idx Event FIFO Acknowledge Index
*
* \return status Acknowledgement Status.
*/
int32_t MCAN_writeTxEventFIFOAck(uint32_t baseAddr, uint32_t idx);
/**
* \brief This API will Force Error on ECC.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param eccErr Force Error on ECC configuration.
* Refer struct #MCAN_ECCErrForceParams.
*
* \return status configuration status.
*/
void MCAN_eccForceError(uint32_t baseAddr,
const MCAN_ECCErrForceParams *eccErr);
/**
* \brief This API will return ECC Error status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param eccErr ECC error status.
* Refer struct #MCAN_ECCErrStatus.
*
* \return None.
*/
void MCAN_eccGetErrorStatus(uint32_t baseAddr,
MCAN_ECCErrStatus *eccErr);
/**
* \brief This API is used to clear the ECC Error status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param errType Error type to clear status.
* Refer enum #MCAN_ECCErrType.
*
* \return None.
*/
void MCAN_eccClearErrorStatus(uint32_t baseAddr, uint32_t errType);
/**
* \brief This API is used to write End of Interrupt for ECC interrupt.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param errType Interrupt to enable.
* Refer enum #MCAN_ECCErrType.
*
* \return None.
*/
void MCAN_eccWriteEOI(uint32_t baseAddr, uint32_t errType);
/**
* \brief This API is used to enable ECC interrupt.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param errType Interrupt to enable.
* Refer enum #MCAN_ECCErrType.
* \param enable ECC Interrupt is enabled if it is TRUE.
* ECC Interrupt is disabled if it is FALSE.
*
* \return None.
*/
void MCAN_eccEnableIntr(uint32_t baseAddr, uint32_t errType, uint32_t enable);
/**
* \brief This API is used to get ECC interrupt status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param errType Interrupt status to read.
* Refer enum #MCAN_ECCErrType.
*
* \return None.
*/
uint32_t MCAN_eccGetIntrStatus(uint32_t baseAddr, uint32_t errType);
/**
* \brief This API is used to clear ECC interrupt status.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param errType Interrupt status to clear.
* Refer enum #MCAN_ECCErrType.
*
* \return None.
*/
void MCAN_eccClearIntrStatus(uint32_t baseAddr, uint32_t errType);
/**
* \brief This API will configure external timestamp counter for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param prescalar Timestamp Counter Prescaler. Range:[0x0-0xFFFFFF]
*
* \return None.
*
* \note Actual value programmed prescalar values is (prescalar - 1).
*/
void MCAN_extTSCounterConfig(uint32_t baseAddr,
uint32_t prescalar);
/**
* \brief This API will enable/disable fast external time stamp counter for
* MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param enable External TS is enabled if it is 1.
* External TS is disabled if it is 0.
*
* \return None.
*/
void MCAN_extTSCounterEnable(uint32_t baseAddr, uint32_t enable);
/**
* \brief This API will enable/disable External TimeStamp Counter
* Overflow Interrupt for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param enable External TimeStamp Counter Overflow Interrupt is
* enabled if it is TRUE.
* External TimeStamp Counter Overflow Interrupt is
* disabled if it is FALSE.
*
* \return None.
*/
void MCAN_extTSEnableIntr(uint32_t baseAddr, uint32_t enable);
/**
* \brief This API is used to write End of Interrupt for External TimeStamp
* Counter Overflow Interrupt.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return None.
*/
void MCAN_extTSWriteEOI(uint32_t baseAddr);
/**
* \brief This API returns Number of unserviced rollover/overflow
* interrupts for external TimeStamp counter.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Returns Number of unserviced rollover/overflow
* interrupts for external TimeStamp counter.
* Maximum number of unserviced interrupts is 0xF.
*/
uint32_t MCAN_extTSGetUnservicedIntrCount(uint32_t baseAddr);
/* ========================================================================== */
/* Advance Functions */
/* ========================================================================== */
/**
* \brief This API is check the MCAN base address.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return Returns \b true if base address is valid, otherwise \b false
*/
/**
* \brief This API is used get the MCAN revision ID.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param revId Contains Revision ID of MCAN module.
* Refer struct #MCAN_RevisionId.
*
* \return None.
*/
void MCAN_getRevisionId(uint32_t baseAddr, MCAN_RevisionId *revId);
/**
* \brief This API get clock stop acknowledgement for MCAN module.
* It return whether MCAN is power down mode or not.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Return Clock Stop Acknowledgement status.
* Return '1' if M_CAN is set in power down mode else
* returns '0'.
*/
uint32_t MCAN_getClockStopAck(uint32_t baseAddr);
/**
* \brief This API will set External TimeStamp Counter Overflow Interrupt
* Raw status for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return None.
*/
void MCAN_extTSSetRawStatus(uint32_t baseAddr);
/**
* \brief This API will clear External TimeStamp Counter Overflow Interrupt
* raw status for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return None.
*/
void MCAN_extTSClearRawStatus(uint32_t baseAddr);
/**
* \brief This API will return Rx pin state of MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return state MCAN Rx Pin State.
* 0= The CAN bus is dominant
* 1= The CAN bus is recessive
*/
uint32_t MCAN_getRxPinState(uint32_t baseAddr);
/**
* \brief This API will set Tx pin state of MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param state MCAN Tx Pin State.
* 00= Reset value
* 01= Sample Point can be monitored at tx pin
* 10= The CAN bus is dominant
* 11= The CAN bus is recessive
* other= It will treated as 11.
*
* \return None.
*/
void MCAN_setTxPinState(uint32_t baseAddr, uint32_t state);
/**
* \brief This API will return Tx pin state of MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return state MCAN Tx Pin State.
* 00= Reset value
* 01= Sample Point can be monitored at tx pin
* 10= The CAN bus is dominant
* 11= The CAN bus is recessive
*/
uint32_t MCAN_getTxPinState(uint32_t baseAddr);
/**
* \brief This API will return current timestamp counter value.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return val Current Timestamp counter value.
*/
uint32_t MCAN_getTSCounterVal(uint32_t baseAddr);
/**
* \brief This API will return clock stop acknowledgement
* for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return ack Clock Stop Acknowledge
* 0= No clock stop acknowledged
* 1= M_CAN may be set in power down
*/
uint32_t MCAN_getClkStopAck(uint32_t baseAddr);
/**
* \brief This API will get the configured bit timings for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param configParams Configuration parameters for MCAN bit timing.
* Refer struct #MCAN_BitTimingParams.
*
* \return None.
*/
void MCAN_getBitTime(uint32_t baseAddr,
MCAN_BitTimingParams *configParams);
/**
* \brief This API will reset timestamp counter value.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return None.
*/
void MCAN_resetTSCounter(uint32_t baseAddr);
/**
* \brief This API will return current time-out counter value.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return val Current Time-out counter value.
*/
uint32_t MCAN_getTOCounterVal(uint32_t baseAddr);
/**
* \brief This API is used get the ECC AGGR revision ID.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param revId Contains Revision ID of ECC AGGR.
* Refer struct #MCAN_ECCAggrRevisionId.
*
* \return None.
*/
void MCAN_eccAggrGetRevisionId(uint32_t baseAddr,
MCAN_ECCAggrRevisionId *revId);
/**
* \brief This API is used get the ECC Wrapper revision ID.
*
* \param baseAddr Base Address of the MCAN Registers.
* \param revId Contains Revision ID of ECC Wrapper
* Refer struct #MCAN_ECCWrapRevisionId.
*
* \return None.
*/
void MCAN_eccWrapGetRevisionId(uint32_t baseAddr,
MCAN_ECCWrapRevisionId *revId);
/**
* \brief This API returns External TimeStamp Counter Overflow Interrupt
* enable status for MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return status Returns TRUE if External TimeStamp Counter Overflow
* Interrupt is enabled.
* Else returns FALSE.
*/
uint32_t MCAN_extTSIsIntrEnable(uint32_t baseAddr);
/**
* \brief This function return endianness value of MCAN module.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \retval val Endianness value. (0x87654321)
*/
uint32_t MCAN_getEndianVal(uint32_t baseAddr);
/**
* \brief This API will get the configured Extended ID AND Mask.
*
* \param baseAddr Base Address of the MCAN Registers.
*
* \return idMask Extended ID AND Mask.
*/
uint32_t MCAN_getExtIDANDMask(uint32_t baseAddr);
/**
* \brief This API will return message object size.
*
* \param elemSize Element Size.
*
* \return message object size
* Size of the message object stored in Message RAM.
*/
uint32_t MCAN_getMsgObjSize(uint32_t elemSize);
// Close the Doxygen group.
//! @}
//###########################################################################
//
// FILE: memcfg.h
//
// TITLE: C28x RAM config driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup memcfg_api MemCfg
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_memcfg.h
//
// TITLE: Definitions for the MEMCFG registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the MEMCFG register offsets
//
//*************************************************************************************************
// Register
// Register
// Clear Register
// Interrupt Enable Register
// Address
// Violation Address
// Violation Address
// Violation Address
// Violation Address
// Violation Address
// Violation Address
// Address
// Register
// Register
// Register
// Enable Register
// Address
// Address
// Address
// Access Violation Address
// Address
// Violation Address
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxCOMMIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxACCPROT0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxTEST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxINIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxINITDONE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxRAMTEST_LOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxCOMMIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxMSEL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxCLAPGM register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxACCPROT0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxACCPROT1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxTEST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxINIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxINITDONE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxRAMTEST_LOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxCOMMIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxACCPROT0 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxTEST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxINIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxINITDONE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxRAMTEST_LOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxLOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxCOMMIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxTEST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxINIT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxINITDONE register
//
//*************************************************************************************************
// MSG RAM
// MSG RAM
// MSG RAM
// MSG RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxRAMTEST_LOCK register
//
//*************************************************************************************************
// Configuration
// Configuration
// Configuration
// Configuration
//*************************************************************************************************
//
// The following are defines for the bit fields in the ROM_LOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ROM_TEST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the ROM_FORCE_ERROR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVINTEN register
//
//*************************************************************************************************
// Enable
// Enable
// Enable
// Enable
// Enable
// Enable
// Enable
// Enable
// Enable
// Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVINTEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRTHRES register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTSET register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CPU_RAM_TEST_ERROR_STS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the CPU_RAM_TEST_ERROR_STS_CLR register
//
//*************************************************************************************************
//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************
//
// Masks to decode memory section defines.
//
//
// Used for access violation functions.
//
//
// Key for writing to memory test config lock registers
//
//*****************************************************************************
//
// Values that can be passed to MemCfg_lockConfig(), MemCfg_unlockConfig(),
// MemCfg_commitConfig(), MemCfg_setProtection(), MemCfg_initSections(),
// MemCfg_setCLAMemType(), MemCfg_setLSRAMControllerSel(),
// MemCfg_getInitStatus() as the memSection(s) or ramSection(s) parameter.
//
//*****************************************************************************
//
// DxRAM - Dedicated RAM config
//
//
// LSxRAM - Local shared RAM config
//
//
// GSxRAM - Global shared RAM config
//
//
// MSGxRAM - Message RAM config
//
//
// ROM memory sections
//
//
// All sections
//
//*****************************************************************************
//
// Values that can be passed to MemCfg_setProtection() as the protectMode
// parameter.
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to MemCfg_enableViolationInterrupt()
// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(),
// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as
// the intFlags parameter. They also make up the return value of
// MemCfg_getViolationInterruptStatus().
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to MemCfg_enableViolationInterrupt()
// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(),
// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as
// the intFlags parameter. They also make up the return value of
// MemCfg_getViolationInterruptStatus().
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to MemCfg_forceCorrErrorStatus(),
// MemCfg_clearCorrErrorStatus(), and MemCfg_getCorrErrorAddress() as the
// stsFlag(s) parameter and returned by MemCfg_getCorrErrorStatus().
//
// Note that MEMCFG_CERR_CPUREAD is the only value below that has a
// corresponding interrupt and may be used with the error functions that take
// an intFlag(s) parameter.
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to MemCfg_forceUncorrErrorStatus(),
// MemCfg_clearUncorrErrorStatus(), and MemCfg_getUncorrErrorAddress() as the
// stsFlag(s) parameter and returned by MemCfg_getUncorrErrorStatus().
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to MemCfg_clearDiagErrorStatus() as stsFlags
// parameter and returned by MemCfg_getDiagErrorStatus().
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to MemCfg_setCLAMemType() as the \e claMemType
//! parameter.
//
//*****************************************************************************
typedef enum
{
MEMCFG_CLA_MEM_DATA, //!< Section is CLA data memory
MEMCFG_CLA_MEM_PROGRAM //!< Section is CLA program memory
} MemCfg_CLAMemoryType;
//*****************************************************************************
//
//! Values that can be passed to MemCfg_setLSRAMControllerSel() as the
//! \e controllerSel parameter.
//
//*****************************************************************************
typedef enum
{
MEMCFG_LSRAMCONTROLLER_CPU_ONLY, //!< CPU is the owner of the section
MEMCFG_LSRAMCONTROLLER_CPU_CLA1 //!< CPU and CLA1 share this section
} MemCfg_LSRAMControllerSel;
//*****************************************************************************
//
//! Values that can be passed to MemCfg_setTestMode() as the \e testMode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! Functional mode. Test mode is disabled.
MEMCFG_TEST_FUNCTIONAL = 0,
//! Writes allowed to data only
MEMCFG_TEST_WRITE_DATA = 1,
//! Writes allowed to ECC only (for DxRAM/MxRAM)
MEMCFG_TEST_WRITE_ECC = 2,
//! Writes allowed to parity only (for LSxRAM, GSxRAM, and MSGxRAM)
MEMCFG_TEST_WRITE_PARITY = 2,
//! Diagnostic mode, similar to functional mode but NMI is not generated.
MEMCFG_TEST_FUNC_DIAG = 3
} MemCfg_TestMode;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the CLA memory type of the specified RAM section.
//!
//! \param ramSections is the logical OR of the sections to be configured.
//! \param claMemType indicates data memory or program memory.
//!
//! This function sets the CLA memory type configuration of the RAM section. If
//! the \e claMemType parameter is \b MEMCFG_CLA_MEM_DATA, the RAM section will
//! be configured as CLA data memory. If \b MEMCFG_CLA_MEM_PROGRAM, the RAM
//! section will be configured as CLA program memory.
//!
//! The \e ramSections parameter is an OR of the following indicators:
//! \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx.
//!
//! \note This API only applies to LSx RAM and has no effect if the CLA isn't
//! controller of the memory section.
//!
//! \sa MemCfg_setLSRAControllerSel()
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_setCLAMemType(uint32_t ramSections, MemCfg_CLAMemoryType claMemType)
{
//
// Check the arguments.
//
;
//
// Write the CLA memory configuration to the appropriate register. Either
// set or clear the bit that determines the function of the RAM section as
// it relates to the CLA.
//
__eallow();
if(claMemType == MEMCFG_CLA_MEM_PROGRAM)
{
//
// Program memory
//
(*((volatile uint32_t *)(0x0005F400U + 0x26U))) |= ramSections;
}
else
{
//
// Data memory
//
(*((volatile uint32_t *)(0x0005F400U + 0x26U))) &= ~ramSections;
}
__edis();
}
//*****************************************************************************
//
//! Enables individual RAM access violation interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//! Can be a logical OR any of the following values:
//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access
//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access
//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access
//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access
//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access
//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access
//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access
//! - \b MEMCFG_NMVIOL_DMAREAD - Non-controller DMA read access
//! - \b MEMCFG_NMVIOL_HICREAD - Non-controller HIC read access
//! - \b MEMCFG_NMVIOL_HICWRITE - Non-controller HIC write access
//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access
//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access
//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access
//! - \b MEMCFG_MVIOL_HICWRITE - Controller HIC write access
//! This function enables the indicated RAM access violation interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_enableViolationInterrupt(uint32_t intFlags)
{
//
// Enable the specified interrupts.
//
__eallow();
(*((volatile uint32_t *)(0x0005F500U + 0x6U))) |=
intFlags & 0x0000FFFFU;
(*((volatile uint32_t *)(0x0005F500U + 0x26U))) |=
(intFlags & 0x000F0000U) >> 16U;
__edis();
}
//*****************************************************************************
//
//! Disables individual RAM access violation interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be disabled.
//! Can be a logical OR any of the following values:
//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access
//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access
//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access
//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access
//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access
//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access
//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access
//! - \b MEMCFG_NMVIOL_DMAREAD - Non-controller DMA read access
//! - \b MEMCFG_NMVIOL_HICREAD - Non-controller HIC read access
//! - \b MEMCFG_NMVIOL_HICWRITE - Non-controller HIC write access
//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access
//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access
//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access
//! - \b MEMCFG_MVIOL_HICWRITE - Controller HIC write access
//!
//! This function disables the indicated RAM access violation interrupt
//! sources. Only the sources that are enabled can be reflected to the
//! processor interrupt; disabled sources have no effect on the processor.
//!
//! \note Note that only non-controller violations may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_disableViolationInterrupt(uint32_t intFlags)
{
//
// Disable the specified interrupts.
//
__eallow();
(*((volatile uint32_t *)(0x0005F500U + 0x6U))) &=
~(intFlags & 0x0000FFFFU);
(*((volatile uint32_t *)(0x0005F500U + 0x26U))) &=
~((intFlags & 0x000F0000U) >> 16U);
__edis();
}
//*****************************************************************************
//
//! Gets the current RAM access violation status.
//!
//! This function returns the RAM access violation status. This function will
//! return flags for both controller and non-controller access violations
//! although only the non-controller flags have the ability to cause the
//! generation of an interrupt.
//!
//! \return Returns the current violation status, enumerated as a bit field of
//! the values:
//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access
//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access
//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access
//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access
//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access
//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access
//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access
//! - \b MEMCFG_NMVIOL_DMAREAD - Non-controller DMA read access
//! - \b MEMCFG_NMVIOL_HICREAD - Non-controller HIC read access
//! - \b MEMCFG_NMVIOL_HICWRITE - Non-controller HIC write access
//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access
//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access
//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access
//! - \b MEMCFG_MVIOL_HICWRITE - Controller HIC write access
//*****************************************************************************
static inline uint32_t
MemCfg_getViolationInterruptStatus(void)
{
uint32_t status;
//
// Read and return RAM access status flags.
//
status = ((*((volatile uint32_t *)(0x0005F500U + 0x0U)))) |
((*((volatile uint32_t *)(0x0005F500U + 0x20U))) <<
16U);
return(status);
}
//*****************************************************************************
//
//! Sets the RAM access violation status.
//!
//! \param intFlags is a bit mask of the access violation flags to be set.
//! Can be a logical OR any of the following values:
//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access
//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access
//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access
//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access
//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access
//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access
//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access
//! - \b MEMCFG_NMVIOL_DMAREAD - Non-controller DMA read access
//! - \b MEMCFG_NMVIOL_HICREAD - Non-controller HIC read access
//! - \b MEMCFG_NMVIOL_HICWRITE - Non-controller HIC write access
//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access
//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access
//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access
//! - \b MEMCFG_MVIOL_HICWRITE - Controller HIC write access
//!
//! This function sets the RAM access violation status. This function will
//! set flags for both controller and non-controller access violations, and an
//! interrupt will be generated if it is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceViolationInterrupt(uint32_t intFlags)
{
//
// Shift and mask the flags appropriately and write them to the
// corresponding SET register.
//
__eallow();
(*((volatile uint32_t *)(0x0005F500U + 0x2U))) =
intFlags & 0x0000FFFFU;
(*((volatile uint32_t *)(0x0005F500U + 0x22U))) =
(intFlags & 0x000F0000U) >> 16U;
__edis();
}
//*****************************************************************************
//
//! Clears RAM access violation flags.
//!
//! \param intFlags is a bit mask of the access violation flags to be cleared.
//! Can be a logical OR any of the following values:
//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access
//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access
//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access
//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access
//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access
//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access
//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access
//! - \b MEMCFG_NMVIOL_DMAREAD - Non-controller DMA read access
//! - \b MEMCFG_NMVIOL_HICREAD - Non-controller HIC read access
//! - \b MEMCFG_NMVIOL_HICWRITE - Non-controller HIC write access
//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access
//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access
//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access
//! - \b MEMCFG_MVIOL_HICWRITE - Controller HIC write access
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearViolationInterruptStatus(uint32_t intFlags)
{
//
// Clear the requested access violation flags.
//
__eallow();
(*((volatile uint32_t *)(0x0005F500U + 0x4U))) |=
intFlags & 0x0000FFFFU;
(*((volatile uint32_t *)(0x0005F500U + 0x24U))) |=
(intFlags & 0x000F0000U) >> 16U;
__edis();
}
//*****************************************************************************
//
//! Sets the correctable error threshold value.
//!
//! \param threshold is the correctable error threshold.
//!
//! This value sets the error-count threshold at which a correctable error
//! interrupt is generated. That is when the error count register reaches the
//! value specified by the \e threshold parameter, an interrupt is
//! generated if it is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_setCorrErrorThreshold(uint32_t threshold)
{
//
// Write the threshold value to the appropriate register.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x30U))) = threshold;
__edis();
}
//*****************************************************************************
//
//! Gets the correctable error count.
//!
//! \return Returns the number of correctable error have occurred.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getCorrErrorCount(void)
{
//
// Read and return the number of errors that have occurred.
//
return((*((volatile uint32_t *)(0x0005F540U + 0x2EU))));
}
//*****************************************************************************
//
//! Enables individual RAM correctable error interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be enabled. Can
//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function enables the indicated RAM correctable error interrupt
//! sources. Only the sources that are enabled can be reflected to the
//! processor interrupt; disabled sources have no effect on the processor.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_enableCorrErrorInterrupt(uint32_t intFlags)
{
//
// Enable the specified interrupts.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x38U))) |= intFlags;
__edis();
}
//*****************************************************************************
//
//! Disables individual RAM correctable error interrupt sources.
//!
//! \param intFlags is a bit mask of the interrupt sources to be disabled. Can
//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function disables the indicated RAM correctable error interrupt
//! sources. Only the sources that are enabled can be reflected to the
//! processor interrupt; disabled sources have no effect on the processor.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_disableCorrErrorInterrupt(uint32_t intFlags)
{
//
// Disable the specified interrupts.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x38U))) &= ~(intFlags);
__edis();
}
//*****************************************************************************
//
//! Gets the current RAM correctable error interrupt status.
//!
//! \return Returns the current error interrupt status. Will return a value of
//! \b MEMCFG_CERR_CPUREAD if an interrupt has been generated. If not, the
//! function will return 0.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getCorrErrorInterruptStatus(void)
{
//
// Read and return correctable error interrupt flags.
//
return((*((volatile uint32_t *)(0x0005F540U + 0x32U))));
}
//*****************************************************************************
//
//! Sets the RAM correctable error interrupt status.
//!
//! \param intFlags is a bit mask of the interrupt sources to be set. Can take
//! the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function sets the correctable error interrupt flag.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceCorrErrorInterrupt(uint32_t intFlags)
{
//
// Write the flags to the appropriate SET register.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x36U))) = intFlags;
__edis();
}
//*****************************************************************************
//
//! Clears the RAM correctable error interrupt status.
//!
//! \param intFlags is a bit mask of the interrupt sources to be cleared. Can
//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved.
//!
//! This function clears the correctable error interrupt flag.
//!
//! \note Note that only correctable errors may generate interrupts.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearCorrErrorInterruptStatus(uint32_t intFlags)
{
//
// Clear the requested flags.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x34U))) |= intFlags;
__edis();
}
//*****************************************************************************
//
//! Gets the current correctable RAM error status.
//!
//! \return Returns the current error status, enumerated as a bit field of
//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ
//
//*****************************************************************************
static inline uint32_t
MemCfg_getCorrErrorStatus(void)
{
//
// Read and return RAM error status flags.
//
return((*((volatile uint32_t *)(0x0005F540U + 0x20U))));
}
//*****************************************************************************
//
//! Gets the current uncorrectable RAM error status.
//!
//! \return Returns the current error status, enumerated as a bit field of
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ
//! or \b MEMCFG_UCERR_HICREAD.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getUncorrErrorStatus(void)
{
//
// Read and return RAM error status flags.
//
return((*((volatile uint32_t *)(0x0005F540U + 0x0U))));
}
//*****************************************************************************
//
//! Sets the specified correctable RAM error status flag.
//!
//! \param stsFlags is a bit mask of the error sources. This parameter can be
//! any of the following values:
//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ
//!
//! This function sets the specified correctable RAM error status flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceCorrErrorStatus(uint32_t stsFlags)
{
//
// Write the flags to the appropriate SET register.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x22U))) = stsFlags;
__edis();
}
//*****************************************************************************
//
//! Sets the specified uncorrectable RAM error status flag.
//!
//! \param stsFlags is a bit mask of the error sources. This parameter can be
//! any of the following values:
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ
//! or \b MEMCFG_UCERR_HICREAD.
//!
//! This function sets the specified uncorrectable RAM error status flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_forceUncorrErrorStatus(uint32_t stsFlags)
{
//
// Write the flags to the appropriate SET register.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x2U))) = stsFlags;
__edis();
}
//*****************************************************************************
//
//! Clears correctable RAM error flags.
//!
//! \param stsFlags is a bit mask of the status flags to be cleared.
//! This parameter can be any of the following :
//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ
//!
//! This function clears the specified correctable RAM error flags.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearCorrErrorStatus(uint32_t stsFlags)
{
//
// Clear the requested flags.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x24U))) |= stsFlags;
__edis();
}
//*****************************************************************************
//
//! Clears uncorrectable RAM error flags.
//!
//! \param stsFlags is a bit mask of the status flags to be cleared.
//! This parameter can be any of the following :
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ
//! or \b MEMCFG_UCERR_HICREAD.
//!
//! This function clears the specified uncorrectable RAM error flags.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearUncorrErrorStatus(uint32_t stsFlags)
{
//
// Clear the requested flags.
//
__eallow();
(*((volatile uint32_t *)(0x0005F540U + 0x4U))) |= stsFlags;
__edis();
}
//*****************************************************************************
//
//! Gets the diagnostics corr/uncorr memory error status in test mode.
//!
//! \return Returns the diagnostics error status in test mode. It can return
//! following values: \b MEMCFG_DIAGERR_UNCORR, and/or \b MEMCFG_DIAGERR_CORR.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getDiagErrorStatus(void)
{
//
// Returns diag error status.
//
return((*((volatile uint32_t *)(0x0005F590U + 0x0U))));
}
//*****************************************************************************
//
//! Clears the diagnostics corr/uncorr memory error status.
//!
//! \param stsFlags is a bit mask of the status flags to be cleared.
//!
//! This function clears the specified diagnostics corr/uncorr RAM/ROM memory
//! error flags in test mode. The param \e stsFlags can be any of the following
//! values: \b MEMCFG_DIAGERR_UNCORR, and/or \b MEMCFG_DIAGERR_CORR.
//!
//! \return None.
//
//*****************************************************************************
static inline void
MemCfg_clearDiagErrorStatus(uint32_t stsFlags)
{
//
// Clear diag error status.
//
(*((volatile uint32_t *)(0x0005F590U + 0x2U))) |= stsFlags;
}
//*****************************************************************************
//
//! Gets address location of diagnostics corr/uncorr memory read/write error.
//!
//! \return Return address location of diagnostics corr/uncorr memory error
//! error in test mode.
//
//*****************************************************************************
static inline uint32_t
MemCfg_getDiagErrorAddress(void)
{
//
// Return diag error address.
//
return((*((volatile uint32_t *)(0x0005F590U + 0x4U))));
}
//*****************************************************************************
//
//! Locks the writes to the configuration of specified memory sections.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function locks writes to the access protection and controller select
//! configuration of a memory section.That means calling MemCfg_setProtection()
//! or MemCfg_setLSRAMControllerSel() for a locked memory section will have no
//! effect until MemCfg_unlockConfig() is called.
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0 and \b MEMCFG_SECT_M1 or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCLA1TOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//! \b MEMCFG_SECT_MSGX_ALL to configure all message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_lockConfig(uint32_t memSections);
//*****************************************************************************
//
//! Unlocks the writes to the configuration of a memory section.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function unlocks writes to the access protection and controller select
//! configuration of a memory section that has been locked using
//! MemCfg_lockConfig().
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0 and \b MEMCFG_SECT_M1 or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCLA1TOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//! \b MEMCFG_SECT_MSGX_ALL to configure all message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_unlockConfig(uint32_t memSections);
//*****************************************************************************
//
//! Permanently locks writes to the configuration of a memory section.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function permanently locks writes to the access protection and
//! controller select configuration of a memory section. That means calling
//! MemCfg_setProtection() or MemCfg_setLSRAMControllerSel() for a locked memory
//! section will have no effect. To lock the configuration in a nonpermanent
//! way, use MemCfg_lockConfig().
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0 and \b MEMCFG_SECT_M1 or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCLA1TOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//! \b MEMCFG_SECT_MSGX_ALL to configure all message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_commitConfig(uint32_t memSections);
//*****************************************************************************
//
//! Sets the access protection mode of a single memory section.
//!
//! \param memSection is the memory section to be configured.
//! \param protectMode is the logical OR of the settings to be applied.
//!
//! This function sets the access protection mode of a specified memory section.
//! The mode is passed into the \e protectMode parameter as the logical OR of
//! the following values:
//! - \b MEMCFG_PROT_ALLOWCPUFETCH or \b MEMCFG_PROT_BLOCKCPUFETCH - CPU fetch
//! - \b MEMCFG_PROT_ALLOWCPUWRITE or \b MEMCFG_PROT_BLOCKCPUWRITE - CPU write
//! - \b MEMCFG_PROT_ALLOWDMAWRITE or \b MEMCFG_PROT_BLOCKDMAWRITE - DMA write
//! - \b MEMCFG_PROT_ALLOWHICWRITE or \b MEMCFG_PROT_BLOCKHICWRITE - HIC write
//!
//! The \e memSection parameter is one of the following indicators:
//! - \b MEMCFG_SECT_M0 or \b MEMCFG_SECT_M1
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx
//!
//! This function will have no effect if the associated registers have been
//! locked by MemCfg_lockConfig() or MemCfg_commitConfig() or if the memory
//! is configured as CLA program memory.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_setProtection(uint32_t memSection, uint32_t protectMode);
//*****************************************************************************
//
//! Sets the controller of the specified LSxRAM section.
//!
//! \param ramSection is the LSxRAM section to be configured.
//! \param controllerSel is the sharing selection.
//!
//! This function sets the controller select configuration of the LSxRAM
//! section.
//! If the \e controllerSel parameter is \b MEMCFG_LSRAMCONTROLLER_CPU_ONLY,
//! the LSxRAM section passed into the \e ramSection parameter will be dedicated
//! to the CPU. If \b MEMCFG_LSRAMCONTROLLER_CPU_CLA1, the memory section will
//! be shared between the CPU and the CLA.
//!
//! The \e ramSection parameter should be a value from \b MEMCFG_SECT_LS0
//! through \b MEMCFG_SECT_LSx.
//!
//! This function will have no effect if the associated registers have been
//! locked by MemCfg_lockConfig() or MemCfg_commitConfig().
//!
//! \note This API only applies to LSxRAM.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_setLSRAMControllerSel(uint32_t ramSection,
MemCfg_LSRAMControllerSel controllerSel);
//*****************************************************************************
//
//! Locks the writes to the test mode configuration of specified memory
//! sections.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function locks writes to the test mode configuration of a RAM section.
//! That means calling MemCfg_setTestMode() for a locked RAM section will have
//! no effect until MemCfg_unlockTestConfig() is called.
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or use \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or use
//! \b MEMCFG_SECT_LSX_ALL to configure all possible LSRAM sections.
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or use
//! \b MEMCFG_SECT_GSX_ALL to configure all possible GSRAM sections.
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//! \b MEMCFG_SECT_MSGX_ALL to configure all possible message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_lockTestConfig(uint32_t memSections);
//*****************************************************************************
//
//! Unlocks the writes to the test mode configuration of specified memory
//! sections.
//!
//! \param memSections is the logical OR of the sections to be configured.
//!
//! This function unlocks writes to the test mode configuration of a RAM
//! section that has been locked using MemCfg_lockTestConfig().
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or use \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or use
//! \b MEMCFG_SECT_LSX_ALL to configure all possible LSRAM sections.
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or use
//! \b MEMCFG_SECT_GSX_ALL to configure all possible GSRAM sections.
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or use
//! \b MEMCFG_SECT_MSGX_ALL to configure all possible message RAM sections.
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_unlockTestConfig(uint32_t memSections);
//*****************************************************************************
//
//! Sets the test mode of the specified memory section.
//!
//! \param memSection is the memory section to be configured.
//! \param testMode is the test mode selected.
//!
//! This function sets the test mode configuration of the RAM section. The
//! \e testMode parameter can take one of the following values:
//! - \b MEMCFG_TEST_FUNCTIONAL
//! - \b MEMCFG_TEST_WRITE_DATA
//! - \b MEMCFG_TEST_WRITE_ECC
//! - \b MEMCFG_TEST_WRITE_PARITY
//! - \b MEMCFG_TEST_FUNC_DIAG
//!
//! The \e memSection parameter is one of the following indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode);
//*****************************************************************************
//
//! Starts the initialization the specified RAM sections.
//!
//! \param ramSections is the logical OR of the sections to be initialized.
//!
//! This function starts the initialization of the specified RAM sections. Use
//! MemCfg_getInitStatus() to check if the initialization is done.
//!
//! The \e ramSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or
//! \b MEMCFG_SECT_MSGX_ALL
//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_initSections(uint32_t ramSections);
//*****************************************************************************
//
//! Get the status of initialized RAM sections.
//!
//! \param ramSections is the logical OR of the sections to be checked.
//!
//! This function gets the initialization status of the RAM sections specified
//! by the \e ramSections parameter.
//!
//! The \e ramSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, or \b MEMCFG_SECT_DX_ALL
//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL
//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL
//! - \b MEMCFG_SECT_MSGCPUTOCLA1, \b MEMCFG_SECT_MSGCLA1TOCPU,
//! \b MEMCFG_SECT_MSGCLA1TODMA, \b MEMCFG_SECT_MSGDMATOCLA1, or
//! \b MEMCFG_SECT_MSGX_ALL
//! - \b OR use \b MEMCFG_SECT_ALL to get status of all possible sections.
//!
//! \note Use MemCfg_initSections() to start the initialization.
//!
//! \return Returns \b true if all the sections specified by \e ramSections
//! have been initialized and \b false if not.
//
//*****************************************************************************
extern _Bool
MemCfg_getInitStatus(uint32_t ramSections);
//*****************************************************************************
//
//! Get the violation address associated with a intFlag.
//!
//! \param intFlag is the type of access violation as indicated by ONE of
//! these values:
//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access
//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access
//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access
//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access
//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access
//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access
//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access
//! - \b MEMCFG_NMVIOL_DMAREAD - Non-controller DMA read access
//! - \b MEMCFG_NMVIOL_HICREAD - Non-controller HIC read access
//! - \b MEMCFG_NMVIOL_HICWRITE - Non-controller HIC write access
//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access
//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access
//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access
//! - \b MEMCFG_MVIOL_HICWRITE - Controller HIC write access
//!
//! \return Returns the violation address associated with the \e intFlag.
//
//*****************************************************************************
extern uint32_t
MemCfg_getViolationAddress(uint32_t intFlag);
//*****************************************************************************
//
//! Get the correctable error address associated with a stsFlag.
//!
//! \param stsFlag is the type of error to which the returned address will
//! correspond. It can take following values: \b MEMCFG_CERR_CPUREAD,
//! \b MEMCFG_CERR_CLA1READ, \b MEMCFG_CERR_DMAREAD.
//!
//! \return Returns the error address associated with the stsFlag.
//
//*****************************************************************************
extern uint32_t
MemCfg_getCorrErrorAddress(uint32_t stsFlag);
//*****************************************************************************
//
//! Get the uncorrectable error address associated with a stsFlag.
//!
//! \param stsFlag is the type of error to which the returned address will
//! correspond. It may be passed one of these values:
//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, or
//! \b MEMCFG_UCERR_CLA1READ values
//!
//! \return Returns the error address associated with the stsFlag.
//
//*****************************************************************************
extern uint32_t
MemCfg_getUncorrErrorAddress(uint32_t stsFlag);
//*****************************************************************************
//
//! Forces parity error in the selected memory.
//!
//! \param memSections is the logical OR of the sections to be tested.
//!
//! This function forces the parity error in the memories specified
//! by the \e memSections parameter.
//!
//! The \e memSections parameter is an OR of one of the following sets of
//! indicators:
//! - \b MEMCFG_SECT_ROMBOOT, \b MEMCFG_SECT_ROMSECURE ,
//! \b MEMCFG_SECT_ROMCLADATA, \b MEMCFG_SECT_ROM_ALL.
//! - \b OR use \b MEMCFG_SECT_ALL to force parity error in all possible
//! memory sections.
//!
//! \return None.
//
//*****************************************************************************
extern void
MemCfg_forceMemError(uint32_t memSections);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: pin_map.h
//
// TITLE: Definitions of pin mux info for gpio.c.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
// 0x00000003 = MUX register value
// 0x0000000C = GMUX register value
// 0x0000FF00 = Shift amount within mux registers
// 0xFFFF0000 = Offset of MUX register
//*****************************************************************************
//#############################################################################
//
// FILE: pmbus.h
//
// TITLE: C28x PMBUS Driver
//
//#############################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup pmbus_api PMBus
//! @{
//
//
// Defines for the API.
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_pmbus.h
//
// TITLE: Definitions for the PMBUS registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the PMBUS register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBMC register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBACK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBSTS register
//
//*************************************************************************************************
// Data Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBINTM register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBSC register
//
//*************************************************************************************************
// slave.
// Register
// acknowledge
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBHSA register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBCTRL register
//
//*************************************************************************************************
// GPIO Mode
// mode
// GPIO Mode
// GPIO mode
// in GPIO Mode
// GPIO mode
// in GPIO Mode
// GPIO mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBTIMCTL register
//
//*************************************************************************************************
// parameters.
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBTIMCLK register
//
//*************************************************************************************************
// pulse width.
// frequency.
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBTIMSTSETUP register
//
//*************************************************************************************************
// start edge.
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBTIMBIDLE register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBTIMLOWTIMOUT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the PMBTIMHIGHTIMOUT register
//
//*************************************************************************************************
// value
//#############################################################################
//
// FILE: pmbus_common.h
//
// TITLE: C28x PMBUS Driver
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup pmbus_api PMBus
//! @{
//
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
//PMBus Version 1.2 command number constants:
//
//*****************************************************************************
//! PMBus Command PAGE
//! PMBus Command OPERATION
//! PMBus Command ON_OFF_CONFIG
//! PMBus Command CLEAR_FAULTS
//! PMBus Command PHASE
//! PMBus Command PAGE_PLUS_WRITE
//! PMBus Command PAGE_PLUS_READ
// 0x07-0x0F Reserved
//! PMBus Command WRITE_PROTECT
//! PMBus Command STORE_DEFAULT_ALL
//! PMBus Command RESTORE_DEFAULT_ALL
//! PMBus Command STORE_DEFAULT_CODE
//! PMBus Command RESTORE_DEFAULT_CODE
//! PMBus Command STORE_USER_ALL
//! PMBus Command RESTORE_USER_ALL
//! PMBus Command STORE_USER_CODE
//! PMBus Command RESTORE_USER_CODE
//! PMBus Command CAPABILITY
//! PMBus Command QUERY
//! PMBus Command SMBALERT_MASK
// 0x1C - 0x1F Reserved
//! PMBus Command VOUT_MODE
//! PMBus Command VOUT_COMMAND
//! PMBus Command VOUT_TRIM
//! PMBus Command VOUT_CAL_OFFSET
//! PMBus Command VOUT_MAX
//! PMBus Command VOUT_MARGIN_HIGH
//! PMBus Command VOUT_MARGIN_LOW
//! PMBus Command VOUT_TRANSITION_RATE
//! PMBus Command VOUT_DROOP
//! PMBus Command VOUT_SCALE_LOOP
//! PMBus Command VOUT_SCALE_MONITOR
// 0x2B - 0x2F Reserved
//! PMBus Command COEFFICIENTS
//! PMBus Command POUT_MAX
//! PMBus Command MAX_DUTY
//! PMBus Command FREQUENCY_SWITCH
// 0x34 Reserved
//! PMBus Command VIN_ON
//! PMBus Command VIN_OFF
//! PMBus Command INTERLEAVE
//! PMBus Command IOUT_CAL_GAIN
//! PMBus Command IOUT_CAL_OFFSET
//! PMBus Command FAN_CONFIG_1_2
//! PMBus Command FAN_COMMAND_1
//! PMBus Command FAN_COMMAND_2
//! PMBus Command FAN_CONFIG_3_4
//! PMBus Command FAN_COMMAND_3
//! PMBus Command FAN_COMMAND_4
//! PMBus Command VOUT_OV_FAULT_LIMIT
//! PMBus Command VOUT_OV_FAULT_RESPONSE
//! PMBus Command VOUT_OV_WARN_LIMIT
//! PMBus Command VOUT_UV_WARN_LIMIT
//! PMBus Command VOUT_UV_FAULT_LIMIT
//! PMBus Command VOUT_UV_FAULT_RESPONSE
//! PMBus Command IOUT_OC_FAULT_LIMIT
//! PMBus Command IOUT_OC_FAULT_RESPONSE
//! PMBus Command IOUT_OC_LV_FAULT_LIMIT
//! PMBus Command IOUT_OC_LV_FAULT_RESPONSE
//! PMBus Command IOUT_OC_WARN_LIMIT
//! PMBus Command IOUT_UC_FAULT_LIMIT
//! PMBus Command IOUT_UC_FAULT_RESPONSE
// 0x4D – 0x4E Reserved
//! PMBus Command OT_FAULT_LIMIT
//! PMBus Command OT_FAULT_RESPONSE
//! PMBus Command OT_WARN_LIMIT
//! PMBus Command UT_WARN_LIMIT
//! PMBus Command UT_FAULT_LIMIT
//! PMBus Command UT_FAULT_RESPONSE
//! PMBus Command VIN_OV_FAULT_LIMIT
//! PMBus Command VIN_OV_FAULT_RESPONSE
//! PMBus Command VIN_OV_WARN_LIMIT
//! PMBus Command VIN_UV_WARN_LIMIT
//! PMBus Command VIN_UV_FAULT_LIMIT
//! PMBus Command VIN_UV_FAULT_RESPONSE
//! PMBus Command IIN_OC_FAULT_LIMIT (For CBC current limit)
//! PMBus Command IIN_OC_FAULT_RESPONSE
//! PMBus Command IIN_OC_WARN_LIMIT
//! PMBus Command POWER_GOOD_ON
//! PMBus Command POWER_GOOD_OFF
//! PMBus Command TON_DELAY
//! PMBus Command TON_RISE
//! PMBus Command TON_MAX_FAULT_LIMIT
//! PMBus Command TON_MAX_FAULT_RESPONSE
//! PMBus Command TOFF_DELAY
//! PMBus Command TOFF_FALL
//! PMBus Command TOFF_MAX_WARN_LIMIT
// 0x67 Rsvd Deleted PMBus v1.1
//! PMBus Command POUT_OP_FAULT_LIMIT
//! PMBus Command POUT_OP_FAULT_RESPONSE
//! PMBus Command POUT_OP_WARN_LIMIT
//! PMBus Command PIN_OP_WARN_LIMIT
// 0x6C - 0x77 Reserved
//! PMBus Command STATUS_BYTE
//! PMBus Command STATUS_WORD
//! PMBus Command STATUS_VOUT
//! PMBus Command STATUS_IOUT
//! PMBus Command STATUS_INPUT
//! PMBus Command STATUS_TEMPERATURE
//! PMBus Command STATUS_CML
//! PMBus Command STATUS_OTHER
//! PMBus Command STATUS_MFR_SPECIFIC
//! PMBus Command STATUS_FANS_1_2
//! PMBus Command STATUS_FANS_3_4
// 0x83 - 0x85 Reserved
//! PMBus Command READ_EIN
//! PMBus Command READ_EOUT
//! PMBus Command READ_VIN
//! PMBus Command READ_IIN
//! PMBus Command READ_VCAP
//! PMBus Command READ_VOUT
//! PMBus Command READ_IOUT
//! PMBus Command READ_TEMPERATURE_1
//! PMBus Command READ_TEMPERATURE_2
//! PMBus Command READ_TEMPERATURE_3
//! PMBus Command READ_FAN_SPEED_1
//! PMBus Command READ_FAN_SPEED_2
//! PMBus Command READ_FAN_SPEED_3
//! PMBus Command READ_FAN_SPEED_4
//! PMBus Command READ_DUTY_CYCLE
//! PMBus Command READ_FREQUENCY
//! PMBus Command READ_POUT
//! PMBus Command READ_PIN
//! PMBus Command PMBUS_REVISION
//! PMBus Command MFR_ID
//! PMBus Command MFR_MODEL
//! PMBus Command MFR_REVISION
//! PMBus Command MFR_LOCATION
//! PMBus Command MFR_DATE
//! PMBus Command MFR_SERIAL
//! PMBus Command APP_PROFILE_SUPPORT
//! PMBus Command MFR_VIN_MIN
//! PMBus Command MFR_VIN_MAX
//! PMBus Command MFR_IIN_MAX
//! PMBus Command MFR_PIN_MAX
//! PMBus Command MFR_VOUT_MIN
//! PMBus Command MFR_VOUT_MAX
//! PMBus Command MFR_IOUT_MAX
//! PMBus Command MFR_POUT_MAX
//! PMBus Command MFR_TAMBIENT_MAX
//! PMBus Command MFR_TAMBIENT_MIN
//! PMBus Command MFR_EFFICIENCY_LL
//! PMBus Command MFR_EFFICIENCY_HL
//! PMBus Command MFR_PIN_ACURRACY
//! PMBus Command MFR_IC_DEVICE
//! PMBus Command MFR_IC_DEVICE_REV
// 0xAF Reserved
//! PMBus Command USER_DATA_00
//! PMBus Command USER_DATA_01
//! PMBus Command USER_DATA_02
//! PMBus Command USER_DATA_03
//! PMBus Command USER_DATA_04
//! PMBus Command USER_DATA_05
//! PMBus Command USER_DATA_06
//! PMBus Command USER_DATA_07
//! PMBus Command USER_DATA_08
//! PMBus Command USER_DATA_09
//! PMBus Command USER_DATA_10
//! PMBus Command USER_DATA_11
//! PMBus Command USER_DATA_12
//! PMBus Command USER_DATA_13
//! PMBus Command USER_DATA_14
//! PMBus Command USER_DATA_15
//! PMBus Command MFR_MAX_TEMP_1
//! PMBus Command MFR_MAX_TEMP_2
//! PMBus Command MFR_MAX_TEMP_3
// 0xC3-0xCF Reserved
//! PMBus Command MFR_LIGHT_LOAD_ENB
//! PMBus Command MFR_SPECIFIC_01
//! PMBus Command MFR_SPECIFIC_02
//! PMBus Command MFR_SPECIFIC_03
//! PMBus Command MFR_SPECIFIC_04
//! PMBus Command MFR_SPECIFIC_05
//! PMBus Command MFR_SPECIFIC_06
//! PMBus Command MFR_SPECIFIC_07
//! PMBus Command MFR_SPECIFIC_08
//! PMBus Command ROM_MODE
//! PMBus Command USER_RAM_00
//! PMBus Command MFR_PHASE_CONTROL
//! PMBus Command MFR_IOUT_OC_FAULT_LIMIT_LOW
//! PMBus Command MFR_VIN_SCALE
//! PMBus Command MFR_VIN_OFFSET
//! PMBus Command MFR_READ_TEMPERATURE_4
//! PMBus Command MFR_OT_LIMIT_1
//! PMBus Command MFR_OT_LIMIT_2
//! PMBus Command MFR_PARM_INFO
//! PMBus Command MFR_PARM_VALUE
//! PMBus Command MFR_CMDS_DCDC_PAGED
//! PMBus Command MFR_CMDS_DCDC_NONPAGED
//! PMBus Command MFR_CMDS_PFC
//! PMBus Command MFR_SETUP_ID
//! PMBus Command MFR_OT_LIMIT_3
//! PMBus Command MFR_OT_LIMIT_4
//! PMBus Command MFR_DEADBAND_CONFIG
//! PMBus Command MFR_PIN_CAL_A
//! PMBus Command MFR_PIN_CAL_B
//! PMBus Command MFR_PIN_CAL_C
//! PMBus Command MFR_PIN_CAL_D
//! PMBus Command MFR_TEMP_CAL_OFFSET
//! PMBus Command MFR_DEBUG_BUFFER
//! PMBus Command MFR_TEMP_CAL_GAIN
//! PMBus Command MFR_STATUS_BIT_MASK
//! PMBus Command MFR_SPECIFIC_35
//! PMBus Command MFR_SPECIFIC_36
//! PMBus Command MFR_SPECIFIC_37
//! PMBus Command MFR_SPECIFIC_38
//! PMBus Command MFR_SPECIFIC_39
//! PMBus Command MFR_VOUT_CAL_MONITOR
//! PMBus Command ROM_MODE_WITH_PASSWORD
//! PMBus Command MFR_SPECIFIC_42
//! PMBus Command MFR_SPECIFIC_43
//! PMBus Command MFR_SPECIFIC_44
//! PMBus Command MFR_DEVICE_ID
//! PMBus Command MFR_SPECIFIC_COMMAND
//! PMBus Command PMBUS_COMMAND_EXT
//*****************************************************************************
//
//! Transaction Descriptor
//!
//! Defines the transaction type, used in the command object
//! and passed to PMBus_configTransfer()
//
//*****************************************************************************
typedef enum{
PMBUS_TRANSACTION_NONE = 0U, //!< No Transaction
PMBUS_TRANSACTION_QUICKCOMMAND = 1U, //!< Quick Command
PMBUS_TRANSACTION_WRITEBYTE = 2U, //!< Write single byte
PMBUS_TRANSACTION_READBYTE = 3U, //!< Read single byte
PMBUS_TRANSACTION_SENDBYTE = 4U, //!< Send Byte
PMBUS_TRANSACTION_RECEIVEBYTE = 5U, //!< Receive Byte
PMBUS_TRANSACTION_BLOCKWRITE = 6U, //!< Block Write (up to 255 bytes)
PMBUS_TRANSACTION_BLOCKREAD = 7U, //!< Block Read (up to 255 bytes)
PMBUS_TRANSACTION_WRITEWORD = 8U, //!< Write word
PMBUS_TRANSACTION_READWORD = 9U, //!< Read word
PMBUS_TRANSACTION_BLOCKWRPC = 10U //!< Block write, then process call
}PMBus_Transaction;
//! Specifies whether to include the CRC8 table in the
//! library build
//*****************************************************************************
//
// PCBCCR Commands -> used in PMBus_configControlleer()
//
//*****************************************************************************
//! Enable Process call message
//! Enable Group command message
//! Enable PEC byte
//! Enable Extended command
//! Enable Command word
//! Enable read
//*****************************************************************************
//
// PMBINTM Commands -> used in PMBus_enableInterrupt() and
// PMBus_disableInterrupt()
//
//*****************************************************************************
//! Bus Free Interrupt
//! Clock Low Time-out Interrupt
//! Data Ready Interrupt
//! Data Request Interrupt
//! Target Address Ready Interrupt
//! End of Message Interrupt
//! Alert Detection Interrupt
//! Control Detection Interrupt
//! Lost Arbitration Interrupt
//! Clock High Detection Interrupt
//! all PMBus interrupts
//*****************************************************************************
//
// PMBSTS Commands -> returned by PMBus_getInterruptStatus()
//
//*****************************************************************************
//! Bus Free Interrupt
//! Clock Low Time-out Interrupt
//! Data Ready Interrupt
//! Data Request Interrupt
//! Target Address Ready Interrupt
//! End of Message Interrupt
//! Alert Detection Interrupt
//! Control Detection Interrupt
//! Lost Arbitration Interrupt
//! Clock High Detection Interrupt
//*****************************************************************************
//
// PMBSC Commands -> They are used in the configWord passed to
// PMBus_configTarget()
//
//*****************************************************************************
//! Enable manual target ack modes
//! Enable PEC byte processing
//! Transmit PEC at end of transaction
//! Data Request flag generated after
//! receipt of command code, firmware
//! required to issue ACK to continue message
//! any bits cleared in target address mask
//! make that bit a don't care
//! Target will auto acknowledge every
//! received byte
//! Target will auto acknowledge every
//! 2 received bytes
//! Target will auto acknowledge every
//! 3 received bytes
//! Target will auto acknowledge every
//! 4 received bytes
//*****************************************************************************
//
// PMBCTRL Commands
//
//*****************************************************************************
//! Reset control state machines
//! Enable Target Alert
//! Set Clock Low Time-out Interrupt
//! generation on falling edge
//! Set Control Interrupt to be
//! generated on rising edge
//! Enable PMBus Current Source A Control
//! Enable PMBus Current Source B Control
//! Disable Clock Low Time-out
//! Enable PMBus Target Enable
//! Enable PMBus Controller Enable
//*****************************************************************************
//
// PMBUS Module Clock defines
//
//*****************************************************************************
//! Min SYSCLK input to PMBus module
//! Max SYSCLK input to PMBus module
//! Max module frequency of 20 MHz
//! Min module frequency = min_sys_freq / 32
//*****************************************************************************
//
//! Clock Mode Descriptor
//!
//! Used in PMBus_configBusClock() to set up the bus speed. There are two
//! possible modes of operation:
//! -# Standard Mode 100 kHz
//! -# Fast Mode 400 kHz
//
//*****************************************************************************
typedef enum{
PMBUS_CLOCKMODE_STANDARD = 0U, //!< Standard mode 100 kHz
PMBUS_CLOCKMODE_FAST = 1U, //!< Fast Mode 400 kHz
}PMBus_ClockMode;
//*****************************************************************************
//
//! Access Type Descriptor
//!
//! Used in PMBus_getCurrentAccessType() to determine if the device, in target
//! mode, was accessed with read or write enabled.
//
//*****************************************************************************
typedef enum{
PMBUS_ACCESSTYPE_WRITE = 0U, //!< Target last address for write transaction
PMBUS_ACCESSTYPE_READ = 1U //!< Target last address for read transaction
}PMBus_accessType;
//*****************************************************************************
//
//! Interrupt Edge Descriptor
//!
//! Used in PMBus_setCtrlIntEdge() and PMBus_setClkLowTimeoutIntEdge() to set
//! the edge, falling or rising, that triggers an interrupt
//
//*****************************************************************************
typedef enum{
PMBUS_INTEDGE_FALLING = 0U, //!< Interrupt generated on falling edge
PMBUS_INTEDGE_RISING = 1U //!< Interrupt generated on rising edge
}PMBus_intEdge;
//*****************************************************************************
//
// globals
//
//*****************************************************************************
//! CRC table for the polynomial x^8+x^2+x^1+1 or 0x7 (File scope only)
extern const uint16_t PMBus_crc8Table[256U];
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a PMBus base address.
//!
//! \param base is the base address of the PMBus instance used.
//!
//! This function determines if a PMBus module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Disables the PMBus module.
//!
//! \param base is the base address of the PMBus instance used.
//!
//! This function resets the internal state machine of the PMBus module and
//! holds it in that state
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_disableModule(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(base + 0x10U))) |= 0x00000001UL;
__edis();
}
//*****************************************************************************
//
//! Enables the PMBus module.
//!
//! \param base is the base address of the PMBus instance used.
//!
//! This function enables operation of the PMBus module by removing it from the
//! reset state
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_enableModule(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
(*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x00000001UL;
__edis();
}
//*****************************************************************************
//
//! Enables PMBus interrupt sources.
//!
//! \param base is the base address of the PMBus instance used.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated PMBus interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter is the logical OR of any of the following:
//!
//! - \b PMBUS_INT_BUS_FREE - Bus Free Interrupt
//! - \b PMBUS_INT_CLK_LOW_TIMEOUT - Clock Low Time-out Interrupt
//! - \b PMBUS_INT_DATA_READY - Data Ready Interrupt
//! - \b PMBUS_INT_DATA_REQUEST - Data Request Interrupt
//! - \b PMBUS_INT_TARGET_ADDR_READY - Target Address Ready Interrupt
//! - \b PMBUS_INT_EOM - End of Message Interrupt
//! - \b PMBUS_INT_ALERT - Alert Detection Interrupt
//! - \b PMBUS_INT_CONTROL - Control Detection Interrupt
//! - \b PMBUS_INT_LOST_ARB - Lost Arbitration Interrupt
//! - \b PMBUS_INT_CLK_HIGH_DETECT - Clock High Detection Interrupt
//! - \b PMBUS_INT_ALL - all PMBus interrupts
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_enableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
__eallow();
//
// Enable the desired basic interrupts, that is, clear their mask bits
// in PMBINTM
//
(*((volatile uint32_t *)(base + 0xAU))) &= ~(intFlags & 0x03FFU);
__edis();
}
//*****************************************************************************
//
//! Disables PMBus interrupt sources.
//!
//! \param base is the base address of the PMBus instance used.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated PMBus interrupt sources. Only
//! the sources that are enabled can be reflected to the processor interrupt.
//! Disabled sources have no effect on the processor.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to PMBus_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_disableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
;
__eallow();
//
// Disable the desired interrupts
//
(*((volatile uint32_t *)(base + 0xAU))) |= (intFlags & 0x03FFU);
__edis();
}
//*****************************************************************************
//
//! Indicates whether or not the PMBus bus is busy.
//!
//! \param status the value of the status register (PMBUS_O_PMBSTS)
//!
//! This function returns an indication of whether or not the PMBus bus is busy
//!
//! \note The status register is cleared each time it is read, therefore, it
//! should be read once at the beginning of an interrupt service routine using
//! PMBus_getInterruptStatus() and saved to a temporary variable for further
//! processing.
//!
//! \return Returns \b true if the PMBus bus is busy; otherwise, returns
//! \b false.
//
//*****************************************************************************
static inline _Bool PMBus_isBusBusy(uint32_t status)
{
return(((status & 0x2000U) == 0U) ? 1 : 0);
}
//*****************************************************************************
//
//! Indicates whether or not the PEC is valid
//!
//! \param status the value of the status register (PMBUS_O_PMBSTS)
//!
//! This function returns an indication of whether or not the received PEC
//! was valid
//!
//! \note The status register is cleared each time it is read, therefore, it
//! should be read once at the beginning of an interrupt service routine using
//! PMBus_getStatus() and saved to a temporary variable for further
//! processing.
//!
//! \return Returns \b true if the PEC is valid; otherwise, returns
//! \b false.
//
//*****************************************************************************
static inline _Bool PMBus_isPECValid(uint32_t status)
{
return(((status & 0x80U) != 0U) ? 1 : 0);
}
//*****************************************************************************
//
//! Enable I2C mode
//!
//! \param base is the base address of the PMBus instance used.
//!
//! Set the PMBus module to work in I2C mode
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_enableI2CMode(uint32_t base)
{
//
// Locals
//
uint32_t interruptState;
//
// Check the arguments.
//
;
__eallow();
//
// Save off the interrupt state and disable them
//
interruptState = (*((volatile uint32_t *)(base + 0xAU)));
(*((volatile uint32_t *)(base + 0xAU))) = 0x000003FFUL;
//
// Set module to I2C mode
//
(*((volatile uint32_t *)(base + 0x10U))) |= 0x80000000U;
//
// Restore the interrupt status
//
(*((volatile uint32_t *)(base + 0xAU))) = interruptState;
__edis();
}
//*****************************************************************************
//
//! Disable I2C mode
//!
//! \param base is the base address of the PMBus instance used.
//!
//! Set the PMBus module to work in PMBus mode
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_disableI2CMode(uint32_t base)
{
//
// Locals
//
uint32_t interruptState;
//
// Check the arguments.
//
;
__eallow();
//
// Save off the interrupt state and disable them
//
interruptState = (*((volatile uint32_t *)(base + 0xAU)));
(*((volatile uint32_t *)(base + 0xAU))) = 0x000003FFUL;
//
// Set module to PMBUS mode
//
(*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x80000000U;
//
// Restore the interrupt status
//
(*((volatile uint32_t *)(base + 0xAU))) = interruptState;
__edis();
}
//*****************************************************************************
//
//! Read the status register
//!
//! \param base is the base address of the PMBus instance used.
//!
//! \return Contents of the status register.
//
//*****************************************************************************
static inline uint32_t PMBus_getStatus(uint32_t base)
{
//
// Check the arguments.
//
;
return((*((volatile uint32_t *)(base + 0x8U))));
}
//*****************************************************************************
//
//! Acknowledge the transaction by writing to the PMBACK register
//!
//! \param base is the base address of the PMBus instance used.
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_ackTransaction(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Acknowledge
//
(*((volatile uint32_t *)(base + 0x6U))) |= 0x1U;
}
//*****************************************************************************
//
//! Nack the transaction by writing to the PMBACK register
//!
//! \param base is the base address of the PMBus instance used.
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_nackTransaction(uint32_t base)
{
//
// Check the arguments.
//
;
//
// NACK
//
(*((volatile uint32_t *)(base + 0x6U))) &= ~(uint32_t)0x1U;
}
//*****************************************************************************
//
//! Alert the controller by asserting the ALERT line
//!
//! \param base is the base address of the PMBus instance used.
//!
//! A target PMBus can alert the controller by pulling the alert line low.
//! This triggers an Alert Response from the controller`, where the ,controller issues
//! the \b Alert \b Response \b Address on the bus with a read bit and the
//! alerting target is required to reply with its address.
//!
//! \note The alerting device should be in target mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_assertAlertLine(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
//Pull the alert line low
//
(*((volatile uint32_t *)(base + 0x10U))) |= 0x2U;
__edis();
}
//*****************************************************************************
//
//! De-assert the alert line
//!
//! \param base is the base address of the PMBus instance used.
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_deassertAlertLine(uint32_t base)
{
//
// Check the arguments.
//
;
__eallow();
//
//Pull the alert line low
//
(*((volatile uint32_t *)(base + 0x10U))) &= ~(uint32_t)0x2U;
__edis();
}
//*****************************************************************************
//
//! Configure the PMBus operation in Controller Mode.
//!
//! \param base is the base address of the PMBus instance used.
//! \param targetAddress address of the Target device
//! \param byteCount number of bytes transmitted (or read) in the message
//! (up to 255)
//! \param configWord can be a combination of the following
//! -# PMBUS_CONTROLLER_ENABLE_PRC_CALL
//! -# PMBUS_CONTROLLER_ENABLE_GRP_CMD
//! -# PMBUS_CONTROLLER_ENABLE_PEC
//! -# PMBUS_CONTROLLER_ENABLE_EXT_CMD
//! -# PMBUS_CONTROLLER_ENABLE_CMD
//! -# PMBUS_CONTROLLER_ENABLE_READ
//!
//! Assuming the PMBus module is set to Controller mode this function will
//! configure the PMBCCR register. It overwrites the contents of the PMBCCR
//! register.
//! \note
//! -# Writing to the PMBCCR register initiates a message on the bus once
//! the bus is free. In the event of a write the TXBUF must be loaded prior
//! to configuration, or very quickly after configuration, before the module
//! starts the bus clock.
//! -# If the user does not specify an option for example,
//! PMBUS_CONTROLLER_ENABLE_READ, the code will write a 0 (a write) in its
//! bit field.
//! -# setting byteCount to 0U (on a write) triggers a quick command; there
//! is no need to precede this command with the PMBus_putControllerData()
//! -# If transmitting with a non-zero byteCount the user must precede this
//! with the PMBus_putControlllerData(), supplying it with the location of the data
//! and the number of bytes (<= 4). For block transmissions the user will have
//! to call PMBus_putControllerData(), PMBus_configController() and then continue
//! calling PMBus_putControllerData() transmitting 4 (or less for the final
//! transmit) bytes at a time till all the data bytes are transmitted.
//! -# If receiving the user must follow up with the PMBus_getData(),
//! supplying it with the location of an empty buffer and the status byte
//! -# In cases where the controller must transmit for example, process call,
//! the user must call PMBus_putControllerData(), then configure the controlller to
//! transmit the command and two bytes, then call PMBus_getData() to
//! read two bytes from the target. The controller module need not be reconfigured
//! between write and read whenever a repeated start is involved in the
//! transaction
//! \return None.
//
//*****************************************************************************
static inline void PMBus_configController(uint32_t base, uint16_t targetAddress,
uint16_t byteCount, uint32_t configWord)
{
//
// Locals
// Form a bit mask of the bit fields configWord changes
//
const uint32_t bitmask = (0x1U | 0x10000U |
0x20000U | 0x40000U |
0x80000U | 0x100000U);
//
// Check the arguments.
//
;
;
;
__eallow();
//
// Write the user configured bit fields (passed in configWord) as well
// as target address and message byte counts. Writing to PMBMC triggers
// activity on the bus, once the bus is free (PMBSTS.BUS_FREE = 1)
//
(*((volatile uint32_t *)(base + 0x0U))) = ((configWord & bitmask) |
(((uint32_t)targetAddress << 1U) &
0xFEU) |
(((uint32_t)byteCount << 8U) &
0xFF00U));
__edis();
}
//*****************************************************************************
//
//! Get the address that the PMBus module will respond to (in target mode)
//!
//! \param base is the base address of the PMBus instance used.
//!
//! This function will query the PMBUS_O_PMBHTA register, this
//! will be the address of the module when used in Target Mode.
//! \return Address of the PMBus device (in slave mode).
//
//*****************************************************************************
static inline uint16_t PMBus_getOwnAddress(uint32_t base)
{
//
// Check the arguments.
//
;
return(((*((volatile uint32_t *)(base + 0xEU))) & 0xFEU) >> 1U);
}
//*****************************************************************************
//
//! Set the current device address
//!
//! \param base is the base address of the PMBus instance used.
//! \param address : Address to be configured.
//!
//! This function configures the current device address, this
//! will be the own address of the module.
//! \return None.
//
//*****************************************************************************
static inline void PMBus_setOwnAddress(uint32_t base, uint16_t Ownaddress)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Write the address to the PMBSC register (bits 6:0)
//
(*((volatile uint32_t *)(base + 0xCU)))|= Ownaddress;
__edis();
}
//*****************************************************************************
//
//! Set the target address
//!
//! \param base is the base address of the PMBus instance used.
//! \param address : Target Address to be configured.
//!
//! This function configures the current device address, this
//! will be the target address.
//! \return None.
//
//*****************************************************************************
static inline void PMBus_setTargetAddress(uint32_t base, uint16_t targetAddress)
{
//
// Check the arguments.
//
;
;
__eallow();
//
// Write the target address to PMBMC register
//
(*((volatile uint32_t *)(base + 0x0U))) |= (((uint32_t)targetAddress << 1U) &
0xFEU);
__edis();
}
//*****************************************************************************
//
//! Determine the current access (read/write) type
//!
//! \param base is the base address of the PMBus instance used.
//!
//! This function will query the PMBUS_O_PMBHTA register, to determine if
//! the current access type was a read or write access. This bit is relevant
//! only when the PMBus module is addressed as a target.
//!
//! \return an enum of the type PMBus_accessType which specifies if the device,
//! in target mode, was addressed for a read or write operation
//
//*****************************************************************************
static inline PMBus_accessType PMBus_getCurrentAccessType(uint32_t base)
{
//
// Check the arguments.
//
;
return((PMBus_accessType)((*((volatile uint32_t *)(base + 0xEU))) & 0x01U));
}
//*****************************************************************************
//
//! Sets the triggering edge of the Control Interrupt
//!
//! \param base is the base address of the PMBus instance used.
//! \param intEdge interrupt to trigger on rising or falling edge
//!
//! \return None.
//
//*****************************************************************************
static inline void PMBus_setCtrlIntEdge(uint32_t base, PMBus_intEdge intEdge)
{
//
// Check the arguments.
//
;
__eallow();
if(intEdge == PMBUS_INTEDGE_FALLING)
{
//
// Clear bit
//
(*((volatile uint32_t *)(base + 0x10U))) &=
~(uint32_t)0x20U;
}
else // PMBUS_INTEDGE_RISING
{
//
// Set bit
//
(*((volatile uint32_t *)(base + 0x10U))) |= 0x20U;
}
__edis();
}
//*****************************************************************************
//
//! Sets the triggering edge of the Clock Low Time-out Interrupt
//!
//! \param base is the base address of the PMBus instance used.
//! \param intEdge interrupt to trigger on rising or falling edge
//!
//! \return None.
//
//*****************************************************************************
static inline
void PMBus_setClkLowTimeoutIntEdge(uint32_t base, PMBus_intEdge intEdge)
{
//
// Check the arguments.
//
;
__eallow();
if(intEdge == PMBUS_INTEDGE_FALLING)
{
//
// Set bit
//
(*((volatile uint32_t *)(base + 0x10U))) |= 0x4U;
}
else // PMBUS_INTEDGE_RISING
{
//
// Clear bit
//
(*((volatile uint32_t *)(base + 0x10U))) &=
~(uint32_t)0x4U;
}
__edis();
}
//*****************************************************************************
//
//! Initializes the PMBus to Target Mode.
//!
//! \param base is the base address of the PMBus instance used.
//! \param address Target address
//! \param mask Target address mask - Used in address detection, the Target
//! mask enables acknowledgement of multiple device addresses by the Target.
//! Writing a '0' to a bit within the Target mask enables the corresponding bit
//! in the Target address to be either '1' or '0' and still allow for a match.
//! Writing a '0' to all bits in the mask enables the PMBus Interface to
//! acknowledge any device address. Upon power-up, the controller mask defaults to
//! 7Fh, indicating the controller will only acknowledge the address programmed
//! into the Controller Address (Bits 6-0).
//! Set to PMBUS_DISABLE_TARGET_ADDRESS_MASK if you do not wish to have a mask
//!
//! This function sets up the PMBus in target mode and also configures the target
//! address for the PMBus module
//!
//! \return None.
//
//*****************************************************************************
extern
void PMBus_initTargetMode(uint32_t base, uint16_t address, uint16_t mask);
//*****************************************************************************
//
//! Configure the PMBus operation in Target Mode.
//!
//! \param base is the base address of the PMBus instance used.
//! \param configWord can be a combination of the following
//! -# PMBUS_CONTROLLER_ENABLE_MANUAL_ACK
//! -# PMBUS_CONTROLLER_ENABLE_PEC_PROCESSING
//! -# PMBUS_CONTROLLER_ENABLE_MANUAL_CMD_ACK
//! -# PMBUS_CONTROLLER_AUTO_ACK_1_BYTES
//! -# PMBUS_CONTROLLER_AUTO_ACK_2_BYTES
//! -# PMBUS_CONTROLLER_AUTO_ACK_3_BYTES
//! -# PMBUS_CONTROLLER_AUTO_ACK_4_BYTES
//!
//! Assuming the PMBus module is set to target mode, this function will
//! configure the PMBSC register. It overwrites the contents of the PMBSC
//! register, with the exception of the address, target mask, TXPEC and byte
//! count bit fields.
//! \note If the user does not specify an option, for example,
//! PMBUS_TARGET_ENABLE_PEC_PROCESSING, the code will write a 0 (a write) in
//! its bit field.
//!
//! \return None.
//
//*****************************************************************************
extern void PMBus_configTarget(uint32_t base, uint32_t configWord);
//*****************************************************************************
//
//! Gets the current PMBus interrupt status.
//!
//! \param base is the base address of the PMBus instance used.
//!
//! This function returns the interrupt status for the PMBus module.
//!
//! \return The current interrupt status, as a bit field of
//! - \b PMBUS_INTSRC_BUS_FREE
//! - \b PMBUS_INTSRC_CLK_LOW_TIMEOUT
//! - \b PMBUS_INTSRC_DATA_READY
//! - \b PMBUS_INTSRC_DATA_REQUEST
//! - \b PMBUS_INTSRC_TARGET_ADDR_READY
//! - \b PMBUS_INTSRC_EOM
//! - \b PMBUS_INTSRC_ALERT
//! - \b PMBUS_INTSRC_CONTROL
//! - \b PMBUS_INTSRC_LOST_ARB
//! - \b PMBUS_INTSRC_CLK_HIGH_DETECT
//
//*****************************************************************************
extern uint32_t PMBus_getInterruptStatus(uint32_t base);
//*****************************************************************************
//
//! Read the receive buffer (Target or Controller mode)
//!
//! \param base is the base address of the PMBus instance used.
//! \param buffer pointer to the message buffer where the received bytes
//! will be written to
//! \param status the value of the status register (PMBUS_O_PMBSTS)
//!
//! This function can read up to 4 bytes in the receive buffer.
//! \note
//! -# The status register is cleared each time it is read, therefore, it
//! should be read once at the beginning of an interrupt service routine using
//! PMBus_getStatus() and saved to a temporary variable for further
//! processing.
//!
//! -# The buffer should be at least 4 words long; anything smaller will
//! lead to the possibility of memory overrun when a transaction of 4 bytes
//! happens.
//!
//! \return Returns the number of byte(s) received by the PMBus in the
//! array pointed to by buffer.
//
//*****************************************************************************
extern uint16_t
PMBus_getData(uint32_t base, uint16_t *buffer, uint32_t status);
//*****************************************************************************
//
//! write to the transmit buffer (Target mode)
//!
//! \param base is the base address of the PMBus instance used.
//! \param buffer pointer to the message buffer where the transmit bytes
//! are stored
//! \param nBytes number of transmit bytes, up to 4
//! \param txPEC 1 transmit PEC at end of message, 0 no PEC
//!
//! This function can write up to 4 bytes in the transmit buffer.
//!
//! \note
//! -# The user must check the UNIT_BUSY bit before attempting a transmission.
//! -# The buffer should be at least 4 words long; anything smaller will
//! lead to the possibility of memory overrun when a transaction of 4 bytes
//! happens.
//!
//! \return None.
//
//*****************************************************************************
extern void
PMBus_putTargetData(uint32_t base, uint16_t *buffer, uint16_t nBytes,
_Bool txPEC);
//*****************************************************************************
//
//! Manual acknowledgement of the target address
//!
//! \param base is the base address of the PMBus instance used.
//! \param address address of the target
//! \param status the value of the status register (PMBUS_O_PMBSTS)
//! \param buffer pointer to a buffer to store the received data
//!//! This function will read the address that was put on the bus, compare it
//! with address passed to this function and then acknowledge on a match (or
//! nack on mismatch). For this function to work, TARGET_ADDR_READY bit in
//! PBINTM must be enabled. This function checks the TARGET_ADDR_READY bit in
//! the status register before acknowledging so it would be preferable to use
//! this function in an interrupt handler that responds to the TARGET_ADDR_READY
//! interrupt.
//!
//! \note
//! -# The status register is cleared each time it is read, therefore, it
//! should be read once at the beginning of an interrupt service routine using
//! PMBus_getStatus() and saved to a temporary variable for further
//! processing.
//! -# The buffer should be at least 4 words long; anything smaller will
//! lead to the possibility of memory overrun when a transaction of 4 bytes
//! happens.
//!
//! \return None.
//
//*****************************************************************************
extern void PMBus_ackAddress(uint32_t base, uint32_t address, uint32_t status,
uint16_t *buffer);
//*****************************************************************************
//
//! Manual acknowledgement of a command
//!
//! \param base is the base address of the PMBus instance used.
//! \param command command to manually acknowledge - it can be any of the
//! commands listed in this header file. All commands have the common
//! prefix \b PMBUS_CMD.
//! \param status contents of the status register PMBUS_O_PMBSTS
//! \param buffer pointer to a buffer to store the received data
//!
//! This function will read the command that was put on the bus, compare it
//! with command passed to this function and then acknowledge on a match (or
//! nack on mismatch). For this function to work, DATA_READY bit in PBINTM
//! must be enabled. This function checks the DATA_READY bit in the status
//! register before acknowledging so it would be preferable to use this
//! function in an interrupt handler that responds to the DATA_READY interrupt.
//!
//! \note
//! -# The status register is cleared each time it is read, therefore, it
//! should be read once at the beginning of an interrupt service routine using
//! PMBus_getStatus() and saved to a temporary variable for further
//! processing.
//! -# The buffer should be at least 4 words long; anything smaller will
//! lead to the possibility of memory overrun when a transaction of 4 bytes
//! happens.
//!
//! \return None.
//
//*****************************************************************************
extern void PMBus_ackCommand(uint32_t base, uint32_t command, uint32_t status,
uint16_t *buffer);
//*****************************************************************************
//
//! Generate a CRC table at run time
//!
//! \param crcTable points to the CRC8 Table (must be size 256)
//!
//! This function generates a CRC lookup table to run a CRC on the
//! received data. The table is generated from the polynomial
//! x^8 + x^2 + x^1 + 1 (0x7 - leading 1 is implicit)
//!
//! \return None.
//
//*****************************************************************************
extern void PMBus_generateCRCTable(uint16_t *crcTable);
//*****************************************************************************
//
//! Run a CRC on the received data and check against the
//! received PEC to validate the integrity of the data
//!
//! \param base is the base address of the PMBus instance used.
//! \param buffer points to the received message
//! \param crcTable points to the CRC8 Table
//! \param byteCount size of the message, does not include the PEC byte
//! \param pec is the received PEC to check against
//!
//! This function uses a CRC lookup table to run a CRC on the
//! received data. The table was generated from the polynomial
//! x^8 + x^2 + x^1 + 1 (0x7 - leading 1 is implicit)
//!
//! \note The buffer should be at least 4 words long; anything smaller will
//! lead to the possibility of memory overrun when a transaction of 4 bytes
//! happens.
//!
//! \return \b true if the calculated CRC is equal to the PEC, \b false
//! otherwise.
//
//*****************************************************************************
extern _Bool PMBus_verifyPEC(uint32_t base, uint16_t *buffer,
const uint16_t *crcTable, uint16_t byteCount, uint16_t pec);
//*****************************************************************************
//
//! Initializes the PMBus to Controller Mode.
//!
//! \param base is the base address of the PMBus instance used.
//!
//! This function sets up the PMBus in controller mode.
//!
//! \return None.
//
//*****************************************************************************
extern void PMBus_initControllerMode(uint32_t base);
//*****************************************************************************
//
//! write to the transmit buffer (Controller mode)
//!
//! \param base is the base address of the PMBus instance used.
//! \param buffer pointer to the message buffer where the transmit bytes
//! are stored
//! \param nBytes number of transmit bytes, up to 255
//!
//! This function can write up to 255 bytes in the transmit buffer.
//!
//! \note
//! -# The user must check the UNIT_BUSY bit before attempting the
//! first transmission.
//! -# The buffer should be at least 4 words long; anything smaller will
//! lead to the possibility of memory overrun when a transaction of 4 bytes
//! happens.
//!
//! \return None.
//
//*****************************************************************************
extern void
PMBus_putControllerData(uint32_t base, uint16_t *buffer, uint16_t nBytes);
//*****************************************************************************
//
//! Configure the PMBus module clock
//!
//! \param base is the base address of the PMBus instance used.
//! \param moduleFrequency desired module frequency; can range from
//! PMBUS_MODULE_FREQ_MIN Hz to PMBUS_MODULE_FREQ_MAX Hz. Please input the
//! frequency in Hz, for example, 312500 for 312.4 kHz
//! \param sysFrequency Frequency of the system clock (input to PMBus). The
//! values may range anywhere from PMBUS_SYS_FREQ_MIN Hz to PMBUS_SYS_FREQ_MAX
//! Hz. Please input the frequency in Hz, for example, 100000000 for 100 MHz.
//!
//! The frequency to the PMBus module may not exceed PMBUS_MODULE_FREQ_MAX Hz,
//! the appropriate clock divider is chosen to bring the module clock to the
//! desired frequency - this value is then returned by the function.
//! In the event that the desired bus frequency is unattainable, the clock
//! divider is set to the maximum possible value
//!
//! \return module frequency calculated from the system frequency and clock
//! divider.
//
//*****************************************************************************
extern uint32_t
PMBus_configModuleClock(uint32_t base, uint32_t moduleFrequency,
uint32_t sysFrequency);
//*****************************************************************************
//
//! Configure the bus clock by overriding the default settings
//!
//! \param base is the base address of the PMBus instance used.
//! \param mode is the operating mode for the PMBus, can be
//! - Standard Mode
//! - Fast Mode
//! \param moduleFrequency desired module frequency; can range from
//! PMBUS_MODULE_FREQ_MIN Hz to PMBUS_MODULE_FREQ_MAX Hz. Please input the
//! frequency in Hz, for example, 312500 for 312.4 kHz.
//!
//! The frequency to the PMBus module may not exceed PMBUS_MODULE_FREQ_MAX Hz.
//!
//! \note
//! -# The module comes out of reset with preprogrammed values that allow
//! it to work in standard mode with a module clock of 10MHz. The module clock
//! is set to 10MHz at power cycle, therefore, the user does not have to call
//! this function unless they wish to change the operating frequency of the
//! module clock from the default 10 MHz.
//!
//! \return \b true for successful override, \b false on failure.
//
//*****************************************************************************
extern _Bool
PMBus_configBusClock(uint32_t base, PMBus_ClockMode mode,
uint32_t moduleFrequency);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: sci.h
//
// TITLE: C28x SCI driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup sci_api SCI
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_sci.h
//
// TITLE: Definitions for the SCI registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the SCI register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICCR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICTL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIHBAUD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCILBAUD register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICTL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXST register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXEMU register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXBUF register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCITXBUF register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFTX register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFRX register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFCT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIPRI register
//
//*************************************************************************************************
//*****************************************************************************
//
// Values that can be passed to SCI_enableInterrupt, SCI_disableInterrupt, and
// SCI_clearInterruptStatus as the intFlags parameter, and returned from
// SCI_getInterruptStatus.
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to SCI_setConfig as the config parameter
// and returned by SCI_getConfig in the config parameter.
// Additionally, the SCI_CONFIG_PAR_* enum subset can be passed to
// SCI_setParityMode as the parity parameter, and are returned by
// SCI_getParityMode.
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be used with SCI_setParityMode() and SCI_getParityMode() to
//! describe the parity of the SCI communication.
//
//*****************************************************************************
typedef enum
{
SCI_CONFIG_PAR_NONE = 0x0000U, //!< No parity
SCI_CONFIG_PAR_EVEN = 0x0060U, //!< Even parity
SCI_CONFIG_PAR_ODD = 0x0020U //!< Odd parity
} SCI_ParityType;
//*****************************************************************************
//
//! Values that can be passed to SCI_setFIFOInterruptLevel() as the txLevel
//! parameter and returned by SCI_getFIFOInteruptLevel() and
//! SCI_getTxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
SCI_FIFO_TX0 = 0x0000U, //!< Transmit interrupt empty
SCI_FIFO_TX1 = 0x0001U, //!< Transmit interrupt 1/16 full
SCI_FIFO_TX2 = 0x0002U, //!< Transmit interrupt 2/16 full
SCI_FIFO_TX3 = 0x0003U, //!< Transmit interrupt 3/16 full
SCI_FIFO_TX4 = 0x0004U, //!< Transmit interrupt 4/16 full
SCI_FIFO_TX5 = 0x0005U, //!< Transmit interrupt 5/16 full
SCI_FIFO_TX6 = 0x0006U, //!< Transmit interrupt 6/16 full
SCI_FIFO_TX7 = 0x0007U, //!< Transmit interrupt 7/16 full
SCI_FIFO_TX8 = 0x0008U, //!< Transmit interrupt 8/16 full
SCI_FIFO_TX9 = 0x0009U, //!< Transmit interrupt 9/16 full
SCI_FIFO_TX10 = 0x000AU, //!< Transmit interrupt 10/16 full
SCI_FIFO_TX11 = 0x000BU, //!< Transmit interrupt 11/16 full
SCI_FIFO_TX12 = 0x000CU, //!< Transmit interrupt 12/16 full
SCI_FIFO_TX13 = 0x000DU, //!< Transmit interrupt 13/16 full
SCI_FIFO_TX14 = 0x000EU, //!< Transmit interrupt 14/16 full
SCI_FIFO_TX15 = 0x000FU, //!< Transmit interrupt 15/16 full
SCI_FIFO_TX16 = 0x0010U //!< Transmit interrupt full
} SCI_TxFIFOLevel;
//*****************************************************************************
//
//! Values that can be passed to SCI_setFIFOInterruptLevel() as the rxLevel
//! parameter and returned by SCI_getFIFOInterruptLevel() and
//! SCI_getRxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
SCI_FIFO_RX0 = 0x0000U, //!< Receive interrupt empty
SCI_FIFO_RX1 = 0x0001U, //!< Receive interrupt 1/16 full
SCI_FIFO_RX2 = 0x0002U, //!< Receive interrupt 2/16 full
SCI_FIFO_RX3 = 0x0003U, //!< Receive interrupt 3/16 full
SCI_FIFO_RX4 = 0x0004U, //!< Receive interrupt 4/16 full
SCI_FIFO_RX5 = 0x0005U, //!< Receive interrupt 5/16 full
SCI_FIFO_RX6 = 0x0006U, //!< Receive interrupt 6/16 full
SCI_FIFO_RX7 = 0x0007U, //!< Receive interrupt 7/16 full
SCI_FIFO_RX8 = 0x0008U, //!< Receive interrupt 8/16 full
SCI_FIFO_RX9 = 0x0009U, //!< Receive interrupt 9/16 full
SCI_FIFO_RX10 = 0x000AU, //!< Receive interrupt 10/16 full
SCI_FIFO_RX11 = 0x000BU, //!< Receive interrupt 11/16 full
SCI_FIFO_RX12 = 0x000CU, //!< Receive interrupt 12/16 full
SCI_FIFO_RX13 = 0x000DU, //!< Receive interrupt 13/16 full
SCI_FIFO_RX14 = 0x000EU, //!< Receive interrupt 14/16 full
SCI_FIFO_RX15 = 0x000FU, //!< Receive interrupt 15/16 full
SCI_FIFO_RX16 = 0x0010U //!< Receive interrupt full
} SCI_RxFIFOLevel;
//*****************************************************************************
//
// Values returned from SCI_getRxStatus(). These correspond to the different
// bits and flags of the SCIRXST register.
//
//*****************************************************************************
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a SCI base address.
//!
//! \param base is the base address of the SCI port.
//!
//! This function determines if a SCI port base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets the type of parity.
//!
//! \param base is the base address of the SCI port.
//! \param parity specifies the type of parity to use.
//!
//! Sets the type of parity to use for transmitting and expect when receiving.
//! The \e parity parameter must be one of the following:
//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setParityMode(uint32_t base, SCI_ParityType parity)
{
//
// Check the arguments.
//
;
//
// Set the parity mode.
//
(*((volatile uint16_t *)(base + 0x0U))) = (((*((volatile uint16_t *)(base + 0x0U))) &
~(0x0060U)) | (uint16_t)parity);
}
//*****************************************************************************
//
//! Gets the type of parity currently being used.
//!
//! \param base is the base address of the SCI port.
//!
//! This function gets the type of parity used for transmitting data and
//! expected when receiving data.
//!
//! \return Returns the current parity settings, specified as one of the
//! following:
//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD.
//
//*****************************************************************************
static inline SCI_ParityType
SCI_getParityMode(uint32_t base)
{
uint16_t parity;
//
// Check the arguments.
//
;
//
// Return the current parity setting.
//
parity = ((*((volatile uint16_t *)(base + 0x0U))) & (0x0060U));
return((SCI_ParityType)parity);
}
//*****************************************************************************
//
//! Sets the multiprocessor protocol to address-bit mode.
//!
//! \param base is the base address of the SCI port.
//!
//! This function sets the multi-processor protocol to address-bit mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setAddrMultiProcessorMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the address-bit mode protocol
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x8U;
}
//*****************************************************************************
//
//! Sets the multiprocessor protocol to idle-line mode.
//!
//! \param base is the base address of the SCI port.
//!
//! This function sets the multi-processor protocol to idle-line protocol.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setIdleMultiProcessorMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the address-bit mode protocol
//
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x8U;
}
//*****************************************************************************
//
//! Locks Autobaud.
//!
//! \param base is the base address of the SCI port.
//!
//! This function performs an autobaud lock for the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_lockAutobaud(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Prime the baud register
//
(*((volatile uint16_t *)(base + 0x2U))) = 0x0U;
(*((volatile uint16_t *)(base + 0x3U))) = 0x1U;
//
// Prepare for autobaud detection.
// Set the CDC bit to enable autobaud detection and clear the ABD bit.
//
(*((volatile uint16_t *)(base + 0xCU))) |= 0x2000U;
(*((volatile uint16_t *)(base + 0xCU))) |= 0x4000U;
//
// Wait until we correctly read an 'A' or 'a' and lock
//
while(((*((volatile uint16_t *)(base + 0xCU))) & 0x8000U) != 0x8000U)
{
}
//
// After autobaud lock, clear the ABD and CDC bits
//
(*((volatile uint16_t *)(base + 0xCU))) |= 0x4000U;
(*((volatile uint16_t *)(base + 0xCU))) &= ~0x2000U;
}
//*****************************************************************************
//
//! Sets the FIFO interrupt level at which interrupts are generated.
//!
//! \param base is the base address of the SCI port.
//! \param txLevel is the transmit FIFO interrupt level, specified as one of
//! the following:
//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, . . . or
//! \b SCI_FIFO_TX15.
//! \param rxLevel is the receive FIFO interrupt level, specified as one of
//! the following
//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX15.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel,
SCI_RxFIFOLevel rxLevel)
{
//
// Check the arguments.
//
;
//
// Set the FIFO interrupt levels.
//
(*((volatile uint16_t *)(base + 0xAU))) = ((*((volatile uint16_t *)(base + 0xAU))) &
(~0x1FU)) | (uint16_t)txLevel;
(*((volatile uint16_t *)(base + 0xBU))) = ((*((volatile uint16_t *)(base + 0xBU))) &
(~0x1FU)) | (uint16_t)rxLevel;
}
//*****************************************************************************
//
//! Gets the FIFO interrupt level at which interrupts are generated.
//!
//! \param base is the base address of the SCI port.
//! \param txLevel is a pointer to storage for the transmit FIFO interrupt
//! level, returned as one of the following:
//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, ... or \b SCI_FIFO_TX15.
//! \param rxLevel is a pointer to storage for the receive FIFO interrupt
//! level, returned as one of the following:
//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX15.
//!
//! This function gets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_getFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel *txLevel,
SCI_RxFIFOLevel *rxLevel)
{
//
// Check the arguments.
//
;
//
// Extract the transmit and receive FIFO levels.
//
*txLevel = (SCI_TxFIFOLevel)((*((volatile uint16_t *)(base + 0xAU))) &
0x1FU);
*rxLevel = (SCI_RxFIFOLevel)((*((volatile uint16_t *)(base + 0xBU))) &
0x1FU);
}
//*****************************************************************************
//
//! Gets the current configuration of a SCI.
//!
//! \param base is the base address of the SCI port.
//! \param lspclkHz is the rate of the clock supplied to the SCI module. This
//! is the LSPCLK.
//! \param baud is a pointer to storage for the baud rate.
//! \param config is a pointer to storage for the data format.
//!
//! The baud rate and data format for the SCI is determined, given an
//! explicitly provided peripheral clock (hence the ExpClk suffix). The
//! returned baud rate is the actual baud rate; it may not be the exact baud
//! rate requested or an ``official'' baud rate. The data format returned in
//! \e config is enumerated the same as the \e config parameter of
//! SCI_setConfig().
//!
//! The peripheral clock is the low speed peripheral clock. This will be
//! the value returned by SysCtl_getLowSeedClock(), or it can be explicitly
//! hard coded if it is constant and known (to save the code/execution overhead
//! of a call to SysCtl_getLowSpeedClock()).
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_getConfig(uint32_t base, uint32_t lspclkHz, uint32_t *baud,
uint32_t *config)
{
//
// Check the arguments.
//
;
//
// Compute the baud rate.
//
*baud = lspclkHz /
((1U + (((uint32_t)(*((volatile uint16_t *)(base + 0x2U))) << 8U) |
(*((volatile uint16_t *)(base + 0x3U))))) * 8U);
//
// Get the parity, data length, and number of stop bits.
//
*config = (uint32_t)(*((volatile uint16_t *)(base + 0x0U))) & (0x0060U |
0x0080U |
0x0007U);
}
//*****************************************************************************
//
//! Enables transmitting and receiving.
//!
//! \param base is the base address of the SCI port.
//!
//! Enables SCI by taking SCI out of the software reset. Sets the TXENA, and
//! RXENA bits which enables transmit and receive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable RX, TX, and the SCI.
//
(*((volatile uint16_t *)(base + 0x1U))) |= (0x2U | 0x1U |
0x20U);
}
//*****************************************************************************
//
//! Disables transmitting and receiving.
//!
//! \param base is the base address of the SCI port.
//!
//! Clears the SCIEN, TXE, and RXE bits. The user should ensure that all the
//! data has been sent before disable the module during transmission.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) &= ~(0x4000U);
//
// Disable the SCI.
//
(*((volatile uint16_t *)(base + 0x1U))) &= ~(0x2U | 0x1U);
}
//*****************************************************************************
//
//! Enables transmitting.
//!
//! \param base is the base address of the SCI port.
//!
//! Enables SCI by taking SCI out of the software reset. Sets the TXENA bit
//! which enables transmit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableTxModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable TX and the SCI.
//
(*((volatile uint16_t *)(base + 0x1U))) |= (0x2U | 0x20U);
}
//*****************************************************************************
//
//! Disables transmitting.
//!
//! \param base is the base address of the SCI port.
//!
//! Disables SCI by taking SCI out of the software reset. Clears the TXENA bit
//! which disables transmit.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableTxModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable TX.
//
(*((volatile uint16_t *)(base + 0x1U))) &= ~0x2U;
}
//*****************************************************************************
//
//! Enables receiving.
//!
//! \param base is the base address of the SCI port.
//!
//! Enables SCI by taking SCI out of the software reset. Sets the RXENA bit
//! which enables receive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableRxModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable RX and the SCI.
//
(*((volatile uint16_t *)(base + 0x1U))) |= (0x1U | 0x20U);
}
//*****************************************************************************
//
//! Disables receiving.
//!
//! \param base is the base address of the SCI port.
//!
//! Disables SCI by taking SCI out of the software reset. Clears the RXENA bit
//! which disables receive.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableRxModule(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable RX.
//
(*((volatile uint16_t *)(base + 0x1U))) &= ~0x1U;
}
//*****************************************************************************
//
//! Enables Sleep Mode
//!
//! \param base is the base address of the SCI port.
//!
//! Enables the sleep mode in SCI by setting the SLEEP bit in SCICTL1 register
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableSleepMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set sleep bit
//
(*((volatile uint16_t *)(base + 0x1U))) |= 0x4U;
}
//*****************************************************************************
//
//! Disables Sleep Mode
//!
//! \param base is the base address of the SCI port.
//!
//! Disables the sleep mode in SCI by clearing the SLEEP bit in SCICTL1 register
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableSleepMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear sleep bit
//
(*((volatile uint16_t *)(base + 0x1U))) &= ~0x4U;
}
//*****************************************************************************
//
//! Enables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions enables the transmit and receive FIFOs in the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) |= 0x8000U;
(*((volatile uint16_t *)(base + 0xAU))) |= 0x4000U | 0x2000U;
(*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U;
}
//*****************************************************************************
//
//! Disables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions disables the transmit and receive FIFOs in the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) &= ~0x4000U;
}
//*****************************************************************************
//
//! Determines if the FIFO enhancement is enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns a flag indicating whether or not the FIFO enhancement
//! is enabled.
//!
//! \return Returns \b true if the FIFO enhancement is enabled or \b false
//! if the FIFO enhancement is disabled.
//
//*****************************************************************************
static inline _Bool
SCI_isFIFOEnabled(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return true if the FIFO is enabled and false if it is disabled.
//
return((((*((volatile uint16_t *)(base + 0xAU))) & 0x4000U) ==
0x4000U) ? 1 : 0);
}
//*****************************************************************************
//
//! Resets the receive FIFO.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions resets the receive FIFO of the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_resetRxFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Reset the specified FIFO.
//
(*((volatile uint16_t *)(base + 0xBU))) &= ~0x2000U;
(*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U;
}
//*****************************************************************************
//
//! Resets the transmit FIFO.
//!
//! \param base is the base address of the SCI port.
//!
//! This functions resets the transmit FIFO of the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_resetTxFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Reset the specified FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) &= ~0x2000U;
(*((volatile uint16_t *)(base + 0xAU))) |= 0x2000U;
}
//*****************************************************************************
//
//! Resets the SCI Transmit and Receive Channels
//!
//! \param base is the base address of the SCI port.
//!
//! This functions resets transmit and receive channels in the SCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_resetChannels(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Reset the Tx and Rx Channels
//
(*((volatile uint16_t *)(base + 0xAU))) &= ~0x8000U;
(*((volatile uint16_t *)(base + 0xAU))) |= 0x8000U;
}
//*****************************************************************************
//
//! Determines if there are any characters in the receive buffer when the
//! FIFO enhancement is not enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns a flag indicating whether or not there is data
//! available in the receive buffer.
//!
//! \return Returns \b true if there is data in the receive buffer or \b false
//! if there is no data in the receive buffer.
//
//*****************************************************************************
static inline _Bool
SCI_isDataAvailableNonFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the availability of characters with FIFO disabled.
//
return((((*((volatile uint16_t *)(base + 0x5U))) & 0x40U) ==
0x40U) ? 1 : 0);
}
//*****************************************************************************
//
//! Determines if there is any space in the transmit buffer when the FIFO
//! enhancement is not enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns a flag indicating whether or not there is space
//! available in the transmit buffer when not using the FIFO enhancement.
//!
//! \return Returns \b true if there is space available in the transmit buffer
//! or \b false if there is no space available in the transmit buffer.
//
//*****************************************************************************
static inline _Bool
SCI_isSpaceAvailableNonFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the availability of space.
//
return((((*((volatile uint16_t *)(base + 0x4U))) & 0x80U) ==
0x80U) ? 1 : 0);
}
//*****************************************************************************
//
//! Get the transmit FIFO status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions gets the current number of words in the transmit FIFO.
//!
//! \return Returns the current number of words in the transmit FIFO specified
//! as one of the following:
//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, \b SCI_FIFO_TX3
//! \b SCI_FIFO_TX4, ..., or \b SCI_FIFO_TX16
//
//*****************************************************************************
static inline SCI_TxFIFOLevel
SCI_getTxFIFOStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Get the current FIFO status
//
return((SCI_TxFIFOLevel)(((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) >>
8U));
}
//*****************************************************************************
//
//! Get the receive FIFO status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions gets the current number of words in the receive FIFO.
//!
//! \return Returns the current number of words in the receive FIFO specified
//! as one of the following:
//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, \b SCI_FIFO_RX3
//! \b SCI_FIFO_RX4, ..., or \b SCI_FIFO_RX16
//
//*****************************************************************************
static inline SCI_RxFIFOLevel
SCI_getRxFIFOStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Get the current FIFO status
//
return((SCI_RxFIFOLevel)(((*((volatile uint16_t *)(base + 0xBU))) & 0x1F00U) >>
8U));
}
//*****************************************************************************
//
//! Determines whether the SCI transmitter is busy or not.
//!
//! \param base is the base address of the SCI port.
//!
//! Allows the caller to determine whether all transmitted bytes have cleared
//! the transmitter hardware when the FIFO is not enabled. When the FIFO is
//! enabled, this function allows the caller to determine whether there is any
//! data in the FIFO.
//!
//! Without the FIFO enabled, if \b false is returned, the transmit buffer and
//! shift registers are empty and the transmitter is not busy. With the FIFO
//! enabled, if \b false is returned, the FIFO is empty. This does not
//! necessarily mean that the transmitter is not busy. The empty FIFO does not
//! reflect the status of the transmitter shift register. The FIFO may be empty
//! while the transmitter is still transmitting data.
//!
//! \return Returns \b true if the SCI is transmitting or \b false if
//! transmissions are complete.
//
//*****************************************************************************
static inline _Bool
SCI_isTransmitterBusy(uint32_t base)
{
//
// Check the argument.
//
;
//
// Check if FIFO enhancement is enabled.
//
if(SCI_isFIFOEnabled(base))
{
//
// With FIFO enhancement, determine if the SCI is busy.
//
return((((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) !=
0U) ? 1 : 0);
}
else
{
//
// Without FIFO enhancement, determine if the SCI is busy.
// Check if the transmit buffer and shift register empty.
//
return((((*((volatile uint16_t *)(base + 0x4U))) & 0x40U) ==
0x40U) ? 0 : 1);
}
}
//*****************************************************************************
//
//! Waits to send a character from the specified port when the FIFO enhancement
//! is enabled.
//!
//! \param base is the base address of the SCI port.
//! \param data is the character to be transmitted.
//!
//! Sends the character \e data to the transmit buffer for the specified port.
//! If there is no space available in the transmit FIFO, this function waits
//! until there is space available before returning. \e data is a uint16_t but
//! only 8 bits are written to the SCI port. SCI only transmits 8 bit
//! characters.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
//
// Wait until space is available in the transmit FIFO.
//
while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16)
{
}
//
// Send a char.
//
(*((volatile uint16_t *)(base + 0x9U))) = data;
}
//*****************************************************************************
//
//! Waits to send a character from the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param data is the character to be transmitted.
//!
//! Sends the character \e data to the transmit buffer for the specified port.
//! If there is no space available in the transmit buffer, or the transmit
//! FIFO if it is enabled, this function waits until there is space available
//! before returning. \e data is a uint16_t but only 8 bits are written to the
//! SCI port. SCI only transmits 8 bit characters.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_writeCharBlockingNonFIFO(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
//
// Wait until space is available in the transmit buffer.
//
while(!SCI_isSpaceAvailableNonFIFO(base))
{
}
//
// Send a char.
//
(*((volatile uint16_t *)(base + 0x9U))) = data;
}
//*****************************************************************************
//
//! Sends a character to the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param data is the character to be transmitted.
//!
//! Writes the character \e data to the transmit buffer for the specified port.
//! This function does not block and only writes to the transmit buffer.
//! The user should use SCI_isSpaceAvailableNonFIFO() or SCI_getTxFIFOStatus()
//! to determine if the transmit buffer or FIFO have space available.
//! \e data is a uint16_t but only 8 bits are written to the SCI port. SCI
//! only transmits 8 bit characters.
//!
//! This function replaces the original SCICharNonBlockingPut() API and
//! performs the same actions. A macro is provided in sci.h to map
//! the original API to this API.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_writeCharNonBlocking(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
//
// Send a char.
//
(*((volatile uint16_t *)(base + 0x9U))) = data;
}
//*****************************************************************************
//
//! Gets current receiver status flags.
//!
//! \param base is the base address of the SCI port.
//!
//! This function returns the current receiver status flags. The returned
//! error flags are equivalent to the error bits returned via the previous
//! reading or receiving of a character with the exception that the overrun
//! error is set immediately the overrun occurs rather than when a character
//! is next read.
//!
//! \return Returns a bitwise OR combination of the receiver status flags,
//! \b SCI_RXSTATUS_WAKE, \b SCI_RXSTATUS_PARITY, \b SCI_RXSTATUS_OVERRUN,
//! \b SCI_RXSTATUS_FRAMING, \b SCI_RXSTATUS_BREAK, \b SCI_RXSTATUS_READY,
//! and \b SCI_RXSTATUS_ERROR.
//
//*****************************************************************************
static inline uint16_t
SCI_getRxStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current value of the receive status register.
//
return((*((volatile uint16_t *)(base + 0x5U))));
}
//*****************************************************************************
//
//! Waits for a character from the specified port when the FIFO enhancement
//! is enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! Gets a character from the receive FIFO for the specified port. If there
//! are no characters available, this function waits until a character is
//! received before returning. Returns immediately in case of Error.
//!
//! \return Returns the character read from the specified port as \e uint16_t
//! or 0x0 in case of Error. The application must use
//! SCI_getRxStatus() API to check if some error occurred before
//! consuming the data
//
//*****************************************************************************
static inline uint16_t
SCI_readCharBlockingFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Wait until a character is available in the receive FIFO.
//
while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0)
{
//
//If there is any error return
//
if((SCI_getRxStatus(base) & 0x0080U) != 0U)
{
return(0U);
}
}
//
// Return the character from the receive buffer.
//
return((uint16_t)((*((volatile uint16_t *)(base + 0x7U))) & 0xFFU));
}
//*****************************************************************************
//
//! Waits for a character from the specified port when the FIFO enhancement
//! is not enabled.
//!
//! \param base is the base address of the SCI port.
//!
//! Gets a character from the receive buffer for the specified port. If there
//! is no characters available, this function waits until a character is
//! received before returning.
//!
//! \return Returns the character read from the specified port as \e uint16_t.
//
//*****************************************************************************
static inline uint16_t
SCI_readCharBlockingNonFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Wait until a character is available in the receive FIFO.
//
while(!SCI_isDataAvailableNonFIFO(base))
{
}
//
// Return the character from the receive buffer.
//
return((uint16_t)((*((volatile uint16_t *)(base + 0x7U))) & 0xFFU));
}
//*****************************************************************************
//
//! Receives a character from the specified port.
//!
//! \param base is the base address of the SCI port.
//!
//! Gets a character from the receive buffer for the specified port. This
//! function does not block and only reads the receive buffer. The user should
//! use SCI_isDataAvailableNonFIFO() or SCI_getRxFIFOStatus() to determine if
//! the receive buffer or FIFO have data available.
//!
//! This function replaces the original SCICharNonBlockingGet() API and
//! performs the same actions. A macro is provided in sci.h to map
//! the original API to this API.
//!
//! \return Returns \e uin16_t which is read from the receive buffer.
//
//*****************************************************************************
static inline uint16_t
SCI_readCharNonBlocking(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the character from the receive buffer.
//
return((uint16_t)((*((volatile uint16_t *)(base + 0x7U))) & 0xFFU));
}
//*****************************************************************************
//
//! Performs a software reset of the SCI and Clears all reported receiver
//! status flags.
//!
//! \param base is the base address of the SCI port.
//!
//! This function performs a software reset of the SCI port. It affects the
//! operating flags of the SCI, but it neither affects the configuration bits
//! nor restores the reset values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_performSoftwareReset(uint32_t base)
{
//
// Check the arguments.
//
;
//
// To clear all errors a sw reset of the module is required
//
(*((volatile uint16_t *)(base + 0x1U))) &= ~0x20U;
(*((volatile uint16_t *)(base + 0x1U))) |= 0x20U;
}
//*****************************************************************************
//
//! Enables Loop Back Test Mode
//!
//! \param base is the base address of the SCI port.
//!
//! Enables the loop back test mode where the Tx pin is internally connected
//! to the Rx pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_enableLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the loop back mode.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x10U;
}
//*****************************************************************************
//
//! Disables Loop Back Test Mode
//!
//! \param base is the base address of the SCI port.
//!
//! Disables the loop back test mode where the Tx pin is no longer internally
//! connected to the Rx pin.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_disableLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear the loop back mode.
//
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x10U;
}
//*****************************************************************************
//
//! Get the receive FIFO Overflow flag status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions gets the receive FIFO overflow flag status.
//!
//! \return Returns \b true if overflow has occurred, else returned \b false if
//! an overflow hasn't occurred.
//
//*****************************************************************************
static inline _Bool
SCI_getOverflowStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return the current FIFO overflow status
//
return(((*((volatile uint16_t *)(base + 0xBU))) & 0x8000U) == 0x8000U);
}
//*****************************************************************************
//
//! Clear the receive FIFO Overflow flag status
//!
//! \param base is the base address of the SCI port.
//!
//! This functions clears the receive FIFO overflow flag status.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SCI_clearOverflowStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear the current FIFO overflow status
//
(*((volatile uint16_t *)(base + 0xBU))) |= 0x4000U;
}
//*****************************************************************************
//
//! Sets the configuration of a SCI.
//!
//! \param base is the base address of the SCI port.
//! \param lspclkHz is the rate of the clock supplied to the SCI module. This
//! is the LSPCLK.
//! \param baud is the desired baud rate.
//! \param config is the data format for the port (number of data bits,
//! number of stop bits, and parity).
//!
//! This function configures the SCI for operation in the specified data
//! format. The baud rate is provided in the \e baud parameter and the data
//! format in the \e config parameter.
//!
//! The \e config parameter is the bitwise OR of three values: the number of
//! data bits, the number of stop bits, and the parity. \b SCI_CONFIG_WLEN_8,
//! \b SCI_CONFIG_WLEN_7, \b SCI_CONFIG_WLEN_6, \b SCI_CONFIG_WLEN_5,
//! \b SCI_CONFIG_WLEN_4, \b SCI_CONFIG_WLEN_3, \b SCI_CONFIG_WLEN_2, and
//! \b SCI_CONFIG_WLEN_1. Select from eight to one data bits per byte
//! (respectively).
//! \b SCI_CONFIG_STOP_ONE and \b SCI_CONFIG_STOP_TWO select one or two stop
//! bits (respectively). \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN,
//! \b SCI_CONFIG_PAR_ODD, select the parity mode (no parity bit, even parity
//! bit, odd parity bit respectively).
//!
//! The peripheral clock is the low speed peripheral clock. This will be
//! the value returned by SysCtl_getLowSpeedClock(), or it can be explicitly
//! hard coded if it is constant and known (to save the code/execution overhead
//! of a call to SysCtl_getLowSpeedClock()).
//!
//! A baud rate divider (BRR) is used in this function to calculate the
//! baud rate. The value of BRR is calculated in float and type casted as int
//! to be fed in the \b SCIHBAUD and \b SCILBAUD registers. This conversion
//! brings an error in the calculated baud rate and the requested. Error will
//! be significant when operating at higher baud rates. The error is due to
//! lower BRR integer value granularity at higher baud rates.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud,
uint32_t config);
//*****************************************************************************
//
//! Waits to send an array of characters from the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param array is the address of the array of characters to be transmitted.
//! It is pointer to the array of characters to be transmitted.
//! \param length is the length of the array, or number of characters in the
//! array to be transmitted.
//!
//! Sends the number of characters specified by \e length, starting at the
//! address \e array, out of the transmit buffer for the specified port.
//! If there is no space available in the transmit buffer, or the transmit
//! FIFO if it is enabled, this function waits until there is space available
//! and \e length number of characters are transmitted before returning.
//! \e array is a pointer to uint16_ts but only the least significant 8 bits
//! are written to the SCI port. SCI only transmits 8 bit characters.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_writeCharArray(uint32_t base, const uint16_t * const array,
uint16_t length);
//*****************************************************************************
//
//! Waits to receive an array of characters from the specified port.
//!
//! \param base is the base address of the SCI port.
//! \param array is the address of the array of characters to be received.
//! It is a pointer to the array of characters to be received.
//! \param length is the length of the array, or number of characters in the
//! array to be received.
//!
//! Receives an array of characters from the receive buffer for the specified
//! port, and stores them as an array of characters starting at address
//! \e array. This function waits until the \e length number of characters are
//! received before returning.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length);
//*****************************************************************************
//
//! Enables individual SCI interrupt sources.
//!
//! \param base is the base address of the SCI port.
//! \param intFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SCI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The \e intFlags parameter is the bitwise OR of any of the following:
//!
//! - \b SCI_INT_RXERR - RXERR Interrupt
//! - \b SCI_INT_RXRDY_BRKDT - RXRDY/BRKDT Interrupt
//! - \b SCI_INT_TXRDY - TXRDY Interrupt
//! - \b SCI_INT_TXFF - TX FIFO Level Interrupt
//! - \b SCI_INT_RXFF - RX FIFO Level Interrupt
//! - \b SCI_INT_FE - Frame Error
//! - \b SCI_INT_OE - Overrun Error
//! - \b SCI_INT_PE - Parity Error
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_enableInterrupt(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Disables individual SCI interrupt sources.
//!
//! \param base is the base address of the SCI port.
//! \param intFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SCI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to SCI_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_disableInterrupt(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param base is the base address of the SCI port.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in SCI_enableInterrupt().
//
//*****************************************************************************
extern uint32_t
SCI_getInterruptStatus(uint32_t base);
//*****************************************************************************
//
//! Clears SCI interrupt sources.
//!
//! \param base is the base address of the SCI port.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SCI interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//!
//! The \e intFlags parameter has the same definition as the \e intFlags
//! parameter to SCI_enableInterrupt().
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Sets SCI Baud rate.
//!
//! \param base is the base address of the SCI port.
//! \param lspclkHz is the rate of the clock supplied to the SCI module. This
//! is the LSPCLK.
//! \param baud is the desired baud rate.
//!
//! This function configures the SCI for operation in the specified baud rate
//! The baud rate is provided in the \e baud parameter.
//!
//! The peripheral clock is the low speed peripheral clock. This will be
//! the value returned by SysCtl_getLowSpeedClock()
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud);
//*****************************************************************************
//
//! Sets the SCI TXWAKE flag
//!
//! \param base is the base address of the SCI port.
//!
//! This function sets the TXWAKE flag bit to indicate that the next frame
//! is an address frame.
//! TXWAKE bit controls selection of data-transmit feature based on
//! which mode is selected from idle-line and address-bit.
//!
//! \return None.
//
//*****************************************************************************
extern void
SCI_setWakeFlag(uint32_t base);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: sdfm.h
//
// TITLE: C28x SDFM Driver
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup sdfm_api SDFM
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_sdfm.h
//
// TITLE: Definitions for the SDFM registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the SDFM register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDIFLG register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDIFLGCLR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDMFILEN register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSTATUS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPH1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA1 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO1 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPH2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPHZ register
//
//*************************************************************************************************
// output
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT1CMPL2 register
//
//*************************************************************************************************
// output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPH1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA2 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO2 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPH2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPHZ register
//
//*************************************************************************************************
// output
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT2CMPL2 register
//
//*************************************************************************************************
// output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPH1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA3 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO3 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPH2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPHZ register
//
//*************************************************************************************************
// output
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC3 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT3CMPL2 register
//
//*************************************************************************************************
// output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPH1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPL1 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA4 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATFIFO4 register
//
//*************************************************************************************************
// mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPH2 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPHZ register
//
//*************************************************************************************************
// output
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFIFOCTL4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDSYNC4 register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDFLT4CMPL2 register
//
//*************************************************************************************************
// output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1CTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT2FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT2FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT1FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1EVT1FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP1LOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2CTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT2FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT2FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT1FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2EVT1FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP2LOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3CTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT2FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT2FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT1FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3EVT1FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP3LOCK register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4CTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT2FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT2FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT1FLTCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4EVT1FLTCLKCTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCOMP4LOCK register
//
//*************************************************************************************************
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//! Macro to get the low threshold
//!
//! Macro to get the high threshold
//!
//! Macro to get the high threshold 1 & 2 to be passed as lowThreshold
//! parameter to SDFM_setCompFilterLowThreshold().
//!
//! Macro to get the high threshold 1 & 2 to be passed as highThreshold
//! parameter to SDFM_setCompFilterHighThreshold().
//!
//! Macro to convert comparator over sampling ratio to acceptable bit location
//!
//! Macro to convert the data shift bit values to acceptable bit location
//!
//! Macro to combine high threshold and low threshold values
//!
//! Macro to set the FIFO level to acceptable bit location
//!
//! Macro to set and enable the zero cross threshold value.
//!
//! Macros to enable or disable filter.
//!
//*****************************************************************************
//
// Defines for SDFM register offsets. Added for internal use. Not to be used by
// application.
//
//*****************************************************************************
//!< SD filter offset
//!< Event Digital filter offset
//!< Offset between high threshold 1 & 2 registers
//!< Offset between low threshold 1 & 2 registers
//*****************************************************************************
//
// Define to mask out the bits in the SDCOMPHFILCTL register that aren't
// associated with comparator event filter configurations. Added for internal
// use, not to be used in application code.
//
//*****************************************************************************
//*****************************************************************************
//
// Define to mask out the bits in the SDCOMPLOCK register that aren't
// associated with lock configuration. Added for internal use, not to be used
// in application code.
//
//*****************************************************************************
//*****************************************************************************
//
// Values that can be passed to SDFM_enableSynchronizer() or
// SDFM_disableSynchronizer() as syncConfig parameter.
//
//*****************************************************************************
//! Define for Clock synchronizer Configuration
//! Define for Data Synchronizer Configuration
//*****************************************************************************
//
//! Values that can be returned from SDFM_getThresholdStatus()
//
//*****************************************************************************
typedef enum
{
SDFM_OUTPUT_WITHIN_THRESHOLD = 0, //!< SDFM output is within threshold
SDFM_OUTPUT_ABOVE_THRESHOLD = 1, //!< SDFM output is above threshold
SDFM_OUTPUT_BELOW_THRESHOLD = 2 //!< SDFM output is below threshold
} SDFM_OutputThresholdStatus;
//*****************************************************************************
//
//! Values that can be passed to all functions as the \e filterNumber
//! parameter.
//
//*****************************************************************************
typedef enum
{
SDFM_FILTER_1 = 0, //!< Digital filter 1
SDFM_FILTER_2 = 1, //!< Digital filter 2
SDFM_FILTER_3 = 2, //!< Digital filter 3
SDFM_FILTER_4 = 3 //!< Digital filter 4
} SDFM_FilterNumber;
//*****************************************************************************
//
//! Values that can be passed to SDFM_setFilterType(),
//! SDFM_setComparatorFilterType() as the \e filterType parameter.
//
//*****************************************************************************
typedef enum
{
//! Digital filter with SincFast structure.
SDFM_FILTER_SINC_FAST = 0x00,
//! Digital filter with Sinc1 structure
SDFM_FILTER_SINC_1 = 0x10,
//! Digital filter with Sinc3 structure.
SDFM_FILTER_SINC_2 = 0x20,
//! Digital filter with Sinc4 structure.
SDFM_FILTER_SINC_3 = 0x30
} SDFM_FilterType;
//*****************************************************************************
//
//! Values that can be passed to SDFM_setupModulatorClock(),as the
//! \e clockMode parameter.
//
//*****************************************************************************
typedef enum
{
//! Modulator clock is identical to the data rate
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE = 0,
} SDFM_ModulatorClockMode;
//*****************************************************************************
//
//! Values that can be passed to SDFM_setOutputDataFormat(),as the
//! \e dataFormat parameter.
//
//*****************************************************************************
typedef enum
{
//! Filter output is in 16 bits 2's complement format.
SDFM_DATA_FORMAT_16_BIT = 0,
//! Filter output is in 32 bits 2's complement format.
SDFM_DATA_FORMAT_32_BIT = 1
} SDFM_OutputDataFormat;
//*****************************************************************************
//
//! Values that can be passed to SDFM_setDataReadyInterruptSource(),as the
//! \e dataReadySource parameter.
//
//*****************************************************************************
typedef enum
{
//! Data ready interrupt source is direct (non -FIFO).
SDFM_DATA_READY_SOURCE_DIRECT = 0,
//! Data ready interrupt source is FIFO.
SDFM_DATA_READY_SOURCE_FIFO = 1
} SDFM_DataReadyInterruptSource;
//*****************************************************************************
//
//! Values that can be passed to SDFM_setPWMSyncSource(),as the
//! \e syncSource parameter.
//
//*****************************************************************************
typedef enum
{
SDFM_SYNC_PWM1_SOCA = 0, //!< SDFM sync source is PWM1 SOCA
SDFM_SYNC_PWM1_SOCB = 1, //!< SDFM sync source is PWM1 SOCB
SDFM_SYNC_PWM2_SOCA = 4, //!< SDFM sync source is PWM2 SOCA
SDFM_SYNC_PWM2_SOCB = 5, //!< SDFM sync source is PWM2 SOCB
SDFM_SYNC_PWM3_SOCA = 8, //!< SDFM sync source is PWM3 SOCA
SDFM_SYNC_PWM3_SOCB = 9, //!< SDFM sync source is PWM3 SOCB
SDFM_SYNC_PWM4_SOCA = 12, //!< SDFM sync source is PWM4 SOCA
SDFM_SYNC_PWM4_SOCB = 13, //!< SDFM sync source is PWM4 SOCB
SDFM_SYNC_PWM5_SOCA = 16, //!< SDFM sync source is PWM5 SOCA
SDFM_SYNC_PWM5_SOCB = 17, //!< SDFM sync source is PWM5 SOCB
SDFM_SYNC_PWM6_SOCA = 20, //!< SDFM sync source is PWM6 SOCA
SDFM_SYNC_PWM6_SOCB = 21, //!< SDFM sync source is PWM6 SOCB
SDFM_SYNC_PWM7_SOCA = 24, //!< SDFM sync source is PWM7 SOCA
SDFM_SYNC_PWM7_SOCB = 25, //!< SDFM sync source is PWM7 SOCB
SDFM_SYNC_PWM8_SOCA = 28, //!< SDFM sync source is PWM8 SOCA
SDFM_SYNC_PWM8_SOCB = 29 //!< SDFM sync source is PWM8 SOCB
} SDFM_PWMSyncSource;
//*****************************************************************************
//
//! Values that can be passed to SDFM_setFIFOClearOnSyncMode(),as the
//! \e fifoClearSyncMode parameter.
//
//*****************************************************************************
typedef enum
{
//! SDFM FIFO buffer is not cleared on Sync signal
SDFM_FIFO_NOT_CLEARED_ON_SYNC = 0,
//! SDFM FIFO buffer is cleared on Sync signal
SDFM_FIFO_CLEARED_ON_SYNC = 1
} SDFM_FIFOClearSyncMode;
//*****************************************************************************
//
//! Values that can be passed to SDFM_setWaitForSyncClearMode(),as the
//! \e syncClearMode parameter.
//
//*****************************************************************************
typedef enum
{
//! Wait for sync cleared using software.
SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC = 0,
//! Wait for sync cleared automatically
SDFM_AUTO_CLEAR_WAIT_FOR_SYNC = 1
} SDFM_WaitForSyncClearMode;
//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventSource() as the
//! \e compEventNum parameter.
//
//*****************************************************************************
typedef enum
{
SDFM_COMP_EVENT_1 = 11U, //!< Selects CEVT1
SDFM_COMP_EVENT_2 = 14U //!< Selects CEVT2
} SDFM_CompEventNumber;
//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventSource() as the
//! \e compEventSource parameter.
//
//*****************************************************************************
typedef enum
{
SDFM_COMP_EVENT_SRC_COMPH1 = 0, //!< COMPH1 event is the source
SDFM_COMP_EVENT_SRC_COMPH1_L1 = 1, //!< Either of COMPH1 or COMPL1 event
//!< can be the source
SDFM_COMP_EVENT_SRC_COMPH2 = 2, //!< COMPH2 event is the source
SDFM_COMP_EVENT_SRC_COMPH2_L2 = 3, //!< Either of COMPH2 or COMPL2 event
//!< can be the source
SDFM_COMP_EVENT_SRC_COMPL1 = 0, //!< COMPL1 event is the source
SDFM_COMP_EVENT_SRC_COMPL2 = 2 //!< COMPL2 event is the source
} SDFM_CompEventSource;
//*****************************************************************************
//
//! Values that can be passed to SDFM_selectClockSource() as the \e clkSource
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! Source is respective channel clock
SDFM_CLK_SOURCE_CHANNEL_CLK = 0x0,
//! Source is SD1 channel clock is the source
SDFM_CLK_SOURCE_SD1_CLK = 0x8U
} SDFM_ClockSource;
//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventHighSource() as the
//! \e source parameter.
//
//*****************************************************************************
typedef enum
{
//! Comparator event high source is unfiltered event
SDFM_COMPHOUT_SOURCE_COMPHIN = 0x0,
//! Comparator event high source is filtered event
SDFM_COMPHOUT_SOURCE_FILTER = 0x8
} SDFM_CompEventHighSource;
//*****************************************************************************
//
//! Values that can be passed to SDFM_selectCompEventLowSource() as the
//! \e source parameter.
//
//*****************************************************************************
typedef enum
{
//! Comparator event low source is unfiltered event
SDFM_COMPLOUT_SOURCE_COMPLIN = 0x000,
//! Comparator event low source is filtered event
SDFM_COMPLOUT_SOURCE_FILTER = 0x800
} SDFM_CompEventLowSource;
//*****************************************************************************
//
//! Values that can be passed to SDFM_configCompEventLowFilter() &
//! SDFM_configCompEventHighFilter() as the \e filterNumber.
//
//*****************************************************************************
typedef struct
{
uint16_t sampleWindow; //!< Sample window size
uint16_t threshold; //!< Majority voting threshold
uint16_t clkPrescale; //!< Sample clock pre-scale
} SDFM_CompEventFilterConfig;
//*****************************************************************************
//
// Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt
// as intFlags parameter
//
//*****************************************************************************
//! Interrupt is generated if Modulator fails.
//!
//! Interrupt on Comparator low-level threshold.
//!
//! Interrupt on Comparator high-level threshold.
//!
//! Interrupt on Acknowledge flag
//!
//! Interrupt on FIFO level
//!
//! Interrupt on FIFO overflow
//!
//*****************************************************************************
//
// Values that can be passed to SDFM_clearInterruptFlag flags parameter
//
//*****************************************************************************
//! Main interrupt flag
//!
//! Filter 1 high -level threshold flag
//!
//! Filter 1 low -level threshold flag
//!
//! Filter 2 high -level threshold flag
//!
//! Filter 2 low -level threshold flag
//!
//! Filter 3 high -level threshold flag
//!
//! Filter 3 low -level threshold flag
//!
//! Filter 4 high -level threshold flag
//!
//! Filter 4 low -level threshold flag
//!
//! Filter 1 modulator failed flag
//!
//! Filter 2 modulator failed flag
//!
//! Filter 3 modulator failed flag
//!
//! Filter 4 modulator failed flag
//!
//! Filter 1 new data flag
//!
//! Filter 2 new data flag
//!
//! Filter 3 new data flag
//!
//! Filter 4 new data flag
//!
//! Filter 1 FIFO overflow flag
//!
//! Filter 2 FIFO overflow flag
//!
//! Filter 3 FIFO overflow flag
//!
//! Filter 4 FIFO overflow flag
//!
//! Filter 1 FIFO overflow flag
//!
//! Filter 2 FIFO overflow flag
//!
//! Filter 3 FIFO overflow flag
//!
//! Filter 4 FIFO overflow flag
//!
//*****************************************************************************
//
//! \internal
//! Checks SDFM base address.
//!
//! \param base specifies the SDFM module base address.
//!
//! This function determines if SDFM module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enable external reset
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables data filter to be reset by an external source (PWM
//! compare output).
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Set the SDSYNCEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) |=
0x1000U;
__edis();
}
//*****************************************************************************
//
//! Disable external reset
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables data filter from being reset by an external source
//! (PWM compare output).
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_disableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Clear the SDSYNCEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) &=
~0x1000U;
__edis();
}
//*****************************************************************************
//
//! Enable filter
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables the filter specified by the \e filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Set the FEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) |=
0x100U;
__edis();
}
//*****************************************************************************
//
//! Disable filter
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables the filter specified by the \e filterNumber
//! variable.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_disableFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Clear the FEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x11U + ((uint32_t)filterNumber * 16U)))) &=
~0x100U;
__edis();
}
//*****************************************************************************
//
//! Enable FIFO buffer
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables the filter FIFO buffer specified by the
//! \e filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableFIFOBuffer(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Set the FFEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x1DU + ((uint32_t)filterNumber * 16U)))) |=
0x2000U;
__edis();
}
//*****************************************************************************
//
//! Disable FIFO buffer
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables the filter FIFO buffer specified by the
//! \e filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableFIFOBuffer(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Clear the FFEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x1DU + ((uint32_t)filterNumber * 16U)))) &=
~0x2000U;
__edis();
}
//*****************************************************************************
//
//! Return the Zero Cross Trip status
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Zero Cross Trip status for the filter
//! specified by filterNumber variable.
//!
//! \return \b true if Comparator filter output >= High-level threshold (Z)
//! \b false if Comparator filter output < High-level threshold (Z)
//
//*****************************************************************************
static inline _Bool
SDFM_getZeroCrossTripStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
return((((*((volatile uint16_t *)(base + 0x7U))) >> (uint16_t)filterNumber) &
0x1U) == 1U);
}
//*****************************************************************************
//
//! Clear the Zero Cross Trip status
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function clears the Zero Cross Trip status for the filter
//! specified by filterNumber variable.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_clearZeroCrossTripStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Set SDCTL MIE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) |= ((uint16_t)1U << (uint16_t)filterNumber);
__edis();
}
//*****************************************************************************
//
//! Enable Comparator.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables the Comparator for the selected filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableComparator(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Set CEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) |=
0x2000U;
__edis();
}
//*****************************************************************************
//
//! Disable Comparator.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables the Comparator for the selected filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableComparator(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Clear CEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) &=
~0x2000U;
__edis();
}
//*****************************************************************************
//
//! Selects Comparator Event Source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number
//! \param compEventNum is the event number
//! \param compEventSource is the event source
//!
//! This function selects the comparator event source. Valid values for
//! \e compEventNum are:
//! - SDFM_COMP_EVENT_1 - Selects comparator event 1
//! - SDFM_COMP_EVENT_2 - Selects comparator event 2
//! Valid values for \e SDFM_COMP_EVENT_1 are:
//! - SDFM_COMP_EVENT_SRC_COMPH1 - COMPH1 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH1_L1 - Either of COMPH1 or COMPL1 event can be
//! the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH2 - COMPH2 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH2_L2 - Either of COMPH2 or COMPL2 event can be
//! the source for selected event
//!
//! Valid values for \e SDFM_COMP_EVENT_2 are:
//! - SDFM_COMP_EVENT_SRC_COMPL1 - COMPL1 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH1_L1 - Either of COMPH1 or COMPL1 event can be
//! the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPL2 - COMPL2 event is the source for selected event
//! - SDFM_COMP_EVENT_SRC_COMPH2_L2 - Either of COMPH2 or COMPL2 event can be
//! the source for selected event
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectCompEventSource(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_CompEventNumber compEventNum,
SDFM_CompEventSource compEventSource)
{
uint32_t address;
;
address = base + 0x15U + ((uint32_t)filterNumber *
(0x20U - 0x10U));
//
// Select source for selected comparator event
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~((uint16_t)0x2U <<
(uint16_t)compEventNum)) |
((uint16_t)compEventSource << (uint16_t)compEventNum) ;
__edis();
}
//*****************************************************************************
//
//! Set filter type.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param filterType is the filter type or structure.
//!
//! This function sets the filter type or structure to be used as specified by
//! filterType for the selected filter number as specified by filterNumber.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setFilterType(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_FilterType filterType)
{
uint32_t address;
;
address = base + 0x11U + ((uint32_t)filterNumber * 16U);
//
// Write to SST bits
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0xC00U)) |
((uint16_t)filterType << 6U);
__edis();
}
//*****************************************************************************
//
//! Set data filter over sampling ratio.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param overSamplingRatio is the data filter over sampling ratio.
//!
//! This function sets the filter oversampling ratio for the filter specified
//! by the filterNumber variable.Valid values for the variable
//! overSamplingRatio are 0 to 255 inclusive. The actual oversampling ratio
//! will be this value plus one.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t overSamplingRatio)
{
uint32_t address;
;
;
address = base + 0x11U + ((uint32_t)filterNumber * 16U);
//
// Write to DOSR bits
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0xFFU)) |
overSamplingRatio;
__edis();
}
//*****************************************************************************
//
//! Set modulator clock mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param clockMode is the modulator clock mode.
//!
//! This function sets the modulator clock mode specified by clockMode
//! for the filter specified by filterNumber.
//!
//! \note This function also enables the data and clock synchronizers for
//! the specified filter.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setupModulatorClock(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_ModulatorClockMode clockMode)
{
uint32_t address;
;
address = base + 0x10U + ((uint32_t)filterNumber * 16U);
//
// Write to MOD bits
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x3U)) |
(uint16_t)clockMode;
//
// Enable data and clock synchronizer
//
(*((volatile uint16_t *)(base + 0x10U + ((uint32_t)filterNumber * (0x20U - 0x10U))))) |=
(0x10U | 0x40U);
__edis();
}
//*****************************************************************************
//
//! Set the output data format
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param dataFormat is the output data format.
//!
//! This function sets the output data format for the filter specified by
//! filterNumber.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setOutputDataFormat(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_OutputDataFormat dataFormat)
{
uint32_t address;
;
address = base + 0x12U + ((uint32_t)filterNumber * 16U);
//
// Write to DR bit
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x400U)) |
((uint16_t)dataFormat << 10U);
__edis();
}
//*****************************************************************************
//
//! Set data shift value.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param shiftValue is the data shift value.
//!
//! This function sets the shift value for the 16 bit 2's complement data
//! format. The valid maximum value for shiftValue is 31.
//!
//! \b Note: Use this function with 16 bit 2's complement data format only.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setDataShiftValue(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t shiftValue)
{
uint32_t address;
;
;
address = base + 0x12U + ((uint32_t)filterNumber * 16U);
//
// Write to SH bit
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0xF800U)) |
(shiftValue << 11U);
__edis();
}
//*****************************************************************************
//
//! Set Filter output high-level threshold.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param highThreshold is the high-level threshold 1 & 2.
//!
//! This function sets the unsigned high-level threshold value for the
//! Comparator filter output. If the output value of the filter exceeds
//! highThreshold and interrupt generation is enabled, an interrupt will be
//! issued. The param \b highThreshold takes both high threshold 1 & 2 values.
//! The upper 16-bits represent the high threshold 2 value while lower 16-bits
//! represent the threshold 1 values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setCompFilterHighThreshold(uint32_t base, SDFM_FilterNumber filterNumber,
uint32_t highThreshold)
{
uint32_t address;
;
;
;
address = base + 0x13U +
((uint32_t)filterNumber * (0x20U - 0x10U));
//
// Write to HLT bit
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x7FFFU) |
(uint16_t)highThreshold;
(*((volatile uint16_t *)(address + (0x1BU - 0x13U)))) =
((*((volatile uint16_t *)(address + (0x1BU - 0x13U)))) &
~0x7FFFU) |
(uint16_t)(highThreshold >> 16U);
__edis();
}
//*****************************************************************************
//
//! Set Filter output low-level threshold.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number
//! \param lowThreshold is the low-level threshold
//!
//! This function sets the unsigned low-level threshold value 1 or 2 for the
//! Comparator filter output. If the output value of the filter gets below
//! lowThreshold and interrupt generation is enabled, an interrupt will be
//! issued. The param \b lowThreshold takes both low threshold 1 & 2 values.
//! The upper 16-bits represent the low threshold 2 value while lower 16-bits
//! represent the threshold 1 values.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setCompFilterLowThreshold(uint32_t base, SDFM_FilterNumber filterNumber,
uint32_t lowThreshold)
{
uint32_t address;
;
;
;
address = base + 0x14U +
((uint32_t)filterNumber * (0x20U - 0x10U));
//
// Write to LLT bit.
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x7FFFU) |
(uint16_t)lowThreshold;
(*((volatile uint16_t *)(address + (0x1FU - 0x14U)))) =
((*((volatile uint16_t *)(address + (0x1FU - 0x14U)))) &
~0x7FFFU) |
(uint16_t)(lowThreshold >> 16U);
__edis();
}
//*****************************************************************************
//
//! Set Filter output zero-cross threshold.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param zeroCrossThreshold is the zero-cross threshold.
//!
//! This function sets the unsigned zero-cross threshold value for the
//! Comparator filter output.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setCompFilterZeroCrossThreshold(uint32_t base,
SDFM_FilterNumber filterNumber,
uint16_t zeroCrossThreshold)
{
uint32_t address;
;
;
address = base + 0x1CU + ((uint32_t)filterNumber * 16U);
//
// Write to ZCT bit
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x7FFFU) |
zeroCrossThreshold;
__edis();
}
//*****************************************************************************
//
//! Enable zero-cross Edge detect mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables Zero Cross Edge detection.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableZeroCrossEdgeDetect(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Set ZCEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) |=
0x400U;
__edis();
}
//*****************************************************************************
//
//! Disable zero-cross Edge detect mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables Zero Cross Edge detection.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableZeroCrossEdgeDetect(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Clear ZCEN bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x15U + ((uint32_t)filterNumber * 16U)))) &=
~0x400U;
__edis();
}
//*****************************************************************************
//
//! Enable SDFM interrupts.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param intFlags is the interrupt source.
//!
//! This function enables the low threshold , high threshold or modulator
//! failure interrupt as determined by intFlags for the filter specified
//! by filterNumber.
//! Valid values for intFlags are:
//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT,
//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT, SDFM_FIFO_INTERRUPT,
//! SDFM_FIFO_OVERFLOW_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t intFlags)
{
uint16_t offset;
;
offset = (uint16_t)filterNumber * 16U;
__eallow();
//
// Low, high threshold, Modulator failure
//
if((intFlags & (0x200U |
0x40U |
0x20U)) != 0U)
{
//
// Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx
//
(*((volatile uint16_t *)(base + 0x15U + offset))) |=
(intFlags & (0x200U |
0x40U |
0x20U));
}
//
// Data filter acknowledge interrupt
//
if((intFlags & 0x1U) != 0U)
{
(*((volatile uint16_t *)(base + 0x11U + offset))) |= 0x200U;
}
//
// FIFO , FIFO overflow interrupt
//
if((intFlags & (0x1000U | 0x8000U)) != 0U)
{
//
// Set OVFIEN or FFIEN bits of SDFM_O_SDFIFOCTLx
//
(*((volatile uint16_t *)(base + 0x1DU + offset))) |=
(intFlags & (0x1000U |
0x8000U));
}
__edis();
}
//*****************************************************************************
//
//! Disable SDFM interrupts.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param intFlags is the interrupt source.
//!
//! This function disables the low threshold , high threshold or modulator
//! failure interrupt as determined by intFlags for the filter
//! specified by filterNumber.
//! Valid values for intFlags are:
//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT,
//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT, SDFM_FIFO_INTERRUPT,
//! SDFM_FIFO_OVERFLOW_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t intFlags)
{
uint16_t offset;
;
offset = (uint16_t)filterNumber * 16U;
__eallow();
//
// Low, high threshold, modulator failure interrupts
//
if((intFlags & (0x200U |
0x40U |
0x20U)) != 0U)
{
//
// Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx
//
(*((volatile uint16_t *)(base + 0x15U + offset))) &=
~(intFlags & (0x200U |
0x40U |
0x20U));
}
//
// Data filter acknowledge interrupt
//
if((intFlags & 0x1U) != 0U)
{
(*((volatile uint16_t *)(base + 0x11U + offset))) &= ~0x200U;
}
//
// FIFO , FIFO overflow interrupt
//
if((intFlags & (0x1000U | 0x8000U)) != 0U)
{
//
// Set OVFIEN or FFIEN bits of SDFM_O_SDFIFOCTLx
//
(*((volatile uint16_t *)(base + 0x1DU + offset))) &=
~(intFlags & (0x1000U | 0x8000U));
}
__edis();
}
//*****************************************************************************
//
//! Set the comparator filter type.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param filterType is the comparator filter type or structure.
//!
//! This function sets the Comparator filter type or structure to be used as
//! specified by filterType for the selected filter number as specified by
//! filterNumber.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setComparatorFilterType(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_FilterType filterType)
{
uint32_t address;
;
address = base + 0x15U + ((uint32_t)filterNumber * 16U);
//
// Write to CS1_CS0 bits
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x180U)) |
((uint16_t)filterType << 3U);
__edis();
}
//*****************************************************************************
//
//! Set Comparator filter over sampling ratio.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param overSamplingRatio is the comparator filter over sampling ration.
//!
//! This function sets the comparator filter oversampling ratio for the filter
//! specified by the filterNumber.Valid values for the variable
//! overSamplingRatio are 0 to 31 inclusive.
//! The actual oversampling ratio will be this value plus one.
//!
//! \return None.
//*****************************************************************************
static inline void
SDFM_setCompFilterOverSamplingRatio(uint32_t base,
SDFM_FilterNumber filterNumber,
uint16_t overSamplingRatio)
{
uint32_t address;
;
;
address = base + 0x15U + ((uint32_t)filterNumber * 16U);
//
// Write to COSR bits
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & (~0x1FU)) |
overSamplingRatio;
__edis();
}
//*****************************************************************************
//
//! Get the filter data output.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the latest data filter output. Depending on the
//! filter data output format selected, the valid value will be the lower 16
//! bits or the whole 32 bits of the returned value.
//!
//! \return Returns the latest data filter output.
//*****************************************************************************
static inline uint32_t
SDFM_getFilterData(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDDATA bits
//
return((*((volatile uint32_t *)(base + 0x16U + ((uint32_t)filterNumber * 16U)))));
}
//*****************************************************************************
//
//! Get the Comparator threshold status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Comparator output threshold status for the given
//! filterNumber.
//!
//! \return Returns the following status flags.
//! - \b SDFM_OUTPUT_WITHIN_THRESHOLD if the output is within the
//! specified threshold.
//! - \b SDFM_OUTPUT_ABOVE_THRESHOLD if the output is above the high
//! threshold
//! - \b SDFM_OUTPUT_BELOW_THRESHOLD if the output is below the low
//! threshold.
//!
//*****************************************************************************
static inline SDFM_OutputThresholdStatus
SDFM_getThresholdStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDIFLG high/low threshold bits
//
return((SDFM_OutputThresholdStatus)(((*((volatile uint32_t *)(base + 0x0U))) >>
(2U * (uint16_t)filterNumber)) & 0x3U));
}
//*****************************************************************************
//
//! Get the Modulator status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Modulator status.
//!
//! \return Returns true if the Modulator is operating normally
//! Returns false if the Modulator has failed
//!
//*****************************************************************************
static inline _Bool
SDFM_getModulatorStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDIFLG MF1, MF2, MF3 OR MF4 bits
//
return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 8U)) &
0x1U) != 0x1U);
}
//*****************************************************************************
//
//! Check if new Filter data is available.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns new filter data status.
//!
//! \return Returns \b true if new filter data is available
//! Returns \b false if no new filter data is available
//!
//*****************************************************************************
static inline _Bool
SDFM_getNewFilterDataStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDIFLG AF1, AF2, AF3 OR AF4 bits
//
return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 12U)) &
0x1U) == 0x1U);
}
//*****************************************************************************
//
//! Check if FIFO buffer is overflowed.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the status of the FIFO buffer overflow for the given
//! filter value.
//!
//! \return Returns \b true if FIFO buffer is overflowed
//! Returns \b false if FIFO buffer is not overflowed
//!
//*****************************************************************************
static inline _Bool
SDFM_getFIFOOverflowStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDIFLG SDFFOVF1, SDFFOVF2, SDFFOVF3 OR SDFFOVF4 bits
//
return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 16U)) &
0x1U) == 0x1U);
}
//*****************************************************************************
//
//! Check FIFO buffer interrupt status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the status of the FIFO buffer interrupt for the given
//! filter.
//!
//! \return Returns \b true if FIFO buffer interrupt has occurred.
//! Returns \b false if FIFO buffer interrupt has not occurred.
//!
//*****************************************************************************
static inline _Bool
SDFM_getFIFOISRStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDIFLG SDFFINT1, SDFFINT2, SDFFINT3 OR SDFFINT4 bits
//
return((((*((volatile uint32_t *)(base + 0x0U))) >> ((uint16_t)filterNumber + 20U)) &
0x1U) == 0x1U);
}
//*****************************************************************************
//
//! Get pending interrupt.
//!
//! \param base is the base address of the SDFM module
//!
//! This function returns any pending interrupt status.
//!
//! \return Returns \b true if there is a pending interrupt.
//! Returns \b false if no interrupt is pending.
//!
//*****************************************************************************
static inline _Bool
SDFM_getIsrStatus(uint32_t base)
{
;
//
// Read SDIFLG MIF
//
return(((*((volatile uint32_t *)(base + 0x0U))) >> 31U) == 0x1U);
}
//*****************************************************************************
//
//! Clear pending flags.
//!
//! \param base is the base address of the SDFM module
//! \param flag is the SDFM status
//!
//! This function clears the specified pending interrupt flag.
//! Valid values are
//! SDFM_MAIN_INTERRUPT_FLAG,SDFM_FILTER_1_NEW_DATA_FLAG,
//! SDFM_FILTER_2_NEW_DATA_FLAG,SDFM_FILTER_3_NEW_DATA_FLAG,
//! SDFM_FILTER_4_NEW_DATA_FLAG,SDFM_FILTER_1_MOD_FAILED_FLAG,
//! SDFM_FILTER_2_MOD_FAILED_FLAG,SDFM_FILTER_3_MOD_FAILED_FLAG,
//! SDFM_FILTER_4_MOD_FAILED_FLAG,SDFM_FILTER_1_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_1_LOW_THRESHOLD_FLAG,SDFM_FILTER_2_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_2_LOW_THRESHOLD_FLAG,SDFM_FILTER_3_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_3_LOW_THRESHOLD_FLAG,SDFM_FILTER_4_HIGH_THRESHOLD_FLAG,
//! SDFM_FILTER_4_LOW_THRESHOLD_FLAG,SDFM_FILTER_1_FIFO_OVERFLOW_FLAG,
//! SDFM_FILTER_2_FIFO_OVERFLOW_FLAG,SDFM_FILTER_3_FIFO_OVERFLOW_FLAG
//! SDFM_FILTER_4_FIFO_OVERFLOW_FLAG,SDFM_FILTER_1_FIFO_INTERRUPT_FLAG,
//! SDFM_FILTER_2_FIFO_INTERRUPT_FLAG,SDFM_FILTER_3_FIFO_INTERRUPT_FLAG
//! SDFM_FILTER_4_FIFO_INTERRUPT_FLAG or any combination of the above flags.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_clearInterruptFlag(uint32_t base, uint32_t flag)
{
;
;
//
// Write to SDIFLGCLR register
//
(*((volatile uint32_t *)(base + 0x2U))) |= flag;
}
//*****************************************************************************
//
//! Enable main interrupt.
//!
//! \param base is the base address of the SDFM module
//!
//! This function enables the main SDFM interrupt.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_enableMainInterrupt(uint32_t base)
{
;
//
// Set SDCTL MIE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) |= 0x2000U;
__edis();
}
//*****************************************************************************
//
//! Disable main interrupt.
//!
//! \param base is the base address of the SDFM module
//!
//! This function disables the main SDFM interrupt.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_disableMainInterrupt(uint32_t base)
{
;
//
// Clear SDCTL MIE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x4U))) &= ~0x2000U;
__edis();
}
//*****************************************************************************
//
//! Enable main filter.
//!
//! \param base is the base address of the SDFM module
//!
//! This function enables main filter.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_enableMainFilter(uint32_t base)
{
;
//
// Set SDMFILEN MFE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x6U))) |= 0x800U;
__edis();
}
//*****************************************************************************
//
//! Disable main filter.
//!
//! \param base is the base address of the SDFM module
//!
//! This function disables main filter.
//!
//! \return None
//!
//*****************************************************************************
static inline void
SDFM_disableMainFilter(uint32_t base)
{
;
//
// Clear SDMFILEN MFE bit
//
__eallow();
(*((volatile uint16_t *)(base + 0x6U))) &= ~0x800U;
__edis();
}
//*****************************************************************************
//
//! Return the FIFO data count
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the FIFO data count.
//!
//! \return Returns the number of data words available in FIFO buffer.
//
//*****************************************************************************
static inline uint16_t
SDFM_getFIFODataCount(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDFFST
//
return(((*((volatile uint16_t *)(base + 0x1DU + ((uint32_t)filterNumber * 16U)))) & 0x7C0U) >>
6U);
}
//*****************************************************************************
//
//! Return the Comparator sinc filter data
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Comparator sinc filter data output.
//!
//! \return Returns the Comparator sinc filter data output.
//!
//
//*****************************************************************************
static inline uint16_t
SDFM_getComparatorSincData(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDCDATA
//
return((*((volatile uint16_t *)(base + 0x1AU + ((uint32_t)filterNumber * 16U)))));
}
//*****************************************************************************
//
//! Return the FIFO data
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the latest FIFO data.
//!
//! \return Returns the latest FIFO data.
//!
//! \note Discard the upper 16 bits if the output data format is 16bits.
//
//*****************************************************************************
static inline uint32_t
SDFM_getFIFOData(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read SDDATFIFO
//
return((*((volatile uint32_t *)(base + 0x18U + ((uint32_t)filterNumber * 16U)))));
}
//*****************************************************************************
//
//! Set the FIFO interrupt level.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param fifoLevel is the FIFO interrupt level.
//!
//! This function sets the FIFO interrupt level. Interrupt is generated when
//! the FIFO buffer word count gets to or exceeds the value of \e fifoLevel.
//! Maximum value for \e fifoLevel is 16.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setFIFOInterruptLevel(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t fifoLevel)
{
uint32_t address;
;
;
address = base + 0x1DU + ((uint32_t)filterNumber * 16U);
//
// Write to SDFFIL bit
//
__eallow();
(*((volatile uint16_t *)(address))) =
(((*((volatile uint16_t *)(address))) & (~0x1FU)) | fifoLevel);
__edis();
}
//*****************************************************************************
//
//! Set data ready interrupt source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param dataReadySource is the data ready interrupt source.
//!
//! This function sets the data ready interrupt source.
//! Valid values for \e dataReadySource:
//! - SDFM_DATA_READY_SOURCE_DIRECT - Direct data ready
//! - SDFM_DATA_READY_SOURCE_FIFO - FIFO data ready.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setDataReadyInterruptSource(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_DataReadyInterruptSource dataReadySource)
{
uint32_t address;
;
address = base + 0x1DU + ((uint32_t)filterNumber * 16U);
//
// Write to DRINTSEL
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x4000U) |
((uint16_t)dataReadySource << 14U);
__edis();
}
//*****************************************************************************
//
//! Get the wait-for-sync event status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function returns the Wait-for-Sync event status.
//!
//! \return Returns true if sync event has occurred.
//! Returns false if sync event has not occurred.
//
//*****************************************************************************
static inline _Bool
SDFM_getWaitForSyncStatus(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Read WTSYNFLG bit
//
return((((*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) &
0x80U) >> 7U) == 0x1U);
}
//*****************************************************************************
//
//! Clear the Wait-for-sync event status.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function clears the Wait-for-sync event status.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_clearWaitForSyncFlag(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
__eallow();
//
// Clear WTSYNCLR bit
//
(*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) |=
0x100U;
__edis();
}
//*****************************************************************************
//
//! Enable wait for sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function enables the wait for sync mode. Data to FIFO will be written
//! only after PWM sync event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableWaitForSync(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
__eallow();
//
// Set WTSYNCEN bit
//
(*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) |=
0x40U;
__edis();
}
//*****************************************************************************
//
//! Disable wait for sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function disables the wait for sync mode. Data to FIFO will be written
//! every Data ready event.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableWaitForSync(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
__eallow();
//
// Clear WTSYNCEN bit
//
(*((volatile uint16_t *)(base + 0x1EU + ((uint32_t)filterNumber * 16U)))) &=
~0x40U;
__edis();
}
//*****************************************************************************
//
//! Set the PWM sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncSource is the PWM sync source.
//!
//! This function sets the PWM sync source for the specific SDFM filter. Valid
//! values for syncSource are SDFM_SYNC_PWMx_CMPy. Where x ranges from 1 to 8
//! Representing PWM1 to PWM8 respectively and y ranges from A to D
//! representing PWM comparators A to D.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setPWMSyncSource(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_PWMSyncSource syncSource)
{
uint32_t address;
;
address = base + 0x1EU + ((uint32_t)filterNumber * 16U);
__eallow();
//
// Write to SYNCSEL bits
//
(*((volatile uint16_t *)(address))) =
((*((volatile uint16_t *)(address))) & ~0x3FU) | (uint16_t)syncSource;
__edis();
//
//Enable SDSYNC reset to data filter
//
SDFM_enableExternalReset(base, filterNumber);
}
//*****************************************************************************
//
//! Set FIFO clear on sync mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param fifoClearSyncMode is the FIFO clear on sync mode.
//!
//! This function sets the FIFO clear mode for the specified filter when a sync
//! happens depending on the value of fifoClearSyncMode.
//! Valid values for fifoClearSyncMode are:
//! - SDFM_FIFO_NOT_CLEARED_ON_SYNC - FIFO is not cleared on sync.
//! - SDFM_FIFO_CLEARED_ON_SYNC - FIFO is cleared on sync.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setFIFOClearOnSyncMode(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_FIFOClearSyncMode fifoClearSyncMode)
{
uint32_t address;
;
address = base + 0x1EU + ((uint32_t)filterNumber * 16U);
__eallow();
//
// Write to FFSYNCCLREN bit
//
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x200U) |
((uint16_t)fifoClearSyncMode << 9U);
__edis();
}
//*****************************************************************************
//
//! Set Wait-for-sync clear mode.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncClearMode is the wait-for-sync clear mode.
//!
//! This function sets the Wait-For-sync clear mode depending on the value of
//! syncClearMode.
//! Valid values for syncClearMode are:
//! - SDFM_MANUAL_CLEAR_WAIT_FOR_SYNC - Wait-for-sync flag is cleared by
//! invoking SDFM_clearWaitForSyncFlag().
//! - SDFM_AUTO_CLEAR_WAIT_FOR_SYNC - Wait-for-sync flag is cleared
//! automatically on FIFO interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_setWaitForSyncClearMode(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_WaitForSyncClearMode syncClearMode)
{
uint32_t address;
;
address = base + 0x1EU + ((uint32_t)filterNumber * 16U);
__eallow();
//
// Write to WTSCLREN bit
//
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0x400U) |
((uint16_t)syncClearMode << 10U);
__edis();
}
//*****************************************************************************
//
//! Selects clock source for SDFM channels.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param clkSource is the clock source
//!
//! This function selects the clock for SDFM module filter channels.
//! Valid values for clkSource are:
//! - SDFM_CLK_SOURCE_CHANNEL_CLK - Respective channel's clk is the source
//! - SDFM_CLK_SOURCE_SD1_CLK - Filter 1 clock is the source
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectClockSource(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_ClockSource clkSource)
{
uint32_t address;
;
address = base + 0x10U +
((uint32_t)filterNumber * (0x20U - 0x10U));
//
// Select SDFM clock source.
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~(0x8U)) |
(uint16_t)clkSource;
__edis();
}
//*****************************************************************************
//
//! Enables Input Synchronizer.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncConfig defines which synchronizer to be enabled
//!
//! This function enables either data or clock or both synchronizer.
//! Valid values for syncConfig can be the logical OR of any of the values:
//! - SDFM_CLOCK_SYNCHRONIZER - Enable SDFM input clock synchronizer
//! - SDFM_DATA_SYNCHRONIZER - Enable SDFM input data synchronizer
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_enableSynchronizer(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t syncConfig)
{
;
//
// Select SDFM clock source.
//
__eallow();
(*((volatile uint16_t *)(base + 0x10U + ((uint32_t)filterNumber * (0x20U - 0x10U))))) |= syncConfig;
__edis();
}
//*****************************************************************************
//
//! Disables Input Synchronizer.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param syncConfig defines which synchronizer to be disabled
//!
//! This function disables either data or clock or both synchronizer.
//! Valid values for syncConfig can be the logical OR of any of the values:
//! - SDFM_CLOCK_SYNCHRONIZER - Disable SDFM input clock synchronizer
//! - SDFM_DATA_SYNCHRONIZER - Disable SDFM input data synchronizer
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_disableSynchronizer(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t syncConfig)
{
;
//
// Select SDFM clock source.
//
__eallow();
(*((volatile uint16_t *)(base + 0x10U + ((uint32_t)filterNumber * (0x20U - 0x10U))))) &= ~syncConfig;
__edis();
}
//*****************************************************************************
//
//! Selects comparator event high source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param source is the comparator event high source
//!
//! This function selects the source for comparator event high.
//! Valid values for source are:
//! - SDFM_COMPHOUT_SOURCE_COMPHIN - Original COMPHIN/CEVT1 signal is source
//! - SDFM_COMPHOUT_SOURCE_FILTER - Filtered COMPHIN/CEVT1 signal is source
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectCompEventHighSource(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_CompEventHighSource source)
{
uint32_t address;
;
address = base + 0x60U +
((uint32_t)filterNumber * (0x68U - 0x60U));
//
// Set COMPHOUT source.
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0xCU) |
(uint16_t)source;
__edis();
}
//*****************************************************************************
//
//! Selects comparator event low source.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param source is the comparator event low source
//!
//! This function selects the source for comparator event low.
//! Valid values for source are:
//! - SDFM_COMPLOUT_SOURCE_COMPLIN - Original COMPLIN/CEVT2 signal is source
//! - SDFM_COMPHOUT_SOURCE_FILTER - Filtered COMPLIN/CEVT2 signal is source
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_selectCompEventLowSource(uint32_t base, SDFM_FilterNumber filterNumber,
SDFM_CompEventLowSource source)
{
uint32_t address;
;
address = base + 0x60U +
((uint32_t)filterNumber * (0x68U - 0x60U));
//
// Set COMPLOUT source.
//
__eallow();
(*((volatile uint16_t *)(address))) = ((*((volatile uint16_t *)(address))) & ~0xC00U) |
(uint16_t)source;
__edis();
}
//*****************************************************************************
//
//! Initializes Comparator Event Low Filter.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function initializes Comparator Event Low Filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_initCompEventLowFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Initialize comparator event low filter.
//
__eallow();
(*((volatile uint16_t *)(base + 0x61U + ((uint32_t)filterNumber * (0x68U - 0x60U))))) |=
(uint16_t)0x8000U;
__edis();
}
//*****************************************************************************
//
//! Initializes Comparator Event High Filter.
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//!
//! This function initializes Comparator Event High Filter.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_initCompEventHighFilter(uint32_t base, SDFM_FilterNumber filterNumber)
{
;
//
// Initialize comparator event high filter.
//
__eallow();
(*((volatile uint16_t *)(base + 0x63U + ((uint32_t)filterNumber * (0x68U - 0x60U))))) |=
(uint16_t)0x8000U;
__edis();
}
//*****************************************************************************
//
//! Lock Comparator Event Filter Configurations
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param lockConfig defines the configurations to be locked
//!
//! This function locks the comparator event filter configurations. Valid
//! values of the lockConfig can be logical OR of any of the following values:
//! - SDFM_SDCOMPLOCK_SDCOMPCTL - Locks write access to SDCOMPCTL register
//! - SDFM_SDCOMPLOCK_COMP - Locks write access to SDCOMPxFILCTL &
//! SDCOMPxFILCLKCTL register
//!
//! \return None.
//
//*****************************************************************************
static inline void
SDFM_lockCompEventFilterConfig(uint32_t base, SDFM_FilterNumber filterNumber,
uint16_t lockConfig)
{
;
//
// Lock comparator event filter related configurations.
//
__eallow();
(*((volatile uint16_t *)(base + 0x67U + ((uint32_t)filterNumber * (0x68U - 0x60U))))) |= lockConfig;
__edis();
}
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Configures SDFM comparator for filter config & threshold values
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio.
//! \param config2 is high-level and low-level threshold 1 values.
//! \param config3 is the zero-cross threshold value.
//!
//! This function configures the comparator filter for filter config and
//! threshold values based on provided inputs.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//! - config1.[3:0] filter number
//! - config1.[7:4] filter type
//! - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location.
//! For example the value
//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16))
//! will select Filter 1, SINC 2 type with an oversampling ratio of 16.
//!
//! The config2 parameter is the logical OR of the filter high and low
//! threshold 1 values.
//! The bit definitions for config2 are as follow:
//! - config2.[15:0] low threshold 1
//! - config2.[31:16] high threshold 1
//! The upper 16 bits define the high threshold 1 and the lower 16 bits define
//! the low threshold 1. SDFM_THRESHOLD(H,L) can be used to combine the high
//! and low thresholds.
//! The config3 parameter is the logical OR of the zero cross threshold
//! enable flag and the zero-cross threshold value.
//! The bit definitions for config3 are as follow:
//! - config3.[15] - Enable or disable zero cross threshold. Valid values
//! are 1 or 0 to enable or disable the zero cross threshold
//! respectively.
//! -config3.[14:0] - Zero Cross Threshold value.
//! The SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) macro can be used to specify the
//! zero-cross threshold value and OR the 1 to enable it.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configComparator(uint32_t base, uint16_t config1,
uint32_t config2, uint16_t config3);
//*****************************************************************************
//
//! Configure SDFM enhanced comparator for filter config & threshold values
//!
//! \param base is the base address of the SDFM module
//! \param filterConfig is the filter number, filter type & over sampling ratio.
//! \param highLowThreshold1 is high-level and low-level threshold 1 values.
//! \param highLowThreshold2 is high-level and low-level threshold 2 values.
//! \param zeroCrossThreshold is the zero-cross threshold value.
//!
//! This function configures the comparator filter for filter config and
//! threshold values based on input parameters.
//!
//! The filterConfig parameter is the logical OR of the filter number, filter
//! type and oversampling ratio.
//! The bit definitions for filterConfig are as follow:
//! - filterConfig.[3:0] filter number
//! - filterConfig.[7:4] filter type
//! - filterConfig.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location.
//! For example the value
//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16))
//! will select Filter 1, SINC 2 type with an oversampling ratio of 16.
//!
//! The highLowThreshold1 parameter is the logical OR of the filter high & low
//! threshold 1 values.
//! The bit definitions for highLowThreshold1 are as follow:
//! - highLowThreshold1.[15:0] low threshold 1
//! - highLowThreshold1.[31:16] high threshold 1
//! The upper 16 bits define the high threshold and the lower 16 bits define
//! the low threshold. SDFM_THRESHOLD(H,L) can be used to combine the high and
//! low thresholds.
//!
//! The highLowThreshold2 parameter is the logical OR of the filter high & low
//! threshold 2 values.
//! The bit definitions for highLowThreshold2 are as follow:
//! - highLowThreshold2.[15:0] low threshold 2
//! - highLowThreshold2.[31:16] high threshold 2
//! The upper 16 bits define the high threshold and the lower 16 bits define
//! the low threshold. SDFM_THRESHOLD(H,L) can be used to combine the high &
//! low thresholds.
//!
//! The zeroCrossThreshold parameter is the logical OR of the zero cross
//! threshold enable flag and the zero-cross threshold value. The bit
//! definitions for zeroCrossThreshold are as follows:
//! - zeroCrossThreshold.[15] - Enable or disable zero cross threshold. Valid
//! values are 1 or 0 to enable or disable the zero cross threshold
//! respectively.
//! - zeroCrossThreshold.[14:0] - Zero Cross Threshold value.
//! The SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) macro can be used as parameter
//! zeroCrossThreshold to enable & specify the zero-cross threshold value.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configEnhancedComparator(uint32_t base, uint16_t filterConfig,
uint32_t highLowThreshold1,
uint32_t highLowThreshold2,
uint16_t zeroCrossThreshold);
//*****************************************************************************
//
//! Configure SDFM data filter
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio
//! configuration.
//! \param config2 is filter switch, data representation and data shift values
//! configuration.
//!
//! This function configures the data filter based on configurations
//! config1 and config2.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//! - config1.[3:0] Filter number
//! - config1.[7:4] Filter type
//! - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio , which ranges [1,256] inclusive , in the appropriate bit location
//! for config1. For example the value
//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64))
//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64.
//!
//! The config2 parameter is the logical OR of data representation, filter
//! switch, and data shift values
//! The bit definitions for config2 are as follow:
//! - config2.[0] Data representation
//! - config2.[1] Filter switch
//! - config2.[15:2] Shift values
//! Valid values for data representation are given in SDFM_OutputDataFormat
//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the
//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value
//! of the data shift value,which ranges [0,31] inclusive, in the appropriate
//! bit location for config2.
//! The shift value is valid only in SDFM_DATA_FORMAT_16_BIT data
//! representation format.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2);
//*****************************************************************************
//
//! Configure SDFM comparator Zero Cross threshold
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio.
//! \param config2 is the zero cross threshold value.
//!
//! This function configures the comparator filter zero cross threshold values
//! based on configurations config1 and config2.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//! - config1.[3:0] filter number
//! - config1.[7:4] filter type
//! - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location.
//! For example the value
//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16))
//! will select Filter 1 , SINC 2 type with an oversampling ratio of 16.
//!
//! The config2 parameter is the value of the zero cross threshold. The maximum
//! acceptable value is 32767.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configZeroCrossComparator(uint32_t base, uint16_t config1,
uint16_t config2);
//*****************************************************************************
//
//! Configure SDFM data filter FIFO
//!
//! \param base is the base address of the SDFM module
//! \param config1 is the filter number, filter type and over sampling ratio
//! configuration.
//! \param config2 is filter switch, data representation and data shift values
//! and FIFO level configuration.
//!
//! This function enables and configures the data filter FIFO based on
//! configurations config1 and config2.
//!
//! The config1 parameter is the logical OR of the filter number, filter type
//! and oversampling ratio.
//! The bit definitions for config1 are as follow:
//! - config1.[3:0] filter number
//! - config1.[7:4] filter type
//! - config1.[15:8] Over sampling Ratio
//! Valid values for filter number and filter type are defined in
//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively.
//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling
//! ratio , which ranges [1,256] inclusive , in the appropriate bit location
//! for config1. For example the value
//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64))
//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64.
//!
//! The config2 parameter is the logical OR of data representation, filter
//! switch, data shift value, and FIFO level
//! The bit definitions for config2 are as follow:
//! - config2.[0] Data representation
//! - config2.[1] filter switch.
//! - config2.[6:2] shift values.
//! - config2.[15:7] FIFO level
//! Valid values for data representation are given in SDFM_OutputDataFormat
//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the
//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value
//! of the data shift value,which ranges [0,31] inclusive, in the appropriate
//! bit location for config2.
//! The value of FIFO level ranges [1,16] inclusive. The macro
//! SDFM_SET_FIFO_LEVEL(X) can be used to set the value of the FIFO level.
//!
//! \return None.
//!
//*****************************************************************************
extern void
SDFM_configDataFilterFIFO(uint32_t base, uint16_t config1, uint16_t config2);
//*****************************************************************************
//
//! Configure Comparator Event Low Filter
//!
//! \param base is the base address of the SDFM module
//! \param filterNumber is the filter number.
//! \param config is the comparator event low source
//!
//! This function configures the sample window, threshold and clock prescale
//! configurations for the comparator event low filter.
//!
//! \return None.
//
//*****************************************************************************
extern void
SDFM_configCompEventLowFilter(uint32_t base, SDFM_FilterNumber filterNumber,
const SDFM_CompEventFilterConfig *config);
//*****************************************************************************
//
//! Configure Comparator Event High Filter
//!
//! \param base is the base address of the SDFM module.
//! \param filterNumber is the filter number.
//! \param config is the comparator event high source
//!
//! This function configures the sample window, threshold and clock prescale
//! configurations for the comparator event high filter.
//!
//! \return None.
//
//*****************************************************************************
extern void
SDFM_configCompEventHighFilter(uint32_t base, SDFM_FilterNumber filterNumber,
const SDFM_CompEventFilterConfig *config);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: spi.h
//
// TITLE: C28x SPI driver.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup spi_api SPI
//! \brief This module is used for SPI configurations.
//! @{
//
//*****************************************************************************
//###########################################################################
//
// FILE: hw_spi.h
//
// TITLE: Definitions for the SPI registers.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*************************************************************************************************
//
// The following are defines for the SPI register offsets
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPICCR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPICTL register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPISTS register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIBRR register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFTX register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFRX register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFCT register
//
//*************************************************************************************************
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIPRI register
//
//*************************************************************************************************
//*****************************************************************************
//
// Values that can be passed to SPI_enableInterrupt(), SPI_disableInterrupt(),
// and SPI_clearInterruptStatus() as the intFlags parameter, and returned by
// SPI_getInterruptStatus().
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro definition is used to transmit a byte of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//!
//! This macro definition is to transmit a byte of data.
//! This macro uses SPI_pollingNonFIFOTransaction function
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro definition is used to transmit a 16-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//!
//! This macro definition is to transmit a 16-bit word of data.
//! This macro uses SPI_pollingNonFIFOTransaction function
//! SPI character length is hardcoded to 16 (16bit word) of character length
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro definition can be used to transmit 'N' bytes of data
//!
//! \param base specifies the SPI module base address.
//! \param txBuffer is the transmit buffer to be transmitted over SPI
//! \param numOfWords is the number of bytes to be transmitted
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This macro definition can be used to transmit 'N' bytes of data.
//! This macro definition uses SPI_pollingFIFOTransaction function.
//!
//! SPI character length is hardcoded to 8 (8bits) of character length
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro definition can be used to transmit 'N' 16-bit words of data
//!
//! \param base specifies the SPI module base address.
//! \param txBuffer is the transmit buffer to be transmitted over SPI
//! \param numOfWords is the number of 16-bit word to be transmitted
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function can be used to transmit 'N' 16-bit words of data.
//! This function uses SPI_pollingFIFOTransaction function.
//! SPI character length is hardcoded to 16 (16-bit word)
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro definition can be used to transmit 'N' with configurable
//! SPI character length
//!
//! \param base specifies the SPI module base address
//! \param charLength specifies the SPI character length
//! \param txBuffer is the transmit buffer to be transmitted over SPI
//! \param numOfWords is the number of 16-bit word to be transmitted
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This macro definition can be used to transmit 'N' with configurable
//! SPI character length.
//!
//! This macro uses SPIpolling_FIFO_Transaction function.
//! SPI character length is configurable using charLength variable.
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro definition is used to receive a byte of data
//!
//! \param base specifies the SPI module base address.
//! \param dummyData is the data which is transmitted to initiate
//! SPI transaction to receive SPI data
//!
//! This macro definition is to receive a byte of data.
//! This macro uses SPI_pollingNonFIFOTransaction function
//! SPI character length is hardcoded to 8 (1byte = 8bits) of character length
//!
//! \return the received byte.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro is used to receive 'N' bytes of data
//!
//! \param base specifies the SPI module base address.
//! \param rxBuffer specifies receive buffer which will store the received bytes
//! \param numOfWords specifies the number of bytes to be received
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function is used to receive 'N' bytes of data
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro is used to receive 'N' 16-bits words of data
//!
//! \param base specifies the SPI module base address.
//! \param rxBuffer specifies receive buffer which will store the received bytes
//! \param numOfWords specifies the number of 16-bit words to be received
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function is used to receive 'N' 16-bit words of data
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 16bits
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! This macro is used to receive 'N' words with specified character length
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the SPI character length of SPI transaction
//! \param rxBuffer specifies receive buffer which will store the received bytes
//! \param numOfWords specifies the number of words with specified character
//! length
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function is used to receive 'N' words with specified character length
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is configurable using charLength variable
//!
//! \return None.
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to SPI_setConfig() as the \e protocol parameter.
//
//*****************************************************************************
typedef enum
{
//! Mode 0. Polarity 0, phase 0. Rising edge without delay.
SPI_PROT_POL0PHA0 = 0x0000U,
//! Mode 1. Polarity 0, phase 1. Rising edge with delay.
SPI_PROT_POL0PHA1 = 0x0002U,
//! Mode 2. Polarity 1, phase 0. Falling edge without delay.
SPI_PROT_POL1PHA0 = 0x0001U,
//! Mode 3. Polarity 1, phase 1. Falling edge with delay.
SPI_PROT_POL1PHA1 = 0x0003U
} SPI_TransferProtocol;
//*****************************************************************************
//
//! Values that can be passed to SPI_setConfig() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
SPI_MODE_PERIPHERAL = 0x0002U, //!< SPI peripheral
SPI_MODE_CONTROLLER = 0x0006U, //!< SPI controller
SPI_MODE_PERIPHERAL_OD = 0x0000U, //!< SPI peripheral w/ output disabled
SPI_MODE_CONTROLLER_OD = 0x0004U //!< SPI controller w/ output disabled
} SPI_Mode;
//*****************************************************************************
//
//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e txLevel
//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e txLevel
//! parameter, and returned by SPI_getTxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
SPI_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty
SPI_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty
SPI_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full
SPI_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full
SPI_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full
SPI_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full
SPI_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full
SPI_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full
SPI_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full
SPI_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full
SPI_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full
SPI_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full
SPI_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full
SPI_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full
SPI_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full
SPI_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full
SPI_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full
SPI_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full
SPI_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full
} SPI_TxFIFOLevel;
//*****************************************************************************
//
//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e rxLevel
//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e rxLevel
//! parameter, and returned by SPI_getRxFIFOStatus().
//
//*****************************************************************************
typedef enum
{
SPI_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty
SPI_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty
SPI_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full
SPI_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full
SPI_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full
SPI_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full
SPI_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full
SPI_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full
SPI_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full
SPI_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full
SPI_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full
SPI_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full
SPI_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full
SPI_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full
SPI_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full
SPI_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full
SPI_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full
SPI_FIFO_RX16 = 0x0010U, //!< Receive FIFO full
SPI_FIFO_RXFULL = 0x0010U, //!< Receive FIFO full
SPI_FIFO_RXDEFAULT = 0x001FU //!< To prevent interrupt at reset
} SPI_RxFIFOLevel;
//*****************************************************************************
//
//! Values that can be passed to SPI_setEmulationMode() as the \e mode
//! parameter.
//
//*****************************************************************************
typedef enum
{
//! Transmission stops after midway in the bit stream
SPI_EMULATION_STOP_MIDWAY = 0x0000U,
//! Continue SPI operation regardless
SPI_EMULATION_FREE_RUN = 0x0010U,
//! Transmission will stop after a started transmission completes
SPI_EMULATION_STOP_AFTER_TRANSMIT = 0x0020U
} SPI_EmulationMode;
//*****************************************************************************
//
//! Values that can be passed to SPI_setPTESignalPolarity() as the \e polarity
//! parameter.
//
//*****************************************************************************
typedef enum
{
SPI_PTE_ACTIVE_LOW = 0x0000U, //!< SPIPTE is active low (normal)
SPI_PTE_ACTIVE_HIGH = 0x2U //!< SPIPTE is active high (inverted)
} SPI_PTEPolarity;
//*****************************************************************************
//
//! Values that can be passed to SPI_receive16Bits(), SPI_receive24Bits(),
//! SPI_receive32Bits()
//
//*****************************************************************************
typedef enum
{
SPI_DATA_LITTLE_ENDIAN = 0U, //!< LITTLE ENDIAN
SPI_DATA_BIG_ENDIAN = 1U, //!< BIG ENDIAN
} SPI_endianess;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks an SPI base address.
//!
//! \param base specifies the SPI module base address.
//!
//! This function determines if a SPI module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enables the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//!
//! This function enables operation of the serial peripheral interface. The
//! serial peripheral interface must be configured before it is enabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableModule(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x0U))) |= 0x80U;
}
//*****************************************************************************
//
//! Disables the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//!
//! This function disables operation of the serial peripheral interface. Call
//! this function before doing any configuration.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableModule(uint32_t base)
{
//
// Check the arguments.
//
;
(*((volatile uint16_t *)(base + 0x0U))) &= ~(0x80U);
}
//*****************************************************************************
//
//! Sets the character length of SPI transaction
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the character length of SPI transaction
//!
//! This function configures the character length of SPI transaction.
//! SPI character length can be from anywhere between 1-bit word to 16 bit word
//! of character length
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setcharLength(uint32_t base, uint16_t charLength)
{
;
SPI_disableModule(base);
(*((volatile uint16_t *)(base + 0x0U))) = ((*((volatile uint16_t *)(base + 0x0U))) & ~0xFU) |
(charLength - 1U);
SPI_enableModule(base);
}
//*****************************************************************************
//
//! Enables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SPI port.
//!
//! This functions enables the transmit and receive FIFOs in the SPI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Enable the FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) |= 0x4000U | 0x2000U;
(*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U;
}
//*****************************************************************************
//
//! Disables the transmit and receive FIFOs.
//!
//! \param base is the base address of the SPI port.
//!
//! This functions disables the transmit and receive FIFOs in the SPI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Disable the FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) &= ~(0x4000U | 0x2000U);
(*((volatile uint16_t *)(base + 0xBU))) &= ~0x2000U;
}
//*****************************************************************************
//
//! Resets the transmit FIFO.
//!
//! \param base is the base address of the SPI port.
//!
//! This function resets the transmit FIFO, setting the FIFO pointer back to
//! zero.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_resetTxFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Reset the TX FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) &= ~0x2000U;
(*((volatile uint16_t *)(base + 0xAU))) |= 0x2000U;
}
//*****************************************************************************
//
//! Resets the receive FIFO.
//!
//! \param base is the base address of the SPI port.
//!
//! This function resets the receive FIFO, setting the FIFO pointer back to
//! zero.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_resetRxFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Reset the RX FIFO.
//
(*((volatile uint16_t *)(base + 0xBU))) &= ~0x2000U;
(*((volatile uint16_t *)(base + 0xBU))) |= 0x2000U;
}
//*****************************************************************************
//
//! Sets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the SPI port.
//! \param txLevel is the transmit FIFO interrupt level, specified as
//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, . . . or
//! \b SPI_FIFO_TX16.
//! \param rxLevel is the receive FIFO interrupt level, specified as
//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, . . . or
//! \b SPI_FIFO_RX16.
//!
//! This function sets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel txLevel,
SPI_RxFIFOLevel rxLevel)
{
//
// Check the arguments.
//
;
//
// Set the FIFO interrupt levels.
//
(*((volatile uint16_t *)(base + 0xAU))) = ((*((volatile uint16_t *)(base + 0xAU))) &
(~0x1FU)) | (uint16_t)txLevel;
(*((volatile uint16_t *)(base + 0xBU))) = ((*((volatile uint16_t *)(base + 0xBU))) &
(~0x1FU)) | (uint16_t)rxLevel;
}
//*****************************************************************************
//
//! Gets the FIFO level at which interrupts are generated.
//!
//! \param base is the base address of the SPI port.
//! \param txLevel is a pointer to storage for the transmit FIFO level,
//! returned as one of \b SPI_FIFO_TX0, \b SPI_FIFO_TX1,
//! \b SPI_FIFO_TX2, . . . or \b SPI_FIFO_TX16.
//! \param rxLevel is a pointer to storage for the receive FIFO level,
//! returned as one of \b SPI_FIFO_RX0, \b SPI_FIFO_RX1,
//! \b SPI_FIFO_RX2, . . . or \b SPI_FIFO_RX16.
//!
//! This function gets the FIFO level at which transmit and receive interrupts
//! are generated.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_getFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel *txLevel,
SPI_RxFIFOLevel *rxLevel)
{
//
// Check the arguments.
//
;
//
// Extract the transmit and receive FIFO levels.
//
*txLevel = (SPI_TxFIFOLevel)((uint16_t)((*((volatile uint16_t *)(base + 0xAU))) &
0x1FU));
*rxLevel = (SPI_RxFIFOLevel)((uint16_t)((*((volatile uint16_t *)(base + 0xBU))) &
0x1FU));
}
//*****************************************************************************
//
//! Get the transmit FIFO status
//!
//! \param base is the base address of the SPI port.
//!
//! This function gets the current number of words in the transmit FIFO.
//!
//! \return Returns the current number of words in the transmit FIFO specified
//! as one of the following:
//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, \b SPI_FIFO_TX3,
//! ..., or \b SPI_FIFO_TX16
//
//*****************************************************************************
static inline SPI_TxFIFOLevel
SPI_getTxFIFOStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Get the current FIFO status
//
return((SPI_TxFIFOLevel)((uint16_t)(((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) >>
8U)));
}
//*****************************************************************************
//
//! Get the receive FIFO status
//!
//! \param base is the base address of the SPI port.
//!
//! This function gets the current number of words in the receive FIFO.
//!
//! \return Returns the current number of words in the receive FIFO specified
//! as one of the following:
//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, \b SPI_FIFO_RX3,
//! ..., or \b SPI_FIFO_RX16
//
//*****************************************************************************
static inline SPI_RxFIFOLevel
SPI_getRxFIFOStatus(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Get the current FIFO status
//
return((SPI_RxFIFOLevel)((uint16_t)(((*((volatile uint16_t *)(base + 0xBU))) & 0x1F00U) >>
8U)));
}
//*****************************************************************************
//
//! Determines whether the SPI transmitter is busy or not.
//!
//! \param base is the base address of the SPI port.
//!
//! This function allows the caller to determine whether all transmitted bytes
//! have cleared the transmitter hardware. If \b false is returned, then the
//! transmit FIFO is empty and all bits of the last transmitted word have left
//! the hardware shift register. This function is only valid when operating in
//! FIFO mode.
//!
//! \return Returns \b true if the SPI is transmitting or \b false if all
//! transmissions are complete.
//
//*****************************************************************************
static inline _Bool
SPI_isBusy(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Determine if the SPI is busy.
//
return(((*((volatile uint16_t *)(base + 0xAU))) & 0x1F00U) != 0U);
}
//*****************************************************************************
//
//! Puts a data element into the SPI transmit buffer.
//!
//! \param base specifies the SPI module base address.
//! \param data is the left-justified data to be transmitted over SPI.
//!
//! This function places the supplied data into the transmit buffer of the
//! specified SPI module.
//!
//! \note The data being sent must be left-justified in \e data. The lower
//! 16 - N bits will be discarded where N is the data width selected in
//! SPI_setConfig(). For example, if configured for a 6-bit data width, the
//! lower 10 bits of data will be discarded.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_writeDataNonBlocking(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
//
// Write data to the transmit buffer.
//
(*((volatile uint16_t *)(base + 0x8U))) = data;
}
//*****************************************************************************
//
//! Gets a data element from the SPI receive buffer.
//!
//! \param base specifies the SPI module base address.
//!
//! This function gets received data from the receive buffer of the specified
//! SPI module and returns it.
//!
//! \note Only the lower N bits of the value written to \e data contain valid
//! data, where N is the data width as configured by SPI_setConfig(). For
//! example, if the interface is configured for 8-bit data width, only the
//! lower 8 bits of the value written to \e data contain valid data.
//!
//! \return Returns the word of data read from the SPI receive buffer.
//
//*****************************************************************************
static inline uint16_t
SPI_readDataNonBlocking(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Check for data to read.
//
return((*((volatile uint16_t *)(base + 0x7U))));
}
//*****************************************************************************
//
//! Waits for space in the FIFO and then puts data into the transmit buffer.
//!
//! \param base specifies the SPI module base address.
//! \param data is the left-justified data to be transmitted over SPI.
//!
//! This function places the supplied data into the transmit buffer of the
//! specified SPI module once space is available in the transmit FIFO. This
//! function should only be used when the FIFO is enabled.
//!
//! \note The data being sent must be left-justified in \e data. The lower
//! 16 - N bits will be discarded where N is the data width selected in
//! SPI_setConfig(). For example, if configured for a 6-bit data width, the
//! lower 10 bits of data will be discarded.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
//
// Wait until space is available in the receive FIFO.
//
while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL)
{
}
//
// Write data to the transmit buffer.
//
(*((volatile uint16_t *)(base + 0x8U))) = data;
}
//*****************************************************************************
//
//! Waits for data in the FIFO and then reads it from the receive buffer.
//!
//! \param base specifies the SPI module base address.
//!
//! This function waits until there is data in the receive FIFO and then reads
//! received data from the receive buffer. This function should only be used
//! when FIFO mode is enabled.
//!
//! \note Only the lower N bits of the value written to \e data contain valid
//! data, where N is the data width as configured by SPI_setConfig(). For
//! example, if the interface is configured for 8-bit data width, only the
//! lower 8 bits of the value written to \e data contain valid data.
//!
//! \return Returns the word of data read from the SPI receive buffer.
//
//*****************************************************************************
static inline uint16_t
SPI_readDataBlockingFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Wait until data is available in the receive FIFO.
//
while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY)
{
}
//
// Check for data to read.
//
return((*((volatile uint16_t *)(base + 0x7U))));
}
//*****************************************************************************
//
//! Waits for the transmit buffer to empty and then writes data to it.
//!
//! \param base specifies the SPI module base address.
//! \param data is the left-justified data to be transmitted over SPI.
//!
//! This function places the supplied data into the transmit buffer of the
//! specified SPI module once it is empty. This function should not be used
//! when FIFO mode is enabled.
//!
//! \note The data being sent must be left-justified in \e data. The lower
//! 16 - N bits will be discarded where N is the data width selected in
//! SPI_setConfig(). For example, if configured for a 6-bit data width, the
//! lower 10 bits of data will be discarded.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_writeDataBlockingNonFIFO(uint32_t base, uint16_t data)
{
//
// Check the arguments.
//
;
//
// Wait until the transmit buffer is not full.
//
while(((*((volatile uint16_t *)(base + 0x2U))) & 0x20U) != 0U)
{
}
//
// Write data to the transmit buffer.
//
(*((volatile uint16_t *)(base + 0x8U))) = data;
}
//*****************************************************************************
//
//! Waits for data to be received and then reads it from the buffer.
//!
//! \param base specifies the SPI module base address.
//!
//! This function waits for data to be received and then reads it from the
//! receive buffer of the specified SPI module. This function should not be
//! used when FIFO mode is enabled.
//!
//! \note Only the lower N bits of the value written to \e data contain valid
//! data, where N is the data width as configured by SPI_setConfig(). For
//! example, if the interface is configured for 8-bit data width, only the
//! lower 8 bits of the value written to \e data contain valid data.
//!
//! \return Returns the word of data read from the SPI receive buffer.
//
//*****************************************************************************
static inline uint16_t
SPI_readDataBlockingNonFIFO(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Wait until data has been received.
//
while(((*((volatile uint16_t *)(base + 0x2U))) & 0x40U) == 0U)
{
}
//
// Check for data to read.
//
return((*((volatile uint16_t *)(base + 0x7U))));
}
//*****************************************************************************
//
//! Enables SPI 3-wire mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function enables 3-wire mode. When in controller mode, this allows
//! SPIPICO to become SPICOCI and SPIPOCI to become free for non-SPI use.
//! When in peripheral mode, SPIPOCI because the SPIPIPO pin and SPIPICO is
//! free for non-SPI use.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableTriWire(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the tri-wire bit to enable 3-wire mode.
//
(*((volatile uint16_t *)(base + 0xFU))) |= 0x1U;
}
//*****************************************************************************
//
//! Disables SPI 3-wire mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function disables 3-wire mode. SPI will operate in normal 4-wire mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableTriWire(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear the tri-wire bit to disable 3-wire mode.
//
(*((volatile uint16_t *)(base + 0xFU))) &= ~0x1U;
}
//*****************************************************************************
//
//! Enables SPI loopback mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function enables loopback mode. This mode is only valid during
//! controller mode and is helpful during device testing as it internally
//! connects PICO and POCI.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the bit that enables loopback mode.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x10U;
}
//*****************************************************************************
//
//! Disables SPI loopback mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function disables loopback mode. Loopback mode is disabled by default
//! after reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableLoopback(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear the bit that enables loopback mode.
//
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x10U;
}
//*****************************************************************************
//
//! Set the peripheral select (SPIPTE) signal polarity.
//!
//! \param base is the base address of the SPI port.
//! \param polarity is the SPIPTE signal polarity.
//!
//! This function sets the polarity of the peripheral select (SPIPTE) signal.
//! The two modes to choose from for the \e polarity parameter are
//! \b SPI_PTE_ACTIVE_LOW for active-low polarity (typical) and
//! \b SPI_PTE_ACTIVE_HIGH for active-high polarity (considered inverted).
//!
//! \note This has no effect on the PTE signal when in controller mode. It is
//! only applicable to peripheral mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setPTESignalPolarity(uint32_t base, SPI_PTEPolarity polarity)
{
//
// Check the arguments.
//
;
//
// Write the polarity of the SPIPTE signal to the register.
//
(*((volatile uint16_t *)(base + 0xFU))) = ((*((volatile uint16_t *)(base + 0xFU))) & ~0x2U) |
(uint16_t)polarity;
}
//*****************************************************************************
//
//! Enables SPI high speed mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function enables high speed mode.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_enableHighSpeedMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the bit that enables high speed mode.
//
(*((volatile uint16_t *)(base + 0x0U))) |= 0x20U;
}
//*****************************************************************************
//
//! Disables SPI high speed mode.
//!
//! \param base is the base address of the SPI port.
//!
//! This function disables high speed mode. High speed mode is disabled by
//! default after reset.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_disableHighSpeedMode(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Clear the bit that enables high speed mode.
//
(*((volatile uint16_t *)(base + 0x0U))) &= ~0x20U;
}
//*****************************************************************************
//
//! Sets SPI emulation mode.
//!
//! \param base is the base address of the SPI port.
//! \param mode is the emulation mode.
//!
//! This function sets the behavior of the SPI operation when an emulation
//! suspend occurs. The \e mode parameter can be one of the following:
//!
//! - \b SPI_EMULATION_STOP_MIDWAY - Transmission stops midway through the bit
//! stream. The rest of the bits will be transmitting after the suspend is
//! deasserted.
//! - \b SPI_EMULATION_STOP_AFTER_TRANSMIT - If the suspend occurs before the
//! first SPICLK pulse, the transmission will not start. If it occurs later,
//! the transmission will be completed.
//! - \b SPI_EMULATION_FREE_RUN - SPI operation continues regardless of a
//! the suspend.
//!
//! \return None.
//
//*****************************************************************************
static inline void
SPI_setEmulationMode(uint32_t base, SPI_EmulationMode mode)
{
//
// Check the arguments.
//
;
//
// Write the desired emulation mode to the register.
//
(*((volatile uint16_t *)(base + 0xFU))) = ((*((volatile uint16_t *)(base + 0xFU))) &
~(0x10U | 0x20U)) |
(uint16_t)mode;
}
//*****************************************************************************
//
//! Configures the FIFO Transmit Delay
//!
//! \param base is the base address of the SPI port.
//! \param delay Tx FIFO delay to be configured in cycles (0..0xFF)
//!
//! This function sets the delay between every transfer from FIFO
//! transmit buffer to transmit shift register. The delay is defined in
//! number SPI serial clock cycles.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_setTxFifoTransmitDelay(uint32_t base, uint16_t delay)
{
//
// Check the arguments.
//
;
;
//
// Configure the FIFO Transmit Delay Bits
//
(*((volatile uint16_t *)(base + 0xCU))) = delay;
}
//*****************************************************************************
//
//! Returns the Emulation Buffer Received Data
//!
//! \param base is the base address of the SPI port.
//!
//! This function returns the Emulation Buffer Received Data
//!
//! \return Rx emulation buffer data
//
//*****************************************************************************
static inline uint16_t
SPI_readRxEmulationBuffer(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Return Emulation Buffer Received Data
//
return((*((volatile uint16_t *)(base + 0x6U))));
}
//*****************************************************************************
//
//! Enable Trasnmit
//!
//! \param base is the base address of the SPI port.
//!
//! This function sets the TALK bit enabling the data trasnmission.
//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as
//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_enableTalk(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the TALK bit
//
(*((volatile uint16_t *)(base + 0x1U))) |= 0x2U;
}
//*****************************************************************************
//
//! Disable Trasnmit
//!
//! \param base is the base address of the SPI port.
//!
//! This function clears the TALK bit disabling the data trasnmission. The
//! output pin will be put in high-impedance state.
//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as
//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_disableTalk(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Set the TALK bit
//
(*((volatile uint16_t *)(base + 0x1U))) &= ~0x2U;
}
//*****************************************************************************
//
//! Reset SPI transmit and receive channels
//!
//! \param base is the base address of the SPI port.
//!
//! This function resets the SPI transmit and receive channels.
//!
//! \return None
//
//*****************************************************************************
static inline void
SPI_reset(uint32_t base)
{
//
// Check the arguments.
//
;
//
// Write to SPRST bit the TX FIFO.
//
(*((volatile uint16_t *)(base + 0xAU))) &= ~0x8000U;
(*((volatile uint16_t *)(base + 0xAU))) |= 0x8000U;
}
//*****************************************************************************
//
//! Configures the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//! \param lspclkHz is the rate of the clock supplied to the SPI module
//! (LSPCLK) in Hz.
//! \param protocol specifies the data transfer protocol.
//! \param mode specifies the mode of operation.
//! \param bitRate specifies the clock rate in Hz.
//! \param dataWidth specifies number of bits transferred per frame.
//!
//! This function configures the serial peripheral interface. It sets the SPI
//! protocol, mode of operation, bit rate, and data width.
//!
//! The \e protocol parameter defines the data frame format. The \e protocol
//! parameter can be one of the following values: \b SPI_PROT_POL0PHA0,
//! \b SPI_PROT_POL0PHA1, \b SPI_PROT_POL1PHA0, or
//! \b SPI_PROT_POL1PHA1. These frame formats encode the following polarity
//! and phase configurations:
//!
//!
//! Polarity Phase Mode
//! 0 0 SPI_PROT_POL0PHA0
//! 0 1 SPI_PROT_POL0PHA1
//! 1 0 SPI_PROT_POL1PHA0
//! 1 1 SPI_PROT_POL1PHA1
//!
//!
//! The \e mode parameter defines the operating mode of the SPI module. The
//! SPI module can operate as a controller or peripheral; the SPI can also be be
//! configured to disable output on its serial output line. The \e mode
//! parameter can be one of the following values: \b SPI_MODE_CONTROLLER,
//! \b SPI_MODE_PERIPHERAL, \b SPI_MODE_CONTROLLER_OD or
//! \b SPI_MODE_PERIPHERAL_OD ("OD" indicates "output disabled").
//!
//! The \e bitRate parameter defines the bit rate for the SPI. This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - \e bitRate can be no greater than lspclkHz divided by 4.
//! - \e lspclkHz / \e bitRate cannot be greater than 128.
//!
//! The \e dataWidth parameter defines the width of the data transfers and
//! can be a value between 1 and 16, inclusive.
//!
//! The peripheral clock is the low speed peripheral clock. This value is
//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtl_getLowSpeedClock()).
//!
//! \note SPI operation should be disabled via SPI_disableModule() before any
//! changes to its configuration.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol,
SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth);
//*****************************************************************************
//
//! Configures the baud rate of the serial peripheral interface.
//!
//! \param base specifies the SPI module base address.
//! \param lspclkHz is the rate of the clock supplied to the SPI module
//! (LSPCLK) in Hz.
//! \param bitRate specifies the clock rate in Hz.
//!
//! This function configures the SPI baud rate. The \e bitRate parameter
//! defines the bit rate for the SPI. This bit rate must satisfy the following
//! clock ratio criteria:
//!
//! - \e bitRate can be no greater than \e lspclkHz divided by 4.
//! - \e lspclkHz / \e bitRate cannot be greater than 128.
//!
//! The peripheral clock is the low speed peripheral clock. This value is
//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtl_getLowSpeedClock()).
//!
//! \note SPI_setConfig() also sets the baud rate. Use SPI_setBaudRate()
//! if you wish to configure it separately from protocol and mode.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate);
//*****************************************************************************
//
//! Enables individual SPI interrupt sources.
//!
//! \param base specifies the SPI module base address.
//! \param intFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated SPI interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor. The \e intFlags parameter can be
//! any of the following values:
//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt
//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty
//! - \b SPI_INT_RXFF (also enables \b SPI_INT_RXFF_OVERFLOW) - RX FIFO level
//! interrupt (and RX FIFO overflow)
//! - \b SPI_INT_TXFF - TX FIFO level interrupt
//!
//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY,
//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with
//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_enableInterrupt(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Disables individual SPI interrupt sources.
//!
//! \param base specifies the SPI module base address.
//! \param intFlags is a bit mask of the interrupt sources to be disabled.
//!
//! This function disables the indicated SPI interrupt sources. The
//! \e intFlags parameter can be any of the following values:
//! - \b SPI_INT_RX_OVERRUN
//! - \b SPI_INT_RX_DATA_TX_EMPTY
//! - \b SPI_INT_RXFF (also disables \b SPI_INT_RXFF_OVERFLOW)
//! - \b SPI_INT_TXFF
//!
//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY,
//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with
//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_disableInterrupt(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param base specifies the SPI module base address.
//!
//! This function returns the interrupt status for the SPI module.
//!
//! \return The current interrupt status, enumerated as a bit field of the
//! following values:
//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt
//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty
//! - \b SPI_INT_RXFF - RX FIFO level interrupt
//! - \b SPI_INT_RXFF_OVERFLOW - RX FIFO overflow
//! - \b SPI_INT_TXFF - TX FIFO level interrupt
//
//*****************************************************************************
extern uint32_t
SPI_getInterruptStatus(uint32_t base);
//*****************************************************************************
//
//! Clears SPI interrupt sources.
//!
//! \param base specifies the SPI module base address.
//! \param intFlags is a bit mask of the interrupt sources to be cleared.
//!
//! This function clears the specified SPI interrupt sources so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep the interrupts from being triggered again immediately upon exit. The
//! \e intFlags parameter can consist of a bit field of the following values:
//! - \b SPI_INT_RX_OVERRUN
//! - \b SPI_INT_RX_DATA_TX_EMPTY
//! - \b SPI_INT_RXFF
//! - \b SPI_INT_RXFF_OVERFLOW
//! - \b SPI_INT_TXFF
//!
//! \note \b SPI_INT_RX_DATA_TX_EMPTY is cleared by a read of the receive
//! receive buffer, so it usually doesn't need to be cleared using this
//! function.
//!
//! \note Also note that \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY,
//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with
//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT.
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags);
//*****************************************************************************
//
//! This function can be used to transmit a 24-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function can be used to transmit a 24-bit word of data.
//! 24-bit word data is divided into three bytes of data.
//!
//! This function uses SPI_pollingFIFOTransaction function.
//! SPI character length is hardcoded to 8 (8bits) of character length
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay);
//*****************************************************************************
//
//! This function can be used to transmit a 32-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param txData is the data to be transmitted over SPI
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function can be used to transmit a 32-bit word of data.
//! 32-bit word data is divided into four bytes of data.
//!
//! This function uses SPI_pollingFIFOTransaction function.
//! SPI character length is hardcoded to 8 (8bits) of character length
//!
//! \return None.
//
//*****************************************************************************
extern void
SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay);
//*****************************************************************************
//
//! This function is used to receive a 16-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param endianness specifies the endianess of received data
//! \param dummyData is the data which is transmitted to initiate
//! SPI transaction to receive SPI data
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function is used to receive a 16-bit word of data.
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return the received 16-bit word.
//
//*****************************************************************************
extern uint16_t
SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
uint16_t txDelay);
//*****************************************************************************
//
//! This function is used to receive a 24-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param endianness specifies the endianess of received data
//! \param dummyData is the data which is transmitted to initiate
//! SPI transaction to receive SPI data
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function is used to receive a 24-bit word of data.
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return the received 24-bit word.
//
//*****************************************************************************
extern uint32_t
SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
uint16_t txDelay);
//*****************************************************************************
//
//! This function is used to receive a 32-bit word of data
//!
//! \param base specifies the SPI module base address.
//! \param endianness specifies the endianess of received data
//! \param dummyData is the data which is transmitted to initiate
//! SPI transaction to receive SPI data
//! \param txDelay specifies the number of serial clock cycles delay time after
//! completion of perious word
//!
//! This function is used to receive a 32-bit word of data.
//! This function uses SPIpolling_FIFO_Transaction function.
//! SPI character length is hardcoded to 8 (1 byte = 8 bits)of character length
//!
//! \return the received 32-bit word.
//
//*****************************************************************************
extern uint32_t
SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData,
uint16_t txDelay);
//*****************************************************************************
//
//! This function is used to initiate SPI transaction of specified character
//! length
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the SPI character length of SPI transaction
//! \param data specified the data to be transmitted
//!
//! This function is used to initiate SPI transaction of specified character.
//! SPI character length is configurable using charLength variable
//!
//! \return .
//
//*****************************************************************************
extern uint16_t
SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength,
uint16_t data);
//*****************************************************************************
//
//! This function is used to initiate SPI transaction of specified character
//! length and 'N' words of transaction
//!
//! \param base specifies the SPI module base address.
//! \param charLength specifies the SPI character length of SPI transaction
//! \param pTxBuffer specifies the pointer to transmit buffer
//! \param pRxBuffer specifies the pointer to receive buffer
//! \param numOfWords specified the number of data to be transmitted / received
//!
//! SPI character length is configurable using charLength variable
//!
//! \return none
//
//*****************************************************************************
extern void
SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength,
uint16_t *pTxBuffer, uint16_t *pRxBuffer,
uint16_t numOfWords, uint16_t txDelay);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//###########################################################################
//
// FILE: version.h
//
// TITLE: API to return the version number of the driverlib.lib in use.
//
//###########################################################################
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup version_api Version
//! @{
//
//*****************************************************************************
//! Version number to be returned by Version_getLibVersion()
//!
//*****************************************************************************
//
//! Returns the driverlib version number
//!
//! This function can be used to check the version number of the driverlib.lib
//! that is in use. The version number will take the format x.xx.xx.xx, so for
//! example, if the function returns 2100200, the driverlib version being used
//! is 2.10.02.00.
//!
//! \return Returns an integer value indicating the driverlib version.
//
//*****************************************************************************
extern uint32_t
Version_getLibVersion(void);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//*****************************************************************************
// CLB
//*****************************************************************************
//*****************************************************************************
// FSI
//*****************************************************************************
//*****************************************************************************
// LIN
//*****************************************************************************
//*****************************************************************************
// SPI
//*****************************************************************************
//*****************************************************************************
// Interrupt
//*****************************************************************************
//*****************************************************************************
// SysCtrl
//*****************************************************************************
//*****************************************************************************
// GPIO
//*****************************************************************************
//*****************************************************************************
// Memcfg
//*****************************************************************************
//*****************************************************************************
// I2C
//*****************************************************************************
//*****************************************************************************
// PMBUS
//*****************************************************************************
//*****************************************************************************
// SDFM
//*****************************************************************************
//#############################################################################
//
// FILE: device.h
//
// TITLE: Device setup for examples.
//
//#############################################################################
//
//
// $Copyright:
// Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
//
// Included Files
//
//
// Check for invalid compile flags
//
//*****************************************************************************
//
// Defines for pin numbers
//
//*****************************************************************************
//
// ControlCARD
//
//
// LEDs
//
//
// CANA
//
//
// SCI for USB-to-UART adapter on FTDI chip
//
//
// MCAN
//
//
// LINA
//
//
// LINB
//
//
// I2C
//
//I2CB GPIO pins
//
// FSI
//
//*****************************************************************************
//
// Defines related to clock configuration
//
//*****************************************************************************
//
// To use INTOSC as the clock source, comment the #define USE_PLL_SRC_XTAL,
// and uncomment the #define USE_PLL_SRC_INTOSC
//
//#define USE_PLL_SRC_INTOSC
//
// 20MHz XTAL on controlCARD is used as the PLL source.
// For use with SysCtl_getClock().
//
//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 20MHz (XTAL_OSC) * 48 (IMULT) / (2 (REFDIV) * 4 (ODIV) * 1(SYSDIV))
//
//
// 120MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
//
// 30MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default
// low speed peripheral clock divider of 4. Update the code below if a
// different LSPCLK divider is used!
//
//*****************************************************************************
//
// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro
// will convert the desired delay in microseconds to the count value expected
// by the function. \b x is the number of microseconds to delay.
//
//*****************************************************************************
//
// Defines for setting FSI clock speeds
//
//*****************************************************************************
//
// Defines, Globals, and Header Includes related to Flash Support
//
//*****************************************************************************
/*****************************************************************************/
/* stddef.h */
/* */
/* Copyright (c) 1993 Texas Instruments Incorporated */
/* http://www.ti.com/ */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in */
/* the documentation and/or other materials provided with the */
/* distribution. */
/* */
/* Neither the name of Texas Instruments Incorporated nor the names */
/* of its contributors may be used to endorse or promote products */
/* derived from this software without specific prior written */
/* permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* */
/*****************************************************************************/
_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.7\")") /* macros required for implementation */
_Pragma("CHECK_MISRA(\"-20.1\")") /* standard headers must define standard names */
_Pragma("CHECK_MISRA(\"-20.2\")") /* standard headers must define standard names */
typedef long ptrdiff_t;
typedef unsigned long size_t;
typedef unsigned long wchar_t;
/*----------------------------------------------------------------------------*/
/* C++11 and C11 required max_align_t to be defined. The libc++ cstddef */
/* header expects the macro __DEFINED_max_align_t to be defined if it is to */
/* use the definintion of max_align_t from stddef.h. Only define it if */
/* compiling for C11 or we're in non strict ansi mode. */
/*----------------------------------------------------------------------------*/
typedef long double max_align_t;
_Pragma("diag_push")
_Pragma("CHECK_MISRA(\"-19.10\")") /* need types as macro arguments */
_Pragma("diag_pop")
_Pragma("diag_pop")
extern uint16_t RamfuncsLoadStart;
extern uint16_t RamfuncsLoadEnd;
extern uint16_t RamfuncsLoadSize;
extern uint16_t RamfuncsRunStart;
extern uint16_t RamfuncsRunEnd;
extern uint16_t RamfuncsRunSize;
//*****************************************************************************
//
// Function Prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup device_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
//! @brief Function to initialize the device. Primarily initializes system
//! control to aknown state by disabling the watchdog, setting up the
//! SYSCLKOUT frequency, and enabling the clocks to the peripherals.
//!
//! \param None.
//! \return None.
//
//*****************************************************************************
extern void Device_init(void);
//*****************************************************************************
//
//!
//! @brief Function to verify the XTAL frequency
//! \param freq is the XTAL frequency in MHz
//! \return The function return true if the the actual XTAL frequency matches with the
//! input value
//
//*****************************************************************************
extern _Bool Device_verifyXTAL(float freq);
//*****************************************************************************
//!
//!
//! @brief Function to turn on all peripherals, enabling reads and writes to the
//! peripherals' registers.
//!
//! Note that to reduce power, unused peripherals should be disabled.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_enableAllPeripherals(void);
//*****************************************************************************
//!
//!
//! @brief Function to disable pin locks on GPIOs.
//!
//! @param None
//! @return None
//
//*****************************************************************************
extern void Device_initGPIO(void);
//*****************************************************************************
//!
//! @brief Error handling function to be called when an ASSERT is violated
//!
//! @param *filename File name in which the error has occurred
//! @param line Line number within the file
//! @return None
//
//*****************************************************************************
extern void __error__(const char *filename, uint32_t line);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//
// Defines
//
struct myDataStruct_s{
float data1;
float data2;
float data3;
float data4;
float data5;
float data6;
float data7;
float data8;
float data9;
float data10;
float data11;
float data12;
float data13;
float data14;
float data15;
float data16;
float data17;
float data18;
float data19;
float data20;
};
volatile extern struct myDataStruct_s mds_cpu2cla;
//
// Globals
//
//Task 1 (C) Variables
extern float duty;
//Task 2 (C) Variables
//Task 3 (C) Variables
//Task 4 (C) Variables
//Task 5 (C) Variables
//Task 6 (C) Variables
//Task 7 (C) Variables
//Task 8 (C) Variables
//Common (C) Variables
//
// Function Prototypes
//
__attribute__((interrupt)) void Cla1Task1();
__attribute__((interrupt)) void Cla1Task2();
__attribute__((interrupt)) void Cla1Task3();
__attribute__((interrupt)) void Cla1Task4();
__attribute__((interrupt)) void Cla1Task5();
__attribute__((interrupt)) void Cla1Task6();
__attribute__((interrupt)) void Cla1Task7();
__attribute__((interrupt)) void Cla1Task8();
//
// End of File
//
/*
* Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
//
// Included Files
//
//*****************************************************************************
//
// PinMux Configurations
//
//*****************************************************************************
//*****************************************************************************
//
// CLA Configurations
//
//*****************************************************************************
//
// The following are symbols defined in the CLA assembly code
// Including them in the shared header file makes them global
// and the main CPU can make use of them.
//
__attribute__((interrupt)) void Cla1Task1();
__attribute__((interrupt)) void Cla1Task2();
__attribute__((interrupt)) void Cla1Task3();
__attribute__((interrupt)) void Cla1Task4();
__attribute__((interrupt)) void Cla1Task5();
__attribute__((interrupt)) void Cla1Task6();
__attribute__((interrupt)) void Cla1Task7();
__attribute__((interrupt)) void Cla1Task8();
void myCLA0_init();
//*****************************************************************************
//
// MEMCFG Configurations
//
//*****************************************************************************
//*****************************************************************************
//
// Board Configurations
//
//*****************************************************************************
void Board_init();
void CLA_init();
void MEMCFG_init();
void PinMux_init();
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
//
// Function Prototypes
//
void initEPWM(void);
void initCLA(void);
extern uint32_t LUTLOADSTART;
extern uint32_t LUTRUNSTART;
extern uint32_t LUTLOADSIZE;
volatile struct myDataStruct_s mds_cpu2cla;
#pragma DATA_SECTION(mds_cpu2cla,"CpuToCla1MsgRAM")
//
// Main
//
void main(void)
{
//
// Initialize device clock and peripherals
//
Device_init();
//
// Disable pin locks and enable internal pullups.
//
Device_initGPIO();
//
// GPIO0 is set to EPWM1A
// GPIO1 is set to EPWM1B
//
// GPIO_setControllerCore(0, GPIO_CORE_CPU1);
// GPIO_setPadConfig(0,GPIO_PIN_TYPE_STD);
// GPIO_setPinConfig(GPIO_0_EPWM1_A);
// GPIO_setControllerCore(1, GPIO_CORE_CPU1);
// GPIO_setPadConfig(1,GPIO_PIN_TYPE_STD);
// GPIO_setPinConfig(GPIO_1_EPWM1_B);
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
//
// Disable sync(Freeze clock to PWM as well)
//
SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
//
// Initialize EPWM module
//
initEPWM();
//
// Initialize resources
//
Board_init();
initCLA();
//
// Enable global interrupts.
//
__asm(" clrc INTM");
//
// Enable sync and clock to PWM
//
SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);
for(;;)
{
}
}
//
// EPWM Initialization
// EPWM1 : generates output of frequency EPWM1_FREQ (100 KHz)
// EPWM4 : Triggers CLA task at frequency EPWM4_FREQ (10 KHz)
//
void initEPWM(void)
{
//
// Set up EPWM1 to
// - run on a base clock of SYSCLK
// - have a period of EPWM1_PERIOD
// - run in count up-down mode
//
EPWM_setClockPrescaler(0x00004000U, EPWM_CLOCK_DIVIDER_1,
EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(0x00004000U, (uint16_t)(((20000000U * 48) / (2 * 4 * 1)) / (2 * 100000UL)));
EPWM_setCounterCompareValue(0x00004000U, EPWM_COUNTER_COMPARE_A, (uint16_t)(((20000000U * 48) / (2 * 4 * 1)) / (2 * 100000UL))/10U);
EPWM_setTimeBaseCounterMode(0x00004000U, EPWM_COUNTER_MODE_UP_DOWN);
EPWM_setTimeBaseCounter(0x00004000U, 0U);
//
// Configuring action-qualifiers for EPWM1 to generate symmetric
// and complementary outputs on channel A and B
//
EPWM_setActionQualifierAction(0x00004000U, EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(0x00004000U, EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
EPWM_setActionQualifierAction(0x00004000U, EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(0x00004000U, EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
//
// Enabling Counter Compare shadow mode
//
EPWM_setCounterCompareShadowLoadMode(0x00004000U, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO);
//
// Set up EPWM4 to
// - run on a base clock of SYSCLK
// - have a period of EPWM4_PERIOD
// - run in count up mode
EPWM_setClockPrescaler(0x00004300U, EPWM_CLOCK_DIVIDER_1,
EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(0x00004300U, (uint16_t)(((20000000U * 48) / (2 * 4 * 1)) / 10000UL));
EPWM_setTimeBaseCounterMode(0x00004300U, EPWM_COUNTER_MODE_UP);
EPWM_setTimeBaseCounter(0x00004300U, 0U);
//
// Enabling EPWM4 interrupt at TBCTR = 0 to trigger
// CLA task
//
EPWM_setInterruptSource(0x00004300U, 1U);
EPWM_enableInterrupt(0x00004300U);
EPWM_setInterruptEventCount(0x00004300U, 1U);
EPWM_setClockPrescaler(0x00004200U, EPWM_CLOCK_DIVIDER_1,
EPWM_HSCLOCK_DIVIDER_1);
EPWM_setTimeBasePeriod(0x00004200U, 32000U);
EPWM_setCounterCompareValue(0x00004200U,EPWM_COUNTER_COMPARE_A,0);
EPWM_setTimeBaseCounterMode(0x00004200U, EPWM_COUNTER_MODE_UP);
EPWM_setTimeBaseCounter(0x00004200U, 0U);
//
// EPWM 1 and 4 should run freely in emulation mode
//
EPWM_setEmulationMode(0x00004000U, EPWM_EMULATION_FREE_RUN);
EPWM_setEmulationMode(0x00004200U, EPWM_EMULATION_FREE_RUN);
EPWM_setEmulationMode(0x00004300U, EPWM_EMULATION_FREE_RUN);
}
//
// CLA Initialization
//
void initCLA(void)
{
memcpy((uint32_t *)&LUTRUNSTART, (uint32_t *)&LUTLOADSTART,
(uint32_t)&LUTLOADSIZE );
//
// Force task 8, the one time initialization task
//
CLA_forceTasks(0x00001400U, (0x80U));
}