1/*



2 * Academic License - for use in teaching, academic research, and meeting



3 * course requirements at degree granting institutions only.  Not for



4 * government, commercial, or other organizational use.



5 *



6 * File: TwoPhaseForStuck.c



7 *



8 * Code generated for Simulink model 'TwoPhaseForStuck'.



9 *



10 * Model version                  : 1.138



11 * Simulink Coder version         : 9.0 (R2018b) 24-May-2018



12 * C/C++ source code generated on : Tue Dec  8 01:36:02 2020



13 *



14 * Target selection: ert.tlc



15 * Embedded hardware selection: Texas Instruments->C2000



16 * Code generation objectives: Unspecified



17 * Validation result: Not run



18 */



19



20#include "TwoPhaseForStuck.h"



21#include "TwoPhaseForStuck_private.h"



22



23/* Block signals (default storage) */



24B_TwoPhaseForStuck_T TwoPhaseForStuck_B;



25



26/* Real-time model */



27RT_MODEL_TwoPhaseForStuck_T TwoPhaseForStuck_M_;



28RT_MODEL_TwoPhaseForStuck_T *const TwoPhaseForStuck_M = &TwoPhaseForStuck_M_;



29static uint16_T adcBInitFlag = 0;



30static uint16_T adcAInitFlag = 0;



31



32/* Model step function */



33void TwoPhaseForStuck_step(void)



34{



35  /* local block i/o variables */



36  real_T rtb_TMPRRD;



37



38  /* S-Function (c2802xadc): '<Root>/ADC' */



39  {



40    /*  Internal Reference Voltage : Fixed scale 0 to 3.3 V range.  */



41    /*  External Reference Voltage : Allowable ranges of VREFHI(ADCINA0) = 3.3 and VREFLO(tied to ground) = 0  */



42    TwoPhaseForStuck_B.ADC = (AdcbResultRegs.ADCRESULT1);



43  }



44



45  /* S-Function (c2802xadc): '<Root>/ADC_1' */



46  {



47    /*  Internal Reference Voltage : Fixed scale 0 to 3.3 V range.  */



48    /*  External Reference Voltage : Allowable ranges of VREFHI(ADCINA0) = 3.3 and VREFLO(tied to ground) = 0  */



49    TwoPhaseForStuck_B.ADC_1 = (AdcaResultRegs.ADCRESULT0);



50  }



51



52  /* S-Function (c2802xadc): '<Root>/ADC_2' */



53  {



54    /*  Internal Reference Voltage : Fixed scale 0 to 3.3 V range.  */



55    /*  External Reference Voltage : Allowable ranges of VREFHI(ADCINA0) = 3.3 and VREFLO(tied to ground) = 0  */



56    TwoPhaseForStuck_B.ADC_2 = (AdcbResultRegs.ADCRESULT0);



57  }



58



59  /* Gain: '<Root>/TMPRRD' incorporates:



60   *  Constant: '<Root>/DuryCycle'



61   */



62  rtb_TMPRRD = TwoPhaseForStuck_P.TMPRRD_Gain *



63    TwoPhaseForStuck_P.DuryCycle_Value;



64



65  /* S-Function (c2802xpwm): '<Root>/ePWM4' */



66



67  /*-- Update CMPA value for ePWM1 --*/



68  {



69    EPwm1Regs.CMPA.bit.CMPA = (uint16_T)(rtb_TMPRRD);



70  }



71



72  /* S-Function (c2802xpwm): '<Root>/ePWM5' incorporates:



73   *  Constant: '<Root>/Phase_2'



74   */



75  EPwm2Regs.TBPHS.bit.TBPHS = TwoPhaseForStuck_P.Phase_2_Value;



76



77  /*-- Update CMPA value for ePWM2 --*/



78  {



79    EPwm2Regs.CMPA.bit.CMPA = (uint16_T)(rtb_TMPRRD);



80  }



81}



82



83/* Model initialize function */



84void TwoPhaseForStuck_initialize(void)



85{



86  /* Registration code */



87



88  /* initialize error status */



89  rtmSetErrorStatus(TwoPhaseForStuck_M, (NULL));



90



91  /* block I/O */



92  (void) memset(((void *) &TwoPhaseForStuck_B), 0,



93                sizeof(B_TwoPhaseForStuck_T));



94



95  /* Start for S-Function (c2802xadc): '<Root>/ADC' */



96  if (adcBInitFlag == 0) {



97    InitAdcB();



98    adcBInitFlag = 1;



99  }



100



101  config_ADCB_SOC1 ();



102



103  /* Start for S-Function (c2802xadc): '<Root>/ADC_1' */



104  if (adcAInitFlag == 0) {



105    InitAdcA();



106    adcAInitFlag = 1;



107  }



108



109  config_ADCA_SOC0 ();



110



111  /* Start for S-Function (c2802xadc): '<Root>/ADC_2' */



112  if (adcBInitFlag == 0) {



113    InitAdcB();



114    adcBInitFlag = 1;



115  }



116



117  config_ADCB_SOC0 ();



118



119  /* Start for S-Function (c2802xpwm): '<Root>/ePWM4' */



120  EALLOW;



121  CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;



122  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;



123  EDIS;



124



125  /*** Initialize ePWM1 modules ***/



126  {



127    /*  // Time Base Control Register



128       EPwm1Regs.TBCTL.bit.CTRMODE              = 0;          // Counter Mode



129       EPwm1Regs.TBCTL.bit.SYNCOSEL             = 1;          // Sync Output Select



130       EPwm1Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select



131       EPwm1Regs.TBCTL.bit.PHSEN                = 0;          // Phase Load Enable



132       EPwm1Regs.TBCTL.bit.PHSDIR               = 0;          // Phase Direction Bit



133       EPwm1Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler



134       EPwm1Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler



135       EPwm1Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse



136     */



137    EPwm1Regs.TBCTL.all = (EPwm1Regs.TBCTL.all & ~0x3FFF) | 0x10;



138



139    /*-- Setup Time-Base (TB) Submodule --*/



140    EPwm1Regs.TBPRD = 999;             // Time Base Period Register



141



142    /* // Time-Base Phase Register



143       EPwm1Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register



144     */



145    EPwm1Regs.TBPHS.all = (EPwm1Regs.TBPHS.all & ~0xFFFF0000) | 0x0;



146



147    // Time Base Counter Register



148    EPwm1Regs.TBCTR = 0x0000;          /* Clear counter*/



149



150    /*-- Setup Counter_Compare (CC) Submodule --*/



151    /*	// Counter Compare Control Register



152       EPwm1Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode



153       EPwm1Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode



154       EPwm1Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load



155       EPwm1Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load



156     */



157    EPwm1Regs.CMPCTL.all = (EPwm1Regs.CMPCTL.all & ~0x5F) | 0x0;



158



159    /* EPwm1Regs.CMPCTL2.bit.SHDWCMODE           = 0;  // Compare C Register Block Operating Mode



160



161       EPwm1Regs.CMPCTL2.bit.SHDWDMODE           = 0;  // Compare D Register Block Operating Mode



162     */



163    EPwm1Regs.CMPCTL2.all = (EPwm1Regs.CMPCTL2.all & ~0x50) | 0x0;



164    EPwm1Regs.CMPA.bit.CMPA = 0;       // Counter Compare A Register



165    EPwm1Regs.CMPB.bit.CMPB = 0;       // Counter Compare B Register



166    EPwm1Regs.CMPC = 0;                // Counter Compare C Register



167    EPwm1Regs.CMPD = 0;                // Counter Compare D Register



168



169    /*-- Setup Action-Qualifier (AQ) Submodule --*/



170    EPwm1Regs.AQCTLA.all = 33;         // Action Qualifier Control Register For Output A



171    EPwm1Regs.AQCTLB.all = 96;         // Action Qualifier Control Register For Output B



172



173    /*	// Action Qualifier Software Force Register



174       EPwm1Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options



175     */



176    EPwm1Regs.AQSFRC.all = (EPwm1Regs.AQSFRC.all & ~0xC0) | 0x0;



177



178    /*	// Action Qualifier Continuous S/W Force Register



179       EPwm1Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A



180       EPwm1Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B



181     */



182    EPwm1Regs.AQCSFRC.all = (EPwm1Regs.AQCSFRC.all & ~0xF) | 0x0;



183



184    /*-- Setup Dead-Band Generator (DB) Submodule --*/



185    /*	// Dead-Band Generator Control Register



186       EPwm1Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control



187       EPwm1Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control



188       EPwm1Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control



189       EPwm1Regs.DBCTL.bit.HALFCYCLE            = 0;          // Half Cycle Clocking Enable



190     */



191    EPwm1Regs.DBCTL.all = (EPwm1Regs.DBCTL.all & ~0x803F) | 0xB;



192    EPwm1Regs.DBRED.bit.DBRED = 20;    // Dead-Band Generator Rising Edge Delay Count Register



193    EPwm1Regs.DBFED.bit.DBFED = 20;    // Dead-Band Generator Falling Edge Delay Count Register



194



195    /*-- Setup Event-Trigger (ET) Submodule --*/



196    /*	// Event Trigger Selection and Pre-Scale Register



197       EPwm1Regs.ETSEL.bit.SOCAEN               = 1;          // Start of Conversion A Enable



198       EPwm1Regs.ETSEL.bit.SOCASELCMP = 0;



199       EPwm1Regs.ETSEL.bit.SOCASEL              = 4 ;          // Start of Conversion A Select



200       EPwm1Regs.ETPS.bit.SOCAPRD               = 1;          // EPWM1SOCA Period Select



201



202       EPwm1Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable



203



204       EPwm1Regs.ETSEL.bit.SOCBSELCMP = 0;



205       EPwm1Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select



206       EPwm1Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM1SOCB Period Select



207       EPwm1Regs.ETSEL.bit.INTEN                = 0;          // EPWM1INTn Enable



208       EPwm1Regs.ETSEL.bit.INTSELCMP = 0;



209       EPwm1Regs.ETSEL.bit.INTSEL              = 4;          // Start of Conversion A Select



210



211       EPwm1Regs.ETPS.bit.INTPRD                = 1;          // EPWM1INTn Period Select



212     */



213    EPwm1Regs.ETSEL.all = (EPwm1Regs.ETSEL.all & ~0xFF7F) | 0x1C04;



214    EPwm1Regs.ETPS.all = (EPwm1Regs.ETPS.all & ~0x3303) | 0x1101;



215



216    /*-- Setup PWM-Chopper (PC) Submodule --*/



217    /*	// PWM Chopper Control Register



218       EPwm1Regs.PCCTL.bit.CHPEN                = 0;          // PWM chopping enable



219       EPwm1Regs.PCCTL.bit.CHPFREQ              = 0;          // Chopping clock frequency



220       EPwm1Regs.PCCTL.bit.OSHTWTH              = 0;          // One-shot pulse width



221       EPwm1Regs.PCCTL.bit.CHPDUTY              = 0;          // Chopping clock Duty cycle



222     */



223    EPwm1Regs.PCCTL.all = (EPwm1Regs.PCCTL.all & ~0x7FF) | 0x0;



224



225    /*-- Set up Trip-Zone (TZ) Submodule --*/



226    EALLOW;



227    EPwm1Regs.TZSEL.all = 0;           // Trip Zone Select Register



228



229    /*	// Trip Zone Control Register



230       EPwm1Regs.TZCTL.bit.TZA                  = 3;          // TZ1 to TZ6 Trip Action On EPWM1A



231       EPwm1Regs.TZCTL.bit.TZB                  = 3;          // TZ1 to TZ6 Trip Action On EPWM1B



232       EPwm1Regs.TZCTL.bit.DCAEVT1              = 3;          // EPWM1A action on DCAEVT1



233       EPwm1Regs.TZCTL.bit.DCAEVT2              = 3;          // EPWM1A action on DCAEVT2



234       EPwm1Regs.TZCTL.bit.DCBEVT1              = 3;          // EPWM1B action on DCBEVT1



235       EPwm1Regs.TZCTL.bit.DCBEVT2              = 3;          // EPWM1B action on DCBEVT2



236     */



237    EPwm1Regs.TZCTL.all = (EPwm1Regs.TZCTL.all & ~0xFFF) | 0xFFF;



238



239    /*	// Trip Zone Enable Interrupt Register



240       EPwm1Regs.TZEINT.bit.OST                 = 0;          // Trip Zones One Shot Int Enable



241       EPwm1Regs.TZEINT.bit.CBC                 = 0;          // Trip Zones Cycle By Cycle Int Enable



242       EPwm1Regs.TZEINT.bit.DCAEVT1             = 0;          // Digital Compare A Event 1 Int Enable



243       EPwm1Regs.TZEINT.bit.DCAEVT2             = 0;          // Digital Compare A Event 2 Int Enable



244       EPwm1Regs.TZEINT.bit.DCBEVT1             = 0;          // Digital Compare B Event 1 Int Enable



245       EPwm1Regs.TZEINT.bit.DCBEVT2             = 0;          // Digital Compare B Event 2 Int Enable



246     */



247    EPwm1Regs.TZEINT.all = (EPwm1Regs.TZEINT.all & ~0x7E) | 0x0;



248



249    /*	// Digital Compare A Control Register



250       EPwm1Regs.DCACTL.bit.EVT1SYNCE           = 0;          // DCAEVT1 SYNC Enable



251       EPwm1Regs.DCACTL.bit.EVT1SOCE            = 1;          // DCAEVT1 SOC Enable



252       EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL      = 0;          // DCAEVT1 Force Sync Signal



253       EPwm1Regs.DCACTL.bit.EVT1SRCSEL          = 0;          // DCAEVT1 Source Signal



254       EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL      = 0;          // DCAEVT2 Force Sync Signal



255       EPwm1Regs.DCACTL.bit.EVT2SRCSEL          = 0;          // DCAEVT2 Source Signal



256     */



257    EPwm1Regs.DCACTL.all = (EPwm1Regs.DCACTL.all & ~0x30F) | 0x4;



258



259    /*	// Digital Compare B Control Register



260       EPwm1Regs.DCBCTL.bit.EVT1SYNCE           = 0;          // DCBEVT1 SYNC Enable



261       EPwm1Regs.DCBCTL.bit.EVT1SOCE            = 0;          // DCBEVT1 SOC Enable



262       EPwm1Regs.DCBCTL.bit.EVT1FRCSYNCSEL      = 0;          // DCBEVT1 Force Sync Signal



263       EPwm1Regs.DCBCTL.bit.EVT1SRCSEL          = 0;          // DCBEVT1 Source Signal



264       EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL      = 0;          // DCBEVT2 Force Sync Signal



265       EPwm1Regs.DCBCTL.bit.EVT2SRCSEL          = 0;          // DCBEVT2 Source Signal



266     */



267    EPwm1Regs.DCBCTL.all = (EPwm1Regs.DCBCTL.all & ~0x30F) | 0x0;



268



269    /*	// Digital Compare Trip Select Register



270       EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL      = 0;          // Digital Compare A High COMP Input Select



271



272       EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL      = 1;          // Digital Compare A Low COMP Input Select



273       EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL      = 0;          // Digital Compare B High COMP Input Select



274       EPwm1Regs.DCTRIPSEL.bit.DCBLCOMPSEL      = 1;          // Digital Compare B Low COMP Input Select



275



276



277



278



279



280     */



281    EPwm1Regs.DCTRIPSEL.all = (EPwm1Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;



282



283    /*	// Trip Zone Digital Comparator Select Register



284       EPwm1Regs.TZDCSEL.bit.DCAEVT1            = 0;          // Digital Compare Output A Event 1



285       EPwm1Regs.TZDCSEL.bit.DCAEVT2            = 0;          // Digital Compare Output A Event 2



286       EPwm1Regs.TZDCSEL.bit.DCBEVT1            = 0;          // Digital Compare Output B Event 1



287       EPwm1Regs.TZDCSEL.bit.DCBEVT2            = 0;          // Digital Compare Output B Event 2



288     */



289    EPwm1Regs.TZDCSEL.all = (EPwm1Regs.TZDCSEL.all & ~0xFFF) | 0x0;



290



291    /*	// Digital Compare Filter Control Register



292       EPwm1Regs.DCFCTL.bit.BLANKE              = 0;          // Blanking Enable/Disable



293       EPwm1Regs.DCFCTL.bit.PULSESEL            = 1;          // Pulse Select for Blanking & Capture Alignment



294       EPwm1Regs.DCFCTL.bit.BLANKINV            = 0;          // Blanking Window Inversion



295       EPwm1Regs.DCFCTL.bit.SRCSEL              = 0;          // Filter Block Signal Source Select



296     */



297    EPwm1Regs.DCFCTL.all = (EPwm1Regs.DCFCTL.all & ~0x3F) | 0x10;



298    EPwm1Regs.DCFOFFSET = 0;           // Digital Compare Filter Offset Register



299    EPwm1Regs.DCFWINDOW = 0;           // Digital Compare Filter Window Register



300



301    /*	// Digital Compare Capture Control Register



302       EPwm1Regs.DCCAPCTL.bit.CAPE              = 0;          // Counter Capture Enable



303     */



304    EPwm1Regs.DCCAPCTL.all = (EPwm1Regs.DCCAPCTL.all & ~0x1) | 0x0;



305



306    /*	// HRPWM Configuration Register



307       EPwm1Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit



308       EPwm1Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit



309     */



310    EPwm1Regs.HRCNFG.all = (EPwm1Regs.HRCNFG.all & ~0xA0) | 0x0;



311



312    /* Update the Link Registers with the link value for all the Compare values and TBPRD */



313    /* No error is thrown if the ePWM register exists in the model or not */



314    EPwm1Regs.EPWMXLINK.bit.TBPRDLINK = 0;



315    EPwm1Regs.EPWMXLINK.bit.CMPALINK = 0;



316    EPwm1Regs.EPWMXLINK.bit.CMPBLINK = 0;



317    EPwm1Regs.EPWMXLINK.bit.CMPCLINK = 0;



318    EPwm1Regs.EPWMXLINK.bit.CMPDLINK = 0;



319    EDIS;



320    EALLOW;



321    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;



322    EDIS;



323  }



324



325  /* Start for S-Function (c2802xpwm): '<Root>/ePWM5' incorporates:



326   *  Constant: '<Root>/Phase_2'



327   */



328  EALLOW;



329  CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;



330  CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;



331  EDIS;



332



333  /*** Initialize ePWM2 modules ***/



334  {



335    /*  // Time Base Control Register



336       EPwm2Regs.TBCTL.bit.CTRMODE              = 0;          // Counter Mode



337       EPwm2Regs.TBCTL.bit.SYNCOSEL             = 0;          // Sync Output Select



338       EPwm2Regs.TBCTL.bit.PRDLD                = 0;          // Shadow select



339       EPwm2Regs.TBCTL.bit.PHSEN                = 1;          // Phase Load Enable



340       EPwm2Regs.TBCTL.bit.PHSDIR               = 0;          // Phase Direction Bit



341       EPwm2Regs.TBCTL.bit.HSPCLKDIV            = 0;          // High Speed TBCLK Pre-scaler



342       EPwm2Regs.TBCTL.bit.CLKDIV               = 0;          // Time Base Clock Pre-scaler



343       EPwm2Regs.TBCTL.bit.SWFSYNC              = 0;          // Software Force Sync Pulse



344     */



345    EPwm2Regs.TBCTL.all = (EPwm2Regs.TBCTL.all & ~0x3FFF) | 0x4;



346



347    /*-- Setup Time-Base (TB) Submodule --*/



348    EPwm2Regs.TBPRD = 999;             // Time Base Period Register



349



350    /* // Time-Base Phase Register



351       EPwm2Regs.TBPHS.bit.TBPHS               = 0;          // Phase offset register



352     */



353    EPwm2Regs.TBPHS.all = (EPwm2Regs.TBPHS.all & ~0xFFFF0000) | 0x0;



354



355    // Time Base Counter Register



356    EPwm2Regs.TBCTR = 0x0000;          /* Clear counter*/



357



358    /*-- Setup Counter_Compare (CC) Submodule --*/



359    /*	// Counter Compare Control Register



360       EPwm2Regs.CMPCTL.bit.SHDWAMODE           = 0;  // Compare A Register Block Operating Mode



361       EPwm2Regs.CMPCTL.bit.SHDWBMODE           = 0;  // Compare B Register Block Operating Mode



362       EPwm2Regs.CMPCTL.bit.LOADAMODE           = 0;          // Active Compare A Load



363       EPwm2Regs.CMPCTL.bit.LOADBMODE           = 0;          // Active Compare B Load



364     */



365    EPwm2Regs.CMPCTL.all = (EPwm2Regs.CMPCTL.all & ~0x5F) | 0x0;



366



367    /* EPwm2Regs.CMPCTL2.bit.SHDWCMODE           = 0;  // Compare C Register Block Operating Mode



368



369       EPwm2Regs.CMPCTL2.bit.SHDWDMODE           = 0;  // Compare D Register Block Operating Mode



370     */



371    EPwm2Regs.CMPCTL2.all = (EPwm2Regs.CMPCTL2.all & ~0x50) | 0x0;



372    EPwm2Regs.CMPA.bit.CMPA = 0;       // Counter Compare A Register



373    EPwm2Regs.CMPB.bit.CMPB = 0;       // Counter Compare B Register



374    EPwm2Regs.CMPC = 0;                // Counter Compare C Register



375    EPwm2Regs.CMPD = 0;                // Counter Compare D Register



376



377    /*-- Setup Action-Qualifier (AQ) Submodule --*/



378    EPwm2Regs.AQCTLA.all = 97;         // Action Qualifier Control Register For Output A



379    EPwm2Regs.AQCTLB.all = 96;         // Action Qualifier Control Register For Output B



380



381    /*	// Action Qualifier Software Force Register



382       EPwm2Regs.AQSFRC.bit.RLDCSF              = 0;          // Reload from Shadow Options



383     */



384    EPwm2Regs.AQSFRC.all = (EPwm2Regs.AQSFRC.all & ~0xC0) | 0x0;



385



386    /*	// Action Qualifier Continuous S/W Force Register



387       EPwm2Regs.AQCSFRC.bit.CSFA               = 0;          // Continuous Software Force on output A



388       EPwm2Regs.AQCSFRC.bit.CSFB               = 0;          // Continuous Software Force on output B



389     */



390    EPwm2Regs.AQCSFRC.all = (EPwm2Regs.AQCSFRC.all & ~0xF) | 0x0;



391



392    /*-- Setup Dead-Band Generator (DB) Submodule --*/



393    /*	// Dead-Band Generator Control Register



394       EPwm2Regs.DBCTL.bit.OUT_MODE             = 3;          // Dead Band Output Mode Control



395       EPwm2Regs.DBCTL.bit.IN_MODE              = 0;          // Dead Band Input Select Mode Control



396       EPwm2Regs.DBCTL.bit.POLSEL               = 2;          // Polarity Select Control



397       EPwm2Regs.DBCTL.bit.HALFCYCLE            = 0;          // Half Cycle Clocking Enable



398     */



399    EPwm2Regs.DBCTL.all = (EPwm2Regs.DBCTL.all & ~0x803F) | 0xB;



400    EPwm2Regs.DBRED.bit.DBRED = 20;    // Dead-Band Generator Rising Edge Delay Count Register



401    EPwm2Regs.DBFED.bit.DBFED = 20;    // Dead-Band Generator Falling Edge Delay Count Register



402



403    /*-- Setup Event-Trigger (ET) Submodule --*/



404    /*	// Event Trigger Selection and Pre-Scale Register



405       EPwm2Regs.ETSEL.bit.SOCAEN               = 1;          // Start of Conversion A Enable



406       EPwm2Regs.ETSEL.bit.SOCASELCMP = 0;



407       EPwm2Regs.ETSEL.bit.SOCASEL              = 4 ;          // Start of Conversion A Select



408       EPwm2Regs.ETPS.bit.SOCAPRD               = 1;          // EPWM2SOCA Period Select



409



410       EPwm2Regs.ETSEL.bit.SOCBEN               = 0;          // Start of Conversion B Enable



411



412       EPwm2Regs.ETSEL.bit.SOCBSELCMP = 0;



413       EPwm2Regs.ETSEL.bit.SOCBSEL              = 1;          // Start of Conversion A Select



414       EPwm2Regs.ETPS.bit.SOCBPRD               = 1;          // EPWM2SOCB Period Select



415       EPwm2Regs.ETSEL.bit.INTEN                = 0;          // EPWM2INTn Enable



416       EPwm2Regs.ETSEL.bit.INTSELCMP = 0;



417       EPwm2Regs.ETSEL.bit.INTSEL              = 4;          // Start of Conversion A Select



418



419       EPwm2Regs.ETPS.bit.INTPRD                = 1;          // EPWM2INTn Period Select



420     */



421    EPwm2Regs.ETSEL.all = (EPwm2Regs.ETSEL.all & ~0xFF7F) | 0x1C04;



422    EPwm2Regs.ETPS.all = (EPwm2Regs.ETPS.all & ~0x3303) | 0x1101;



423



424    /*-- Setup PWM-Chopper (PC) Submodule --*/



425    /*	// PWM Chopper Control Register



426       EPwm2Regs.PCCTL.bit.CHPEN                = 0;          // PWM chopping enable



427       EPwm2Regs.PCCTL.bit.CHPFREQ              = 0;          // Chopping clock frequency



428       EPwm2Regs.PCCTL.bit.OSHTWTH              = 0;          // One-shot pulse width



429       EPwm2Regs.PCCTL.bit.CHPDUTY              = 0;          // Chopping clock Duty cycle



430     */



431    EPwm2Regs.PCCTL.all = (EPwm2Regs.PCCTL.all & ~0x7FF) | 0x0;



432



433    /*-- Set up Trip-Zone (TZ) Submodule --*/



434    EALLOW;



435    EPwm2Regs.TZSEL.all = 0;           // Trip Zone Select Register



436



437    /*	// Trip Zone Control Register



438       EPwm2Regs.TZCTL.bit.TZA                  = 3;          // TZ1 to TZ6 Trip Action On EPWM2A



439       EPwm2Regs.TZCTL.bit.TZB                  = 3;          // TZ1 to TZ6 Trip Action On EPWM2B



440       EPwm2Regs.TZCTL.bit.DCAEVT1              = 3;          // EPWM2A action on DCAEVT1



441       EPwm2Regs.TZCTL.bit.DCAEVT2              = 3;          // EPWM2A action on DCAEVT2



442       EPwm2Regs.TZCTL.bit.DCBEVT1              = 3;          // EPWM2B action on DCBEVT1



443       EPwm2Regs.TZCTL.bit.DCBEVT2              = 3;          // EPWM2B action on DCBEVT2



444     */



445    EPwm2Regs.TZCTL.all = (EPwm2Regs.TZCTL.all & ~0xFFF) | 0xFFF;



446



447    /*	// Trip Zone Enable Interrupt Register



448       EPwm2Regs.TZEINT.bit.OST                 = 0;          // Trip Zones One Shot Int Enable



449       EPwm2Regs.TZEINT.bit.CBC                 = 0;          // Trip Zones Cycle By Cycle Int Enable



450       EPwm2Regs.TZEINT.bit.DCAEVT1             = 0;          // Digital Compare A Event 1 Int Enable



451       EPwm2Regs.TZEINT.bit.DCAEVT2             = 0;          // Digital Compare A Event 2 Int Enable



452       EPwm2Regs.TZEINT.bit.DCBEVT1             = 0;          // Digital Compare B Event 1 Int Enable



453       EPwm2Regs.TZEINT.bit.DCBEVT2             = 0;          // Digital Compare B Event 2 Int Enable



454     */



455    EPwm2Regs.TZEINT.all = (EPwm2Regs.TZEINT.all & ~0x7E) | 0x0;



456



457    /*	// Digital Compare A Control Register



458       EPwm2Regs.DCACTL.bit.EVT1SYNCE           = 0;          // DCAEVT1 SYNC Enable



459       EPwm2Regs.DCACTL.bit.EVT1SOCE            = 1;          // DCAEVT1 SOC Enable



460       EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL      = 0;          // DCAEVT1 Force Sync Signal



461       EPwm2Regs.DCACTL.bit.EVT1SRCSEL          = 0;          // DCAEVT1 Source Signal



462       EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL      = 0;          // DCAEVT2 Force Sync Signal



463       EPwm2Regs.DCACTL.bit.EVT2SRCSEL          = 0;          // DCAEVT2 Source Signal



464     */



465    EPwm2Regs.DCACTL.all = (EPwm2Regs.DCACTL.all & ~0x30F) | 0x4;



466



467    /*	// Digital Compare B Control Register



468       EPwm2Regs.DCBCTL.bit.EVT1SYNCE           = 0;          // DCBEVT1 SYNC Enable



469       EPwm2Regs.DCBCTL.bit.EVT1SOCE            = 0;          // DCBEVT1 SOC Enable



470       EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL      = 0;          // DCBEVT1 Force Sync Signal



471       EPwm2Regs.DCBCTL.bit.EVT1SRCSEL          = 0;          // DCBEVT1 Source Signal



472       EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL      = 0;          // DCBEVT2 Force Sync Signal



473       EPwm2Regs.DCBCTL.bit.EVT2SRCSEL          = 0;          // DCBEVT2 Source Signal



474     */



475    EPwm2Regs.DCBCTL.all = (EPwm2Regs.DCBCTL.all & ~0x30F) | 0x0;



476



477    /*	// Digital Compare Trip Select Register



478       EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL      = 0;          // Digital Compare A High COMP Input Select



479



480       EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL      = 1;          // Digital Compare A Low COMP Input Select



481       EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL      = 0;          // Digital Compare B High COMP Input Select



482       EPwm2Regs.DCTRIPSEL.bit.DCBLCOMPSEL      = 1;          // Digital Compare B Low COMP Input Select



483



484



485



486



487



488     */



489    EPwm2Regs.DCTRIPSEL.all = (EPwm2Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;



490



491    /*	// Trip Zone Digital Comparator Select Register



492       EPwm2Regs.TZDCSEL.bit.DCAEVT1            = 0;          // Digital Compare Output A Event 1



493       EPwm2Regs.TZDCSEL.bit.DCAEVT2            = 0;          // Digital Compare Output A Event 2



494       EPwm2Regs.TZDCSEL.bit.DCBEVT1            = 0;          // Digital Compare Output B Event 1



495       EPwm2Regs.TZDCSEL.bit.DCBEVT2            = 0;          // Digital Compare Output B Event 2



496     */



497    EPwm2Regs.TZDCSEL.all = (EPwm2Regs.TZDCSEL.all & ~0xFFF) | 0x0;



498



499    /*	// Digital Compare Filter Control Register



500       EPwm2Regs.DCFCTL.bit.BLANKE              = 0;          // Blanking Enable/Disable



501       EPwm2Regs.DCFCTL.bit.PULSESEL            = 1;          // Pulse Select for Blanking & Capture Alignment



502       EPwm2Regs.DCFCTL.bit.BLANKINV            = 0;          // Blanking Window Inversion



503       EPwm2Regs.DCFCTL.bit.SRCSEL              = 0;          // Filter Block Signal Source Select



504     */



505    EPwm2Regs.DCFCTL.all = (EPwm2Regs.DCFCTL.all & ~0x3F) | 0x10;



506    EPwm2Regs.DCFOFFSET = 0;           // Digital Compare Filter Offset Register



507    EPwm2Regs.DCFWINDOW = 0;           // Digital Compare Filter Window Register



508



509    /*	// Digital Compare Capture Control Register



510       EPwm2Regs.DCCAPCTL.bit.CAPE              = 0;          // Counter Capture Enable



511     */



512    EPwm2Regs.DCCAPCTL.all = (EPwm2Regs.DCCAPCTL.all & ~0x1) | 0x0;



513



514    /*	// HRPWM Configuration Register



515       EPwm2Regs.HRCNFG.bit.SWAPAB              = 0;          // Swap EPWMA and EPWMB Outputs Bit



516       EPwm2Regs.HRCNFG.bit.SELOUTB             = 0;          // EPWMB Output Selection Bit



517     */



518    EPwm2Regs.HRCNFG.all = (EPwm2Regs.HRCNFG.all & ~0xA0) | 0x0;



519



520    /* Update the Link Registers with the link value for all the Compare values and TBPRD */



521    /* No error is thrown if the ePWM register exists in the model or not */



522    EPwm2Regs.EPWMXLINK.bit.TBPRDLINK = 1;



523    EPwm2Regs.EPWMXLINK.bit.CMPALINK = 1;



524    EPwm2Regs.EPWMXLINK.bit.CMPBLINK = 1;



525    EPwm2Regs.EPWMXLINK.bit.CMPCLINK = 1;



526    EPwm2Regs.EPWMXLINK.bit.CMPDLINK = 1;



527    EDIS;



528    EALLOW;



529    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;



530    EDIS;



531  }



532}



533



534/* Model terminate function */



535void TwoPhaseForStuck_terminate(void)



536{



537  /* (no terminate code required) */



538}



539



540/*



541 * File trailer for generated code.



542 *



543 * [EOF]



544 */



545