//============================================================================
// includes
//============================================================================

#include "F28x_Project.h"
#include "CLAACCESS-Shared_C.h"
//#include "F2807x_device.h"     // Headerfile Include File
//#include "F2807x_settings.h"   // Settings Include File

//============================================================================
// definitions
//============================================================================

// Whether MDEBUGSTOP needs to be compiled or not
#define CLA_DEBUG 0

#define TEST_MIN_PWM 15

//============================================================================
// function prototypes
//============================================================================

//============================================================================
// Variables used for computation on the CLA are in CLA writable space
// i.e. the CLA data RAM
//============================================================================

//
// CLA TASK 1 variables
//
#pragma DATA_SECTION(iErr,"CLADataLS0");
volatile float iErr;
#pragma DATA_SECTION(iErrf,"CLADataLS0");
volatile float iErrf;

#pragma DATA_SECTION(iCtrl,"CLADataLS0");
volatile long iCtrl;

// These variables are declared in the message RAM

// CPU TO CLA direction

#pragma DATA_SECTION(iRef_CLA,"CLADataLS0");
volatile float iRef_CLA;
#pragma DATA_SECTION(iRef_Raw,"CpuToCla1MsgRAM");
volatile long iRef_Raw;

#pragma DATA_SECTION(vRef_CLA,"CLADataLS0");
volatile float vRef_CLA;
#pragma DATA_SECTION(vRef_Raw,"CpuToCla1MsgRAM");
volatile long vRef_Raw;

#pragma DATA_SECTION(xPre_CLA,"CLADataLS0");
volatile float xPre_CLA;
#pragma DATA_SECTION(xPre_Raw,"CpuToCla1MsgRAM");
volatile long xPre_Raw;

#pragma DATA_SECTION(Kip_CLA,"CpuToCla1MsgRAM");
volatile float Kip_CLA;
#pragma DATA_SECTION(Kifb_CLA,"CpuToCla1MsgRAM");
volatile float Kifb_CLA;
#pragma DATA_SECTION(Kif_CLA,"CpuToCla1MsgRAM");
volatile float Kif_CLA;
#pragma DATA_SECTION(xPreCorr_CLA,"CpuToCla1MsgRAM");
volatile float xPreCorr_CLA;

#pragma DATA_SECTION(EnableFlag,"CpuToCla1MsgRAM");
volatile long EnableFlag;

#pragma DATA_SECTION(VoltageMode_CLA,"CpuToCla1MsgRAM");
volatile long VoltageMode_CLA;

#pragma DATA_SECTION(currentSoftStart_CLA,"CLADataLS0");
volatile float currentSoftStart_CLA;

#if (DMC_CLA_BUILDLEVEL==LEVEL1 || DMC_CLA_BUILDLEVEL==LEVEL2)

#pragma DATA_SECTION(PwmTestMonoflop_CLA,"CLADataLS0");
volatile long PwmTestMonoflop_CLA;

#pragma DATA_SECTION(PwmTestMonoflop_Shadow,"CLADataLS0");
volatile long PwmTestMonoflop_Shadow;

#pragma DATA_SECTION(PwmTestMonoflop,"CpuToCla1MsgRAM");
volatile long PwmTestMonoflop;

#pragma DATA_SECTION(PwmTestPwm,"CpuToCla1MsgRAM");
volatile short PwmTestPwm;

#endif

// CLA TO CPU direction

#pragma DATA_SECTION(iSense_CLA,"CLADataLS0");
volatile float iSense_CLA;
#pragma DATA_SECTION(iSense_Raw,"Cla1ToCpuMsgRAM");
volatile long iSense_Raw;

#pragma DATA_SECTION(vSense_CLA,"CLADataLS0");
volatile float vSense_CLA;
#pragma DATA_SECTION(vSense_Raw,"Cla1ToCpuMsgRAM");
volatile long vSense_Raw;

#pragma DATA_SECTION(vRect_CLA,"CLADataLS0");
volatile float vRect_CLA;
#pragma DATA_SECTION(vRect_Raw,"Cla1ToCpuMsgRAM");
volatile long vRect_Raw;

#pragma DATA_SECTION(PWM_Raw,"Cla1ToCpuMsgRAM");
volatile long PWM_Raw;

#pragma DATA_SECTION(CLA_iRefTest,"Cla1ToCpuMsgRAM");
volatile long CLA_iRefTest;
#pragma DATA_SECTION(CLA_iSenseTest,"Cla1ToCpuMsgRAM");
volatile long CLA_iSenseTest;
#pragma DATA_SECTION(CLA_iPreTest,"Cla1ToCpuMsgRAM");
volatile long CLA_iPreTest;
#pragma DATA_SECTION(CLA_iCtrlTest,"Cla1ToCpuMsgRAM");
volatile long CLA_iCtrlTest;

#pragma DATA_SECTION(xPreTmp,"CLADataLS0");
volatile float xPreTmp;

#pragma DATA_SECTION(xPreTmp,"CLADataLS0");
int x;

#pragma DATA_SECTION(xPreTmp,"CLADataLS0");
unsigned int CLA2;

#pragma DATA_SECTION(xPreTmp,"CLADataLS0");
unsigned int CLA3;

#pragma DATA_SECTION(xPreTmp,"CLADataLS0");
unsigned int CLA4;

//============================================================================
// function definitions
//============================================================================

interrupt void Cla1Task1(void)
{
}

interrupt void Cla1Task4(void)
{
	__meallow();

	//CLA2 = (AdcaResultRegs.ADCRESULT0);
	// CLA2 = AdcaRegs.ADCCTL1.all;
	//CLA2 = EPwm3Regs.CMPA.bit.CMPA;

/*
	if( x != 0 )
	{
		x = 0;
		EPwm3Regs.AQCSFRC.bit.CSFA = AQ_CLEAR;
		//GPIO_WritePin(3, 1);
	}
	else
	{
		x = 1;
		EPwm3Regs.AQCSFRC.bit.CSFA = AQ_SET;
		//GPIO_WritePin(3, 0);
	}
*/

	EPwm3Regs.CMPA.bit.CMPA = 125;
	EPwm3Regs.CMPA.bit.CMPAHR = 125;
	CLA_iRefTest = CLA2 = EPwm3Regs.CMPA.bit.CMPA;
	CLA_iSenseTest = CLA4 = EPwm3Regs.CMPA.bit.CMPAHR;
	vSense_Raw = iRef_Raw; //Testing CPU-CLA-CPU communication : OK
	vRect_Raw = (long)(AdcaResultRegs.ADCRESULT0);	// Testing ADC result register access. : OK! (0x904) :)
	PWM_Raw = (long)(EPwm1Regs.TBCTL.all);	// TEsting EPWM Periph register access. : NOT OK!
	//ECap1Regs.ECEINT.all = 0xfe; vSense_Raw = (long)(ECap1Regs.ECEINT.all); // Testing ECAP Periph register access. : NOT OK! (clock enabled)
	//EQep1Regs.QEINT.all = 0xfe; vSense_Raw = (long)(EQep1Regs.QEINT.all); // Testing EQEP Periph register access. : NOT OK! (clock enabled)
	//vSense_Raw = (long)(AdcaRegs.ADCCOUNTER.all);	// Testing ADC control register access. : OK!
	//DacaRegs.DACOUTEN.bit.DACOUTEN = 1;	vSense_Raw = (long)(DacaRegs.DACOUTEN.all);	// Testing DAC control register access. : NOT OK!



	__medis();

	CLA_iPreTest = CLA3++;
}


//===========================================================================
// End of file.
//===========================================================================
