//#############################################################################
//
// FILE:   clockTree.h
//
// TITLE:  Setups device clocking for examples.
//
//#############################################################################
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//###########################################################################

#ifndef CLOCKTREE_H
#define CLOCKTREE_H

//*****************************************************************************
//
// Summary of SYSPLL related clock configuration
//
//*****************************************************************************
//
// Input Clock to SYSPLL (OSCCLK)	= 10 MHz    (INTOSC2 provides OSCCLK)
//
//##### SYSPLL ENABLED #####
//
// PLLRAWCLK				= 200 MHz   (Output of SYSPLL if enabled) 
// PLLSYSCLK				= 100 MHz
// CPUCLK					= 100 MHz
// SYSCLK					= 100 MHz
// LSPCLK					= 25 MHz 
	
//*****************************************************************************
//
// Macro definitions used in device.c (SYSPLL / LSPCLK)
//
//*****************************************************************************
//
//	Input Clock to SYSPLL (OSCCLK) = INTOSC2 = 10 MHz
//
#define DEVICE_OSCSRC_FREQ          10000000U
//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// SYSPLL ENABLED
// SYSCLK = 100 MHz = 10 MHz (OSCCLK) * (20 (IMULT) + 0 (FMULT)) / (1 (ODIV) * 2 (SYSCLKDIVSEL))	
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * (20 + 0)) / (1 * 2))
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_OSC2 | SYSCTL_IMULT(20) | \
									 SYSCTL_FMULT_NONE | SYSCTL_ODIV(1)  | \
									 SYSCTL_SYSDIV(2)| SYSCTL_PLL_ENABLE)

//
// Define to pass to SysCtl_setLowSpeedClock().
// Low Speed Clock (LSPCLK) = 100 MHz / 4 = 25 MHz
//
#define DEVICE_LSPCLK_CFG  			SYSCTL_LSPCLK_PRESCALE_4

#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 4)

//*****************************************************************************
//
// CPUCLK Domain (100 MHz)
//
//*****************************************************************************
// C28x
// FPU
// TMU
// VCU
// Flash
// M0_M1_RAM
// BOOTROM
// EPIE
// LocalSharedRAMs
// GlobalSharedRAMs
// GPIO
// DCSM
//	
//*****************************************************************************
//
// SYSCLK Domain (100 MHz)
//
//*****************************************************************************
// EPIE
// LocalSharedRAMs
// GlobalSharedRAMs
// GPIO
// DCSM
//	
/////////////////////	
// Gated CPU1 SYSCLK
/////////////////////
// CLA
// Timer0
// DMA
// ePWM
// eCAP
// eQEP
// SDFM
// ADC
// CMPSS
// DAC
// PGA
// I2C
// PMBus
// LIN
//

//*****************************************************************************
//
// Gated Peripheral SYSCLK Domain (100 MHz) 
//
//*****************************************************************************
// CLA
// Timer0
// DMA
// ePWM
// eCAP
// eQEP
// SDFM
// ADC
// CMPSS
// DAC
// PGA
// I2C
// PMBus
// LIN
//	
//*****************************************************************************
//
// Gated LSPCLK Domain (25 MHz) 
//
//*****************************************************************************
// SCI
// SPI

#endif // CLOCKTREE_H

