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MotorWare f2806x Driver API Documentation
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Contains public interface to various functions related to the phase-locked loop (PLL) object. More...
Go to the source code of this file.
Data Structures | |
| struct | _PLL_Obj_ |
| Defines the phase lock loop (PLL) object. More... | |
Macros | |
| #define | PLL_BASE_ADDR (0x00007011) |
| Defines the base address of the phase lock loop (PLL) registers. More... | |
| #define | PLL_PLLCR_DIV_BITS (15 << 0) |
| Defines the location of the DIV bits in the PLLCR register. More... | |
| #define | PLL_PLLSTS_PLLLOCKS_BITS (1 << 0) |
| Defines the location of the PLLLOCKS bits in the PLLSTS register. More... | |
| #define | PLL_PLLSTS_PLLOFF_BITS (1 << 2) |
| Defines the location of the PLLOFF bits in the PLLSTS register. More... | |
| #define | PLL_PLLSTS_MCLKSTS_BITS (1 << 3) |
| Defines the location of the MCLKSTS bits in the PLLSTS register. More... | |
| #define | PLL_PLLSTS_MCLKCLR_BITS (1 << 4) |
| Defines the location of the MCLKCLR bits in the PLLSTS register. More... | |
| #define | PLL_PLLSTS_OSCOFF_BITS (1 << 5) |
| Defines the location of the OSCOFF bits in the PLLSTS register. More... | |
| #define | PLL_PLLSTS_MCLKOFF_BITS (1 << 6) |
| Defines the location of the MCLKOFF bits in the PLLSTS register. More... | |
| #define | PLL_PLLSTS_DIVSEL_BITS (3 << 7) |
| Defines the location of the DIVSEL bits in the PLLSTS register. More... | |
| #define | PLL_PLLSTS_NORMRDYE_BITS (1 << 15) |
| Defines the location of the NORMRDYE bits in the PLLSTS register. More... | |
Typedefs | |
| typedef struct _PLL_Obj_ | PLL_Obj |
| Defines the phase lock loop (PLL) object. More... | |
| typedef struct _PLL_Obj_ * | PLL_Handle |
| Defines the phase lock loop (PLL) handle. More... | |
Enumerations | |
| enum | PLL_ClkFreq_e { PLL_ClkFreq_5_MHz =(1 << 0), PLL_ClkFreq_10_MHz =(2 << 0), PLL_ClkFreq_15_MHz =(3 << 0), PLL_ClkFreq_20_MHz =(4 << 0), PLL_ClkFreq_25_MHz =(5 << 0), PLL_ClkFreq_30_MHz =(6 << 0), PLL_ClkFreq_35_MHz =(7 << 0), PLL_ClkFreq_40_MHz =(8 << 0), PLL_ClkFreq_45_MHz =(9 << 0), PLL_ClkFreq_50_MHz =(10 << 0), PLL_ClkFreq_55_MHz =(11 << 0), PLL_ClkFreq_60_MHz =(12 << 0), PLL_ClkFreq_65_MHz =(13 << 0), PLL_ClkFreq_70_MHz =(14 << 0), PLL_ClkFreq_75_MHz =(15 << 0), PLL_ClkFreq_80_MHz =(16 << 0), PLL_ClkFreq_85_MHz =(17 << 0), PLL_ClkFreq_90_MHz =(18 << 0) } |
| Enumeration to define the phase lock loop (PLL) clock frequency. More... | |
| enum | PLL_DivideSelect_e { PLL_DivideSelect_ClkIn_by_4 =(0 << 7), PLL_DivideSelect_ClkIn_by_2 =(2 << 7), PLL_DivideSelect_ClkIn_by_1 =(3 << 7) } |
| Enumeration to define the phase lock loop (PLL) divide select. More... | |
| enum | PLL_ClkStatus_e { PLL_ClkStatus_Normal =(0 << 3), PLL_ClkStatus_Missing =(1 << 3) } |
| Enumeration to define the phase lock loop (PLL) clock status. More... | |
| enum | PLL_LockStatus_e { PLL_LockStatus_Locking =(0 << 0), PLL_LockStatus_Done =(1 << 0) } |
| Enumeration to define the phase lock loop (PLL) clock lock status. More... | |
Functions | |
| void | PLL_disable (PLL_Handle pllHandle) |
| Disables the phase lock loop (PLL) More... | |
| void | PLL_disableClkDetect (PLL_Handle pllHandle) |
| Disables the clock detect logic. More... | |
| void | PLL_disableNormRdy (PLL_Handle pllHandle) |
| Disables the NORMRDY signal. More... | |
| void | PLL_disableOsc (PLL_Handle pllHandle) |
| Disables the oscillator. More... | |
| void | PLL_enable (PLL_Handle pllHandle) |
| Enables the phase lock loop (PLL) More... | |
| void | PLL_enableClkDetect (PLL_Handle pllHandle) |
| Enables the clock detect logic. More... | |
| void | PLL_enableNormRdy (PLL_Handle pllHandle) |
| Enables the NORMRDY signal. More... | |
| void | PLL_enableOsc (PLL_Handle pllHandle) |
| Enables the oscillator. More... | |
| PLL_ClkFreq_e | PLL_getClkFreq (PLL_Handle pllHandle) |
| Gets the phase lock loop (PLL) clock frequency. More... | |
| PLL_ClkStatus_e | PLL_getClkStatus (PLL_Handle pllHandle) |
| Gets the phase lock loop (PLL) clock status. More... | |
| PLL_DivideSelect_e | PLL_getDivideSelect (PLL_Handle pllHandle) |
| Gets the phase lock loop (PLL) divide select value. More... | |
| PLL_LockStatus_e | PLL_getLockStatus (PLL_Handle pllHandle) |
| Gets the phase lock loop (PLL) lock status. More... | |
| PLL_Handle | PLL_init (void *pMemory, const size_t numBytes) |
| Initializes the phase lock loop (PLL) object handle. More... | |
| void | PLL_resetClkDetect (PLL_Handle pllHandle) |
| Resets the phase lock loop (PLL) clock detect logic. More... | |
| void | PLL_setClkFreq (PLL_Handle pllHandle, const PLL_ClkFreq_e freq) |
| Sets the phase lock loop (PLL) clock frequency. More... | |
| void | PLL_setDivideSelect (PLL_Handle pllHandle, const PLL_DivideSelect_e divSelect) |
| Sets the phase lock loop (PLL) divide select value. More... | |
| void | PLL_setLockPeriod (PLL_Handle pllHandle, const uint16_t lockPeriod) |
| Sets the phase lock loop (PLL) lock time. More... | |
Contains public interface to various functions related to the phase-locked loop (PLL) object.
(C) Copyright 2015, Texas Instruments, Inc.
Definition in file pll.h.
1.8.9.1