MEMORY { /* BEGIN is used for the "boot to Flash" bootloader mode */ BOOT_RSVD : origin = 0x000002, length = 0x000126 RAMM0 : origin = 0x000128, length = 0x0002D8 RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAMLS0_3 : origin = 0x008000, length = 0x002000 RAMLS4_7 : origin = 0x00A000, length = 0x002000 /* RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS1 : origin = 0x008800, length = 0x000800 RAMLS2 : origin = 0x009000, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMLS4 : origin = 0x00A000, length = 0x000800 RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 RAMLS7 : origin = 0x00B800, length = 0x000800 */ RAMLS8 : origin = 0x014000, length = 0x002000 // When configured as CLA program use the address 0x4000 RAMLS9 : origin = 0x016000, length = 0x002000 // When configured as CLA program use the address 0x6000 //RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory //RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory BOOT_ACT_KEY : origin = 0x00C000, length = 0x000010 /* Boot activate key */ RAMGS0 : origin = 0x00C010, length = 0x001FF0 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2_3 : origin = 0x010000, length = 0x004000 // RAMGS2 : origin = 0x010000, length = 0x002000 // RAMGS3 : origin = 0x012000, length = 0x002000 BOOTROM : origin = 0x3F8000, length = 0x007FC0 SECURE_ROM : origin = 0x3F2000, length = 0x006000 RESET : origin = 0x3FFFC0, length = 0x000002 /* Flash sectors */ /* BANK 0 */ // FLASH_BOOT_CODE : origin = 0x080002, length = 0x003FEC /* IAP boot code */ // BOOT_FUNCTION_ID : origin = 0x083FEE, length = 0x000002 /* Function ID record */ // BOOT_VERSION : origin = 0x083FF0, length = 0x000010 /* Boot version record */ FLASH_SIGNATURE : origin = 0x085000, length = 0x000006 /* Signature of app header */ FLASH_APP_HEADER : origin = 0x085006, length = 0x00001A /* App header field */ COMPLIANT_ADDRESS : origin = 0x085020, length = 0x000002 /* Address of compliant table */ FLASH_HEADER_RES : origin = 0x085022, length = 0x0000DE /* Reserved field of app header */ COMPLIANT_TABLE : origin = 0x085100, length = 0x000100 /* Compliant table field */ FLASH_BEGIN : origin = 0x085200, length = 0x000002 /* Flash begin */ FLASH_APP_CODE : origin = 0x085202, length = 0x009DFE /* App code field */ /* BANK 1 */ FLASH_CALIBRATION : origin = 0x08F000, length = 0x001000 /* MFR Data */ FLASH_BANK1_APP : origin = 0x090000, length = 0x00A000 /* Bank1 app ROM field */ /* Reserved */ /* FLASH_BANK2 : origin = 0x0C0000, length = 0x20000 FLASH_BANK3 : origin = 0x0E0000, length = 0x20000 FLASH_BANK4 : origin = 0x100000, length = 0x20000 */ CLATOCPURAM : origin = 0x001480, length = 0x000080 CPUTOCLARAM : origin = 0x001500, length = 0x000080 CLATODMARAM : origin = 0x001680, length = 0x000080 DMATOCLARAM : origin = 0x001700, length = 0x000080 } SECTIONS { codestart : > FLASH_BEGIN, ALIGN(8) .text : > FLASH_APP_CODE, ALIGN(8) .cinit : > FLASH_APP_CODE, ALIGN(8) .switch : > FLASH_APP_CODE, ALIGN(8) .reset : > RESET, TYPE = DSECT /* not used */ .stack : > RAMM1 #if defined(__TI_EABI__) .bss : >> RAMGS0 | RAMGS1 .bss:output : >> RAMGS0 | RAMGS1 .init_array : > FLASH_APP_CODE, ALIGN(8) .const : > FLASH_APP_CODE, ALIGN(8) .data : >> RAMGS0 | RAMGS1 .sysmem : >> RAMGS0 | RAMGS1 .bss:cio : >> RAMGS0 | RAMGS1 #else .pinit : > FLASH_APP_CODE, ALIGN(8) .econst : > FLASH_APP_CODE, ALIGN(8) .ebss : >> RAMGS0 | RAMGS1 .esysmem : >> RAMGS0 | RAMGS1 .cio : >> RAMGS0 | RAMGS1 #endif .ramgs0 : > RAMGS0 .boot_activate : START(_boot_activate) {} > BOOT_ACT_KEY, TYPE = NOINIT .signature : START(_start_of_approm) {} > FLASH_SIGNATURE .appheader : > FLASH_APP_HEADER .compliantaddress : > COMPLIANT_ADDRESS .headerreserved : > FLASH_HEADER_RES .complianttable : START(_start_of_complianttable), {} > COMPLIANT_TABLE .approm : START(_start_of_appcode), END(_end_of_approm) {} > FLASH_APP_CODE .calibration : START(_start_of_calibration), END(_end_of_calibration) { . += SIZE(FLASH_CALIBRATION); } > FLASH_CALIBRATION .appbank1 : START(_start_of_appbank1), END(_end_of_appbank1) { . += SIZE(FLASH_BANK1_APP); } > FLASH_BANK1_APP .TI.ramfunc : { -l FAPI_F28P55x_COFF_v4.00.00.lib Sine_Process.obj Math_Table.obj(.econst) } LOAD = FLASH_APP_CODE, RUN = RAMGS2_3, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), ALIGN(8) cla1ToCpuMsgRAM : > CLATOCPURAM cpuToCla1MsgRAM : > CPUTOCLARAM .scratchpad : >> RAMLS4_7 .bss_cla : >> RAMLS0_3 Cla1Prog : LOAD = FLASH_APP_CODE, RUN = RAMLS4_7, LOAD_START(_ClaFuncsLoadStart), LOAD_SIZE(_ClaFuncsLoadSize), RUN_START(_ClaFuncsRunStart), ALIGN(8) .const_cla : LOAD = FLASH_APP_CODE, RUN = RAMLS0_3, LOAD_START(_ClaConstLoadStart), LOAD_SIZE(_ClaConstLoadSize), RUN_START(_ClaConstRunStart), ALIGN(8) } //---------------- END LINE -----------------------------------------------------------------------