MotorWare f2806x Driver API Documentation

- Main Page
- Modules
- Data Structures
- Files

- File List
- Globals

clk.c
Go to the documentation of this file.
1 /* --COPYRIGHT--,BSD
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * --/COPYRIGHT--*/
37
38
39 // **************************************************************************
40 // the includes
41
42 #include "sw/drivers/clk/src/32b/f28x/f2806x/clk.h"
43
44
45 // **************************************************************************
46 // the defines
47
48
49 // **************************************************************************
50 // the globals
51
52
53 // **************************************************************************
54 // the functions
55
56
57 void CLK_disableAdcClock(CLK_Handle clkHandle)
58 {
59 CLK_Obj *clk = (CLK_Obj *)clkHandle;
60
61
62 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
63
64 // clear the bits
65 clk->PCLKCR0 &= (~CLK_PCLKCR0_ADCENCLK_BITS);
66
67 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
68
69 return;
70 } // end of CLK_disableAdcClock() function
71
72
73 void CLK_disableClaClock(CLK_Handle clkHandle)
74 {
75 CLK_Obj *clk = (CLK_Obj *)clkHandle;
76
77
78 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
79
80 // clear the bits
81 clk->PCLKCR3 &= (~CLK_PCLKCR3_CLA1ENCLK_BITS);
82
83 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
84
85 return;
86 } // end of CLK_disableClaClock() function
87
88
89 void CLK_disableClkIn(CLK_Handle clkHandle)
90 {
91 CLK_Obj *clk = (CLK_Obj *)clkHandle;
92
93
94 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
95
96 // set the bits
97 clk->CLKCTL |= CLK_CLKCTL_XCLKINOFF_BITS;
98
99 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
100
101 return;
102 } // end of CLK_disableClkIn() function
103
104
105 void CLK_disableCompClock(CLK_Handle clkHandle,const CLK_CompNumber_e compNumber)
106 {
107 CLK_Obj *clk = (CLK_Obj *)clkHandle;
108
109
110 // clear the bits
111 clk->PCLKCR3 &= (~compNumber);
112
113 return;
114 } // end of CLK_disableCompClock() function
115
116
117 void CLK_disableCpuTimerClock(CLK_Handle clkHandle,const CLK_CpuTimerNumber_e cpuTimerNumber)
118 {
119 CLK_Obj *clk = (CLK_Obj *)clkHandle;
120
121
122 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
123
124 // clear the bits
125 clk->PCLKCR3 &= (~cpuTimerNumber);
126
127 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
128
129 return;
130 } // end of CLK_disableCpuTimerClock() function
131
132
133 void CLK_disableCrystalOsc(CLK_Handle clkHandle)
134 {
135 CLK_Obj *clk = (CLK_Obj *)clkHandle;
136
137
138 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
139
140 // set the bits
141 clk->CLKCTL |= CLK_CLKCTL_XTALOSCOFF_BITS;
142
143 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
144
145 return;
146 } // end of CLK_disableCrystalOsc() function
147
148
149 void CLK_disableEcanaClock(CLK_Handle clkHandle)
150 {
151 CLK_Obj *clk = (CLK_Obj *)clkHandle;
152
153
154 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
155
156 // clear the bits
157 clk->PCLKCR0 &= (~CLK_PCLKCR0_ECANAENCLK_BITS);
158
159 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
160
161 return;
162 } // end of CLK_disableEcanaClock() function
163
164
165 void CLK_disableEcap1Clock(CLK_Handle clkHandle)
166 {
167 CLK_Obj *clk = (CLK_Obj *)clkHandle;
168
169
170 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
171
172 // clear the bits
173 clk->PCLKCR1 &= (~CLK_PCLKCR1_ECAP1ENCLK_BITS);
174
175 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
176
177 return;
178 } // end of CLK_disableEcap1Clock() function
179
180
181 void CLK_disableEqep1Clock(CLK_Handle clkHandle)
182 {
183 CLK_Obj *clk = (CLK_Obj *)clkHandle;
184
185
186 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
187
188 // clear the bits
189 clk->PCLKCR1 &= (~CLK_PCLKCR1_EQEP1ENCLK_BITS);
190
191 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
192
193 return;
194 } // end of CLK_disableEqep1Clock() function
195
196 void CLK_disableEqep2Clock(CLK_Handle clkHandle)
197 {
198 CLK_Obj *clk = (CLK_Obj *)clkHandle;
199
200
201 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
202
203 // clear the bits
204 clk->PCLKCR1 &= (~CLK_PCLKCR1_EQEP2ENCLK_BITS);
205
206 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
207
208 return;
209 } // end of CLK_disableEqep2Clock() function
210
211
212 void CLK_disableGpioInputClock(CLK_Handle clkHandle)
213 {
214 CLK_Obj *clk = (CLK_Obj *)clkHandle;
215
216
217 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
218
219 // clear the bits
220 clk->PCLKCR3 &= (~CLK_PCLKCR3_GPIOINENCLK_BITS);
221
222 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
223
224 return;
225 } // end of CLK_disableGpioInputClock() function
226
227
228 void CLK_disableHrPwmClock(CLK_Handle clkHandle)
229 {
230 CLK_Obj *clk = (CLK_Obj *)clkHandle;
231
232
233 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
234
235 // clear the bits
236 clk->PCLKCR0 &= (~CLK_PCLKCR0_HRPWMENCLK_BITS);
237
238 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
239
240 return;
241 } // end of CLK_disableHrPwmClock() function
242
243
244 void CLK_disableI2cClock(CLK_Handle clkHandle)
245 {
246 CLK_Obj *clk = (CLK_Obj *)clkHandle;
247
248
249 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
250
251 // clear the bits
252 clk->PCLKCR0 &= (~CLK_PCLKCR0_I2CAENCLK_BITS);
253
254 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
255
256 return;
257 } // end of CLK_disableI2cClock() function
258
259
260 void CLK_disableLinAClock(CLK_Handle clkHandle)
261 {
262 CLK_Obj *clk = (CLK_Obj *)clkHandle;
263
264
265 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
266
267 // clear the bits
268 clk->PCLKCR0 &= (~CLK_PCLKCR0_LINAENCLK_BITS);
269
270 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
271
272 return;
273 } // end of CLK_disableLinAClock() function
274
275
276 void CLK_disableOsc1(CLK_Handle clkHandle)
277 {
278 CLK_Obj *clk = (CLK_Obj *)clkHandle;
279
280
281 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
282
283 // set the bits
284 clk->CLKCTL |= CLK_CLKCTL_INTOSC1OFF_BITS;
285
286 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
287
288 return;
289 } // end of CLK_disableOsc1() function
290
291
292 void CLK_disableOsc1HaltMode(CLK_Handle clkHandle)
293 {
294 CLK_Obj *clk = (CLK_Obj *)clkHandle;
295
296
297 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
298
299 // set the bits
300 clk->CLKCTL |= CLK_CLKCTL_INTOSC1HALTI_BITS;
301
302 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
303
304 return;
305 } // end of CLK_disableOsc1HaltMode() function
306
307
308 void CLK_disableOsc2(CLK_Handle clkHandle)
309 {
310 CLK_Obj *clk = (CLK_Obj *)clkHandle;
311
312
313 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
314
315 // set the bits
316 clk->CLKCTL |= CLK_CLKCTL_INTOSC2OFF_BITS;
317
318 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
319
320 return;
321 } // end of CLK_disableOsc2() function
322
323
324 void CLK_disableOsc2HaltMode(CLK_Handle clkHandle)
325 {
326 CLK_Obj *clk = (CLK_Obj *)clkHandle;
327
328
329 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
330
331 // set the bits
332 clk->CLKCTL |= CLK_CLKCTL_INTOSC2HALTI_BITS;
333
334 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
335
336 return;
337 } // end of CLK_disableOsc2HaltMode() function
338
339
340 void CLK_disablePwmClock(CLK_Handle clkHandle,const PWM_Number_e pwmNumber)
341 {
342 CLK_Obj *clk = (CLK_Obj *)clkHandle;
343
344
345 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
346
347 // clear the bits
348 clk->PCLKCR1 &= (~(1 << pwmNumber));
349
350 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
351
352 return;
353 } // end of CLK_disablePwmClock() function
354
355
356 void CLK_disableSciaClock(CLK_Handle clkHandle)
357 {
358 CLK_Obj *clk = (CLK_Obj *)clkHandle;
359
360
361 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
362
363 // clear the bits
364 clk->PCLKCR0 &= (~CLK_PCLKCR0_SCIAENCLK_BITS);
365
366 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
367
368 return;
369 } // end of CLK_disableSciaClock() function
370
371
372 void CLK_disableScibClock(CLK_Handle clkHandle)
373 {
374 CLK_Obj *clk = (CLK_Obj *)clkHandle;
375
376
377 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
378
379 // clear the bits
380 clk->PCLKCR0 &= (~CLK_PCLKCR0_SCIBENCLK_BITS);
381
382 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
383
384 return;
385 } // end of CLK_disableScibClock() function
386
387
388 void CLK_disableSpiaClock(CLK_Handle clkHandle)
389 {
390 CLK_Obj *clk = (CLK_Obj *)clkHandle;
391
392
393 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
394
395 // clear the bits
396 clk->PCLKCR0 &= (~CLK_PCLKCR0_SPIAENCLK_BITS);
397
398 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
399
400 return;
401 } // end of CLK_disableSpiaClock() function
402
403
404 void CLK_disableSpibClock(CLK_Handle clkHandle)
405 {
406 CLK_Obj *clk = (CLK_Obj *)clkHandle;
407
408
409 // clear the bits
410 clk->PCLKCR0 &= (~CLK_PCLKCR0_SPIBENCLK_BITS);
411
412 return;
413 } // end of CLK_disableSpibClock() function
414
415
416 void CLK_disableTbClockSync(CLK_Handle clkHandle)
417 {
418 CLK_Obj *clk = (CLK_Obj *)clkHandle;
419
420
421 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
422
423 // clear the bits
424 clk->PCLKCR0 &= (~CLK_PCLKCR0_TBCLKSYNC_BITS);
425
426 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
427
428 return;
429 } // end of CLK_disableTbClockSync() function
430
431
432 void CLK_disableWatchDogHaltMode(CLK_Handle clkHandle)
433 {
434 CLK_Obj *clk = (CLK_Obj *)clkHandle;
435
436
437 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
438
439 // set the bits
440 clk->CLKCTL |= CLK_CLKCTL_WDHALTI_BITS;
441
442 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
443
444 return;
445 } // end of CLK_disableWatchDogHaltMode() function
446
447
448 void CLK_enableAdcClock(CLK_Handle clkHandle)
449 {
450 CLK_Obj *clk = (CLK_Obj *)clkHandle;
451
452
453 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
454
455 // set the bits
456 clk->PCLKCR0 |= CLK_PCLKCR0_ADCENCLK_BITS;
457
458 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
459
460 return;
461 } // end of CLK_enableAdcClock() function
462
463
464 void CLK_enableClaClock(CLK_Handle clkHandle)
465 {
466 CLK_Obj *clk = (CLK_Obj *)clkHandle;
467
468
469 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
470
471 // set the bits
472 clk->PCLKCR3 |= CLK_PCLKCR3_CLA1ENCLK_BITS;
473
474 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
475
476 return;
477 } // end of CLK_enableClaClock() function
478
479
480 void CLK_enableCompClock(CLK_Handle clkHandle,const CLK_CompNumber_e compNumber)
481 {
482 CLK_Obj *clk = (CLK_Obj *)clkHandle;
483
484
485 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
486
487 // set the bits
488 clk->PCLKCR3 |= compNumber;
489
490 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
491
492 return;
493 } // end of CLK_enableCompClock() function
494
495
496 void CLK_enableCpuTimerClock(CLK_Handle clkHandle,const CLK_CpuTimerNumber_e cpuTimerNumber)
497 {
498 CLK_Obj *clk = (CLK_Obj *)clkHandle;
499
500
501 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
502
503 // set the bits
504 clk->PCLKCR3 |= cpuTimerNumber;
505
506 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
507
508 return;
509 } // end of CLK_enableCpuTimerClock() function
510
511
512 void CLK_enableCrystalOsc(CLK_Handle clkHandle)
513 {
514 CLK_Obj *clk = (CLK_Obj *)clkHandle;
515
516
517 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
518
519 // clear the bits
520 clk->CLKCTL &= (~CLK_CLKCTL_XTALOSCOFF_BITS);
521
522 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
523
524 return;
525 } // end of CLK_enableCrystalOsc() function
526
527
528 void CLK_enableEcanaClock(CLK_Handle clkHandle)
529 {
530 CLK_Obj *clk = (CLK_Obj *)clkHandle;
531
532
533 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
534
535 // set the bits
536 clk->PCLKCR0 |= CLK_PCLKCR0_ECANAENCLK_BITS;
537
538 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
539
540 return;
541 } // end of CLK_enableEcanaClock() function
542
543
544 void CLK_enableEqep1Clock(CLK_Handle clkHandle)
545 {
546 CLK_Obj *clk = (CLK_Obj *)clkHandle;
547
548
549 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
550
551 // set the bits
552 clk->PCLKCR1 |= CLK_PCLKCR1_EQEP1ENCLK_BITS;
553
554 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
555
556 return;
557 } // end of CLK_enableEqep1Clock() function
558
559 void CLK_enableEqep2Clock(CLK_Handle clkHandle)
560 {
561 CLK_Obj *clk = (CLK_Obj *)clkHandle;
562
563
564 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
565
566 // set the bits
567 clk->PCLKCR1 |= (uint16_t)CLK_PCLKCR1_EQEP2ENCLK_BITS;
568
569 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
570
571 return;
572 } // end of CLK_enableEqep2Clock() function
573
574 void CLK_enableEcap1Clock(CLK_Handle clkHandle)
575 {
576 CLK_Obj *clk = (CLK_Obj *)clkHandle;
577
578
579 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
580
581 // set the bits
582 clk->PCLKCR1 |= CLK_PCLKCR1_ECAP1ENCLK_BITS;
583
584 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
585
586 return;
587 } // end of CLK_enableEcap1Clock() function
588
589
590 void CLK_enableClkIn(CLK_Handle clkHandle)
591 {
592 CLK_Obj *clk = (CLK_Obj *)clkHandle;
593
594
595 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
596
597 // clear the bits
598 clk->CLKCTL &= (~CLK_CLKCTL_XCLKINOFF_BITS);
599
600 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
601
602 return;
603 } // end of CLK_enableClkIn() function
604
605
606 void CLK_enableGpioInputClock(CLK_Handle clkHandle)
607 {
608 CLK_Obj *clk = (CLK_Obj *)clkHandle;
609
610
611 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
612
613 // set the bits
614 clk->PCLKCR3 |= CLK_PCLKCR3_GPIOINENCLK_BITS;
615
616 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
617
618 return;
619 } // end of CLK_enableGpioInputClock() function
620
621
622 void CLK_enableHrPwmClock(CLK_Handle clkHandle)
623 {
624 CLK_Obj *clk = (CLK_Obj *)clkHandle;
625
626
627 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
628
629 // set the bits
630 clk->PCLKCR0 |= CLK_PCLKCR0_HRPWMENCLK_BITS;
631
632 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
633
634 return;
635 } // end of CLK_enableHrPwmClock() function
636
637
638 void CLK_enableI2cClock(CLK_Handle clkHandle)
639 {
640 CLK_Obj *clk = (CLK_Obj *)clkHandle;
641
642
643 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
644
645 // set the bits
646 clk->PCLKCR0 |= CLK_PCLKCR0_I2CAENCLK_BITS;
647
648 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
649
650 return;
651 } // end of CLK_enableI2cClock() function
652
653
654 void CLK_enableLinAClock(CLK_Handle clkHandle)
655 {
656 CLK_Obj *clk = (CLK_Obj *)clkHandle;
657
658
659 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
660
661 // set the bits
662 clk->PCLKCR0 |= CLK_PCLKCR0_LINAENCLK_BITS;
663
664 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
665
666 return;
667 } // end of CLK_enableLinAClock() function
668
669
670 void CLK_enableOsc1(CLK_Handle clkHandle)
671 {
672 CLK_Obj *clk = (CLK_Obj *)clkHandle;
673
674
675 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
676
677 // clear the bits
678 clk->CLKCTL &= (~CLK_CLKCTL_INTOSC1OFF_BITS);
679
680 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
681
682 return;
683 } // end of CLK_enableOsc1() function
684
685
686 void CLK_enableOsc1HaltMode(CLK_Handle clkHandle)
687 {
688 CLK_Obj *clk = (CLK_Obj *)clkHandle;
689
690
691 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
692
693 // clear the bits
694 clk->CLKCTL &= (~CLK_CLKCTL_INTOSC1HALTI_BITS);
695
696 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
697
698 return;
699 } // end of CLK_enableOsc1HaltMode() function
700
701
702 void CLK_enableOsc2(CLK_Handle clkHandle)
703 {
704 CLK_Obj *clk = (CLK_Obj *)clkHandle;
705
706
707 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
708
709 // clear the bits
710 clk->CLKCTL &= (~CLK_CLKCTL_INTOSC2OFF_BITS);
711
712 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
713
714 return;
715 } // end of CLK_enableOsc2() function
716
717
718 void CLK_enableOsc2HaltMode(CLK_Handle clkHandle)
719 {
720 CLK_Obj *clk = (CLK_Obj *)clkHandle;
721
722
723 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
724
725 // clear the bits
726 clk->CLKCTL &= (~CLK_CLKCTL_INTOSC2HALTI_BITS);
727
728 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
729
730 return;
731 } // end of CLK_enableOsc2HaltMode() function
732
733
734 void CLK_enablePwmClock(CLK_Handle clkHandle,const PWM_Number_e pwmNumber)
735 {
736 CLK_Obj *clk = (CLK_Obj *)clkHandle;
737
738
739 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
740
741 // set the bits
742 clk->PCLKCR1 |= 1 << pwmNumber;
743
744 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
745
746 return;
747 } // end of CLK_enablePwmClock() function
748
749
750 void CLK_enableSciaClock(CLK_Handle clkHandle)
751 {
752 CLK_Obj *clk = (CLK_Obj *)clkHandle;
753
754
755 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
756
757 // set the bits
758 clk->PCLKCR0 |= CLK_PCLKCR0_SCIAENCLK_BITS;
759
760 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
761
762 return;
763 } // end of CLK_enableSciaClock() function
764
765
766 void CLK_enableScibClock(CLK_Handle clkHandle)
767 {
768 CLK_Obj *clk = (CLK_Obj *)clkHandle;
769
770
771 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
772
773 // set the bits
774 clk->PCLKCR0 |= CLK_PCLKCR0_SCIBENCLK_BITS;
775
776 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
777
778 return;
779 } // end of CLK_enableScibClock() function
780
781
782 void CLK_enableSpiaClock(CLK_Handle clkHandle)
783 {
784 CLK_Obj *clk = (CLK_Obj *)clkHandle;
785
786
787 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
788
789 // set the bits
790 clk->PCLKCR0 |= CLK_PCLKCR0_SPIAENCLK_BITS;
791
792 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
793
794 return;
795 } // end of CLK_enableSpiaClock() function
796
797
798 void CLK_enableSpibClock(CLK_Handle clkHandle)
799 {
800 CLK_Obj *clk = (CLK_Obj *)clkHandle;
801
802
803 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
804
805 // set the bits
806 clk->PCLKCR0 |= CLK_PCLKCR0_SPIBENCLK_BITS;
807
808 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
809
810 return;
811 } // end of CLK_enableSpibClock() function
812
813
814 void CLK_enableTbClockSync(CLK_Handle clkHandle)
815 {
816 CLK_Obj *clk = (CLK_Obj *)clkHandle;
817
818
819 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
820
821 // set the bits
822 clk->PCLKCR0 |= CLK_PCLKCR0_TBCLKSYNC_BITS;
823
824 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
825
826 return;
827 } // end of CLK_enableTbClockSync() function
828
829
830 void CLK_enableWatchDogHaltMode(CLK_Handle clkHandle)
831 {
832 CLK_Obj *clk = (CLK_Obj *)clkHandle;
833
834
835 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
836
837 // clear the bits
838 clk->CLKCTL &= (~CLK_CLKCTL_WDHALTI_BITS);
839
840 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
841
842 return;
843 } // end of CLK_enableWatchDogHaltMode() function
844
845
846 CLK_Handle CLK_init(void *pMemory,const size_t numBytes)
847 {
848 CLK_Handle clkHandle;
849
850
851 if(numBytes < sizeof(CLK_Obj))
852 return((CLK_Handle)NULL);
853
854 // assign the handle
855 clkHandle = (CLK_Handle)pMemory;
856
857 return(clkHandle);
858 } // end of CLK_init() function
859
860
861 void CLK_setClkOutPreScaler(CLK_Handle clkHandle,
862 const CLK_ClkOutPreScaler_e preScaler)
863 {
864 CLK_Obj *clk = (CLK_Obj *)clkHandle;
865
866
867 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
868
869 // clear the bits
870 clk->XCLK &= (~CLK_XCLK_XCLKOUTDIV_BITS);
871
872 // set the bits
873 clk->XCLK |= preScaler;
874
875 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
876
877 return;
878 } // end of CLK_setClkOutPreScaler() function
879
880
881 void CLK_setLowSpdPreScaler(CLK_Handle clkHandle,
882 const CLK_LowSpdPreScaler_e preScaler)
883 {
884 CLK_Obj *clk = (CLK_Obj *)clkHandle;
885
886
887 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
888
889 // set the bits
890 clk->LOSPCP = preScaler;
891
892 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
893
894 return;
895 } // end of CLK_setLowSpdPreScaler() function
896
897
898 void CLK_setOscSrc(CLK_Handle clkHandle,const CLK_OscSrc_e src)
899 {
900 CLK_Obj *clk = (CLK_Obj *)clkHandle;
901
902
903 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
904
905 // clear the bits
906 clk->CLKCTL &= (~CLK_CLKCTL_OSCCLKSRCSEL_BITS);
907
908 // set the bits
909 clk->CLKCTL |= src;
910
911 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
912
913 return;
914 } // end of CLK_setOscSrc() function
915
916
917 void CLK_setOsc2Src(CLK_Handle clkHandle,const CLK_Osc2Src_e src)
918 {
919 CLK_Obj *clk = (CLK_Obj *)clkHandle;
920
921
922 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
923
924 // clear the bits
925 clk->CLKCTL &= (~CLK_CLKCTL_OSCCLKSRC2SEL_BITS);
926
927 // set the bits
928 clk->CLKCTL |= src;
929
930 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
931
932 return;
933 } // end of CLK_setOsc2Src() function
934
935
936 void CLK_setXClkInSrc(CLK_Handle clkHandle, const CLK_XClkInSrc_e src)
937 {
938 CLK_Obj *clk = (CLK_Obj *)clkHandle;
939
940 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
941
942 // clear the bits
943 clk->XCLK &= (~CLK_XCLK_XCLKINSEL_BITS);
944
945 //set the bits
946 clk->XCLK |= src;
947
948 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
949
950 return;
951 } //end of CLK_setXCLKINSrc() function
952
953
954 void CLK_setTimer2PreScale(CLK_Handle clkHandle,
955 const CLK_Timer2PreScaler_e preScaler)
956 {
957 CLK_Obj *clk = (CLK_Obj *)clkHandle;
958
959
960 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
961
962 // clear the bits
963 clk->CLKCTL &= (~CLK_CLKCTL_TMR2CLKPRESCALE_BITS);
964
965 // set the bits
966 clk->CLKCTL |= preScaler;
967
968 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
969
970 return;
971 } // end of CLK_setTimer2PreScaler() function
972
973
974 void CLK_setTimer2Src(CLK_Handle clkHandle,const CLK_Timer2Src_e src)
975 {
976 CLK_Obj *clk = (CLK_Obj *)clkHandle;
977
978
979 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
980
981 // clear the bits
982 clk->CLKCTL &= (~CLK_CLKCTL_TMR2CLKSRCSEL_BITS);
983
984 // set the bits
985 clk->CLKCTL |= src;
986
987 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
988
989 return;
990 } // end of CLK_setTimer2Src() function
991
992
993 void CLK_setWatchDogSrc(CLK_Handle clkHandle,const CLK_WdClkSrc_e src)
994 {
995 CLK_Obj *clk = (CLK_Obj *)clkHandle;
996
997
998 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
999
1000 // clear the bits
1001 clk->CLKCTL &= (~CLK_CLKCTL_WDCLKSRCSEL_BITS);
1002
1003 // set the bits
1004 clk->CLKCTL |= src;
1005
1006 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
1007
1008 return;
1009 } // end of CLK_setWatchDogSrc() function
1010
1011
1012
1013 // end of file
CLK_XClkInSrc_e
CLK_XClkInSrc_e
Enumeration to define the clock in source.
Definition: clk.h:305
CLK_CLKCTL_INTOSC2OFF_BITS
#define CLK_CLKCTL_INTOSC2OFF_BITS
Defines the location of the INTOSC2OFF bits in the CLKCTL register.
Definition: clk.h:230
CLK_disableCpuTimerClock
void CLK_disableCpuTimerClock(CLK_Handle clkHandle, const CLK_CpuTimerNumber_e cpuTimerNumber)
Disables the CPU timer clock.
Definition: clk.c:117
CLK_PCLKCR0_SPIBENCLK_BITS
#define CLK_PCLKCR0_SPIBENCLK_BITS
Defines the location of the SPIBENCLK bits in the PCLKCR0 register.
Definition: clk.h:98
CLK_disableAdcClock
void CLK_disableAdcClock(CLK_Handle clkHandle)
Disables the ADC clock.
Definition: clk.c:57
_CLK_Obj_
Defines the clock (CLK) object.
Definition: clk.h:364
CLK_XCLK_XCLKINSEL_BITS
#define CLK_XCLK_XCLKINSEL_BITS
Defines the location of the XCLKINSEL bits in the XCLK register.
Definition: clk.h:197
CLK_enableSpiaClock
void CLK_enableSpiaClock(CLK_Handle clkHandle)
Enables the SPI-A clock.
Definition: clk.c:782
CLK_Osc2Src_e
CLK_Osc2Src_e
Enumeration to define the clock oscillator 2 source.
Definition: clk.h:323
CLK_CLKCTL_OSCCLKSRCSEL_BITS
#define CLK_CLKCTL_OSCCLKSRCSEL_BITS
Defines the location of the OSCCLKSRCSEL bits in the CLKCTL register.
Definition: clk.h:202
DISABLE_PROTECTED_REGISTER_WRITE_MODE
#define DISABLE_PROTECTED_REGISTER_WRITE_MODE
Define to disable protected register writes.
Definition: cpu.h:101
CLK_CLKCTL_WDCLKSRCSEL_BITS
#define CLK_CLKCTL_WDCLKSRCSEL_BITS
Defines the location of the WDCLKSRCSEL bits in the CLKCTL register.
Definition: clk.h:210
CLK_disableSpibClock
void CLK_disableSpibClock(CLK_Handle clkHandle)
Disables the SPI-B clock.
Definition: clk.c:404
CLK_setXClkInSrc
void CLK_setXClkInSrc(CLK_Handle clkHandle, const CLK_XClkInSrc_e src)
Sets the XCLKIN Clock Source.
Definition: clk.c:936
CLK_disableTbClockSync
void CLK_disableTbClockSync(CLK_Handle clkHandle)
Disables the ePWM module time base clock sync signal.
Definition: clk.c:416
CLK_enableTbClockSync
void CLK_enableTbClockSync(CLK_Handle clkHandle)
Enables the ePWM module time base clock sync signal.
Definition: clk.c:814
CLK_disableEqep1Clock
void CLK_disableEqep1Clock(CLK_Handle clkHandle)
Disables the EQEP1 clock.
Definition: clk.c:181
CLK_setTimer2PreScale
void CLK_setTimer2PreScale(CLK_Handle clkHandle, const CLK_Timer2PreScaler_e preScaler)
Definition: clk.c:954
CLK_setOscSrc
void CLK_setOscSrc(CLK_Handle clkHandle, const CLK_OscSrc_e src)
Sets the oscillator clock source.
Definition: clk.c:898
CLK_setWatchDogSrc
void CLK_setWatchDogSrc(CLK_Handle clkHandle, const CLK_WdClkSrc_e src)
Sets the watchdog clock source.
Definition: clk.c:993
CLK_enableClkIn
void CLK_enableClkIn(CLK_Handle clkHandle)
Enables the XCLKIN oscillator input.
Definition: clk.c:590
CLK_disableEcanaClock
void CLK_disableEcanaClock(CLK_Handle clkHandle)
Disables the ECANA clock.
Definition: clk.c:149
CLK_CLKCTL_XTALOSCOFF_BITS
#define CLK_CLKCTL_XTALOSCOFF_BITS
Defines the location of the XTALOSCOFF bits in the CLKCTL register.
Definition: clk.h:246
CLK_enableSciaClock
void CLK_enableSciaClock(CLK_Handle clkHandle)
Enables the SCI-A clock.
Definition: clk.c:750
CLK_enableCpuTimerClock
void CLK_enableCpuTimerClock(CLK_Handle clkHandle, const CLK_CpuTimerNumber_e cpuTimerNumber)
Enables the CPU timer clock.
Definition: clk.c:496
CLK_enableWatchDogHaltMode
void CLK_enableWatchDogHaltMode(CLK_Handle clkHandle)
Enables the watchdog halt mode ignore.
Definition: clk.c:830
CLK_LowSpdPreScaler_e
CLK_LowSpdPreScaler_e
Enumeration to define the low speed clock prescaler, which sets the clock frequency.
Definition: clk.h:290
CLK_XCLK_XCLKOUTDIV_BITS
#define CLK_XCLK_XCLKOUTDIV_BITS
Defines the location of the XCLKOUTDIV bits in the XCLK register.
Definition: clk.h:193
CLK_PCLKCR0_HRPWMENCLK_BITS
#define CLK_PCLKCR0_HRPWMENCLK_BITS
Defines the location of the HRPWMENCLK bits in the PCLKCR0 register.
Definition: clk.h:74
CLK_CLKCTL_TMR2CLKSRCSEL_BITS
#define CLK_CLKCTL_TMR2CLKSRCSEL_BITS
Defines the location of the TMR2CLKSRCSEL bits in the CLKCTL register.
Definition: clk.h:214
CLK_CLKCTL_INTOSC1OFF_BITS
#define CLK_CLKCTL_INTOSC1OFF_BITS
Defines the location of the INTOSC1OFF bits in the CLKCTL register.
Definition: clk.h:222
CLK_disableScibClock
void CLK_disableScibClock(CLK_Handle clkHandle)
Disables the SCI-B clock.
Definition: clk.c:372
CLK_enableCompClock
void CLK_enableCompClock(CLK_Handle clkHandle, const CLK_CompNumber_e compNumber)
Enables the comparator clock.
Definition: clk.c:480
CLK_enableOsc2
void CLK_enableOsc2(CLK_Handle clkHandle)
Enables internal oscillator 2.
Definition: clk.c:702
CLK_CLKCTL_INTOSC2HALTI_BITS
#define CLK_CLKCTL_INTOSC2HALTI_BITS
Defines the location of the INTOSC2HALTI bits in the CLKCTL register.
Definition: clk.h:234
CLK_disableClkIn
void CLK_disableClkIn(CLK_Handle clkHandle)
Disables the XCLKIN oscillator input.
Definition: clk.c:89
CLK_enableScibClock
void CLK_enableScibClock(CLK_Handle clkHandle)
Enables the SCI-B clock.
Definition: clk.c:766
CLK_init
CLK_Handle CLK_init(void *pMemory, const size_t numBytes)
Initializes the clock (CLK) object handle.
Definition: clk.c:846
CLK_enableClaClock
void CLK_enableClaClock(CLK_Handle clkHandle)
Enables the CLA clock.
Definition: clk.c:464
CLK_setTimer2Src
void CLK_setTimer2Src(CLK_Handle clkHandle, const CLK_Timer2Src_e src)
Sets the timer 2 clock source.
Definition: clk.c:974
_CLK_Obj_::LOSPCP
volatile uint16_t LOSPCP
Low-Speed Peripheral Clock Pre-Scaler Register.
Definition: clk.h:370
ENABLE_PROTECTED_REGISTER_WRITE_MODE
#define ENABLE_PROTECTED_REGISTER_WRITE_MODE
Define to allow protected register writes.
Definition: cpu.h:93
CLK_setOsc2Src
void CLK_setOsc2Src(CLK_Handle clkHandle, const CLK_Osc2Src_e src)
Sets the oscillator 2 clock source.
Definition: clk.c:917
CLK_CompNumber_e
CLK_CompNumber_e
Enumeration to define the comparator numbers.
Definition: clk.h:270
CLK_CLKCTL_INTOSC1HALTI_BITS
#define CLK_CLKCTL_INTOSC1HALTI_BITS
Defines the location of the INTOSC1HALTI bits in the CLKCTL register.
Definition: clk.h:226
CLK_ClkOutPreScaler_e
CLK_ClkOutPreScaler_e
Enumeration to define the external clock output frequency.
Definition: clk.h:259
CLK_Handle
struct _CLK_Obj_ * CLK_Handle
Defines the clock (CLK) handle.
Definition: clk.h:380
CLK_PCLKCR0_SCIAENCLK_BITS
#define CLK_PCLKCR0_SCIAENCLK_BITS
Defines the location of the SCIAENCLK bits in the PCLKCR0 register.
Definition: clk.h:102
CLK_enableSpibClock
void CLK_enableSpibClock(CLK_Handle clkHandle)
Enables the SPI-B clock.
Definition: clk.c:798
CLK_enableGpioInputClock
void CLK_enableGpioInputClock(CLK_Handle clkHandle)
Enables the GPIO input clock.
Definition: clk.c:606
CLK_Timer2PreScaler_e
CLK_Timer2PreScaler_e
Enumeration to define the timer 2 prescaler, which sets the timer 2 frequency.
Definition: clk.h:332
CLK_enableEqep2Clock
void CLK_enableEqep2Clock(CLK_Handle clkHandle)
Enables the EQEP2 clock.
Definition: clk.c:559
CLK_disableOsc2HaltMode
void CLK_disableOsc2HaltMode(CLK_Handle clkHandle)
Disables internal oscillator 2 halt mode ignore.
Definition: clk.c:324
CLK_disablePwmClock
void CLK_disablePwmClock(CLK_Handle clkHandle, const PWM_Number_e pwmNumber)
Disables the pwm clock.
Definition: clk.c:340
CLK_PCLKCR3_GPIOINENCLK_BITS
#define CLK_PCLKCR3_GPIOINENCLK_BITS
Defines the location of the GPIOINENCLK bits in the PCLKCR3 register.
Definition: clk.h:179
CLK_PCLKCR0_TBCLKSYNC_BITS
#define CLK_PCLKCR0_TBCLKSYNC_BITS
Defines the location of the TBCLKSYNC bits in the PCLKCR0 register.
Definition: clk.h:82
clk.h
Contains public interface to various functions related to the clock (CLK) object. ...
CLK_enableEqep1Clock
void CLK_enableEqep1Clock(CLK_Handle clkHandle)
Enables the EQEP1 clock.
Definition: clk.c:544
CLK_enableLinAClock
void CLK_enableLinAClock(CLK_Handle clkHandle)
Enables the LIN-A clock.
Definition: clk.c:654
CLK_setLowSpdPreScaler
void CLK_setLowSpdPreScaler(CLK_Handle clkHandle, const CLK_LowSpdPreScaler_e preScaler)
Sets the low speed peripheral clock prescaler.
Definition: clk.c:881
CLK_disableI2cClock
void CLK_disableI2cClock(CLK_Handle clkHandle)
Disables the I2C clock.
Definition: clk.c:244
CLK_PCLKCR0_I2CAENCLK_BITS
#define CLK_PCLKCR0_I2CAENCLK_BITS
Defines the location of the I2CAENCLK bits in the PCLKCR0 register.
Definition: clk.h:90
CLK_Timer2Src_e
CLK_Timer2Src_e
Enumeration to define the timer 2 source.
Definition: clk.h:344
_CLK_Obj_::XCLK
volatile uint16_t XCLK
XCLKOUT/XCLKIN Control.
Definition: clk.h:366
CLK_disableSpiaClock
void CLK_disableSpiaClock(CLK_Handle clkHandle)
Disables the SPI-A clock.
Definition: clk.c:388
CLK_enableOsc1
void CLK_enableOsc1(CLK_Handle clkHandle)
Enables internal oscillator 1.
Definition: clk.c:670
CLK_enableEcap1Clock
void CLK_enableEcap1Clock(CLK_Handle clkHandle)
Enables the ECAP1 clock.
Definition: clk.c:574
CLK_PCLKCR0_ECANAENCLK_BITS
#define CLK_PCLKCR0_ECANAENCLK_BITS
Defines the location of the ECANAENCLK bits in the PCLKCR0 register.
Definition: clk.h:110
CLK_PCLKCR0_LINAENCLK_BITS
#define CLK_PCLKCR0_LINAENCLK_BITS
Defines the location of the LINAENCLK bits in the PCLKCR0 register.
Definition: clk.h:78
CLK_disableOsc1HaltMode
void CLK_disableOsc1HaltMode(CLK_Handle clkHandle)
Disables internal oscillator 1 halt mode ignore.
Definition: clk.c:292
CLK_disableSciaClock
void CLK_disableSciaClock(CLK_Handle clkHandle)
Disables the SCI-A clock.
Definition: clk.c:356
CLK_enableEcanaClock
void CLK_enableEcanaClock(CLK_Handle clkHandle)
Enables the ECANA clock.
Definition: clk.c:528
CLK_CLKCTL_WDHALTI_BITS
#define CLK_CLKCTL_WDHALTI_BITS
Defines the location of the WDHALTI bits in the CLKCTL register.
Definition: clk.h:238
CLK_disableEqep2Clock
void CLK_disableEqep2Clock(CLK_Handle clkHandle)
Disables the EQEP2 clock.
Definition: clk.c:196
_CLK_Obj_::PCLKCR1
volatile uint16_t PCLKCR1
Peripheral Clock Control Register 1.
Definition: clk.h:372
CLK_disableClaClock
void CLK_disableClaClock(CLK_Handle clkHandle)
Disables the CLA clock.
Definition: clk.c:73
CLK_PCLKCR0_ADCENCLK_BITS
#define CLK_PCLKCR0_ADCENCLK_BITS
Defines the location of the ADCENCLK bits in the PCLKCR0 register.
Definition: clk.h:86
CLK_WdClkSrc_e
CLK_WdClkSrc_e
Enumeration to define the watchdog clock source.
Definition: clk.h:355
CLK_disableEcap1Clock
void CLK_disableEcap1Clock(CLK_Handle clkHandle)
Disables the ECAP1 clock.
Definition: clk.c:165
CLK_enableI2cClock
void CLK_enableI2cClock(CLK_Handle clkHandle)
Enables the I2C clock.
Definition: clk.c:638
CLK_PCLKCR1_ECAP1ENCLK_BITS
#define CLK_PCLKCR1_ECAP1ENCLK_BITS
Defines the location of the ECAP1ENCLK bits in the PCLKCR1 register.
Definition: clk.h:143
CLK_PCLKCR1_EQEP2ENCLK_BITS
#define CLK_PCLKCR1_EQEP2ENCLK_BITS
Defines the location of the EQEP2ENCLK bits in the PCLKCR1 register.
Definition: clk.h:151
_CLK_Obj_::CLKCTL
volatile uint16_t CLKCTL
Clock Control Register.
Definition: clk.h:368
CLK_enableOsc1HaltMode
void CLK_enableOsc1HaltMode(CLK_Handle clkHandle)
Enables internal oscillator 1 halt mode ignore.
Definition: clk.c:686
CLK_PCLKCR0_SPIAENCLK_BITS
#define CLK_PCLKCR0_SPIAENCLK_BITS
Defines the location of the SPIAENCLK bits in the PCLKCR0 register.
Definition: clk.h:94
CLK_enableCrystalOsc
void CLK_enableCrystalOsc(CLK_Handle clkHandle)
Enables the crystal oscillator.
Definition: clk.c:512
CLK_CLKCTL_XCLKINOFF_BITS
#define CLK_CLKCTL_XCLKINOFF_BITS
Defines the location of the XCLKINOFF bits in the CLKCTL register.
Definition: clk.h:242
CLK_disableLinAClock
void CLK_disableLinAClock(CLK_Handle clkHandle)
Disables the LIN-A clock.
Definition: clk.c:260
CLK_disableGpioInputClock
void CLK_disableGpioInputClock(CLK_Handle clkHandle)
Disables the GPIO input clock.
Definition: clk.c:212
CLK_setClkOutPreScaler
void CLK_setClkOutPreScaler(CLK_Handle clkHandle, const CLK_ClkOutPreScaler_e preScaler)
Sets the external clock out prescaler.
Definition: clk.c:861
CLK_disableWatchDogHaltMode
void CLK_disableWatchDogHaltMode(CLK_Handle clkHandle)
Disables the watchdog halt mode ignore.
Definition: clk.c:432
CLK_PCLKCR3_CLA1ENCLK_BITS
#define CLK_PCLKCR3_CLA1ENCLK_BITS
Defines the location of the CLA1ENCLK bits in the PCLKCR3 register.
Definition: clk.h:183
_CLK_Obj_::PCLKCR3
volatile uint16_t PCLKCR3
Peripheral Clock Control Register 3.
Definition: clk.h:374
CLK_disableCompClock
void CLK_disableCompClock(CLK_Handle clkHandle, const CLK_CompNumber_e compNumber)
Disables the comparator clock.
Definition: clk.c:105
_CLK_Obj_::PCLKCR0
volatile uint16_t PCLKCR0
Peripheral Clock Control Register 0.
Definition: clk.h:371
CLK_enableOsc2HaltMode
void CLK_enableOsc2HaltMode(CLK_Handle clkHandle)
Enables internal oscillator 2 halt mode ignore.
Definition: clk.c:718
CLK_PCLKCR0_SCIBENCLK_BITS
#define CLK_PCLKCR0_SCIBENCLK_BITS
Defines the location of the SCIBENCLK bits in the PCLKCR0 register.
Definition: clk.h:106
CLK_CpuTimerNumber_e
CLK_CpuTimerNumber_e
Enumeration to define the CPU timer numbers.
Definition: clk.h:280
CLK_enableAdcClock
void CLK_enableAdcClock(CLK_Handle clkHandle)
Enables the ADC clock.
Definition: clk.c:448
PWM_Number_e
PWM_Number_e
Enumeration to define the pulse width modulation (PWM) numbers.
Definition: pwm.h:715
CLK_PCLKCR1_EQEP1ENCLK_BITS
#define CLK_PCLKCR1_EQEP1ENCLK_BITS
Defines the location of the EQEP1ENCLK bits in the PCLKCR1 register.
Definition: clk.h:147
CLK_disableOsc2
void CLK_disableOsc2(CLK_Handle clkHandle)
Disables internal oscillator 2.
Definition: clk.c:308
CLK_enablePwmClock
void CLK_enablePwmClock(CLK_Handle clkHandle, const PWM_Number_e pwmNumber)
Enables the pwm clock.
Definition: clk.c:734
CLK_disableHrPwmClock
void CLK_disableHrPwmClock(CLK_Handle clkHandle)
Disables the HRPWM clock.
Definition: clk.c:228
CLK_OscSrc_e
CLK_OscSrc_e
Enumeration to define the clock oscillator source.
Definition: clk.h:314
CLK_CLKCTL_TMR2CLKPRESCALE_BITS
#define CLK_CLKCTL_TMR2CLKPRESCALE_BITS
Defines the location of the TMR2CLKPRESCALE bits in the CLKCTL register.
Definition: clk.h:218
CLK_disableCrystalOsc
void CLK_disableCrystalOsc(CLK_Handle clkHandle)
Disables the crystal oscillator.
Definition: clk.c:133
CLK_CLKCTL_OSCCLKSRC2SEL_BITS
#define CLK_CLKCTL_OSCCLKSRC2SEL_BITS
Defines the location of the OSCCLKSRC2SEL bits in the CLKCTL register.
Definition: clk.h:206
CLK_enableHrPwmClock
void CLK_enableHrPwmClock(CLK_Handle clkHandle)
Enables the HRPWM clock.
Definition: clk.c:622
CLK_disableOsc1
void CLK_disableOsc1(CLK_Handle clkHandle)
Disables internal oscillator 1.
Definition: clk.c:276