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pll.c
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1 /* --COPYRIGHT--,BSD
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38
39
40 // **************************************************************************
41 // the includes
42
43 #include "sw/drivers/pll/src/32b/f28x/f2806x/pll.h"
44
45
46 // **************************************************************************
47 // the defines
48
49
50 // **************************************************************************
51 // the globals
52
53
54 // **************************************************************************
55 // the functions
56
57 void PLL_disable(PLL_Handle pllHandle)
58 {
59 PLL_Obj *pll = (PLL_Obj *)pllHandle;
60
61
62 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
63
64 // set the bits
65 pll->PLLSTS |= PLL_PLLSTS_PLLOFF_BITS;
66
67 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
68
69 return;
70 } // end of PLL_disable() function
71
72
73 void PLL_disableClkDetect(PLL_Handle pllHandle)
74 {
75 PLL_Obj *pll = (PLL_Obj *)pllHandle;
76
77
78 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
79
80 // set the bits
81 pll->PLLSTS |= PLL_PLLSTS_MCLKOFF_BITS;
82
83 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
84
85 return;
86 } // end of PLL_disableClkDetect() function
87
88
89 void PLL_disableNormRdy(PLL_Handle pllHandle)
90 {
91 PLL_Obj *pll = (PLL_Obj *)pllHandle;
92
93
94 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
95
96 // clear the bits
97 pll->PLLSTS &= (~PLL_PLLSTS_NORMRDYE_BITS);
98
99 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
100
101 return;
102 } // end of PLL_disableNormRdy() function
103
104
105 void PLL_disableOsc(PLL_Handle pllHandle)
106 {
107 PLL_Obj *pll = (PLL_Obj *)pllHandle;
108
109
110 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
111
112 // set the bits
113 pll->PLLSTS |= PLL_PLLSTS_OSCOFF_BITS;
114
115 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
116
117 return;
118 } // end of PLL_disableOsc() function
119
120
121 void PLL_enable(PLL_Handle pllHandle)
122 {
123 PLL_Obj *pll = (PLL_Obj *)pllHandle;
124
125
126 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
127
128 // clear the bits
129 pll->PLLSTS &= (~PLL_PLLSTS_PLLOFF_BITS);
130
131 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
132
133 return;
134 } // end of PLL_enable() function
135
136
137 void PLL_enableClkDetect(PLL_Handle pllHandle)
138 {
139 PLL_Obj *pll = (PLL_Obj *)pllHandle;
140
141
142 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
143
144 // clear the bits
145 pll->PLLSTS &= (~PLL_PLLSTS_MCLKOFF_BITS);
146
147 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
148
149 return;
150 } // end of PLL_enableClkDetect() function
151
152
153 void PLL_enableNormRdy(PLL_Handle pllHandle)
154 {
155 PLL_Obj *pll = (PLL_Obj *)pllHandle;
156
157
158 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
159
160 // set the bits
161 pll->PLLSTS |= (uint16_t)PLL_PLLSTS_NORMRDYE_BITS;
162
163 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
164
165 return;
166 } // end of PLL_enableNormRdy() function
167
168
169 void PLL_enableOsc(PLL_Handle pllHandle)
170 {
171 PLL_Obj *pll = (PLL_Obj *)pllHandle;
172
173
174 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
175
176 // clear the bits
177 pll->PLLSTS &= (~PLL_PLLSTS_OSCOFF_BITS);
178
179 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
180
181 return;
182 } // end of PLL_enableOsc() function
183
184
185 PLL_ClkFreq_e PLL_getClkFreq(PLL_Handle pllHandle)
186 {
187 PLL_Obj *pll = (PLL_Obj *)pllHandle;
188
189
190 // get the clock rate
191 PLL_ClkFreq_e clkFreq = (PLL_ClkFreq_e)(pll->PLLCR & PLL_PLLCR_DIV_BITS);
192
193 return(clkFreq);
194 } // end of PLL_getClkFreq() function
195
196
197 PLL_ClkStatus_e PLL_getClkStatus(PLL_Handle pllHandle)
198 {
199 PLL_Obj *pll = (PLL_Obj *)pllHandle;
200
201 // mask the bits
202 PLL_ClkStatus_e status = (PLL_ClkStatus_e)(pll->PLLSTS & PLL_PLLSTS_MCLKSTS_BITS);
203
204 return(status);
205 } // end of PLL_getClkStatus() function
206
207
208 PLL_DivideSelect_e PLL_getDivideSelect(PLL_Handle pllHandle)
209 {
210 PLL_Obj *pll = (PLL_Obj *)pllHandle;
211
212 // mask the bits
213 PLL_DivideSelect_e divSelect = (PLL_DivideSelect_e)(pll->PLLSTS & PLL_PLLSTS_DIVSEL_BITS);
214
215 return(divSelect);
216 } // end of PLL_getDivideSelect() function
217
218
219 PLL_LockStatus_e PLL_getLockStatus(PLL_Handle pllHandle)
220 {
221 volatile PLL_Obj *pll = (PLL_Obj *)pllHandle;
222
223
224 // mask the bits
225 PLL_LockStatus_e status = (PLL_LockStatus_e)(pll->PLLSTS & PLL_PLLSTS_PLLLOCKS_BITS);
226
227 return(status);
228 } // end of PLL_getLockStatus() function
229
230
231 PLL_Handle PLL_init(void *pMemory, const size_t numBytes)
232 {
233 PLL_Handle pllHandle;
234
235
236 if(numBytes < sizeof(PLL_Obj))
237 return((PLL_Handle)NULL);
238
239 // assign the handle
240 pllHandle = (PLL_Handle)pMemory;
241
242 return(pllHandle);
243 } // end of PLL_init() function
244
245
246 void PLL_resetClkDetect(PLL_Handle pllHandle)
247 {
248 PLL_Obj *pll = (PLL_Obj *)pllHandle;
249
250
251 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
252
253 // set the bits
254 pll->PLLSTS |= PLL_PLLSTS_MCLKCLR_BITS;
255
256 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
257
258 return;
259 } // end of PLL_resetClkDetect() function
260
261
262 void PLL_setClkFreq(PLL_Handle pllHandle,const PLL_ClkFreq_e clkFreq)
263 {
264 PLL_Obj *pll = (PLL_Obj *)pllHandle;
265
266
267 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
268
269 // set the bits
270 pll->PLLCR = clkFreq;
271
272 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
273
274 return;
275 } // end of PLL_setClkFreq() function
276
277
278 void PLL_setDivideSelect(PLL_Handle pllHandle,const PLL_DivideSelect_e divSelect)
279 {
280 PLL_Obj *pll = (PLL_Obj *)pllHandle;
281
282
283 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
284
285 // clear the bits
286 pll->PLLSTS &= (~PLL_PLLSTS_DIVSEL_BITS);
287
288 // set the bits
289 pll->PLLSTS |= divSelect;
290
291 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
292
293 return;
294 } // end of PLL_setDivideSelect() function
295
296
297 void PLL_setLockPeriod(PLL_Handle pllHandle, const uint16_t lockPeriod)
298 {
299 PLL_Obj *pll = (PLL_Obj *)pllHandle;
300
301
302 ENABLE_PROTECTED_REGISTER_WRITE_MODE;
303
304 // set the bits
305 pll->PLLLOCKPRD = lockPeriod;
306
307 DISABLE_PROTECTED_REGISTER_WRITE_MODE;
308
309 return;
310 } // end of PLL_setLockPeriod() function
311
312
313 // end of file
PLL_disableClkDetect
void PLL_disableClkDetect(PLL_Handle pllHandle)
Disables the clock detect logic.
Definition: pll.c:73
DISABLE_PROTECTED_REGISTER_WRITE_MODE
#define DISABLE_PROTECTED_REGISTER_WRITE_MODE
Define to disable protected register writes.
Definition: cpu.h:101
PLL_PLLSTS_MCLKOFF_BITS
#define PLL_PLLSTS_MCLKOFF_BITS
Defines the location of the MCLKOFF bits in the PLLSTS register.
Definition: pll.h:99
PLL_PLLSTS_PLLLOCKS_BITS
#define PLL_PLLSTS_PLLLOCKS_BITS
Defines the location of the PLLLOCKS bits in the PLLSTS register.
Definition: pll.h:79
PLL_PLLSTS_NORMRDYE_BITS
#define PLL_PLLSTS_NORMRDYE_BITS
Defines the location of the NORMRDYE bits in the PLLSTS register.
Definition: pll.h:107
PLL_enable
void PLL_enable(PLL_Handle pllHandle)
Enables the phase lock loop (PLL)
Definition: pll.c:121
_PLL_Obj_::PLLSTS
volatile uint16_t PLLSTS
PLL Status Register.
Definition: pll.h:171
PLL_PLLSTS_OSCOFF_BITS
#define PLL_PLLSTS_OSCOFF_BITS
Defines the location of the OSCOFF bits in the PLLSTS register.
Definition: pll.h:95
PLL_getLockStatus
PLL_LockStatus_e PLL_getLockStatus(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) lock status.
Definition: pll.c:219
PLL_disableNormRdy
void PLL_disableNormRdy(PLL_Handle pllHandle)
Disables the NORMRDY signal.
Definition: pll.c:89
PLL_PLLSTS_MCLKCLR_BITS
#define PLL_PLLSTS_MCLKCLR_BITS
Defines the location of the MCLKCLR bits in the PLLSTS register.
Definition: pll.h:91
PLL_getClkStatus
PLL_ClkStatus_e PLL_getClkStatus(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) clock status.
Definition: pll.c:197
PLL_disable
void PLL_disable(PLL_Handle pllHandle)
Disables the phase lock loop (PLL)
Definition: pll.c:57
ENABLE_PROTECTED_REGISTER_WRITE_MODE
#define ENABLE_PROTECTED_REGISTER_WRITE_MODE
Define to allow protected register writes.
Definition: cpu.h:93
PLL_setDivideSelect
void PLL_setDivideSelect(PLL_Handle pllHandle, const PLL_DivideSelect_e divSelect)
Sets the phase lock loop (PLL) divide select value.
Definition: pll.c:278
PLL_getClkFreq
PLL_ClkFreq_e PLL_getClkFreq(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) clock frequency.
Definition: pll.c:185
PLL_disableOsc
void PLL_disableOsc(PLL_Handle pllHandle)
Disables the oscillator.
Definition: pll.c:105
PLL_enableNormRdy
void PLL_enableNormRdy(PLL_Handle pllHandle)
Enables the NORMRDY signal.
Definition: pll.c:153
PLL_Handle
struct _PLL_Obj_ * PLL_Handle
Defines the phase lock loop (PLL) handle.
Definition: pll.h:181
PLL_enableClkDetect
void PLL_enableClkDetect(PLL_Handle pllHandle)
Enables the clock detect logic.
Definition: pll.c:137
pll.h
Contains public interface to various functions related to the phase-locked loop (PLL) object...
_PLL_Obj_
Defines the phase lock loop (PLL) object.
Definition: pll.h:169
PLL_setClkFreq
void PLL_setClkFreq(PLL_Handle pllHandle, const PLL_ClkFreq_e clkFreq)
Sets the phase lock loop (PLL) clock frequency.
Definition: pll.c:262
PLL_ClkFreq_e
PLL_ClkFreq_e
Enumeration to define the phase lock loop (PLL) clock frequency.
Definition: pll.h:116
PLL_DivideSelect_e
PLL_DivideSelect_e
Enumeration to define the phase lock loop (PLL) divide select.
Definition: pll.h:141
PLL_PLLSTS_PLLOFF_BITS
#define PLL_PLLSTS_PLLOFF_BITS
Defines the location of the PLLOFF bits in the PLLSTS register.
Definition: pll.h:83
PLL_getDivideSelect
PLL_DivideSelect_e PLL_getDivideSelect(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) divide select value.
Definition: pll.c:208
PLL_PLLCR_DIV_BITS
#define PLL_PLLCR_DIV_BITS
Defines the location of the DIV bits in the PLLCR register.
Definition: pll.h:74
PLL_setLockPeriod
void PLL_setLockPeriod(PLL_Handle pllHandle, const uint16_t lockPeriod)
Sets the phase lock loop (PLL) lock time.
Definition: pll.c:297
_PLL_Obj_::PLLLOCKPRD
volatile uint16_t PLLLOCKPRD
PLL Lock Period Register.
Definition: pll.h:173
PLL_init
PLL_Handle PLL_init(void *pMemory, const size_t numBytes)
Initializes the phase lock loop (PLL) object handle.
Definition: pll.c:231
PLL_PLLSTS_MCLKSTS_BITS
#define PLL_PLLSTS_MCLKSTS_BITS
Defines the location of the MCLKSTS bits in the PLLSTS register.
Definition: pll.h:87
_PLL_Obj_::PLLCR
volatile uint16_t PLLCR
PLL Control Register.
Definition: pll.h:175
PLL_resetClkDetect
void PLL_resetClkDetect(PLL_Handle pllHandle)
Resets the phase lock loop (PLL) clock detect logic.
Definition: pll.c:246
PLL_PLLSTS_DIVSEL_BITS
#define PLL_PLLSTS_DIVSEL_BITS
Defines the location of the DIVSEL bits in the PLLSTS register.
Definition: pll.h:103
PLL_LockStatus_e
PLL_LockStatus_e
Enumeration to define the phase lock loop (PLL) clock lock status.
Definition: pll.h:160
PLL_ClkStatus_e
PLL_ClkStatus_e
Enumeration to define the phase lock loop (PLL) clock status.
Definition: pll.h:151
PLL_enableOsc
void PLL_enableOsc(PLL_Handle pllHandle)
Enables the oscillator.
Definition: pll.c:169