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lin.h
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1 /* --COPYRIGHT--,BSD
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33
34
35
36 #ifndef _LIN_H_
37 #define _LIN_H_
38
39 // TI File $Revision: /main/4 $
40 // Checkin $Date: April 29, 2009 09:56:39 $
41 //###########################################################################
42 //
43 // FILE: LIN.h
44 //
45 // TITLE: DSP2803x Device LIN Register Definitions.
46 //
47 //###########################################################################
48 // $TI Release: 2803x C/C++ Header Files and Peripheral Examples V1.23 $
49 // $Release Date: October 15, 2010 $
50 //###########################################################################
51
52 #include "sw/modules/types/src/types.h"
53
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57
58 /* --------------------------------------------------- */
59 /* LIN Registers */
60 /* ----------------------------------------------------*/
61
62 /* Global Control Register 0 (SCIGCR0) bit definitions */
63 struct SCIGCR0_BITS { // bit description
64 uint16_t RESET:1; // 0 LIN Module reset bit
65 uint16_t rsvd1:15; // 15:1 reserved
66 uint16_t rsvd2:16; // 31:16 reserved
67 };
68
69 /* Allow access to the bit fields or entire register */
70 union SCIGCR0_REG {
71 uint32_t all;
72 struct SCIGCR0_BITS bit;
73 };
74
75 /* Global Control Register 1 (SCIGCR1) bit definitions */
76 struct SCIGCR1_BITS { // bit description
77 uint16_t COMMMODE:1; // 0 SCI/LIN communications mode bit
78 uint16_t TIMINGMODE:1; // 1 SCI timing mode bit. Should be set to 1 for SCI mode.
79 uint16_t PARITYENA:1; // 2 Parity enable
80 uint16_t PARITY:1; // 3 SCI parity odd/even selection
81 uint16_t STOP:1; // 4 SCI number of stop bits
82 uint16_t CLK_MASTER:1; // 5 LIN Master/Slave selection and SCI clock enable
83 uint16_t LINMODE:1; // 6 LIN Mode enable/disable
84 uint16_t SWnRST:1; // 7 Software reset
85 uint16_t SLEEP:1; // 8 SCI sleep (SCI compatibility mode)
86 uint16_t ADAPT:1; // 9 Automatic baudrate adjustment control(LIN mode)
87 uint16_t MBUFMODE:1; // 10 Multi-buffer mode
88 uint16_t CTYPE:1; // 11 Checksum type (LIN mode)
89 uint16_t HGENCTRL:1; // 12 Mask filtering comparison control (LIN mode)
90 uint16_t STOPEXTFRAME:1;// 13 Stop extended frame communication (LIN mode)
91 uint16_t rsvd2:2; // 15:14 Reserved
92 uint16_t LOOPBACK:1; // 16 Digital loopback mode
93 uint16_t CONT:1; // 17 Continue on suspend
94 uint16_t rsvd3:6; // 23:18 reserved
95 uint16_t RXENA:1; // 24 SCI mode receiver enable
96 uint16_t TXENA:1; // 25 SCI mode transmitter enable
97 uint16_t rsvd4:6; // 31:26 reserved
98 };
99
100 /* Allow access to the bit fields or entire register */
101 union SCIGCR1_REG {
102 uint32_t all;
103 struct SCIGCR1_BITS bit;
104 };
105
106 /* Global Control Register 2 (SCIGCR2) bit definitions */
107 struct SCIGCR2_BITS { // bit description
108 uint16_t POWERDOWN:1; // 0 Low-power mode PowerDown bit
109 uint16_t rsvd1:7; // 7:1 reserved
110 uint16_t GENWU:1; // 8 Generate Wakeup
111 uint16_t rsvd2:7; // 15:9 reserved
112 uint16_t SC:1; // 16 Send Checksum (LIN mode)
113 uint16_t CC:1; // 17 Compare Checksum (LIN mode)
114 uint16_t rsvd3:14; // 31:18 reserved
115 };
116
117 /* Allow access to the bit fields or entire register */
118 union SCIGCR2_REG {
119 uint32_t all;
120 struct SCIGCR2_BITS bit;
121 };
122
123 /* SCI Set Interrupt Register (SCISETINT) bit definitions */
124 struct SCISETINT_BITS { // bit description
125 uint16_t SETBRKDTINT:1; // 0 Set Break-detect Interrupt (SCI compatible mode)
126 uint16_t SETWAKEUPINT:1; // 1 Set Wake-up Interrupt
127 uint16_t rsvd1:2; // 3:2 reserved
128 uint16_t SETTIMEOUTINT:1; // 4 Set Timeout Interrupt (LIN only)
129 uint16_t rsvd2:1; // 5 reserved
130 uint16_t SETTOAWUSINT:1; // 6 Set Timeout After Wakeup Signal Interrupt (LIN only)
131 uint16_t SETTOA3WUSINT:1; // 7 Set Timeout After 3 Wakeup Signals Interrupt (LIN only)
132 uint16_t SETTXINT:1; // 8 Set Transmitter Interrupt
133 uint16_t SETRXINT:1; // 9 Receiver Interrupt Enable
134 uint16_t rsvd3:3; // 12:10 reserved
135 uint16_t SETIDINT:1; // 13 Set Identifier Interrupt (LIN only)
136 uint16_t rsvd4:2; // 15:14 reserved
137 uint16_t rsvd5:2; // 17:16 reserved
138 uint16_t rsvd6:1; // 18 reserved
139 uint16_t rsvd7:5; // 23:19 reserved
140 uint16_t SETPEINT:1; // 24 Set Parity Interrupt
141 uint16_t SETOEINT:1; // 25 Set Overrun-Error Interrupt
142 uint16_t SETFEINT:1; // 26 Set Framing-Error Interrupt
143 uint16_t SETNREINT:1; // 27 Set No-Response-Error Interrupt (LIN only)
144 uint16_t SETISFEINT:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt (LIN only)
145 uint16_t SETCEINT:1; // 29 Set Checksum-error Interrupt (LIN only)
146 uint16_t SETPBEINT:1; // 30 Set Physical Bus Error Interrupt (LIN only)
147 uint16_t SETBEINT:1; // 31 Set Bit Error Interrupt (LIN only)
148 };
149
150 /* Allow access to the bit fields or entire register */
151 union SCISETINT_REG {
152 uint32_t all;
153 struct SCISETINT_BITS bit;
154 };
155
156 /* SCI Clear Interrupt (SCICLEARINT) Register bit definitions */
157 struct SCICLEARINT_BITS { // bit description
158 uint16_t CLRBRKDTINT:1; // 0 Clear Break-detect Interrupt (SCI compatible mode)
159 uint16_t CLRWAKEUPINT:1; // 1 Clear Wake-up Interrupt
160 uint16_t rsvd1:2; // 3:2 reserved
161 uint16_t CLRTIMEOUTINT:1; // 4 Clear Timeout Interrupt (LIN only)
162 uint16_t rsvd2:1; // 5 reserved
163 uint16_t CLRTOAWUSINT:1; // 6 Clear Timeout After Wakeup Signal Interrupt (LIN only)
164 uint16_t CLRTOA3WUSINT:1; // 7 Clear Timeout After 3 Wakeup Signals Interrupt (LIN only)
165 uint16_t CLRTXINT:1; // 8 Clear Transmitter Interrupt
166 uint16_t CLRRXINT:1; // 9 Clear Receiver Interrupt
167 uint16_t rsvd3:3; // 12:10 reserved
168 uint16_t CLRIDINT:1; // 13 Clear Identifier Interrupt (LIN only)
169 uint16_t rsvd4:2; // 15:14 reserved
170 uint16_t rsvd5:2; // 17:16 reserved
171 uint16_t rsvd6:1; // 18 reserved
172 uint16_t rsvd7:5; // 23:19 reserved
173 uint16_t CLRPEINT:1; // 24 Clear Parity Interrupt
174 uint16_t CLROEINT:1; // 25 Clear Overrun-Error Interrupt
175 uint16_t CLRFEINT:1; // 26 Clear Framing-Error Interrupt
176 uint16_t CLRNREINT:1; // 27 Clear No-Response-Error Interrupt (LIN only)
177 uint16_t CLRISFEINT:1; // 28 Clear Inconsistent-Synch-Field-Error Interrupt (LIN only)
178 uint16_t CLRCEINT:1; // 29 Clear Checksum-error Interrupt (LIN only)
179 uint16_t CLRPBEINT:1; // 30 Clear Physical Bus Error Interrupt (LIN only)
180 uint16_t CLRBEINT:1; // 31 Clear Bit Error Interrupt (LIN only)
181 };
182
183 /* Allow access to the bit fields or entire register */
184 union SCICLEARINT_REG {
185 uint32_t all;
186 struct SCICLEARINT_BITS bit;
187 };
188
189 /* SCI Set Interrupt Level Register (SCISETINTLVL) bit definitions */
190 struct SCISETINTLVL_BITS { // bit description
191 uint16_t SETBRKDTINTLVL:1; // 0 Set Break-detect Interrupt Level (SCI compatible mode)
192 uint16_t SETWAKEUPINTLVL:1; // 1 Set Wake-up Interrupt Level
193 uint16_t rsvd1:2; // 3:2 reserved
194 uint16_t SETTIMEOUTINTLVL:1; // 4 Set Timeout Interrupt Level (LIN only)
195 uint16_t rsvd2:1; // 5 reserved
196 uint16_t SETTOAWUSINTLVL:1; // 6 Set Timeout After Wakeup Signal Interrupt Level (LIN only)
197 uint16_t SETTOA3WUSINTLVL:1; // 7 Set Timeout After 3 Wakeup Signals Interrupt Level (LIN only)
198 uint16_t SETTXINTLVL:1; // 8 Set Transmitter Interrupt Level
199 uint16_t SETRXINTOVO:1; // 9 Receiver Interrupt Enable Level
200 uint16_t rsvd3:3; // 12:10 reserved
201 uint16_t SETIDINTLVL:1; // 13 Set Identifier Interrupt Level (LIN only)
202 uint16_t rsvd4:2; // 15:14 reserved
203 uint16_t rsvd5:2; // 17:16 reserved
204 uint16_t rsvd6:1; // 18 reserved
205 uint16_t rsvd7:5; // 23:19 reserved
206 uint16_t SETPEINTLVL:1; // 24 Set Parity Interrupt Level
207 uint16_t SETOEINTLVL:1; // 25 Set Overrun-Error Interrupt Level
208 uint16_t SETFEINTLVL:1; // 26 Set Framing-Error Interrupt Level
209 uint16_t SETNREINTLVL:1; // 27 Set No-Response-Error Interrupt Level (LIN only)
210 uint16_t SETISFEINTLVL:1; // 28 Set Inconsistent-Synch-Field-Error Interrupt Level (LIN only)
211 uint16_t SETCEINTLVL:1; // 29 Set Checksum-error Interrupt Level (LIN only)
212 uint16_t SETPBEINTLVL:1; // 30 Set Physical Bus Error Interrupt Level (LIN only)
213 uint16_t SETBEINTLVL:1; // 31 Set Bit Error Interrupt Level(LIN only)
214 };
215
216 /* Allow access to the bit fields or entire register */
217 union SCISETINTLVL_REG {
218 uint32_t all;
219 struct SCISETINTLVL_BITS bit;
220 };
221
222 /* SCI Clear Interrupt Level (SCICLEARINTLVL) Register bit definitions */
223 struct SCICLEARINTLVL_BITS { // bit description
224 uint16_t CLRBRKDTINTLVL:1; // 0 Clear Break-detect Interrupt Level (SCI compatible mode)
225 uint16_t CLRWAKEUPINTLVL:1; // 1 Clear Wake-up Interrupt Level
226 uint16_t rsvd1:2; // 3:2 reserved
227 uint16_t CLRTIMEOUTINTLVL:1; // 4 Clear Timeout Interrupt Level (LIN only)
228 uint16_t rsvd2:1; // 5 reserved
229 uint16_t CLRTOAWUSINTLVL:1; // 6 Clear Timeout After Wakeup Signal Interrupt Level (LIN only)
230 uint16_t CLRTOA3WUSINTLVL:1; // 7 Clear Timeout After 3 Wakeup Signals Interrupt Level (LIN only)
231 uint16_t CLRTXINTLVL:1; // 8 Clear Transmitter Interrupt Level
232 uint16_t CLRRXINTLVL:1; // 9 Clear Receiver Interrupt Level
233 uint16_t rsvd3:3; // 12:10 reserved
234 uint16_t CLRIDINTLVL:1; // 13 Clear Identifier Interrupt Level (LIN only)
235 uint16_t rsvd4:2; // 15:14 reserved
236 uint16_t rsvd5:2; // 17:16 reserved
237 uint16_t rsvd6:1; // 18 reserved
238 uint16_t rsvd7:5; // 23:19 reserved
239 uint16_t CLRPEINTLVL:1; // 24 Clear Parity Interrupt Level
240 uint16_t CLROEINTLVL:1; // 25 Clear Overrun-Error Interrupt Level
241 uint16_t CLRFEINTLVL:1; // 26 Clear Framing-Error Interrupt Level
242 uint16_t CLRNREINTLVL:1; // 27 Clear No-Response-Error Interrupt Level (LIN only)
243 uint16_t CLRISFEINTLVL:1; // 28 Clear Inconsistent-Synch-Field-Error Interrupt Level (LIN only)
244 uint16_t CLRCEINTLVL:1; // 29 Clear Checksum-error Interrupt Level (LIN only)
245 uint16_t CLRPBEINTLVL:1; // 30 Clear Physical Bus Error Interrupt Level (LIN only)
246 uint16_t CLRBEINTLVL:1; // 31 Clear Bit Error Interrupt Level (LIN only)
247 };
248
249 /* Allow access to the bit fields or entire register */
250 union SCICLEARINTLVL_REG {
251 uint32_t all;
252 struct SCICLEARINTLVL_BITS bit;
253 };
254
255 /* SCI Flags Register (SCIFLR) bit definitions */
256 struct SCIFLR_BITS { // bit description
257 uint16_t BRKDT:1; // 0 Break-detect Flag (SCI compatible mode)
258 uint16_t WAKEUP:1; // 1 Wake-up Flag
259 uint16_t IDLE:1; // 2 SCI receiver in idle state (SCI compatible mode)
260 uint16_t BUSY:1; // 3 Busy Flag
261 uint16_t TIMEOUT:1; // 4 LIN Bus IDLE timeout Flag (LIN only)
262 uint16_t rsvd2:1; // 5 reserved
263 uint16_t TOAWUS:1; // 6 Timeout After Wakeup Signal Flag (LIN only)
264 uint16_t TOA3WUS:1; // 7 Timeout After 3 Wakeup Signals Flag (LIN only)
265 uint16_t TXRDY:1; // 8 Transmitter Buffer Ready Flag
266 uint16_t RXRDY:1; // 9 Receiver Buffer Ready Flag
267 uint16_t TXWAKE:1; // 10 SCI Transmitter Wakeup Method Select
268 uint16_t TXEMPTY:1; // 11 Transmitter Empty Clag
269 uint16_t RXWAKE:1; // 12 Receiver Wakeup Detect Flag
270 uint16_t IDTXFLAG:1; // 13 Identifier On Transmit Flag (LIN only)
271 uint16_t IDRXFLAG:1; // 14 Identifier on Receive Flag
272 uint16_t rsvd3:1; // 15
273 uint16_t rsvd4:8; // 23:16 reserved
274 uint16_t PE:1; // 24 Parity Error Flag
275 uint16_t OE:1; // 25 Overrun Error Flag
276 uint16_t FE:1; // 26 Framing Error Flag
277 uint16_t NRE:1; // 27 No-Response Error Flag (LIN only)
278 uint16_t ISFE:1; // 28 Inconsistent Synch Field Error Flag (LIN only)
279 uint16_t CE:1; // 29 Checksum Error Flag (LIN only)
280 uint16_t PBE:1; // 30 Physical Bus Error Flag (LIN only)
281 uint16_t BE:1; // 31 Bit Error Flag (LIN only)
282 };
283
284 /* Allow access to the bit fields or entire register */
285 union SCIFLR_REG {
286 uint32_t all;
287 struct SCIFLR_BITS bit;
288 };
289
290 /* SCI Interrupt Vector Offset 0 (SCIINTVECT0) bit definitions */
291 struct SCIINTVECT0_BITS { // bit description
292 uint16_t INTVECT0:5; // 4:0 Interrupt vector offset for INT0
293 uint16_t rsvd1:11; // 15:5 reserved
294 uint16_t rsvd2:16; // 31:16 reserved
295 };
296
297 /* Allow access to the bit fields or entire register */
298 union SCIINTVECT0_REG {
299 uint32_t all;
300 struct SCIINTVECT0_BITS bit;
301 };
302
303 /* SCI Interrupt Vector Offset 1 (SCIINTVECT1) bit definitions */
304 struct SCIINTVECT1_BITS { // bit description
305 uint16_t INTVECT1:5; // 4:0 Interrupt vector offset for INT1
306 uint16_t rsvd1:11; // 15:5 reserved
307 uint16_t rsvd2:16; // 31:16 reserved
308 };
309
310 /* Allow access to the bit fields or entire register */
311 union SCIINTVECT1_REG {
312 uint32_t all;
313 struct SCIINTVECT1_BITS bit;
314 };
315
316 /* SCI Format Control Register (SCIFORMAT) bit definitions */
317 struct SCIFORMAT_BITS { // bit description
318 uint16_t CHAR:3; // 2:0 Character Length Control Bits
319 uint16_t rsvd1:13; // 15:3 reserved
320 uint16_t LENGTH:3; // 18:16 Frame Length Control Bits
321 uint16_t rsvd2:13; // 31:19 reserved
322 };
323
324 /* Allow access to the bit fields or entire register */
325 union SCIFORMAT_REG {
326 uint32_t all;
327 struct SCIFORMAT_BITS bit;
328 };
329
330 /* Baud Rate Selection Register (BRSR) bit definitions */
331 struct BRSR_BITS { // bit description
332 uint16_t SCI_LIN_PSL :16; // 15:0 SCI/LIN Prescaler Low
333 uint16_t SCI_LIN_PSH :8; // 23:16 SCI/LIN Prescaler High
334 uint16_t M:4; // 27:24 SCI/LIN Fractional Divider Selection
335 uint16_t rsvd1:4; // 31:28 reserved
336 };
337
338 /* Allow access to the bit fields or entire register */
339 union BRSR_REG {
340 uint32_t all;
341 struct BRSR_BITS bit;
342 };
343
344 /* SCI Pin I/O Control Register 2 (SCIPIO2) bit definitions */
345 struct SCIPIO2_BITS { // bit description
346 uint16_t rsvd1:1; // 0 reserved
347 uint16_t RXIN:1; // 1 SCIRX pin value
348 uint16_t TXIN:1; // 2 SCITX pin value
349 uint16_t rsvd2:13; // 15:3 reserved
350 uint16_t rsvd3:16; // 31:16 reserved
351 };
352
353 /* Allow access to the bit fields or entire register */
354 union SCIPIO2_REG {
355 uint32_t all;
356 struct SCIPIO2_BITS bit;
357 };
358
359
360 /* LIN Compare Register (LINCOMP) bit definitions */
361 struct LINCOMP_BITS { // bit description
362 uint16_t SBREAK:3; // 2:0 Synch Break Extend
363 uint16_t rsvd1:5; // 7:3 reserved
364 uint16_t SDEL:2; // 9:8 Sync Delimiter Compare
365 uint16_t rsvd2:6; // 15:10 reserved
366 uint16_t rsvd3:16; // 31:16 reserved
367 };
368
369 /* Allow access to the bit fields or entire register */
370 union LINCOMP_REG {
371 uint32_t all;
372 struct LINCOMP_BITS bit;
373 };
374
375
376 /* LIN Receive Data 0 Register (LINRD0) bit definitions */
377 struct LINRD0_BITS { // bit description
378 uint16_t RD3:8; // 7:0 Receive Buffer 3
379 uint16_t RD2:8; // 15:8 Receive Buffer 2
380 uint16_t RD1:8; // 23:16 Receive Buffer 1
381 uint16_t RD0:8; // 31:24 Receive Buffer 0
382 };
383
384 /* Allow access to the bit fields or entire register */
385 union LINRD0_REG {
386 uint32_t all;
387 struct LINRD0_BITS bit;
388 };
389
390 /* LIN Receive Data 1 Register (LINRD1) bit definitions */
391 struct LINRD1_BITS { // bit description
392 uint16_t RD7:8; // 7:0 Receive Buffer 7
393 uint16_t RD6:8; // 15:8 Receive Buffer 6
394 uint16_t RD5:8; // 23:16 Receive Buffer 5
395 uint16_t RD4:8; // 31:24 Receive Buffer 4
396 };
397
398 /* Allow access to the bit fields or entire register */
399 union LINRD1_REG {
400 uint32_t all;
401 struct LINRD1_BITS bit;
402 };
403
404 /* LIN Acceptance Mask Register (LINMASK) bit definitions */
405 struct LINMASK_BITS { // bit description
406 uint16_t TXIDMASK:8; // 7:0 TX ID Mask bits (LIN only)
407 uint16_t rsvd1:8; // 15:8 reserved
408 uint16_t RXIDMASK:8; // 23:16 RX ID Mask bits (LIN only)
409 uint16_t rsvd2:8; // 31:24 reserved
410 };
411
412 /* Allow access to the bit fields or entire register */
413 union LINMASK_REG {
414 uint32_t all;
415 struct LINMASK_BITS bit;
416 };
417
418 /* LIN ID Register (LINID) bit definitions */
419 struct LINID_BITS { // bit description
420 uint16_t IDBYTE:8; // 7:0 LIN message ID (LIN only)
421 uint16_t IDSLAVETASKBYTE:8; // 15:8 Received ID comparison ID (LIN only)
422 uint16_t RECEIVEDID:8; // 23:16 Current Message ID (LIN only)
423 uint16_t rsvd1:8; // 31:24 reserved
424 };
425
426 /* Allow access to the bit fields or entire register */
427 union LINID_REG {
428 uint32_t all;
429 struct LINID_BITS bit;
430 };
431
432 /* LIN Transmit Data 0 Register (LINTD0) bit definitions */
433 struct LINTD0_BITS { // bit description
434 uint16_t TD3:8; // 7:0 Transmit Buffer 3
435 uint16_t TD2:8; // 15:8 Transmit Buffer 2
436 uint16_t TD1:8; // 23:16 Transmit Buffer 1
437 uint16_t TD0:8; // 31:24 Transmit Buffer 0
438 };
439
440 /* Allow access to the bit fields or entire register */
441 union LINTD0_REG {
442 uint32_t all;
443 struct LINTD0_BITS bit;
444 };
445
446 /* LIN Transmit Data 1 Register (LINTD1) bit definitions */
447 struct LINTD1_BITS { // bit description
448 uint16_t TD7:8; // 7:0 Transmit Buffer 7
449 uint16_t TD6:8; // 15:8 Transmit Buffer 6
450 uint16_t TD5:8; // 23:16 Transmit Buffer 5
451 uint16_t TD4:8; // 31:24 Transmit Buffer 4
452 };
453
454 /* Allow access to the bit fields or entire register */
455 union LINTD1_REG {
456 uint32_t all;
457 struct LINTD1_BITS bit;
458 };
459
460 /* IODFT for LIN (IODFTCTRL) bit definitions */
461 struct IODFTCTRL_BITS { // bit description
462 uint16_t RXPENA:1; // 0 Analog Loopback Via Receive Pin Enable
463 uint16_t LPBENA:1; // 1 Module Loopback Enable
464 uint16_t rsvd1:6; // 7:2 reserved
465 uint16_t IODFTENA:4; // 11:8 IO DFT Enable Key
466 uint16_t rsvd2:4; // 15:12 Reserved
467 uint16_t TXSHIFT:3; // 18:16 Transmit Delay Shift
468 uint16_t PINSAMPLEMASK:2; // 20:19 TX Pin Sample Mask
469 uint16_t rsvd3:3; // 23:21 Reserved
470 uint16_t BRKDTERRENA:1; // 24 Break Detect Error Enable (SCI compatibility mode)
471 uint16_t PERRENA:1; // 25 Parity Error Enable (SCI compatibility mode)
472 uint16_t FERRENA:1; // 26 Frame Error Enable (SCI compatibility mode)
473 uint16_t rsvd:1; // 27 reserved
474 uint16_t ISFERRENA:1; // 28 Inconsistent Synch Field Error Enable (LIN mode)
475 uint16_t CERRENA:1; // 29 Checksum Error Enable(LIN mode)
476 uint16_t PBERRENA:1; // 30 Physical Bus Error Enable (LIN mode)
477 uint16_t BERRENA:1; // 31 Bit Error Enable (LIN mode)
478 };
479
480 /* Allow access to the bit fields or entire register */
481 union IODFTCTRL_REG {
482 uint32_t all;
483 struct IODFTCTRL_BITS bit;
484 };
485
486
487 /**************************************/
488 /* LIN register file */
489 /**************************************/
490
491 struct LIN_REGS {
492 union SCIGCR0_REG SCIGCR0; // Global Control Register 0
493 union SCIGCR1_REG SCIGCR1; // Global Control Register 1
494 union SCIGCR2_REG SCIGCR2; // Global Control Register 2
495 union SCISETINT_REG SCISETINT; // Interrupt Enable Register
496 union SCICLEARINT_REG SCICLEARINT; // Interrupt Disable Register
497 union SCISETINTLVL_REG SCISETINTLVL; // Set Interrupt Level Register
498 union SCICLEARINTLVL_REG SCICLEARINTLVL; // Clear Interrupt Level Register
499 union SCIFLR_REG SCIFLR; // Flag Register
500 union SCIINTVECT0_REG SCIINTVECT0; // Interrupt Vector Offset Register 0
501 union SCIINTVECT1_REG SCIINTVECT1; // Interrupt Vector Offset Register 1
502 union SCIFORMAT_REG SCIFORMAT; // Length Control Register
503 union BRSR_REG BRSR; // Baud Rate Selection Register
504 uint32_t SCIED; // Emulation buffer Register
505 uint32_t SCIRD; // Receiver data buffer Register
506 uint32_t SCITD; // Transmit data buffer Register
507 uint32_t rsvd1[2]; // reserved
508 union SCIPIO2_REG SCIPIO2; // Pin control Register 2
509 uint32_t rsvd2[6]; // reserved
510 union LINCOMP_REG LINCOMP; // Compare register
511 union LINRD0_REG LINRD0; // Receive data register 0
512 union LINRD1_REG LINRD1; // Receive data register 1
513 union LINMASK_REG LINMASK; // Acceptance mask register
514 union LINID_REG LINID; // LIN ID Register
515 union LINTD0_REG LINTD0; // Transmit Data Register 0
516 union LINTD1_REG LINTD1; // Transmit Data Register 1
517 uint32_t MBRSR; // Baud Rate Selection Register
518 uint32_t rsvd3[4]; // reserved
519 union IODFTCTRL_REG IODFTCTRL; // IODFT for LIN
520 };
521
522 //---------------------------------------------------------------------------
523 // LIN External References & Function Declarations:
524 //
525 extern volatile struct LIN_REGS LinaRegs;
526
527 #ifdef __cplusplus
528 }
529 #endif /* extern "C" */
530
531 #endif // end of _LIN_H_ definition
532
LIN_REGS::SCICLEARINT
union SCICLEARINT_REG SCICLEARINT
Definition: lin.h:496
SCICLEARINT_BITS::CLRNREINT
uint16_t CLRNREINT
Definition: lin.h:176
SCIFLR_BITS::BE
uint16_t BE
Definition: lin.h:281
LINCOMP_BITS::SBREAK
uint16_t SBREAK
Definition: lin.h:362
SCISETINTLVL_BITS::SETTIMEOUTINTLVL
uint16_t SETTIMEOUTINTLVL
Definition: lin.h:194
LINRD1_REG::bit
struct LINRD1_BITS bit
Definition: lin.h:401
LINTD1_REG
Definition: lin.h:455
SCIGCR1_BITS::HGENCTRL
uint16_t HGENCTRL
Definition: lin.h:89
SCIINTVECT0_REG
Definition: lin.h:298
SCICLEARINT_BITS::CLRBRKDTINT
uint16_t CLRBRKDTINT
Definition: lin.h:158
SCISETINTLVL_BITS::rsvd5
uint16_t rsvd5
Definition: lin.h:203
SCIPIO2_REG
Definition: lin.h:354
LINRD0_REG::bit
struct LINRD0_BITS bit
Definition: lin.h:387
SCISETINT_REG
Definition: lin.h:151
SCIGCR1_BITS::rsvd4
uint16_t rsvd4
Definition: lin.h:97
LINCOMP_BITS
Definition: lin.h:361
IODFTCTRL_BITS::IODFTENA
uint16_t IODFTENA
Definition: lin.h:465
SCIGCR0_BITS::RESET
uint16_t RESET
Definition: lin.h:64
LINTD0_REG
Definition: lin.h:441
SCIPIO2_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:350
SCIFLR_BITS::OE
uint16_t OE
Definition: lin.h:275
SCISETINTLVL_REG::all
uint32_t all
Definition: lin.h:218
IODFTCTRL_BITS::TXSHIFT
uint16_t TXSHIFT
Definition: lin.h:467
IODFTCTRL_REG::all
uint32_t all
Definition: lin.h:482
SCICLEARINT_REG
Definition: lin.h:184
SCICLEARINT_BITS::rsvd5
uint16_t rsvd5
Definition: lin.h:170
SCISETINT_BITS::SETIDINT
uint16_t SETIDINT
Definition: lin.h:135
LINTD0_REG::bit
struct LINTD0_BITS bit
Definition: lin.h:443
SCISETINT_BITS::SETFEINT
uint16_t SETFEINT
Definition: lin.h:142
SCICLEARINTLVL_BITS::CLRIDINTLVL
uint16_t CLRIDINTLVL
Definition: lin.h:234
LINCOMP_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:363
SCIGCR1_BITS::LINMODE
uint16_t LINMODE
Definition: lin.h:83
SCICLEARINTLVL_BITS::rsvd5
uint16_t rsvd5
Definition: lin.h:236
SCIGCR1_BITS::RXENA
uint16_t RXENA
Definition: lin.h:95
LINID_BITS::IDSLAVETASKBYTE
uint16_t IDSLAVETASKBYTE
Definition: lin.h:421
SCISETINT_BITS::SETTOAWUSINT
uint16_t SETTOAWUSINT
Definition: lin.h:130
SCIFLR_BITS::RXWAKE
uint16_t RXWAKE
Definition: lin.h:269
SCIGCR2_BITS::SC
uint16_t SC
Definition: lin.h:112
SCICLEARINT_BITS::CLRBEINT
uint16_t CLRBEINT
Definition: lin.h:180
SCIGCR2_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:111
SCIGCR0_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:65
SCICLEARINTLVL_BITS::CLRCEINTLVL
uint16_t CLRCEINTLVL
Definition: lin.h:244
LIN_REGS::SCIGCR0
union SCIGCR0_REG SCIGCR0
Definition: lin.h:492
SCIFLR_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:272
LINRD0_BITS
Definition: lin.h:377
SCIFLR_BITS::PBE
uint16_t PBE
Definition: lin.h:280
SCIFORMAT_BITS::CHAR
uint16_t CHAR
Definition: lin.h:318
SCIINTVECT0_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:293
LINTD0_BITS
Definition: lin.h:433
LIN_REGS::BRSR
union BRSR_REG BRSR
Definition: lin.h:503
SCIGCR1_BITS::TXENA
uint16_t TXENA
Definition: lin.h:96
SCIFLR_BITS::TXRDY
uint16_t TXRDY
Definition: lin.h:265
IODFTCTRL_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:464
IODFTCTRL_BITS::BERRENA
uint16_t BERRENA
Definition: lin.h:477
SCISETINTLVL_BITS::SETNREINTLVL
uint16_t SETNREINTLVL
Definition: lin.h:209
SCICLEARINT_BITS::CLRTXINT
uint16_t CLRTXINT
Definition: lin.h:165
LINRD0_BITS::RD1
uint16_t RD1
Definition: lin.h:380
LINRD1_BITS::RD6
uint16_t RD6
Definition: lin.h:393
SCIFLR_BITS::TIMEOUT
uint16_t TIMEOUT
Definition: lin.h:261
BRSR_BITS::M
uint16_t M
Definition: lin.h:334
SCIINTVECT1_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:307
SCIFORMAT_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:321
LIN_REGS::SCIINTVECT1
union SCIINTVECT1_REG SCIINTVECT1
Definition: lin.h:501
SCIGCR0_REG
Definition: lin.h:70
LINRD1_BITS::RD5
uint16_t RD5
Definition: lin.h:394
SCISETINT_BITS::SETTIMEOUTINT
uint16_t SETTIMEOUTINT
Definition: lin.h:128
IODFTCTRL_BITS::FERRENA
uint16_t FERRENA
Definition: lin.h:472
LINMASK_BITS
Definition: lin.h:405
BRSR_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:335
SCIFLR_BITS::IDRXFLAG
uint16_t IDRXFLAG
Definition: lin.h:271
LINID_BITS
Definition: lin.h:419
SCIGCR1_REG
Definition: lin.h:101
SCIINTVECT1_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:306
LINID_BITS::IDBYTE
uint16_t IDBYTE
Definition: lin.h:420
SCISETINTLVL_BITS::rsvd6
uint16_t rsvd6
Definition: lin.h:204
SCIINTVECT0_REG::bit
struct SCIINTVECT0_BITS bit
Definition: lin.h:300
SCIFLR_REG::bit
struct SCIFLR_BITS bit
Definition: lin.h:287
SCIINTVECT0_BITS::INTVECT0
uint16_t INTVECT0
Definition: lin.h:292
SCIINTVECT1_BITS
Definition: lin.h:304
SCICLEARINTLVL_REG::all
uint32_t all
Definition: lin.h:251
SCIINTVECT0_REG::all
uint32_t all
Definition: lin.h:299
SCICLEARINTLVL_BITS::CLRRXINTLVL
uint16_t CLRRXINTLVL
Definition: lin.h:232
SCIGCR2_REG::all
uint32_t all
Definition: lin.h:119
SCIFLR_BITS::BUSY
uint16_t BUSY
Definition: lin.h:260
SCIFLR_BITS::RXRDY
uint16_t RXRDY
Definition: lin.h:266
SCIFLR_BITS::BRKDT
uint16_t BRKDT
Definition: lin.h:257
SCICLEARINT_BITS::CLRISFEINT
uint16_t CLRISFEINT
Definition: lin.h:177
BRSR_REG
Definition: lin.h:339
SCISETINT_BITS::SETWAKEUPINT
uint16_t SETWAKEUPINT
Definition: lin.h:126
SCIFLR_BITS::CE
uint16_t CE
Definition: lin.h:279
SCIFORMAT_REG
Definition: lin.h:325
SCIFORMAT_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:319
SCICLEARINT_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:160
IODFTCTRL_REG::bit
struct IODFTCTRL_BITS bit
Definition: lin.h:483
LINTD1_BITS::TD6
uint16_t TD6
Definition: lin.h:449
LIN_REGS::LINMASK
union LINMASK_REG LINMASK
Definition: lin.h:513
SCIFLR_REG
Definition: lin.h:285
LIN_REGS::SCIED
uint32_t SCIED
Definition: lin.h:504
LINRD0_BITS::RD3
uint16_t RD3
Definition: lin.h:378
LIN_REGS::MBRSR
uint32_t MBRSR
Definition: lin.h:517
SCISETINT_BITS::SETCEINT
uint16_t SETCEINT
Definition: lin.h:145
SCIGCR2_BITS::GENWU
uint16_t GENWU
Definition: lin.h:110
SCIFLR_REG::all
uint32_t all
Definition: lin.h:286
IODFTCTRL_BITS::RXPENA
uint16_t RXPENA
Definition: lin.h:462
SCISETINT_BITS::rsvd5
uint16_t rsvd5
Definition: lin.h:137
SCIFLR_BITS::NRE
uint16_t NRE
Definition: lin.h:277
SCIGCR0_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:66
SCICLEARINT_BITS::CLRPBEINT
uint16_t CLRPBEINT
Definition: lin.h:179
SCISETINTLVL_BITS::SETCEINTLVL
uint16_t SETCEINTLVL
Definition: lin.h:211
LINTD1_BITS::TD7
uint16_t TD7
Definition: lin.h:448
SCIGCR1_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:91
BRSR_BITS
Definition: lin.h:331
LINRD0_REG::all
uint32_t all
Definition: lin.h:386
SCIPIO2_BITS::TXIN
uint16_t TXIN
Definition: lin.h:348
SCICLEARINT_REG::all
uint32_t all
Definition: lin.h:185
SCIFLR_BITS::WAKEUP
uint16_t WAKEUP
Definition: lin.h:258
SCIGCR2_REG
Definition: lin.h:118
LINCOMP_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:365
LINID_REG
Definition: lin.h:427
LIN_REGS::SCITD
uint32_t SCITD
Definition: lin.h:506
SCIGCR1_BITS::SLEEP
uint16_t SLEEP
Definition: lin.h:85
SCICLEARINTLVL_BITS::CLRISFEINTLVL
uint16_t CLRISFEINTLVL
Definition: lin.h:243
SCICLEARINTLVL_REG
Definition: lin.h:250
BRSR_BITS::SCI_LIN_PSL
uint16_t SCI_LIN_PSL
Definition: lin.h:332
SCISETINTLVL_BITS::rsvd7
uint16_t rsvd7
Definition: lin.h:205
SCIPIO2_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:349
SCISETINTLVL_BITS::SETBRKDTINTLVL
uint16_t SETBRKDTINTLVL
Definition: lin.h:191
LINMASK_BITS::RXIDMASK
uint16_t RXIDMASK
Definition: lin.h:408
SCIFLR_BITS::TOA3WUS
uint16_t TOA3WUS
Definition: lin.h:264
SCISETINTLVL_REG::bit
struct SCISETINTLVL_BITS bit
Definition: lin.h:219
SCIGCR1_BITS::CONT
uint16_t CONT
Definition: lin.h:93
SCIGCR2_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:114
IODFTCTRL_BITS::LPBENA
uint16_t LPBENA
Definition: lin.h:463
SCICLEARINTLVL_BITS::rsvd7
uint16_t rsvd7
Definition: lin.h:238
SCICLEARINT_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:167
SCISETINT_BITS::SETBEINT
uint16_t SETBEINT
Definition: lin.h:147
LINMASK_REG
Definition: lin.h:413
SCICLEARINT_BITS::CLRCEINT
uint16_t CLRCEINT
Definition: lin.h:178
SCIFLR_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:262
LINRD1_BITS
Definition: lin.h:391
LINTD1_BITS
Definition: lin.h:447
SCICLEARINT_BITS::CLRIDINT
uint16_t CLRIDINT
Definition: lin.h:168
SCISETINT_BITS::rsvd7
uint16_t rsvd7
Definition: lin.h:139
LIN_REGS::SCIFORMAT
union SCIFORMAT_REG SCIFORMAT
Definition: lin.h:502
SCICLEARINTLVL_BITS::CLRTIMEOUTINTLVL
uint16_t CLRTIMEOUTINTLVL
Definition: lin.h:227
SCISETINTLVL_BITS
Definition: lin.h:190
LinaRegs
volatile struct LIN_REGS LinaRegs
LINID_BITS::RECEIVEDID
uint16_t RECEIVEDID
Definition: lin.h:422
LIN_REGS::SCIGCR1
union SCIGCR1_REG SCIGCR1
Definition: lin.h:493
SCICLEARINT_BITS::CLROEINT
uint16_t CLROEINT
Definition: lin.h:174
SCICLEARINTLVL_BITS::rsvd6
uint16_t rsvd6
Definition: lin.h:237
SCIPIO2_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:346
SCIGCR0_REG::all
uint32_t all
Definition: lin.h:71
SCISETINT_BITS::rsvd4
uint16_t rsvd4
Definition: lin.h:136
LIN_REGS::LINRD1
union LINRD1_REG LINRD1
Definition: lin.h:512
SCICLEARINTLVL_BITS::CLRPEINTLVL
uint16_t CLRPEINTLVL
Definition: lin.h:239
LIN_REGS::rsvd3
uint32_t rsvd3[4]
Definition: lin.h:518
BRSR_BITS::SCI_LIN_PSH
uint16_t SCI_LIN_PSH
Definition: lin.h:333
LINTD1_BITS::TD5
uint16_t TD5
Definition: lin.h:450
SCICLEARINT_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:162
LINTD1_REG::bit
struct LINTD1_BITS bit
Definition: lin.h:457
LINRD1_REG::all
uint32_t all
Definition: lin.h:400
LINMASK_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:407
IODFTCTRL_BITS::rsvd
uint16_t rsvd
Definition: lin.h:473
LINMASK_BITS::TXIDMASK
uint16_t TXIDMASK
Definition: lin.h:406
SCIGCR1_BITS::PARITY
uint16_t PARITY
Definition: lin.h:80
LIN_REGS::rsvd2
uint32_t rsvd2[6]
Definition: lin.h:509
LINCOMP_BITS::SDEL
uint16_t SDEL
Definition: lin.h:364
SCIGCR0_REG::bit
struct SCIGCR0_BITS bit
Definition: lin.h:72
SCICLEARINTLVL_BITS::CLRPBEINTLVL
uint16_t CLRPBEINTLVL
Definition: lin.h:245
SCICLEARINT_BITS::CLRWAKEUPINT
uint16_t CLRWAKEUPINT
Definition: lin.h:159
SCICLEARINTLVL_BITS::CLRNREINTLVL
uint16_t CLRNREINTLVL
Definition: lin.h:242
SCISETINTLVL_BITS::SETIDINTLVL
uint16_t SETIDINTLVL
Definition: lin.h:201
SCIFLR_BITS::IDLE
uint16_t IDLE
Definition: lin.h:259
SCISETINT_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:134
SCISETINTLVL_BITS::SETTOA3WUSINTLVL
uint16_t SETTOA3WUSINTLVL
Definition: lin.h:197
LINID_REG::all
uint32_t all
Definition: lin.h:428
LINMASK_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:409
SCIFORMAT_BITS::LENGTH
uint16_t LENGTH
Definition: lin.h:320
SCISETINTLVL_BITS::SETOEINTLVL
uint16_t SETOEINTLVL
Definition: lin.h:207
SCISETINT_BITS::SETOEINT
uint16_t SETOEINT
Definition: lin.h:141
SCIGCR1_BITS::TIMINGMODE
uint16_t TIMINGMODE
Definition: lin.h:78
SCICLEARINT_BITS::rsvd7
uint16_t rsvd7
Definition: lin.h:172
IODFTCTRL_BITS::CERRENA
uint16_t CERRENA
Definition: lin.h:475
LIN_REGS::SCIINTVECT0
union SCIINTVECT0_REG SCIINTVECT0
Definition: lin.h:500
SCICLEARINT_BITS::CLRFEINT
uint16_t CLRFEINT
Definition: lin.h:175
LIN_REGS::SCICLEARINTLVL
union SCICLEARINTLVL_REG SCICLEARINTLVL
Definition: lin.h:498
SCIGCR1_BITS::STOPEXTFRAME
uint16_t STOPEXTFRAME
Definition: lin.h:90
LIN_REGS::LINID
union LINID_REG LINID
Definition: lin.h:514
SCIFLR_BITS
Definition: lin.h:256
IODFTCTRL_BITS
Definition: lin.h:461
LIN_REGS::SCISETINTLVL
union SCISETINTLVL_REG SCISETINTLVL
Definition: lin.h:497
SCICLEARINTLVL_BITS::CLRBRKDTINTLVL
uint16_t CLRBRKDTINTLVL
Definition: lin.h:224
LIN_REGS::SCIRD
uint32_t SCIRD
Definition: lin.h:505
SCISETINT_BITS::SETNREINT
uint16_t SETNREINT
Definition: lin.h:143
SCIGCR1_BITS::CTYPE
uint16_t CTYPE
Definition: lin.h:88
SCICLEARINTLVL_BITS::CLRTOA3WUSINTLVL
uint16_t CLRTOA3WUSINTLVL
Definition: lin.h:230
SCIGCR2_BITS
Definition: lin.h:107
BRSR_REG::bit
struct BRSR_BITS bit
Definition: lin.h:341
SCICLEARINT_BITS::rsvd6
uint16_t rsvd6
Definition: lin.h:171
LIN_REGS
Definition: lin.h:491
SCIGCR1_BITS::COMMMODE
uint16_t COMMMODE
Definition: lin.h:77
SCISETINTLVL_BITS::SETPBEINTLVL
uint16_t SETPBEINTLVL
Definition: lin.h:212
SCIINTVECT1_BITS::INTVECT1
uint16_t INTVECT1
Definition: lin.h:305
SCISETINT_BITS::SETTOA3WUSINT
uint16_t SETTOA3WUSINT
Definition: lin.h:131
SCICLEARINTLVL_BITS::CLROEINTLVL
uint16_t CLROEINTLVL
Definition: lin.h:240
IODFTCTRL_BITS::PERRENA
uint16_t PERRENA
Definition: lin.h:471
IODFTCTRL_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:466
SCIGCR1_BITS::SWnRST
uint16_t SWnRST
Definition: lin.h:84
SCICLEARINTLVL_BITS::CLRFEINTLVL
uint16_t CLRFEINTLVL
Definition: lin.h:241
SCIINTVECT0_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:294
LINTD0_BITS::TD1
uint16_t TD1
Definition: lin.h:436
SCICLEARINTLVL_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:228
LINCOMP_REG
Definition: lin.h:370
LINCOMP_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:366
IODFTCTRL_BITS::BRKDTERRENA
uint16_t BRKDTERRENA
Definition: lin.h:470
SCIGCR1_BITS::CLK_MASTER
uint16_t CLK_MASTER
Definition: lin.h:82
SCISETINT_BITS::SETISFEINT
uint16_t SETISFEINT
Definition: lin.h:144
LIN_REGS::rsvd1
uint32_t rsvd1[2]
Definition: lin.h:507
SCICLEARINT_BITS::CLRTIMEOUTINT
uint16_t CLRTIMEOUTINT
Definition: lin.h:161
LINTD0_REG::all
uint32_t all
Definition: lin.h:442
SCIINTVECT1_REG
Definition: lin.h:311
LINTD0_BITS::TD2
uint16_t TD2
Definition: lin.h:435
SCIPIO2_REG::all
uint32_t all
Definition: lin.h:355
LIN_REGS::LINRD0
union LINRD0_REG LINRD0
Definition: lin.h:511
SCICLEARINTLVL_BITS::CLRTOAWUSINTLVL
uint16_t CLRTOAWUSINTLVL
Definition: lin.h:229
SCICLEARINTLVL_BITS
Definition: lin.h:223
SCIFORMAT_REG::all
uint32_t all
Definition: lin.h:326
SCIGCR0_BITS
Definition: lin.h:63
LIN_REGS::SCIFLR
union SCIFLR_REG SCIFLR
Definition: lin.h:499
LINRD0_BITS::RD0
uint16_t RD0
Definition: lin.h:381
BRSR_REG::all
uint32_t all
Definition: lin.h:340
SCIINTVECT1_REG::bit
struct SCIINTVECT1_BITS bit
Definition: lin.h:313
IODFTCTRL_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:469
LINMASK_REG::bit
struct LINMASK_BITS bit
Definition: lin.h:415
SCICLEARINT_BITS::CLRPEINT
uint16_t CLRPEINT
Definition: lin.h:173
LINTD1_BITS::TD4
uint16_t TD4
Definition: lin.h:451
SCICLEARINT_REG::bit
struct SCICLEARINT_BITS bit
Definition: lin.h:186
SCICLEARINTLVL_BITS::CLRBEINTLVL
uint16_t CLRBEINTLVL
Definition: lin.h:246
SCIPIO2_BITS
Definition: lin.h:345
SCIGCR1_REG::bit
struct SCIGCR1_BITS bit
Definition: lin.h:103
SCISETINT_BITS::SETRXINT
uint16_t SETRXINT
Definition: lin.h:133
SCISETINT_REG::bit
struct SCISETINT_BITS bit
Definition: lin.h:153
LIN_REGS::SCIPIO2
union SCIPIO2_REG SCIPIO2
Definition: lin.h:508
LIN_REGS::SCISETINT
union SCISETINT_REG SCISETINT
Definition: lin.h:495
SCICLEARINT_BITS::CLRRXINT
uint16_t CLRRXINT
Definition: lin.h:166
SCICLEARINTLVL_BITS::CLRTXINTLVL
uint16_t CLRTXINTLVL
Definition: lin.h:231
SCISETINT_BITS::SETPBEINT
uint16_t SETPBEINT
Definition: lin.h:146
SCISETINT_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:129
LINCOMP_REG::bit
struct LINCOMP_BITS bit
Definition: lin.h:372
SCIINTVECT0_BITS
Definition: lin.h:291
SCISETINTLVL_BITS::rsvd2
uint16_t rsvd2
Definition: lin.h:195
SCICLEARINT_BITS::CLRTOAWUSINT
uint16_t CLRTOAWUSINT
Definition: lin.h:163
LINRD0_BITS::RD2
uint16_t RD2
Definition: lin.h:379
SCISETINTLVL_BITS::SETPEINTLVL
uint16_t SETPEINTLVL
Definition: lin.h:206
SCIFLR_BITS::TOAWUS
uint16_t TOAWUS
Definition: lin.h:263
SCISETINTLVL_REG
Definition: lin.h:217
SCICLEARINTLVL_BITS::CLRWAKEUPINTLVL
uint16_t CLRWAKEUPINTLVL
Definition: lin.h:225
SCICLEARINTLVL_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:226
SCISETINTLVL_BITS::SETISFEINTLVL
uint16_t SETISFEINTLVL
Definition: lin.h:210
IODFTCTRL_BITS::ISFERRENA
uint16_t ISFERRENA
Definition: lin.h:474
IODFTCTRL_REG
Definition: lin.h:481
SCIGCR1_BITS::STOP
uint16_t STOP
Definition: lin.h:81
SCISETINTLVL_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:200
SCIGCR1_BITS::MBUFMODE
uint16_t MBUFMODE
Definition: lin.h:87
SCIGCR1_BITS::ADAPT
uint16_t ADAPT
Definition: lin.h:86
SCISETINTLVL_BITS::SETFEINTLVL
uint16_t SETFEINTLVL
Definition: lin.h:208
SCICLEARINTLVL_REG::bit
struct SCICLEARINTLVL_BITS bit
Definition: lin.h:252
SCICLEARINT_BITS
Definition: lin.h:157
SCIGCR2_BITS::POWERDOWN
uint16_t POWERDOWN
Definition: lin.h:108
SCISETINT_BITS::SETBRKDTINT
uint16_t SETBRKDTINT
Definition: lin.h:125
LIN_REGS::SCIGCR2
union SCIGCR2_REG SCIGCR2
Definition: lin.h:494
SCIFLR_BITS::ISFE
uint16_t ISFE
Definition: lin.h:278
LINRD1_BITS::RD7
uint16_t RD7
Definition: lin.h:392
SCISETINTLVL_BITS::SETRXINTOVO
uint16_t SETRXINTOVO
Definition: lin.h:199
LIN_REGS::LINTD0
union LINTD0_REG LINTD0
Definition: lin.h:515
SCISETINTLVL_BITS::SETWAKEUPINTLVL
uint16_t SETWAKEUPINTLVL
Definition: lin.h:192
LINID_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:423
SCIFLR_BITS::IDTXFLAG
uint16_t IDTXFLAG
Definition: lin.h:270
SCISETINT_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:127
SCIGCR2_REG::bit
struct SCIGCR2_BITS bit
Definition: lin.h:120
IODFTCTRL_BITS::PBERRENA
uint16_t PBERRENA
Definition: lin.h:476
LINTD0_BITS::TD3
uint16_t TD3
Definition: lin.h:434
LINID_REG::bit
struct LINID_BITS bit
Definition: lin.h:429
IODFTCTRL_BITS::PINSAMPLEMASK
uint16_t PINSAMPLEMASK
Definition: lin.h:468
LINCOMP_REG::all
uint32_t all
Definition: lin.h:371
LINRD1_REG
Definition: lin.h:399
LINTD0_BITS::TD0
uint16_t TD0
Definition: lin.h:437
SCIFLR_BITS::rsvd4
uint16_t rsvd4
Definition: lin.h:273
SCIFLR_BITS::PE
uint16_t PE
Definition: lin.h:274
SCICLEARINTLVL_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:233
SCIFORMAT_REG::bit
struct SCIFORMAT_BITS bit
Definition: lin.h:327
SCISETINT_REG::all
uint32_t all
Definition: lin.h:152
LIN_REGS::LINCOMP
union LINCOMP_REG LINCOMP
Definition: lin.h:510
SCIGCR1_BITS::rsvd3
uint16_t rsvd3
Definition: lin.h:94
SCISETINTLVL_BITS::SETTOAWUSINTLVL
uint16_t SETTOAWUSINTLVL
Definition: lin.h:196
LINRD0_REG
Definition: lin.h:385
LINTD1_REG::all
uint32_t all
Definition: lin.h:456
SCIGCR1_BITS::PARITYENA
uint16_t PARITYENA
Definition: lin.h:79
SCIGCR2_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:109
SCISETINT_BITS::SETPEINT
uint16_t SETPEINT
Definition: lin.h:140
SCIFLR_BITS::FE
uint16_t FE
Definition: lin.h:276
SCIGCR2_BITS::CC
uint16_t CC
Definition: lin.h:113
SCIFLR_BITS::TXEMPTY
uint16_t TXEMPTY
Definition: lin.h:268
SCICLEARINT_BITS::CLRTOA3WUSINT
uint16_t CLRTOA3WUSINT
Definition: lin.h:164
SCIGCR1_BITS
Definition: lin.h:76
SCIGCR1_BITS::LOOPBACK
uint16_t LOOPBACK
Definition: lin.h:92
SCIINTVECT1_REG::all
uint32_t all
Definition: lin.h:312
SCISETINTLVL_BITS::rsvd4
uint16_t rsvd4
Definition: lin.h:202
LINMASK_REG::all
uint32_t all
Definition: lin.h:414
SCICLEARINT_BITS::rsvd4
uint16_t rsvd4
Definition: lin.h:169
SCIPIO2_BITS::RXIN
uint16_t RXIN
Definition: lin.h:347
SCIFLR_BITS::TXWAKE
uint16_t TXWAKE
Definition: lin.h:267
SCISETINT_BITS::rsvd6
uint16_t rsvd6
Definition: lin.h:138
LIN_REGS::LINTD1
union LINTD1_REG LINTD1
Definition: lin.h:516
SCIGCR1_REG::all
uint32_t all
Definition: lin.h:102
LINRD1_BITS::RD4
uint16_t RD4
Definition: lin.h:395
LIN_REGS::IODFTCTRL
union IODFTCTRL_REG IODFTCTRL
Definition: lin.h:519
SCICLEARINTLVL_BITS::rsvd4
uint16_t rsvd4
Definition: lin.h:235
SCIFORMAT_BITS
Definition: lin.h:317
SCISETINTLVL_BITS::rsvd1
uint16_t rsvd1
Definition: lin.h:193
SCISETINTLVL_BITS::SETTXINTLVL
uint16_t SETTXINTLVL
Definition: lin.h:198
SCISETINT_BITS
Definition: lin.h:124
SCIPIO2_REG::bit
struct SCIPIO2_BITS bit
Definition: lin.h:356
SCISETINT_BITS::SETTXINT
uint16_t SETTXINT
Definition: lin.h:132
SCISETINTLVL_BITS::SETBEINTLVL
uint16_t SETBEINTLVL
Definition: lin.h:213