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pll.h
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1 /* --COPYRIGHT--,BSD
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32 #ifndef _PLL_H_
33 #define _PLL_H_
34
41
42
43 // **************************************************************************
44 // the includes
45
46 #include "sw/modules/types/src/types.h"
47
48 #include "sw/drivers/cpu/src/32b/f28x/f2806x/cpu.h"
49
50
55
56
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61
62
63 // **************************************************************************
64 // the defines
65
66
69 #define PLL_BASE_ADDR (0x00007011)
70
71
74 #define PLL_PLLCR_DIV_BITS (15 << 0)
75
76
79 #define PLL_PLLSTS_PLLLOCKS_BITS (1 << 0)
80
83 #define PLL_PLLSTS_PLLOFF_BITS (1 << 2)
84
87 #define PLL_PLLSTS_MCLKSTS_BITS (1 << 3)
88
91 #define PLL_PLLSTS_MCLKCLR_BITS (1 << 4)
92
95 #define PLL_PLLSTS_OSCOFF_BITS (1 << 5)
96
99 #define PLL_PLLSTS_MCLKOFF_BITS (1 << 6)
100
103 #define PLL_PLLSTS_DIVSEL_BITS (3 << 7)
104
107 #define PLL_PLLSTS_NORMRDYE_BITS (1 << 15)
108
109
110 // **************************************************************************
111 // the typedefs
112
113
116 typedef enum
117 {
118 PLL_ClkFreq_5_MHz=(1 << 0),
119 PLL_ClkFreq_10_MHz=(2 << 0),
120 PLL_ClkFreq_15_MHz=(3 << 0),
121 PLL_ClkFreq_20_MHz=(4 << 0),
122 PLL_ClkFreq_25_MHz=(5 << 0),
123 PLL_ClkFreq_30_MHz=(6 << 0),
124 PLL_ClkFreq_35_MHz=(7 << 0),
125 PLL_ClkFreq_40_MHz=(8 << 0),
126 PLL_ClkFreq_45_MHz=(9 << 0),
127 PLL_ClkFreq_50_MHz=(10 << 0),
128 PLL_ClkFreq_55_MHz=(11 << 0),
129 PLL_ClkFreq_60_MHz=(12 << 0),
130 PLL_ClkFreq_65_MHz=(13 << 0),
131 PLL_ClkFreq_70_MHz=(14 << 0),
132 PLL_ClkFreq_75_MHz=(15 << 0),
133 PLL_ClkFreq_80_MHz=(16 << 0),
134 PLL_ClkFreq_85_MHz=(17 << 0),
135 PLL_ClkFreq_90_MHz=(18 << 0)
136 } PLL_ClkFreq_e;
137
138
141 typedef enum
142 {
143 PLL_DivideSelect_ClkIn_by_4=(0 << 7),
144 PLL_DivideSelect_ClkIn_by_2=(2 << 7),
145 PLL_DivideSelect_ClkIn_by_1=(3 << 7)
146 } PLL_DivideSelect_e;
147
148
151 typedef enum
152 {
153 PLL_ClkStatus_Normal=(0 << 3),
154 PLL_ClkStatus_Missing=(1 << 3)
155 } PLL_ClkStatus_e;
156
157
160 typedef enum
161 {
162 PLL_LockStatus_Locking=(0 << 0),
163 PLL_LockStatus_Done=(1 << 0)
164 } PLL_LockStatus_e;
165
166
169 typedef struct _PLL_Obj_
170 {
171 volatile uint16_t PLLSTS;
172 volatile uint16_t rsvd_1;
173 volatile uint16_t PLLLOCKPRD;
174 volatile uint16_t rsvd_2[13];
175 volatile uint16_t PLLCR;
176 } PLL_Obj;
177
178
181 typedef struct _PLL_Obj_ *PLL_Handle;
182
183
184 // **************************************************************************
185 // the globals
186
187
188 // **************************************************************************
189 // the function prototypes
190
193 extern void PLL_disable(PLL_Handle pllHandle);
194
195
198 extern void PLL_disableClkDetect(PLL_Handle pllHandle);
199
200
203 extern void PLL_disableNormRdy(PLL_Handle pllHandle);
204
205
208 extern void PLL_disableOsc(PLL_Handle pllHandle);
209
210
213 extern void PLL_enable(PLL_Handle pllHandle);
214
215
218 extern void PLL_enableClkDetect(PLL_Handle pllHandle);
219
220
223 extern void PLL_enableNormRdy(PLL_Handle pllHandle);
224
225
228 extern void PLL_enableOsc(PLL_Handle pllHandle);
229
230
234 extern PLL_ClkFreq_e PLL_getClkFreq(PLL_Handle pllHandle);
235
236
240 extern PLL_ClkStatus_e PLL_getClkStatus(PLL_Handle pllHandle);
241
242
246 extern PLL_DivideSelect_e PLL_getDivideSelect(PLL_Handle pllHandle);
247
248
252 extern PLL_LockStatus_e PLL_getLockStatus(PLL_Handle pllHandle);
253
254
259 extern PLL_Handle PLL_init(void *pMemory,const size_t numBytes);
260
261
264 extern void PLL_resetClkDetect(PLL_Handle pllHandle);
265
266
270 extern void PLL_setClkFreq(PLL_Handle pllHandle,const PLL_ClkFreq_e freq);
271
272
276 extern void PLL_setDivideSelect(PLL_Handle pllHandle,const PLL_DivideSelect_e divSelect);
277
278
282 extern void PLL_setLockPeriod(PLL_Handle pllHandle,const uint16_t lockPeriod);
283
284
285 #ifdef __cplusplus
286 }
287 #endif // extern "C"
288
290 #endif // end of _PLL_H_ definition
291
PLL_disableClkDetect
void PLL_disableClkDetect(PLL_Handle pllHandle)
Disables the clock detect logic.
Definition: pll.c:73
PLL_ClkFreq_60_MHz
Denotes a clock frequency of 60 MHz.
Definition: pll.h:129
PLL_ClkFreq_40_MHz
Denotes a clock frequency of 40 MHz.
Definition: pll.h:125
PLL_Obj
struct _PLL_Obj_ PLL_Obj
Defines the phase lock loop (PLL) object.
PLL_enable
void PLL_enable(PLL_Handle pllHandle)
Enables the phase lock loop (PLL)
Definition: pll.c:121
_PLL_Obj_::PLLSTS
volatile uint16_t PLLSTS
PLL Status Register.
Definition: pll.h:171
PLL_ClkFreq_30_MHz
Denotes a clock frequency of 30 MHz.
Definition: pll.h:123
PLL_ClkFreq_70_MHz
Denotes a clock frequency of 70 MHz.
Definition: pll.h:131
PLL_ClkFreq_10_MHz
Denotes a clock frequency of 10 MHz.
Definition: pll.h:119
PLL_getLockStatus
PLL_LockStatus_e PLL_getLockStatus(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) lock status.
Definition: pll.c:219
PLL_disableNormRdy
void PLL_disableNormRdy(PLL_Handle pllHandle)
Disables the NORMRDY signal.
Definition: pll.c:89
PLL_getClkStatus
PLL_ClkStatus_e PLL_getClkStatus(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) clock status.
Definition: pll.c:197
PLL_ClkFreq_90_MHz
Denotes a clock frequency of 90 MHz.
Definition: pll.h:135
PLL_disable
void PLL_disable(PLL_Handle pllHandle)
Disables the phase lock loop (PLL)
Definition: pll.c:57
PLL_ClkFreq_80_MHz
Denotes a clock frequency of 80 MHz.
Definition: pll.h:133
PLL_DivideSelect_ClkIn_by_1
Denotes a divide select of CLKIN/1.
Definition: pll.h:145
PLL_setDivideSelect
void PLL_setDivideSelect(PLL_Handle pllHandle, const PLL_DivideSelect_e divSelect)
Sets the phase lock loop (PLL) divide select value.
Definition: pll.c:278
PLL_getClkFreq
PLL_ClkFreq_e PLL_getClkFreq(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) clock frequency.
Definition: pll.c:185
PLL_ClkFreq_50_MHz
Denotes a clock frequency of 50 MHz.
Definition: pll.h:127
PLL_ClkFreq_85_MHz
Denotes a clock frequency of 85 MHz.
Definition: pll.h:134
PLL_disableOsc
void PLL_disableOsc(PLL_Handle pllHandle)
Disables the oscillator.
Definition: pll.c:105
PLL_ClkFreq_65_MHz
Denotes a clock frequency of 65 MHz.
Definition: pll.h:130
PLL_enableNormRdy
void PLL_enableNormRdy(PLL_Handle pllHandle)
Enables the NORMRDY signal.
Definition: pll.c:153
PLL_Handle
struct _PLL_Obj_ * PLL_Handle
Defines the phase lock loop (PLL) handle.
Definition: pll.h:181
PLL_ClkFreq_45_MHz
Denotes a clock frequency of 45 MHz.
Definition: pll.h:126
PLL_enableClkDetect
void PLL_enableClkDetect(PLL_Handle pllHandle)
Enables the clock detect logic.
Definition: pll.c:137
PLL_ClkFreq_25_MHz
Denotes a clock frequency of 25 MHz.
Definition: pll.h:122
PLL_ClkStatus_Missing
Denotes a missing clock.
Definition: pll.h:154
_PLL_Obj_
Defines the phase lock loop (PLL) object.
Definition: pll.h:169
PLL_DivideSelect_ClkIn_by_4
Denotes a divide select of CLKIN/4.
Definition: pll.h:143
PLL_setClkFreq
void PLL_setClkFreq(PLL_Handle pllHandle, const PLL_ClkFreq_e freq)
Sets the phase lock loop (PLL) clock frequency.
Definition: pll.c:262
_PLL_Obj_::rsvd_2
volatile uint16_t rsvd_2[13]
Reserved.
Definition: pll.h:174
PLL_LockStatus_Locking
Denotes that the system is locking to the clock.
Definition: pll.h:162
PLL_ClkFreq_5_MHz
Denotes a clock frequency of 5 MHz.
Definition: pll.h:118
PLL_ClkFreq_e
PLL_ClkFreq_e
Enumeration to define the phase lock loop (PLL) clock frequency.
Definition: pll.h:116
PLL_ClkFreq_75_MHz
Denotes a clock frequency of 75 MHz.
Definition: pll.h:132
PLL_ClkStatus_Normal
Denotes a normal clock.
Definition: pll.h:153
cpu.h
Contains public interface to various functions related to the central processing unit (CPU) object...
PLL_DivideSelect_e
PLL_DivideSelect_e
Enumeration to define the phase lock loop (PLL) divide select.
Definition: pll.h:141
PLL_ClkFreq_35_MHz
Denotes a clock frequency of 35 MHz.
Definition: pll.h:124
PLL_getDivideSelect
PLL_DivideSelect_e PLL_getDivideSelect(PLL_Handle pllHandle)
Gets the phase lock loop (PLL) divide select value.
Definition: pll.c:208
PLL_setLockPeriod
void PLL_setLockPeriod(PLL_Handle pllHandle, const uint16_t lockPeriod)
Sets the phase lock loop (PLL) lock time.
Definition: pll.c:297
_PLL_Obj_::PLLLOCKPRD
volatile uint16_t PLLLOCKPRD
PLL Lock Period Register.
Definition: pll.h:173
PLL_init
PLL_Handle PLL_init(void *pMemory, const size_t numBytes)
Initializes the phase lock loop (PLL) object handle.
Definition: pll.c:231
PLL_ClkFreq_20_MHz
Denotes a clock frequency of 20 MHz.
Definition: pll.h:121
_PLL_Obj_::rsvd_1
volatile uint16_t rsvd_1
Reserved.
Definition: pll.h:172
PLL_LockStatus_Done
Denotes that the system is locked to the clock.
Definition: pll.h:163
_PLL_Obj_::PLLCR
volatile uint16_t PLLCR
PLL Control Register.
Definition: pll.h:175
PLL_DivideSelect_ClkIn_by_2
Denotes a divide select of CLKIN/2.
Definition: pll.h:144
PLL_resetClkDetect
void PLL_resetClkDetect(PLL_Handle pllHandle)
Resets the phase lock loop (PLL) clock detect logic.
Definition: pll.c:246
PLL_LockStatus_e
PLL_LockStatus_e
Enumeration to define the phase lock loop (PLL) clock lock status.
Definition: pll.h:160
PLL_ClkStatus_e
PLL_ClkStatus_e
Enumeration to define the phase lock loop (PLL) clock status.
Definition: pll.h:151
PLL_ClkFreq_55_MHz
Denotes a clock frequency of 55 MHz.
Definition: pll.h:128
PLL_ClkFreq_15_MHz
Denotes a clock frequency of 15 MHz.
Definition: pll.h:120
PLL_enableOsc
void PLL_enableOsc(PLL_Handle pllHandle)
Enables the oscillator.
Definition: pll.c:169