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sci.c
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1 /* --COPYRIGHT--,BSD
2 * Copyright (c) 2015, Texas Instruments Incorporated
3 * All rights reserved.
4 *
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10 * notice, this list of conditions and the following disclaimer.
11 *
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14 * documentation and/or other materials provided with the distribution.
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37
38
39 // **************************************************************************
40 // the includes
41
42 #include "sw/drivers/sci/src/32b/f28x/f2806x/sci.h"
43
44
45 // **************************************************************************
46 // the defines
47
48
49 // **************************************************************************
50 // the globals
51
52
53 // **************************************************************************
54 // the functions
55
56
57 void SCI_clearAutoBaudDetect(SCI_Handle sciHandle)
58 {
59 SCI_Obj *sci = (SCI_Obj *)sciHandle;
60
61
62 // set the bits
63 sci->SCIFFCT |= SCI_SCIFFCT_ABDCLR_BITS;
64
65 return;
66 } // end of SCI_clearAutoBaudDetect() function
67
68
69 void SCI_clearRxFifoOvf(SCI_Handle sciHandle)
70 {
71 SCI_Obj *sci = (SCI_Obj *)sciHandle;
72
73
74 // set the bits
75 sci->SCIFFRX |= SCI_SCIFFRX_FIFO_OVFCLR_BITS;
76
77 return;
78 } // end of SCI_clearRxFifoOvf() function
79
80
81 void SCI_clearRxFifoInt(SCI_Handle sciHandle)
82 {
83 SCI_Obj *sci = (SCI_Obj *)sciHandle;
84
85
86 // set the bits
87 sci->SCIFFRX |= SCI_SCIFFRX_INTCLR_BITS;
88
89 return;
90 } // end of SCI_clearRxFifoInt() function
91
92
93 void SCI_clearTxFifoInt(SCI_Handle sciHandle)
94 {
95 SCI_Obj *sci = (SCI_Obj *)sciHandle;
96
97
98 // set the bits
99 sci->SCIFFTX |= SCI_SCIFFTX_INTCLR_BITS;
100
101 return;
102 } // end of SCI_clearTxFifoInt() function
103
104
105 void SCI_disable(SCI_Handle sciHandle)
106 {
107 SCI_Obj *sci = (SCI_Obj *)sciHandle;
108
109
110 // clear the bits
111 sci->SCICTL1 &= (~SCI_SCICTL1_RESET_BITS);
112
113 return;
114 } // end of SCI_disable() function
115
116
117 void SCI_disableAutoBaudAlign(SCI_Handle sciHandle)
118 {
119 SCI_Obj *sci = (SCI_Obj *)sciHandle;
120
121
122 // clear the bits
123 sci->SCIFFCT &= (~SCI_SCIFFCT_CDC_BITS);
124
125 return;
126 } // end of SCI_disableAutoBaudAlign() function
127
128
129 void SCI_disableLoopBack(SCI_Handle sciHandle)
130 {
131 SCI_Obj *sci = (SCI_Obj *)sciHandle;
132
133
134 // clear the bits
135 sci->SCICCR &= (~SCI_SCICCR_LB_ENA_BITS);
136
137 return;
138 } // end of SCI_disableLoopBack() function
139
140
141 void SCI_disableParity(SCI_Handle sciHandle)
142 {
143 SCI_Obj *sci = (SCI_Obj *)sciHandle;
144
145
146 // clear the bits
147 sci->SCICCR &= (~SCI_SCICCR_PARITY_ENA_BITS);
148
149 return;
150 } // end of SCI_disableParity() function
151
152
153 void SCI_disableRx(SCI_Handle sciHandle)
154 {
155 SCI_Obj *sci = (SCI_Obj *)sciHandle;
156
157
158 // clear the bits
159 sci->SCICTL1 &= (~SCI_SCICTL1_RXENA_BITS);
160
161 return;
162 } // end of SCI_disableRx() function
163
164
165 void SCI_disableRxErrorInt(SCI_Handle sciHandle)
166 {
167 SCI_Obj *sci = (SCI_Obj *)sciHandle;
168
169
170 // clear the bits
171 sci->SCICTL1 &= (~SCI_SCICTL1_RX_ERR_INT_ENA_BITS);
172
173 return;
174 } // end of SCI_disableRxErrorInt() function
175
176
177 void SCI_disableRxFifoInt(SCI_Handle sciHandle)
178 {
179 SCI_Obj *sci = (SCI_Obj *)sciHandle;
180
181
182 // clear the bits
183 sci->SCIFFRX &= (~SCI_SCIFFRX_IENA_BITS);
184
185 return;
186 } // end of SCI_disableRxFifoInt() function
187
188
189 void SCI_disableRxInt(SCI_Handle sciHandle)
190 {
191 SCI_Obj *sci = (SCI_Obj *)sciHandle;
192
193
194 // clear the bits
195 sci->SCICTL2 &= (~SCI_SCICTL2_RX_INT_ENA_BITS);
196
197 return;
198 } // end of SCI_disableRxInt() function
199
200
201 void SCI_disableSleep(SCI_Handle sciHandle)
202 {
203 SCI_Obj *sci = (SCI_Obj *)sciHandle;
204
205
206 // clear the bits
207 sci->SCICTL1 &= (~SCI_SCICTL1_SLEEP_BITS);
208
209 return;
210 } // end of SCI_disableSleep() function
211
212
213 void SCI_disableTx(SCI_Handle sciHandle)
214 {
215 SCI_Obj *sci = (SCI_Obj *)sciHandle;
216
217
218 // clear the bits
219 sci->SCICTL1 &= (~SCI_SCICTL1_TXENA_BITS);
220
221 return;
222 } // end of SCI_disableTx() function
223
224
225 void SCI_disableTxFifoEnh(SCI_Handle sciHandle)
226 {
227 SCI_Obj *sci = (SCI_Obj *)sciHandle;
228
229
230 // clear the bits
231 sci->SCIFFTX &= (~SCI_SCIFFTX_FIFO_ENA_BITS);
232
233 return;
234 } // end of SCI_disableTxFifo() function
235
236
237 void SCI_disableTxFifoInt(SCI_Handle sciHandle)
238 {
239 SCI_Obj *sci = (SCI_Obj *)sciHandle;
240
241
242 // clear the bits
243 sci->SCIFFTX &= (~SCI_SCIFFTX_IENA_BITS);
244
245 return;
246 } // end of SCI_disableTxFifoInt() function
247
248
249 void SCI_disableTxInt(SCI_Handle sciHandle)
250 {
251 SCI_Obj *sci = (SCI_Obj *)sciHandle;
252
253
254 // clear the bits
255 sci->SCICTL2 &= (~SCI_SCICTL2_TX_INT_ENA_BITS);
256
257 return;
258 } // end of SCI_disableTxInt() function
259
260
261 void SCI_disableTxWake(SCI_Handle sciHandle)
262 {
263 SCI_Obj *sci = (SCI_Obj *)sciHandle;
264
265
266 // clear the bits
267 sci->SCICTL1 &= (~SCI_SCICTL1_TXWAKE_BITS);
268
269 return;
270 } // end of SCI_disableTxWake() function
271
272
273 void SCI_enable(SCI_Handle sciHandle)
274 {
275 SCI_Obj *sci = (SCI_Obj *)sciHandle;
276
277
278 // set the bits
279 sci->SCICTL1 |= SCI_SCICTL1_RESET_BITS;
280
281 return;
282 } // end of SCI_enable() function
283
284
285 void SCI_enableAutoBaudAlign(SCI_Handle sciHandle)
286 {
287 SCI_Obj *sci = (SCI_Obj *)sciHandle;
288
289
290 // set the bits
291 sci->SCIFFCT |= SCI_SCIFFCT_CDC_BITS;
292
293 return;
294 } // end of SCI_enableAutoBaudAlign() function
295
296
297 void SCI_enableChannels(SCI_Handle sciHandle)
298 {
299 SCI_Obj *sci = (SCI_Obj *)sciHandle;
300
301
302 // set the bits
303 sci->SCIFFTX |= (uint16_t)SCI_SCIFFTX_CHAN_RESET_BITS;
304
305 return;
306 } // SCI_enableChannels() function
307
308
309 void SCI_enableLoopBack(SCI_Handle sciHandle)
310 {
311 SCI_Obj *sci = (SCI_Obj *)sciHandle;
312
313
314 // set the bits
315 sci->SCICCR |= SCI_SCICCR_LB_ENA_BITS;
316
317 return;
318 } // end of SCI_enableLoopBack() function
319
320
321 void SCI_enableParity(SCI_Handle sciHandle)
322 {
323 SCI_Obj *sci = (SCI_Obj *)sciHandle;
324
325
326 // set the bits
327 sci->SCICCR |= SCI_SCICCR_PARITY_ENA_BITS;
328
329 return;
330 } // end of SCI_enableParity() function
331
332
333 void SCI_enableRx(SCI_Handle sciHandle)
334 {
335 SCI_Obj *sci = (SCI_Obj *)sciHandle;
336
337
338 // set the bits
339 sci->SCICTL1 |= SCI_SCICTL1_RXENA_BITS;
340
341 return;
342 } // end of SCI_enableRx() function
343
344
345 void SCI_enableRxErrorInt(SCI_Handle sciHandle)
346 {
347 SCI_Obj *sci = (SCI_Obj *)sciHandle;
348
349
350 // set the bits
351 sci->SCICTL1 |= SCI_SCICTL1_RX_ERR_INT_ENA_BITS;
352
353 return;
354 } // end of SCI_enableRxErrorInt() function
355
356
357 void SCI_enableRxInt(SCI_Handle sciHandle)
358 {
359 SCI_Obj *sci = (SCI_Obj *)sciHandle;
360
361
362 // set the bits
363 sci->SCICTL2 |= SCI_SCICTL2_RX_INT_ENA_BITS;
364
365 return;
366 } // end of SCI_enableRxInt() function
367
368
369 void SCI_enableSleep(SCI_Handle sciHandle)
370 {
371 SCI_Obj *sci = (SCI_Obj *)sciHandle;
372
373
374 // set the bits
375 sci->SCICTL1 |= SCI_SCICTL1_SLEEP_BITS;
376
377 return;
378 } // end of SCI_enableSleep() function
379
380
381 void SCI_enableRxFifo(SCI_Handle sciHandle)
382 {
383 SCI_Obj *sci = (SCI_Obj *)sciHandle;
384
385
386 // set the bits
387 sci->SCIFFRX |= SCI_SCIFFRX_FIFO_RESET_BITS;
388
389 return;
390 } // end of SCI_enableRxFifo() function
391
392
393 void SCI_enableRxFifoInt(SCI_Handle sciHandle)
394 {
395 SCI_Obj *sci = (SCI_Obj *)sciHandle;
396
397
398 // set the bits
399 sci->SCIFFRX |= SCI_SCIFFRX_IENA_BITS;
400
401 return;
402 } // end of SCI_enableRxFifoInt() function
403
404
405 void SCI_enableTx(SCI_Handle sciHandle)
406 {
407 SCI_Obj *sci = (SCI_Obj *)sciHandle;
408
409
410 // set the bits
411 sci->SCICTL1 |= SCI_SCICTL1_TXENA_BITS;
412
413 return;
414 } // end of SCI_enableTx() function
415
416
417 void SCI_enableTxFifo(SCI_Handle sciHandle)
418 {
419 SCI_Obj *sci = (SCI_Obj *)sciHandle;
420
421
422 // set the bits
423 sci->SCIFFTX |= SCI_SCIFFTX_FIFO_RESET_BITS;
424
425 return;
426 } // end of SCI_enableTxFifo() function
427
428
429 void SCI_enableTxFifoEnh(SCI_Handle sciHandle)
430 {
431 SCI_Obj *sci = (SCI_Obj *)sciHandle;
432
433
434 // set the bits
435 sci->SCIFFTX |= SCI_SCIFFTX_FIFO_ENA_BITS;
436
437 return;
438 } // end of SCI_enableTxFifo() function
439
440
441 void SCI_enableTxFifoInt(SCI_Handle sciHandle)
442 {
443 SCI_Obj *sci = (SCI_Obj *)sciHandle;
444
445
446 // set the bits
447 sci->SCIFFTX |= SCI_SCIFFTX_IENA_BITS;
448
449 return;
450 } // end of SCI_enableTxFifoInt() function
451
452
453 void SCI_enableTxInt(SCI_Handle sciHandle)
454 {
455 SCI_Obj *sci = (SCI_Obj *)sciHandle;
456
457
458 // set the bits
459 sci->SCICTL2 |= SCI_SCICTL2_TX_INT_ENA_BITS;
460
461 return;
462 } // end of SCI_enableTxInt() function
463
464
465 void SCI_enableTxWake(SCI_Handle sciHandle)
466 {
467 SCI_Obj *sci = (SCI_Obj *)sciHandle;
468
469
470 // set the bits
471 sci->SCICTL1 |= SCI_SCICTL1_TXWAKE_BITS;
472
473 return;
474 } // end of SCI_enableTxWake() function
475
476
477 uint16_t SCI_getDataBlocking(SCI_Handle sciHandle)
478 {
479 SCI_Obj *sci = (SCI_Obj *)sciHandle;
480
481 while(SCI_rxDataReady(sciHandle) != true)
482 {
483 }
484
485 return(sci->SCIRXBUF);
486 } // end of SCI_getDataBlocking() function
487
488
489 uint16_t SCI_getDataNonBlocking(SCI_Handle sciHandle, uint16_t * success)
490 {
491 SCI_Obj *sci = (SCI_Obj *)sciHandle;
492
493 if(SCI_rxDataReady(sciHandle))
494 {
495 *success = true;
496 return(sci->SCIRXBUF);
497 }
498
499 *success = false;
500 return(NULL);
501 } // end of SCI_getDataNonBlocking() function
502
503
504 SCI_FifoStatus_e SCI_getRxFifoStatus(SCI_Handle sciHandle)
505 {
506 SCI_Obj *sci = (SCI_Obj *)sciHandle;
507 SCI_FifoStatus_e status;
508
509 // get the status
510 status = (SCI_FifoStatus_e)(sci->SCIFFRX & SCI_SCIFFRX_FIFO_ST_BITS);
511
512 return(status);
513 } // SCI_getRxFifoStatus() function
514
515
516 SCI_FifoStatus_e SCI_getTxFifoStatus(SCI_Handle sciHandle)
517 {
518 SCI_Obj *sci = (SCI_Obj *)sciHandle;
519 SCI_FifoStatus_e status;
520
521 // get the status
522 status = (SCI_FifoStatus_e)(sci->SCIFFTX & SCI_SCIFFTX_FIFO_ST_BITS);
523
524 return(status);
525 } // SCI_getTxFifoStatus() function
526
527
528 SCI_Handle SCI_init(void *pMemory,const size_t numBytes)
529 {
530 SCI_Handle sciHandle;
531
532
533 if(numBytes < sizeof(SCI_Obj))
534 return((SCI_Handle)NULL);
535
536 // assign the handle
537 sciHandle = (SCI_Handle)pMemory;
538
539 return(sciHandle);
540 } // end of SCI_init() function
541
542
543 void SCI_putDataBlocking(SCI_Handle sciHandle, uint16_t data)
544 {
545 SCI_Obj *sci = (SCI_Obj *)sciHandle;
546
547 while(SCI_txReady(sciHandle) != true)
548 {
549 }
550
551 // write the data
552 sci->SCITXBUF = data;
553
554 return;
555 } // end of SCI_putDataBlocking() function
556
557
558 uint16_t SCI_putDataNonBlocking(SCI_Handle sciHandle, uint16_t data)
559 {
560 SCI_Obj *sci = (SCI_Obj *)sciHandle;
561
562 if(SCI_txReady(sciHandle))
563 {
564 // write the data
565 sci->SCITXBUF = data;
566
567 return(true);
568 }
569
570 return(false);
571 } // end of SCI_putDataNonBlocking() function
572
573
574 void SCI_reset(SCI_Handle sciHandle)
575 {
576 SCI_Obj *sci = (SCI_Obj *)sciHandle;
577
578
579 // clear the bits
580 sci->SCICTL1 &= (~SCI_SCICTL1_RESET_BITS);
581
582 return;
583 } // end of SCI_reset() function
584
585
586 void SCI_resetChannels(SCI_Handle sciHandle)
587 {
588 SCI_Obj *sci = (SCI_Obj *)sciHandle;
589
590
591 // clear the bits
592 sci->SCIFFTX &= (~SCI_SCIFFTX_CHAN_RESET_BITS);
593 asm(" nop");
594 sci->SCIFFTX |= (uint16_t)(SCI_SCIFFTX_CHAN_RESET_BITS);
595
596 return;
597 } // SCI_resetChannels() function
598
599
600 void SCI_resetRxFifo(SCI_Handle sciHandle)
601 {
602 SCI_Obj *sci = (SCI_Obj *)sciHandle;
603
604
605 // clear the bits
606 sci->SCIFFRX &= (~SCI_SCIFFRX_FIFO_RESET_BITS);
607 asm(" nop");
608 sci->SCIFFRX |= SCI_SCIFFRX_FIFO_RESET_BITS;
609
610 return;
611 } // end of SCI_resetRxFifo() function
612
613
614 void SCI_resetTxFifo(SCI_Handle sciHandle)
615 {
616 SCI_Obj *sci = (SCI_Obj *)sciHandle;
617
618
619 // clear the bits
620 sci->SCIFFTX &= (~SCI_SCIFFTX_FIFO_RESET_BITS);
621 asm(" nop");
622 sci->SCIFFTX |= SCI_SCIFFTX_FIFO_RESET_BITS;
623
624 return;
625 } // end of SCI_resetTxFifo() function
626
627
628 void SCI_setBaudRate(SCI_Handle sciHandle,const SCI_BaudRate_e baudRate)
629 {
630 SCI_Obj *sci = (SCI_Obj *)sciHandle;
631
632
633 // set the bits
634 sci->SCIHBAUD = ((uint16_t)baudRate >> 8);
635 sci->SCILBAUD = baudRate & 0xFF;
636
637 return;
638 } // end of SCI_setBaudRate() function
639
640
641 void SCI_setCharLength(SCI_Handle sciHandle,const SCI_CharLength_e charLength)
642 {
643 SCI_Obj *sci = (SCI_Obj *)sciHandle;
644
645
646 // clear the bits
647 sci->SCICCR &= (~SCI_SCICCR_CHAR_LENGTH_BITS);
648
649 // set the bits
650 sci->SCICCR |= charLength;
651
652 return;
653 } // SCI_setCharLength() function
654
655
656 void SCI_setMode(SCI_Handle sciHandle,const SCI_Mode_e mode)
657 {
658 SCI_Obj *sci = (SCI_Obj *)sciHandle;
659
660
661 // clear the bits
662 sci->SCICCR &= (~SCI_SCICCR_MODE_BITS);
663
664 // set the bits
665 sci->SCICCR |= mode;
666
667 return;
668 } // SCI_setMode() function
669
670
671 void SCI_setNumStopBits(SCI_Handle sciHandle,const SCI_NumStopBits_e numBits)
672 {
673 SCI_Obj *sci = (SCI_Obj *)sciHandle;
674
675
676 // clear the bits
677 sci->SCICCR &= (~SCI_SCICCR_STOP_BITS);
678
679 // set the bits
680 sci->SCICCR |= numBits;
681
682 return;
683 } // SCI_setNumStopBits() function
684
685
686 void SCI_setPriority(SCI_Handle sciHandle,const SCI_Priority_e priority)
687 {
688 SCI_Obj *sci = (SCI_Obj *)sciHandle;
689
690
691 // set the bits
692 sci->SCIPRI = priority;
693
694 return;
695 } // SCI_setPriority() function
696
697
698 void SCI_setParity(SCI_Handle sciHandle,const SCI_Parity_e parity)
699 {
700 SCI_Obj *sci = (SCI_Obj *)sciHandle;
701
702
703 // clear the bits
704 sci->SCICCR &= (~SCI_SCICCR_PARITY_BITS);
705
706 // set the bits
707 sci->SCICCR |= parity;
708
709 return;
710 } // SCI_setParity() function
711
712
713 void SCI_setTxDelay(SCI_Handle sciHandle,const uint_least8_t delay)
714 {
715 SCI_Obj *sci = (SCI_Obj *)sciHandle;
716
717
718 // clear the bits
719 sci->SCIFFCT &= (~SCI_SCIFFCT_DELAY_BITS);
720
721 // set the bits
722 sci->SCIFFCT |= delay;
723
724 return;
725 } // end of SCI_setTxDelay() function
726
727 void SCI_setRxFifoIntLevel(SCI_Handle sciHandle, const SCI_FifoLevel_e fifoLevel)
728 {
729 SCI_Obj *sci = (SCI_Obj *)sciHandle;
730
731
732 // clear the value
733 sci->SCIFFRX &= (~SCI_SCIFFRX_IL_BITS);
734
735 // set the bits
736 sci->SCIFFRX |= fifoLevel;
737
738 return;
739 } // end of SCI_setRxFifoIntLevel() function
740
741 void SCI_setTxFifoIntLevel(SCI_Handle sciHandle,const SCI_FifoLevel_e fifoLevel)
742 {
743 SCI_Obj *sci = (SCI_Obj *)sciHandle;
744
745
746 // clear the value
747 sci->SCIFFTX &= (~SCI_SCIFFTX_IL_BITS);
748
749 // set the bits
750 sci->SCIFFTX |= fifoLevel;
751
752 return;
753 } // end of SCI_setTxFifoIntLevel() function
754
755
756 // end of file
SCI_Handle
struct _SCI_Obj_ * SCI_Handle
Defines the serial communications interface (SCI) handle.
Definition: sci.h:371
SCI_SCICCR_PARITY_BITS
#define SCI_SCICCR_PARITY_BITS
Defines the location of the EVEN/ODD PARITY bits in the SCICCR register.
Definition: sci.h:96
SCI_clearAutoBaudDetect
void SCI_clearAutoBaudDetect(SCI_Handle sciHandle)
Clears the auto baud detect mode.
Definition: sci.c:57
SCI_getDataBlocking
uint16_t SCI_getDataBlocking(SCI_Handle sciHandle)
Gets data from the serial communications interface (Blocking)
Definition: sci.c:477
SCI_setPriority
void SCI_setPriority(SCI_Handle sciHandle, const SCI_Priority_e priority)
Sets the serial communications interface (SCI) priority.
Definition: sci.c:686
SCI_SCIFFCT_CDC_BITS
#define SCI_SCIFFCT_CDC_BITS
Defines the location of the CDC bits in the SCIFFCT register.
Definition: sci.h:246
SCI_reset
void SCI_reset(SCI_Handle sciHandle)
Resets the serial communications interface (SCI)
Definition: sci.c:574
SCI_SCIFFTX_IENA_BITS
#define SCI_SCIFFTX_IENA_BITS
Defines the location of the TXFFIENA bits in the SCIFFTX register.
Definition: sci.h:213
SCI_enableTxWake
void SCI_enableTxWake(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) wakeup method.
Definition: sci.c:465
SCI_FifoLevel_e
SCI_FifoLevel_e
Enumeration to define the serial communications interface (SCI) FIFO level.
Definition: sci.h:325
SCI_enable
void SCI_enable(SCI_Handle sciHandle)
Enables the serial communications interface (SCI)
Definition: sci.c:273
SCI_enableTx
void SCI_enableTx(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) masater/slave transmit mode.
Definition: sci.c:405
SCI_enableRxInt
void SCI_enableRxInt(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) receive interrupt.
Definition: sci.c:357
SCI_SCIFFTX_IL_BITS
#define SCI_SCIFFTX_IL_BITS
Defines the location of the TXFFIL4-0 bits in the SCIFFTX register.
Definition: sci.h:209
_SCI_Obj_::SCIFFTX
volatile uint16_t SCIFFTX
SCI FIFO Transmit Register.
Definition: sci.h:361
SCI_SCICCR_PARITY_ENA_BITS
#define SCI_SCICCR_PARITY_ENA_BITS
Defines the location of the PARITY ENABLE bits in the SCICCR register.
Definition: sci.h:92
SCI_disable
void SCI_disable(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) interrupt.
Definition: sci.c:105
SCI_disableTx
void SCI_disableTx(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) master/slave transmit mode.
Definition: sci.c:213
SCI_enableAutoBaudAlign
void SCI_enableAutoBaudAlign(SCI_Handle sciHandle)
Enable the serial communications interface (SCI) auto baud alignment.
Definition: sci.c:285
SCI_setMode
void SCI_setMode(SCI_Handle sciHandle, const SCI_Mode_e mode)
Sets the serial communications interface (SCI) miltprocessor mode.
Definition: sci.c:656
_SCI_Obj_::SCIPRI
volatile uint16_t SCIPRI
SCI Priority Register.
Definition: sci.h:365
SCI_enableTxFifoInt
void SCI_enableTxFifoInt(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) transmit FIFO interrupt.
Definition: sci.c:441
SCI_setRxFifoIntLevel
void SCI_setRxFifoIntLevel(SCI_Handle sciHandle, const SCI_FifoLevel_e fifoLevel)
Sets the serial communications interface (SCI) receive FIFO level for generating an interrupt...
Definition: sci.c:727
SCI_SCICTL1_RESET_BITS
#define SCI_SCICTL1_RESET_BITS
Defines the location of the SW RESET bits in the SCICTL1 register.
Definition: sci.h:121
SCI_SCIFFTX_FIFO_RESET_BITS
#define SCI_SCIFFTX_FIFO_RESET_BITS
Defines the location of the TXFIFO Reset bits in the SCIFFTX register.
Definition: sci.h:229
SCI_enableParity
void SCI_enableParity(SCI_Handle sciHandle)
Enables the serial peripheral interface (SCI) parity.
Definition: sci.c:321
_SCI_Obj_::SCICTL1
volatile uint16_t SCICTL1
SCI Control Register 1.
Definition: sci.h:352
SCI_enableTxFifo
void SCI_enableTxFifo(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) transmit FIFO.
Definition: sci.c:417
SCI_enableRxFifoInt
void SCI_enableRxFifoInt(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) receive FIFO interrupt.
Definition: sci.c:393
SCI_SCIFFTX_INTCLR_BITS
#define SCI_SCIFFTX_INTCLR_BITS
Defines the location of the TXFFINT CLR bits in the SCIFFTX register.
Definition: sci.h:217
SCI_disableLoopBack
void SCI_disableLoopBack(SCI_Handle sciHandle)
Disables the serial peripheral interface (SCI) loop back mode.
Definition: sci.c:129
SCI_rxDataReady
static bool SCI_rxDataReady(SCI_Handle sciHandle)
Determines if the serial communications interface (SCI) has receive data ready.
Definition: sci.h:639
SCI_SCICTL1_RXENA_BITS
#define SCI_SCICTL1_RXENA_BITS
Defines the location of the RXENA bits in the SCICTL1 register.
Definition: sci.h:105
SCI_SCIFFRX_FIFO_ST_BITS
#define SCI_SCIFFRX_FIFO_ST_BITS
Defines the location of the RXFFST4-0 bits in the SCIFFRX register.
Definition: sci.h:192
SCI_FifoStatus_e
SCI_FifoStatus_e
Enumeration to define the serial communications interface (SCI) FIFO status.
Definition: sci.h:337
SCI_setCharLength
void SCI_setCharLength(SCI_Handle sciHandle, const SCI_CharLength_e charLength)
Sets the serial communications interface (SCI) character length.
Definition: sci.c:641
SCI_SCIFFRX_IL_BITS
#define SCI_SCIFFRX_IL_BITS
Defines the location of the RXFFIL4-0 bits in the SCIFFRX register.
Definition: sci.h:176
SCI_enableSleep
void SCI_enableSleep(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) sleep mode.
Definition: sci.c:369
SCI_setBaudRate
void SCI_setBaudRate(SCI_Handle sciHandle, const SCI_BaudRate_e baudRate)
Sets the serial communications interface (SCI) baud rate.
Definition: sci.c:628
SCI_enableTxFifoEnh
void SCI_enableTxFifoEnh(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) transmit FIFO enhancements.
Definition: sci.c:429
SCI_getDataNonBlocking
uint16_t SCI_getDataNonBlocking(SCI_Handle sciHandle, uint16_t *success)
Read data from the serial communications interface (Non-Blocking)
Definition: sci.c:489
SCI_disableRxFifoInt
void SCI_disableRxFifoInt(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) receive FIFO interrupt.
Definition: sci.c:177
SCI_SCIFFRX_IENA_BITS
#define SCI_SCIFFRX_IENA_BITS
Defines the location of the RXFFIENA bits in the SCIFFRX register.
Definition: sci.h:180
SCI_disableRxErrorInt
void SCI_disableRxErrorInt(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) receive error interrupt.
Definition: sci.c:165
_SCI_Obj_::SCITXBUF
volatile uint16_t SCITXBUF
SCI Transmit Data Buffer Register.
Definition: sci.h:360
sci.h
Contains public interface to various functions related to the serial communications interface (SCI) o...
SCI_SCICTL1_SLEEP_BITS
#define SCI_SCICTL1_SLEEP_BITS
Defines the location of the SLEEP bits in the SCICTL1 register.
Definition: sci.h:113
SCI_NumStopBits_e
SCI_NumStopBits_e
Enumeration to define the serial communications interface (SCI) number of stop bits.
Definition: sci.h:297
SCI_setNumStopBits
void SCI_setNumStopBits(SCI_Handle sciHandle, const SCI_NumStopBits_e numBits)
Sets the serial communications interface (SCI) number of stop bits.
Definition: sci.c:671
SCI_SCIFFTX_FIFO_ST_BITS
#define SCI_SCIFFTX_FIFO_ST_BITS
Defines the location of the TXFFST4-0 bits in the SCIFFTX register.
Definition: sci.h:225
SCI_SCIFFRX_FIFO_RESET_BITS
#define SCI_SCIFFRX_FIFO_RESET_BITS
Defines the location of the RXFIFO Reset bits in the SCIFFRX register.
Definition: sci.h:196
SCI_clearRxFifoOvf
void SCI_clearRxFifoOvf(SCI_Handle sciHandle)
Clears the Rx FIFO overflow flag.
Definition: sci.c:69
SCI_SCICCR_STOP_BITS
#define SCI_SCICCR_STOP_BITS
Defines the location of the STOP bits in the SCICCR register.
Definition: sci.h:100
SCI_SCIFFCT_ABDCLR_BITS
#define SCI_SCIFFCT_ABDCLR_BITS
Defines the location of the ABD CLR bits in the SCIFFCT register.
Definition: sci.h:250
_SCI_Obj_
Defines the serial communications interface (SCI) object.
Definition: sci.h:349
SCI_resetTxFifo
void SCI_resetTxFifo(SCI_Handle sciHandle)
Resets the serial communications interface (SCI) transmit FIFO.
Definition: sci.c:614
SCI_disableParity
void SCI_disableParity(SCI_Handle sciHandle)
Disable the parity.
Definition: sci.c:141
SCI_disableAutoBaudAlign
void SCI_disableAutoBaudAlign(SCI_Handle sciHandle)
Disable the serial communications interface (SCI) auto baud alignment.
Definition: sci.c:117
SCI_CharLength_e
SCI_CharLength_e
Enumeration to define the serial communications interface (SCI) character lengths.
Definition: sci.h:273
SCI_SCICCR_LB_ENA_BITS
#define SCI_SCICCR_LB_ENA_BITS
Defines the location of the LOOP BACK ENA bits in the SCICCR register.
Definition: sci.h:88
SCI_enableRxFifo
void SCI_enableRxFifo(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) receive FIFO.
Definition: sci.c:381
SCI_disableRxInt
void SCI_disableRxInt(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) receive interrupt.
Definition: sci.c:189
SCI_txReady
static bool SCI_txReady(SCI_Handle sciHandle)
Determines if the serial communications interface (SCI) is ready to transmit.
Definition: sci.h:707
SCI_SCIFFCT_DELAY_BITS
#define SCI_SCIFFCT_DELAY_BITS
Defines the location of the FFTXDLY7-0 bits in the SCIFFCT register.
Definition: sci.h:242
SCI_setTxDelay
void SCI_setTxDelay(SCI_Handle sciHandle, const uint_least8_t delay)
Sets the serial communications interface (SCI) transmit delay.
Definition: sci.c:713
_SCI_Obj_::SCICTL2
volatile uint16_t SCICTL2
SCI Control Register 2.
Definition: sci.h:355
SCI_Priority_e
SCI_Priority_e
Enumeration to define the serial communications interface (SCI) emulation suspend priority...
Definition: sci.h:315
SCI_enableLoopBack
void SCI_enableLoopBack(SCI_Handle sciHandle)
Enables the serial peripheral interface (SCI) loop back mode.
Definition: sci.c:309
SCI_setParity
void SCI_setParity(SCI_Handle sciHandle, const SCI_Parity_e parity)
Sets the serial communications interface (SCI) parity.
Definition: sci.c:698
SCI_SCIFFRX_INTCLR_BITS
#define SCI_SCIFFRX_INTCLR_BITS
Defines the location of the RXFFINT CLR bits in the SCIFFRX register.
Definition: sci.h:184
SCI_enableTxInt
void SCI_enableTxInt(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) transmit interrupt.
Definition: sci.c:453
_SCI_Obj_::SCIRXBUF
volatile uint16_t SCIRXBUF
SCI Receive Data Buffer Register.
Definition: sci.h:358
SCI_putDataNonBlocking
uint16_t SCI_putDataNonBlocking(SCI_Handle sciHandle, uint16_t data)
Writes data to the serial communications interface (Non-Blocking)
Definition: sci.c:558
SCI_SCICCR_MODE_BITS
#define SCI_SCICCR_MODE_BITS
Defines the location of the ADDR/IDLE MODE bits in the SCICCR register.
Definition: sci.h:84
SCI_resetRxFifo
void SCI_resetRxFifo(SCI_Handle sciHandle)
Resets the serial communications interface (SCI) receive FIFO.
Definition: sci.c:600
SCI_getRxFifoStatus
SCI_FifoStatus_e SCI_getRxFifoStatus(SCI_Handle sciHandle)
Gets the serial communications interface (SCI) receive FIFO status.
Definition: sci.c:504
SCI_SCIFFTX_CHAN_RESET_BITS
#define SCI_SCIFFTX_CHAN_RESET_BITS
Defines the location of the SCIRST bits in the SCIFFTX register.
Definition: sci.h:237
SCI_disableTxWake
void SCI_disableTxWake(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) wakeup method.
Definition: sci.c:261
SCI_enableChannels
void SCI_enableChannels(SCI_Handle sciHandle)
Enable the serial communications interface (SCI) transmit and receive channels.
Definition: sci.c:297
_SCI_Obj_::SCIHBAUD
volatile uint16_t SCIHBAUD
SCI Baud Register, High Bits.
Definition: sci.h:353
SCI_disableTxFifoEnh
void SCI_disableTxFifoEnh(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) transmit FIFO enhancements.
Definition: sci.c:225
SCI_disableSleep
void SCI_disableSleep(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) sleep mode.
Definition: sci.c:201
SCI_Mode_e
SCI_Mode_e
Enumeration to define the serial communications interface (SCI) multiprocessor protocol mode...
Definition: sci.h:288
SCI_SCICTL1_TXENA_BITS
#define SCI_SCICTL1_TXENA_BITS
Defines the location of the TXENA bits in the SCICTL1 register.
Definition: sci.h:109
SCI_getTxFifoStatus
SCI_FifoStatus_e SCI_getTxFifoStatus(SCI_Handle sciHandle)
Gets the serial communications interface (SCI) transmit FIFO status.
Definition: sci.c:516
SCI_putDataBlocking
void SCI_putDataBlocking(SCI_Handle sciHandle, uint16_t data)
Writes data to the serial communications interface (Blocking)
Definition: sci.c:543
SCI_SCICTL1_RX_ERR_INT_ENA_BITS
#define SCI_SCICTL1_RX_ERR_INT_ENA_BITS
Defines the location of the RX ERR INT ENA bits in the SCICTL1 register.
Definition: sci.h:125
SCI_clearTxFifoInt
void SCI_clearTxFifoInt(SCI_Handle sciHandle)
Clears the Tx FIFO interrupt flag.
Definition: sci.c:93
SCI_disableTxInt
void SCI_disableTxInt(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) transmit interrupt.
Definition: sci.c:249
_SCI_Obj_::SCIFFRX
volatile uint16_t SCIFFRX
SCI FIFO Receive Register.
Definition: sci.h:362
SCI_enableRx
void SCI_enableRx(SCI_Handle sciHandle)
Enables the serial peripheral interface (SCI) receiver.
Definition: sci.c:333
SCI_disableRx
void SCI_disableRx(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) master/slave receive mode.
Definition: sci.c:153
SCI_Parity_e
SCI_Parity_e
Enumeration to define the serial communications interface (SCI) parity.
Definition: sci.h:306
_SCI_Obj_::SCIFFCT
volatile uint16_t SCIFFCT
SCI FIFO Control Register.
Definition: sci.h:363
SCI_BaudRate_e
SCI_BaudRate_e
Enumeration to define the serial communications interface (SCI) baud rates. This enumeration assume a...
Definition: sci.h:262
SCI_SCICCR_CHAR_LENGTH_BITS
#define SCI_SCICCR_CHAR_LENGTH_BITS
Defines the location of the SCICHAR2-0 bits in the SCICCR register.
Definition: sci.h:80
_SCI_Obj_::SCICCR
volatile uint16_t SCICCR
SCI Configuration Control Register.
Definition: sci.h:351
SCI_SCICTL2_RX_INT_ENA_BITS
#define SCI_SCICTL2_RX_INT_ENA_BITS
Defines the location of the RX/BK INT ENA bits in the SCICTL2 register.
Definition: sci.h:134
SCI_SCICTL2_TX_INT_ENA_BITS
#define SCI_SCICTL2_TX_INT_ENA_BITS
Defines the location of the TX INT ENA bits in the SCICTL2 register.
Definition: sci.h:130
SCI_enableRxErrorInt
void SCI_enableRxErrorInt(SCI_Handle sciHandle)
Enables the serial communications interface (SCI) receive error interrupt.
Definition: sci.c:345
SCI_SCIFFRX_FIFO_OVFCLR_BITS
#define SCI_SCIFFRX_FIFO_OVFCLR_BITS
Defines the location of the RXFFOVF CLR bits in the SCIFFRX register.
Definition: sci.h:200
SCI_disableTxFifoInt
void SCI_disableTxFifoInt(SCI_Handle sciHandle)
Disables the serial communications interface (SCI) transmit FIFO interrupt.
Definition: sci.c:237
SCI_SCIFFTX_FIFO_ENA_BITS
#define SCI_SCIFFTX_FIFO_ENA_BITS
Defines the location of the SCIFFENA bits in the SCIFFTX register.
Definition: sci.h:233
SCI_setTxFifoIntLevel
void SCI_setTxFifoIntLevel(SCI_Handle sciHandle, const SCI_FifoLevel_e fifoLevel)
Sets the serial communications interface (SCI) transmit FIFO level for generating an interrupt...
Definition: sci.c:741
SCI_clearRxFifoInt
void SCI_clearRxFifoInt(SCI_Handle sciHandle)
Clears the Rx FIFO interrupt flag.
Definition: sci.c:81
_SCI_Obj_::SCILBAUD
volatile uint16_t SCILBAUD
SCI Baud Register, Low Bits.
Definition: sci.h:354
SCI_init
SCI_Handle SCI_init(void *pMemory, const size_t numBytes)
Initializes the serial communications interface (SCI) object handle.
Definition: sci.c:528
SCI_SCICTL1_TXWAKE_BITS
#define SCI_SCICTL1_TXWAKE_BITS
Defines the location of the TXWAKE bits in the SCICTL1 register.
Definition: sci.h:117
SCI_resetChannels
void SCI_resetChannels(SCI_Handle sciHandle)
Resets the serial communications interface (SCI) transmit and receive channels.
Definition: sci.c:586