MotorWare f2806x Driver API Documentation

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Data Structures | Macros | Typedefs | Enumerations | Functions
PLL

## Data Structures
struct | _PLL_Obj_
| Defines the phase lock loop (PLL) object. More...

## Macros
#define | PLL_BASE_ADDR (0x00007011)
| Defines the base address of the phase lock loop (PLL) registers. More...
#define | PLL_PLLCR_DIV_BITS (15 << 0)
| Defines the location of the DIV bits in the PLLCR register. More...
#define | PLL_PLLSTS_PLLLOCKS_BITS (1 << 0)
| Defines the location of the PLLLOCKS bits in the PLLSTS register. More...
#define | PLL_PLLSTS_PLLOFF_BITS (1 << 2)
| Defines the location of the PLLOFF bits in the PLLSTS register. More...
#define | PLL_PLLSTS_MCLKSTS_BITS (1 << 3)
| Defines the location of the MCLKSTS bits in the PLLSTS register. More...
#define | PLL_PLLSTS_MCLKCLR_BITS (1 << 4)
| Defines the location of the MCLKCLR bits in the PLLSTS register. More...
#define | PLL_PLLSTS_OSCOFF_BITS (1 << 5)
| Defines the location of the OSCOFF bits in the PLLSTS register. More...
#define | PLL_PLLSTS_MCLKOFF_BITS (1 << 6)
| Defines the location of the MCLKOFF bits in the PLLSTS register. More...
#define | PLL_PLLSTS_DIVSEL_BITS (3 << 7)
| Defines the location of the DIVSEL bits in the PLLSTS register. More...
#define | PLL_PLLSTS_NORMRDYE_BITS (1 << 15)
| Defines the location of the NORMRDYE bits in the PLLSTS register. More...

## Typedefs
typedef struct _PLL_Obj_ | PLL_Obj
| Defines the phase lock loop (PLL) object. More...
typedef struct _PLL_Obj_ * | PLL_Handle
| Defines the phase lock loop (PLL) handle. More...

## Enumerations
enum | PLL_ClkFreq_e { PLL_ClkFreq_5_MHz =(1 << 0), PLL_ClkFreq_10_MHz =(2 << 0), PLL_ClkFreq_15_MHz =(3 << 0), PLL_ClkFreq_20_MHz =(4 << 0), PLL_ClkFreq_25_MHz =(5 << 0), PLL_ClkFreq_30_MHz =(6 << 0), PLL_ClkFreq_35_MHz =(7 << 0), PLL_ClkFreq_40_MHz =(8 << 0), PLL_ClkFreq_45_MHz =(9 << 0), PLL_ClkFreq_50_MHz =(10 << 0), PLL_ClkFreq_55_MHz =(11 << 0), PLL_ClkFreq_60_MHz =(12 << 0), PLL_ClkFreq_65_MHz =(13 << 0), PLL_ClkFreq_70_MHz =(14 << 0), PLL_ClkFreq_75_MHz =(15 << 0), PLL_ClkFreq_80_MHz =(16 << 0), PLL_ClkFreq_85_MHz =(17 << 0), PLL_ClkFreq_90_MHz =(18 << 0) }
| Enumeration to define the phase lock loop (PLL) clock frequency. More...
enum | PLL_DivideSelect_e { PLL_DivideSelect_ClkIn_by_4 =(0 << 7), PLL_DivideSelect_ClkIn_by_2 =(2 << 7), PLL_DivideSelect_ClkIn_by_1 =(3 << 7) }
| Enumeration to define the phase lock loop (PLL) divide select. More...
enum | PLL_ClkStatus_e { PLL_ClkStatus_Normal =(0 << 3), PLL_ClkStatus_Missing =(1 << 3) }
| Enumeration to define the phase lock loop (PLL) clock status. More...
enum | PLL_LockStatus_e { PLL_LockStatus_Locking =(0 << 0), PLL_LockStatus_Done =(1 << 0) }
| Enumeration to define the phase lock loop (PLL) clock lock status. More...

## Functions
void | PLL_disable (PLL_Handle pllHandle)
| Disables the phase lock loop (PLL) More...
void | PLL_disableClkDetect (PLL_Handle pllHandle)
| Disables the clock detect logic. More...
void | PLL_disableNormRdy (PLL_Handle pllHandle)
| Disables the NORMRDY signal. More...
void | PLL_disableOsc (PLL_Handle pllHandle)
| Disables the oscillator. More...
void | PLL_enable (PLL_Handle pllHandle)
| Enables the phase lock loop (PLL) More...
void | PLL_enableClkDetect (PLL_Handle pllHandle)
| Enables the clock detect logic. More...
void | PLL_enableNormRdy (PLL_Handle pllHandle)
| Enables the NORMRDY signal. More...
void | PLL_enableOsc (PLL_Handle pllHandle)
| Enables the oscillator. More...
PLL_ClkFreq_e | PLL_getClkFreq (PLL_Handle pllHandle)
| Gets the phase lock loop (PLL) clock frequency. More...
PLL_ClkStatus_e | PLL_getClkStatus (PLL_Handle pllHandle)
| Gets the phase lock loop (PLL) clock status. More...
PLL_DivideSelect_e | PLL_getDivideSelect (PLL_Handle pllHandle)
| Gets the phase lock loop (PLL) divide select value. More...
PLL_LockStatus_e | PLL_getLockStatus (PLL_Handle pllHandle)
| Gets the phase lock loop (PLL) lock status. More...
PLL_Handle | PLL_init (void *pMemory, const size_t numBytes)
| Initializes the phase lock loop (PLL) object handle. More...
void | PLL_resetClkDetect (PLL_Handle pllHandle)
| Resets the phase lock loop (PLL) clock detect logic. More...
void | PLL_setClkFreq (PLL_Handle pllHandle, const PLL_ClkFreq_e freq)
| Sets the phase lock loop (PLL) clock frequency. More...
void | PLL_setDivideSelect (PLL_Handle pllHandle, const PLL_DivideSelect_e divSelect)
| Sets the phase lock loop (PLL) divide select value. More...
void | PLL_setLockPeriod (PLL_Handle pllHandle, const uint16_t lockPeriod)
| Sets the phase lock loop (PLL) lock time. More...

## Detailed Description

## Data Structure Documentation

struct _PLL_Obj_

Defines the phase lock loop (PLL) object.

Definition at line 169 of file pll.h.

Data Fields
volatile uint16_t | PLLCR | PLL Control Register.
volatile uint16_t | PLLLOCKPRD | PLL Lock Period Register.
volatile uint16_t | PLLSTS | PLL Status Register.
volatile uint16_t | rsvd_1 | Reserved.
volatile uint16_t | rsvd_2[13] | Reserved.

## Macro Definition Documentation

#define PLL_BASE_ADDR (0x00007011)

Defines the base address of the phase lock loop (PLL) registers.

Definition at line 69 of file pll.h.

#define PLL_PLLCR_DIV_BITS (15 << 0)

Defines the location of the DIV bits in the PLLCR register.

Definition at line 74 of file pll.h.

Referenced by PLL_getClkFreq().

#define PLL_PLLSTS_DIVSEL_BITS (3 << 7)

Defines the location of the DIVSEL bits in the PLLSTS register.

Definition at line 103 of file pll.h.

Referenced by PLL_getDivideSelect(), and PLL_setDivideSelect().

#define PLL_PLLSTS_MCLKCLR_BITS (1 << 4)

Defines the location of the MCLKCLR bits in the PLLSTS register.

Definition at line 91 of file pll.h.

Referenced by PLL_resetClkDetect().

#define PLL_PLLSTS_MCLKOFF_BITS (1 << 6)

Defines the location of the MCLKOFF bits in the PLLSTS register.

Definition at line 99 of file pll.h.

Referenced by PLL_disableClkDetect(), and PLL_enableClkDetect().

#define PLL_PLLSTS_MCLKSTS_BITS (1 << 3)

Defines the location of the MCLKSTS bits in the PLLSTS register.

Definition at line 87 of file pll.h.

Referenced by PLL_getClkStatus().

#define PLL_PLLSTS_NORMRDYE_BITS (1 << 15)

Defines the location of the NORMRDYE bits in the PLLSTS register.

Definition at line 107 of file pll.h.

Referenced by PLL_disableNormRdy(), and PLL_enableNormRdy().

#define PLL_PLLSTS_OSCOFF_BITS (1 << 5)

Defines the location of the OSCOFF bits in the PLLSTS register.

Definition at line 95 of file pll.h.

Referenced by PLL_disableOsc(), and PLL_enableOsc().

#define PLL_PLLSTS_PLLLOCKS_BITS (1 << 0)

Defines the location of the PLLLOCKS bits in the PLLSTS register.

Definition at line 79 of file pll.h.

Referenced by PLL_getLockStatus().

#define PLL_PLLSTS_PLLOFF_BITS (1 << 2)

Defines the location of the PLLOFF bits in the PLLSTS register.

Definition at line 83 of file pll.h.

Referenced by PLL_disable(), and PLL_enable().

## Typedef Documentation

typedef struct _PLL_Obj_* PLL_Handle

Defines the phase lock loop (PLL) handle.

Definition at line 181 of file pll.h.

typedef struct _PLL_Obj_ PLL_Obj

Defines the phase lock loop (PLL) object.

## Enumeration Type Documentation

enum PLL_ClkFreq_e

Enumeration to define the phase lock loop (PLL) clock frequency.

Enumerator
PLL_ClkFreq_5_MHz | Denotes a clock frequency of 5 MHz.
PLL_ClkFreq_10_MHz | Denotes a clock frequency of 10 MHz.
PLL_ClkFreq_15_MHz | Denotes a clock frequency of 15 MHz.
PLL_ClkFreq_20_MHz | Denotes a clock frequency of 20 MHz.
PLL_ClkFreq_25_MHz | Denotes a clock frequency of 25 MHz.
PLL_ClkFreq_30_MHz | Denotes a clock frequency of 30 MHz.
PLL_ClkFreq_35_MHz | Denotes a clock frequency of 35 MHz.
PLL_ClkFreq_40_MHz | Denotes a clock frequency of 40 MHz.
PLL_ClkFreq_45_MHz | Denotes a clock frequency of 45 MHz.
PLL_ClkFreq_50_MHz | Denotes a clock frequency of 50 MHz.
PLL_ClkFreq_55_MHz | Denotes a clock frequency of 55 MHz.
PLL_ClkFreq_60_MHz | Denotes a clock frequency of 60 MHz.
PLL_ClkFreq_65_MHz | Denotes a clock frequency of 65 MHz.
PLL_ClkFreq_70_MHz | Denotes a clock frequency of 70 MHz.
PLL_ClkFreq_75_MHz | Denotes a clock frequency of 75 MHz.
PLL_ClkFreq_80_MHz | Denotes a clock frequency of 80 MHz.
PLL_ClkFreq_85_MHz | Denotes a clock frequency of 85 MHz.
PLL_ClkFreq_90_MHz | Denotes a clock frequency of 90 MHz.

Definition at line 116 of file pll.h.

enum PLL_ClkStatus_e

Enumeration to define the phase lock loop (PLL) clock status.

Enumerator
PLL_ClkStatus_Normal | Denotes a normal clock.
PLL_ClkStatus_Missing | Denotes a missing clock.

Definition at line 151 of file pll.h.

enum PLL_DivideSelect_e

Enumeration to define the phase lock loop (PLL) divide select.

Enumerator
PLL_DivideSelect_ClkIn_by_4 | Denotes a divide select of CLKIN/4.
PLL_DivideSelect_ClkIn_by_2 | Denotes a divide select of CLKIN/2.
PLL_DivideSelect_ClkIn_by_1 | Denotes a divide select of CLKIN/1.

Definition at line 141 of file pll.h.

enum PLL_LockStatus_e

Enumeration to define the phase lock loop (PLL) clock lock status.

Enumerator
PLL_LockStatus_Locking | Denotes that the system is locking to the clock.
PLL_LockStatus_Done | Denotes that the system is locked to the clock.

Definition at line 160 of file pll.h.

## Function Documentation

void PLL_disable | ( | PLL_Handle | pllHandle | ) |

Disables the phase lock loop (PLL)

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 57 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_PLLOFF_BITS, and _PLL_Obj_::PLLSTS.

void PLL_disableClkDetect | ( | PLL_Handle | pllHandle | ) |

Disables the clock detect logic.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 73 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_MCLKOFF_BITS, and _PLL_Obj_::PLLSTS.

void PLL_disableNormRdy | ( | PLL_Handle | pllHandle | ) |

Disables the NORMRDY signal.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 89 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_NORMRDYE_BITS, and _PLL_Obj_::PLLSTS.

void PLL_disableOsc | ( | PLL_Handle | pllHandle | ) |

Disables the oscillator.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 105 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_OSCOFF_BITS, and _PLL_Obj_::PLLSTS.

void PLL_enable | ( | PLL_Handle | pllHandle | ) |

Enables the phase lock loop (PLL)

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 121 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_PLLOFF_BITS, and _PLL_Obj_::PLLSTS.

void PLL_enableClkDetect | ( | PLL_Handle | pllHandle | ) |

Enables the clock detect logic.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 137 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_MCLKOFF_BITS, and _PLL_Obj_::PLLSTS.

void PLL_enableNormRdy | ( | PLL_Handle | pllHandle | ) |

Enables the NORMRDY signal.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 153 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_NORMRDYE_BITS, and _PLL_Obj_::PLLSTS.

void PLL_enableOsc | ( | PLL_Handle | pllHandle | ) |

Enables the oscillator.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 169 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_OSCOFF_BITS, and _PLL_Obj_::PLLSTS.

PLL_ClkFreq_e PLL_getClkFreq | ( | PLL_Handle | pllHandle | ) |

Gets the phase lock loop (PLL) clock frequency.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Returns
  The clock frequency

Definition at line 185 of file pll.c.

References PLL_PLLCR_DIV_BITS, and _PLL_Obj_::PLLCR.

PLL_ClkStatus_e PLL_getClkStatus | ( | PLL_Handle | pllHandle | ) |

Gets the phase lock loop (PLL) clock status.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Returns
  The clock status

Definition at line 197 of file pll.c.

References PLL_PLLSTS_MCLKSTS_BITS, and _PLL_Obj_::PLLSTS.

PLL_DivideSelect_e PLL_getDivideSelect | ( | PLL_Handle | pllHandle | ) |

Gets the phase lock loop (PLL) divide select value.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Returns
  The divide select value

Definition at line 208 of file pll.c.

References PLL_PLLSTS_DIVSEL_BITS, and _PLL_Obj_::PLLSTS.

PLL_LockStatus_e PLL_getLockStatus | ( | PLL_Handle | pllHandle | ) |

Gets the phase lock loop (PLL) lock status.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Returns
  The lock status

Definition at line 219 of file pll.c.

References PLL_PLLSTS_PLLLOCKS_BITS, and _PLL_Obj_::PLLSTS.

PLL_Handle PLL_init | ( | void * | pMemory,
|  | const size_t | numBytes
| ) |  |

Initializes the phase lock loop (PLL) object handle.

Parameters

  [in] | pMemory | A pointer to the base address of the PLL registers
  [in] | numBytes | The number of bytes allocated for the PLL object, bytes

Returns
  The phase lock loop (PLL) object handle

Definition at line 231 of file pll.c.

void PLL_resetClkDetect | ( | PLL_Handle | pllHandle | ) |

Resets the phase lock loop (PLL) clock detect logic.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle

Definition at line 246 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_MCLKCLR_BITS, and _PLL_Obj_::PLLSTS.

void PLL_setClkFreq | ( | PLL_Handle | pllHandle,
|  | const PLL_ClkFreq_e | freq
| ) |  |

Sets the phase lock loop (PLL) clock frequency.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle
  [in] | freq | The clock frequency

Definition at line 262 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, and _PLL_Obj_::PLLCR.

void PLL_setDivideSelect | ( | PLL_Handle | pllHandle,
|  | const PLL_DivideSelect_e | divSelect
| ) |  |

Sets the phase lock loop (PLL) divide select value.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle
  [in] | divSelect | The divide select value

Definition at line 278 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, PLL_PLLSTS_DIVSEL_BITS, and _PLL_Obj_::PLLSTS.

void PLL_setLockPeriod | ( | PLL_Handle | pllHandle,
|  | const uint16_t | lockPeriod
| ) |  |

Sets the phase lock loop (PLL) lock time.

Parameters

  [in] | pllHandle | The phase lock loop (PLL) object handle
  [in] | lockPeriod | The lock period, cycles

Definition at line 297 of file pll.c.

References DISABLE_PROTECTED_REGISTER_WRITE_MODE, ENABLE_PROTECTED_REGISTER_WRITE_MODE, and _PLL_Obj_::PLLLOCKPRD.