|
MotorWare f2806x Driver API Documentation
|
Contains public interface to various functions related to the central processing unit (CPU) object. More...
#include "sw/modules/types/src/types.h"Go to the source code of this file.
Data Structures | |
| struct | _CPU_Obj_ |
| Defines the central processing unit (CPU) object. More... | |
Macros | |
| #define | EINT asm(" clrc INTM") |
| Define to enable interrupts (legacy) More... | |
| #define | ENABLE_INTERRUPTS asm(" clrc INTM") |
| Define to enable interrupts. More... | |
| #define | DINT asm(" setc INTM") |
| Define to disable interrupts (legacy) More... | |
| #define | DISABLE_INTERRUPTS asm(" setc INTM") |
| Define to disable interrupts. More... | |
| #define | ERTM asm(" clrc DBGM") |
| Define to enable debug events. More... | |
| #define | DRTM asm(" setc DBGM") |
| Define to disable debug events. More... | |
| #define | EALLOW asm(" EALLOW") |
| Define to allow protected register writes (legacy) More... | |
| #define | ENABLE_PROTECTED_REGISTER_WRITE_MODE asm(" EALLOW") |
| Define to allow protected register writes. More... | |
| #define | EDIS asm(" EDIS") |
| Define to disable protected register writes (legacy) More... | |
| #define | DISABLE_PROTECTED_REGISTER_WRITE_MODE asm(" EDIS") |
| Define to disable protected register writes. More... | |
| #define | ESTOP0 asm(" ESTOP0") |
| Define for emulation stop 0. More... | |
| #define | IDLE asm(" IDLE") |
| Define for entering IDLE mode. More... | |
| #define | CPU_IER_INT1_BITS (1 << 0) |
| Defines the location of the INT1 bits in the IER register. More... | |
| #define | CPU_IER_INT2_BITS (1 << 1) |
| Defines the location of the INT2 bits in the IER register. More... | |
| #define | CPU_IER_INT3_BITS (1 << 2) |
| Defines the location of the INT3 bits in the IER register. More... | |
| #define | CPU_IER_INT4_BITS (1 << 3) |
| Defines the location of the INT4 bits in the IER register. More... | |
| #define | CPU_IER_INT5_BITS (1 << 4) |
| Defines the location of the INT5 bits in the IER register. More... | |
| #define | CPU_IER_INT6_BITS (1 << 5) |
| Defines the location of the INT6 bits in the IER register. More... | |
| #define | CPU_IER_INT7_BITS (1 << 6) |
| Defines the location of the INT7 bits in the IER register. More... | |
| #define | CPU_IER_INT8_BITS (1 << 7) |
| Defines the location of the INT8 bits in the IER register. More... | |
| #define | CPU_IER_INT9_BITS (1 << 8) |
| Defines the location of the INT9 bits in the IER register. More... | |
| #define | CPU_IER_INT10_BITS (1 << 9) |
| Defines the location of the INT10 bits in the IER register. More... | |
| #define | CPU_IER_INT11_BITS (1 << 10) |
| Defines the location of the INT11 bits in the IER register. More... | |
| #define | CPU_IER_INT12_BITS (1 << 11) |
| Defines the location of the INT12 bits in the IER register. More... | |
| #define | CPU_IER_INT13_BITS (1 << 12) |
| Defines the location of the INT13 bits in the IER register. More... | |
| #define | CPU_IER_INT14_BITS (1 << 13) |
| Defines the location of the INT14 bits in the IER register. More... | |
| #define | CPU_IER_DLOGINT_BITS (1 << 14) |
| Defines the location of the DLOGINT bits in the IER register. More... | |
| #define | CPU_IER_RTOSINT_BITS (1 << 15) |
| Defines the location of the RTOSINT bits in the IER register. More... | |
| #define | CPU_IFR_INT1_BITS (1 << 0) |
| Defines the location of the INT1 bits in the IER register. More... | |
| #define | CPU_IFR_INT2_BITS (1 << 1) |
| Defines the location of the INT2 bits in the IER register. More... | |
| #define | CPU_IFR_INT3_BITS (1 << 2) |
| Defines the location of the INT3 bits in the IER register. More... | |
| #define | CPU_IFR_INT4_BITS (1 << 3) |
| Defines the location of the INT4 bits in the IER register. More... | |
| #define | CPU_IFR_INT5_BITS (1 << 4) |
| Defines the location of the INT5 bits in the IER register. More... | |
| #define | CPU_IFR_INT6_BITS (1 << 5) |
| Defines the location of the INT6 bits in the IER register. More... | |
| #define | CPU_IFR_INT7_BITS (1 << 6) |
| Defines the location of the INT7 bits in the IER register. More... | |
| #define | CPU_IFR_INT8_BITS (1 << 7) |
| Defines the location of the INT8 bits in the IER register. More... | |
| #define | CPU_IFR_INT9_BITS (1 << 8) |
| Defines the location of the INT9 bits in the IER register. More... | |
| #define | CPU_IFR_INT10_BITS (1 << 9) |
| Defines the location of the INT10 bits in the IER register. More... | |
| #define | CPU_IFR_INT11_BITS (1 << 10) |
| Defines the location of the INT11 bits in the IER register. More... | |
| #define | CPU_IFR_INT12_BITS (1 << 11) |
| Defines the location of the INT12 bits in the IER register. More... | |
| #define | CPU_IFR_INT13_BITS (1 << 12) |
| Defines the location of the INT13 bits in the IER register. More... | |
| #define | CPU_IFR_INT14_BITS (1 << 13) |
| Defines the location of the INT14 bits in the IER register. More... | |
| #define | CPU_IFR_DLOGINT_BITS (1 << 14) |
| Defines the location of the DLOGINT bits in the IFR register. More... | |
| #define | CPU_IFR_RTOSINT_BITS (1 << 15) |
| Defines the location of the RTOSINT bits in the IFR register. More... | |
| #define | CPU_DBGIER_INT1_BITS (1 << 0) |
| Defines the location of the INT1 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT2_BITS (1 << 1) |
| Defines the location of the INT2 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT3_BITS (1 << 2) |
| Defines the location of the INT3 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT4_BITS (1 << 3) |
| Defines the location of the INT4 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT5_BITS (1 << 4) |
| Defines the location of the INT5 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT6_BITS (1 << 5) |
| Defines the location of the INT6 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT7_BITS (1 << 6) |
| Defines the location of the INT7 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT8_BITS (1 << 7) |
| Defines the location of the INT8 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT9_BITS (1 << 8) |
| Defines the location of the INT9 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT10_BITS (1 << 9) |
| Defines the location of the INT10 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT11_BITS (1 << 10) |
| Defines the location of the INT11 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT12_BITS (1 << 11) |
| Defines the location of the INT12 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT13_BITS (1 << 12) |
| Defines the location of the INT13 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_INT14_BITS (1 << 13) |
| Defines the location of the INT14 bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_DLOGINT_BITS (1 << 14) |
| Defines the location of the DLOGINT bits in the DBGIER register. More... | |
| #define | CPU_DBGIER_RTOSINT_BITS (1 << 15) |
| Defines the location of the RTOSINT bits in the DBGIER register. More... | |
| #define | CPU_ST0_SXM_BITS (1 << 0) |
| Defines the location of the SXM bits in the ST0 register. More... | |
| #define | CPU_ST0_OVM_BITS (1 << 1) |
| Defines the location of the OVM bits in the ST0 register. More... | |
| #define | CPU_ST0_TC_BITS (1 << 2) |
| Defines the location of the T bits in the ST0 register. More... | |
| #define | CPU_ST0_C_BITS (1 << 3) |
| Defines the location of the C bits in the ST0 register. More... | |
| #define | CPU_ST0_Z_BITS (1 << 4) |
| Defines the location of the Z bits in the ST0 register. More... | |
| #define | CPU_ST0_N_BITS (1 << 5) |
| Defines the location of the N bits in the ST0 register. More... | |
| #define | CPU_ST0_V_BITS (1 << 6) |
| Defines the location of the V bits in the ST0 register. More... | |
| #define | CPU_ST0_PW_BITS (7 << 7) |
| Defines the location of the PW bits in the ST0 register. More... | |
| #define | CPU_ST0_OVCOVCU_BITS (63 << 10) |
| Defines the location of the OVCOVCU bits in the ST0 register. More... | |
| #define | CPU_ST1_INTM_BITS (1 << 0) |
| Defines the location of the INTM bits in the ST1 register. More... | |
| #define | CPU_ST1_DBGM_BITS (1 << 1) |
| Defines the location of the DBGM bits in the ST1 register. More... | |
| #define | CPU_ST1_PAGE0_BITS (1 << 2) |
| Defines the location of the PAGE0 bits in the ST1 register. More... | |
| #define | CPU_ST1_VMAP_BITS (1 << 3) |
| Defines the location of the VMAP bits in the ST1 register. More... | |
| #define | CPU_ST1_SPA_BITS (1 << 4) |
| Defines the location of the SPA bits in the ST1 register. More... | |
| #define | CPU_ST1_LOOP_BITS (1 << 5) |
| Defines the location of the LOOP bits in the ST1 register. More... | |
| #define | CPU_ST1_EALLOW_BITS (1 << 6) |
| Defines the location of the EALLOW bits in the ST1 register. More... | |
| #define | CPU_ST1_IDLESTAT_BITS (1 << 7) |
| Defines the location of the IDLESTAT bits in the ST1 register. More... | |
| #define | CPU_ST1_AMODE_BITS (1 << 8) |
| Defines the location of the AMODE bits in the ST1 register. More... | |
| #define | CPU_ST1_OBJMODE_BITS (1 << 9) |
| Defines the location of the OBJMODE bits in the ST1 register. More... | |
| #define | CPU_ST1_MOM1MAP_BITS (1 << 11) |
| Defines the location of the MOM1MAP bits in the ST1 register. More... | |
| #define | CPU_ST1_XF_BITS (1 << 12) |
| Defines the location of the XF bits in the ST1 register. More... | |
| #define | CPU_ST1_ARP_BITS (7 << 13) |
| Defines the location of the ARP bits in the ST1 register. More... | |
Typedefs | |
| typedef struct _CPU_Obj_ | CPU_Obj |
| Defines the central processing unit (CPU) object. More... | |
| typedef struct _CPU_Obj_ * | CPU_Handle |
| Defines the central processing unit (CPU) handle. More... | |
Enumerations | |
| enum | CPU_ExtIntNumber_e { CPU_ExtIntNumber_1 =0, CPU_ExtIntNumber_2, CPU_ExtIntNumber_3 } |
| Enumeration to define the external interrupt numbers. More... | |
| enum | CPU_IntNumber_e { CPU_IntNumber_1 =(1 << 0), CPU_IntNumber_2 =(1 << 1), CPU_IntNumber_3 =(1 << 2), CPU_IntNumber_4 =(1 << 3), CPU_IntNumber_5 =(1 << 4), CPU_IntNumber_6 =(1 << 5), CPU_IntNumber_7 =(1 << 6), CPU_IntNumber_8 =(1 << 7), CPU_IntNumber_9 =(1 << 8), CPU_IntNumber_10 =(1 << 9), CPU_IntNumber_11 =(1 << 10), CPU_IntNumber_12 =(1 << 11), CPU_IntNumber_13 =(1 << 12), CPU_IntNumber_14 =(1 << 13) } |
| Enumeration to define the interrupt numbers. More... | |
Functions | |
| void | CPU_clearIntFlags (CPU_Handle cpuHandle) |
| Clears all interrupt flags. More... | |
| void | CPU_disableDebugInt (CPU_Handle cpuHandle) |
| Disables the debug interrupt. More... | |
| void | CPU_disableGlobalInts (CPU_Handle cpuHandle) |
| Disables global interrupts. More... | |
| void | CPU_disableInt (CPU_Handle cpuHandle, const CPU_IntNumber_e intNumber) |
| Disables a specified interrupt number. More... | |
| void | CPU_disableInts (CPU_Handle cpuHandle) |
| Disables all interrupts. More... | |
| void | CPU_disableProtectedRegisterWrite (CPU_Handle cpuHandle) |
| Disables protected register writes. More... | |
| void | CPU_enableDebugInt (CPU_Handle cpuHandle) |
| Enables the debug interrupt. More... | |
| void | CPU_enableGlobalInts (CPU_Handle cpuHandle) |
| Enables global interrupts. More... | |
| void | CPU_enableInt (CPU_Handle cpuHandle, const CPU_IntNumber_e intNumber) |
| Enables a specified interrupt number. More... | |
| void | CPU_enableProtectedRegisterWrite (CPU_Handle cpuHandle) |
| Enables protected register writes. More... | |
| CPU_Handle | CPU_init (void *pMemory, const size_t numBytes) |
| Initializes the central processing unit (CPU) object handle. More... | |
Variables | |
| CPU_Obj | cpu |
| Defines the CPU object. More... | |
| cregister volatile unsigned int | IFR |
| External reference to the interrupt flag register (IFR) register. More... | |
| cregister volatile unsigned int | IER |
| External reference to the interrupt enable register (IER) register. More... | |
Contains public interface to various functions related to the central processing unit (CPU) object.
(C) Copyright 2015, Texas Instruments, Inc.
Definition in file cpu.h.
1.8.9.1