45 #include "sw/modules/types/src/types.h"
65 #define EINT asm(" clrc INTM")
69 #define ENABLE_INTERRUPTS asm(" clrc INTM")
73 #define DINT asm(" setc INTM")
77 #define DISABLE_INTERRUPTS asm(" setc INTM")
81 #define ERTM asm(" clrc DBGM")
85 #define DRTM asm(" setc DBGM")
89 #define EALLOW asm(" EALLOW")
93 #define ENABLE_PROTECTED_REGISTER_WRITE_MODE asm(" EALLOW")
97 #define EDIS asm(" EDIS")
101 #define DISABLE_PROTECTED_REGISTER_WRITE_MODE asm(" EDIS")
105 #define ESTOP0 asm(" ESTOP0")
109 #define IDLE asm(" IDLE")
113 #define CPU_IER_INT1_BITS (1 << 0)
117 #define CPU_IER_INT2_BITS (1 << 1)
121 #define CPU_IER_INT3_BITS (1 << 2)
125 #define CPU_IER_INT4_BITS (1 << 3)
129 #define CPU_IER_INT5_BITS (1 << 4)
133 #define CPU_IER_INT6_BITS (1 << 5)
137 #define CPU_IER_INT7_BITS (1 << 6)
141 #define CPU_IER_INT8_BITS (1 << 7)
145 #define CPU_IER_INT9_BITS (1 << 8)
149 #define CPU_IER_INT10_BITS (1 << 9)
153 #define CPU_IER_INT11_BITS (1 << 10)
157 #define CPU_IER_INT12_BITS (1 << 11)
161 #define CPU_IER_INT13_BITS (1 << 12)
165 #define CPU_IER_INT14_BITS (1 << 13)
169 #define CPU_IER_DLOGINT_BITS (1 << 14)
173 #define CPU_IER_RTOSINT_BITS (1 << 15)
179 #define CPU_IFR_INT1_BITS (1 << 0)
183 #define CPU_IFR_INT2_BITS (1 << 1)
187 #define CPU_IFR_INT3_BITS (1 << 2)
191 #define CPU_IFR_INT4_BITS (1 << 3)
195 #define CPU_IFR_INT5_BITS (1 << 4)
199 #define CPU_IFR_INT6_BITS (1 << 5)
203 #define CPU_IFR_INT7_BITS (1 << 6)
207 #define CPU_IFR_INT8_BITS (1 << 7)
211 #define CPU_IFR_INT9_BITS (1 << 8)
215 #define CPU_IFR_INT10_BITS (1 << 9)
219 #define CPU_IFR_INT11_BITS (1 << 10)
223 #define CPU_IFR_INT12_BITS (1 << 11)
227 #define CPU_IFR_INT13_BITS (1 << 12)
231 #define CPU_IFR_INT14_BITS (1 << 13)
235 #define CPU_IFR_DLOGINT_BITS (1 << 14)
239 #define CPU_IFR_RTOSINT_BITS (1 << 15)
244 #define CPU_DBGIER_INT1_BITS (1 << 0)
248 #define CPU_DBGIER_INT2_BITS (1 << 1)
252 #define CPU_DBGIER_INT3_BITS (1 << 2)
256 #define CPU_DBGIER_INT4_BITS (1 << 3)
260 #define CPU_DBGIER_INT5_BITS (1 << 4)
264 #define CPU_DBGIER_INT6_BITS (1 << 5)
268 #define CPU_DBGIER_INT7_BITS (1 << 6)
272 #define CPU_DBGIER_INT8_BITS (1 << 7)
276 #define CPU_DBGIER_INT9_BITS (1 << 8)
280 #define CPU_DBGIER_INT10_BITS (1 << 9)
284 #define CPU_DBGIER_INT11_BITS (1 << 10)
288 #define CPU_DBGIER_INT12_BITS (1 << 11)
292 #define CPU_DBGIER_INT13_BITS (1 << 12)
296 #define CPU_DBGIER_INT14_BITS (1 << 13)
300 #define CPU_DBGIER_DLOGINT_BITS (1 << 14)
304 #define CPU_DBGIER_RTOSINT_BITS (1 << 15)
310 #define CPU_ST0_SXM_BITS (1 << 0)
314 #define CPU_ST0_OVM_BITS (1 << 1)
318 #define CPU_ST0_TC_BITS (1 << 2)
322 #define CPU_ST0_C_BITS (1 << 3)
326 #define CPU_ST0_Z_BITS (1 << 4)
330 #define CPU_ST0_N_BITS (1 << 5)
334 #define CPU_ST0_V_BITS (1 << 6)
338 #define CPU_ST0_PW_BITS (7 << 7)
342 #define CPU_ST0_OVCOVCU_BITS (63 << 10)
348 #define CPU_ST1_INTM_BITS (1 << 0)
352 #define CPU_ST1_DBGM_BITS (1 << 1)
356 #define CPU_ST1_PAGE0_BITS (1 << 2)
360 #define CPU_ST1_VMAP_BITS (1 << 3)
364 #define CPU_ST1_SPA_BITS (1 << 4)
368 #define CPU_ST1_LOOP_BITS (1 << 5)
372 #define CPU_ST1_EALLOW_BITS (1 << 6)
376 #define CPU_ST1_IDLESTAT_BITS (1 << 7)
380 #define CPU_ST1_AMODE_BITS (1 << 8)
384 #define CPU_ST1_OBJMODE_BITS (1 << 9)
388 #define CPU_ST1_MOM1MAP_BITS (1 << 11)
392 #define CPU_ST1_XF_BITS (1 << 12)
396 #define CPU_ST1_ARP_BITS (7 << 13)
457 extern cregister
volatile unsigned int IFR;
462 extern cregister
volatile unsigned int IER;
524 extern CPU_Handle
CPU_init(
void *pMemory,
const size_t numBytes);
532 #endif // end of __CPU_H__ definition
struct _CPU_Obj_ CPU_Obj
Defines the central processing unit (CPU) object.
void CPU_clearIntFlags(CPU_Handle cpuHandle)
Clears all interrupt flags.
Denotes interrupt number 6.
Denotes interrupt number 3.
Denotes interrupt number 13.
void CPU_enableGlobalInts(CPU_Handle cpuHandle)
Enables global interrupts.
uint_least8_t tmp
a filler value for the object
Defines the central processing unit (CPU) object.
CPU_Handle CPU_init(void *pMemory, const size_t numBytes)
Initializes the central processing unit (CPU) object handle.
void CPU_disableProtectedRegisterWrite(CPU_Handle cpuHandle)
Disables protected register writes.
CPU_Obj cpu
Defines the CPU object.
void CPU_enableDebugInt(CPU_Handle cpuHandle)
Enables the debug interrupt.
CPU_IntNumber_e
Enumeration to define the interrupt numbers.
void CPU_disableInt(CPU_Handle cpuHandle, const CPU_IntNumber_e intNumber)
Disables a specified interrupt number.
Denotes interrupt number 14.
Denotes interrupt number 1.
cregister volatile unsigned int IER
External reference to the interrupt enable register (IER) register.
Denotes interrupt number 2.
Denotes interrupt number 5.
cregister volatile unsigned int IFR
External reference to the interrupt flag register (IFR) register.
Denotes external interrupt number 1.
Denotes interrupt number 9.
void CPU_disableGlobalInts(CPU_Handle cpuHandle)
Disables global interrupts.
struct _CPU_Obj_ * CPU_Handle
Defines the central processing unit (CPU) handle.
Denotes interrupt number 8.
Denotes interrupt number 10.
Denotes external interrupt number 3.
void CPU_enableInt(CPU_Handle cpuHandle, const CPU_IntNumber_e intNumber)
Enables a specified interrupt number.
Denotes interrupt number 11.
CPU_ExtIntNumber_e
Enumeration to define the external interrupt numbers.
void CPU_enableProtectedRegisterWrite(CPU_Handle cpuHandle)
Enables protected register writes.
void CPU_disableInts(CPU_Handle cpuHandle)
Disables all interrupts.
Denotes external interrupt number 2.
Denotes interrupt number 12.
void CPU_disableDebugInt(CPU_Handle cpuHandle)
Disables the debug interrupt.
Denotes interrupt number 7.
Denotes interrupt number 4.