drv8301.h

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/* --COPYRIGHT--,BSD
 * Copyright (c) 2015, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * --/COPYRIGHT--*/
#ifndef _DRV8301_H_
#define _DRV8301_H_



// **************************************************************************
// the includes

// drivers
#include "sw/drivers/spi/src/32b/f28x/f2806x/spi.h"
#include "sw/drivers/gpio/src/32b/f28x/f2806x/gpio.h"

// modules

// solutions






#ifdef __cplusplus
extern "C" {
#endif


// **************************************************************************
// the defines

#define DRV8301_ADDR_MASK               (0x7800)


#define DRV8301_DATA_MASK               (0x07FF)


#define DRV8301_RW_MASK                 (0x8000)


#define DRV8301_FAULT_TYPE_MASK         (0x07FF)


#define DRV8301_STATUS1_FETLC_OC_BITS   (1 << 0)

#define DRV8301_STATUS1_FETHC_OC_BITS   (1 << 1)

#define DRV8301_STATUS1_FETLB_OC_BITS   (1 << 2)

#define DRV8301_STATUS1_FETHB_OC_BITS   (1 << 3)

#define DRV8301_STATUS1_FETLA_OC_BITS   (1 << 4)

#define DRV8301_STATUS1_FETHA_OC_BITS   (1 << 5)

#define DRV8301_STATUS1_OTW_BITS        (1 << 6)

#define DRV8301_STATUS1_OTSD_BITS       (1 << 7)

#define DRV8301_STATUS1_PVDD_UV_BITS    (1 << 8)

#define DRV8301_STATUS1_GVDD_UV_BITS    (1 << 9)

#define DRV8301_STATUS1_FAULT_BITS      (1 << 10)


#define DRV8301_STATUS2_ID_BITS        (15 << 0)

#define DRV8301_STATUS2_GVDD_OV_BITS    (1 << 7)


#define DRV8301_CTRL1_GATE_CURRENT_BITS  (3 << 0)

#define DRV8301_CTRL1_GATE_RESET_BITS    (1 << 2)

#define DRV8301_CTRL1_PWM_MODE_BITS      (1 << 3)

#define DRV8301_CTRL1_OC_MODE_BITS       (3 << 4)

#define DRV8301_CTRL1_OC_ADJ_SET_BITS   (31 << 6)


#define DRV8301_CTRL2_OCTW_SET_BITS      (3 << 0)

#define DRV8301_CTRL2_GAIN_BITS          (3 << 2)

#define DRV8301_CTRL2_DC_CAL_1_BITS      (1 << 4)

#define DRV8301_CTRL2_DC_CAL_2_BITS      (1 << 5)

#define DRV8301_CTRL2_OC_TOFF_BITS       (1 << 6)


// **************************************************************************
// the typedefs

typedef enum 
{
  DRV8301_CtrlMode_Read = 1 << 15,   
  DRV8301_CtrlMode_Write = 0 << 15   
} DRV8301_CtrlMode_e;


typedef enum 
{
  DRV8301_DcCalMode_Ch1_Load   = (0 << 4),   
  DRV8301_DcCalMode_Ch1_NoLoad = (1 << 4),   
  DRV8301_DcCalMode_Ch2_Load   = (0 << 5),   
  DRV8301_DcCalMode_Ch2_NoLoad = (1 << 5)    
} DRV8301_DcCalMode_e;


typedef enum 
{
  DRV8301_FaultType_NoFault  = (0 << 0),  
  DRV8301_FaultType_FETLC_OC = (1 << 0),  
  DRV8301_FaultType_FETHC_OC = (1 << 1),  
  DRV8301_FaultType_FETLB_OC = (1 << 2),  
  DRV8301_FaultType_FETHB_OC = (1 << 3),  
  DRV8301_FaultType_FETLA_OC = (1 << 4),  
  DRV8301_FaultType_FETHA_OC = (1 << 5),  
  DRV8301_FaultType_OTW      = (1 << 6),  
  DRV8301_FaultType_OTSD     = (1 << 7),  
  DRV8301_FaultType_PVDD_UV  = (1 << 8),  
  DRV8301_FaultType_GVDD_UV  = (1 << 9),  
  DRV8301_FaultType_GVDD_OV  = (1 << 10)  
} DRV8301_FaultType_e;


typedef enum 
{
  DRV8301_OcMode_CurrentLimit  = 0 << 4,   
  DRV8301_OcMode_LatchShutDown = 1 << 4,   
  DRV8301_OcMode_ReportOnly    = 2 << 4,   
  DRV8301_OcMode_Disabled      = 3 << 4    
} DRV8301_OcMode_e;


typedef enum 
{
  DRV8301_OcOffTimeMode_Normal  = 0 << 6,   
  DRV8301_OcOffTimeMode_Ctrl    = 1 << 6    
} DRV8301_OcOffTimeMode_e;


typedef enum 
{
  DRV8301_OcTwMode_Both    = 0 << 0,   
  DRV8301_OcTwMode_OT_Only = 1 << 0,   
  DRV8301_OcTwMode_OC_Only = 2 << 0    
} DRV8301_OcTwMode_e;


typedef enum 
{
  DRV8301_PeakCurrent_1p70_A  = 0 << 0,   
  DRV8301_PeakCurrent_0p70_A  = 1 << 0,   
  DRV8301_PeakCurrent_0p25_A  = 2 << 0    
} DRV8301_PeakCurrent_e;


typedef enum 
{
  DRV8301_PwmMode_Six_Inputs   = 0 << 3,   
  DRV8301_PwmMode_Three_Inputs = 1 << 3    
} DRV8301_PwmMode_e;


typedef enum 
{
  DRV8301_RegName_Status_1  = 0 << 11,   
  DRV8301_RegName_Status_2  = 1 << 11,   
  DRV8301_RegName_Control_1 = 2 << 11,  
  DRV8301_RegName_Control_2 = 3 << 11   
} DRV8301_RegName_e;



typedef enum 
{
  DRV8301_Reset_Normal = 0 << 2,   
  DRV8301_Reset_All = 1 << 2       
} DRV8301_Reset_e;


typedef enum 
{
  DRV8301_ShuntAmpGain_10VpV = 0 << 2,   
  DRV8301_ShuntAmpGain_20VpV = 1 << 2,   
  DRV8301_ShuntAmpGain_40VpV = 2 << 2,   
  DRV8301_ShuntAmpGain_80VpV = 3 << 2    
} DRV8301_ShuntAmpGain_e;


typedef enum 
{
  DRV8301_ShuntAmpNumber_1 = 1,      
  DRV8301_ShuntAmpNumber_2 = 2       
} DRV8301_ShuntAmpNumber_e;


typedef enum 
{
  DRV8301_VdsLevel_0p060_V =  0 << 6,      
  DRV8301_VdsLevel_0p068_V =  1 << 6,      
  DRV8301_VdsLevel_0p076_V =  2 << 6,      
  DRV8301_VdsLevel_0p086_V =  3 << 6,      
  DRV8301_VdsLevel_0p097_V =  4 << 6,      
  DRV8301_VdsLevel_0p109_V =  5 << 6,      
  DRV8301_VdsLevel_0p123_V =  6 << 6,      
  DRV8301_VdsLevel_0p138_V =  7 << 6,      
  DRV8301_VdsLevel_0p155_V =  8 << 6,      
  DRV8301_VdsLevel_0p175_V =  9 << 6,      
  DRV8301_VdsLevel_0p197_V = 10 << 6,      
  DRV8301_VdsLevel_0p222_V = 11 << 6,      
  DRV8301_VdsLevel_0p250_V = 12 << 6,      
  DRV8301_VdsLevel_0p282_V = 13 << 6,      
  DRV8301_VdsLevel_0p317_V = 14 << 6,      
  DRV8301_VdsLevel_0p358_V = 15 << 6,      
  DRV8301_VdsLevel_0p403_V = 16 << 6,      
  DRV8301_VdsLevel_0p454_V = 17 << 6,      
  DRV8301_VdsLevel_0p511_V = 18 << 6,      
  DRV8301_VdsLevel_0p576_V = 19 << 6,      
  DRV8301_VdsLevel_0p648_V = 20 << 6,      
  DRV8301_VdsLevel_0p730_V = 21 << 6,      
  DRV8301_VdsLevel_0p822_V = 22 << 6,      
  DRV8301_VdsLevel_0p926_V = 23 << 6,      
  DRV8301_VdsLevel_1p043_V = 24 << 6,      
  DRV8301_VdsLevel_1p175_V = 25 << 6,      
  DRV8301_VdsLevel_1p324_V = 26 << 6,      
  DRV8301_VdsLevel_1p491_V = 27 << 6,      
  DRV8301_VdsLevel_1p679_V = 28 << 6,      
  DRV8301_VdsLevel_1p892_V = 29 << 6,      
  DRV8301_VdsLevel_2p131_V = 30 << 6,      
  DRV8301_VdsLevel_2p400_V = 31 << 6       
} DRV8301_VdsLevel_e;


typedef enum
{
  DRV8301_GETID=0
} Drv8301SpiOutputDataSelect_e;


typedef struct _DRV_SPI_8301_Stat1_t_
{
  bool                  FAULT;
  bool                  GVDD_UV;
  bool                  PVDD_UV;
  bool                  OTSD;
  bool                  OTW;
  bool                  FETHA_OC;
  bool                  FETLA_OC;
  bool                  FETHB_OC;
  bool                  FETLB_OC;
  bool                  FETHC_OC;
  bool                  FETLC_OC;
}DRV_SPI_8301_Stat1_t_;


typedef struct _DRV_SPI_8301_Stat2_t_
{
  bool                  GVDD_OV;
  uint16_t              DeviceID;
}DRV_SPI_8301_Stat2_t_;


typedef struct _DRV_SPI_8301_CTRL1_t_
{
  DRV8301_PeakCurrent_e    DRV8301_CURRENT;
  DRV8301_Reset_e          DRV8301_RESET;
  DRV8301_PwmMode_e        PWM_MODE;
  DRV8301_OcMode_e         OC_MODE;
  DRV8301_VdsLevel_e       OC_ADJ_SET;
}DRV_SPI_8301_CTRL1_t_;


typedef struct _DRV_SPI_8301_CTRL2_t_
{
  DRV8301_OcTwMode_e       OCTW_SET;
  DRV8301_ShuntAmpGain_e   GAIN;
  DRV8301_DcCalMode_e      DC_CAL_CH1p2;
  DRV8301_OcOffTimeMode_e  OC_TOFF;
}DRV_SPI_8301_CTRL2_t_;


typedef struct _DRV_SPI_8301_Vars_t_
{
  DRV_SPI_8301_Stat1_t_     Stat_Reg_1;
  DRV_SPI_8301_Stat2_t_     Stat_Reg_2;
  DRV_SPI_8301_CTRL1_t_     Ctrl_Reg_1;
  DRV_SPI_8301_CTRL2_t_     Ctrl_Reg_2;
  bool                  SndCmd;
  bool                  RcvCmd;
}DRV_SPI_8301_Vars_t;


typedef struct _DRV8301_Obj_
{
  SPI_Handle       spiHandle;                  
  GPIO_Handle      gpioHandle;                 
  GPIO_Number_e    gpioNumber;                 
  bool             RxTimeOut;                  
  bool             enableTimeOut;              
} DRV8301_Obj;


typedef struct _DRV8301_Obj_ *DRV8301_Handle;


typedef  uint16_t    DRV8301_Word_t;


// **************************************************************************
// the globals



// **************************************************************************
// the function prototypes


static inline DRV8301_Word_t DRV8301_buildCtrlWord(const DRV8301_CtrlMode_e ctrlMode,
                                                   const DRV8301_RegName_e regName,
                                                   const uint16_t data)
{
  DRV8301_Word_t ctrlWord = ctrlMode | regName | (data & DRV8301_DATA_MASK);

  return(ctrlWord);
} // end of DRV8301_buildCtrlWord() function


extern DRV8301_DcCalMode_e DRV8301_getDcCalMode(DRV8301_Handle handle,
                                                const DRV8301_ShuntAmpNumber_e ampNumber);

extern void DRV8301_enable(DRV8301_Handle handle);


extern DRV8301_FaultType_e DRV8301_getFaultType(DRV8301_Handle handle);


extern uint16_t DRV8301_getId(DRV8301_Handle handle);


extern DRV8301_VdsLevel_e DRV8301_getOcLevel(DRV8301_Handle handle);


extern DRV8301_OcMode_e DRV8301_getOcMode(DRV8301_Handle handle);


extern DRV8301_OcOffTimeMode_e DRV8301_getOcOffTimeMode(DRV8301_Handle handle);


extern DRV8301_OcTwMode_e DRV8301_getOcTwMode(DRV8301_Handle handle);


extern DRV8301_PeakCurrent_e DRV8301_getPeakCurrent(DRV8301_Handle handle);


extern DRV8301_PwmMode_e DRV8301_getPwmMode(DRV8301_Handle handle);


extern DRV8301_ShuntAmpGain_e DRV8301_getShuntAmpGain(DRV8301_Handle handle);


extern uint16_t DRV8301_getStatusRegister1(DRV8301_Handle handle);


extern uint16_t DRV8301_getStatusRegister2(DRV8301_Handle handle);


extern DRV8301_Handle DRV8301_init(void *pMemory,const size_t numBytes);


extern bool DRV8301_isFault(DRV8301_Handle handle);


extern bool DRV8301_isReset(DRV8301_Handle handle);


extern uint16_t DRV8301_readSpi(DRV8301_Handle handle,const DRV8301_RegName_e regName);


extern void DRV8301_reset(DRV8301_Handle handle);


static inline void DRV8301_resetEnableTimeout(DRV8301_Handle handle)
{
  DRV8301_Obj *obj = (DRV8301_Obj *)handle;

  obj->enableTimeOut = false;

  return;
}


static inline void DRV8301_resetRxTimeout(DRV8301_Handle handle)
{
  DRV8301_Obj *obj = (DRV8301_Obj *)handle;

  obj->RxTimeOut = false;

  return;
}


extern void DRV8301_setDcCalMode(DRV8301_Handle handle,
                                 const DRV8301_ShuntAmpNumber_e ampNumber,
                                 const DRV8301_DcCalMode_e mode);


void DRV8301_setGpioHandle(DRV8301_Handle handle,GPIO_Handle gpioHandle);


void DRV8301_setGpioNumber(DRV8301_Handle handle,GPIO_Number_e gpioNumber);


extern void DRV8301_setOcLevel(DRV8301_Handle handle,const DRV8301_VdsLevel_e VdsLevel);


extern void DRV8301_setOcMode(DRV8301_Handle handle,const DRV8301_OcMode_e mode);


extern void DRV8301_setOcOffTimeMode(DRV8301_Handle handle,const DRV8301_OcOffTimeMode_e mode);


extern void DRV8301_setOcTwMode(DRV8301_Handle handle,const DRV8301_OcTwMode_e mode);


extern void DRV8301_setPeakCurrent(DRV8301_Handle handle,const DRV8301_PeakCurrent_e peakCurrent);


extern void DRV8301_setPwmMode(DRV8301_Handle handle,const DRV8301_PwmMode_e mode);


extern void DRV8301_setShuntAmpGain(DRV8301_Handle handle,const DRV8301_ShuntAmpGain_e gain);


void DRV8301_setSpiHandle(DRV8301_Handle handle,SPI_Handle spiHandle);


extern void DRV8301_writeSpi(DRV8301_Handle handle,const DRV8301_RegName_e regName,const uint16_t data);


extern void DRV8301_writeData(DRV8301_Handle handle, DRV_SPI_8301_Vars_t *Spi_8301_Vars);


extern void DRV8301_readData(DRV8301_Handle handle, DRV_SPI_8301_Vars_t *Spi_8301_Vars);


extern void DRV8301_setupSpi(DRV8301_Handle handle, DRV_SPI_8301_Vars_t *Spi_8301_Vars);


#ifdef __cplusplus
}
#endif // extern "C"


#endif // end of _DRV8301_H_ definition