Uint16 Index_Cnt=0; 
Uint16 Tx_Total_len = 0,Tx_lenCnt = 0; 
volatile Uint8 RxtestFlag = 0;
Uint16 RxTESTLen = 0;
Uint16 lentest = 0,lentestPre = 0;
#pragma DATA_SECTION(gbyUsart1RxBuffer,"RS485flash_buffer");
Uint8 gbyUsart1RxBuffer[256];//USART RX buffer
#pragma DATA_SECTION(COM1_RxBuff,"RS485flash_buffer");
Uint8 COM1_RxBuff[256] = {0};
Uint8 gbyAckMirrorGroupBuffer[152];//TX 
__interrupt void cpu_timer1_isr(void)//Timer 1 100 us
{
   CpuTimer1.InterruptCount++;
   Usart1_TxEndDelay();//
   if((CpuTimer1.InterruptCount %2) == 0)
   {
   if(IsUartTxEnd())UsartDataGet();//get data from FIFO
     }
   // The CPU acknowledges the interrupt.
   EDIS;
}
 
void USARTB_CpuIntEn(void)//FIFO RX interrupt config
{
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;    // Enable the PIE block
    PieCtrlRegs.PIEIER9.bit.INTx3=1;      // PIE Group 9, INT1
#if TX_INT_EN  > 0
    PieCtrlRegs.PIEIER9.bit.INTx4=1;      // PIE Group 9, INT2
#endif
    IER |= M_INT9; // Enable CPU INT
    EINT;   //Enable interrupt
}
 
void scib_echoback_init(void)//SCIB initiate
{
    // Note: Clocks were turned on to the SCIA peripheral
    // in the InitSysCtrl() function
  USARTB_IntHandlerConfig();
  ScibRegs.SCICCR.all =0x0007;   // 1 stop bit,  No loopback
                                   // No parity,8 char bits,
                                   // async mode, idle-line protocol
  ScibRegs.SCICTL1.all =0x0003;  // enable TX, RX, internal SCICLK,RX ERR
                                   // Disable , SLEEP, TXWAKE
  ScibRegs.SCICTL2.bit.TXINTENA =0; //Disable 
  ScibRegs.SCIHBAUD    =0x0000;  // 115200 baud @LSPCLK = 22.5MHz (90 MHz SYSCLK).22500000/((BAUD+1)*8)=115200
  ScibRegs.SCILBAUD    =0x0018;//0x0018;22500000/((BAUD+1)*8)=115200
  ScibRegs.SCICTL1.all =0x0023;  // Relinquish SCI from Reset
  scib_fifo_init();
  USARTB_CpuIntEn(); //Enable PIE
}
 
void scib_fifo_init(void)//SCI——RX FIFO initiate
{
ScibRegs.SCIFFTX.all=0xE040;//0xE040; //Close FIFO init 
ScibRegs.SCIFFRX.all=0x0022; //FIFO depth is 4?
ScibRegs.SCIFFCT.all=0x01;//0x01;
ScibRegs.SCICTL1.all =0x0063;     //SCI exit reset status
ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
}
 
void UsartDataGet(void)//get data from Usart
{
   Uint16 js;
   lentest = ScibRegs.SCIFFRX.bit.RXFFST;
   if(((Index_Cnt+lentest) >0) && ( RxtestFlag != 1) &&(lentestPre == (Index_Cnt+lentest)))
   {
     for(js = 0; js < lentest; js ++)
     { // Read RXFFST data
       COM1_RxBuff[Index_Cnt] = (ScibRegs.SCIRXBUF.all & 0x00FF);//ScibRegs.SCIRXBUF.all;
       gbyUsart1RxBuffer[Index_Cnt] = COM1_RxBuff[Index_Cnt];
       Index_Cnt ++;
     }
     RxTESTLen = Index_Cnt;
     Index_Cnt = 0;
     RxtestFlag = 1;
     ScibRegs.SCIFFRX.all=0x0022;//0x0024; //FIFO depth is 4
     ScibRegs.SCIFFCT.all=0x01;//0x01;
     ScibRegs.SCICTL1.all =0x0003;     //SCI exit reset
     ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
   }
   else
   {
   }
   lentestPre = Index_Cnt+lentest;
}
 
__interrupt void USARTB_RxIntHandler(void)//FIFO Rx overflow interrupt
{
Uint16 icnt = 0;
    Uint16 llen;
if(ScibRegs.SCIRXST.bit.RXERROR == 1)
    {
      llen = ScibRegs.SCIFFRX.bit.RXFFST;
     for(icnt = 0; icnt < llen; icnt ++)
     { //read RXFFST data
         COM1_RxBuff[Index_Cnt] = (ScibRegs.SCIRXBUF.all & 0x00FF);//ScibRegs.SCIRXBUF.bit.RXDT;//ScibRegs.SCIRXBUF.all;
         gbyUsart1RxBuffer[Index_Cnt] = COM1_RxBuff[Index_Cnt];
         Index_Cnt ++;
      }
       ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
       ScibRegs.SCICTL1.all =0x0003;     //SCI exit reset
      ScibRegs.SCICTL1.all =0x0063;     //SCI exit reset
      UARTERRCnt ++;
}
else
{
  llen = ScibRegs.SCIFFRX.bit.RXFFST;
  for(icnt = 0; icnt < llen; icnt ++)
  { //read RXFFST data
     COM1_RxBuff[Index_Cnt] = (ScibRegs.SCIRXBUF.all & 0x00FF);//ScibRegs.SCIRXBUF.bit.RXDT;//ScibRegs.SCIRXBUF.all;
     gbyUsart1RxBuffer[Index_Cnt] = COM1_RxBuff[Index_Cnt];
     Index_Cnt ++;
  }
}
    ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // 
    ScibRegs.SCIFFRX.bit.RXFFINTCLR=1;   //
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;
}
 

#if TX_INT_EN > 0
__interrupt void USARTB_TxIntHandler(void)
{
u16 Tx_length = 0;
u16 Tii = 0;
Tx_length = Tx_Total_len - Tx_lenCnt;
if((Tx_length > 0) && (Tx_length < 152) && (!IsUartTxEnd()))
{
       if(Tx_length >=2)
       {
         for(Tii =0;Tii<2;Tii++)
         {
          ScibRegs.SCITXBUF= (gbyAckMirrorGroupBuffer[Tx_lenCnt] & 0x00FF);
          Tx_lenCnt ++;
         }
       }
       else
       {
        for(Tii =0;Tii<Tx_length;Tii++)
         {
                 ScibRegs.SCITXBUF= (gbyAckMirrorGroupBuffer[Tx_lenCnt] & 0x00FF);
                 Tx_lenCnt ++;
         }
       }
             ScibRegs.SCIFFTX.bit.TXFFINTCLR =1; // Clear SCI init flag
}
else
{
if(ScibRegs.SCICTL2.bit.TXEMPTY == 1)
{
gbyUsart1TxEndDelay = 5;
ScibRegs.SCIFFTX.bit.TXFFIENA =0;
ScibRegs.SCICTL2.bit.TXINTENA =0; //enable Tx init*/
}
 else
 {
  }
}
ScibRegs.SCIFFTX.bit.TXFFINTCLR =1; // clear SCI init flag
PieCtrlRegs.PIEACK.bit.ACK9 = 1;        // Issue PIE ack
}
#endif
 
void ComMirrorGroup_Send(u8 *pbyData, u16 wLength)
{
USART_TXEN;
USART_DEN_TXEN;
Tx_Total_len = wLength;
Tx_lenCnt = 0;
ScibRegs.SCICTL1.all =0x0003;//0x0003;
ScibRegs.SCIFFTX.bit.TXFFST = 0;
ScibRegs.SCIFFTX.bit.TXFFINTCLR = 0;
ScibRegs.SCIFFTX.bit.TXFFIL = 2;
ScibRegs.SCIFFCT.all=0x00;
//SCI exit reset
ScibRegs.SCICTL2.bit.TXINTENA =0; //enable tx init
ScibRegs.SCIFFTX.bit.TXFFINTCLR = 1;
ScibRegs.SCICTL1.bit.SWRESET =1;     //SCI exit reset
while (ScibRegs.SCICTL2.bit.TXRDY == 0)
{ //wait until flag to be 1 if SCITXBUF is not ready to receive new data
;
}
ScibRegs.SCIFFTX.bit.TXFIFOXRESET=0;
ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;
ScibRegs.SCIFFRX.bit.RXFIFORESET=0;
ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
while (ScibRegs.SCICTL2.bit.TXRDY == 0)
{ //wait until flag to be 1 if SCITXBUF is not ready to receive new data
;
}
ScibRegs.SCIFFTX.bit.SCIFFENA = 1;
ScibRegs.SCIFFTX.bit.TXFFIENA =1;
}
 
Main loop:
while(1)
{
    if(RxtestFlag )
   {
         USART_DEN_TXEN;
         USART_TXEN;
      Memcpy(gbyAckMirrorGroupBuffer,gbyUsart1RxBuffer,RxTESTLen );
      RxtestFlag  = 0;
      ComMirrorGroup_Send(gbyAckMirrorGroupBuffer,RxTESTLen ) ;
   }
}
 
/*tx end delay*/
void Usart1_TxEndDelay(void)
{
    if( gbyUsart1TxEndDelay > 0)
    {
        gbyUsart1TxEndDelay--;
        if(gbyUsart1TxEndDelay == 1)
        {
         USART_DEN_RXEN;
         USART_RXEN;
         Inc_ComMirrorGroupTxPkt(); //record tx package error rate
        }
        if(gbyUsart1TxEndDelay == 0)
        {
         Scib_Rx_Init();//
        }
    }
}
void Scib_Rx_Init(void)
{
gbyUsart1TxEndDelay = 0;
gbUsart1TxEndFlag = SET;
RxtestFlag = 0;
    USART_DEN_RXEN;
    USART_RXEN;
    Tx_Total_len = 0;
    Tx_lenCnt = 0;
    ScibRegs.SCICTL2.bit.TXINTENA =0; //enable tx init
    ScibRegs.SCIFFTX.bit.TXFFIENA =0;
    ScibRegs.SCIFFTX.bit.SCIFFENA = 1;
ScibRegs.SCIFFCT.all=0x01;//0x01;
ScibRegs.SCIFFRX.bit.RXFIFORESET=1;
ScibRegs.SCICTL1.all =0x0003;     //SCI exit reset
ScibRegs.SCICTL1.all =0x0063;     //SCI exit reset
ScibRegs.SCIFFTX.bit.TXFFIL = 0;
ScibRegs.SCIFFRX.bit.RXFFIL = 2;
ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 1;
ScibRegs.SCIFFRX.bit.RXFFINTCLR = 0;
ScibRegs.SCIFFRX.bit.RXFFIENA = 1;
}