// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   /* BEGIN           	: origin = 0x080000, length = 0x000002 */
   BEGIN             : origin = 0x082000, length = 0x000002
   RAMM0           	: origin = 0x000123,   length = 0x0002DD
   RAMD0           	: origin = 0x00B000,   length = 0x000800
   RAMLS0          	: origin = 0x008000,   length = 0x000800
   RAMLS1          	: origin = 0x008800,   length = 0x000800   
   /* RAMLS4      	   : origin = 0x00A000, length = 0x000800 */
   /* RAMLS5           : origin = 0x00A800, length = 0x000800 */
   RAMLS4_5         : origin = 0x00A000,   length = 0x001000
   
   // RAMGS14          : origin = 0x01A000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   // RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   // RAMGS14_15         : origin = 0x01A000,   length = 0x001FF8
   RAMGS14_1           : origin = 0x01A000,   length = 0x0003FF
   RAMGS14_2__15       : origin = 0x01A400,   length = 0x001BF0

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0,   length = 0x000002

   /* Flash sectors */
   /* FLASHA           : origin = 0x080002, length = 0x001FFE */	/* on-chip Flash */
   BOOTLOADER       : origin = 0x080000, length = 0x002000  /* on-chip Flash, occupied by the bootlaoder */
   /* FLASHB           : origin = 0x082000, length = 0x002000 */  /* on-chip Flash */
   FLASHB           : origin = 0x082002, length = 0x001FFE	/* on-chip Flash */
   FLASHC           : origin = 0x084000,   length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000,   length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000,   length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000,   length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000,   length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000,   length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000,   length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000,   length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000,   length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000,   length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000,   length = 0x002000	/* on-chip Flash */
   //FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */
   FLASHN1           : origin = 0x0BE000, length = 0x003FF	/* on-chip Flash */
   FLASHN2           : origin = 0x0BE400, length = 0x001BF0	/* on-chip Flash */

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : 

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMLS2      		: origin = 0x009000,   length = 0x000800
   RAMLS3      		: origin = 0x009800,   length = 0x000800

   RAMGS0           : origin = 0x00C000,   length = 0x001000
   RAMGS1           : origin = 0x00D000,   length = 0x001000
   //RAMGS2           : origin = 0x00E000,   length = 0x001000
   //RAMGS3           : origin = 0x00F000,   length = 0x001000
   RAMGS2_3         : origin = 0x00E000,   length = 0x002000
   RAMGS4           : origin = 0x010000,   length = 0x001000
   RAMGS5           : origin = 0x011000,   length = 0x001000
   RAMGS6           : origin = 0x012000,   length = 0x001000
   RAMGS7           : origin = 0x013000,   length = 0x001000
   RAMGS8           : origin = 0x014000,   length = 0x001000
   RAMGS9           : origin = 0x015000,   length = 0x001000
   RAMGS10          : origin = 0x016000,   length = 0x001000

//   RAMGS11          : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD     : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11          : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13          : origin = 0x019000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   EMIF1_CS0n       : origin = 0x80000000, length = 0x10000000
   EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000
   EMIF1_CS3n       : origin = 0x00300000, length = 0x00080000
   EMIF1_CS4n       : origin = 0x00380000, length = 0x00060000
   EMIF2_CS0n       : origin = 0x90000000, length = 0x10000000
   EMIF2_CS2n       : origin = 0x00002000, length = 0x00001000

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
   
  
   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit           : > FLASHB | FLASHC,     PAGE = 0, ALIGN(8)
   .text            : >> FLASHE | FLASHF | FLASHG | FLASHH | FLASHI | FLASHJ,      PAGE = 0, ALIGN(8)
   codestart        : > BEGIN       PAGE = 0, ALIGN(8)
   .stack           : > RAMM1       PAGE = 1
   .switch          : > FLASHB | FLASHC     PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
 #if defined(__TI_EABI__)
   .init_array         : > FLASHB | FLASHC,       PAGE = 0, ALIGN(8)
   .bss                : > RAMLS2 | RAMLS3,       PAGE = 1
   .bss:output         : > RAMLS2 | RAMLS3,       PAGE = 1
   .data               : > RAMLS2 | RAMLS3,       PAGE = 1
   .sysmem             : > RAMLS2 | RAMLS3,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHK | FLASHL | FLASHM,       PAGE = 0, ALIGN(8)
#else
   .pinit              : > FLASHB | FLASHC,       PAGE = 0, ALIGN(8)
   .ebss               : > RAMLS2 | RAMLS3,		 PAGE = 1
   .esysmem            : > RAMLS2 | RAMLS3,       PAGE = 1
   /* Initalized sections go in Flash */
   .econst             : > FLASHK | FLASHL | FLASHM,  	 PAGE = 0, ALIGN(8)
#endif

   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .em2_cs0         : > EMIF2_CS0n, PAGE = 1
   .em2_cs2         : > EMIF2_CS2n, PAGE = 1

//   SHARERAMGS0		: > RAMGS0,		PAGE = 1
//   SHARERAMGS1		: > RAMGS1,		PAGE = 1
//   SHARERAMGS2		: > RAMGS2,		PAGE = 1
//   ramgs0           : > RAMGS0,     PAGE = 1
//   ramgs1           : > RAMGS1,     PAGE = 1
   SHARERAM_CPU1      : > RAMGS2_3 | RAMGS4 |RAMGS5 | RAMGS6 | RAMGS7,		PAGE = 1
   SHARERAM_CPU2      : > RAMGS8 | RAMGS9 | RAMGS10 |RAMGS11 | RAMGS12 | RAMGS13,		PAGE = 1

   RAM_CPU1TOCPU2           : > CPU1TOCPU2RAM,     PAGE = 1
   RAM_CPU2TOCPU1           : > CPU2TOCPU1RAM,     PAGE = 1

/* Digital Controller Library functions */ /*!!!!!!! DCL a remapper si utilisé !!!! */
	dclfuncs		: > RAMLS0,		PAGE = 0
	dcl32funcs		: > RAMLS0,		PAGE = 0

/* CLA specific sections */
   #if defined(__TI_EABI__)
   		Cla1Prog    : LOAD = FLASHD,
                      RUN = RAMLS4_5,
                      LOAD_START(Cla1funcsLoadStart),
                      LOAD_END(Cla1funcsLoadEnd),
                      RUN_START(Cla1funcsRunStart),
                      LOAD_SIZE(Cla1funcsLoadSize),
                      PAGE = 0, ALIGN(8)
   #else
      	Cla1Prog    : LOAD = FLASHD,
                      RUN = RAMLS4_5,
                      LOAD_START(_Cla1funcsLoadStart),
                      LOAD_END(_Cla1funcsLoadEnd),
                      RUN_START(_Cla1funcsRunStart),
                      LOAD_SIZE(_Cla1funcsLoadSize),
                      PAGE = 0, ALIGN(8)
   #endif

   CLADataLS0		: > RAMLS0, PAGE=0
   CLADataLS1		: > RAMLS1, PAGE=0

   Cla1ToCpu1MsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   Cla1ToCpu2MsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   Cpu1ToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
   Cpu2ToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1


					
#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHD,
							 RUN = RAMD0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
        #else
            .TI.ramfunc : {} LOAD = FLASHD,
							 RUN = RAMD0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    #else
   ramfuncs         : LOAD = FLASHD,
                      RUN = RAMD0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
    #endif

#endif

   /* Identification & Trim specific sections */
	GROUP : LOAD = FLASHN1,
            RUN = RAMGS14_1,
            LOAD_START(_IdentLoadStart),
            LOAD_END(_IdentLoadEnd),
            RUN_START(_IdentRunStart),
            LOAD_SIZE(_IdentLoadSize),
            PAGE = 0, ALIGN(8)
	{
		SW_IDENTIFICATION:{} align(8)
		ANALOG_TRIM:{} align(8)
	}

   /* Calibration specific sections */
	GROUP : LOAD = FLASHN2,
            RUN = RAMGS14_2__15,
            LOAD_START(_CalibrationLoadStart),
            LOAD_END(_CalibrationLoadEnd),
            RUN_START(_CalibrationRunStart),
            LOAD_SIZE(_CalibrationLoadSize),
            PAGE = 0, ALIGN(8)
	{
		CALIBRATION_HEADER:{} align(8)
		CALIBRATION:{} align(8)
	}
	
	/* Non Volatile memory specific sections */
	GROUP : > RAMGS0, PAGE = 1, ALIGN(8),
			RUN_START(_NVM_RunStart),
            LOAD_SIZE(_NVM_Size)
	{
		NVM_HEADER:{} align(8)
		NVM:{} align(8)
	}
	//GROUP : > RAMGS1, PAGE = 1, ALIGN(8)
	//{
	//	NVM_CPU2_HEADER:{}
	//	NVM_CPU2:{}
	//}

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

#ifdef CLA_C
   /* CLA C compiler sections */
   //
   // Must be allocated to memory the CLA has write access to
   //
   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 0

   .scratchpad      : > RAMLS1,       PAGE = 0
   .bss_cla		    : > RAMLS1,       PAGE = 0
   .const_cla	    :  LOAD = FLASHB,
                       RUN = RAMLS1,
                       RUN_START(_Cla1ConstRunStart),
                       LOAD_START(_Cla1ConstLoadStart),
                       LOAD_SIZE(_Cla1ConstLoadSize),
                       PAGE = 0
#endif //CLA_C
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/
