In the following example, two 3.3V, 10A modules are to be paralleled.
Nunits is the number of paralleled units
Useful identities
measured crossover frequency of the module.
maximum output current of the module
output voltage of the module
maximum voltage adjustment of the module by way of the remote sense, usually given as a percentage in the module data sheet
VDD input of the UCC39002
Measured internal resistance between VOUT+ and SENSE+, Rsense
Desired maximum power dissipation of the current sense resistor
calculated maximum value of the current sense resistor, Rshunt,
standard resistor value used for current sensing
calculated power dissipation of given sense resistor
voltage drop across sense resistor (make sure it is less than the voltage adjustment range of the module and is much greater than the input voltage offset, 100
although the drop across the current sense resistor is less than the usuable voltage adjustment range, it is a significant portion of it.
Internal resistor at the LS pin
absolute max current sense amplifier output voltage before saturation, the master's Vcsa determines the voltage of the load share bus
The output current of the LS driver is limited to 1mA, this relates to the maximum number of modules, Nunits, to be paralleled to the LS voltage, Nunits_ max:
because VLS is approximately equal to Vcsa this just determines whether the number of modules in parallel exceeds the current capability of the LS driver; so long as Vcso is less than VLSmax than everything is cool.
just keep this in mind for master IC bias current
the absolute allowable current sense gain before saturation, ACSAmax
chosen current sense gain for this design, keeping well below the theoretical maximum calculated above:
Gain set by Rcsa1 (parallel) and Rcsa2 (series)
resultant current sense amplifier output voltage and approximate LS bus voltage
add a "high frequency" pole for noise roll off:
Actual value of Ccsa:
Resultant pole
these compensation components must be on both input terminals of the differential amplifier
First meaure the internal resistance between +Vout and +Sense.
If we consider the voltage differential between +Vout and +Sense to be equal to the voltage adgjustment range of the converter:
and the adjustment range has been limited to:
Solve for Isense
Because this internal resistor is essentially in parallel with the ADJ resistor, the ADJ amplifier current will be the sum of this Isense and IRadj
Internally the adjust pin is clamped to 3.5V and has a 500 Ohm emitter resistor which results in a maximum sink current at the adjust pin (data sheet functional block diagram shows 3V and 500
Because Vadj must be greater than or equal to Veao+1V, in order to keep the BJT on the adj from saturating, Radj must be carefully selected.
Solve for Iadj:
We know that Veao will be approximately equal to:
And the voltage on Vadj is equal to:
And to keep the Adj BJT from saturating:
Substituting leads to:
which leads to:
multiply both sides by Radj:
In order to keep the internal bipolar from saturating, Radj must be greater than or equal to:
So Radj must be greater than or equal to this to fulfill the Vadj-Veao >/= 1V requirement.
the adjust resistor is also sized such that it operates over the available voltage adjustment current range of the module
select Radj such that it is large enough to fulfill the Vadj-Veao is greater than or equal to 1V requirement AND results in an adjust current not greater than the 7mA limitation of the IC.
selected R adj value to meet both requirements
In other words, there are two factors that are dependent: the Iadj and the
BJT is saturating if Vadj-Veao<1V
Now for the bode plots
Based on the given Bode, the loop equation is derived and plotted to match measured plot...
Want the total loop to cross at a decade or more befroe the module's crossover.
The gain of the module at the desired crossover frequency, in V/V:
or calculate from dB as taken from the Bode plot
The gain of the module at the desired crossover frequency, in dB, which can be read directly from the Bode plot
taking the Current sense amp into consideration:
this is the actual gain over frequency but the pole is usually way beyond the module bandwidth and won't be a factor
voltage gain
Adjust amplifier gain
Internal Error amplifier transconductance
open loop gain, converted to dB:
Combining all of the known gains to determine the error amp compensation:
We know that the gain of a transconductance error amplifier is equal to:
Substituting for s:
Assumption for CEAO, should be a relatively large value due to the low frequency requirement:
to get a valid result for Reao, Ceao must be equal to or larger than this
Solving for the magnitude of the resistance:
OR
IS THIS A REAL OR IMAGINARY VALUE?
resultant actual zero frequency
Now Bode the whole thing: