Sl No |
Test ID |
Test Name |
Test Result |
---|
1 |
TEST.PD.USB4.DRST.2 |
TEST.PD.USB4.DRST.2 –Data_Reset command response of UFP UUT, Invalid Sequence |
FAIL |
Test Status |
Test Description |
---|
  |
  |
  |
 COMMON.PROC.BU.2: |
  |
 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk: |
  |
                    SourceCap Packet15 |
  |
                          UUT should respond with request - - COMMON.PROC.BU.2#1: |
  |
                                   Request Packet17 |
  |
 COMMON.PROC.BU.2 - REVISION_3_0 Rev3ChkdSnk: |
  |
                    SourceCap Packet71 |
  |
                          UUT should respond with request - - COMMON.PROC.BU.2#1: |
  |
                                   Request Packet73 |
  |
 Rev3ChkdSnk: |
  |
                          Data_Reset command response check - TEST.PD.USB4.DRST.2#1: |
  |
                                   UUT respond Accept to Data_Reset command at protocol index 39 |
  |
                          Error recovery check - TEST.PD.USB4.DRST.2#3: |
  |
                                   UUT did error recovery at 11.0645 mS after recieving the Get_Sink_Cap |
  |
 Rev3ChkdSnk: |
  |
                          Data_Reset command response check - TEST.PD.USB4.DRST.2#2: |
  |
                                   UUT respond Accept to Data_Reset command at protocol index 95 |
  |
                          Error recovery check - TEST.PD.USB4.DRST.2#4: |
  |
                                   UUT failed to do error recovery |
Index |
   Start time(s.ms.μs.ns) |
   Stop time(s.ms.μs.ns) |
Message Origin |
 Message |
  |
 Secondary Message |
 SOP |
 Port Type |
 Msg ID |
 PDO |
 Header(MSB to LSB) |
 Payload(LSB to MSB) |
---|---|---|---|---|---|---|---|---|---|---|---|
TEST_PD_USB4_DRST_2_Data_Reset_command_response_of_UFP_UUT_Invalid_Sequence |
|||||||||||
Port A Packet Details |
|||||||||||
4 |
747.275320 mS |
747.275320 mS |
T-> |
Ra_Asserted |
NONE |
NONE/NONE/R- |
0 |
Ra_CC2 |
0x0000 |
||
9 |
747.795570 mS |
747.795570 mS |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||
10 |
747.977830 mS |
747.977830 mS |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Disabled -> FSM_State_Unattached_SRC |
0x0000 |
||
11 |
749.495260 mS |
749.495260 mS |
T-> |
Attach |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|
12 |
749.511920 mS |
749.511920 mS |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC |
0x0000 |
||
13 |
899.594470 mS |
899.594470 mS |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC |
0x0000 |
||
15 |
956.271650 mS |
956.869050 mS |
T-> |
SourceCap |
SOP |
DFP/Source/R3 |
0 |
 FS: 5V .1A; |
0x11A1 |
0x0A-0x90-0x01-0x28- |
|
16 |
956.927060 mS |
957.424260 mS |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
0 |
0x0041 |
|||
17 |
961.517300 mS |
962.147110 mS |
<-D |
Request |
SOP |
UFP/Sink/R3 |
0 |
PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A |
0x1082 |
0x00-0x00-0x80-0x13- |
|
18 |
962.191710 mS |
962.661120 mS |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
0 |
0x0121 |
|||
19 |
964.271730 mS |
964.741140 mS |
T-> |
Accept |
SOP |
DFP/Source/R3 |
1 |
0x03A3 |
|||
20 |
964.804940 mS |
965.301940 mS |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
1 |
0x0241 |
|||
21 |
1.287.270.033 |
1.287.739.074 |
T-> |
PS_RDY |
SOP |
DFP/Source/R3 |
2 |
0x05A6 |
|||
22 |
1.287.803.034 |
1.288.300.055 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
2 |
0x0441 |
|||
24 |
1.288.336.090 |
1.288.336.090 |
T-> |
Rp_Asserted |
Rp_4_7k_3A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_4_7k_3A_Asserted |
0x0000 |
|
25 |
1.295.899.003 |
1.296.396.023 |
<-D |
PR_Swap |
SOP |
UFP/Sink/R3 |
1 |
0x028A |
|||
26 |
1.296.441.063 |
1.296.911.004 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
1 |
0x0321 |
|||
27 |
1.298.272.005 |
1.298.741.046 |
T-> |
Reject |
SOP |
DFP/Source/R3 |
3 |
0x07A4 |
|||
28 |
1.298.796.026 |
1.299.293.046 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
3 |
0x0641 |
|||
31 |
2.249.241.014 |
2.249.241.014 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||
33 |
2.249.276.055 |
2.249.276.055 |
T-> |
Rp_Asserted |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|
37 |
2.271.274.029 |
2.271.743.069 |
T-> |
Data_Reset |
SOP |
DFP/Source/R3 |
4 |
0x09AE |
|||
38 |
2.271.795.009 |
2.272.292.030 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
4 |
0x0841 |
|||
39 |
2.276.383.054 |
2.276.880.075 |
<-D |
Accept |
SOP |
UFP/Sink/R3 |
2 |
0x0483 |
|||
40 |
2.276.925.055 |
2.277.394.095 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
2 |
0x0521 |
|||
41 |
2.479.273.028 |
2.479.742.069 |
T-> |
Get_Sink_Cap |
SOP |
DFP/Source/R3 |
5 |
0x0BA8 |
|||
42 |
2.479.794.009 |
2.480.291.030 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
5 |
0x0A41 |
|||
43 |
2.490.806.075 |
2.490.806.075 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Attached_SRC -> FSM_State_Unattached_SRC |
0x0000 |
||
44 |
2.490.807.021 |
2.490.807.021 |
T-> |
Detach |
NONE |
NONE/NONE/- |
0 |
NONE |
0x0000 |
||
45 |
2.492.570.004 |
2.492.570.004 |
<-D |
NONE |
LOAD_CURRENT |
NONE |
NONE/NONE/R- |
0 |
LOAD_CURRENT:0A |
0x0000 |
|
46 |
3.483.952.042 |
3.483.952.042 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||
47 |
3.485.652.011 |
3.485.652.011 |
T-> |
Attach |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|
48 |
3.485.668.077 |
3.485.668.077 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC |
0x0000 |
||
49 |
3.635.751.032 |
3.635.751.032 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC |
0x0000 |
||
51 |
3.683.279.060 |
3.683.877.000 |
T-> |
SourceCap |
SOP |
DFP/Source/R3 |
0 |
 FS: 5V .1A; |
0x11A1 |
0x0A-0x90-0x01-0x28- |
|
52 |
3.683.935.000 |
3.684.432.021 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
0 |
0x0041 |
|||
53 |
3.688.533.045 |
3.689.163.026 |
<-D |
Request |
SOP |
UFP/Sink/R3 |
0 |
PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A |
0x1082 |
0x00-0x00-0x80-0x13- |
|
54 |
3.689.209.026 |
3.689.678.067 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
0 |
0x0121 |
|||
55 |
3.691.276.048 |
3.691.745.089 |
T-> |
Accept |
SOP |
DFP/Source/R3 |
1 |
0x03A3 |
|||
56 |
3.691.809.069 |
3.692.306.069 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
1 |
0x0241 |
|||
57 |
3.771.566.083 |
3.771.566.083 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Attached_SRC -> FSM_State_Disabled |
0x0000 |
||
58 |
3.771.567.033 |
3.771.567.033 |
T-> |
Detach |
NONE |
NONE/NONE/- |
0 |
NONE |
0x0000 |
||
59 |
3.773.572.054 |
3.773.572.054 |
<-D |
NONE |
LOAD_CURRENT |
NONE |
NONE/NONE/R- |
0 |
LOAD_CURRENT:0A |
0x0000 |
|
60 |
4.771.274.041 |
4.771.274.041 |
T-> |
Ra_Asserted |
NONE |
NONE/NONE/R- |
0 |
Ra_CC2 |
0x0000 |
||
65 |
4.771.748.041 |
4.771.748.041 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||
66 |
4.771.986.002 |
4.771.986.002 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Disabled -> FSM_State_Unattached_SRC |
0x0000 |
||
67 |
4.773.448.009 |
4.773.448.009 |
T-> |
Attach |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|
68 |
4.773.464.076 |
4.773.464.076 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Unattached_SRC -> FSM_State_AttachWait_SRC |
0x0000 |
||
69 |
4.923.547.031 |
4.923.547.031 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_AttachWait_SRC -> FSM_State_Attached_SRC |
0x0000 |
||
71 |
4.971.280.039 |
4.971.877.079 |
T-> |
SourceCap |
SOP |
DFP/Source/R3 |
0 |
 FS: 5V .1A; |
0x11A1 |
0x0A-0x90-0x01-0x28- |
|
72 |
4.971.935.079 |
4.972.433.000 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
0 |
0x0041 |
|||
73 |
4.976.531.064 |
4.977.161.045 |
<-D |
Request |
SOP |
UFP/Sink/R3 |
0 |
PDO#1 Fixed; OpCurrent = 0A; MaxCurrent = 0A |
0x1082 |
0x00-0x00-0x80-0x13- |
|
74 |
4.977.206.085 |
4.977.676.025 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
0 |
0x0121 |
|||
75 |
4.979.277.027 |
4.979.746.068 |
T-> |
Accept |
SOP |
DFP/Source/R3 |
1 |
0x03A3 |
|||
76 |
4.979.810.028 |
4.980.307.048 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
1 |
0x0241 |
|||
77 |
5.302.279.007 |
5.302.748.048 |
T-> |
PS_RDY |
SOP |
DFP/Source/R3 |
2 |
0x05A6 |
|||
78 |
5.302.812.008 |
5.303.309.028 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
2 |
0x0441 |
|||
80 |
5.303.346.031 |
5.303.346.031 |
T-> |
Rp_Asserted |
Rp_4_7k_3A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_4_7k_3A_Asserted |
0x0000 |
|
81 |
5.310.843.016 |
5.311.340.037 |
<-D |
PR_Swap |
SOP |
UFP/Sink/R3 |
1 |
0x028A |
|||
82 |
5.311.386.037 |
5.311.855.078 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
1 |
0x0321 |
|||
83 |
5.313.277.059 |
5.313.747.000 |
T-> |
Reject |
SOP |
DFP/Source/R3 |
3 |
0x07A4 |
|||
84 |
5.313.801.080 |
5.314.299.000 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
3 |
0x0641 |
|||
87 |
6.273.193.099 |
6.273.193.099 |
<-D |
Rd_Detected |
NONE |
NONE/NONE/R- |
0 |
Rd in CC1; |
0x0000 |
||
89 |
6.273.283.007 |
6.273.283.007 |
T-> |
Rp_Asserted |
Rp_12k_1_5A_Asserted |
NONE |
NONE/NONE/R- |
0 |
Rp_12k_1_5A_Asserted |
0x0000 |
|
93 |
6.295.281.053 |
6.295.750.094 |
T-> |
Data_Reset |
SOP |
DFP/Source/R3 |
4 |
0x09AE |
|||
94 |
6.295.802.034 |
6.296.299.055 |
<-D |
GoodCRC |
SOP |
UFP/Sink/R2 |
4 |
0x0841 |
|||
95 |
6.300.390.059 |
6.300.887.079 |
<-D |
Accept |
SOP |
UFP/Sink/R3 |
2 |
0x0483 |
|||
96 |
6.300.932.079 |
6.301.402.020 |
T-> |
GoodCRC |
SOP |
DFP/Source/R1 |
2 |
0x0521 |
|||
97 |
9.808.579.035 |
9.808.579.035 |
T-> |
FSM_State_Transition |
NONE |
NONE/NONE/R- |
0 |
FSM_State_Attached_SRC -> FSM_State_Disabled |
0x0000 |
||
98 |
9.808.579.084 |
9.808.579.084 |
T-> |
Detach |
NONE |
NONE/NONE/- |
0 |
NONE |
0x0000 |
||
99 |
9.811.584.098 |
9.811.584.098 |
<-D |
NONE |
LOAD_CURRENT |
NONE |
NONE/NONE/R- |
0 |
LOAD_CURRENT:0A |
0x0000 |
AMS Index |
AMS Name |
AMS Start |
AMS Stop |
AMS Status |
Child AMS Count |
---|
0 |
Power_Negotiation |
15 |
22 |
COMPLETE |
0 |
1 |
Power_Role_Swap |
25 |
28 |
COMPLETE |
0 |
2 |
Data_Reset |
37 |
40 |
PARTIAL_TESTER_PACKET_MISSING |
0 |
3 |
Get_Sink_Capabilities |
41 |
42 |
PARTIAL_DUT_PACKET_MISSING |
0 |
4 |
Power_Negotiation |
51 |
56 |
PARTIAL_TESTER_PACKET_MISSING |
0 |
5 |
Power_Negotiation |
71 |
78 |
COMPLETE |
0 |
6 |
Power_Role_Swap |
81 |
84 |
COMPLETE |
0 |
7 |
Data_Reset |
93 |
96 |
PARTIAL_TESTER_PACKET_MISSING |
0 |
Manufacturer |
Promise Technology, Inc. |
Model Number |
Pegasus R12 |
Serial Number |
1 |
Test Lab |
Test_Engineer |
Test_Engineer |
Remarks |
Remarks |
Date_and_Time |
2024/7/18 下午 05:37:11 |
Parameter |
Value |
---|
GRL_USB_PD_Controller_Serial_No |
GRL-C2-EPR-2021010 |
GRL_USB_PD_Software_Version |
1.6.24.0 |
GRL_USB_PD_Firmware_Version |
1.2.35 |
GRL USB-PD Ethernet Buffer Size |
62K |
GRL USB-PD Eload Firmware Version |
1.5 / 1.5 |
GRL USB-PD PPS Firmware Version |
4.0 / 4.0 |
Board Calibration |
Calibration Success |
RX mask Power selection |
Neutral Power |
Device_Type |
DRP |
Cable Type |
GRL_SPL_EPR_CABLE_1 |
Impedance (milli ohm) |
13 |
PD_Merged CTS Version |
v.Q2-2024 |
VIF_File_Name |
portA.xml |
Noise Pattern Generation: |
Two-Tone Noise |
Application mode |
Compliance |
Execution Time(In Minutes) |
44 |
Parameter |
Value |
---|
Connect EPR Test Fixture |
False |
FR_Swap AUTO Box Connected |
False |